Release 6.4 Public Patch #03 Open Group X Project Team To apply this patch: cd to the top of the source tree (to the directory containing the "xc" subdirectory) and do: patch -p -s < ThisFile Patch will work silently unless an error occurs. If you want to watch patch do its thing, leave out the "-s" argument to patch. Finally, to rebuild after applying this patch, cd to the "xc" subdirectory and do: make Everything >& every.log This patch updates the XFree86 ddxen (xfree86, xfree98, xfree68) to XFree86 3.3.2. ** NOTE ** NOTE ** NOTE ** NOTE ** NOTE ** NOTE ** NOTE ** NOTE ** NOTE ** This patch is freely redistributable. There are no license terms associated with the fixes in this patch file. Anyone may use this patch free of charge. ** NOTE ** NOTE ** NOTE ** NOTE ** NOTE ** NOTE ** NOTE ** NOTE ** NOTE ** ***************************************************************************** Prereq: R6.4, public-patch-2 *** bug-report@@/PUBLIC-LATEST Mon Jun 29 10:04:45 1998 --- xc/bug-report Tue Jun 30 16:01:13 1998 *************** *** 9,15 **** VERSION: ! R6.4, public-patch-2 [X Project Team public patches edit this line to indicate the patch level] CLIENT MACHINE and OPERATING SYSTEM: --- 9,15 ---- VERSION: ! R6.4, public-patch-3 [X Project Team public patches edit this line to indicate the patch level] CLIENT MACHINE and OPERATING SYSTEM: *** ./programs/Xserver/hw/xfree86/Imakefile@@/PUBLIC-LATEST Sat Jul 19 16:16:26 1997 --- xc/programs/Xserver/hw/xfree86/Imakefile Sat Mar 7 13:07:08 1998 *************** *** 1,9 **** ! XCOMM $TOG: Imakefile /main/14 1997/07/19 16:16:28 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree86/Imakefile,v 3.28 1996/12/23 06:30:29 dawes Exp $ #include #define IHaveSubdirs --- 1,9 ---- ! XCOMM $TOG: Imakefile /main/16 1998/03/07 13:08:49 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree86/Imakefile,v 3.28.2.1 1998/02/15 16:08:46 hohndel Exp $ #include #define IHaveSubdirs *************** *** 28,34 **** ACCELDIRS = accel #endif ! #if !defined(OsfArchitecture) && !defined(AmoebaArchitecture) SUPERPROBE = SuperProbe #endif --- 28,34 ---- ACCELDIRS = accel #endif ! #if !defined(OsfArchitecture) && !defined(AmoebaArchitecture) && !defined(ArcArchitecture) SUPERPROBE = SuperProbe #endif *** ./programs/Xserver/hw/xfree86/LinkKit/Imakefile.LK@@/PUBLIC-LATEST Sat Jul 19 09:16:31 1997 --- xc/programs/Xserver/hw/xfree86/LinkKit/Imakefile.LK Fri Mar 6 16:25:55 1998 *************** *** 1,9 **** ! XCOMM $TOG: Imakefile.LK /main/12 1997/07/19 09:16:33 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree86/LinkKit/Imakefile.LK,v 3.39.2.3 1997/05/12 12:52:17 hohndel Exp $ /* * Server Makefile for LinkKit */ --- 1,9 ---- ! XCOMM $TOG: Imakefile.LK /main/13 1998/03/06 16:27:33 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree86/LinkKit/Imakefile.LK,v 3.39.2.4 1998/02/15 16:08:49 hohndel Exp $ /* * Server Makefile for LinkKit */ *************** *** 654,659 **** --- 654,701 ---- #endif /* XF98TGUIServer */ + #if XF98MGAServer + XCOMM + XCOMM XFree98 Matrox Millennium/Mystique Server + XCOMM + INCLUDES = -Iinclude -Iinclude/X11 -Idrivers98 + DDXDIR1 = $(XF98VGADRIVERSRC) + XF98MGAUBDIRS = $(XF98VGADRIVERSRC) + XF98MGAOBJS = XF86_SVGA.o mgaConf.o $(XAAOBJS) + XF98MGALIBS = $(XF98VGADRIVERSRC)/LibraryTargetName(drivermga) $(XAALIBS) \ + $(XF98DRIVERSRC)/LibraryTargetName(mga) $(XF98LIBS) CFBLibs + XF98MGASYSLIBS = $(SYSLIBS) + XF98VGADRIVERS = XF98SvgaDrivers + ConfigTargetNoDepend(mgaConf,$(ICONFIGFILES),cmga.sh,mga) + XF86_SVGA.o: XF86_SVGA.c $(ICONFIGFILES) + SetUIDServerTarget(XF98_MGA,$(XF98MGAUBDIRS),$(XF98MGAOBJS),$(XF98MGALIBS),$(XF98MGASYSLIBS)) + #ifndef ServerToInstall + #define ServerToInstall XF98_MGA + #endif + #endif /* XF98MGAServer */ + + + #if XF98SVGAServer + XCOMM + XCOMM XFree98 Cirrus Logic CLGD7555 Server + XCOMM + INCLUDES = -Iinclude -Iinclude/X11 -Idrivers98 + DDXDIR1 = $(XF98VGADRIVERSRC) + XF98SVGAUBDIRS = $(XF98VGADRIVERSRC) + XF98SVGAOBJS = XF86_SVGA.o vga256Conf.o $(XAAOBJS) + XF98SVGALIBS = $(XF98VGADRIVERSRC)/LibraryTargetName(driversvga) $(XAALIBS) \ + $(XF98DRIVERSRC)/LibraryTargetName(vga256) $(XF98LIBS) CFBLibs + XF98SVGASYSLIBS = $(SYSLIBS) + XF98VGADRIVERS = XF98SvgaDrivers + ConfigTargetNoDepend(vga256Conf,$(ICONFIGFILES),cvga256.sh,cirrus) + XF86_SVGA.o: XF86_SVGA.c $(ICONFIGFILES) + SetUIDServerTarget(XF98_SVGA,$(XF98SVGAUBDIRS),$(XF98SVGAOBJS),$(XF98SVGALIBS),$(XF98SVGASYSLIBS)) + #ifndef ServerToInstall + #define ServerToInstall XF98_SVGA + #endif + #endif /* XF98SVGAServer */ + + #if XF98EGCServer XCOMM XCOMM XFree98 EGC Server *************** *** 886,892 **** #endif /* Only these servers have subdirs */ ! #if XF86SVGAServer || XF86MonoServer || XF86VGA16Server || XF86S3Server || XF98GANBWAPServer || XF98NEC480Server || XF98NKVNECServer || XF98WABSServer || XF98WABEPServer || XF98WSNAServer || XF98TGUIServer || XF98NECS3Server || XF98PWSKBServer || XF98PWLBServer || XF98GA968Server #define IHaveSubdirs --- 928,938 ---- #endif /* Only these servers have subdirs */ ! #if XF86SVGAServer || XF86MonoServer || XF86VGA16Server || XF86S3Server || \ ! XF98GANBWAPServer || XF98NEC480Server || XF98NKVNECServer || \ ! XF98WABSServer || XF98WABEPServer || XF98WSNAServer || XF98TGUIServer || \ ! XF98MGAServer || XF98SVGAServer || XF98NECS3Server || XF98PWSKBServer || \ ! XF98PWLBServer || XF98GA968Server #define IHaveSubdirs *** ./programs/Xserver/hw/xfree86/LinkKit/README@@/PUBLIC-LATEST Sat Jul 19 09:16:37 1997 --- xc/programs/Xserver/hw/xfree86/LinkKit/README Mon Mar 9 12:57:28 1998 *************** *** 7,26 **** ! Readme for the XFree86 3.3 LinkKit The XFree86 Project, Inc. ! 16 May 1997 ! 1. Readme for the XFree86 3.3 LinkKit 1. For systems which don't use gcc-2, you may need to install libgcc.a if the binary distribution you are using was built with gcc-2. ! 2. Make sure that you have the XFree86 3.3 libraries installed under /usr/X11R6 if you will be linking Xnest with the LinkKit. The LinkKit is now self-contained for the other servers. --- 7,26 ---- ! Readme for the XFree86 3.3.2 LinkKit The XFree86 Project, Inc. ! 26 February 1998 ! 1. Readme for the XFree86 3.3.2 LinkKit 1. For systems which don't use gcc-2, you may need to install libgcc.a if the binary distribution you are using was built with gcc-2. ! 2. Make sure that you have the XFree86 3.3.2 libraries installed under /usr/X11R6 if you will be linking Xnest with the LinkKit. The LinkKit is now self-contained for the other servers. *************** *** 61,73 **** ! Readme for the XFree86 3.3 LinkKit ! Readme for the XFree86 3.3 LinkKit --- 61,73 ---- ! Readme for the XFree86 3.3.2 LinkKit ! Readme for the XFree86 3.3.2 LinkKit *************** *** 89,94 **** --- 89,100 ---- o To build the Trident Cyber9320/9680 server: set XF98TGUIServer to YES. + o To build the Matrox Millennium/Mystique Server: set XF98MGAServer to + YES. + + o To build the Cirrus Logic CLGD7555 Server: set XF98SVGAServer to + YES. + o To build the EGC server: set XF98EGCServer to YES. o To build the NEC S3 server: set XF98NECS3Server to YES. *************** *** 118,130 **** include in the mono or VGA16 servers (when building dual-headed servers). - o Note: the ordering of drivers determines the order in which the - probing is done. The `generic' driver should be the last one - included in the Mono and VGA16 and SVGA servers because its probe - always succeeds. - o To use dynamically loadable modules(e.g. PEX, XIE): set Extensions- - DynamicModules to YES. --- 124,130 ---- *************** *** 133,142 **** ! Readme for the XFree86 3.3 LinkKit o To include the PEX extension: set BuildPexExt to YES. o To include the X Image Extension: set BuildXIE to YES. --- 133,150 ---- ! Readme for the XFree86 3.3.2 LinkKit + o Note: the ordering of drivers determines the order in which the + probing is done. The `generic' driver should be the last one + included in the Mono and VGA16 and SVGA servers because its probe + always succeeds. + + o To use dynamically loadable modules(e.g. PEX, XIE): set Extensions- + DynamicModules to YES. + o To include the PEX extension: set BuildPexExt to YES. o To include the X Image Extension: set BuildXIE to YES. *************** *** 184,207 **** ning it with the `-showconfig' flag. To check which extensions are included, start the Xserver and run `xdpyinfo'. - Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/LinkKit.sgml,v 3.14.2.1 1997/05/17 12:03:29 dawes Exp $ - $TOG: README /main/10 1997/07/19 09:16:38 kaleb $ - Readme for the XFree86 3.3 LinkKit --- 192,215 ---- ning it with the `-showconfig' flag. To check which extensions are included, start the Xserver and run `xdpyinfo'. + Readme for the XFree86 3.3.2 LinkKit + Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/LinkKit.sgml,v 3.14.2.3 1998/02/26 20:11:26 hohndel Exp $ + $TOG: README /main/12 1998/03/09 12:59:16 kaleb $ *************** *** 257,262 **** --- 265,271 ---- + Readme for the XFree86 3.3.2 LinkKit *************** *** 269,279 **** CONTENTS ! 1. Readme for the XFree86 3.3 LinkKit ...................................... 1 --- 278,345 ---- + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CONTENTS ! 1. Readme for the XFree86 3.3.2 LinkKit .................................... 1 *************** *** 329,332 **** ! $XFree86: xc/programs/Xserver/hw/xfree86/LinkKit/README,v 3.21.2.1 1997/05/17 12:25:09 dawes Exp $ --- 395,398 ---- ! $XFree86: xc/programs/Xserver/hw/xfree86/LinkKit/README,v 3.21.2.3 1998/02/27 02:54:54 dawes Exp $ *** ./programs/Xserver/hw/xfree86/LinkKit/site.def.LK@@/PUBLIC-LATEST Sat Jul 19 09:16:47 1997 --- xc/programs/Xserver/hw/xfree86/LinkKit/site.def.LK Fri Mar 6 16:26:05 1998 *************** *** 1,10 **** ! XCOMM $TOG: site.def.LK /main/13 1997/07/19 09:16:48 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree86/LinkKit/site.def.LK,v 3.25.2.3 1997/05/17 12:25:09 dawes Exp $ /* Configuration file for Server Link Kit */ --- 1,10 ---- ! XCOMM $TOG: site.def.LK /main/14 1998/03/06 16:27:43 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree86/LinkKit/site.def.LK,v 3.25.2.6 1998/02/26 13:58:57 dawes Exp $ /* Configuration file for Server Link Kit */ *************** *** 146,151 **** --- 146,153 ---- #define XF98WABEPServer YES #define XF98WSNAServer YES #define XF98TGUIServer YES + #define XF98MGAServer YES + #define XF98SVGAServer YES #define XF98NECS3Server YES #define XF98PWSKBServer YES #define XF98PWLBServer YES *************** *** 162,175 **** */ #define XF86SvgaDrivers nv et4000 et3000 pvga1 gvga ati sis tvga8900 \ ! cirrus ncr77c22 mga oak al2101 ali cl64xx \ ! video7 chips ark mx realtek apm generic ! #define XF86Vga16Drivers /*et4000*/ et3000 ncr77c22 ati sis tvga8900 oak \ cl64xx generic ! #define XF86Vga2Drivers /*et4000*/ et3000 pvga1 gvga ati sis tvga8900 \ ! /*cirrus*/ ncr77c22 oak cl64xx generic #define XF86MonoDrivers hgc1280 sigma apollo hercules --- 164,178 ---- */ #define XF86SvgaDrivers nv et4000 et3000 pvga1 gvga ati sis tvga8900 \ ! cirrus ncr77c22 compaq mga oak al2101 \ ! ali cl64xx video7 ark mx realtek apm \ ! s3v s3_svga chips generic ! #define XF86Vga16Drivers et4000 et3000 ncr77c22 ati sis tvga8900 oak \ cl64xx generic ! #define XF86Vga2Drivers et4000 et3000 pvga1 gvga ati sis tvga8900 \ ! cirrus ncr77c22 oak cl64xx generic #define XF86MonoDrivers hgc1280 sigma apollo hercules *** ./programs/Xserver/hw/xfree86/SuperProbe/Imakefile@@/PUBLIC-LATEST Sat Jul 19 09:19:03 1997 --- xc/programs/Xserver/hw/xfree86/SuperProbe/Imakefile Fri Mar 6 16:26:09 1998 *************** *** 1,10 **** ! XCOMM $TOG: Imakefile /main/15 1997/07/19 09:19:05 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree86/SuperProbe/Imakefile,v 3.23.2.2 1997/05/06 13:24:03 dawes Exp $ #if defined(SVR3Architecture) || defined(SVR4Architecture) || defined(SCOArchitecture) # define OSModule OS_SYSV --- 1,10 ---- ! XCOMM $TOG: Imakefile /main/16 1998/03/06 16:27:47 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree86/SuperProbe/Imakefile,v 3.23.2.3 1998/02/15 23:31:53 robin Exp $ #if defined(SVR3Architecture) || defined(SVR4Architecture) || defined(SCOArchitecture) # define OSModule OS_SYSV *************** *** 54,64 **** SVGA_SRC = Tseng.c WD.c ChipsTech.c Video7.c Genoa.c Trident.c Oak.c \ Cirrus.c Ahead.c ATI.c S3.c AL.c Yamaha.c NCR.c MX.c \ RealTek.c Primus.c Compaq.c HMC.c UMC.c Weitek.c SiS.c \ ! ARK.c Alliance.c Matrox.c SigmaDesigns.c SVGA_OBJ = Tseng.o WD.o ChipsTech.o Video7.o Genoa.o Trident.o Oak.o \ Cirrus.o Ahead.o ATI.o S3.o AL.o Yamaha.o NCR.o MX.o \ RealTek.o Primus.o Compaq.o HMC.o UMC.o Weitek.o SiS.o \ ! ARK.o Alliance.o Matrox.o SigmaDesigns.o COPROC_SRC = 8514.c ATIMach.c I128.c GLINT.c COPROC_OBJ = 8514.o ATIMach.o I128.o GLINT.o SRCS = Main.c $(SVGA_SRC) $(COPROC_SRC) $(BASE_SRC) Print.c Utils.c $(OS_SRC) --- 54,64 ---- SVGA_SRC = Tseng.c WD.c ChipsTech.c Video7.c Genoa.c Trident.c Oak.c \ Cirrus.c Ahead.c ATI.c S3.c AL.c Yamaha.c NCR.c MX.c \ RealTek.c Primus.c Compaq.c HMC.c UMC.c Weitek.c SiS.c \ ! ARK.c Alliance.c Matrox.c SigmaDesigns.c Intergraphics.c SVGA_OBJ = Tseng.o WD.o ChipsTech.o Video7.o Genoa.o Trident.o Oak.o \ Cirrus.o Ahead.o ATI.o S3.o AL.o Yamaha.o NCR.o MX.o \ RealTek.o Primus.o Compaq.o HMC.o UMC.o Weitek.o SiS.o \ ! ARK.o Alliance.o Matrox.o SigmaDesigns.o Intergraphics.o COPROC_SRC = 8514.c ATIMach.c I128.c GLINT.c COPROC_OBJ = 8514.o ATIMach.o I128.o GLINT.o SRCS = Main.c $(SVGA_SRC) $(COPROC_SRC) $(BASE_SRC) Print.c Utils.c $(OS_SRC) *** /dev/null Tue Jun 30 11:42:54 1998 --- xc/programs/Xserver/hw/xfree86/SuperProbe/Intergraphics.c Fri Mar 6 16:26:14 1998 *************** *** 0 **** --- 1,84 ---- + /* $TOG: Intergraphics.c /main/1 1998/03/06 16:27:52 kaleb $ */ + /* + * (c) Copyright 1997 Harald Koenig + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * JOSEPH MOSS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of Joseph Moss shall not be + * used in advertising or otherwise to promote the sale, use or other dealings + * in this Software without prior written authorization from Joseph Moss. + * + */ + + /* $XFree86: xc/programs/Xserver/hw/xfree86/SuperProbe/Intergraphics.c,v 1.1.2.1 1998/02/16 14:38:51 robin Exp $ */ + + #include "Probe.h" + + static Word Ports[] = {0x000, }; + #define NUMPORTS (sizeof(Ports)/sizeof(Word)) + + static int MemProbe_Intergraphics __STDCARGS((int)); + + Chip_Descriptor Intergraphics_Descriptor = { + "Intergraphics", + Probe_Intergraphics, + Ports, + NUMPORTS, + FALSE, + FALSE, + TRUE, + NULL, + }; + + Bool Probe_Intergraphics(Chipset) + int *Chipset; + { + Bool result = FALSE; + Byte chip, old, old1, val; + int i = 0; + + if (!NoPCI) + { + while ((pcrp = pci_devp[i]) != (struct pci_config_reg *)NULL) { + if (pcrp->_vendor == PCI_VENDOR_INTERGRAPHICS) + { + switch (pcrp->_device) + { + case PCI_CHIP_INTERG_1680: + *Chipset = CHIP_IG_1680; + break; + case PCI_CHIP_INTERG_1682: + *Chipset = CHIP_IG_1682; + break; + default: + Chip_data = chip; + *Chipset = CHIP_IG_UNK; + break; + } + PCIProbed = TRUE; + return(TRUE); + } + i++; + } + } + + return(FALSE); + } + + *** ./programs/Xserver/hw/xfree86/SuperProbe/Main.c@@/PUBLIC-LATEST Sun Aug 10 12:56:19 1997 --- xc/programs/Xserver/hw/xfree86/SuperProbe/Main.c Fri Mar 6 16:26:18 1998 *************** *** 1,4 **** ! /* $TOG: Main.c /main/13 1997/08/10 12:54:55 kaleb $ */ /* * (c) Copyright 1993,1994 by David Wexelblat * --- 1,4 ---- ! /* $TOG: Main.c /main/14 1998/03/06 16:27:55 kaleb $ */ /* * (c) Copyright 1993,1994 by David Wexelblat * *************** *** 26,32 **** * */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/SuperProbe/Main.c,v 3.17.2.5 1997/07/07 04:10:59 dawes Exp $ */ #include "Probe.h" #include "PatchLevel.h" --- 26,32 ---- * */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/SuperProbe/Main.c,v 3.17.2.6 1998/02/15 23:31:54 robin Exp $ */ #include "Probe.h" #include "PatchLevel.h" *************** *** 77,82 **** --- 77,83 ---- &ARK_Descriptor, &Alliance_Descriptor, &SigmaDesigns_Descriptor, + &Intergraphics_Descriptor, &CT_Descriptor, /* I think this is screwing people up, so put it last */ NULL }; *** ./programs/Xserver/hw/xfree86/SuperProbe/OS_SYSV.c@@/PUBLIC-LATEST Sat Jul 19 09:19:59 1997 --- xc/programs/Xserver/hw/xfree86/SuperProbe/OS_SYSV.c Mon Mar 23 15:30:07 1998 *************** *** 25,31 **** * in this Software without prior written authorization from David Wexelblat. * */ ! /* $TOG: OS_SYSV.c /main/14 1997/07/19 09:20:00 kaleb $ */ #if defined(sun) /* Fix for Solaris */ --- 25,31 ---- * in this Software without prior written authorization from David Wexelblat. * */ ! /* $TOG: OS_SYSV.c /main/15 1998/03/23 15:42:38 mgreess $ */ #if defined(sun) /* Fix for Solaris */ *************** *** 86,98 **** #ifdef __STDC__ int sysi86(int, ...); int syscall(int, ...); ! #ifndef SCO int munmap(caddr_t, size_t); #endif #else int sysi86(); int syscall(); ! #ifndef SCO int munmap(); #endif #endif --- 86,98 ---- #ifdef __STDC__ int sysi86(int, ...); int syscall(int, ...); ! #if !(defined(SCO) || defined(USL)) int munmap(caddr_t, size_t); #endif #else int sysi86(); int syscall(); ! #if !(defined(SCO) || defined(USL)) int munmap(); #endif #endif *** ./programs/Xserver/hw/xfree86/SuperProbe/PCI.h@@/PUBLIC-LATEST Sun Aug 10 12:56:30 1997 --- xc/programs/Xserver/hw/xfree86/SuperProbe/PCI.h Fri Mar 6 16:26:22 1998 *************** *** 227,232 **** --- 227,233 ---- #define PCI_VENDOR_S3 0x5333 #define PCI_VENDOR_ARK 0xEDD8 #define PCI_VENDOR_3DLABS 0x3D3D + #define PCI_VENDOR_INTERGRAPHICS 0x10ea /* Matrox */ #define PCI_CHIP_MGA2085PX 0x0518 *************** *** 315,320 **** --- 316,323 ---- #define PCI_CHIP_ViRGE 0x5631 #define PCI_CHIP_ViRGE_VX 0x883D #define PCI_CHIP_ViRGE_DXGX 0x8A01 + #define PCI_CHIP_ViRGE_GX2 0x8A10 + #define PCI_CHIP_ViRGE_MX 0x8C01 /* ARK Logic */ #define PCI_CHIP_1000PV 0xA091 *************** *** 328,334 **** #define PCI_CHIP_3DLABS_DELTA 0x0003 #define PCI_CHIP_3DLABS_PERMEDIA 0x0004 /* Increase this as required */ ! #define MAX_DEV_PER_VENDOR 16 #endif /* _PCI_H */ --- 331,342 ---- #define PCI_CHIP_3DLABS_DELTA 0x0003 #define PCI_CHIP_3DLABS_PERMEDIA 0x0004 + /* Intergraphics */ + #define PCI_CHIP_INTERG_1680 0x1680 + #define PCI_CHIP_INTERG_1682 0x1682 + + /* Increase this as required */ ! #define MAX_DEV_PER_VENDOR 18 #endif /* _PCI_H */ *** ./programs/Xserver/hw/xfree86/SuperProbe/PatchLevel.h@@/PUBLIC-LATEST Sun Aug 10 12:56:35 1997 --- xc/programs/Xserver/hw/xfree86/SuperProbe/PatchLevel.h Fri Mar 6 16:26:27 1998 *************** *** 1,4 **** ! /* $TOG: PatchLevel.h /main/17 1997/08/10 12:55:11 kaleb $ */ /* * (c) Copyright 1993,1994 by David Wexelblat * --- 1,4 ---- ! /* $TOG: PatchLevel.h /main/18 1998/03/06 16:28:04 kaleb $ */ /* * (c) Copyright 1993,1994 by David Wexelblat * *************** *** 26,35 **** * */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/SuperProbe/PatchLevel.h,v 3.20.2.3 1997/08/04 02:59:10 dawes Exp $ */ #define VERSION 2 ! #define PATCHLEV 15 ! #define RELDATE "4 August 1997" #define PRINT_VERSION printf("\n%s Version %d.%d (%s)\n", \ MyName,VERSION,PATCHLEV,RELDATE) --- 26,35 ---- * */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/SuperProbe/PatchLevel.h,v 3.20.2.4 1998/02/24 19:05:52 hohndel Exp $ */ #define VERSION 2 ! #define PATCHLEV 16 ! #define RELDATE "24 February 1998" #define PRINT_VERSION printf("\n%s Version %d.%d (%s)\n", \ MyName,VERSION,PATCHLEV,RELDATE) *** ./programs/Xserver/hw/xfree86/SuperProbe/Print.c@@/PUBLIC-LATEST Sun Aug 10 12:56:40 1997 --- xc/programs/Xserver/hw/xfree86/SuperProbe/Print.c Fri Mar 6 16:26:31 1998 *************** *** 1,4 **** ! /* $TOG: Print.c /main/27 1997/08/10 12:55:16 kaleb $ */ /* * (c) Copyright 1993,1994 by David Wexelblat * --- 1,4 ---- ! /* $TOG: Print.c /main/28 1998/03/06 16:28:09 kaleb $ */ /* * (c) Copyright 1993,1994 by David Wexelblat * *************** *** 26,32 **** * */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/SuperProbe/Print.c,v 3.46.2.7 1997/08/02 13:48:09 dawes Exp $ */ #include "Probe.h" --- 26,32 ---- * */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/SuperProbe/Print.c,v 3.46.2.9 1998/02/15 23:31:55 robin Exp $ */ #include "Probe.h" *************** *** 131,136 **** --- 131,138 ---- "S3 ViRGE/DX", "S3 ViRGE/GX", "S3 PLATO/PX", + "S3 ViRGE/GX2", + "S3 ViRGE/MX", }, /* Trident */ { "Trident (chipset unknown)", "Trident LX8200", *************** *** 194,199 **** --- 196,204 ---- "Matrox Millennium II" }, /* Sigma Designs */ { "Sigma Designs (chipset unknown)", "Sigma Designs REALmagic64/GX (SD 6425)" }, + /* Intergraphcis */ { "Intergraphics (chipset unknown)", + "Intergraphics IGA-1680", + "Intergraphics IGA-1682" }, }; static CONST char *Herc_Names[] = *** ./programs/Xserver/hw/xfree86/SuperProbe/Probe.h@@/PUBLIC-LATEST Sun Aug 10 12:56:45 1997 --- xc/programs/Xserver/hw/xfree86/SuperProbe/Probe.h Fri Mar 6 16:26:36 1998 *************** *** 1,4 **** ! /* $TOG: Probe.h /main/29 1997/08/10 12:55:21 kaleb $ */ /* * (c) Copyright 1993,1994 by David Wexelblat * --- 1,4 ---- ! /* $TOG: Probe.h /main/30 1998/03/06 16:28:13 kaleb $ */ /* * (c) Copyright 1993,1994 by David Wexelblat * *************** *** 26,32 **** * */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/SuperProbe/Probe.h,v 3.45.2.7 1997/08/02 13:48:09 dawes Exp $ */ /* * Includes --- 26,32 ---- * */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/SuperProbe/Probe.h,v 3.45.2.9 1998/02/15 23:31:55 robin Exp $ */ /* * Includes *************** *** 190,195 **** --- 190,196 ---- Bool Probe_Weitek __STDCARGS((int *)); Bool Probe_ARK __STDCARGS((int *)); Bool Probe_SigmaDesigns __STDCARGS((int *)); + Bool Probe_Intergraphics __STDCARGS((int *)); /* CoProc */ Bool Probe_8514 __STDCARGS((int *)); Bool Probe_ATIMach __STDCARGS((int *)); *************** *** 247,252 **** --- 248,254 ---- extern Chip_Descriptor Yamaha_Descriptor; extern Chip_Descriptor ARK_Descriptor; extern Chip_Descriptor SigmaDesigns_Descriptor; + extern Chip_Descriptor Intergraphics_Descriptor; extern Chip_Descriptor IBM8514_Descriptor; extern Chip_Descriptor ATIMach_Descriptor; *************** *** 411,419 **** #define V_ALLIANCE 24 #define V_MATROX 25 #define V_SD 26 ! #define NUM_VENDORS 26 ! #define CHPS_PER_VENDOR 34 #define CHIP_AHEAD_UNK SVGA_TYPE(V_AHEAD,0) /* Ahead unknown */ #define CHIP_AHEAD_A SVGA_TYPE(V_AHEAD,1) /* Ahead V5000 Version A*/ --- 413,422 ---- #define V_ALLIANCE 24 #define V_MATROX 25 #define V_SD 26 + #define V_IG 27 ! #define NUM_VENDORS 27 ! #define CHPS_PER_VENDOR 35 #define CHIP_AHEAD_UNK SVGA_TYPE(V_AHEAD,0) /* Ahead unknown */ #define CHIP_AHEAD_A SVGA_TYPE(V_AHEAD,1) /* Ahead V5000 Version A*/ *************** *** 571,576 **** --- 574,581 ---- #define CHIP_S3_ViRGE_DX SVGA_TYPE(V_S3,30) /* S3 ViRGE/DX */ #define CHIP_S3_ViRGE_GX SVGA_TYPE(V_S3,31) /* S3 ViRGE/GX */ #define CHIP_S3_PLATO_PX SVGA_TYPE(V_S3,32) /* S3 PLATO/PX */ + #define CHIP_S3_ViRGE_GX2 SVGA_TYPE(V_S3,33) /* S3 ViRGE/GX2 */ + #define CHIP_S3_ViRGE_MX SVGA_TYPE(V_S3,34) /* S3 ViRGE/MX */ #define CHIP_TVGA_UNK SVGA_TYPE(V_TRIDENT,0) /* Trident unknown */ #define CHIP_TVGA8200 SVGA_TYPE(V_TRIDENT,1) /* Trident LX8200 */ #define CHIP_TVGA8800BR SVGA_TYPE(V_TRIDENT,2) /* Trident 8800BR */ *************** *** 650,655 **** --- 655,663 ---- #define CHIP_YAMAHA6388 SVGA_TYPE(V_YAMAHA,0) /* Yamaha 6388 VPDC */ #define CHIP_SD_RM_UNK SVGA_TYPE(V_SD,0) /* Sigma Desigs unknown */ #define CHIP_SD_RM64GX SVGA_TYPE(V_SD,1) /* Sigma Desigs SD6425 */ + #define CHIP_IG_UNK SVGA_TYPE(V_IG,0) /* Intergraphics unknown */ + #define CHIP_IG_1680 SVGA_TYPE(V_IG,1) /* Intergraphics IGA-1680 */ + #define CHIP_IG_1682 SVGA_TYPE(V_IG,2) /* Intergraphics IGA-1682 */ /* * Graphics Coprocessors *** ./programs/Xserver/hw/xfree86/SuperProbe/S3.c@@/PUBLIC-LATEST Sat Jul 19 09:20:40 1997 --- xc/programs/Xserver/hw/xfree86/SuperProbe/S3.c Fri Mar 6 16:26:41 1998 *************** *** 1,4 **** ! /* $XFree86: xc/programs/Xserver/hw/xfree86/SuperProbe/S3.c,v 3.15.2.1 1997/05/06 13:24:45 dawes Exp $ */ /* * (c) Copyright 1993,1994 by David Wexelblat * --- 1,4 ---- ! /* $XFree86: xc/programs/Xserver/hw/xfree86/SuperProbe/S3.c,v 3.15.2.3 1998/02/15 23:31:56 robin Exp $ */ /* * (c) Copyright 1993,1994 by David Wexelblat * *************** *** 26,32 **** * */ ! /* $TOG: S3.c /main/13 1997/07/19 09:20:41 kaleb $ */ #include "Probe.h" --- 26,32 ---- * */ ! /* $TOG: S3.c /main/14 1998/03/06 16:28:18 kaleb $ */ #include "Probe.h" *************** *** 135,140 **** --- 135,148 ---- else *Chipset = CHIP_S3_ViRGE_DX; break; + case PCI_CHIP_ViRGE_GX2: + PCIProbed = TRUE; + *Chipset = CHIP_S3_ViRGE_GX2; + break; + case PCI_CHIP_ViRGE_MX: + PCIProbed = TRUE; + *Chipset = CHIP_S3_ViRGE_MX; + break; case PCI_CHIP_ViRGE_VX: PCIProbed = TRUE; *Chipset = CHIP_S3_ViRGE_VX; *************** *** 315,354 **** chip_id = rdinx(CRTC_IDX, 0x2d) << 8; chip_id |= rdinx(CRTC_IDX, 0x2e); chip_rev = rdinx(CRTC_IDX, 0x2f); ! if (chip_id == 0x8880) *Chipset = CHIP_S3_866; ! else if (chip_id == 0x8890) *Chipset = CHIP_S3_868; ! else if (chip_id == 0x8810) *Chipset = CHIP_S3_Trio32; ! else if (chip_id == PCI_CHIP_TRIO) if ((chip_rev&0x40) == 0x40) *Chipset = CHIP_S3_Trio64V; else *Chipset = CHIP_S3_Trio64; ! else if (chip_id == PCI_CHIP_968) ! *Chipset = CHIP_S3_968; ! else if (chip_id == PCI_CHIP_ViRGE) ! *Chipset = CHIP_S3_ViRGE; ! else if (chip_id == PCI_CHIP_ViRGE_VX) ! *Chipset = CHIP_S3_ViRGE_VX; ! else if (chip_id == PCI_CHIP_PLATO_PX) ! *Chipset = CHIP_S3_PLATO_PX; ! else if (chip_id == PCI_CHIP_TRIO64V2_DXGX) if (rdinx(CRTC_IDX, 0x6f) & 1) *Chipset = CHIP_S3_Trio64V2_GX; else *Chipset = CHIP_S3_Trio64V2_DX; ! else if (chip_id == 0x8a01) if (rdinx(CRTC_IDX, 0x6f) & 1) *Chipset = CHIP_S3_ViRGE_GX; else *Chipset = CHIP_S3_ViRGE_DX; ! else { ! Chip_data = rev; ! Chip_data = (Chip_data << 16) | chip_id; ! Chip_data = (Chip_data << 8) | chip_rev; ! *Chipset = CHIP_S3_UNKNOWN; } break; } --- 323,371 ---- chip_id = rdinx(CRTC_IDX, 0x2d) << 8; chip_id |= rdinx(CRTC_IDX, 0x2e); chip_rev = rdinx(CRTC_IDX, 0x2f); ! switch (chip_id) { ! case 0x8880: *Chipset = CHIP_S3_866; ! break; ! case 0x8890: *Chipset = CHIP_S3_868; ! break; ! case 0x8810: *Chipset = CHIP_S3_Trio32; ! break; ! case PCI_CHIP_TRIO: if ((chip_rev&0x40) == 0x40) *Chipset = CHIP_S3_Trio64V; else *Chipset = CHIP_S3_Trio64; ! break; ! case PCI_CHIP_TRIO64V2_DXGX: if (rdinx(CRTC_IDX, 0x6f) & 1) *Chipset = CHIP_S3_Trio64V2_GX; else *Chipset = CHIP_S3_Trio64V2_DX; ! break; ! case PCI_CHIP_ViRGE_DXGX: if (rdinx(CRTC_IDX, 0x6f) & 1) *Chipset = CHIP_S3_ViRGE_GX; else *Chipset = CHIP_S3_ViRGE_DX; ! break; ! ! case PCI_CHIP_968: ! case PCI_CHIP_AURORA64VP: ! case PCI_CHIP_ViRGE: ! case PCI_CHIP_ViRGE_VX: ! case PCI_CHIP_PLATO_PX: ! case PCI_CHIP_ViRGE_GX2: ! case PCI_CHIP_ViRGE_MX: ! *Chipset = chip_id; ! break; ! default: ! Chip_data = rev; ! Chip_data = (Chip_data << 16) | chip_id; ! Chip_data = (Chip_data << 8) | chip_rev; ! *Chipset = CHIP_S3_UNKNOWN; } break; } *************** *** 402,407 **** --- 419,437 ---- break; case 6: Mem = 1 * 1024; + break; + } + } + else if (Chipset == CHIP_S3_ViRGE_GX2 || + Chipset == CHIP_S3_ViRGE_MX) + { + switch((config & 0xC0) >> 6) + { + case 1: + Mem = 4 * 1024; + break; + case 3: + Mem = 2 * 1024; break; } } *** ./programs/Xserver/hw/xfree86/SuperProbe/SuperProbe.man@@/PUBLIC-LATEST Tue Nov 4 21:17:24 1997 --- xc/programs/Xserver/hw/xfree86/SuperProbe/SuperProbe.man Fri Mar 6 16:26:45 1998 *************** *** 1,5 **** .\" $XFree86: xc/programs/Xserver/hw/xfree86/SuperProbe/SuperProbe.man,v 3.4 1996/12/23 06:31:38 dawes Exp $ ! .TH SuperProbe 1 "Release 6.4 (XFree86 3.3.1/SuperProbe 2.15)" "X Version 11" .SH NAME SuperProbe - probe for and identify installed video hardware. .SH SYNOPSIS --- 1,5 ---- .\" $XFree86: xc/programs/Xserver/hw/xfree86/SuperProbe/SuperProbe.man,v 3.4 1996/12/23 06:31:38 dawes Exp $ ! .TH SuperProbe 1 "Release 6.3 (XFree86 3.2/SuperProbe 2.12)" "X Version 11" .SH NAME SuperProbe - probe for and identify installed video hardware. .SH SYNOPSIS *************** *** 204,207 **** .br with help from David Dawes and the XFree86 development team. ! .\" $TOG: SuperProbe.man /main/8 1997/11/04 21:20:19 kaleb $ --- 204,207 ---- .br with help from David Dawes and the XFree86 development team. ! .\" $TOG: SuperProbe.man /main/9 1998/03/06 16:28:23 kaleb $ *** ./programs/Xserver/hw/xfree86/VGADriverDoc/VGADriver.Doc@@/PUBLIC-LATEST Sat Jul 19 09:21:40 1997 --- xc/programs/Xserver/hw/xfree86/VGADriverDoc/VGADriver.Doc Fri Mar 6 16:26:49 1998 *************** *** 1095,1101 **** 12. Vendor Contact Information ! ATI Technologies (VGA-Wonder, Mach8, Mach32) 33 Commerce Valley Drive East" Thornhill, Ontario Canada L3T 7N6 --- 1095,1101 ---- 12. Vendor Contact Information ! ATI Technologies (VGA-Wonder, Mach8, Mach32, Mach64) 33 Commerce Valley Drive East" Thornhill, Ontario Canada L3T 7N6 *************** *** 1196,1208 **** Western Digital (714) 932-4900 ! Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/VGADriv.sgml,v 3.13 1997/01/25 03:22:16 dawes Exp $ ! $TOG: VGADriver.Doc /main/9 1997/07/19 09:21:41 kaleb $ --- 1196,1208 ---- Western Digital (714) 932-4900 ! Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/VGADriv.sgml,v 3.13.2.1 1998/02/01 16:04:54 robin Exp $ ! $TOG: VGADriver.Doc /main/10 1998/03/06 16:28:27 kaleb $ *************** *** 1385,1388 **** ! $XFree86: xc/programs/Xserver/hw/xfree86/VGADriverDoc/VGADriver.Doc,v 3.27 1997/01/27 22:12:18 dawes Exp $ --- 1385,1388 ---- ! $XFree86: xc/programs/Xserver/hw/xfree86/VGADriverDoc/VGADriver.Doc,v 3.27.2.1 1998/02/08 11:19:29 dawes Exp $ *** ./programs/Xserver/hw/xfree86/XF86Conf.man@@/PUBLIC-LATEST Tue Nov 4 21:16:59 1997 --- xc/programs/Xserver/hw/xfree86/XF86Conf.man Fri Mar 6 16:25:15 1998 *************** *** 1,5 **** ! .\" $XFree86: xc/programs/Xserver/hw/xfree86/XF86Conf.man,v 3.52.2.4 1997/05/29 14:01:01 dawes Exp $ ! .TH XF86Config 4/5 "Release 6.4 (XFree86 3.3.1)" "X Version 11" .SH NAME XF86Config - Configuration File for XFree86 .SH DESCRIPTION --- 1,5 ---- ! .\" $XFree86: xc/programs/Xserver/hw/xfree86/XF86Conf.man,v 3.52.2.7 1998/02/26 13:58:52 dawes Exp $ ! .TH XF86Config 4/5 "Version 3.3.2" "XFree86" .SH NAME XF86Config - Configuration File for XFree86 .SH DESCRIPTION *************** *** 288,311 **** .sp .in 20 .nf .B BusMouse .B Logitech .B Microsoft .B MMSeries .B Mouseman .B MouseSystems .B PS/2 ! .B MMHitTab ! .B GlidePoint ! .B IntelliMouse .B Xqueue - .B OSMouse .fi .in -20 .RS 8 .PP ! One should specify \fBBusMouse\fP for the Logitech bus mouse. ! Also, many newer Logitech serial mice use either the \fBMicrosoft\fP or \fBMouseMan\fP protocol. \fBXqueue\fP should be specified here if it was used in the \fBKeyboard\fP section. \fBOSMouse\fP refers to the event-driver mouse interface available on SCO's SVR3, and the --- 288,322 ---- .sp .in 20 .nf + .B Auto .B BusMouse + .B GlidePoint + .B GlidePointPS/2 + .B IntelliMouse + .B IMPS/2 .B Logitech .B Microsoft + .B MMHitTab .B MMSeries .B Mouseman + .B MouseManPlusPS/2 .B MouseSystems + .B NetMousePS/2 + .B NetScrollPS/2 + .B OSMouse .B PS/2 ! .B SysMouse ! .B ThinkingMouse ! .B ThinkingMousePS/2 .B Xqueue .fi .in -20 .RS 8 .PP ! One should specify \fBBusMouse\fP for the Logitech bus mouse and ! bus or InPort mice from Microsoft and ATI. ! The \fBLogitech\fP protocol is for old serial mouse models from Logitech. ! Many newer Logitech serial mice use either the \fBMicrosoft\fP or \fBMouseMan\fP protocol. \fBXqueue\fP should be specified here if it was used in the \fBKeyboard\fP section. \fBOSMouse\fP refers to the event-driver mouse interface available on SCO's SVR3, and the *************** *** 312,320 **** mouse interface provided for OS/2. This may optionally be followed by a number specifying the number of buttons the mouse has. .PP ! If you have a mouse connected to a PS/2 port, you should specify \fBPS/2\fP, ! regardless of the type of mouse you are using. .RE .TP 8 .B Device \fI"pointer-dev"\fP --- 323,342 ---- mouse interface provided for OS/2. This may optionally be followed by a number specifying the number of buttons the mouse has. + \fBSysMouse\fP refers to the system mouse device, /dev/sysmouse, in + FreeBSD. .PP ! The \fBPS/2\fP and other \fBXXXXPS/2\fP protocol types are for PS/2 mice. ! \fBPS/2\fP should always work with any PS/2 mouse ! regardless of the model of the PS/2 mouse. ! The other \fBXXXXPS/2\fP protocol types may or may not be supported by ! your OS. ! .PP ! The rest of the protocol types are for serial mice. ! If your serial mouse is of a relatively new model, you may specify ! \fBAuto\fP, then the X server will try to select an appropriate ! protocol type automatically. The \fBAuto\fP protocol type may ! also work for the PS/2 and bus mice on some OSs. .RE .TP 8 .B Device \fI"pointer-dev"\fP *************** *** 333,338 **** --- 355,370 ---- rate is 1200). For 99% of mice you should not set this to anything other than the default (1200). .TP 8 + .B Buttons \fIN\fP + This option tells the X server the number of buttons on the mouse. + Currently there is no reliable way to automatically detect the correct + number. + This option is the only means for the X server to obtain it. + The default value is three. + Note that if you intend to assign Z axis movement to button events + using the \fBZAxisMapping\fP option below, you need to take account + of those buttons into \fIN\fP too. + .TP 8 .B Emulate3Buttons enables the emulation of the third mouse button for mice which only have two physical buttons. The third button is emulated by pressing *************** *** 351,356 **** --- 383,392 ---- sets the number of motion/button-events the mouse sends per second. This is currently only supported for some Logitech mice. .TP 8 + .B Resolution \fIcount\fP + sets the resolution of the device in counts per inch. + This is not always supported by all the mice. + .TP 8 .B ClearDTR This option clears the DTR line on the serial port used by the mouse. This option is only valid for a mouse using the \fBMouseSystems\fP *************** *** 366,371 **** --- 402,418 ---- protocol. Some dual-protocol mice require both DTR and RTS to be cleared to operate in MouseSystems mode. Both the \fBClearDTR\fP and \fBClearRTS\fP options should be used for such mice. + .TP 8 + .B ZAxisMapping X + .TP 8 + .B ZAxisMapping Y + .TP 8 + .B ZAxisMapping \fIN M\fP + Some mouse devices have a wheel or a roller. Its action is + reported as the Z (third) axis movement in the X server. + The Z axis movement can be assigned to another axis (\fIX\fP or \fIY\fP) + or a pair of buttons (the button \fIN\fP for negative movement + and \fIM\fP for positive movement) with this option. .PP The \fBMonitor\fP sections are used to define the specifications of a monitor and a list of video modes suitable for use with a *************** *** 1072,1075 **** Refer to the .I XFree86(1) manual page. ! .\" $TOG: XF86Conf.man /main/29 1997/11/04 21:19:54 kaleb $ --- 1119,1122 ---- Refer to the .I XFree86(1) manual page. ! .\" $TOG: XF86Conf.man /main/30 1998/03/06 16:26:52 kaleb $ *** ./programs/Xserver/hw/xfree86/XF86Setup/Imakefile@@/PUBLIC-LATEST Sat Jul 19 09:22:05 1997 --- xc/programs/Xserver/hw/xfree86/XF86Setup/Imakefile Fri Mar 6 16:26:55 1998 *************** *** 1,10 **** ! XCOMM $TOG: Imakefile /main/5 1997/07/19 09:22:06 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/Imakefile,v 3.14.2.2 1997/05/27 11:26:49 dawes Exp $ #include #define IHaveSubdirs --- 1,10 ---- ! XCOMM $TOG: Imakefile /main/6 1998/03/06 16:28:33 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/Imakefile,v 3.14.2.6 1998/02/24 13:02:56 dawes Exp $ #include #define IHaveSubdirs *************** *** 31,37 **** TCL_FILES = phase1.tcl phase2.tcl phase3.tcl phase4.tcl phase5.tcl \ setuplib.tcl srvflags.tcl carddata.tcl \ card.tcl done.tcl filelist.tcl keyboard.tcl \ ! mondata.tcl monitor.tcl mouse.tcl LICENSE TCLLIB_FILES = tcllib/button.tcl tcllib/combobox.tcl tcllib/misc.tcl \ tcllib/downarrow.xbm tcllib/dialog.tcl tcllib/entry.tcl \ tcllib/focus.tcl tcllib/init.tcl tcllib/listbox.tcl \ --- 31,38 ---- TCL_FILES = phase1.tcl phase2.tcl phase3.tcl phase4.tcl phase5.tcl \ setuplib.tcl srvflags.tcl carddata.tcl \ card.tcl done.tcl filelist.tcl keyboard.tcl \ ! mseproto.tcl \ ! mondata.tcl monitor.tcl modeselect.tcl mouse.tcl LICENSE TCLLIB_FILES = tcllib/button.tcl tcllib/combobox.tcl tcllib/misc.tcl \ tcllib/downarrow.xbm tcllib/dialog.tcl tcllib/entry.tcl \ tcllib/focus.tcl tcllib/init.tcl tcllib/listbox.tcl \ *************** *** 41,47 **** tcllib/tkerror.tcl tcllib/uparrow.xbm tcllib/license.terms PICS_FILES = pics/vidcard.xbm pics/vidcard.msk \ pics/XFree86.xbm pics/XFree86.msk ! SUBDIRS = scripts #if BuildServersOnly && !defined(UseInstalled) /* Use installed X libraries and headers */ --- 42,48 ---- tcllib/tkerror.tcl tcllib/uparrow.xbm tcllib/license.terms PICS_FILES = pics/vidcard.xbm pics/vidcard.msk \ pics/XFree86.xbm pics/XFree86.msk ! SUBDIRS = scripts texts #if BuildServersOnly && !defined(UseInstalled) /* Use installed X libraries and headers */ *************** *** 53,59 **** #define XawClientDepLibs /**/ #endif ! #if defined(SVR4Architecture) || (defined(LinuxArchitecture) && UseElfFormat) /* Some OSs need this, and it should(?) be harmless when not needed */ /* Not available for Linux x86/a.out and Linux AXP/ECOFF */ EXTRASYSLIBS = -ldl --- 54,60 ---- #define XawClientDepLibs /**/ #endif ! #if defined(SVR4Architecture) || (defined(LinuxArchitecture) && UseElfFormat) || defined(BSD386Architecture) /* Some OSs need this, and it should(?) be harmless when not needed */ /* Not available for Linux x86/a.out and Linux AXP/ECOFF */ EXTRASYSLIBS = -ldl *************** *** 87,92 **** --- 88,95 ---- -I$(EXTINCSRC) $(USEINSTALLEDINC) \ -I$(TCLINCDIR) -I$(TKINCDIR) + MSEPROTODEFS = $(STD_DEFINES) + #if HasLdRunPath CCENVSETUP = LD_RUN_PATH=$(USRLIBDIR):$(TCLLIBDIR) CCLINK = $(CCENVSETUP) $(CC) *************** *** 99,104 **** --- 102,109 ---- LinkSourceFile(cards.c,../xf86config) LinkSourceFile(xf86Config.c,../common) LinkSourceFile(xf86_Config.h,../common) + + CppFileTarget(mseproto.tcl, mseproto.cpp, $(MSEPROTODEFS), NullParameter) MakeSubdirs($(SUBDIRS)) DependSubdirs($(SUBDIRS)) *** ./programs/Xserver/hw/xfree86/XF86Setup/README@@/PUBLIC-LATEST Wed Oct 23 13:16:13 1996 --- xc/programs/Xserver/hw/xfree86/XF86Setup/README Fri Mar 6 16:26:59 1998 *************** *** 40,46 **** main.c Main prog that starts the Tcl interpreter tclcards.c Routines to connect Tcl and the Cards database reading functions - tclcards.h Prototypes for above tclkbd.c Routines to connect to the XKB extension tclmisc.c Routines to connect to the XFree86-Misc extension tclmisc.h Prototypes for above --- 40,45 ---- *************** *** 61,66 **** --- 60,66 ---- filelist.tcl Lists of files that should be checked for proper installation keyboard.tcl Routines for keyboard and other configuration + modeselect.tcl Mode selection routines mondata.tcl Default monitor sync rates and modes monitor.tcl Monitor configuration routines mouse.tcl Mouse configuration routines *************** *** 78,84 **** widget bindings (from the Tcl & Tk 4.0p3 distributions) and with misc tcl routines and the combobox widget ! NEW TCL COMMANDS The program includes a Tcl interpreter which has been extended with --- 78,87 ---- widget bindings (from the Tcl & Tk 4.0p3 distributions) and with misc tcl routines and the combobox widget ! texts Directory containing helps and messages ! (The subdirectories "generic" and "ja" correspond ! to English and Japanese respectively) ! NEW TCL COMMANDS The program includes a Tcl interpreter which has been extended with *************** *** 99,104 **** --- 102,113 ---- Several commands have been added which allow the program to communicate with the XFree86-VidModeExtension server extension, namely: + xf86vid_addmodeline + Add a new mode to the list of video modes + xf86vid_checkmodeline + Checks that a mode is usable + xf86vid_deletemodeline + Removes a mode from the list of valid modes xf86vid_getversion Query extension version xf86vid_getbasevals Get the ErrorBase and EventBase *************** *** 110,115 **** --- 119,126 ---- xf86vid_lockmodeswitch Turn on/off mode switching xf86vid_switchmode Switch to next/previous mode + xf86vid_switchtomode + Switch to a mode Only the last two take an argument, which is either "lock" or "unlock" in the case of "xf86vid_lockmodeswitch" and either "next" or "prev" in *************** *** 149,157 **** Get the current keyboard settings xf86misc_setkeyboard Set the current keyboard settings - xf86misc_getsaver Get the power saver settings - xf86misc_setsaver Set the power saver settings XKEYBOARD extension commands A few commands are available for communicating with the XKEYBOARD --- 160,175 ---- Get the current keyboard settings xf86misc_setkeyboard Set the current keyboard settings + XF86Config file reading commands + + Two commands are available for reading XF86Config file: + + xf86config_findfile + Locate the XF86Config that would be used by the server + xf86config_readfile + Read in the XF86Config file and set the values from it + XKEYBOARD extension commands A few commands are available for communicating with the XKEYBOARD *************** *** 161,167 **** xkb_free Free a previously allocated keyboard description structure xkb_getrulesprop Read the _XKB_RULES_NAMES root property ! xkb_list Returns a list of available components xkb_listrules Returns a list of available rules defs and their descriptions xkb_load Change the keyboard setup for the specified --- 179,185 ---- xkb_free Free a previously allocated keyboard description structure xkb_getrulesprop Read the _XKB_RULES_NAMES root property ! xkb_listcomponents Returns a list of available components xkb_listrules Returns a list of available rules defs and their descriptions xkb_load Change the keyboard setup for the specified *************** *** 192,197 **** --- 210,216 ---- rmdir Remove the named directory umask Set the file creation mode mask sleep Sleeps for the specified number of seconds + clock Obtain and manipulate time findfocuswindow Search along an axis for a window which accepts focus (added to the interpreter after Tk has been initialized) *** ./programs/Xserver/hw/xfree86/XF86Setup/README.html@@/PUBLIC-LATEST Sat Jul 19 09:22:10 1997 --- xc/programs/Xserver/hw/xfree86/XF86Setup/README.html Fri Mar 6 16:27:04 1998 *************** *** 1,9 **** ! ! README for XF86Setup --- 1,9 ---- ! ! README for XF86Setup *************** *** 50,56 ****
main.c
Main prog that starts the Tcl interpreter
tclcards.c
Routines to connect Tcl and the Cards database reading functions -
tclcards.h
Prototypes for above
tclkbd.c
Routines to connect to the XKB extension
tclmisc.c
Routines to connect to the XFree86-Misc extension --- 50,55 ---- *************** *** 72,77 **** --- 71,77 ----
filelist.tcl
Lists of files that should be checked for proper installation
keyboard.tcl
Routines for keyboard and other configuration +
modeselect.tcl
Mode selection routines
mondata.tcl
Default monitor sync rates and modes
monitor.tcl
Monitor configuration routines
mouse.tcl
Mouse configuration routines *************** *** 89,94 **** --- 89,97 ---- standard widget bindings (from the Tcl & Tk 4.0p3 distributions) and with misc tcl routines and the combobox widget +
texts
Directory containing helps and messages + (The subdirectories "generic" and "ja" correspond + to English and Japanese respectively)

New Tcl commands

*************** *** 114,119 **** --- 117,125 ---- communicate with the XFree86-VidModeExtension server extension, namely:
+
xf86vid_addmodeline
Add a new mode to the list of video modes +
xf86vid_checkmodeline
Checks that a mode is usable +
xf86vid_deletemodeline
Removes a mode from the list of valid modes
xf86vid_getversion
Query extension version
xf86vid_getbasevals
Get the ErrorBase and EventBase
xf86vid_getmodeline
Get the current video mode settings *************** *** 121,126 **** --- 127,133 ----
xf86vid_getmonitor
Get monitor specs
xf86vid_lockmodeswitch
Turn on/off mode switching
xf86vid_switchmode
Switch to next/previous mode +
xf86vid_switchtomode
Switch to a mode

Only the last two take an argument, which is either lock or unlock in the case of xf86vid_lockmodeswitch *************** *** 156,165 ****

xf86misc_setmouse
Set the current mouse settings
xf86misc_getkeyboard
Get the current keyboard settings
xf86misc_setkeyboard
Set the current keyboard settings -
xf86misc_getsaver
Get the power saver settings -
xf86misc_setsaver
Set the power saver settings

XKEYBOARD extension commands

A few commands are available for communicating with the XKEYBOARD --- 163,180 ----

xf86misc_setmouse
Set the current mouse settings
xf86misc_getkeyboard
Get the current keyboard settings
xf86misc_setkeyboard
Set the current keyboard settings +

XF86Config file reading commands

+ +

Two commands are available for reading XF86Config file: +

+
xf86config_findfile
Locate the XF86Config that would be + used by the server +
xf86config_readfile
Read in the XF86Config file and set + the values from it +
+

XKEYBOARD extension commands

A few commands are available for communicating with the XKEYBOARD *************** *** 170,176 ****

xkb_free
Free a previously allocated keyboard description structure
xkb_getrulesprop
Read the _XKB_RULES_NAMES root property !
xkb_list
Returns a list of available components
xkb_listrules
Returns a list of available rules defs and their descriptions
xkb_load
Change the keyboard setup for the --- 185,191 ----
xkb_free
Free a previously allocated keyboard description structure
xkb_getrulesprop
Read the _XKB_RULES_NAMES root property !
xkb_listcomponents
Returns a list of available components
xkb_listrules
Returns a list of available rules defs and their descriptions
xkb_load
Change the keyboard setup for the *************** *** 204,209 **** --- 219,225 ----
umask
Set the file creation mode mask
sleep
Sleeps for the specified number of seconds +
clock
Obtain and manipulate time
findfocuswindow
Search along an axis for a window which accepts focus (added to the interpreter after Tk has been initialized) *** ./programs/Xserver/hw/xfree86/XF86Setup/XF86Setup.man@@/PUBLIC-LATEST Tue Nov 4 21:17:28 1997 --- xc/programs/Xserver/hw/xfree86/XF86Setup/XF86Setup.man Fri Mar 6 16:27:08 1998 *************** *** 1,6 **** ! .\" $TOG: XF86Setup.man /main/5 1997/11/04 21:20:23 kaleb $ ! .\" $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/XF86Setup.man,v 3.4.2.1 1997/05/21 15:02:28 dawes Exp $ ! .TH XF86Setup 1 "Release 6.4 (XFree86 3.3.1)" "X Version 11" .SH NAME XF86Setup - Graphical configuration utility for XFree86 .SH SYNOPSIS --- 1,6 ---- ! .\" $TOG: XF86Setup.man /main/6 1998/03/06 16:28:46 kaleb $ ! .\" $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/XF86Setup.man,v 3.4.2.2 1998/02/28 04:47:06 dawes Exp $ ! .TH XF86Setup 1 "Version 3.3.2" "XFree86" .SH NAME XF86Setup - Graphical configuration utility for XFree86 .SH SYNOPSIS *** ./programs/Xserver/hw/xfree86/XF86Setup/card.tcl@@/PUBLIC-LATEST Sun Aug 10 12:57:02 1997 --- xc/programs/Xserver/hw/xfree86/XF86Setup/card.tcl Fri Mar 6 16:27:12 1998 *************** *** 1,9 **** ! # $TOG: card.tcl /main/7 1997/08/10 12:55:38 kaleb $ # # # # ! # $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/card.tcl,v 3.12.2.1 1997/06/20 09:13:48 hohndel Exp $ # # Copyright 1996 by Joseph V. Moss # --- 1,9 ---- ! # $TOG: card.tcl /main/8 1998/03/06 16:28:49 kaleb $ # # # # ! # $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/card.tcl,v 3.12.2.4 1998/02/26 13:58:58 dawes Exp $ # # Copyright 1996 by Joseph V. Moss # *************** *** 19,33 **** proc Card_create_widgets { win } { global ServerList XF86Setup_library cardDevNum DeviceIDs global cardDetail cardReadmeWasSeen UseConfigFile set w [winpathprefix $win] set cardDevNum 0 ! frame $w.card -width 640 -height 420 \ ! -relief ridge -borderwidth 5 frame $w.card.top pack $w.card.top -side top -fill x -padx 5m if { [llength $DeviceIDs] > 1 } { ! label $w.card.title -text "Card selected:" -anchor w pack $w.card.title -side left -fill x -padx 5m -in $w.card.top combobox $w.card.cardselect -state disabled -bd 2 pack $w.card.cardselect -side left -in $w.card.top --- 19,39 ---- proc Card_create_widgets { win } { global ServerList XF86Setup_library cardDevNum DeviceIDs global cardDetail cardReadmeWasSeen UseConfigFile + global pc98_EGC messages set w [winpathprefix $win] set cardDevNum 0 ! if !$pc98_EGC { ! frame $w.card -width 640 -height 420 \ ! -relief ridge -borderwidth 5 ! } else { ! frame $w.card -width 640 -height 400 \ ! -relief ridge -borderwidth 5 ! } frame $w.card.top pack $w.card.top -side top -fill x -padx 5m if { [llength $DeviceIDs] > 1 } { ! label $w.card.title -text $messages(card.1) -anchor w pack $w.card.title -side left -fill x -padx 5m -in $w.card.top combobox $w.card.cardselect -state disabled -bd 2 pack $w.card.cardselect -side left -in $w.card.top *************** *** 38,44 **** bind $w.card.cardselect.popup.list \ "+[list Card_cardselect $win]" } else { ! label $w.card.title -text "Card selected: None" -anchor w pack $w.card.title -side left -fill x -padx 5m -in $w.card.top } --- 44,50 ---- bind $w.card.cardselect.popup.list \ "+[list Card_cardselect $win]" } else { ! label $w.card.title -text $messages(card.2) -anchor w pack $w.card.title -side left -fill x -padx 5m -in $w.card.top } *************** *** 70,81 **** frame $w.card.buttons pack $w.card.buttons -side bottom -fill x ! button $w.card.readme -text "Read README file" \ -command [list Card_display_readme $win] pack $w.card.readme -side left -expand yes \ -in $w.card.buttons ! button $w.card.modebutton -text "Detailed Setup" \ -command [list Card_switchdetail $win] pack $w.card.modebutton -side left -expand yes \ -in $w.card.buttons --- 76,87 ---- frame $w.card.buttons pack $w.card.buttons -side bottom -fill x ! button $w.card.readme -text $messages(card.3) \ -command [list Card_display_readme $win] pack $w.card.readme -side left -expand yes \ -in $w.card.buttons ! button $w.card.modebutton -text $messages(card.4) \ -command [list Card_switchdetail $win] pack $w.card.modebutton -side left -expand yes \ -in $w.card.buttons *************** *** 84,90 **** frame $w.card.server pack $w.card.server -side top -fill x -in $w.card.detail ! label $w.card.server.title -text Server: pack $w.card.server.title -side left foreach serv $ServerList { set lcserv [string tolower $serv] --- 90,96 ---- frame $w.card.server pack $w.card.server -side top -fill x -in $w.card.detail ! label $w.card.server.title -text $messages(card.5) pack $w.card.server.title -side left foreach serv $ServerList { set lcserv [string tolower $serv] *************** *** 101,107 **** frame $w.card.chipset pack $w.card.chipset -side left -expand yes -fill x \ -in $w.card.detail.cboxen -padx 5m ! label $w.card.chipset.title -text Chipset combobox $w.card.chipset.cbox -state disabled -bd 2 pack $w.card.chipset.title $w.card.chipset.cbox --- 107,113 ---- frame $w.card.chipset pack $w.card.chipset -side left -expand yes -fill x \ -in $w.card.detail.cboxen -padx 5m ! label $w.card.chipset.title -text $messages(card.7) combobox $w.card.chipset.cbox -state disabled -bd 2 pack $w.card.chipset.title $w.card.chipset.cbox *************** *** 108,114 **** frame $w.card.ramdac pack $w.card.ramdac -side left -expand yes -fill x \ -in $w.card.detail.cboxen -padx 5m ! label $w.card.ramdac.title -text RamDac combobox $w.card.ramdac.cbox -state disabled -bd 2 pack $w.card.ramdac.title $w.card.ramdac.cbox --- 114,120 ---- frame $w.card.ramdac pack $w.card.ramdac -side left -expand yes -fill x \ -in $w.card.detail.cboxen -padx 5m ! label $w.card.ramdac.title -text $messages(card.8) combobox $w.card.ramdac.cbox -state disabled -bd 2 pack $w.card.ramdac.title $w.card.ramdac.cbox *************** *** 115,121 **** frame $w.card.clockchip pack $w.card.clockchip -side left -expand yes -fill x \ -in $w.card.detail.cboxen -padx 5m ! label $w.card.clockchip.title -text ClockChip combobox $w.card.clockchip.cbox -state disabled -bd 2 pack $w.card.clockchip.title $w.card.clockchip.cbox --- 121,127 ---- frame $w.card.clockchip pack $w.card.clockchip -side left -expand yes -fill x \ -in $w.card.detail.cboxen -padx 5m ! label $w.card.clockchip.title -text $messages(card.9) combobox $w.card.clockchip.cbox -state disabled -bd 2 pack $w.card.clockchip.title $w.card.clockchip.cbox *************** *** 124,132 **** pack $extr -side bottom -padx 5m \ -fill x -expand yes -in $w.card.detail frame $extr.dacspeed ! pack $extr.dacspeed -side left -fill x -expand yes ! label $extr.dacspeed.title -text "RAMDAC Max Speed" ! checkbutton $extr.dacspeed.probe -width 15 -text "Probed" \ -variable cardDacProbe -indicator off \ -command [list Card_dacspeed $win] \ -highlightthickness 0 --- 130,140 ---- pack $extr -side bottom -padx 5m \ -fill x -expand yes -in $w.card.detail frame $extr.dacspeed ! if { $UseConfigFile } { ! pack $extr.dacspeed -side left -fill x -expand yes ! } ! label $extr.dacspeed.title -text $messages(card.10) ! checkbutton $extr.dacspeed.probe -width 15 -text $messages(card.11) \ -variable cardDacProbe -indicator off \ -command [list Card_dacspeed $win] \ -highlightthickness 0 *************** *** 139,148 **** pack $extr.dacspeed.value -side top -fill x -expand yes frame $extr.videoram pack $extr.videoram -side left -fill x -expand yes ! label $extr.videoram.title -text "Video RAM" pack $extr.videoram.title -side top -fill x -expand yes radiobutton $extr.videoram.mprobed -indicator off -width 15 \ ! -variable cardRamSize -value 0 -text "Probed" \ -highlightthickness 0 pack $extr.videoram.mprobed -side top -expand yes frame $extr.videoram.cols --- 147,156 ---- pack $extr.dacspeed.value -side top -fill x -expand yes frame $extr.videoram pack $extr.videoram -side left -fill x -expand yes ! label $extr.videoram.title -text $messages(card.12) pack $extr.videoram.title -side top -fill x -expand yes radiobutton $extr.videoram.mprobed -indicator off -width 15 \ ! -variable cardRamSize -value 0 -text $messages(card.13) \ -highlightthickness 0 pack $extr.videoram.mprobed -side top -expand yes frame $extr.videoram.cols *************** *** 153,180 **** -side left -fill x -expand yes \ -in $extr.videoram.cols radiobutton $extr.videoram.m256k \ ! -variable cardRamSize -value 256 -text "256K" \ -highlightthickness 0 radiobutton $extr.videoram.m512k \ ! -variable cardRamSize -value 512 -text "512K" \ -highlightthickness 0 radiobutton $extr.videoram.m1m \ ! -variable cardRamSize -value 1024 -text "1Meg" \ -highlightthickness 0 radiobutton $extr.videoram.m2m \ ! -variable cardRamSize -value 2048 -text "2Meg" \ -highlightthickness 0 radiobutton $extr.videoram.m3m \ ! -variable cardRamSize -value 3072 -text "3Meg" \ -highlightthickness 0 radiobutton $extr.videoram.m4m \ ! -variable cardRamSize -value 4096 -text "4Meg" \ -highlightthickness 0 radiobutton $extr.videoram.m6m \ ! -variable cardRamSize -value 6144 -text "6Meg" \ -highlightthickness 0 radiobutton $extr.videoram.m8m \ ! -variable cardRamSize -value 8192 -text "8Meg" \ -highlightthickness 0 pack $extr.videoram.m256k $extr.videoram.m512k \ $extr.videoram.m1m $extr.videoram.m2m \ --- 161,188 ---- -side left -fill x -expand yes \ -in $extr.videoram.cols radiobutton $extr.videoram.m256k \ ! -variable cardRamSize -value 256 -text $messages(card.14) \ -highlightthickness 0 radiobutton $extr.videoram.m512k \ ! -variable cardRamSize -value 512 -text $messages(card.15) \ -highlightthickness 0 radiobutton $extr.videoram.m1m \ ! -variable cardRamSize -value 1024 -text $messages(card.16) \ -highlightthickness 0 radiobutton $extr.videoram.m2m \ ! -variable cardRamSize -value 2048 -text $messages(card.17) \ -highlightthickness 0 radiobutton $extr.videoram.m3m \ ! -variable cardRamSize -value 3072 -text $messages(card.18) \ -highlightthickness 0 radiobutton $extr.videoram.m4m \ ! -variable cardRamSize -value 4096 -text $messages(card.19) \ -highlightthickness 0 radiobutton $extr.videoram.m6m \ ! -variable cardRamSize -value 6144 -text $messages(card.20) \ -highlightthickness 0 radiobutton $extr.videoram.m8m \ ! -variable cardRamSize -value 8192 -text $messages(card.21) \ -highlightthickness 0 pack $extr.videoram.m256k $extr.videoram.m512k \ $extr.videoram.m1m $extr.videoram.m2m \ *************** *** 192,198 **** frame $w.card.options.list pack $w.card.options.list -side top combobox $w.card.options.list.cbox -state disabled -width 80 -bd 2 ! label $w.card.options.list.title -text "Selected options:" $w.card.options.list.cbox.popup.list configure \ -selectmode multiple pack $w.card.options.list.title -side left --- 200,206 ---- frame $w.card.options.list pack $w.card.options.list -side top combobox $w.card.options.list.cbox -state disabled -width 80 -bd 2 ! label $w.card.options.list.title -text $messages(card.22) $w.card.options.list.cbox.popup.list configure \ -selectmode multiple pack $w.card.options.list.title -side left *************** *** 204,211 **** -setgrid true -height 4 -background white scrollbar $w.card.options.text.sb -command \ [list $w.card.options.text.text yview] ! label $w.card.options.text.title -text "Additional lines to\ ! add to Device section of the XF86Config file:" pack $w.card.options.text.title -fill x -expand yes -side top pack $w.card.options.text.text -fill x -expand yes -side left pack $w.card.options.text.sb -side left -fill y --- 212,218 ---- -setgrid true -height 4 -background white scrollbar $w.card.options.text.sb -command \ [list $w.card.options.text.text yview] ! label $w.card.options.text.title -text $messages(card.23) pack $w.card.options.text.title -fill x -expand yes -side top pack $w.card.options.text.text -fill x -expand yes -side left pack $w.card.options.text.sb -side left -fill y *************** *** 237,251 **** } proc Card_dacspeed { win } { ! global cardDacSpeed cardDacProbe set w [winpathprefix $win] if { $cardDacProbe } { ! #$w.card.extra.dacspeed.probe configure -text "Probed: Yes" $w.card.extra.dacspeed.value configure \ -foreground [option get $w.card background *] ;# -state disabled } else { ! #$w.card.extra.dacspeed.probe configure -text "Probed: No" $w.card.extra.dacspeed.value configure \ -foreground [option get $w.card foreground *] -state normal } --- 244,260 ---- } proc Card_dacspeed { win } { ! global cardDacSpeed cardDacProbe messages set w [winpathprefix $win] if { $cardDacProbe } { ! #$w.card.extra.dacspeed.probe configure \ ! # -text $messages(card.24) $w.card.extra.dacspeed.value configure \ -foreground [option get $w.card background *] ;# -state disabled } else { ! #$w.card.extra.dacspeed.probe configure \ ! # -text $messages(card.25) $w.card.extra.dacspeed.value configure \ -foreground [option get $w.card foreground *] -state normal } *************** *** 252,279 **** } proc Card_switchdetail { win } { ! global cardDetail cardDevNum set w [winpathprefix $win] if { $cardDetail == "std" } { set cardDetail detail ! $w.card.modebutton configure -text "Card List" pack forget $w.card.list pack $w.card.detail -expand yes -side top -fill both ! $w.card.bot.message configure -text \ ! "First make sure the correct server is selected,\ ! then make whatever changes are needed\n\ ! If the Chipset, RamDac, or ClockChip entries\ ! are left blank, they will be probed" } else { set cardDetail std ! $w.card.modebutton configure -text "Detailed Setup" pack forget $w.card.detail pack $w.card.list -expand yes -side top -fill both ! $w.card.bot.message configure -text \ ! "Select your card from the list.\n\ ! If your card is not listed,\ ! click on the Detailed Setup button" } } --- 261,281 ---- } proc Card_switchdetail { win } { ! global cardDetail cardDevNum messages set w [winpathprefix $win] if { $cardDetail == "std" } { set cardDetail detail ! $w.card.modebutton configure -text $messages(card.26) pack forget $w.card.list pack $w.card.detail -expand yes -side top -fill both ! $w.card.bot.message configure -text $messages(card.30) } else { set cardDetail std ! $w.card.modebutton configure -text $messages(card.27) pack forget $w.card.detail pack $w.card.list -expand yes -side top -fill both ! $w.card.bot.message configure -text $messages(card.31) } } *************** *** 308,313 **** --- 310,316 ---- proc Card_selected { win lbox } { global cardServer cardReadmeWasSeen cardDevNum cardDriverReadme + global messages set w [winpathprefix $win] if { ![string length [$lbox curselection]] } return *************** *** 314,320 **** set cardentry [$lbox get [$lbox curselection]] set carddata [xf86cards_getentry $cardentry] set cardDriverReadme "" ! $w.card.title configure -text "Card selected: $cardentry" $w.card.options.text.text delete 0.0 end if { [lsearch [lindex $carddata 7] UNSUPPORTED] == -1 } { #Card_cbox_setentry $w.card.chipset.cbox [lindex $carddata 1] --- 317,323 ---- set cardentry [$lbox get [$lbox curselection]] set carddata [xf86cards_getentry $cardentry] set cardDriverReadme "" ! $w.card.title configure -text "$messages(card.28)$cardentry" $w.card.options.text.text delete 0.0 end if { [lsearch [lindex $carddata 7] UNSUPPORTED] == -1 } { #Card_cbox_setentry $w.card.chipset.cbox [lindex $carddata 1] *************** *** 345,360 **** Card_cbox_setentry $w.card.clockchip.cbox [lindex $carddata 4] $w.card.options.text.text insert 0.0 [lindex $carddata 6] if { $cardReadmeWasSeen($cardDevNum) } { ! $w.card.bot.message configure -text \ ! "That's all there is to configuring your card\n\ ! unless you would like to make changes to the\ ! standard settings (by pressing Detailed Setup)" } else { ! $w.card.bot.message configure -text \ ! "That's probably all there is to configuring\ ! your card, but you should probably check the\n\ ! README to make sure. If any changes are needed,\ ! press the Detailed Setup button" } } else { set cardServer VGA16 --- 348,356 ---- Card_cbox_setentry $w.card.clockchip.cbox [lindex $carddata 4] $w.card.options.text.text insert 0.0 [lindex $carddata 6] if { $cardReadmeWasSeen($cardDevNum) } { ! $w.card.bot.message configure -text $messages(card.32) } else { ! $w.card.bot.message configure -text $messages(card.33) } } else { set cardServer VGA16 *************** *** 361,371 **** Card_cbox_setentry $w.card.chipset.cbox generic Card_cbox_setentry $w.card.ramdac.cbox "" Card_cbox_setentry $w.card.clockchip.cbox "" ! $w.card.bot.message configure -text \ ! "You have selected a card which is not fully\ ! supported by XFree86, however all of the proper\n\ ! configuration options have been set such that it\ ! should work in standard VGA mode" } Card_set_cboxlists $win cardselected } --- 357,363 ---- Card_cbox_setentry $w.card.chipset.cbox generic Card_cbox_setentry $w.card.ramdac.cbox "" Card_cbox_setentry $w.card.clockchip.cbox "" ! $w.card.bot.message configure -text $messages(card.34) } Card_set_cboxlists $win cardselected } *************** *** 372,398 **** proc Card_set_cboxlists { win args } { global CardChipSets CardRamDacs CardClockChips cardServer ! global CardReadmes cardReadmeWasSeen CardOptions Xwinhome set w [winpathprefix $win] ! if ![file exists $Xwinhome/bin/XF86_$cardServer] { ! if ![string compare $args cardselected] { ! $w.card.bot.message configure -text \ ! "*** The server required by your card is not\ ! installed! Please abort, install the\ ! $cardServer server as\n\ ! $Xwinhome/bin/XF86_$cardServer and\ ! run this program again ***" ! } else { ! $w.card.bot.message configure -text \ ! "*** The selected server is not\ ! installed! Please abort, install the\ ! $cardServer server as\n\ ! $Xwinhome/bin/XF86_$cardServer and\ ! run this program again ***" ! } ! bell ! } if { [llength $CardReadmes($cardServer)] > 0 } { $w.card.readme configure -state normal } else { --- 364,373 ---- proc Card_set_cboxlists { win args } { global CardChipSets CardRamDacs CardClockChips cardServer ! global CardReadmes cardReadmeWasSeen CardOptions set w [winpathprefix $win] ! $w.card.bot.message configure -text [make_message_card $args] if { [llength $CardReadmes($cardServer)] > 0 } { $w.card.readme configure -state normal } else { *************** *** 465,471 **** proc Card_display_readme { win } { global cardServer CardReadmes cardReadmeWasSeen cardDriverReadme ! global cardDevNum Xwinhome set w [winpathprefix $win] catch {destroy .cardreadme} --- 440,446 ---- proc Card_display_readme { win } { global cardServer CardReadmes cardReadmeWasSeen cardDriverReadme ! global cardDevNum Xwinhome messages pc98_EGC set w [winpathprefix $win] catch {destroy .cardreadme} *************** *** 476,481 **** --- 451,459 ---- text .cardreadme.file.text -setgrid true \ -xscroll ".cardreadme.horz.hsb set" \ -yscroll ".cardreadme.file.vsb set" + if $pc98_EGC { + .cardreadme.file.text configure -height 20 + } if { ![string compare $cardServer "SVGA"] && [string length $cardDriverReadme] } { set readmeindex $cardServer-$cardDriverReadme *************** *** 495,501 **** scrollbar .cardreadme.file.vsb \ -command ".cardreadme.file.text yview" \ -repeatdelay 1200 -repeatinterval 800 ! button .cardreadme.ok -text "Dismiss" -command "destroy .cardreadme" focus .cardreadme.ok pack .cardreadme.file -side top -fill both pack .cardreadme.file.text -side left --- 473,480 ---- scrollbar .cardreadme.file.vsb \ -command ".cardreadme.file.text yview" \ -repeatdelay 1200 -repeatinterval 800 ! button .cardreadme.ok -text $messages(card.29) \ ! -command "destroy .cardreadme" focus .cardreadme.ok pack .cardreadme.file -side top -fill both pack .cardreadme.file.text -side left *************** *** 524,529 **** --- 503,509 ---- global DeviceIDs cardServer ServerList cardDevNum global AccelServerList CardChipSets CardRamDacs CardClockChips global cardDacSpeed cardDacProbe cardRamSize UseConfigFile + global messages set w [winpathprefix $win] set devid [lindex $DeviceIDs $cardDevNum] *************** *** 537,550 **** set Device_${devid}(Options) [split [$w.card.options.list.cbox eget] ,] if {[llength $DeviceIDs] == 1} { set Device_${devid}(BoardName) [string range \ ! [$w.card.title cget -text] 15 end] } if { $UseConfigFile } { - if { $cardRamSize } { - set Device_${devid}(VideoRam) $cardRamSize - } else { - set Device_${devid}(VideoRam) "" - } if { $cardDacProbe } { set Device_${devid}(DacSpeed) "" } else { --- 517,531 ---- set Device_${devid}(Options) [split [$w.card.options.list.cbox eget] ,] if {[llength $DeviceIDs] == 1} { set Device_${devid}(BoardName) [string range \ ! [$w.card.title cget -text] \ ! [string length $messages(card.28)] end] } + if { $cardRamSize } { + set Device_${devid}(VideoRam) $cardRamSize + } else { + set Device_${devid}(VideoRam) "" + } if { $UseConfigFile } { if { $cardDacProbe } { set Device_${devid}(DacSpeed) "" } else { *************** *** 587,657 **** set cardDacProbe 1 } Card_dacspeed $win - } - } - - proc Card_popup_help { win } { - global cardDetail - - catch {destroy .cardhelp} - toplevel .cardhelp -bd 5 -relief ridge - wm title .cardhelp "Help" - wm geometry .cardhelp +30+30 - text .cardhelp.text - if { $cardDetail == "std" } { - .cardhelp.text insert 0.0 "\n\n\ - Pick your card from the list.\n\n\ - If there are README files that may pertain to your card\n\ - the 'Read README file' button will then be usable (i.e. not\ - greyed out).\n\ - Please read them.\n\n\ - If your card is not in the list, or if there are any\ - special settings\n\ - listed in the README file as required by your card, you\ - can press the\n\ - 'Detailed Setup' button to make sure that\ - they have been selected." } else { ! global DeviceIDs ! if { [llength $DeviceIDs] > 1 } { ! .cardhelp.text insert 0.0 \ ! " If you picked a card from the Card list, at least most\ ! things should\n\ ! already be set properly.\n\n" ! } else { ! .cardhelp.text insert 0.0 "\n\n" ! } ! .cardhelp.text insert end \ ! " First select the appropriate server for your card.\n\ ! Then read the README file corresponding to the selected\ ! server by pressing\n\ ! the 'Read README file' button (it won't do anything, if\ ! there is no README).\n\n\ ! Next, pick the chipset, and Ramdac of your card, if\ ! directed by the README\n\ ! file. In most cases, you don't need to select these,\ ! as the server will\n\ ! detect (probe) them automatically.\n\n\ ! The clockchip should generally be picked, if your card\ ! has one, as these\n\ ! are often impossible to probe (the exception is when\ ! the clockchip is built\n\ ! into one of the other chips).\n\n\ ! Choose whatever options are appropriate (again,\ ! according to the README).\n\n\ ! You can also set the maximum speed of your Ramdac. Some\ ! Ramdacs are available\n\ ! with various speed ratings. The max speed cannot be\ ! detected by the server\n\ ! so it will use the speed rating of the slowest version\ ! of the specified Ramdac.\n\n\ ! Additionally, you can also specify the amount of RAM on\ ! your card, though\n\ ! the server will usually be able to detect this." } - .cardhelp.text configure -state disabled - button .cardhelp.ok -text "Dismiss" -command "destroy .cardhelp" - focus .cardhelp.ok - pack .cardhelp.text .cardhelp.ok } - --- 568,574 ---- set cardDacProbe 1 } Card_dacspeed $win } else { ! set cardRamSize 0 } } *** ./programs/Xserver/hw/xfree86/XF86Setup/carddata.tcl@@/PUBLIC-LATEST Sun Aug 10 12:57:08 1997 --- xc/programs/Xserver/hw/xfree86/XF86Setup/carddata.tcl Fri Mar 6 16:27:17 1998 *************** *** 1,9 **** ! # $TOG: carddata.tcl /main/10 1997/08/10 12:55:44 kaleb $ # # # # ! # $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/carddata.tcl,v 3.12.2.5 1997/08/02 13:48:11 dawes Exp $ # # Copyright 1996 by Joseph V. Moss # --- 1,9 ---- ! # $TOG: carddata.tcl /main/11 1998/03/06 16:28:55 kaleb $ # # # # ! # $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/carddata.tcl,v 3.12.2.7 1998/02/15 16:08:51 hohndel Exp $ # # Copyright 1996 by Joseph V. Moss # *************** *** 16,25 **** # ! set ServerList [list Mono VGA16 SVGA 8514 AGX I128 \ ! Mach8 Mach32 Mach64 P9000 S3 S3V TGA W32 ] ! set AccelServerList [list 8514 AGX I128 Mach8 Mach32 Mach64 P9000 \ ! S3 S3V TGA W32 ] ### --- 16,32 ---- # ! if !$pc98 { ! set ServerList [list Mono VGA16 SVGA 8514 AGX I128 \ ! Mach8 Mach32 Mach64 P9000 S3 S3V TGA W32 ] ! set AccelServerList [list 8514 AGX I128 Mach8 Mach32 Mach64 P9000 \ ! S3 S3V TGA W32 ] ! } else { ! set ServerList [list EGC NEC480 GANBWAP NKVNEC TGUI MGA \ ! WABS WABEP WSNA NECS3 PWSKB PWLB GA968 ] ! set AccelServerList [list EGC NEC480 GANBWAP NKVNEC TGUI MGA \ ! WABS WABEP WSNA NECS3 PWSKB PWLB GA968 ] ! } ### *************** *** 27,33 **** # and SVGA servers, the list is broken out by driver)? set CardChipSets(SVGA-al2101) al2101 set CardChipSets(SVGA-ali) { ali2228 ali2301 ali2302 ali2308 ali2401 } ! set CardChipSets(SVGA-apm) { ap6422 at24 } set CardChipSets(SVGA-ark) { ark1000vl ark1000pv ark2000pv ark2000mt } set CardChipSets(SVGA-ati) ati set CardChipSets(SVGA-cl64xx) { cl6410 cl6412 cl6420 cl6440 } --- 34,40 ---- # and SVGA servers, the list is broken out by driver)? set CardChipSets(SVGA-al2101) al2101 set CardChipSets(SVGA-ali) { ali2228 ali2301 ali2302 ali2308 ali2401 } ! set CardChipSets(SVGA-apm) { ap6422 at24 AT3D } set CardChipSets(SVGA-ark) { ark1000vl ark1000pv ark2000pv ark2000mt } set CardChipSets(SVGA-ati) ati set CardChipSets(SVGA-cl64xx) { cl6410 cl6412 cl6420 cl6440 } *************** *** 51,57 **** set CardChipSets(SVGA-mga) { mga2064w mga1064sg mga2164w } set CardChipSets(SVGA-mx) mx set CardChipSets(SVGA-ncr77c22) { ncr77c22 ncr77c22e } ! set CardChipSets(SVGA-nv) { nv1 stg2000 } set CardChipSets(SVGA-oak) { oti067 oti077 oti087 oti037c } set CardChipSets(SVGA-pvga1) { pvga1 \ wd90c00 wd90c10 wd90c30 wd90c24 \ --- 58,64 ---- set CardChipSets(SVGA-mga) { mga2064w mga1064sg mga2164w } set CardChipSets(SVGA-mx) mx set CardChipSets(SVGA-ncr77c22) { ncr77c22 ncr77c22e } ! set CardChipSets(SVGA-nv) { nv1 stg2000 riva128 } set CardChipSets(SVGA-oak) { oti067 oti077 oti087 oti037c } set CardChipSets(SVGA-pvga1) { pvga1 \ wd90c00 wd90c10 wd90c30 wd90c24 \ *************** *** 119,124 **** --- 126,155 ---- et4000w32p_rev_b et4000w32p_rev_c \ et4000w32p_rev_d et6000 } + set CardChipSets(EGC) { vga } + set CardChipSets(NEC480) { pegc } + set CardChipSets(GANBWAP) { clgd5426 clgd5428 clgd5429 clgd5430 \ + clgd5434 clgd5440 clgd5446 clgd7543 \ + clgd7548 clgd7555 } + set CardChipSets(NKVNEC) { clgd5426 clgd5428 clgd5429 clgd5430 \ + clgd5434 clgd5440 clgd5446 clgd7543 \ + clgd7548 clgd7555 } + set CardChipSets(WABS) { clgd5426 clgd5428 clgd5429 clgd5430 \ + clgd5434 clgd5440 clgd5446 clgd7543 \ + clgd7548 clgd7555 } + set CardChipSets(WABEP) { clgd5426 clgd5428 clgd5429 clgd5430 \ + clgd5434 clgd5440 clgd5446 clgd7543 \ + clgd7548 clgd7555 } + set CardChipSets(WSNA) { clgd5426 clgd5428 clgd5429 clgd5430 \ + clgd5434 clgd5440 clgd5446 clgd7543 \ + clgd7548 clgd7555 } + set CardChipSets(TGUI) { tgui9660xgi tgui9680 cyber938x } + set CardChipSets(MGA) { } + set CardChipSets(NECS3) { s3_generic mmio_928 } + set CardChipSets(PWSKB) { s3_generic mmio_928 } + set CardChipSets(PWLB) { mmio_928 s3_generic } + set CardChipSets(GA968) { newmmio mmio_928 s3_generic } + ### # For each server, what ramdacs can be chosen? *************** *** 200,205 **** --- 231,250 ---- set CardRamDacs(Mono-ati) $CardRamDacs(SVGA-ati) set CardRamDacs(Mono-et4000) $CardRamDacs(SVGA-et4000) set CardRamDacs(Mono) $CardRamDacs(VGA16) + + set CardRamDacs(EGC) {} + set CardRamDacs(NEC480) {} + set CardRamDacs(GANBWAP) {} + set CardRamDacs(NKVNEC) {} + set CardRamDacs(WABS) {} + set CardRamDacs(WABEP) {} + set CardRamDacs(WSNA) {} + set CardRamDacs(TGUI) {} + set CardRamDacs(MGA) ti3026 + set CardRamDacs(NECS3) { sc15025 s3_sdac } + set CardRamDacs(PWSKB) { sc15025 bt478 bt485 s3_gendac att20c498 } + set CardRamDacs(PWLB) { att20c505 sc15025 ti3025 } + set CardRamDacs(GA968) ibm_rgb524 unset daclist idx ### *************** *** 250,255 **** --- 295,314 ---- set CardClockChips(Mono) [lrmdups [concat $CardClockChips(Mono-cirrus) \ $CardClockChips(Mono-et4000) \ $CardClockChips(Mono-tvga8900)] ] + + set CardClockChips(EGC) {} + set CardClockChips(NEC480) {} + set CardClockChips(GANBWAP) cirrus + set CardClockChips(NKVNEC) cirrus + set CardClockChips(WABS) cirrus + set CardClockChips(WABEP) cirrus + set CardClockChips(WSNA) cirrus + set CardClockChips(TGUI) tgui + set CardClockChips(MGA) ti3026 + set CardClockChips(NECS3) s3_sdac + set CardClockChips(PWSKB) { icd2061a s3_gendac } + set CardClockChips(PWLB) { icd2061a ti3025 } + set CardClockChips(GA968) {} unset clklist idx # For each server, what options can be chosen? *************** *** 378,383 **** --- 437,459 ---- power_saver slow_dram \ w32_interleave_off w32_interleave_on } + set CardOptions(EGC) {} + set CardOptions(NEC480) {} + set CardOptions(GANBWAP) { ga98nb1 ga98nb2 ga98nb4 wap epsonmemwin \ + sw_cursor } + set CardOptions(NKVNEC) { nec_cirrus } + set CardOptions(WABS) {} + set CardOptions(WABEP) { med_dram } + set CardOptions(WSNA) { epsonmemwin sw_cursor med_dram } + set CardOptions(TGUI) { noaccel } + set CardOptions(MGA) { noaccel } + set CardOptions(NECS3) { necwab nomemaccess dac_8_bit bt485_curs } + set CardOptions(PWSKB) { pcskb pcskb4 pchkb pw805i pw_mux \ + nomemaccess epsonmemwin dac_8_bit \ + bt485_curs } + set CardOptions(PWLB) { pw_localbus dac_8_bit bt485_curs numbernine } + set CardOptions(GA968) {} + # For each server, what readme files are applicable? set CardReadmes(SVGA-ark) README.ark set CardReadmes(SVGA-ati) README.ati *************** *** 442,444 **** --- 518,533 ---- set CardReadmes(TGA) README.DECtga set CardReadmes(W32) README.W32 + set CardReadmes(EGC) {} + set CardReadmes(NEC480) {} + set CardReadmes(GANBWAP) README.cirrus + set CardReadmes(NKVNEC) README.cirrus + set CardReadmes(WABS) README.cirrus + set CardReadmes(WABEP) README.cirrus + set CardReadmes(WSNA) README.cirrus + set CardReadmes(TGUI) README.trident + set CardReadmes(MGA) README.MGA + set CardReadmes(NECS3) README.S3 + set CardReadmes(PWSKB) README.S3 + set CardReadmes(PWLB) README.S3 + set CardReadmes(GA968) README.S3 *** ./programs/Xserver/hw/xfree86/XF86Setup/done.tcl@@/PUBLIC-LATEST Sat Jul 19 09:22:30 1997 --- xc/programs/Xserver/hw/xfree86/XF86Setup/done.tcl Fri Mar 6 16:27:21 1998 *************** *** 1,9 **** ! # $TOG: done.tcl /main/5 1997/07/19 09:22:31 kaleb $ # # # # ! # $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/done.tcl,v 3.7 1996/12/27 06:54:02 dawes Exp $ # # Copyright 1996 by Joseph V. Moss # --- 1,9 ---- ! # $TOG: done.tcl /main/6 1998/03/06 16:28:59 kaleb $ # # # # ! # $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/done.tcl,v 3.7.2.2 1998/02/21 06:06:59 robin Exp $ # # Copyright 1996 by Joseph V. Moss # *************** *** 16,36 **** # proc Done_create_widgets { win } { set w [winpathprefix $win] ! frame $w.done -width 640 -height 420 \ ! -relief ridge -borderwidth 5 frame $w.done.pad -relief raised -bd 3 pack $w.done.pad -padx 20 -pady 15 -expand yes label $w.done.pad.text ! $w.done.pad.text configure -text "\n\n\ ! If you've finished configuring everything press the\n\ ! Okay button to start the X server using the\ ! configuration you've selected.\n\n\ ! If you still wish to configure some things,\n\ ! press one of the buttons at the top and then\n\ ! press \"Done\" again, when you've finished." pack $w.done.pad.text -fill both -expand yes ! button $w.done.pad.okay -text "Okay" \ -command [list Done_nextphase $w] pack $w.done.pad.okay -side bottom -pady 10m focus $w.done.pad.okay --- 16,36 ---- # proc Done_create_widgets { win } { + global pc98_EGC messages set w [winpathprefix $win] ! if !$pc98_EGC { ! frame $w.done -width 640 -height 420 \ ! -relief ridge -borderwidth 5 ! } else { ! frame $w.done -width 640 -height 400 \ ! -relief ridge -borderwidth 5 ! } frame $w.done.pad -relief raised -bd 3 pack $w.done.pad -padx 20 -pady 15 -expand yes label $w.done.pad.text ! $w.done.pad.text configure -text $messages(done.1) pack $w.done.pad.text -fill both -expand yes ! button $w.done.pad.okay -text $messages(done.2) \ -command [list Done_nextphase $w] pack $w.done.pad.okay -side bottom -pady 10m focus $w.done.pad.okay *************** *** 47,73 **** pack forget $w.done } - proc Done_popup_help { win } { - catch {destroy .donehelp} - toplevel .donehelp -bd 5 -relief ridge - wm title .donehelp "Help" - wm geometry .donehelp +30+30 - text .donehelp.text - .donehelp.text insert 0.0 "\n\n\ - If you've finished configuring everything, select the\ - 'Okay' button.\n\n\ - If there are still some configuration screens you\ - have not completed,\n\ - pick the appropriate button from the row across the top\ - and then press\n\ - 'Done' again, when you've finished all of the\ - configuration screens." - .donehelp.text configure -state disabled - button .donehelp.ok -text "Dismiss" -command "destroy .donehelp" - focus .donehelp.ok - pack .donehelp.text .donehelp.ok - } - proc Done_execute { win } { global CfgSelection --- 47,52 ---- *************** *** 77,83 **** } proc Done_nextphase { win } { ! global StartServer XF86Setup_library env set w [winpathprefix $win] if $StartServer { --- 56,62 ---- } proc Done_nextphase { win } { ! global StartServer XF86Setup_library env messages set w [winpathprefix $win] if $StartServer { *** ./programs/Xserver/hw/xfree86/XF86Setup/filelist.tcl@@/PUBLIC-LATEST Sat Jul 19 09:22:35 1997 --- xc/programs/Xserver/hw/xfree86/XF86Setup/filelist.tcl Fri Mar 6 16:27:26 1998 *************** *** 1,9 **** ! # $TOG: filelist.tcl /main/3 1997/07/19 09:22:36 kaleb $ # # # # ! # $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/filelist.tcl,v 3.4 1996/12/27 06:54:03 dawes Exp $ # # Copyright 1996 by Joseph V. Moss # --- 1,9 ---- ! # $TOG: filelist.tcl /main/4 1998/03/06 16:29:04 kaleb $ # # # # ! # $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/filelist.tcl,v 3.4.2.1 1998/02/26 13:58:58 dawes Exp $ # # Copyright 1996 by Joseph V. Moss # *************** *** 93,105 **** } array set FilePermsReadMe { ! lib/X11/doc/README.Oak 444 ! lib/X11/doc/README.ati 444 ! lib/X11/doc/README.trident 444 ! lib/X11/doc/README.agx 444 lib/X11/doc/README.Mach64 444 lib/X11/doc/README.P9000 444 lib/X11/doc/README.S3 444 lib/X11/doc/README.W32 444 } --- 93,117 ---- } array set FilePermsReadMe { ! lib/X11/doc/README.DECtga 444 ! lib/X11/doc/README.MGA 444 ! lib/X11/doc/README.Mach32 444 lib/X11/doc/README.Mach64 444 + lib/X11/doc/README.NV1 444 + lib/X11/doc/README.Oak 444 lib/X11/doc/README.P9000 444 lib/X11/doc/README.S3 444 + lib/X11/doc/README.S3V 444 + lib/X11/doc/README.SiS 444 + lib/X11/doc/README.Video7 444 lib/X11/doc/README.W32 444 + lib/X11/doc/README.WstDig 444 + lib/X11/doc/README.agx 444 + lib/X11/doc/README.ark 444 + lib/X11/doc/README.ati 444 + lib/X11/doc/README.chips 444 + lib/X11/doc/README.cirrus 444 + lib/X11/doc/README.trident 444 + lib/X11/doc/README.tseng 444 } *** ./programs/Xserver/hw/xfree86/XF86Setup/keyboard.tcl@@/PUBLIC-LATEST Sat Jul 19 09:22:39 1997 --- xc/programs/Xserver/hw/xfree86/XF86Setup/keyboard.tcl Fri Mar 6 16:27:30 1998 *************** *** 1,9 **** ! # $TOG: keyboard.tcl /main/3 1997/07/19 09:22:41 kaleb $ # # # # ! # $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/keyboard.tcl,v 3.9 1996/12/27 06:54:04 dawes Exp $ # # Copyright 1996 by Joseph V. Moss # --- 1,9 ---- ! # $TOG: keyboard.tcl /main/4 1998/03/06 16:29:07 kaleb $ # # # # ! # $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/keyboard.tcl,v 3.9.2.2 1998/02/21 06:06:59 robin Exp $ # # Copyright 1996 by Joseph V. Moss # *************** *** 17,45 **** proc Keyboard_create_widgets { win } { global XKBComponents XKBinserver XKBhandle set w [winpathprefix $win] ! frame $w.keyboard -width 640 -height 420 \ ! -relief ridge -borderwidth 5 frame $w.keyboard.xkb ! label $w.keyboard.xkb.text -text \ ! "Select the appropriate model and layout" frame $w.keyboard.xkb.geom ! label $w.keyboard.xkb.geom.title -text "Model:" combobox $w.keyboard.xkb.geom.cbox -bd 2 -width 30 eval [list $w.keyboard.xkb.geom.cbox linsert end] \ $XKBComponents(models,descriptions) pack $w.keyboard.xkb.geom.title $w.keyboard.xkb.geom.cbox -side top frame $w.keyboard.xkb.lang ! label $w.keyboard.xkb.lang.title -text "Layout (language):" combobox $w.keyboard.xkb.lang.cbox -bd 2 -width 30 eval [list $w.keyboard.xkb.lang.cbox linsert end] \ $XKBComponents(layouts,descriptions) pack $w.keyboard.xkb.lang.title $w.keyboard.xkb.lang.cbox -side top frame $w.keyboard.xkb.vari ! label $w.keyboard.xkb.vari.title -text \ ! "Variant (non U.S. Keyboards only):" combobox $w.keyboard.xkb.vari.cbox -bd 2 -width 30 $w.keyboard.xkb.vari.cbox linsert end "" eval [list $w.keyboard.xkb.vari.cbox linsert end] \ --- 17,49 ---- proc Keyboard_create_widgets { win } { global XKBComponents XKBinserver XKBhandle + global pc98 messages set w [winpathprefix $win] ! if !$pc98 { ! frame $w.keyboard -width 640 -height 420 \ ! -relief ridge -borderwidth 5 ! } else { ! frame $w.keyboard -width 640 -height 400 \ ! -relief ridge -borderwidth 5 ! } frame $w.keyboard.xkb ! label $w.keyboard.xkb.text -text $messages(keyboard.4) frame $w.keyboard.xkb.geom ! label $w.keyboard.xkb.geom.title -text $messages(keyboard.1) combobox $w.keyboard.xkb.geom.cbox -bd 2 -width 30 eval [list $w.keyboard.xkb.geom.cbox linsert end] \ $XKBComponents(models,descriptions) pack $w.keyboard.xkb.geom.title $w.keyboard.xkb.geom.cbox -side top frame $w.keyboard.xkb.lang ! label $w.keyboard.xkb.lang.title -text $messages(keyboard.2) combobox $w.keyboard.xkb.lang.cbox -bd 2 -width 30 eval [list $w.keyboard.xkb.lang.cbox linsert end] \ $XKBComponents(layouts,descriptions) pack $w.keyboard.xkb.lang.title $w.keyboard.xkb.lang.cbox -side top frame $w.keyboard.xkb.vari ! label $w.keyboard.xkb.vari.title -text $messages(keyboard.6) combobox $w.keyboard.xkb.vari.cbox -bd 2 -width 30 $w.keyboard.xkb.vari.cbox linsert end "" eval [list $w.keyboard.xkb.vari.cbox linsert end] \ *************** *** 65,71 **** } pack $w.keyboard.xkb.graphic -side top -expand yes -fill x if { $XKBinserver } { ! button $w.keyboard.xkb.apply -text "Apply" \ -command "Keyboard_loadsettings $win load" pack $w.keyboard.xkb.apply -side top -expand yes -fill both } --- 69,75 ---- } pack $w.keyboard.xkb.graphic -side top -expand yes -fill x if { $XKBinserver } { ! button $w.keyboard.xkb.apply -text $messages(keyboard.3) \ -command "Keyboard_loadsettings $win load" pack $w.keyboard.xkb.apply -side top -expand yes -fill both } *************** *** 80,86 **** } proc Keyboard_create_options_widgets { win } { ! global XKBComponents keyboardXkbOpts set w [winpathprefix $win] set numopts [llength $XKBComponents(options,names)] --- 84,90 ---- } proc Keyboard_create_options_widgets { win } { ! global XKBComponents keyboardXkbOpts messages set w [winpathprefix $win] set numopts [llength $XKBComponents(options,names)] *************** *** 89,95 **** return } ! label $w.keyboard.options.title -text "Available options:" pack $w.keyboard.options.title -fill x \ -expand no -pady 3m -side top frame $w.keyboard.options.line -relief sunken -height 2 -bd 3 --- 93,99 ---- return } ! label $w.keyboard.options.title -text $messages(keyboard.5) pack $w.keyboard.options.title -fill x \ -expand no -pady 3m -side top frame $w.keyboard.options.line -relief sunken -height 2 -bd 3 *************** *** 117,123 **** pack $canv.list.$name -fill both -expand no set tmp [list $name default] set value -1 ! set desc "Use default setting" set keyboardXkbOpts($name) -1 } else { checkbutton $canv.list.$name \ --- 121,127 ---- pack $canv.list.$name -fill both -expand no set tmp [list $name default] set value -1 ! set desc $messages(keyboard.7) set keyboardXkbOpts($name) -1 } else { checkbutton $canv.list.$name \ *************** *** 223,235 **** proc Keyboard_loadsettings { win loadflag } { global XKBComponents XKBrules Keyboard XKBhandle keyboardXkbOpts set w [winpathprefix $win] if { $loadflag == "load" } { ! $w.keyboard.xkb.message configure -text "Applying..." } if { $loadflag == "noload" } { ! $w.keyboard.xkb.message configure -text "Please wait..." } update set geom_idx [$w.keyboard.xkb.geom.cbox curselection] --- 227,240 ---- proc Keyboard_loadsettings { win loadflag } { global XKBComponents XKBrules Keyboard XKBhandle keyboardXkbOpts + global messages set w [winpathprefix $win] if { $loadflag == "load" } { ! $w.keyboard.xkb.message configure -text $messages(keyboard.9) } if { $loadflag == "noload" } { ! $w.keyboard.xkb.message configure -text $messages(keyboard.10) } update set geom_idx [$w.keyboard.xkb.geom.cbox curselection] *************** *** 261,267 **** set notloaded [catch {eval xkb_load $comp $loadflag} kbd] if { $notloaded } { $w.keyboard.xkb.message configure \ ! -text "Failed! Try again" bell after 1000 } else { --- 266,272 ---- set notloaded [catch {eval xkb_load $comp $loadflag} kbd] if { $notloaded } { $w.keyboard.xkb.message configure \ ! -text $messages(keyboard.8) bell after 1000 } else { *************** *** 285,309 **** } focus $w $w.keyboard.xkb.message configure -text "" - } - - proc Keyboard_popup_help { win } { - catch {destroy .keyboardhelp} - toplevel .keyboardhelp -bd 5 -relief ridge - wm title .keyboardhelp "Help" - wm geometry .keyboardhelp +30+30 - text .keyboardhelp.text - .keyboardhelp.text insert 0.0 "\n\n\n\ - First select the model of keyboard that you have (or\ - the closest equivalent).\n\ - The small graphic will automatically be updated.\n\n\ - Next select the layout and any variant or options desired.\n\n\ - Pressing the 'Apply' button will cause the selected\ - settings to take effect." - .keyboardhelp.text configure -state disabled - button .keyboardhelp.ok -text "Dismiss" \ - -command "destroy .keyboardhelp" - focus .keyboardhelp.ok - pack .keyboardhelp.text .keyboardhelp.ok } --- 290,294 ---- *** ./programs/Xserver/hw/xfree86/XF86Setup/main.c@@/PUBLIC-LATEST Sun Aug 10 12:57:14 1997 --- xc/programs/Xserver/hw/xfree86/XF86Setup/main.c Fri Mar 6 16:27:34 1998 *************** *** 1,9 **** ! /* $TOG: main.c /main/4 1997/08/10 12:55:49 kaleb $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/main.c,v 3.9.2.1 1997/07/13 14:45:02 dawes Exp $ */ /* * Copyright 1996 by Joseph V. Moss * --- 1,9 ---- ! /* $TOG: main.c /main/5 1998/03/06 16:29:12 kaleb $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/main.c,v 3.9.2.3 1998/02/24 13:54:11 hohndel Exp $ */ /* * Copyright 1996 by Joseph V. Moss * *************** *** 60,65 **** --- 60,67 ---- static int nodialog = 0; /* Don't use Dialog */ static int notk = 0; /* Don't add Tk to interp */ static int usescriptdir = 0; /* Use script dir, not PATH */ + static Boolean pc98 = FALSE; /* machine architecure */ + static int pc98_EGC = 0; /* default server */ #define PHASE1 "phase1.tcl" #define PHASE2 "phase2.tcl" *************** *** 82,91 **** " set Xwinhome $env(XWINHOME)\n" "} else {\n" " set xdirs [list " PROJECTROOT " /usr/X11R6 /usr/X11 " ! "/usr/X /var/X11R6 /var/X11 /var/X /usr/X11R6.1 " "/usr/local/X11R6 /usr/local/X11 /usr/local/X]\n" " foreach dir $xdirs {\n" ! " if {[llength [glob -nocomplain $dir/bin/XF86_*]] } {\n" " set Xwinhome $dir\n" " break\n" " }\n" --- 84,93 ---- " set Xwinhome $env(XWINHOME)\n" "} else {\n" " set xdirs [list " PROJECTROOT " /usr/X11R6 /usr/X11 " ! "/usr/X /var/X11R6 /var/X11 /var/X /usr/X11R6.3 " "/usr/local/X11R6 /usr/local/X11 /usr/local/X]\n" " foreach dir $xdirs {\n" ! " if {[llength [glob -nocomplain $dir/bin/XF86_* $dir/bin/XF98_*]] } {\n" " set Xwinhome $dir\n" " break\n" " }\n" *************** *** 123,128 **** --- 125,134 ---- "Options always available:\n" " -sync Use synchronous mode for display server\n" " -name Name to use for application\n" + #ifdef PC98 + " -egc Use EGC server\n" + " -pegc Use NEC480 server\n" + #endif "\n" "Options available only when a filename is specified:\n" " -display Display to use\n" *************** *** 150,155 **** --- 156,165 ---- "Don't open a connection to the X server or load Tk widgets"}, {"-script", TK_ARGV_CONSTANT, (char *) 1, (char *) &usescriptdir, "Look for filename in the scripts directory"}, + {"-egc", TK_ARGV_CONSTANT, (char *) 1, (char *) &pc98_EGC, + "Use egc"}, + {"-pegc", TK_ARGV_CONSTANT, (char *) 0, (char *) &pc98_EGC, + "Use pegc"}, {"--", TK_ARGV_REST, (char *) 1, (char *) &rest, "Pass all remaining arguments through to script"}, /* This one is undocumented - it's used when execing a 2nd copy */ *************** *** 410,415 **** --- 420,442 ---- XtFree(tmpptr); Tcl_SetVar(interp, "argc", tmpbuf, TCL_GLOBAL_ONLY); Tcl_SetVar(interp, "argv0", argv0, TCL_GLOBAL_ONLY); + #ifdef PC98 + nodialog = 1; + Tcl_SetVar(interp, "pc98", "1", TCL_GLOBAL_ONLY); + if (pc98_EGC) { + #if defined(linux) || defined(SVR4) + fprintf(stderr, "Sorry, EGC server doesn't work on this OS.\n"); + fprintf(stderr, "-egc option can't be used.\n"); + exit(1); + #endif + Tcl_SetVar(interp, "pc98_EGC", "1", TCL_GLOBAL_ONLY); + } else { + Tcl_SetVar(interp, "pc98_EGC", "0", TCL_GLOBAL_ONLY); + } + #else + Tcl_SetVar(interp, "pc98", "0", TCL_GLOBAL_ONLY); + Tcl_SetVar(interp, "pc98_EGC", "0", TCL_GLOBAL_ONLY); + #endif if (filename == NULL) { Tcl_LinkVar(interp, "Phase2FallBack", *************** *** 608,614 **** --- 635,645 ---- #endif ); + #if TK_MAJOR_VERSION == 8 + extern int TkpInit ( + #else extern int TkPlatformInit ( + #endif #if NeedFunctionProtoTypes Tcl_Interp *interp #endif *************** *** 670,676 **** --- 701,711 ---- Tcl_ResetResult(interp); mainWindow = Tk_MainWindow(interp); + #if TK_MAJOR_VERSION == 8 + TkpInit(interp); + #else TkPlatformInit(interp); + #endif #endif XtFree(class); *** /dev/null Tue Jun 30 11:43:24 1998 --- xc/programs/Xserver/hw/xfree86/XF86Setup/modeselect.tcl Fri Mar 6 16:27:38 1998 *************** *** 0 **** --- 1,203 ---- + # $TOG: modeselect.tcl /main/1 1998/03/06 16:29:16 kaleb $ + # + # + # + # + # $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/modeselect.tcl,v 3.1.2.3 1998/02/21 06:07:00 robin Exp $ + # + # Copyright 1996 by Joseph V. Moss + # 1997 by Dirk H Hohndel + # + # See the file "LICENSE" for information regarding redistribution terms, + # and for a DISCLAIMER OF ALL WARRANTIES. + # + + # + # routines to select the modes that the user actually wants to use + # + + proc Modeselect_create_widgets { win } { + global MonitorIDs monDevNum monCanvas MonitorDescriptions + global pc98_EGC messages + + set w [winpathprefix $win] + + if !$pc98_EGC { + frame $w.modesel -width 640 -height 420 \ + -relief ridge -borderwidth 5 + } else { + frame $w.modesel -width 640 -height 400 \ + -relief ridge -borderwidth 5 + } + frame $w.modesel.top + frame $w.modesel.mid -relief sunken -borderwidth 3 + frame $w.modesel.bot + pack $w.modesel.top -side top + pack $w.modesel.mid -side top -expand yes + pack $w.modesel.bot -side top + + label $w.modesel.top.title -text $messages(modeselect.1) + frame $w.modesel.type + pack $w.modesel.top.title $w.modesel.type -in $w.modesel.top -side top + set canv [canvas $w.modesel.buttons] + + checkbutton $w.modesel.buttons.m640x480 \ + -text $messages(modeselect.2) \ + -indicatoron no -variable m640x480 \ + -command [list modesel_enable $win " 640x480*"] + lappend lbuttons $w.modesel.buttons.m640x480 + checkbutton $w.modesel.buttons.m800x600 \ + -text $messages(modeselect.3) \ + -indicatoron no -variable m800x600 \ + -command [list modesel_enable $win " 800x600*"] + lappend lbuttons $w.modesel.buttons.m800x600 + checkbutton $w.modesel.buttons.m1024x768 \ + -text $messages(modeselect.4) \ + -indicatoron no -variable m1024x768 \ + -command [list modesel_enable $win "1024x768*"] + lappend lbuttons $w.modesel.buttons.m1024x768 + checkbutton $w.modesel.buttons.m1152x864 \ + -text $messages(modeselect.5) \ + -indicatoron no -variable m1152x864 \ + -command [list modesel_enable $win "1152x864*"] + lappend lbuttons $w.modesel.buttons.m1152x864 + checkbutton $w.modesel.buttons.m1280x1024 \ + -text $messages(modeselect.6) \ + -indicatoron no -variable m1280x1024 \ + -command [list modesel_enable $win "1280x1024*"] + lappend lbuttons $w.modesel.buttons.m1280x1024 + checkbutton $w.modesel.buttons.m1600x1200 \ + -text $messages(modeselect.7) \ + -indicatoron no -variable m1600x1200 \ + -command [list modesel_enable $win "1600x1200*"] + lappend lbuttons $w.modesel.buttons.m1600x1200 + checkbutton $w.modesel.buttons.m640x400 \ + -text $messages(modeselect.8) \ + -indicatoron no -variable m640x400 \ + -command [list modesel_enable $win " 640x400*"] + lappend lbuttons $w.modesel.buttons.m640x400 + checkbutton $w.modesel.buttons.m320x200 \ + -text $messages(modeselect.9) \ + -indicatoron no -variable m320x200 \ + -command [list modesel_enable $win " 320x200*"] + lappend lbuttons $w.modesel.buttons.m320x200 + checkbutton $w.modesel.buttons.m320x240 \ + -text $messages(modeselect.10) \ + -indicatoron no -variable m320x240 \ + -command [list modesel_enable $win " 320x240*"] + lappend lbuttons $w.modesel.buttons.m320x240 + checkbutton $w.modesel.buttons.m400x300 \ + -text $messages(modeselect.11) \ + -indicatoron no -variable m400x300 \ + -command [list modesel_enable $win " 400x300*"] + lappend lbuttons $w.modesel.buttons.m400x300 + checkbutton $w.modesel.buttons.m480x300 \ + -text $messages(modeselect.12) \ + -indicatoron no -variable m480x300 \ + -command [list modesel_enable $win " 480x300*"] + lappend lbuttons $w.modesel.buttons.m480x300 + checkbutton $w.modesel.buttons.m512x384 \ + -text $messages(modeselect.13) \ + -indicatoron no -variable m512x384 \ + -command [list modesel_enable $win " 512x384*"] + lappend lbuttons $w.modesel.buttons.m512x384 + set ht 0 + set wd 0 + foreach wb $lbuttons { + set bwd [winfo reqwidth $wb] + if {$wd < $bwd} {set wd $bwd} + } + foreach wb $lbuttons { + $canv create window \ + [expr ($wd-[winfo reqwidth $wb])/2] $ht \ + -anchor nw -window $wb + set ht [expr $ht + [winfo reqheight $wb]] + } + $canv configure -yscrollcommand [list $w.modesel.sb set] \ + -scrollregion [list 0 0 $wd $ht] \ + -width $wd + scrollbar $w.modesel.sb \ + -command [list $canv yview] + pack $canv -in $w.modesel.mid \ + -side left -fill both -expand yes -pady 2m + pack $w.modesel.sb -in $w.modesel.mid -side right \ + -fill y -expand yes + frame $w.modesel.dcd + label $w.modesel.dcd.title -text $messages(modeselect.14) + radiobutton $w.modesel.8bpp -text $messages(modeselect.15) \ + -indicatoron false -variable ColorDepth \ + -value "depth8" -underline 19 \ + -command [list modesel_color_select $w 8] + radiobutton $w.modesel.16bpp -text $messages(modeselect.16) \ + -indicatoron false -variable ColorDepth \ + -value "depth16" -underline 19 \ + -command [list modesel_color_select $w 16] + radiobutton $w.modesel.24bpp -text $messages(modeselect.17) \ + -indicatoron false -variable ColorDepth \ + -value "depth24" -underline 19 \ + -command [list modesel_color_select $w 24] + radiobutton $w.modesel.32bpp -text $messages(modeselect.18) \ + -indicatoron false -variable ColorDepth \ + -value "depth32" -underline 19 \ + -command [list modesel_color_select $w 32] + pack $w.modesel.8bpp $w.modesel.16bpp $w.modesel.24bpp \ + $w.modesel.32bpp -side left -fill x -expand yes \ + -in $w.modesel.dcd + pack $w.modesel.dcd.title $w.modesel.dcd -side left -fill y -expand yes + } + + proc Modeselection_activate { win } { + set w [winpathprefix $win] + pack $w.modesel -side top -fill both -expand yes + } + + proc Modeselection_deactivate { win } { + set w [winpathprefix $win] + pack forget $w.modesel + + } + + proc modesel_color_select { win val } { + global DefaultColorDepth + + set w [winpathprefix $win] + + set DefaultColorDepth $val + } + + proc modesel_enable { win val } { + global MonitorStdModes SelectedMonitorModes haveSelectedModes + + set w [winpathprefix $win] + + set haveSelectedModes 1 + + # we need to handle the fact that these are toggle buttons, so every + # other time this is selected, the user actually wants to deselect + # the entries + # this would be much easier if I have a way to remove pairs from an array... + if { [array get SelectedMonitorModes $val] != "" } { + # puts stderr "$val already existed" + # + foreach desc [array names SelectedMonitorModes $val] { + if [string match \#removed $SelectedMonitorModes($desc)] { + # ok, we're enabling again + set SelectedMonitorModes($desc) $MonitorStdModes($desc) + } else { + # puts stderr "invalidating for $desc" + set SelectedMonitorModes($desc) "#removed" + } + } + } else { + # puts stderr "add $val to selected modes" + foreach desc [array names MonitorStdModes $val] { + set modeline $MonitorStdModes($desc) + # puts stderr "$desc :: $modeline" + set SelectedMonitorModes($desc) $modeline + } + } + # foreach desc [array names SelectedMonitorModes] { + # puts stderr "$desc -> $SelectedMonitorModes($desc)" + # } + } + *** ./programs/Xserver/hw/xfree86/XF86Setup/mondata.tcl@@/PUBLIC-LATEST Sat Jul 19 09:22:51 1997 --- xc/programs/Xserver/hw/xfree86/XF86Setup/mondata.tcl Fri Mar 6 16:27:42 1998 *************** *** 1,9 **** ! # $TOG: mondata.tcl /main/5 1997/07/19 09:22:52 kaleb $ # # # # ! # $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/mondata.tcl,v 3.8.2.2 1997/05/12 12:52:18 hohndel Exp $ # # Copyright 1996 by Joseph V. Moss # --- 1,9 ---- ! # $TOG: mondata.tcl /main/6 1998/03/06 16:29:20 kaleb $ # # # # ! # $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/mondata.tcl,v 3.8.2.4 1998/02/15 16:08:53 hohndel Exp $ # # Copyright 1996 by Joseph V. Moss # *************** *** 54,60 **** --- 54,68 ---- "Multi-frequency that can do 1280x1024 @ 76 Hz" \ ] + set haveSelectedModes 0 + + set DefaultColorDepth 8 + + array set SelectedMonitorModes { } + array set MonitorStdModes { + " 640x400 @ pc98 EGC mode : 60 Hz, 24 kHz hsync" + "16.442 640 649 656 663 400 407 415 440" " 640x400 @ 70 Hz, 31.5 kHz hsync" "25.175 640 664 760 800 400 409 411 450" " 640x480 @ 60 Hz, 31.5 kHz hsync" *************** *** 85,91 **** "45.8 640 672 768 864 480 488 494 530 -HSync -VSync" "1152x864 @ 60 Hz, 53.5 kHz hsync" "89.9 1152 1216 1472 1680 864 868 876 892 -HSync -VSync" ! "800x600 @ 85 Hz, 55.84 kHz hsync" "60.75 800 864 928 1088 600 616 621 657 -HSync -VSync" "1024x768 @ 70 Hz, 56.5 kHz hsync" "75 1024 1048 1184 1328 768 771 777 806 -hsync -vsync" --- 93,99 ---- "45.8 640 672 768 864 480 488 494 530 -HSync -VSync" "1152x864 @ 60 Hz, 53.5 kHz hsync" "89.9 1152 1216 1472 1680 864 868 876 892 -HSync -VSync" ! " 800x600 @ 85 Hz, 55.84 kHz hsync" "60.75 800 864 928 1088 600 616 621 657 -HSync -VSync" "1024x768 @ 70 Hz, 56.5 kHz hsync" "75 1024 1048 1184 1328 768 771 777 806 -hsync -vsync" *************** *** 95,101 **** "85 1024 1032 1152 1360 768 784 787 823" "1152x864 @ 70 Hz, 62.4 kHz hsync" "92 1152 1208 1368 1474 864 865 875 895" ! "800x600 @ 100 Hz, 64.02 kHz hsync" "69.650 800 864 928 1088 600 604 610 640 -HSync -VSync" "1024x768 @ 85 Hz, 70.24 kHz hsync" "98.9 1024 1056 1216 1408 768 782 788 822 -HSync -VSync" --- 103,109 ---- "85 1024 1032 1152 1360 768 784 787 823" "1152x864 @ 70 Hz, 62.4 kHz hsync" "92 1152 1208 1368 1474 864 865 875 895" ! " 800x600 @ 100 Hz, 64.02 kHz hsync" "69.650 800 864 928 1088 600 604 610 640 -HSync -VSync" "1024x768 @ 85 Hz, 70.24 kHz hsync" "98.9 1024 1056 1216 1408 768 782 788 822 -HSync -VSync" *************** *** 131,159 **** "230 1800 1896 2088 2392 1440 1441 1444 1490 +HSync +VSync" "1800x1440 @ 70Hz, 104.52 kHz hsync" "250 1800 1896 2088 2392 1440 1441 1444 1490 +HSync +VSync" ! "320x200 @ 70 Hz, 31.5 kHz hsync, 8:5 aspect ratio" "12.588 320 336 384 400 200 204 205 225 Doublescan" ! "320x240 @ 60 Hz, 31.5 kHz hsync, 4:3 aspect ratio" "12.588 320 336 384 400 240 245 246 262 Doublescan" ! "320x240 @ 72 Hz, 36.5 kHz hsync" "15.750 320 336 384 400 240 244 246 262 Doublescan" ! "400x300 @ 56 Hz, 35.2 kHz hsync, 4:3 aspect ratio" "18 400 416 448 512 300 301 302 312 Doublescan" ! "400x300 @ 60 Hz, 37.8 kHz hsync" "20 400 416 480 528 300 301 303 314 Doublescan" ! "400x300 @ 72 Hz, 48.0 kHz hsync" "25 400 424 488 520 300 319 322 333 Doublescan" ! "480x300 @ 56 Hz, 35.2 kHz hsync, 8:5 aspect ratio" "21.656 480 496 536 616 300 301 302 312 Doublescan" ! "480x300 @ 60 Hz, 37.8 kHz hsync" "23.890 480 496 576 632 300 301 303 314 Doublescan" ! "480x300 @ 63 Hz, 39.6 kHz hsync" "25 480 496 576 632 300 301 303 314 Doublescan" ! "480x300 @ 72 Hz, 48.0 kHz hsync" "29.952 480 504 584 624 300 319 322 333 Doublescan" ! "512x384 @ 78 Hz, 31.50 kHz hsync" "20.160 512 528 592 640 384 385 388 404 -HSync -VSync" ! "512x384 @ 85 Hz, 34.38 kHz hsync" "22 512 528 592 640 384 385 388 404 -HSync -VSync" } --- 139,167 ---- "230 1800 1896 2088 2392 1440 1441 1444 1490 +HSync +VSync" "1800x1440 @ 70Hz, 104.52 kHz hsync" "250 1800 1896 2088 2392 1440 1441 1444 1490 +HSync +VSync" ! " 320x200 @ 70 Hz, 31.5 kHz hsync, 8:5 aspect ratio" "12.588 320 336 384 400 200 204 205 225 Doublescan" ! " 320x240 @ 60 Hz, 31.5 kHz hsync, 4:3 aspect ratio" "12.588 320 336 384 400 240 245 246 262 Doublescan" ! " 320x240 @ 72 Hz, 36.5 kHz hsync" "15.750 320 336 384 400 240 244 246 262 Doublescan" ! " 400x300 @ 56 Hz, 35.2 kHz hsync, 4:3 aspect ratio" "18 400 416 448 512 300 301 302 312 Doublescan" ! " 400x300 @ 60 Hz, 37.8 kHz hsync" "20 400 416 480 528 300 301 303 314 Doublescan" ! " 400x300 @ 72 Hz, 48.0 kHz hsync" "25 400 424 488 520 300 319 322 333 Doublescan" ! " 480x300 @ 56 Hz, 35.2 kHz hsync, 8:5 aspect ratio" "21.656 480 496 536 616 300 301 302 312 Doublescan" ! " 480x300 @ 60 Hz, 37.8 kHz hsync" "23.890 480 496 576 632 300 301 303 314 Doublescan" ! " 480x300 @ 63 Hz, 39.6 kHz hsync" "25 480 496 576 632 300 301 303 314 Doublescan" ! " 480x300 @ 72 Hz, 48.0 kHz hsync" "29.952 480 504 584 624 300 319 322 333 Doublescan" ! " 512x384 @ 78 Hz, 31.50 kHz hsync" "20.160 512 528 592 640 384 385 388 404 -HSync -VSync" ! " 512x384 @ 85 Hz, 34.38 kHz hsync" "22 512 528 592 640 384 385 388 404 -HSync -VSync" } *** ./programs/Xserver/hw/xfree86/XF86Setup/monitor.tcl@@/PUBLIC-LATEST Sat Jul 19 09:22:56 1997 --- xc/programs/Xserver/hw/xfree86/XF86Setup/monitor.tcl Fri Mar 6 16:27:47 1998 *************** *** 1,9 **** ! # $TOG: monitor.tcl /main/3 1997/07/19 09:22:57 kaleb $ # # # # ! # $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/monitor.tcl,v 3.9 1996/12/27 06:54:07 dawes Exp $ # # Copyright 1996 by Joseph V. Moss # --- 1,9 ---- ! # $TOG: monitor.tcl /main/4 1998/03/06 16:29:24 kaleb $ # # # # ! # $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/monitor.tcl,v 3.9.2.2 1998/02/21 06:07:00 robin Exp $ # # Copyright 1996 by Joseph V. Moss # *************** *** 17,27 **** proc Monitor_create_widgets { win } { global MonitorIDs monDevNum monCanvas MonitorDescriptions set w [winpathprefix $win] set monDevNum 0 ! frame $w.monitor -width 640 -height 420 \ ! -relief ridge -borderwidth 5 frame $w.monitor.sync pack $w.monitor.sync -side top -pady 1m --- 17,33 ---- proc Monitor_create_widgets { win } { global MonitorIDs monDevNum monCanvas MonitorDescriptions + global pc98_EGC messages set w [winpathprefix $win] set monDevNum 0 ! if !$pc98_EGC { ! frame $w.monitor -width 640 -height 420 \ ! -relief ridge -borderwidth 5 ! } else { ! frame $w.monitor -width 640 -height 400 \ ! -relief ridge -borderwidth 5 ! } frame $w.monitor.sync pack $w.monitor.sync -side top -pady 1m *************** *** 28,38 **** frame $w.monitor.sync.line1 pack $w.monitor.sync.line1 -side top -fill x -expand yes ! label $w.monitor.sync.title -text "Monitor sync rates" pack $w.monitor.sync.title -side left -fill x \ -in $w.monitor.sync.line1 -expand yes if { [llength $MonitorIDs] > 1 } { ! label $w.monitor.sync.monsel -text "Monitor selected:" -anchor w pack $w.monitor.sync.monsel -side left \ -in $w.monitor.sync.line1 combobox $w.monitor.sync.monselect -state disabled -bd 2 --- 34,45 ---- frame $w.monitor.sync.line1 pack $w.monitor.sync.line1 -side top -fill x -expand yes ! label $w.monitor.sync.title -text $messages(monitor.1) pack $w.monitor.sync.title -side left -fill x \ -in $w.monitor.sync.line1 -expand yes if { [llength $MonitorIDs] > 1 } { ! label $w.monitor.sync.monsel \ ! -text $messages(monitor.2) -anchor w pack $w.monitor.sync.monsel -side left \ -in $w.monitor.sync.line1 combobox $w.monitor.sync.monselect -state disabled -bd 2 *************** *** 47,53 **** } frame $w.monitor.sync.horz pack $w.monitor.sync.horz -side left -padx 10m ! label $w.monitor.sync.horz.title -text "Horizontal" entry $w.monitor.sync.horz.entry -width 35 -bd 2 pack $w.monitor.sync.horz.title -side left pack $w.monitor.sync.horz.entry -side left --- 54,60 ---- } frame $w.monitor.sync.horz pack $w.monitor.sync.horz -side left -padx 10m ! label $w.monitor.sync.horz.title -text $messages(monitor.3) entry $w.monitor.sync.horz.entry -width 35 -bd 2 pack $w.monitor.sync.horz.title -side left pack $w.monitor.sync.horz.entry -side left *************** *** 54,60 **** frame $w.monitor.sync.vert pack $w.monitor.sync.vert -side left -padx 10m ! label $w.monitor.sync.vert.title -text "Vertical" entry $w.monitor.sync.vert.entry -width 35 -bd 2 pack $w.monitor.sync.vert.title -side left pack $w.monitor.sync.vert.entry -side left --- 61,67 ---- frame $w.monitor.sync.vert pack $w.monitor.sync.vert -side left -padx 10m ! label $w.monitor.sync.vert.title -text $messages(monitor.4) entry $w.monitor.sync.vert.entry -width 35 -bd 2 pack $w.monitor.sync.vert.title -side left pack $w.monitor.sync.vert.entry -side left *************** *** 61,68 **** set canv $w.monitor.canvas set monCanvas $canv ! canvas $canv -width 600 -height 330 -highlightthickness 0 \ ! -takefocus 0 -relief sunken -borderwidth 2 pack $canv -side top -fill x frame $canv.list --- 68,80 ---- set canv $w.monitor.canvas set monCanvas $canv ! if !$pc98_EGC { ! canvas $canv -width 600 -height 330 -highlightthickness 0 \ ! -takefocus 0 -relief sunken -borderwidth 2 ! } else { ! canvas $canv -width 600 -height 250 -highlightthickness 0 \ ! -takefocus 0 -relief sunken -borderwidth 2 ! } pack $canv -side top -fill x frame $canv.list *************** *** 69,76 **** listbox $canv.list.lb -height 10 -width 55 -setgrid true \ -yscroll [list $canv.list.sb set] scrollbar $canv.list.sb -command [list $canv.list.lb yview] ! pack $canv.list.lb -side left -fill y ! #pack $canv.list.sb -side left -fill y eval [list $canv.list.lb insert end] $MonitorDescriptions bind $canv.list.lb \ [list Monitor_setstandard $win $canv] --- 81,94 ---- listbox $canv.list.lb -height 10 -width 55 -setgrid true \ -yscroll [list $canv.list.sb set] scrollbar $canv.list.sb -command [list $canv.list.lb yview] ! if !$pc98_EGC { ! pack $canv.list.lb -side left -fill y ! #pack $canv.list.sb -side left -fill y ! } else { ! $canv.list.lb configure -height 5 ! pack $canv.list.lb -side left -fill y ! pack $canv.list.sb -side left -fill y ! } eval [list $canv.list.lb insert end] $MonitorDescriptions bind $canv.list.lb \ [list Monitor_setstandard $win $canv] *************** *** 77,116 **** bind $canv.list.lb \ [list Monitor_setstandard $win $canv] ! $canv create rectangle 150 55 550 305 -fill cyan ! $canv create rectangle 160 70 540 280 -fill grey ! $canv create rectangle 170 80 530 270 -fill blue ! $canv create arc 170 76 530 84 -fill blue \ ! -start 0 -extent 180 -style chord -outline blue ! $canv create arc 170 266 530 274 -fill blue \ ! -start 0 -extent -180 -style chord -outline blue ! $canv create arc 166 80 174 270 -fill blue \ ! -start 90 -extent 180 -style chord -outline blue ! $canv create arc 526 80 534 270 -fill blue \ ! -start 90 -extent -180 -style chord -outline blue ! $canv create line 160 70 170 80 ! $canv create line 540 70 530 80 ! $canv create line 540 280 530 270 ! $canv create line 160 280 170 270 ! $canv create rectangle 320 305 380 315 -fill cyan ! $canv create rectangle 285 315 415 320 -fill cyan ! $canv create window 350 175 -window $canv.list ! $canv create rectangle 120 30 570 45 -fill white -tag hsync ! for {set i 20} {$i<=110} {incr i 10} { $canv create text [expr $i*5+20] 22 -text $i } - $canv create rectangle 50 30 65 305 -fill white -tag vsync - for {set i 40} {$i<=150} {incr i 10} { - $canv create text 35 [expr $i*2.5-70] -text $i -anchor e - } - frame $w.monitor.bot ! label $w.monitor.bot.message -text \ ! "Enter the Horizontal and Vertical Sync ranges for your monitor\n\ ! or if you do not have that information, choose from the list" pack $w.monitor.bot -side top pack $w.monitor.bot.message --- 95,164 ---- bind $canv.list.lb \ [list Monitor_setstandard $win $canv] ! if !$pc98_EGC { ! $canv create rectangle 150 55 550 305 -fill cyan ! $canv create rectangle 160 70 540 280 -fill grey ! $canv create rectangle 170 80 530 270 -fill blue ! $canv create arc 170 76 530 84 -fill blue \ ! -start 0 -extent 180 -style chord -outline blue ! $canv create arc 170 266 530 274 -fill blue \ ! -start 0 -extent -180 -style chord -outline blue ! $canv create arc 166 80 174 270 -fill blue \ ! -start 90 -extent 180 -style chord -outline blue ! $canv create arc 526 80 534 270 -fill blue \ ! -start 90 -extent -180 -style chord -outline blue ! $canv create line 160 70 170 80 ! $canv create line 540 70 530 80 ! $canv create line 540 280 530 270 ! $canv create line 160 280 170 270 ! $canv create rectangle 320 305 380 315 -fill cyan ! $canv create rectangle 285 315 415 320 -fill cyan ! $canv create window 350 175 -window $canv.list ! $canv create rectangle 120 30 570 45 -fill white -tag hsync ! for {set i 20} {$i<=110} {incr i 10} { ! $canv create text [expr $i*5+20] 22 -text $i ! } ! ! $canv create rectangle 50 30 65 305 -fill white -tag vsync ! for {set i 40} {$i<=150} {incr i 10} { ! $canv create text 35 [expr $i*2.5-70] -text $i -anchor e ! } ! } else { ! $canv create rectangle 150 55 550 225 -fill cyan ! $canv create rectangle 160 70 540 200 -fill grey ! $canv create rectangle 170 80 530 190 -fill blue ! $canv create arc 170 76 530 84 -fill blue \ ! -start 0 -extent 180 -style chord -outline blue ! $canv create arc 170 186 530 194 -fill blue \ ! -start 0 -extent -180 -style chord -outline blue ! $canv create arc 166 80 174 190 -fill blue \ ! -start 90 -extent 180 -style chord -outline blue ! $canv create arc 526 80 534 190 -fill blue \ ! -start 90 -extent -180 -style chord -outline blue ! $canv create line 160 70 170 80 ! $canv create line 540 70 530 80 ! $canv create line 540 200 530 190 ! $canv create line 160 200 170 190 ! $canv create rectangle 320 225 380 235 -fill cyan ! $canv create rectangle 285 235 415 240 -fill cyan ! ! $canv create window 350 135 -window $canv.list ! ! $canv create rectangle 120 30 570 45 -fill white -tag hsync ! for {set i 20} {$i<=110} {incr i 10} { $canv create text [expr $i*5+20] 22 -text $i + } + + $canv create rectangle 50 30 65 225 -fill white -tag vsync + for {set i 40} {$i<=150} {incr i 10} { + $canv create text 35 [expr $i*1.7-38] -text $i -anchor e + } } frame $w.monitor.bot ! label $w.monitor.bot.message -text $messages(monitor.5) pack $w.monitor.bot -side top pack $w.monitor.bot.message *************** *** 204,232 **** } } - proc Monitor_popup_help { win } { - catch {destroy .monitorhelp} - toplevel .monitorhelp -bd 5 -relief ridge - wm title .monitorhelp "Help" - wm geometry .monitorhelp +30+30 - text .monitorhelp.text - .monitorhelp.text insert 0.0 "\n\n\n\ - Enter the horizontal and vertical sync rates of your\n\ - monitor. These should be listed in your manual.\n\n\ - If you can not find this information, you can pick from the\n\ - the list of common monitor capabilities, the one that best\n\ - describes your monitor, and the appropriate sync rates\n\ - will be filled in for you.\n\n\ - It is very important that these values be correct!\n\n\ - Using video modes that require sync rates beyond the\n\ - capabilities of your monitor may damage it.\n\ - The server will automatically exclude any video modes\n\ - that require sync rates beyond those you enter." - .monitorhelp.text configure -state disabled - button .monitorhelp.ok -text "Dismiss" -command "destroy .monitorhelp" - pack .monitorhelp.text .monitorhelp.ok - } - proc Monitor_setstandard { win c } { global MonitorHsyncRanges MonitorVsyncRanges --- 252,257 ---- *************** *** 243,248 **** --- 268,274 ---- proc Monitor_sync_ent { win c dir } { global tk_version + global pc98_EGC set w [winpathprefix $win] if { [string compare $dir horz] == 0 } { *************** *** 256,264 **** set min 40.0 set max 150.0 set x1 50 - set y1 {$beg*2.5-70} set x2 65 ! set y2 {$end*2.5-70} } set rng [zap_white [$w get]] set rnglist [split $rng ,] --- 282,295 ---- set min 40.0 set max 150.0 set x1 50 set x2 65 ! if !$pc98_EGC { ! set y1 {$beg*2.5-70} ! set y2 {$end*2.5-70} ! } else { ! set y1 {$beg*1.7-38} ! set y2 {$end*1.7-38} ! } } set rng [zap_white [$w get]] set rnglist [split $rng ,] *** ./programs/Xserver/hw/xfree86/XF86Setup/mouse.tcl@@/PUBLIC-LATEST Sat Jul 19 09:23:00 1997 --- xc/programs/Xserver/hw/xfree86/XF86Setup/mouse.tcl Fri Mar 6 16:27:51 1998 *************** *** 1,9 **** ! # $TOG: mouse.tcl /main/7 1997/07/19 09:23:02 kaleb $ # # # # ! # $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/mouse.tcl,v 3.19.2.2 1997/05/21 15:02:28 dawes Exp $ # # Copyright 1996 by Joseph V. Moss # --- 1,9 ---- ! # $TOG: mouse.tcl /main/8 1998/03/06 16:29:29 kaleb $ # # # # ! # $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/mouse.tcl,v 3.19.2.9 1998/02/28 04:47:06 dawes Exp $ # # Copyright 1996 by Joseph V. Moss # *************** *** 15,25 **** # Mouse configuration routines # ! set mseTypeList { Microsoft MouseSystems MMSeries Logitech BusMouse ! MouseMan PS/2 MMHitTab GlidePoint IntelliMouse Xqueue OSMouse } set msePatterns [list {tty[0-9A-Za-o]*} cua* *bm *mse* *mouse* \ ! ps*x psm* m320 pms* com* gpmdata ] set mseDevices "" foreach pat $msePatterns { if ![catch {glob /dev/$pat}] { --- 15,24 ---- # Mouse configuration routines # ! set mseTypeList [concat $SupportedMouseTypes { Xqueue OSMouse } ] set msePatterns [list {tty[0-9A-Za-o]*} cua* *bm *mse* *mouse* \ ! ps*x psm* m320 pms* com* gpmdata lms* kdmouse logi msm] set mseDevices "" foreach pat $msePatterns { if ![catch {glob /dev/$pat}] { *************** *** 33,45 **** proc Mouse_proto_select { win } { global mseType baudRate chordMiddle clearDTR clearRTS sampleRate ! global mseDeviceSelected set w [winpathprefix $win] set canv $w.mouse.mid.right.canvas $canv itemconfigure mbut -fill white $canv itemconfigure coord -fill black ! if {[lsearch -exact {BusMouse Xqueue OSMouse PS/2} $mseType] == -1} { foreach rate {1200 2400 4800 9600} { $w.mouse.brate.$rate configure -state normal } --- 32,47 ---- proc Mouse_proto_select { win } { global mseType baudRate chordMiddle clearDTR clearRTS sampleRate ! global mseRes mseButtons mseDeviceSelected messages set w [winpathprefix $win] set canv $w.mouse.mid.right.canvas $canv itemconfigure mbut -fill white $canv itemconfigure coord -fill black ! if {[lsearch -exact {BusMouse Xqueue OSMouse PS/2 IMPS/2 ! ThinkingMousePS/2 MouseManPlusPS/2 GlidePointPS/2 ! NetMousePS/2 NetScrollPS/2 SysMouse} \ ! $mseType] == -1} { foreach rate {1200 2400 4800 9600} { $w.mouse.brate.$rate configure -state normal } *************** *** 56,71 **** } } if { ![string compare MMHitTab $mseType] } { ! $w.mouse.srate.title configure -text "Lines/inch" $w.mouse.srate.scale configure -to 1200 -tickinterval 200 \ -resolution 20 $w.mouse.srate.scale configure -state normal } else { ! $w.mouse.srate.title configure -text "Sample Rate" $w.mouse.srate.scale configure -to 150 -tickinterval 25 \ -resolution 1 if {[lsearch -exact \ ! {MouseMan BusMouse Xqueue OSMouse PS/2} \ $mseType] == -1} { $w.mouse.srate.scale configure -state normal } else { --- 58,73 ---- } } if { ![string compare MMHitTab $mseType] } { ! $w.mouse.srate.title configure -text $messages(mouse.1) $w.mouse.srate.scale configure -to 1200 -tickinterval 200 \ -resolution 20 $w.mouse.srate.scale configure -state normal } else { ! $w.mouse.srate.title configure -text $messages(mouse.2) $w.mouse.srate.scale configure -to 150 -tickinterval 25 \ -resolution 1 if {[lsearch -exact \ ! {MouseMan BusMouse Xqueue OSMouse} \ $mseType] == -1} { $w.mouse.srate.scale configure -state normal } else { *************** *** 99,108 **** proc Mouse_create_widgets { win } { global mseType mseDevices baudRate sampleRate mseTypeList clearDTR global emulate3Buttons emulate3Timeout chordMiddle clearRTS set w [winpathprefix $win] ! frame $w.mouse -width 640 -height 420 \ ! -relief ridge -borderwidth 5 frame $w.mouse.top frame $w.mouse.mid -relief sunken -borderwidth 3 frame $w.mouse.bot --- 101,116 ---- proc Mouse_create_widgets { win } { global mseType mseDevices baudRate sampleRate mseTypeList clearDTR global emulate3Buttons emulate3Timeout chordMiddle clearRTS + global pc98_EGC mseRes mseButtons messages set w [winpathprefix $win] ! if !$pc98_EGC { ! frame $w.mouse -width 640 -height 420 \ ! -relief ridge -borderwidth 5 ! } else { ! frame $w.mouse -width 640 -height 400 \ ! -relief ridge -borderwidth 5 ! } frame $w.mouse.top frame $w.mouse.mid -relief sunken -borderwidth 3 frame $w.mouse.bot *************** *** 110,116 **** pack $w.mouse.mid -side top -fill x -expand yes pack $w.mouse.bot -side top ! label $w.mouse.top.title -text "Select the mouse protocol" frame $w.mouse.type pack $w.mouse.top.title $w.mouse.type -in $w.mouse.top -side top set i 0 --- 118,124 ---- pack $w.mouse.mid -side top -fill x -expand yes pack $w.mouse.bot -side top ! label $w.mouse.top.title -text $messages(mouse.3) frame $w.mouse.type pack $w.mouse.top.title $w.mouse.type -in $w.mouse.top -side top set i 0 *************** *** 117,123 **** foreach Type $mseTypeList { set type [string tolower $Type] radiobutton $w.mouse.type.$type -text $Type \ ! -width 12 \ -indicatoron false \ -variable mseType -value $Type \ -highlightthickness 1 \ --- 125,131 ---- foreach Type $mseTypeList { set type [string tolower $Type] radiobutton $w.mouse.type.$type -text $Type \ ! -width 16 \ -indicatoron false \ -variable mseType -value $Type \ -highlightthickness 1 \ *************** *** 132,145 **** frame $w.mouse.device pack $w.mouse.device -in $w.mouse.mid.left -side top \ -pady 3m -padx 3m ! label $w.mouse.device.title -text "Mouse Device" entry $w.mouse.device.entry -bd 2 bind $w.mouse.device.entry \ "[list Mouse_setlistbox $win $w.mouse.device.list.lb]; \ focus $w.mouse.em3but" frame $w.mouse.device.list ! listbox $w.mouse.device.list.lb -height 3 \ ! -yscroll [list $w.mouse.device.list.sb set] eval [list $w.mouse.device.list.lb insert end] $mseDevices bind $w.mouse.device.list.lb \ "[list Mouse_setentry $win $w.mouse.device.list.lb]; \ --- 140,158 ---- frame $w.mouse.device pack $w.mouse.device -in $w.mouse.mid.left -side top \ -pady 3m -padx 3m ! label $w.mouse.device.title -text $messages(mouse.5) entry $w.mouse.device.entry -bd 2 bind $w.mouse.device.entry \ "[list Mouse_setlistbox $win $w.mouse.device.list.lb]; \ focus $w.mouse.em3but" frame $w.mouse.device.list ! if !$pc98_EGC { ! listbox $w.mouse.device.list.lb -height 6 \ ! -yscroll [list $w.mouse.device.list.sb set] ! } else { ! listbox $w.mouse.device.list.lb -height 4 \ ! -yscroll [list $w.mouse.device.list.sb set] ! } eval [list $w.mouse.device.list.lb insert end] $mseDevices bind $w.mouse.device.list.lb \ "[list Mouse_setentry $win $w.mouse.device.list.lb]; \ *************** *** 158,175 **** frame $w.mouse.mid.left.buttons pack $w.mouse.mid.left.buttons -in $w.mouse.mid.left \ -side top -fill x -pady 2m ! checkbutton $w.mouse.em3but -text Emulate3Buttons \ -indicatoron no -variable emulate3Buttons \ -command [list Mouse_set_em3but $win] ! checkbutton $w.mouse.chdmid -text ChordMiddle \ -indicatoron no -variable chordMiddle \ -command [list Mouse_set_chdmid $win] pack $w.mouse.em3but $w.mouse.chdmid -in $w.mouse.mid.left.buttons \ -side top -fill x -padx 3m -anchor w frame $w.mouse.brate ! pack $w.mouse.brate -in $w.mouse.mid.left -side top -pady 2m ! label $w.mouse.brate.title -text "Baud Rate" pack $w.mouse.brate.title -side top frame $w.mouse.brate.left frame $w.mouse.brate.right --- 171,214 ---- frame $w.mouse.mid.left.buttons pack $w.mouse.mid.left.buttons -in $w.mouse.mid.left \ -side top -fill x -pady 2m ! checkbutton $w.mouse.em3but -text $messages(mouse.6) \ -indicatoron no -variable emulate3Buttons \ -command [list Mouse_set_em3but $win] ! checkbutton $w.mouse.chdmid -text $messages(mouse.7) \ -indicatoron no -variable chordMiddle \ -command [list Mouse_set_chdmid $win] pack $w.mouse.em3but $w.mouse.chdmid -in $w.mouse.mid.left.buttons \ -side top -fill x -padx 3m -anchor w + frame $w.mouse.resolution + pack $w.mouse.resolution -in $w.mouse.mid.left -side top -pady 2m + label $w.mouse.resolution.title -text $messages(mouse.19) + pack $w.mouse.resolution.title -side top + frame $w.mouse.resolution.left + frame $w.mouse.resolution.mid + frame $w.mouse.resolution.right + pack $w.mouse.resolution.left $w.mouse.resolution.mid \ + $w.mouse.resolution.right -side left -expand yes -fill x + radiobutton $w.mouse.resolution.200 -text $messages(mouse.20) \ + -variable mseRes -value 200 + pack $w.mouse.resolution.200 -side top -fill x -anchor w \ + -in $w.mouse.resolution.left + radiobutton $w.mouse.resolution.100 -text $messages(mouse.21) \ + -variable mseRes -value 100 + pack $w.mouse.resolution.100 -side top -fill x -anchor w \ + -in $w.mouse.resolution.mid + radiobutton $w.mouse.resolution.50 -text $messages(mouse.22) \ + -variable mseRes -value 50 + pack $w.mouse.resolution.50 -side top -fill x -anchor w \ + -in $w.mouse.resolution.right + + frame $w.mouse.mid.mid + pack $w.mouse.mid.mid -side left -fill x -fill y + frame $w.mouse.brate ! # pack $w.mouse.brate -in $w.mouse.mid.left -side top -pady 2m ! pack $w.mouse.brate -in $w.mouse.mid.mid -side top -pady 2m ! label $w.mouse.brate.title -text $messages(mouse.8) pack $w.mouse.brate.title -side top frame $w.mouse.brate.left frame $w.mouse.brate.right *************** *** 183,201 **** } frame $w.mouse.flags ! pack $w.mouse.flags -in $w.mouse.mid.left -side top \ -fill x -pady 3m ! label $w.mouse.flags.title -text Flags ! checkbutton $w.mouse.flags.dtr -text ClearDTR \ ! -indicatoron no -variable clearDTR ! checkbutton $w.mouse.flags.rts -text ClearRTS \ ! -indicatoron no -variable clearRTS pack $w.mouse.flags.title $w.mouse.flags.dtr $w.mouse.flags.rts \ -side top -fill x -padx 3m -anchor w frame $w.mouse.srate pack $w.mouse.srate -in $w.mouse.mid -side left -fill y -expand yes ! label $w.mouse.srate.title -text "Sample Rate" scale $w.mouse.srate.scale -orient vertical -from 0 -to 150 \ -tickinterval 25 -variable sampleRate -state disabled pack $w.mouse.srate.title -side top --- 222,263 ---- } frame $w.mouse.flags ! pack $w.mouse.flags -in $w.mouse.mid.mid -side top \ -fill x -pady 3m ! label $w.mouse.flags.title -text $messages(mouse.10) ! checkbutton $w.mouse.flags.dtr -text $messages(mouse.11) \ ! -width 14 -indicatoron no -variable clearDTR ! checkbutton $w.mouse.flags.rts -text $messages(mouse.12) \ ! -width 14 -indicatoron no -variable clearRTS pack $w.mouse.flags.title $w.mouse.flags.dtr $w.mouse.flags.rts \ -side top -fill x -padx 3m -anchor w + frame $w.mouse.buttons + pack $w.mouse.buttons -in $w.mouse.mid.mid -side top \ + -pady 3m + label $w.mouse.buttons.title -text $messages(mouse.23) + pack $w.mouse.buttons.title -side top + frame $w.mouse.buttons.left + frame $w.mouse.buttons.mid + frame $w.mouse.buttons.right + pack $w.mouse.buttons.left $w.mouse.buttons.mid \ + $w.mouse.buttons.right -side left -expand yes -fill x + radiobutton $w.mouse.buttons.3 -text 3 \ + -variable mseButtons -value 3 + pack $w.mouse.buttons.3 -side top -fill x -anchor w \ + -in $w.mouse.buttons.left + radiobutton $w.mouse.buttons.4 -text 4 \ + -variable mseButtons -value 4 + pack $w.mouse.buttons.4 -side top -fill x -anchor w \ + -in $w.mouse.buttons.mid + radiobutton $w.mouse.buttons.5 -text 5 \ + -variable mseButtons -value 5 + pack $w.mouse.buttons.5 -side top -fill x -anchor w \ + -in $w.mouse.buttons.right + frame $w.mouse.srate pack $w.mouse.srate -in $w.mouse.mid -side left -fill y -expand yes ! label $w.mouse.srate.title -text $messages(mouse.13) scale $w.mouse.srate.scale -orient vertical -from 0 -to 150 \ -tickinterval 25 -variable sampleRate -state disabled pack $w.mouse.srate.title -side top *************** *** 203,209 **** frame $w.mouse.em3tm pack $w.mouse.em3tm -in $w.mouse.mid -side left -fill y -expand yes ! label $w.mouse.em3tm.title -text "Emulate3Timeout" scale $w.mouse.em3tm.scale -orient vertical -from 0 -to 1000 \ -tickinterval 250 -variable emulate3Timeout -resolution 5 pack $w.mouse.em3tm.title -side top --- 265,271 ---- frame $w.mouse.em3tm pack $w.mouse.em3tm -in $w.mouse.mid -side left -fill y -expand yes ! label $w.mouse.em3tm.title -text $messages(mouse.14) scale $w.mouse.em3tm.scale -orient vertical -from 0 -to 1000 \ -tickinterval 250 -variable emulate3Timeout -resolution 5 pack $w.mouse.em3tm.title -side top *************** *** 212,235 **** frame $w.mouse.mid.right pack $w.mouse.mid.right -side left set canv $w.mouse.mid.right.canvas ! canvas $canv -width 2.75i -height 4i -highlightthickness 0 \ ! -takefocus 0 ! $canv create rectangle 0.25i 1.25i 2.50i 3.75i -fill white \ ! -tag {mbut mbut4} ! $canv create rectangle 0.25i 0.25i 1.00i 1.25i -fill white \ ! -tag {mbut mbut1} ! $canv create rectangle 1.00i 0.25i 1.75i 1.25i -fill white \ ! -tag {mbut mbut2} ! $canv create rectangle 1.75i 0.25i 2.50i 1.25i -fill white \ ! -tag {mbut mbut3} ! $canv create text 1.375i 2.25i -tag coord ! button $w.mouse.mid.right.apply -text "Apply" \ -command [list Mouse_setsettings $win] pack $canv $w.mouse.mid.right.apply -side top label $w.mouse.bot.mesg \ ! -text "Press ? or Alt-H for a list of key bindings" \ -foreground [$w.mouse.top.title cget -foreground] pack $w.mouse.bot.mesg --- 274,306 ---- frame $w.mouse.mid.right pack $w.mouse.mid.right -side left set canv $w.mouse.mid.right.canvas ! if !$pc98_EGC { ! set canvHeight 4i ! set canvRect4Height 3.75i ! set canvTextHeight 2.25i ! } else { ! set canvHeight 2i ! set canvRect4Height 1.75i ! set canvTextHeight 1.50i ! } ! canvas $canv -width 1.5i -height 3i -highlightthickness 0 \ ! -takefocus 0 ! $canv create rectangle 0.1i 1i 1.3i 2.5i -fill white \ ! -tag {mbut mbut4} ! $canv create rectangle 0.1i 0.25i 0.5i 1i -fill white \ ! -tag {mbut mbut1} ! $canv create rectangle 0.5i 0.25i 0.9i 1i -fill white \ ! -tag {mbut mbut2} ! $canv create rectangle 0.9i 0.25i 1.3i 1i -fill white \ ! -tag {mbut mbut3} ! $canv create text 0.7i 2.20i -tag coord ! button $w.mouse.mid.right.apply -text $messages(mouse.15) \ -command [list Mouse_setsettings $win] pack $canv $w.mouse.mid.right.apply -side top label $w.mouse.bot.mesg \ ! -text $messages(mouse.16) \ -foreground [$w.mouse.top.title cget -foreground] pack $w.mouse.bot.mesg *************** *** 262,272 **** --- 333,347 ---- bind $win c [format $ifcmd $w $w.mouse.chdmid invoke ] bind $win d [format $ifcmd $w $w.mouse.flags.dtr invoke ] bind $win e [format $ifcmd $w $w.mouse.em3but invoke ] + bind $win l [format $ifcmd $w Mouse_nextresolution $win ] bind $win n [format $ifcmd $w Mouse_selectentry $win ] bind $win p [format $ifcmd $w Mouse_nextprotocol $win ] bind $win r [format $ifcmd $w $w.mouse.flags.rts invoke ] bind $win s [format $ifcmd $w Mouse_incrsamplerate $win ] bind $win t [format $ifcmd $w Mouse_increm3timeout $win ] + bind $win 3 [format $ifcmd $w $w.mouse.buttons.3 invoke ] + bind $win 4 [format $ifcmd $w $w.mouse.buttons.4 invoke ] + bind $win 5 [format $ifcmd $w $w.mouse.buttons.5 invoke ] if ![info exists mseHelpShown] { Mouse_popup_help $win set mseHelpShown yes *************** *** 295,344 **** bind $win t "" } - proc Mouse_popup_help { win } { - toplevel .mousehelp -bd 5 -relief ridge - wm title .mousehelp "Help" - wm geometry .mousehelp +30+30 - text .mousehelp.text -takefocus 0 -width 90 -height 30 - .mousehelp.text insert end \ - { First select the protocol for your mouse using 'p', then if needed, change the device - name. If applicable, also set the baud rate (1200 should work). Avoid moving the - mouse or pressing buttons before the correct protocol has been selected. Press 'a' - to apply the changes and try moving your mouse around. If the mouse pointer does - not move properly, try a different protocol or device name. - - Once the mouse is moving properly, test that the various buttons also work correctly. - If you have a three button mouse and the middle button does not work, try the buttons - labeled ChordMiddle and Emulate3Buttons. - - Note: the `Logitech' protocol is only used by older Logitech mice. Most current - models use the `Microsoft' or `MouseMan' protocol. - - Key Function - ------------------------------------------------------ - a - Apply changes - b - Change to next baud rate - c - Toggle the ChordMiddle button - d - Toggle the ClearDTR button - e - Toggle the Emulate3button button - n - Set the name of the device - p - Select the next protocol - r - Toggle the ClearRTS button - s - Increase the sample rate - t - Increase the 3-button emulation timeout - ------------------------------------------------------ - You can also use Tab, and Shift-Tab to move around and then use Enter to activate - the selected button. - - See the documentation for more information - } - - button .mousehelp.ok -text "Dismiss" -command "destroy .mousehelp" - focus .mousehelp.ok - .mousehelp.text configure -state disabled - pack .mousehelp.text .mousehelp.ok - } - proc Mouse_selectentry { win } { set w [winpathprefix $win] if { [ $w.mouse.device.entry cget -state] != "disabled" } { --- 370,375 ---- *************** *** 377,382 **** --- 408,424 ---- } while { [$w.mouse.brate.$baudRate cget -state] == "disabled" } } + proc Mouse_nextresolution { win } { + global mseRes + + set w [winpathprefix $win] + set mseRes [expr $mseRes/2] + if { $mseRes < 50 } { + set mseRes 200 + } + $w.mouse.resolution.$mseRes invoke + } + proc Mouse_incrsamplerate { win } { global sampleRate *************** *** 436,446 **** proc Mouse_setsettings { win } { global mseType baudRate sampleRate clearDTR Pointer global emulate3Buttons emulate3Timeout chordMiddle clearRTS ! global mseDeviceSelected set w [winpathprefix $win] $w.mouse.bot.mesg configure -foreground black \ ! -text "Applying..." $win configure -cursor watch update idletasks set mseDeviceSelected 1 --- 478,488 ---- proc Mouse_setsettings { win } { global mseType baudRate sampleRate clearDTR Pointer global emulate3Buttons emulate3Timeout chordMiddle clearRTS ! global mseRes mseButtons mseDeviceSelected messages set w [winpathprefix $win] $w.mouse.bot.mesg configure -foreground black \ ! -text $messages(mouse.4) $win configure -cursor watch update idletasks set mseDeviceSelected 1 *************** *** 463,469 **** } check_tmpdirs set result [catch { eval [list xf86misc_setmouse \ ! $msedev $mseType $baudRate $sampleRate \ $em3but $emulate3Timeout $chdmid] $flags } ] if { $result } { bell -displayof $w --- 505,511 ---- } check_tmpdirs set result [catch { eval [list xf86misc_setmouse \ ! $msedev $mseType $baudRate $sampleRate $mseRes $mseButtons \ $em3but $emulate3Timeout $chdmid] $flags } ] if { $result } { bell -displayof $w *************** *** 480,485 **** --- 522,529 ---- } else { set Pointer(SampleRate) $sampleRate } + set Pointer(Resolution) $mseRes + set Pointer(Buttons) $mseButtons set Pointer(Emulate3Buttons) [expr $emulate3Buttons?"ON":""] set Pointer(Emulate3Timeout) \ [expr $emulate3Buttons?$emulate3Timeout:""] *************** *** 488,494 **** set Pointer(ClearRTS) [expr $clearRTS?"ON":""] } $w.mouse.bot.mesg configure \ ! -text "Press ? or Alt-H for a list of key bindings" \ -foreground [$w.mouse.top.title cget -foreground] $win configure -cursor top_left_arrow } --- 532,538 ---- set Pointer(ClearRTS) [expr $clearRTS?"ON":""] } $w.mouse.bot.mesg configure \ ! -text $messages(mouse.9) \ -foreground [$w.mouse.top.title cget -foreground] $win configure -cursor top_left_arrow } *************** *** 496,502 **** proc Mouse_getsettings { win } { global mseType mseTypeList baudRate sampleRate clearDTR Pointer global emulate3Buttons emulate3Timeout chordMiddle clearRTS ! global mseDeviceSelected set w [winpathprefix $win] set initlist [xf86misc_getmouse] --- 540,546 ---- proc Mouse_getsettings { win } { global mseType mseTypeList baudRate sampleRate clearDTR Pointer global emulate3Buttons emulate3Timeout chordMiddle clearRTS ! global mseRes mseButtons mseDeviceSelected SupportedMouseTypes set w [winpathprefix $win] set initlist [xf86misc_getmouse] *************** *** 504,513 **** set inittype [lindex $initlist 1] set initbrate [lindex $initlist 2] set initsrate [lindex $initlist 3] ! set initem3btn [lindex $initlist 4] ! set initem3tm [lindex $initlist 5] ! set initchdmid [lindex $initlist 6] ! set initflags [lrange $initlist 7 end] set mseDeviceSelected 1 if [getuid] { --- 548,559 ---- set inittype [lindex $initlist 1] set initbrate [lindex $initlist 2] set initsrate [lindex $initlist 3] ! set initres [lindex $initlist 4] ! set initbtn [lindex $initlist 5] ! set initem3btn [lindex $initlist 6] ! set initem3tm [lindex $initlist 7] ! set initchdmid [lindex $initlist 8] ! set initflags [lrange $initlist 9 end] set mseDeviceSelected 1 if [getuid] { *************** *** 536,554 **** set emulate3Buttons [expr [string compare $initem3btn on] == 0] set emulate3Timeout $initem3tm set sampleRate $initsrate set clearDTR [expr [string first $initflags ClearDTR] >= 0] set clearRTS [expr [string first $initflags ClearRTS] >= 0] set mtype [string tolower $inittype] if { $mtype == "osmouse" || $mtype == "xqueue" } { - foreach mse $mseTypeList { - $w.mouse.type.[string tolower $mse] \ - configure -state disabled - } $w.mouse.type.$mtype configure -state normal } else { ! $w.mouse.type.osmouse configure -state disabled ! $w.mouse.type.xqueue configure -state disabled } $w.mouse.type.$mtype invoke } --- 582,614 ---- set emulate3Buttons [expr [string compare $initem3btn on] == 0] set emulate3Timeout $initem3tm set sampleRate $initsrate + set mseRes $initres + if { $mseRes <= 0 } { + set mseRes 100 + } + $w.mouse.resolution.$mseRes invoke + set mseButtons $initbtn + if { $mseButtons < 3 } { + set mseButtons 3 + } elseif { $mseButtons > 5 } { + set mseButtons 5 + } + $w.mouse.buttons.$mseButtons invoke set clearDTR [expr [string first $initflags ClearDTR] >= 0] set clearRTS [expr [string first $initflags ClearRTS] >= 0] + foreach mse $mseTypeList { + $w.mouse.type.[string tolower $mse] \ + configure -state disabled + } set mtype [string tolower $inittype] if { $mtype == "osmouse" || $mtype == "xqueue" } { $w.mouse.type.$mtype configure -state normal } else { ! foreach mse $SupportedMouseTypes { ! $w.mouse.type.[string tolower $mse] \ ! configure -state normal ! } } $w.mouse.type.$mtype invoke } *************** *** 591,598 **** --- 651,672 ---- switch $mousetype { PS/2 { set idx [lsearch -regexp $mseDevices \ {/dev/p[ms].*} ] } + IMPS/2 { set idx [lsearch -regexp $mseDevices \ + {/dev/p[ms].*} ] } + ThikingMousePS/2 { set idx [lsearch -regexp $mseDevices \ + {/dev/p[ms].*} ] } + MouseManPlusPS/2 { set idx [lsearch -regexp $mseDevices \ + {/dev/p[ms].*} ] } + GlidePointPS/2 { set idx [lsearch -regexp $mseDevices \ + {/dev/p[ms].*} ] } + NetMousePS/2 { set idx [lsearch -regexp $mseDevices \ + {/dev/p[ms].*} ] } + NetScrollPS/2 { set idx [lsearch -regexp $mseDevices \ + {/dev/p[ms].*} ] } BusMouse { set idx [lsearch -regexp $mseDevices \ /dev/.*bm|/dev/mse.* ] } + SysMouse { set idx [lsearch -regexp $mseDevices \ + /dev/sysmouse.* ] } OsMouse - Xqueue { return "" } default { set idx [lsearch -regexp $mseDevices \ *** /dev/null Tue Jun 30 11:43:29 1998 --- xc/programs/Xserver/hw/xfree86/XF86Setup/mseproto.cpp Fri Mar 6 16:27:56 1998 *************** *** 0 **** --- 1,80 ---- + /* $TOG: mseproto.cpp /main/1 1998/03/06 16:29:34 kaleb $ */ + + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/mseproto.cpp,v 1.1.2.5 1998/02/28 08:54:10 dawes Exp $ */ + + #if defined(PC98) + set SerialMouseTypes [list \ + "Microsoft" \ + "Logitech" \ + "MouseMan" \ + "IntelliMouse" \ + ] + #else + set SerialMouseTypes [list \ + "Microsoft" \ + "MouseSystems" \ + "MMSeries" \ + "Logitech" \ + "MouseMan" \ + "MMHitTab" \ + "GlidePoint" \ + "IntelliMouse" \ + "ThinkingMouse" \ + ] + #endif + + set BusMouseTypes [list \ + "BusMouse" \ + ] + + #if defined(PC98) + set StandardPS2Types [] + set ExtendedPS2Types [] + #else + set StandardPS2Types [list \ + "PS/2" \ + ] + + set ExtendedPS2Types [list \ + "IMPS/2" \ + "ThinkingMousePS/2" \ + "MouseManPlusPS/2" \ + "GlidePointPS/2" \ + "NetMousePS/2" \ + "NetScrollPS/2" \ + ] + #endif + + set PnpMouseTypes [list \ + "Auto" \ + ] + + + #if defined(__FreeBSD__) + set ExtraMouseTypes [list \ + "SysMouse" \ + ] + #define MOUSE_TYPES $SerialMouseTypes $BusMouseTypes $StandardPS2Types \ + $PnpMouseTypes $ExtraMouseTypes + #elif defined(__NetBSD__) + #define MOUSE_TYPES $SerialMouseTypes $BusMouseTypes $PnpMouseTypes + #elif defined(__OpenBSD__) + #define MOUSE_TYPES $SerialMouseTypes $BusMouseTypes $StandardPS2Types \ + $PnpMouseTypes + #elif defined(Lynx) + #define MOUSE_TYPES $SerialMouseTypes $BusMouseTypes $StandardPS2Types + #elif defined(ISC) + #define MOUSE_TYPES $SerialMouseTypes $BusMouseTypes $StandardPS2Types + #elif defined(sun) && defined(i386) && defined(SVR4) + #define MOUSE_TYPES $SerialMouseTypes $BusMouseTypes $StandardPS2Types + #elif defined (SVR4) || defined(SYSV) + #define MOUSE_TYPES $SerialMouseTypes $PnpMouseTypes + #else + #define MOUSE_TYPES $SerialMouseTypes $BusMouseTypes $StandardPS2Types \ + $PnpMouseTypes $ExtendedPS2Types + #endif + + set SupportedMouseTypes [concat MOUSE_TYPES] *** ./programs/Xserver/hw/xfree86/XF86Setup/phase1.tcl@@/PUBLIC-LATEST Sun Aug 10 12:57:19 1997 --- xc/programs/Xserver/hw/xfree86/XF86Setup/phase1.tcl Fri Mar 6 16:28:00 1998 *************** *** 1,9 **** ! # $TOG: phase1.tcl /main/5 1997/08/10 12:55:55 kaleb $ # # # # ! # $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/phase1.tcl,v 3.13.2.1 1997/06/20 09:13:50 hohndel Exp $ # # Copyright 1996 by Joseph V. Moss # --- 1,9 ---- ! # $TOG: phase1.tcl /main/6 1998/03/06 16:29:38 kaleb $ # # # # ! # $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/phase1.tcl,v 3.13.2.4 1998/02/26 13:58:59 dawes Exp $ # # Copyright 1996 by Joseph V. Moss # *************** *** 19,24 **** --- 19,26 ---- # load the autoload stuff source $tcl_library/init.tcl + # load language specific library + source $XF86Setup_library/texts/local_text.tcl # load in our library source $XF86Setup_library/setuplib.tcl source $XF86Setup_library/filelist.tcl *************** *** 227,236 **** configuration with this program" okay exit 1 } ! if { ![file exists $Xwinhome/bin/XF86_VGA16] } { ! mesg "The VGA16 server is required when using\n\ ! this program to set the initial configuration" okay ! exit 1 } set UseConfigFile [mesg "Would you like to use the\ existing XF86Config file for defaults?" yesno] --- 229,248 ---- configuration with this program" okay exit 1 } ! if !$pc98 { ! if { ![file exists $Xwinhome/bin/XF86_VGA16] } { ! mesg "The VGA16 server is required when using\n\ ! this program to set the initial configuration" okay ! exit 1 ! } ! } else { ! if { ![file exists $Xwinhome/bin/XF98_EGC] ! && ![file exists $Xwinhome/bin/XF98_NEC480] } { ! mesg "Either the EGC server or the NEC480 server\n\ ! is required when using this program to set\nn ! the initial configuration" okay ! exit 1 ! } } set UseConfigFile [mesg "Would you like to use the\ existing XF86Config file for defaults?" yesno] *************** *** 247,255 **** mesg "You need to be root to run this program" okay exit 1 } ! if { !$ReConfig && ![file exists $Xwinhome/bin/XF86_VGA16] } { ! mesg "The VGA16 server is required to run this program" okay ! exit 1 } # initialize the configuration variables initconfig $Xwinhome --- 259,276 ---- mesg "You need to be root to run this program" okay exit 1 } ! if !$pc98 { ! if { !$ReConfig && ![file exists $Xwinhome/bin/XF86_VGA16] } { ! mesg "The VGA16 server is required to run this program" okay ! exit 1 ! } ! } else { ! if { !$ReConfig && ![file exists $Xwinhome/bin/XF98_EGC] ! && ![file exists $Xwinhome/bin/XF98_NEC480] } { ! mesg "Either the EGC server or the NEC480 server is required\n\ ! to run this program" okay ! exit 1 ! } } # initialize the configuration variables initconfig $Xwinhome *************** *** 333,344 **** if $StartServer { # write out a temp XF86Config file ! writeXF86Config $Confname-1 -vgamode -generic mesg "Press \[Enter\] to switch to graphics mode.\n\ \nThis may take a while..." okay ! set ServerPID [start_server VGA16 $Confname-1 ServerOut-1] if { $ServerPID == 0 } { mesg "Unable to start X server!" info --- 354,382 ---- if $StartServer { # write out a temp XF86Config file ! if !$pc98 { ! writeXF86Config $Confname-1 -vgamode -generic ! } else { ! writeXF86Config $Confname-1 -vgamode ! } mesg "Press \[Enter\] to switch to graphics mode.\n\ \nThis may take a while..." okay ! if !$pc98 { ! set ServerPID [start_server VGA16 $Confname-1 ServerOut-1] ! } else { ! if !$pc98_EGC { ! set ServerPID [start_server NEC480 $Confname-1 ServerOut-1] ! # if {$ServerPID == 0 || $ServerPID == -1} { ! # puts "Unable to start NEC480 server!\n\ ! # try to start EGC server.\n"; ! # set pc98_EGC 1; ! # } ! } else { ! set ServerPID [start_server EGC $Confname-1 ServerOut-1] ! } ! } if { $ServerPID == 0 } { mesg "Unable to start X server!" info *** ./programs/Xserver/hw/xfree86/XF86Setup/phase2.tcl@@/PUBLIC-LATEST Sat Jul 19 09:23:11 1997 --- xc/programs/Xserver/hw/xfree86/XF86Setup/phase2.tcl Fri Mar 6 16:28:04 1998 *************** *** 1,9 **** ! # $TOG: phase2.tcl /main/3 1997/07/19 09:23:12 kaleb $ # # # # ! # $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/phase2.tcl,v 3.10 1997/01/23 10:59:34 dawes Exp $ # # Copyright 1996 by Joseph V. Moss # --- 1,9 ---- ! # $TOG: phase2.tcl /main/4 1998/03/06 16:29:42 kaleb $ # # # # ! # $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/phase2.tcl,v 3.10.2.5 1998/02/26 13:59:00 dawes Exp $ # # Copyright 1996 by Joseph V. Moss # *************** *** 22,28 **** create_main_window [set w .xf86setup] # put up a message ASAP so the user knows we're still alive ! label $w.waitmsg -text "Loading - Please wait...\n\n\n" pack $w.waitmsg -expand yes -fill both update idletasks --- 22,28 ---- create_main_window [set w .xf86setup] # put up a message ASAP so the user knows we're still alive ! label $w.waitmsg -text $messages(phase2.1) pack $w.waitmsg -expand yes -fill both update idletasks *************** *** 34,48 **** set XKBrules $Xwinhome/lib/X11/xkb/rules/xfree86 if { [catch {set XKBhandle [xkb_read from_server]} res] } { ! $w.waitmsg configure -text \ ! "Unable to read keyboard information from the server.\n\n\ ! This problem most often occurs when you are running when\n\ ! you are running a server which does not have the XKEYBOARD\n\ ! extension or which has it disabled.\n\n\ ! The ability of this program to configure the keyboard is\n\ ! reduced without the XKEYBOARD extension, but is still\ ! functional.\n\n\ ! Continuing..." update idletasks after 10000 set XKBinserver 0 --- 34,40 ---- set XKBrules $Xwinhome/lib/X11/xkb/rules/xfree86 if { [catch {set XKBhandle [xkb_read from_server]} res] } { ! $w.waitmsg configure -text $messages(phase2.2) update idletasks after 10000 set XKBinserver 0 *************** *** 78,83 **** --- 70,76 ---- # Setup the default bindings for the various widgets source $tcl_library/tk.tcl + source $XF86Setup_library/mseproto.tcl source $XF86Setup_library/mouse.tcl source $XF86Setup_library/keyboard.tcl source $XF86Setup_library/card.tcl *************** *** 84,96 **** source $XF86Setup_library/monitor.tcl source $XF86Setup_library/srvflags.tcl source $XF86Setup_library/done.tcl proc Intro_create_widgets { win } { global XF86Setup_library set w [winpathprefix $win] ! frame $w.intro -width 640 -height 420 \ -relief ridge -borderwidth 5 image create bitmap XFree86-logo \ -foreground black -background cyan \ -file $XF86Setup_library/pics/XFree86.xbm \ --- 77,96 ---- source $XF86Setup_library/monitor.tcl source $XF86Setup_library/srvflags.tcl source $XF86Setup_library/done.tcl + source $XF86Setup_library/modeselect.tcl proc Intro_create_widgets { win } { global XF86Setup_library + global pc98_EGC pc98 messages set w [winpathprefix $win] ! if !$pc98_EGC { ! frame $w.intro -width 640 -height 420 \ ! -relief ridge -borderwidth 5 ! } else { ! frame $w.intro -width 640 -height 400 \ -relief ridge -borderwidth 5 + } image create bitmap XFree86-logo \ -foreground black -background cyan \ -file $XF86Setup_library/pics/XFree86.xbm \ *************** *** 98,132 **** label $w.intro.logo -image XFree86-logo pack $w.intro.logo ! text $w.intro.text ! $w.intro.text tag configure heading \ -justify center -foreground yellow \ -font -adobe-times-bold-i-normal--25-180-*-*-p-*-iso8859-1 ! $w.intro.text insert end "Introduction to Configuration\ ! with XF86Setup" heading ! $w.intro.text insert end "\n\n\ ! There are five areas of configuration that need to\ ! be completed, corresponding to the buttons\n\ ! along the top:\n\n\ ! \tMouse\t\t- Use this to set the protocol, baud rate, etc.\ ! used by your mouse\n\ ! \tKeyboard\t- Set the nationality and layout of\ ! your keyboard\n\ ! \tCard\t\t- Used to select the chipset, RAMDAC, etc.\ ! of your card\n\ ! \tMonitor\t\t- Use this to enter your\ ! monitor's capabilities\n\ ! \tOther\t\t- Configure some miscellaneous settings\n\n\ ! You'll probably want to start with configuring your\ ! mouse (you can just press \[Enter\] to do so)\n\ ! and when you've finished configuring all five of these,\ ! select the Done button.\n\n\ ! To select any of the buttons, press the underlined\ ! letter together with either Control or Alt.\n\ ! You can also press ? or click on the Help button at\ ! any time for additional instructions\n\n" ! pack $w.intro.text -fill both -expand yes -padx 10 -pady 10 ! $w.intro.text configure -state disabled } proc Intro_activate { win } { --- 98,123 ---- label $w.intro.logo -image XFree86-logo pack $w.intro.logo ! frame $w.intro.textframe ! text $w.intro.textframe.text ! $w.intro.textframe.text tag configure heading \ -justify center -foreground yellow \ -font -adobe-times-bold-i-normal--25-180-*-*-p-*-iso8859-1 ! make_intro_headline $w.intro.textframe.text ! $w.intro.textframe.text insert end $messages(phase2.12) ! scrollbar $w.intro.textframe.scroll \ ! -command "$w.intro.textframe.text yview" ! bind $w \ ! "$w.intro.textframe.text yview scroll -1 unit;break;" ! bind $w \ ! "$w.intro.textframe.text yview scroll 1 unit;break;" ! ! $w.intro.textframe.text configure \ ! -yscrollcommand "$w.intro.textframe.scroll set" ! pack $w.intro.textframe.scroll -side right -fill y ! pack $w.intro.textframe.text -fill both -expand yes -side right ! pack $w.intro.textframe -fill both -expand yes -padx 10 -pady 10 ! $w.intro.textframe.text configure -state disabled } proc Intro_activate { win } { *************** *** 139,177 **** pack forget $w.intro } - proc Intro_popup_help { win } { - catch {destroy .introhelp} - toplevel .introhelp -bd 5 -relief ridge - wm title .introhelp "Help" - wm geometry .introhelp +30+30 - text .introhelp.text - .introhelp.text insert 0.0 "\n\ - You need to fill in the requested information on each\ - of the five\n\ - configuration screens. The buttons along the top allow\ - you to choose which\n\ - screen you are going to work on. You can do them in\ - any order or go back\n\ - to each of them as many times as you like, however,\ - it will be very\n\ - difficult to use some of them if your mouse is not\ - working, so you\n\ - should configure your mouse first.\n\n\ - Until you get your mouse working, here are some keys you\ - can use:\n\n\ - \ \ Tab, Ctrl-Tab Move to the \"next\" widget\n\ - \ \ Shift-Tab Move to the \"previous\" widget\n\ - \ \ Move in the appropriate direction\n\ - \ \ Return Activate the selected widget\n\n\ - Also, you can press Alt and one of the underlined letters\ - to activate the\n\ - corresponding button." - .introhelp.text configure -state disabled - button .introhelp.ok -text "Dismiss" -command "destroy .introhelp" - focus .introhelp.ok - pack .introhelp.text .introhelp.ok - } - proc config_select { win } { global CfgSelection prevSelection --- 130,135 ---- *************** *** 192,214 **** frame $w.menu -width 640 ! radiobutton $w.menu.mouse -text Mouse -indicatoron false \ -variable CfgSelection -value Mouse -underline 0 \ -command [list config_select $w] ! radiobutton $w.menu.keyboard -text Keyboard -indicatoron false \ ! -variable CfgSelection -value Keyboard -underline 0 \ ! -command [list config_select $w] ! radiobutton $w.menu.card -text Card -indicatoron false \ -variable CfgSelection -value Card -underline 0 \ -command [list config_select $w] ! radiobutton $w.menu.monitor -text Monitor -indicatoron false \ -variable CfgSelection -value Monitor -underline 2 \ -command [list config_select $w] ! radiobutton $w.menu.other -text Other -indicatoron false \ -variable CfgSelection -value Other -underline 0 \ -command [list config_select $w] ! pack $w.menu.mouse $w.menu.keyboard $w.menu.card $w.menu.monitor \ ! $w.menu.other -side left -fill both -expand yes frame $w.buttons #label $w.buttons.xlogo -bitmap @/usr/X11R6/include/X11/bitmaps/xlogo16 -anchor w --- 150,183 ---- frame $w.menu -width 640 ! radiobutton $w.menu.mouse -text $messages(phase2.3) -indicatoron false \ -variable CfgSelection -value Mouse -underline 0 \ -command [list config_select $w] ! radiobutton $w.menu.keyboard -text $messages(phase2.4) \ ! -indicatoron false \ ! -variable CfgSelection -value Keyboard -underline 0 \ ! -command [list config_select $w] ! radiobutton $w.menu.card -text $messages(phase2.5) -indicatoron false \ -variable CfgSelection -value Card -underline 0 \ -command [list config_select $w] ! radiobutton $w.menu.monitor -text $messages(phase2.6) -indicatoron false \ -variable CfgSelection -value Monitor -underline 2 \ -command [list config_select $w] ! radiobutton $w.menu.modeselect -text $messages(phase2.7) -indicatoron false \ ! -variable CfgSelection -value Modeselection -underline 4 \ ! -command [list config_select $w] ! radiobutton $w.menu.other -text $messages(phase2.8) -indicatoron false \ -variable CfgSelection -value Other -underline 0 \ -command [list config_select $w] ! if !$pc98 { ! pack $w.menu.mouse $w.menu.keyboard $w.menu.card \ ! $w.menu.monitor $w.menu.modeselect $w.menu.other \ ! -side left -fill both -expand yes ! } else { ! pack $w.menu.mouse $w.menu.card $w.menu.monitor \ ! $w.menu.modeselect $w.menu.other \ ! -side left -fill both -expand yes ! } frame $w.buttons #label $w.buttons.xlogo -bitmap @/usr/X11R6/include/X11/bitmaps/xlogo16 -anchor w *************** *** 215,234 **** #label $w.buttons.xlogo -bitmap @/usr/tmp/xfset1.xbm -anchor w \ -foreground black #pack $w.buttons.xlogo -side left -anchor w -expand no -padx 0 -fill x ! button $w.buttons.abort -text Abort -underline 0 \ -command "clear_scrn;puts stderr Aborted;shutdown 1" ! button $w.buttons.done -text Done -underline 0 \ -command [list Done_execute $w] ! button $w.buttons.help -text Help -underline 0 \ -command [list config_help $w] pack $w.buttons.abort $w.buttons.done $w.buttons.help \ -expand no -side left -padx 50 Intro_create_widgets $w ! Keyboard_create_widgets $w Mouse_create_widgets $w Card_create_widgets $w Monitor_create_widgets $w Other_create_widgets $w Done_create_widgets $w --- 184,207 ---- #label $w.buttons.xlogo -bitmap @/usr/tmp/xfset1.xbm -anchor w \ -foreground black #pack $w.buttons.xlogo -side left -anchor w -expand no -padx 0 -fill x ! button $w.buttons.abort -text $messages(phase2.9) -underline 0 \ -command "clear_scrn;puts stderr Aborted;shutdown 1" ! button $w.buttons.done -text $messages(phase2.10) -underline 0 \ -command [list Done_execute $w] ! button $w.buttons.help -text $messages(phase2.11) -underline 0 \ -command [list config_help $w] pack $w.buttons.abort $w.buttons.done $w.buttons.help \ -expand no -side left -padx 50 + make_underline $w Intro_create_widgets $w ! if !$pc98 { ! Keyboard_create_widgets $w ! } Mouse_create_widgets $w Card_create_widgets $w Monitor_create_widgets $w + Modeselect_create_widgets $w Other_create_widgets $w Done_create_widgets $w *************** *** 246,251 **** --- 219,225 ---- ac_bind $w c [list $w.menu.card invoke] ac_bind $w k [list $w.menu.keyboard invoke] ac_bind $w n [list $w.menu.monitor invoke] + ac_bind $w s [list $w.menu.modeselect invoke] ac_bind $w o [list $w.menu.other invoke] set_default_arrow_bindings *** ./programs/Xserver/hw/xfree86/XF86Setup/phase4.tcl@@/PUBLIC-LATEST Sat Jul 19 09:23:21 1997 --- xc/programs/Xserver/hw/xfree86/XF86Setup/phase4.tcl Fri Mar 6 16:28:09 1998 *************** *** 1,9 **** ! # $TOG: phase4.tcl /main/2 1997/07/19 09:23:23 kaleb $ # # # # ! # $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/phase4.tcl,v 3.8 1996/12/27 06:54:11 dawes Exp $ # # Copyright 1996 by Joseph V. Moss # --- 1,9 ---- ! # $TOG: phase4.tcl /main/3 1998/03/06 16:29:46 kaleb $ # # # # ! # $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/phase4.tcl,v 3.8.2.1 1998/02/21 06:07:01 robin Exp $ # # Copyright 1996 by Joseph V. Moss # *************** *** 15,20 **** --- 15,22 ---- # Phase IV - Commands run after second server is started # + source $XF86Setup_library/texts/local_text.tcl + if $StartServer { set_resource_defaults *************** *** 23,29 **** create_main_window [set w .xf86setup] # put up a message ASAP so the user knows we're still alive ! label $w.waitmsg -text "Loading - Please wait..." pack $w.waitmsg -expand yes -fill both update idletasks --- 25,31 ---- create_main_window [set w .xf86setup] # put up a message ASAP so the user knows we're still alive ! label $w.waitmsg -text $messages(phase4.1) pack $w.waitmsg -expand yes -fill both update idletasks *************** *** 32,38 **** source $tk_library/tk.tcl set_default_arrow_bindings ! set msg "Congratulations, you've got a running server!\n\n" } else { set msg "" } --- 34,40 ---- source $tk_library/tk.tcl set_default_arrow_bindings ! set msg $messages(phase4.13) } else { set msg "" } *************** *** 45,50 **** --- 47,53 ---- proc Phase4_nextphase { win } { global Confname StartServer + global messages set w [winpathprefix $win] set saveto [$w.saveto.entry get] *************** *** 51,79 **** check_tmpdirs writeXF86Config $Confname-3 -displayof $w -realdevice set backupmsg "" if [file exists $saveto] { if {[catch {exec mv $saveto $saveto.bak} ret] != 0} { bell ! $w.mesg configure -text \ ! "Unable to backup $saveto as $saveto.bak!\n\ ! The configuration has not been saved!\n\ ! Try again, with a different file name" return } ! set backupmsg "A backup of the previous configuration has\n\ ! been saved to the file $saveto.bak" } if {[catch {exec cp $Confname-3 $saveto} ret] != 0} { bell ! $w.mesg configure -text \ ! "Unable to save the configuration to\n\ ! the file $saveto.\n\n\ ! Try again, with a different file name" return } ! $w.text configure -text \ ! "The configuration has been completed.\n\n\ ! $backupmsg" pack forget $w.buttons $w.mesg $w.saveto if $StartServer { set cmd {mesg "Just a moment..." info; shutdown} --- 54,75 ---- check_tmpdirs writeXF86Config $Confname-3 -displayof $w -realdevice set backupmsg "" + make_message_phase4 $saveto if [file exists $saveto] { if {[catch {exec mv $saveto $saveto.bak} ret] != 0} { bell ! $w.mesg configure -text $messages(phase4.2); return } ! set backupmsg $messages(phase4.3) } if {[catch {exec cp $Confname-3 $saveto} ret] != 0} { bell ! $w.mesg configure -text $messages(phase4.4) return } ! $w.text configure \ ! -text "$messages(phase4.5)$backupmsg" pack forget $w.buttons $w.mesg $w.saveto if $StartServer { set cmd {mesg "Just a moment..." info; shutdown} *************** *** 80,98 **** } else { set cmd {shutdown;source $XF86Setup_library/phase5.tcl} } ! button $w.okay -text "Okay" -command $cmd pack $w.text $w.okay -side top focus $w.okay } ! label $w.text -text " $msg\ ! You can now run xvidtune to adjust your display settings,\n\ ! if you want to change the size or placement of the screen image\n\n\ ! If not, go ahead and exit\n\n\n\ ! If you choose to save the configuration, a backup copy will be\n\ ! made, if the file already exists" frame $w.saveto ! label $w.saveto.title -text "Save configuration to:" entry $w.saveto.entry -bd 2 -width 40 pack $w.saveto.title $w.saveto.entry -side left if [getuid] { --- 76,89 ---- } else { set cmd {shutdown;source $XF86Setup_library/phase5.tcl} } ! button $w.okay -text $messages(phase4.6) -command $cmd pack $w.text $w.okay -side top focus $w.okay } ! label $w.text -text " $msg$messages(phase4.7)" frame $w.saveto ! label $w.saveto.title -text $messages(phase4.8) entry $w.saveto.entry -bd 2 -width 40 pack $w.saveto.title $w.saveto.entry -side left if [getuid] { *************** *** 106,117 **** } label $w.mesg -text "" frame $w.buttons ! button $w.buttons.xvidtune -text "Run xvidtune" \ -command [list Phase4_run_xvidtune $w] ! button $w.buttons.save -text "Save the configuration and exit" \ -command [list Phase4_nextphase $w] ! button $w.buttons.abort -text "Abort - Don't save the configuration" \ ! -command "clear_scrn;puts stderr Aborted;shutdown 1" pack $w.buttons.xvidtune $w.buttons.save $w.buttons.abort -side top \ -pady 5m -fill x --- 97,108 ---- } label $w.mesg -text "" frame $w.buttons ! button $w.buttons.xvidtune -text $messages(phase4.9) \ -command [list Phase4_run_xvidtune $w] ! button $w.buttons.save -text $messages(phase4.10) \ -command [list Phase4_nextphase $w] ! button $w.buttons.abort -text $messages(phase4.11) \ ! -command "clear_scrn;puts stderr $messages(phase4.12);shutdown 1" pack $w.buttons.xvidtune $w.buttons.save $w.buttons.abort -side top \ -pady 5m -fill x *** ./programs/Xserver/hw/xfree86/XF86Setup/phase5.tcl@@/PUBLIC-LATEST Sun Aug 10 12:57:24 1997 --- xc/programs/Xserver/hw/xfree86/XF86Setup/phase5.tcl Fri Mar 6 16:28:13 1998 *************** *** 1,9 **** ! # $TOG: phase5.tcl /main/6 1997/08/10 12:56:00 kaleb $ # # # # ! # $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/phase5.tcl,v 3.7.2.1 1997/06/20 09:13:50 hohndel Exp $ # # Copyright 1996 by Joseph V. Moss # --- 1,9 ---- ! # $TOG: phase5.tcl /main/7 1998/03/06 16:29:51 kaleb $ # # # # ! # $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/phase5.tcl,v 3.7.2.3 1998/02/21 06:07:02 robin Exp $ # # Copyright 1996 by Joseph V. Moss # *************** *** 47,54 **** set lastlink $linkname set linkname [readlink $linkname] } ! if { [file type $linkname]=="link" && ![file exists $linkname] } { set lastlink [readlink $linkname] } if { $nlinks < 20 } { --- 47,56 ---- set lastlink $linkname set linkname [readlink $linkname] } ! catch { ! if { [file type $linkname]=="link" && ![file exists $linkname] } { set lastlink [readlink $linkname] + } } if { $nlinks < 20 } { *************** *** 64,79 **** set linkdir [file dirname $lastlink] set mklink [mesg "Do you want to create an 'X' link\ to the $server server?\n\n(the link will be\ ! created in the directory: $linkdir)" yesno] if $mklink { set CWD [pwd] cd $linkdir catch "unlink X" ret ! if [catch "link $Xwinhome/bin/XF86_$server X" ret] { ! mesg "Link creation failed!\n\ ! You'll have to do it yourself" okay } else { ! mesg "Link created successfully." okay } cd $CWD } --- 66,90 ---- set linkdir [file dirname $lastlink] set mklink [mesg "Do you want to create an 'X' link\ to the $server server?\n\n(the link will be\ ! created in the directory: $linkdir) Okay?" yesno] if $mklink { set CWD [pwd] cd $linkdir catch "unlink X" ret ! if !$pc98 { ! if [catch "link $Xwinhome/bin/XF86_$server X" ret] { ! mesg "Link creation failed!\n\ ! You'll have to do it yourself" okay ! } else { ! mesg "Link created successfully." okay ! } } else { ! if [catch "link $Xwinhome/bin/XF98_$server X" ret] { ! mesg "Link creation failed!\n\ ! You'll have to do it yourself" okay ! } else { ! mesg "Link created successfully." okay ! } } cd $CWD } *** ./programs/Xserver/hw/xfree86/XF86Setup/scripts/mseconfig.tcl@@/PUBLIC-LATEST Sat Jul 19 09:23:35 1997 --- xc/programs/Xserver/hw/xfree86/XF86Setup/scripts/mseconfig.tcl Fri Mar 6 16:28:37 1998 *************** *** 1,9 **** ! # $TOG: mseconfig.tcl /main/2 1997/07/19 09:23:37 kaleb $ # # # # ! # $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/scripts/mseconfig.tcl,v 3.3 1996/12/27 06:54:48 dawes Exp $ set clicks1 [clock clicks] --- 1,9 ---- ! # $TOG: mseconfig.tcl /main/3 1998/03/06 16:30:15 kaleb $ # # # # ! # $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/scripts/mseconfig.tcl,v 3.3.2.4 1998/02/26 13:59:01 dawes Exp $ set clicks1 [clock clicks] *************** *** 12,17 **** --- 12,19 ---- Protocol "" BaudRate "" SampleRate "" + Resolution "" + Buttons "" Emulate3Buttons "" Emulate3Timeout "" ChordMiddle "" *************** *** 64,69 **** --- 66,72 ---- exit 1 } + source $XF86Setup_library/texts/local_text.tcl source $XF86Setup_library/setuplib.tcl if ![getuid] { set rand1 [random 1073741823] *************** *** 90,99 **** } set_resource_defaults source $XF86Setup_library/mouse.tcl Mouse_create_widgets . Mouse_activate . ! button .mouse.exit -text "Exit" -command "exit 0" -underline 1 pack .mouse.exit -side bottom -expand yes -fill x bind . "exit 0" bind . "exit 0" --- 93,104 ---- } set_resource_defaults + source $XF86Setup_library/mseproto.tcl source $XF86Setup_library/mouse.tcl Mouse_create_widgets . Mouse_activate . ! button .mouse.exit -text $messages(mouse.17) \ ! -command "exit 0" -underline $messages(mouse.18) pack .mouse.exit -side bottom -expand yes -fill x bind . "exit 0" bind . "exit 0" *** ./programs/Xserver/hw/xfree86/XF86Setup/scripts/xmseconfig.man@@/PUBLIC-LATEST Tue Nov 4 21:17:32 1997 --- xc/programs/Xserver/hw/xfree86/XF86Setup/scripts/xmseconfig.man Fri Mar 6 16:28:41 1998 *************** *** 1,4 **** ! .\" $TOG: xmseconfig.man /main/5 1997/11/04 21:20:27 kaleb $ .\" .\" .\" --- 1,4 ---- ! .\" $TOG: xmseconfig.man /main/6 1998/03/06 16:30:18 kaleb $ .\" .\" .\" *************** *** 5,11 **** .\" .\" .\" $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/scripts/xmseconfig.man,v 3.3 1996/12/27 06:54:50 dawes Exp $ ! .TH xmseconfig 1 "Release 6.4 (XFree86 3.3.1)" "X Version 11" .SH NAME xmseconfig - Graphical mouse configuration utility .SH SYNOPSIS --- 5,11 ---- .\" .\" .\" $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/scripts/xmseconfig.man,v 3.3 1996/12/27 06:54:50 dawes Exp $ ! .TH xmseconfig 1 "Version 3.2" "XFree86" .SH NAME xmseconfig - Graphical mouse configuration utility .SH SYNOPSIS *** ./programs/Xserver/hw/xfree86/XF86Setup/setuplib.tcl@@/PUBLIC-LATEST Sat Jul 19 09:23:50 1997 --- xc/programs/Xserver/hw/xfree86/XF86Setup/setuplib.tcl Fri Mar 6 16:28:17 1998 *************** *** 1,9 **** ! # $TOG: setuplib.tcl /main/4 1997/07/19 09:23:51 kaleb $ # # # # ! # $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/setuplib.tcl,v 3.13 1996/12/27 06:54:13 dawes Exp $ # # Copyright 1996 by Joseph V. Moss # --- 1,9 ---- ! # $TOG: setuplib.tcl /main/5 1998/03/06 16:29:55 kaleb $ # # # # ! # $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/setuplib.tcl,v 3.13.2.7 1998/02/28 08:54:10 dawes Exp $ # # Copyright 1996 by Joseph V. Moss # *************** *** 22,27 **** --- 22,28 ---- global "Monitor_Primary Monitor" "Device_Primary Card" global DeviceIDs MonitorIDs global Scrn_Accel Scrn_Mono Scrn_VGA2 Scrn_VGA16 Scrn_SVGA + global pc98 pc98_EGC set fontdir "$xwinhome/lib/X11/fonts" set Files(FontPath) [list $fontdir/misc:unscaled \ *************** *** 47,81 **** XkbSymbols XkbGeometry XkbKeymap } { set Keyboard($key) "" } ! set Keyboard(XkbDisable) "" ! set Keyboard(XkbRules) xfree86 ! set Keyboard(XkbModel) pc101 ! set Keyboard(XkbLayout) us ! set Keyboard(XkbVariant) "" ! set Keyboard(XkbOptions) "" - set Pointer(Protocol) Microsoft set Pointer(Device) /dev/mouse set Pointer(BaudRate) "" - set Pointer(Emulate3Buttons) "" set Pointer(Emulate3Timeout) "" set Pointer(ChordMiddle) "" set Pointer(SampleRate) "" set Pointer(ClearDTR) "" set Pointer(ClearRTS) "" ! set id "Primary Monitor" ! set Monitor_${id}(VendorName) Unknown ! set Monitor_${id}(ModelName) Unknown ! set Monitor_${id}(HorizSync) 31.5 ! set Monitor_${id}(VertRefresh) 60 ! set Monitor_${id}(Gamma) "" ! set MonitorIDs [list $id] ! set id "Primary Card" set Device_${id}(VendorName) Unknown set Device_${id}(BoardName) Unknown ! set Device_${id}(Server) SVGA foreach key {Chipset Ramdac DacSpeed Clocks ClockChip ClockProg Options VideoRam BIOSBase Membase IOBase DACBase POSBase COPBase VGABase --- 48,118 ---- XkbSymbols XkbGeometry XkbKeymap } { set Keyboard($key) "" } ! if !$pc98 { ! set Keyboard(XkbDisable) "" ! set Keyboard(XkbRules) xfree86 ! set Keyboard(XkbModel) pc101 ! set Keyboard(XkbLayout) us ! set Keyboard(XkbVariant) "" ! set Keyboard(XkbOptions) "" ! set Pointer(Protocol) Microsoft ! set Pointer(Emulate3Buttons) "" ! } else { ! set Keyboard(XkbDisable) "" ! set Keyboard(XkbRules) xfree98 ! set Keyboard(XkbModel) pc98 ! set Keyboard(XkbLayout) nec/jp ! set Keyboard(XkbVariant) "" ! set Keyboard(XkbOptions) "" ! set Pointer(Protocol) BusMouse ! set Pointer(Emulate3Buttons) 1 ! } set Pointer(Device) /dev/mouse set Pointer(BaudRate) "" set Pointer(Emulate3Timeout) "" set Pointer(ChordMiddle) "" set Pointer(SampleRate) "" + set Pointer(Resolution) "" + set Pointer(Buttons) "" set Pointer(ClearDTR) "" set Pointer(ClearRTS) "" ! if !$pc98_EGC { ! set id "Primary Monitor" ! set Monitor_${id}(VendorName) Unknown ! set Monitor_${id}(ModelName) Unknown ! set Monitor_${id}(HorizSync) 31.5 ! set Monitor_${id}(VertRefresh) 60 ! set Monitor_${id}(Gamma) "" ! set MonitorIDs [list $id] ! } else { ! set id "Primary Monitor" ! set Monitor_${id}(VendorName) Unknown ! set Monitor_${id}(ModelName) Unknown ! set Monitor_${id}(HorizSync) 24.8 ! set Monitor_${id}(VertRefresh) 56.4 ! set Monitor_${id}(Gamma) "" ! set MonitorIDs [list $id] ! } set id "Primary Card" set Device_${id}(VendorName) Unknown set Device_${id}(BoardName) Unknown ! if !$pc98 { ! set Device_${id}(Server) SVGA ! } else { ! if !$pc98_EGC { ! set Device_${id}(Server) NEC480 ! } else { ! set Device_${id}(Server) EGC ! } ! set uname [exec uname] ! if {$uname == {FreeBSD}} { ! set Pointer(Device) /dev/mse0 ! } elseif {$uname == {NetBSD}} { ! set Pointer(Device) /dev/lms0 ! } ! } foreach key {Chipset Ramdac DacSpeed Clocks ClockChip ClockProg Options VideoRam BIOSBase Membase IOBase DACBase POSBase COPBase VGABase *************** *** 94,111 **** set Scrn_Accel(OffTime) "" set Scrn_Accel(DefaultColorDepth) "" ! array set Scrn_Mono [array get Scrn_Accel] ! array set Scrn_VGA2 [array get Scrn_Accel] array set Scrn_VGA16 [array get Scrn_Accel] array set Scrn_SVGA [array get Scrn_Accel] ! set Scrn_Mono(Driver) "Mono" set Scrn_SVGA(Driver) "SVGA" - set Scrn_VGA2(Driver) "VGA2" set Scrn_VGA16(Driver) "VGA16" ! set Scrn_Mono(Depth,1) 1 ! set Scrn_VGA2(Depth,1) 1 set Scrn_VGA16(Depth,4) 4 foreach depth {8 15 16 24 32} { --- 131,154 ---- set Scrn_Accel(OffTime) "" set Scrn_Accel(DefaultColorDepth) "" ! if !$pc98 { ! array set Scrn_Mono [array get Scrn_Accel] ! array set Scrn_VGA2 [array get Scrn_Accel] ! } array set Scrn_VGA16 [array get Scrn_Accel] array set Scrn_SVGA [array get Scrn_Accel] ! if !$pc98 { ! set Scrn_Mono(Driver) "Mono" ! set Scrn_VGA2(Driver) "VGA2" ! } set Scrn_SVGA(Driver) "SVGA" set Scrn_VGA16(Driver) "VGA16" ! if !$pc98 { ! set Scrn_Mono(Depth,1) 1 ! set Scrn_VGA2(Depth,1) 1 ! } set Scrn_VGA16(Depth,4) 4 foreach depth {8 15 16 24 32} { *************** *** 119,126 **** proc writeXF86Config {filename args} { global Files ServerFlags Keyboard Pointer ! global MonitorIDs DeviceIDs MonitorStdModes global Scrn_Accel Scrn_Mono Scrn_VGA2 Scrn_VGA16 Scrn_SVGA check_tmpdirs set fd [open $filename w] --- 162,170 ---- proc writeXF86Config {filename args} { global Files ServerFlags Keyboard Pointer ! global MonitorIDs DeviceIDs MonitorStdModes SelectedMonitorModes global Scrn_Accel Scrn_Mono Scrn_VGA2 Scrn_VGA16 Scrn_SVGA + global pc98 pc98_EGC haveSelectedModes DefaultColorDepth check_tmpdirs set fd [open $filename w] *************** *** 225,232 **** } elseif { [string length $Pointer(Device)] } { puts $fd " Device \"$Pointer(Device)\"" } ! foreach key {BaudRate Emulate3Timeout SampleRate} { ! if { [string length $Pointer($key)] } { puts $fd [format " %-15s %s" $key $Pointer($key)] } } --- 269,276 ---- } elseif { [string length $Pointer(Device)] } { puts $fd " Device \"$Pointer(Device)\"" } ! foreach key {BaudRate Emulate3Timeout SampleRate Resolution Buttons} { ! if { [string length $Pointer($key)] && $Pointer($key) } { puts $fd [format " %-15s %s" $key $Pointer($key)] } } *************** *** 256,276 **** } set modepattern "None" if { [lsearch -exact $args -vgamode] >= 0 } { ! set modepattern " 640x480*" } if { [lsearch -exact $args -defaultmodes] >= 0 } { set modepattern "*" } if { [string compare None $modepattern] != 0} { ! foreach desc [lsort -decreasing \ ! [array names MonitorStdModes $modepattern]] { set modeline $MonitorStdModes($desc) puts $fd "# $desc" set id [format "%dx%d" \ ! [lindex $modeline 1] [lindex $modeline 5]] puts $fd [format " Modeline %-11s %s" \ ! "\"$id\"" $modeline] lappend modeNames $id } } else { set dispof [lsearch -exact $args -displayof] --- 300,340 ---- } set modepattern "None" if { [lsearch -exact $args -vgamode] >= 0 } { ! if !$pc98_EGC { ! set modepattern " 640x480*" ! } else { ! set modepattern " 640x400*" ! } } if { [lsearch -exact $args -defaultmodes] >= 0 } { set modepattern "*" } if { [string compare None $modepattern] != 0} { ! if { $haveSelectedModes <= 0 } { ! # puts stderr "No selected modes" ! foreach desc [lsort -decreasing \ ! [array names MonitorStdModes $modepattern]] { set modeline $MonitorStdModes($desc) puts $fd "# $desc" set id [format "%dx%d" \ ! [lindex $modeline 1] [lindex $modeline 5]] puts $fd [format " Modeline %-11s %s" \ ! "\"$id\"" $modeline] lappend modeNames $id + } + } else { + foreach desc [lsort -decreasing \ + [array names SelectedMonitorModes $modepattern]] { + set modeline $SelectedMonitorModes($desc) + if ![string match \#removed $modeline] { + puts $fd "# $desc" + set id [format "%dx%d" \ + [lindex $modeline 1] [lindex $modeline 5]] + puts $fd [format " Modeline %-11s %s" \ + "\"$id\"" $modeline] + lappend modeNames $id + } + } } } else { set dispof [lsearch -exact $args -displayof] *************** *** 344,351 **** puts $fd "EndSection" } ! foreach drvr {Accel Mono VGA2 VGA16 SVGA} { if { [string compare $drvr [set Scrn_${drvr}(Driver)]] } \ continue puts $fd "" --- 408,420 ---- puts $fd "EndSection" } ! foreach drvr {Accel SVGA VGA16 VGA2 Mono} { + if $pc98 { + if {![string compare $drvr "Mono"] || \ + ![string compare $drvr "VGA2"]} \ + continue + } if { [string compare $drvr [set Scrn_${drvr}(Driver)]] } \ continue puts $fd "" *************** *** 353,360 **** puts $fd " Driver \"$drvr\"" puts $fd " Device \"[set Scrn_${drvr}(Device)]\"" puts $fd " Monitor \"[set Scrn_${drvr}(Monitor)]\"" ! foreach key {ScreenNo BlankTime SuspendTime OffTime \ ! DefaultColorDepth} { if { [string length [set Scrn_${drvr}($key)]] } { puts $fd [format " %-15s %s" \ $key [set Scrn_${drvr}($key)] ] --- 422,432 ---- puts $fd " Driver \"$drvr\"" puts $fd " Device \"[set Scrn_${drvr}(Device)]\"" puts $fd " Monitor \"[set Scrn_${drvr}(Monitor)]\"" ! if { ![string compare $drvr "Accel"] || ! ![string compare $drvr "SVGA"] } { ! puts $fd " DefaultColorDepth $DefaultColorDepth" ! } ! foreach key {ScreenNo BlankTime SuspendTime OffTime } { if { [string length [set Scrn_${drvr}($key)]] } { puts $fd [format " %-15s %s" \ $key [set Scrn_${drvr}($key)] ] *************** *** 420,430 **** } proc create_main_window { w } { toplevel $w ! $w configure -height 480 -width 640 -highlightthickness 0 pack propagate $w no wm geometry $w +0+0 ! #wm minsize $w 640 480 } proc set_default_arrow_bindings { } { --- 492,512 ---- } proc create_main_window { w } { + global pc98_EGC + toplevel $w ! if !$pc98_EGC { ! $w configure -height 480 -width 640 -highlightthickness 0 ! } else { ! $w configure -height 400 -width 640 -highlightthickness 0 ! } pack propagate $w no wm geometry $w +0+0 ! if !$pc98_EGC { ! #wm minsize $w 640 480 ! } else { ! #wm minsize $w 640 400 ! } } proc set_default_arrow_bindings { } { *************** *** 437,443 **** } proc start_server { server configfile outfile } { ! global env TmpDir Xwinhome serverNumber if { ![info exists serverNumber] } { set serverNumber 7 --- 519,525 ---- } proc start_server { server configfile outfile } { ! global env TmpDir Xwinhome serverNumber pc98 if { ![info exists serverNumber] } { set serverNumber 7 *************** *** 446,454 **** } set env(DISPLAY) [set disp :$serverNumber] ! set pid [exec $Xwinhome/bin/XF86_$server $disp \ ! -allowMouseOpenFail -xf86config $configfile \ ! -bestRefresh >& $TmpDir/$outfile & ] sleep 9 set trycount 0 --- 528,542 ---- } set env(DISPLAY) [set disp :$serverNumber] ! if !$pc98 { ! set pid [exec $Xwinhome/bin/XF86_$server $disp \ ! -allowMouseOpenFail -xf86config $configfile \ ! -bestRefresh >& $TmpDir/$outfile & ] ! } else { ! set pid [exec $Xwinhome/bin/XF98_$server $disp \ ! -allowMouseOpenFail -xf86config $configfile \ ! -bestRefresh >& $TmpDir/$outfile & ] ! } sleep 9 set trycount 0 *************** *** 528,539 **** } proc save_state {} { ! global env XF86SetupDir TmpDir StateFileName PID set StateFileName "$TmpDir/state" check_tmpdirs set fd [open $StateFileName w] global Dialog Confname ConfigFile UseConfigFile StartServer puts $fd [list set Dialog $Dialog] puts $fd [list set Confname $Confname] puts $fd [list set ConfigFile $ConfigFile] --- 616,629 ---- } proc save_state {} { ! global env XF86SetupDir TmpDir StateFileName PID set StateFileName "$TmpDir/state" check_tmpdirs set fd [open $StateFileName w] global Dialog Confname ConfigFile UseConfigFile StartServer + global pc98 + puts $fd [list set Dialog $Dialog] puts $fd [list set Confname $Confname] puts $fd [list set ConfigFile $ConfigFile] *************** *** 542,552 **** puts $fd [list set XF86SetupDir $XF86SetupDir] puts $fd [list set TmpDir $TmpDir] puts $fd [list set PID $PID] ! global DeviceIDs MonitorIDs puts $fd [list set DeviceIDs $DeviceIDs] puts $fd [list set MonitorIDs $MonitorIDs] ! set arrlist [list Files ServerFlags Keyboard Pointer \ ! Scrn_Accel Scrn_Mono Scrn_VGA2 Scrn_VGA16 Scrn_SVGA] foreach devid $DeviceIDs { lappend arrlist Device_$devid } --- 632,651 ---- puts $fd [list set XF86SetupDir $XF86SetupDir] puts $fd [list set TmpDir $TmpDir] puts $fd [list set PID $PID] ! global DeviceIDs MonitorIDs haveSelectedModes DefaultColorDepth puts $fd [list set DeviceIDs $DeviceIDs] puts $fd [list set MonitorIDs $MonitorIDs] ! puts $fd [list set DefaultColorDepth $DefaultColorDepth] ! puts $fd [list set haveSelectedModes $haveSelectedModes] ! if !$pc98 { ! set arrlist [list Files ServerFlags Keyboard Pointer \ ! SelectedMonitorModes MonitorStdModes \ ! Scrn_Accel Scrn_Mono Scrn_VGA2 Scrn_VGA16 Scrn_SVGA] ! } else { ! set arrlist [list Files ServerFlags Keyboard Pointer \ ! SelectedMonitorModes MonitorStdModes \ ! Scrn_Accel Scrn_VGA16 Scrn_SVGA] ! } foreach devid $DeviceIDs { lappend arrlist Device_$devid } *** ./programs/Xserver/hw/xfree86/XF86Setup/srvflags.tcl@@/PUBLIC-LATEST Sat Jul 19 09:23:55 1997 --- xc/programs/Xserver/hw/xfree86/XF86Setup/srvflags.tcl Fri Mar 6 16:28:22 1998 *************** *** 1,9 **** ! # $TOG: srvflags.tcl /main/3 1997/07/19 09:23:57 kaleb $ # # # # ! # $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/srvflags.tcl,v 3.4 1996/12/27 06:54:14 dawes Exp $ # # Copyright 1996 by Joseph V. Moss # --- 1,9 ---- ! # $TOG: srvflags.tcl /main/4 1998/03/06 16:30:00 kaleb $ # # # # ! # $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/srvflags.tcl,v 3.4.2.2 1998/02/21 06:07:02 robin Exp $ # # Copyright 1996 by Joseph V. Moss # *************** *** 18,54 **** proc Other_create_widgets { win } { global ServerFlags otherZap otherZoom otherTrapSignals global otherXvidtune otherInpDevMods set w [winpathprefix $win] frame $w.other -width 640 -height 420 \ -relief ridge -borderwidth 5 - frame $w.srvflags -bd 2 -relief sunken ! pack $w.srvflags -in $w.other \ ! -fill both -expand yes -padx 20m -pady 20m ! label $w.srvflags.title -text "Optional server settings\n\n\ ! These should be set to reasonable values, by default,\n\ ! so you probably don't need to change anything" pack $w.srvflags.title -side top -fill both -expand yes frame $w.srvflags.line -height 2 -bd 2 -relief sunken pack $w.srvflags.line -side top -fill x -pady 2m checkbutton $w.srvflags.zap -indicatoron true \ ! -text "Allow server to be killed with\ ! hotkey sequence (Ctrl-Alt-Backspace)" \ -variable otherZap -anchor w checkbutton $w.srvflags.zoom -indicatoron true \ ! -text "Allow video mode switching" \ -variable otherZoom -anchor w checkbutton $w.srvflags.trapsignals -indicatoron true \ ! -text "Don't Trap Signals\ ! - prevents the server from exitting cleanly" \ -variable otherTrapSignals -anchor w checkbutton $w.srvflags.nonlocalxvidtune -indicatoron true \ ! -text "Allow video mode changes from other hosts" \ -variable otherXvidtune -anchor w checkbutton $w.srvflags.nonlocalmodindev -indicatoron true \ ! -text "Allow changes to keyboard and mouse settings\ ! from other hosts" -variable otherInpDevMods -anchor w pack $w.srvflags.zap $w.srvflags.zoom $w.srvflags.trapsignals \ -anchor w -expand yes -fill x -padx 15m pack $w.srvflags.nonlocalxvidtune $w.srvflags.nonlocalmodindev \ --- 18,56 ---- proc Other_create_widgets { win } { global ServerFlags otherZap otherZoom otherTrapSignals global otherXvidtune otherInpDevMods + global pc98_EGC messages set w [winpathprefix $win] frame $w.other -width 640 -height 420 \ -relief ridge -borderwidth 5 frame $w.srvflags -bd 2 -relief sunken ! if !$pc98_EGC { ! pack $w.srvflags -in $w.other \ ! -fill both -expand yes -padx 20m -pady 20m ! } else { ! pack $w.srvflags -in $w.other \ ! -fill both -expand yes -padx 20m -pady 5m ! $w.other configure -height 400 ! } ! label $w.srvflags.title -text $messages(srvflags.1) pack $w.srvflags.title -side top -fill both -expand yes frame $w.srvflags.line -height 2 -bd 2 -relief sunken pack $w.srvflags.line -side top -fill x -pady 2m checkbutton $w.srvflags.zap -indicatoron true \ ! -text $messages(srvflags.2) \ -variable otherZap -anchor w checkbutton $w.srvflags.zoom -indicatoron true \ ! -text $messages(srvflags.3) \ -variable otherZoom -anchor w checkbutton $w.srvflags.trapsignals -indicatoron true \ ! -text $messages(srvflags.4) \ -variable otherTrapSignals -anchor w checkbutton $w.srvflags.nonlocalxvidtune -indicatoron true \ ! -text $messages(srvflags.5) \ -variable otherXvidtune -anchor w checkbutton $w.srvflags.nonlocalmodindev -indicatoron true \ ! -text $messages(srvflags.6) \ ! -variable otherInpDevMods -anchor w pack $w.srvflags.zap $w.srvflags.zoom $w.srvflags.trapsignals \ -anchor w -expand yes -fill x -padx 15m pack $w.srvflags.nonlocalxvidtune $w.srvflags.nonlocalmodindev \ *************** *** 83,107 **** [expr $otherXvidtune?"AllowNonLocalXvidtune":""] set ServerFlags(AllowNonLocalModInDev) \ [expr $otherInpDevMods?"AllowNonLocalModInDev":""] - } - - proc Other_popup_help { win } { - catch {destroy .otherhelp} - toplevel .otherhelp -bd 5 -relief ridge - wm title .otherhelp "Help" - wm geometry .otherhelp +30+30 - text .otherhelp.text - .otherhelp.text insert 0.0 "\n\n\ - On this screen you can select the settings of various\ - server options.\n\ - These should already be set to the values most often used\n\ - and generally you don't need to make any changes.\n\n\ - If you would like more information regarding what each\ - of these do,\n\ - read the XF86Config man page." - .otherhelp.text configure -state disabled - button .otherhelp.ok -text "Dismiss" -command "destroy .otherhelp" - focus .otherhelp.ok - pack .otherhelp.text .otherhelp.ok } --- 85,89 ---- *** ./programs/Xserver/hw/xfree86/XF86Setup/tcllib/tk.tcl@@/PUBLIC-LATEST Sat Jul 19 09:25:27 1997 --- xc/programs/Xserver/hw/xfree86/XF86Setup/tcllib/tk.tcl Fri Mar 6 16:28:44 1998 *************** *** 1,9 **** ! # $TOG: tk.tcl /main/2 1997/07/19 09:25:28 kaleb $ # # # # ! # $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/tcllib/tk.tcl,v 3.2 1996/12/27 06:55:09 dawes Exp $ # # tk.tcl -- # --- 1,9 ---- ! # $TOG: tk.tcl /main/3 1998/03/06 16:30:22 kaleb $ # # # # ! # $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/tcllib/tk.tcl,v 3.2.2.1 1998/02/15 16:08:59 hohndel Exp $ # # tk.tcl -- # *************** *** 21,32 **** # Insist on running with compatible versions of Tcl and Tk. scan [info tclversion] "%d.%d" a b ! if {$a != 7} { ! error "wrong version of Tcl loaded ([info tclversion]): need 7.x" } scan $tk_version "%d.%d" a b ! if {($a != 4) || ($b < 0)} { ! error "wrong version of Tk loaded ($tk_version): need 4.x" } unset a b --- 21,32 ---- # Insist on running with compatible versions of Tcl and Tk. scan [info tclversion] "%d.%d" a b ! if {$a < 7 || ($a == 7 && $b < 5)} { ! error "wrong version of Tcl loaded ([info tclversion]): need 7.5 or later" } scan $tk_version "%d.%d" a b ! if {($a < 4) || ($a == 4 && $b < 1)} { ! error "wrong version of Tk loaded ($tk_version): need 4.1 or later" } unset a b *** ./programs/Xserver/hw/xfree86/XF86Setup/tclmisc.c@@/PUBLIC-LATEST Sun Aug 10 12:57:34 1997 --- xc/programs/Xserver/hw/xfree86/XF86Setup/tclmisc.c Fri Mar 6 16:28:26 1998 *************** *** 4,10 **** ! /* $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/tclmisc.c,v 3.6.2.2 1997/07/26 06:30:45 dawes Exp $ */ /* * Copyright 1996 by Joseph V. Moss * --- 4,10 ---- ! /* $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/tclmisc.c,v 3.6.2.5 1998/02/25 14:26:50 dawes Exp $ */ /* * Copyright 1996 by Joseph V. Moss * *************** *** 308,314 **** static char *msetable[] = { "None", "Microsoft", "MouseSystems", "MMSeries", "Logitech", "BusMouse", "Mouseman", "PS/2", "MMHitTab", "GlidePoint", "IntelliMouse", ! "Unknown", "Xqueue", "OSMouse" }; #define MSETABLESIZE (sizeof(msetable)/sizeof(char *)) /* --- 308,317 ---- static char *msetable[] = { "None", "Microsoft", "MouseSystems", "MMSeries", "Logitech", "BusMouse", "Mouseman", "PS/2", "MMHitTab", "GlidePoint", "IntelliMouse", ! "ThinkingMouse", "IMPS/2", "ThinkingMousePS/2", ! "MouseManPlusPS/2", "GlidePointPS/2", ! "NetMousePS/2", "NetScrollPS/2", "SysMouse", ! "Auto", "Xqueue", "OSMouse" }; #define MSETABLESIZE (sizeof(msetable)/sizeof(char *)) /* *************** *** 341,352 **** (char *) NULL); return TCL_ERROR; } else { ! if ( mseinfo.type < 0 || mseinfo.type >= MSETABLESIZE) ! mseinfo.type = 10; /* Unknown */ ! sprintf(tmpbuf, "%s %s %d %d %s %d %s", mseinfo.device==NULL? "{}": mseinfo.device, ! msetable[mseinfo.type+1], mseinfo.baudrate, mseinfo.samplerate, mseinfo.emulate3buttons? "on": "off", mseinfo.emulate3timeout, mseinfo.chordmiddle? "on": "off"); --- 344,363 ---- (char *) NULL); return TCL_ERROR; } else { ! char *name; ! if (mseinfo.type == MTYPE_XQUEUE) ! name = "Xqueue"; ! else if (mseinfo.type == MTYPE_OSMOUSE) ! name = "OSMouse"; ! else if (mseinfo.type < 0 || (mseinfo.type >= MSETABLESIZE)) ! name = "Unknown"; ! else ! name = msetable[mseinfo.type+1]; ! sprintf(tmpbuf, "%s %s %d %d %d %d %s %d %s", mseinfo.device==NULL? "{}": mseinfo.device, ! name, mseinfo.baudrate, mseinfo.samplerate, + mseinfo.resolution, mseinfo.buttons, mseinfo.emulate3buttons? "on": "off", mseinfo.emulate3timeout, mseinfo.chordmiddle? "on": "off"); *************** *** 369,376 **** static char *setmouseusage = "Usage: xf86misc_setmouse " ! " on|off " ! " on|off [ClearDTR] [ClearRTS] [ReOpen]"; int TCL_XF86MiscSetMouseSettings(clientData, interp, argc, argv) --- 380,387 ---- static char *setmouseusage = "Usage: xf86misc_setmouse " ! " " ! " on|off on|off [ClearDTR] [ClearRTS] [ReOpen]"; int TCL_XF86MiscSetMouseSettings(clientData, interp, argc, argv) *************** *** 383,389 **** int i; Tk_Window tkwin; ! if (argc < 8 || argc > 11) { Tcl_SetResult(interp, setmouseusage, TCL_STATIC); return TCL_ERROR; } --- 394,400 ---- int i; Tk_Window tkwin; ! if (argc < 9 || argc > 12) { Tcl_SetResult(interp, setmouseusage, TCL_STATIC); return TCL_ERROR; } *************** *** 397,402 **** --- 408,417 ---- mseinfo.type = i - 1; } } + if (!StrCaseCmp("Xqueue", argv[2])) + mseinfo.type = MTYPE_XQUEUE; + else if (!StrCaseCmp("OSMouse", argv[2])) + mseinfo.type = MTYPE_OSMOUSE; if (mseinfo.type == -1) { Tcl_AppendResult(interp, "Invalid mouse type\n", setmouseusage, (char *) NULL); *************** *** 404,412 **** } mseinfo.baudrate = atoi(argv[3]); mseinfo.samplerate = atoi(argv[4]); ! if (!StrCaseCmp(argv[5], "on")) mseinfo.emulate3buttons = 1; ! else if (!StrCaseCmp(argv[5], "off")) mseinfo.emulate3buttons = 0; else { Tcl_AppendResult(interp, "Option must be either on or off\n", --- 419,429 ---- } mseinfo.baudrate = atoi(argv[3]); mseinfo.samplerate = atoi(argv[4]); ! mseinfo.resolution = atoi(argv[5]); ! mseinfo.buttons = atoi(argv[6]); ! if (!StrCaseCmp(argv[7], "on")) mseinfo.emulate3buttons = 1; ! else if (!StrCaseCmp(argv[7], "off")) mseinfo.emulate3buttons = 0; else { Tcl_AppendResult(interp, "Option must be either on or off\n", *************** *** 413,422 **** setmouseusage, (char *) NULL); return TCL_ERROR; } ! mseinfo.emulate3timeout = atoi(argv[6]); ! if (!StrCaseCmp(argv[7], "on")) mseinfo.chordmiddle = 1; ! else if (!StrCaseCmp(argv[7], "off")) mseinfo.chordmiddle = 0; else { Tcl_AppendResult(interp, "Option must be either on or off\n", --- 430,439 ---- setmouseusage, (char *) NULL); return TCL_ERROR; } ! mseinfo.emulate3timeout = atoi(argv[8]); ! if (!StrCaseCmp(argv[9], "on")) mseinfo.chordmiddle = 1; ! else if (!StrCaseCmp(argv[9], "off")) mseinfo.chordmiddle = 0; else { Tcl_AppendResult(interp, "Option must be either on or off\n", *************** *** 424,430 **** return TCL_ERROR; } mseinfo.flags = 0; ! for (i = 8; i < argc; i++) { if (!StrCaseCmp(argv[i], "cleardtr")) mseinfo.flags |= MF_CLEAR_DTR; else if (!StrCaseCmp(argv[i], "clearrts")) --- 441,447 ---- return TCL_ERROR; } mseinfo.flags = 0; ! for (i = 10; i < argc; i++) { if (!StrCaseCmp(argv[i], "cleardtr")) mseinfo.flags |= MF_CLEAR_DTR; else if (!StrCaseCmp(argv[i], "clearrts")) *** ./programs/Xserver/hw/xfree86/XF86Setup/tclxfconf.c@@/PUBLIC-LATEST Sun Aug 10 12:57:39 1997 --- xc/programs/Xserver/hw/xfree86/XF86Setup/tclxfconf.c Fri Mar 6 16:28:30 1998 *************** *** 1,4 **** ! /* $TOG: tclxfconf.c /main/5 1997/08/10 12:56:14 kaleb $ */ --- 1,4 ---- ! /* $TOG: tclxfconf.c /main/6 1998/03/06 16:30:08 kaleb $ */ *************** *** 5,11 **** ! /* $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/tclxfconf.c,v 3.15.2.4 1997/08/01 13:46:01 dawes Exp $ */ /* * Copyright 1996 by Joseph V. Moss * --- 5,11 ---- ! /* $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/tclxfconf.c,v 3.15.2.5 1998/02/15 16:08:56 hohndel Exp $ */ /* * Copyright 1996 by Joseph V. Moss * *************** *** 514,520 **** #define StrOrNull(xx) ((xx)==NULL? "": (xx)) static char *msetypes[] = { "None", "Microsoft", "MouseSystems", "MMSeries", "Logitech", "BusMouse", "Mouseman", "PS/2", "MMHitTab", ! "GlidePoint", "IntelliMouse", "Unknown", "Xqueue", "OSMouse" }; int --- 514,522 ---- #define StrOrNull(xx) ((xx)==NULL? "": (xx)) static char *msetypes[] = { "None", "Microsoft", "MouseSystems", "MMSeries", "Logitech", "BusMouse", "Mouseman", "PS/2", "MMHitTab", ! "GlidePoint", "IntelliMouse", "ThinkingMouse", "IMPS/2", ! "ThinkingMousePS/2", "MouseManPlusPS/2", "GlidePointPS/2", ! "NetMousePS/2", "NetScrollPS/2", "SysMouse", "Auto", }; int *************** *** 683,699 **** char *varname; { char tmpbuf[16]; #ifdef XQUEUE if (xf86Info.mouseDev->mseProc == xf86XqueMseProc) ! xf86Info.mouseDev->mseType = 11; #endif #if defined(USE_OSMOUSE) || defined(OSMOUSE_ONLY) if (xf86Info.mouseDev->mseProc == xf86OsMouseProc) ! xf86Info.mouseDev->mseType = 12; #endif ! Tcl_SetVar2(interp, "mouse", "Protocol", ! msetypes[xf86Info.mouseDev->mseType+1], 0); Tcl_SetVar2(interp, "mouse", "Device", StrOrNull(xf86Info.mouseDev->mseDevice), 0); sprintf(tmpbuf, "%d", xf86Info.mouseDev->baudRate); --- 685,704 ---- char *varname; { char tmpbuf[16]; + char *name; + name = NULL; #ifdef XQUEUE if (xf86Info.mouseDev->mseProc == xf86XqueMseProc) ! name = "Xqueue"; #endif #if defined(USE_OSMOUSE) || defined(OSMOUSE_ONLY) if (xf86Info.mouseDev->mseProc == xf86OsMouseProc) ! name = "OSMouse"; #endif ! if (name == NULL) ! name = msetypes[xf86Info.mouseDev->mseType + 1]; ! Tcl_SetVar2(interp, "mouse", "Protocol", name, 0); Tcl_SetVar2(interp, "mouse", "Device", StrOrNull(xf86Info.mouseDev->mseDevice), 0); sprintf(tmpbuf, "%d", xf86Info.mouseDev->baudRate); *************** *** 700,705 **** --- 705,712 ---- Tcl_SetVar2(interp, "mouse", "BaudRate", tmpbuf, 0); sprintf(tmpbuf, "%d", xf86Info.mouseDev->sampleRate); Tcl_SetVar2(interp, "mouse", "SampleRate", tmpbuf, 0); + sprintf(tmpbuf, "%d", xf86Info.mouseDev->resolution); + Tcl_SetVar2(interp, "mouse", "Resolution", tmpbuf, 0); Tcl_SetVar2(interp, "mouse", "Emulate3Buttons", xf86Info.mouseDev->emulate3Buttons? "Emulate3Buttons": "", 0); sprintf(tmpbuf, "%d", xf86Info.mouseDev->emulate3Timeout); *** /dev/null Tue Jun 30 11:43:45 1998 --- xc/programs/Xserver/hw/xfree86/XF86Setup/texts/Imakefile Fri Mar 6 16:28:49 1998 *************** *** 0 **** --- 1,25 ---- + XCOMM $TOG: Imakefile /main/1 1998/03/06 16:30:26 kaleb $ + + + + + XCOMM + XCOMM $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/texts/Imakefile,v 1.1.2.2 1998/02/26 20:11:16 hohndel Exp $ + XCOMM + + #include + #define IHaveSubdirs + + XF86SETUPLIBDIR = $(LIBDIR)/XF86Setup + SCRIPTSDIR = $(XF86SETUPLIBDIR)/texts + + SCRIPTFILES = local_text.tcl + + SUBDIRS = generic ja + + all:: + + InstallMultiple($(SCRIPTFILES),$(SCRIPTSDIR)) + + MakeSubdirs($(SUBDIRS)) + DependSubdirs($(SUBDIRS)) *** /dev/null Tue Jun 30 11:43:46 1998 --- xc/programs/Xserver/hw/xfree86/XF86Setup/texts/local_text.tcl Fri Mar 6 16:28:56 1998 *************** *** 0 **** --- 1,137 ---- + # $TOG: local_text.tcl /main/1 1998/03/06 16:30:34 kaleb $ + + + + + # + # $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/texts/local_text.tcl,v 1.1.2.3 1998/02/26 20:11:16 hohndel Exp $ + # + proc Make_popup_help { file } { + global pc98 pc98_EGC messages + + set win .help_$file + # get 'message' variable. + source [Find_local_text help_$file.tcl] + + catch {destroy $win} + toplevel $win -bd 5 -relief ridge + wm title $win "Help" + if !$pc98_EGC { + wm geometry $win 590x430+30+20 + } else { + $win configure -height 350 + wm geometry $win 590x350+30+20 + } + text $win.text -takefocus 0 -width 90 -height 30 \ + -yscrollcommand [list $win.sb set] + scrollbar $win.sb -command [list $win.text yview] + bind $win \ + "$win.text yview scroll -1 unit ; break ;" + bind $win \ + "$win.text yview scroll 1 unit ; break ;" + $win.text insert 0.0 $message + $win.text configure -state disabled + button $win.ok -text $messages(phase2.13) \ + -command "destroy $win" + pack $win.ok -side bottom + pack $win.text -side left -fill both -expand yes + pack $win.text $win.ok + focus $win.ok + } + + proc append_helppath { newlang } { + upvar rootdir r + upvar lang l + global helppath + + set l $newlang + if [file isdirectory $r/$l] { + lappend helppath $r/$l + } + } + + proc Make_local_directory {} { + global locale helppath XF86Setup_library + set rootdir $XF86Setup_library/texts + if {[info exists locale]} { + append_helppath $locale + while {[set pt [string last . $lang]] != -1} { + append_helppath [string range $lang 0 [expr $pt-1]] + } + if {[set pt [string first _ $lang]] != -1} { + append_helppath [string range $lang 0 [expr $pt-1]] + } + } + append_helppath generic + } + + proc Read_locale {} { + global env Xwinhome locale + set locale_dir $Xwinhome/lib/X11/locale + set locale {} + if {[info exists env(LANG)]} { + if {[file readable $locale_dir/locale.alias]} { + set cmd {[ \t]+/ {print $2;}} + set cmd "/^$env(LANG)$cmd"; + set locale [exec awk $cmd $locale_dir/locale.alias] + } + if {$locale == {} } { + set locale $env(LANG) + } + } + } + + proc Find_local_text {filename} { + global helppath + foreach path $helppath { + if [file exists $path/$filename] { + if {[file readable $path/$filename] && \ + [file isfile $path/$filename]} { + return $path/$filename + } + } + } + return /dev/null + } + + proc Card_popup_help { win } { + global cardDetail + Make_popup_help card + if {$cardDetail != "std"} { + pack .help_card.sb -side right -fill y + } + } + + proc Done_popup_help { win } { + Make_popup_help done + } + + proc Keyboard_popup_help { win } { + Make_popup_help keyboard + } + + proc Monitor_popup_help { win } { + Make_popup_help monitor + } + + proc Other_popup_help { win } { + Make_popup_help other + } + + proc Intro_popup_help { win } { + Make_popup_help intro + } + + proc Mouse_popup_help { win } { + Make_popup_help mouse + pack .help_mouse.sb -side right -fill y + } + + proc Modeselection_popup_help { win } { + Make_popup_help modeselect + } + + Read_locale + Make_local_directory + source [Find_local_text messages.tcl] + source [Find_local_text message_proc.tcl] *** /dev/null Tue Jun 30 11:43:47 1998 --- xc/programs/Xserver/hw/xfree86/XF86Setup/texts/generic/Imakefile Fri Mar 6 16:29:00 1998 *************** *** 0 **** --- 1,19 ---- + XCOMM $TOG: Imakefile /main/1 1998/03/06 16:30:39 kaleb $ + + + + + XCOMM + XCOMM $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/texts/generic/Imakefile,v 1.1.2.2 1998/02/26 20:11:17 hohndel Exp $ + XCOMM + XF86SETUPLIBDIR = $(LIBDIR)/XF86Setup + SCRIPTSDIR = $(XF86SETUPLIBDIR)/texts/generic + + SCRIPTFILES = messages.tcl message_proc.tcl \ + help_card.tcl help_done.tcl help_keyboard.tcl \ + help_monitor.tcl help_mouse.tcl help_other.tcl \ + help_intro.tcl help_modeselect.tcl + + all:: + + InstallMultiple($(SCRIPTFILES),$(SCRIPTSDIR)) *** /dev/null Tue Jun 30 11:43:48 1998 --- xc/programs/Xserver/hw/xfree86/XF86Setup/texts/generic/help_card.tcl Fri Mar 6 16:29:05 1998 *************** *** 0 **** --- 1,60 ---- + # $TOG: help_card.tcl /main/1 1998/03/06 16:30:42 kaleb $ + + + + + # $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/texts/generic/help_card.tcl,v 1.1.2.2 1998/02/26 20:11:17 hohndel Exp $ + # + global cardDetail + + if { $cardDetail == "std" } { + set message "\n\n\ + Pick your card from the list.\n\n\ + If there are README files that may pertain to your card\n\ + the 'Read README file' button will then be usable (i.e. not\ + greyed out).\n\ + Please read them.\n\n\ + If your card is not in the list, or if there are any\ + special settings\n\ + listed in the README file as required by your card, you\ + can press the\n\ + 'Detailed Setup' button to make sure that\ + they have been selected." + } else { + global DeviceIDs + if { [llength $DeviceIDs] > 1 } { + set message \ + " If you picked a card from the Card list, at least most\ + things should\n\ + already be set properly.\n\n" + } else { + set message "\n\n" + } + append message \ + " First select the appropriate server for your card.\n\ + Then read the README file corresponding to the selected\ + server by pressing\n\ + the 'Read README file' button (it won't do anything, if\ + there is no README).\n\n\ + Next, pick the chipset, and Ramdac of your card, if\ + directed by the README\n\ + file. In most cases, you don't need to select these,\ + as the server will\n\ + detect (probe) them automatically.\n\n\ + The clockchip should generally be picked, if your card\ + has one, as these\n\ + are often impossible to probe (the exception is when\ + the clockchip is built\n\ + into one of the other chips).\n\n\ + Choose whatever options are appropriate (again,\ + according to the README).\n\n\ + You can also set the maximum speed of your Ramdac. Some\ + Ramdacs are available\n\ + with various speed ratings. The max speed cannot be\ + detected by the server\n\ + so it will use the speed rating of the slowest version\ + of the specified Ramdac.\n\n\ + Additionally, you can also specify the amount of RAM on\ + your card, though\n\ + the server will usually be able to detect this." + } *** /dev/null Tue Jun 30 11:43:49 1998 --- xc/programs/Xserver/hw/xfree86/XF86Setup/texts/generic/help_done.tcl Fri Mar 6 16:29:08 1998 *************** *** 0 **** --- 1,17 ---- + # $TOG: help_done.tcl /main/1 1998/03/06 16:30:46 kaleb $ + + + + + # $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/texts/generic/help_done.tcl,v 1.1.2.2 1998/02/26 20:11:18 hohndel Exp $ + # + set message "\n\n\ + If you've finished configuring everything, select the\ + 'Okay' button.\n\n\ + If there are still some configuration screens you\ + have not completed,\n\ + pick the appropriate button from the row across the top\ + and then press\n\ + 'Done' again, when you've finished all of the\ + configuration screens." + *** /dev/null Tue Jun 30 11:43:50 1998 --- xc/programs/Xserver/hw/xfree86/XF86Setup/texts/generic/help_intro.tcl Fri Mar 6 16:29:12 1998 *************** *** 0 **** --- 1,28 ---- + # $TOG: help_intro.tcl /main/1 1998/03/06 16:30:50 kaleb $ + + + + + # $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/texts/generic/help_intro.tcl,v 1.1.2.2 1998/02/26 20:11:18 hohndel Exp $ + # + set message "\n\ + You need to fill in the requested information on each\ + of the five\n\ + configuration screens. The buttons along the top allow\ + you to choose which\n\ + screen you are going to work on. You can do them in\ + any order or go back\n\ + to each of them as many times as you like, however,\ + it will be very\n\ + difficult to use some of them if your mouse is not\ + working, so you\n\ + should configure your mouse first.\n\n\ + Until you get your mouse working, here are some keys you\ + can use:\n\n\ + \ \ Tab, Ctrl-Tab Move to the \"next\" widget\n\ + \ \ Shift-Tab Move to the \"previous\" widget\n\ + \ \ Move in the appropriate direction\n\ + \ \ Return Activate the selected widget\n\n\ + Also, you can press Alt and one of the underlined letters\ + to activate the\n\ + corresponding button." *** /dev/null Tue Jun 30 11:43:51 1998 --- xc/programs/Xserver/hw/xfree86/XF86Setup/texts/generic/help_keyboard.tcl Fri Mar 6 16:29:16 1998 *************** *** 0 **** --- 1,14 ---- + # $TOG: help_keyboard.tcl /main/1 1998/03/06 16:30:53 kaleb $ + + + + + # $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/texts/generic/help_keyboard.tcl,v 1.1.2.2 1998/02/26 20:11:18 hohndel Exp $ + # + set message "\n\n\n\ + First select the model of keyboard that you have (or\ + the closest equivalent).\n\ + The small graphic will automatically be updated.\n\n\ + Next select the layout and any variant or options desired.\n\n\ + Pressing the 'Apply' button will cause the selected\ + settings to take effect." *** /dev/null Tue Jun 30 11:43:53 1998 --- xc/programs/Xserver/hw/xfree86/XF86Setup/texts/generic/help_modeselect.tcl Fri Mar 6 16:29:19 1998 *************** *** 0 **** --- 1,19 ---- + # $TOG: help_modeselect.tcl /main/1 1998/03/06 16:30:57 kaleb $ + + + + + # $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/texts/generic/help_modeselect.tcl,v 1.1.2.3 1998/02/26 20:11:18 hohndel Exp $ + # + set message "\n\n\ + XFree86 supports multiple modes that you can cycle\n\ + through while running the X server (on hardware that supports this).\n\ + Click on the modes that you want to have included in your\n\ + configuration.\n\ + \n\ + Additionally, you can select the default color depth the server \n\ + starts in when no overriding flags are given on the command line.\n\ + Be aware that XF86Setup may fail if you select a color depth that\n\ + your hardware (or the server that you have chosen) does not support.\n" + + *** /dev/null Tue Jun 30 11:43:54 1998 --- xc/programs/Xserver/hw/xfree86/XF86Setup/texts/generic/help_monitor.tcl Fri Mar 6 16:29:23 1998 *************** *** 0 **** --- 1,19 ---- + # $TOG: help_monitor.tcl /main/1 1998/03/06 16:31:01 kaleb $ + + + + + # $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/texts/generic/help_monitor.tcl,v 1.1.2.2 1998/02/26 20:11:19 hohndel Exp $ + # + set message "\n\n\n\ + Enter the horizontal and vertical sync rates of your\n\ + monitor. These should be listed in your manual.\n\n\ + If you can not find this information, you can pick from the\n\ + the list of common monitor capabilities, the one that best\n\ + describes your monitor, and the appropriate sync rates\n\ + will be filled in for you.\n\n\ + It is very important that these values be correct!\n\n\ + Using video modes that require sync rates beyond the\n\ + capabilities of your monitor may damage it.\n\ + The server will automatically exclude any video modes\n\ + that require sync rates beyond those you enter." *** /dev/null Tue Jun 30 11:43:55 1998 --- xc/programs/Xserver/hw/xfree86/XF86Setup/texts/generic/help_mouse.tcl Fri Mar 6 16:29:27 1998 *************** *** 0 **** --- 1,43 ---- + # $TOG: help_mouse.tcl /main/1 1998/03/06 16:31:04 kaleb $ + + + + + # $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/texts/generic/help_mouse.tcl,v 1.1.2.4 1998/02/26 20:11:19 hohndel Exp $ + # + set message \ + { First select the protocol for your mouse using 'p', then if needed, change the device + name. If applicable, also set the baud rate (1200 should work). Avoid moving the + mouse or pressing buttons before the correct protocol has been selected. Press 'a' + to apply the changes and try moving your mouse around. If the mouse pointer does + not move properly, try a different protocol or device name. + + Once the mouse is moving properly, test that the various buttons also work correctly. + If you have a three button mouse and the middle button does not work, try the buttons + labeled ChordMiddle and Emulate3Buttons. + + Note: the `Logitech' protocol is only used by older Logitech mice. Most current + models use the `Microsoft' or `MouseMan' protocol. + + Key Function + ------------------------------------------------------ + a - Apply changes + b - Change to next baud rate + c - Toggle the ChordMiddle button + d - Toggle the ClearDTR button + e - Toggle the Emulate3button button + l - Select the next resolution + n - Set the name of the device + p - Select the next protocol + r - Toggle the ClearRTS button + s - Increase the sample rate + t - Increase the 3-button emulation timeout + 3 - Set buttons to 3 + 4 - Set buttons to 4 + 5 - Set buttons to 5 + ------------------------------------------------------ + You can also use Tab, and Shift-Tab to move around and then use Enter to activate + the selected button. + + See the documentation for more information + } *** /dev/null Tue Jun 30 11:43:56 1998 --- xc/programs/Xserver/hw/xfree86/XF86Setup/texts/generic/help_other.tcl Fri Mar 6 16:29:30 1998 *************** *** 0 **** --- 1,15 ---- + # $TOG: help_other.tcl /main/1 1998/03/06 16:31:08 kaleb $ + + + + + # $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/texts/generic/help_other.tcl,v 1.1.2.2 1998/02/26 20:11:19 hohndel Exp $ + # + set message "\n\n\ + On this screen you can select the settings of various\ + server options.\n\ + These should already be set to the values most often used\n\ + and generally you don't need to make any changes.\n\n\ + If you would like more information regarding what each\ + of these do,\n\ + read the XF86Config man page." *** /dev/null Tue Jun 30 11:43:57 1998 --- xc/programs/Xserver/hw/xfree86/XF86Setup/texts/generic/messages.tcl Fri Mar 6 16:29:38 1998 *************** *** 0 **** --- 1,216 ---- + # $TOG: messages.tcl /main/1 1998/03/06 16:31:16 kaleb $ + + + + + # $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/texts/generic/messages.tcl,v 1.1.2.4 1998/02/26 20:11:20 hohndel Exp $ + # + # messages in done.tcl : + set messages(done.1) "\n\n\ + If you've finished configuring everything press the\n\ + Okay button to start the X server using the\ + configuration you've selected.\n\n\ + If you still wish to configure some things,\n\ + press one of the buttons at the top and then\n\ + press \"Done\" again, when you've finished." + set messages(done.2) "Okay." + + # messages in srvflags : + set messages(srvflags.1) "Optional server settings\n\n\ + These should be set to reasonable values, by default,\n\ + so you probably don't need to change anything" + set messages(srvflags.2) "Allow server to be killed with\ + hotkey sequence (Ctrl-Alt-Backspace)" + set messages(srvflags.3) "Allow video mode switching" + set messages(srvflags.4) "Don't Trap Signals\ + - prevents the server from exitting cleanly" + set messages(srvflags.5) "Allow video mode changes from other hosts" + set messages(srvflags.6) "Allow changes to keyboard and mouse settings\ + from other hosts" + + # messages in phase2 : + set messages(phase2.1) "Loading - Please wait...\n\n\n" + set messages(phase2.2) \ + "Unable to read keyboard information from the server.\n\n\ + This problem most often occurs when you are running when\n\ + you are running a server which does not have the XKEYBOARD\n\ + extension or which has it disabled.\n\n\ + The ability of this program to configure the keyboard is\n\ + reduced without the XKEYBOARD extension, but is still\ + functional.\n\n\ + Continuing..." + set messages(phase2.3) Mouse + set messages(phase2.4) Keyboard + set messages(phase2.5) Card + set messages(phase2.6) Monitor + set messages(phase2.7) Modeselection + set messages(phase2.8) Other + set messages(phase2.9) Abort + set messages(phase2.10) Done + set messages(phase2.11) Help + set messages(phase2.12) "\n\ + There are five areas of configuration that need to\ + be completed, corresponding to the buttons\n\ + along the top:\n\n\ + \tMouse\t\t- Use this to set the protocol, baud rate, etc.\ + used by your mouse\n\ + \tKeyboard\t- Set the nationality and layout of\ + your keyboard\n\ + \tCard\t\t- Used to select the chipset, RAMDAC, etc.\ + of your card\n\ + \tMonitor\t\t- Use this to enter your\ + monitor's capabilities\n\ + \tModeselction\t\t- Use this to chose the modes\ + that you want to use\n\ + \tOther\t\t- Configure some miscellaneous settings\n\n\ + You'll probably want to start with configuring your\ + mouse (you can just press \[Enter\] to do so)\n\ + and when you've finished configuring all five of these,\ + select the Done button.\n\n\ + To select any of the buttons, press the underlined\ + letter together with either Control or Alt.\n\ + You can also press ? or click on the Help button at\ + any time for additional instructions\n\n" + set messages(phase2.13) "Dismiss" + + # messages in phase4 : + set messages(phase4.1) "Loading - Please wait..." + # phase.2-5 is generated by proc 'make_message_phase4'. + set messages(phase4.6) "Okay" + set messages(phase4.7) \ + "You can now run xvidtune to adjust your display settings,\n\ + if you want to change the size or placement of the screen image\n\n\ + If not, go ahead and exit\n\n\n\ + If you choose to save the configuration, a backup copy will be\n\ + made, if the file already exists" + set messages(phase4.8) "Save configuration to:" + set messages(phase4.9) "Run xvidtune" + set messages(phase4.10) "Save the configuration and exit" + set messages(phase4.11) "Abort - Don't save the configuration" + set messages(phase4.12) "Aborted" + set messages(phase4.13) "Congratulations, you've got a running server!\n\n" + + # messages in card.tcl : + set messages(card.1) "Card selected:" + set messages(card.2) "Card selected: None" + set messages(card.3) "Read README file" + set messages(card.4) "Detailed Setup" + set messages(card.5) Server: + set messages(card.7) Chipset + set messages(card.8) RamDac + set messages(card.9) ClockChip + set messages(card.10) "RAMDAC Max Speed" + set messages(card.11) "Probed" + set messages(card.12) "Video RAM" + set messages(card.13) "Probed" + set messages(card.14) "256K" + set messages(card.15) "512K" + set messages(card.16) "1Meg" + set messages(card.17) "2Meg" + set messages(card.18) "3Meg" + set messages(card.19) "4Meg" + set messages(card.20) "6Meg" + set messages(card.21) "8Meg" + set messages(card.22) "Selected options:" + set messages(card.23) "Additional lines to\ + add to Device section of the XF86Config file:" + #set messages(card.24) "Probed: Yes" + #set messages(card.25) "Probed: No" + set messages(card.26) "Card List" + set messages(card.27) "Detailed Setup" + set messages(card.28) "Card selected: " + set messages(card.29) "Dismiss" + set messages(card.30) \ + "First make sure the correct server is selected,\ + then make whatever changes are needed\n\ + If the Chipset, RamDac, or ClockChip entries\ + are left blank, they will be probed" + set messages(card.31) \ + "Select your card from the list.\n\ + If your card is not listed,\ + click on the Detailed Setup button" + set messages(card.32) \ + "That's all there is to configuring your card\n\ + unless you would like to make changes to the\ + standard settings (by pressing Detailed Setup)" + set messages(card.33) \ + "That's probably all there is to configuring\ + your card, but you should probably check the\n\ + README to make sure. If any changes are needed,\ + press the Detailed Setup button" + set messages(card.34) \ + "You have selected a card which is not fully\ + supported by XFree86, however all of the proper\n\ + configuration options have been set such that it\ + should work in standard VGA mode" + + # messages in keyboard.tcl : + set messages(keyboard.1) "Model:" + set messages(keyboard.2) "Layout (language):" + set messages(keyboard.3) "Apply" + set messages(keyboard.4) \ + "Select the appropriate model and layout" + set messages(keyboard.5) "Available options:" + set messages(keyboard.6) \ + "Variant (non U.S. Keyboards only):" + set messages(keyboard.7) "Use default setting" + set messages(keyboard.8) "Failed! Try again" + set messages(keyboard.9) "Applying..." + set messages(keyboard.10) "Please wait..." + + # messages in modeselect.tcl : + + set messages(modeselect.1) "Select the modes you want to use" + set messages(modeselect.2) 640x480 + set messages(modeselect.3) 800x600 + set messages(modeselect.4) 1024x768 + set messages(modeselect.5) 1152x864 + set messages(modeselect.6) 1280x1024 + set messages(modeselect.7) 1600x1200 + set messages(modeselect.8) 640x400 + set messages(modeselect.9) 320x200 + set messages(modeselect.10) 320x240 + set messages(modeselect.11) 400x300 + set messages(modeselect.12) 480x300 + set messages(modeselect.13) 512x384 + set messages(modeselect.14) "Select the default color depth you want to use" + set messages(modeselect.15) " 8bpp " + set messages(modeselect.16) " 16bpp " + set messages(modeselect.17) " 24bpp " + set messages(modeselect.18) " 32bpp " + + # messages in monitor.tcl : + + set messages(monitor.1) "Monitor sync rates" + set messages(monitor.2) "Monitor selected:" + set messages(monitor.3) "Horizontal" + set messages(monitor.4) "Vertical" + set messages(monitor.5) \ + "Enter the Horizontal and Vertical Sync ranges for your monitor\n\ + or if you do not have that information, choose from the list" + + # messages in mouse.tcl : + + set messages(mouse.1) "Lines/inch" + set messages(mouse.2) "Sample Rate" + set messages(mouse.3) "Select the mouse protocol" + set messages(mouse.4) "Applying..." + set messages(mouse.5) "Mouse Device" + set messages(mouse.6) Emulate3Buttons + set messages(mouse.7) ChordMiddle + set messages(mouse.8) "Baud Rate" + set messages(mouse.9) "Press ? or Alt-H for a list of key bindings" + set messages(mouse.10) Flags + set messages(mouse.11) ClearDTR + set messages(mouse.12) ClearRTS + set messages(mouse.13) "Sample Rate" + set messages(mouse.14) "Emulate3Timeout" + set messages(mouse.15) "Apply" + set messages(mouse.16) "Press ? or Alt-H for a list of key bindings" + set messages(mouse.17) "Exit" + set messages(mouse.18) 1 + set messages(mouse.19) "Resolution" + set messages(mouse.20) "High" + set messages(mouse.21) "Medium" + set messages(mouse.22) "Low" + set messages(mouse.23) "Buttons" *** /dev/null Tue Jun 30 11:43:59 1998 --- xc/programs/Xserver/hw/xfree86/XF86Setup/texts/generic/message_proc.tcl Fri Mar 6 16:29:34 1998 *************** *** 0 **** --- 1,82 ---- + # $TOG: message_proc.tcl /main/1 1998/03/06 16:31:12 kaleb $ + + + + + # $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/texts/generic/message_proc.tcl,v 1.1.2.2 1998/02/26 20:11:19 hohndel Exp $ + # + # These procedures generate local messages with arguments + + proc make_message_phase4 { saveto } { + global messages + set messages(phase4.2) \ + "Unable to backup $saveto as $saveto.bak!\n\ + The configuration has not been saved!\n\ + Try again, with a different file name" + set messages(phase4.3) "A backup of the previous configuration has\n\ + been saved to the file $saveto.bak" + set messages(phase4.4) "Unable to save the configuration to\n\ + the file $saveto.\n\n\ + Try again, with a different file name" + set messages(phase4.5) "The configuration has been completed.\n\n" + + } + proc make_message_card { args } { + global pc98 messages Xwinhome + global cardServer + + set mes "" + if !$pc98 { + if ![file exists $Xwinhome/bin/XF86_$cardServer] { + if ![string compare $args cardselected] { + set mes \ + "*** The server required by your card is not\ + installed! Please abort, install the\ + $cardServer server as\n\ + $Xwinhome/bin/XF86_$cardServer and\ + run this program again ***" + } else { + set mes \ + "*** The selected server is not\ + installed! Please abort, install the\ + $cardServer server as\n\ + $Xwinhome/bin/XF86_$cardServer and\ + run this program again ***" + } + bell + } + } else { + if ![file exists $Xwinhome/bin/XF98_$cardServer] { + if ![string compare $args cardselected] { + set mes \ + "*** The server required by your card is not\ + installed! Please abort, install the\ + $cardServer server as\n\ + $Xwinhome/bin/XF98_$cardServer and\ + run this program again ***" + } else { + set mes \ + "*** The selected server is not\ + installed! Please abort, install the\ + $cardServer server as\n\ + $Xwinhome/bin/XF98_$cardServer and\ + run this program again ***" + } + bell + } + } + return $mes + } + + proc make_intro_headline { win } { + global pc98 + + $win insert end \ + "Introduction to Configuration with XF86Setup" heading + if !$pc98 { + $win insert end "\n" + } + } + + proc make_underline { win } { + } *** /dev/null Tue Jun 30 11:44:00 1998 --- xc/programs/Xserver/hw/xfree86/XF86Setup/texts/ja/Imakefile Fri Mar 6 16:29:42 1998 *************** *** 0 **** --- 1,19 ---- + XCOMM $TOG: Imakefile /main/1 1998/03/06 16:31:20 kaleb $ + + + + + XCOMM + XCOMM $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/texts/ja/Imakefile,v 1.1.2.3 1998/02/26 20:11:21 hohndel Exp $ + XCOMM + XF86SETUPLIBDIR = $(LIBDIR)/XF86Setup + SCRIPTSDIR = $(XF86SETUPLIBDIR)/texts/ja + + SCRIPTFILES = messages.tcl message_proc.tcl \ + help_card.tcl help_done.tcl help_keyboard.tcl \ + help_monitor.tcl help_mouse.tcl help_other.tcl \ + help_intro.tcl help_modeselect.tcl + + all:: + + InstallMultiple($(SCRIPTFILES),$(SCRIPTSDIR)) *** /dev/null Tue Jun 30 11:44:02 1998 --- xc/programs/Xserver/hw/xfree86/XF86Setup/texts/ja/help_card.tcl Fri Mar 6 16:29:46 1998 *************** *** 0 **** --- 1,52 ---- + # $TOG: help_card.tcl /main/1 1998/03/06 16:31:23 kaleb $ + + + + + # $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/texts/ja/help_card.tcl,v 1.1.2.2 1998/02/26 20:11:21 hohndel Exp $ + # + global cardDetail + + if { $cardDetail == "std" } { + set message "\n\n\ + ¥ê¥¹¥È¤«¤é»ÈÍѤ·¤Æ¤¤¤ë¥°¥é¥Õ¥£¥Ã¥¯¥«¡¼¥É¤òÁªÂò¤·¤Æ²¼¤µ¤¤¡£\n\n\ + ¤â¤·¡¢¤½¤Î¥«¡¼¥ÉÍѤΠREADME ¥Õ¥¡¥¤¥ë¤¬¤¢¤ì¤Ð ¤òÁªÂò¤Ç¤­¤ë¤è¤¦¤Ë¤Ê¤ê¤Þ¤¹¡£²Äǽ¤Ê¸Â¤ê¡¢Æɤà¤è¤¦¤Ë\n\ + ¤·¤Æ¤¯¤À¤µ¤¤¡£README ¥Õ¥¡¥¤¥ë¤¬¤Ê¤±¤ì¤Ð¤³¤Î¥Ü¥¿¥ó¤Ï\n\ + ³¥¿§¤Ë¤Ê¤Ã¤Æ¡¢ÁªÂò¤Ç¤­¤Ê¤¯¤Ê¤Ã¤Æ¤¤¤ë¤Ï¤º¤Ç¤¹¡£\n\n\ + ¤â¤·¡¢»È¤Ã¤Æ¤¤¤ë¥°¥é¥Õ¥£¥Ã¥¯¥«¡¼¥É¤¬¥ê¥¹¥È¤Ë¤Ê¤¤»þ¡¢\n\ + ¤¢¤ë¤¤¤Ï README ¥Õ¥¡¥¤¥ë¤Ë¡Ö¤³¤Î¥°¥é¥Õ¥£¥Ã¥¯¥«¡¼¥É¤Ï\n\ + Æüì¤ÊÀßÄ꤬ɬÍפÀ¡×¤È½ñ¤¤¤Æ¤¢¤Ã¤¿¾ì¹ç¤Ë¤Ï <¾ÜºÙÀßÄê> ¤ò\n\ + ²¡¤·¤ÆɬÍפÊÀßÄê¤ò¹Ô¤Ê¤Ã¤Æ²¼¤µ¤¤¡£" + } else { + global DeviceIDs + if { [llength $DeviceIDs] > 1 } { + set message "\n\ + ¥ê¥¹¥È¤«¤é»ÈÍѤ·¤Æ¤¤¤ë¥°¥é¥Õ¥£¥Ã¥¯¥«¡¼¥É¤òÁªÂò¤¹¤ì¤Ð¡¢\n\ + ¤Û¤È¤ó¤É¤ÎÀßÄê¤ÏºÑ¤ó¤Ç¤¤¤ë¤Ï¤º¤Ç¤¹¡£\n" + } else { + set message "\n\n" + } + append message "\ + ¤Þ¤º¡¢¥°¥é¥Õ¥£¥Ã¥¯¥«¡¼¥É¤ËºÇŬ¤Ê¥µ¡¼¥Ð¡¼¤òÁª¤ó¤Ç\n\ + ¤¯¤À¤µ¤¤¡£¤½¤·¤Æ ¤ò²¡¤·¤Æ\n\ + ¤½¤Î¥µ¡¼¥Ð¡¼¤ËÂбþ¤¹¤ë README ¤òÆɤó¤Ç²¼¤µ¤¤¡£\n\ + ¤â¤·¡¢¤³¤Î¥Ü¥¿¥ó¤¬Í­¸ú¤Ë¤Ê¤Ã¤Æ¤Ê¤±¤ì¤Ð¡¢¤½¤Î\n\ + ¤Ë¤Ï README ¥Õ¥¡¥¤¥ë¤¬Â¸ºß¤·¤Æ¤¤¤Þ¤»¤ó¡£\n\n\ + ¼¡¤Ë¡¢¥°¥é¥Õ¥£¥Ã¥¯¥«¡¼¥É¤Ë»È¤ï¤ì¤Æ¤¤¤ë¥Á¥Ã¥×¥»¥Ã¥È¤È\n\ + RAMDAC ¤ò README ¤Ë½ñ¤¤¤Æ¤¢¤ë¤è¤¦¤ËÁª¤ó¤Ç²¼¤µ¤¤¡£\n\ + ¤¿¤¤¤Æ¤¤¤Ï¥µ¡¼¥Ð¡¼¤¬¼«Æ°Ç§¼±(Probe) ¤·¤Æ¤¯¤ì¤ë¤Î¤Ç\n\ + ¤³¤ì¤òÀßÄꤹ¤ëɬÍפϤ¢¤ê¤Þ¤»¤ó¡£\n\n\ + ¥¯¥í¥Ã¥¯¥Á¥Ã¥×¤Ë¤Ä¤¤¤Æ¤Ï¡¢¥Á¥Ã¥×¥»¥Ã¥È¤Ë¥¯¥í¥Ã¥¯\n\ + ¥Á¥Ã¥×¤¬ÁȤ߹þ¤Þ¤ì¤Æ¤¤¤ë¤Ê¤É¤ÎÆüì¤Ê¾ì¹ç¤Ç¤Ê¤±¤ì¤Ð\n\ + Áª¤ÖɬÍפ¬¤¢¤ê¤Þ¤¹¡£\n\n\ + ¼¡¤Ë¡¢README ¤òÆɤߤʤ¬¤éɬÍפʥª¥×¥·¥ç¥ó¤òÀßÄê\n\ + ¤·¤Æ¤¯¤À¤µ¤¤¡£\n\n\ + ¤¤¤¯¤Ä¤«¤Î®ÅÙ¤¬Áª¤Ù¤ë¤è¤¦¤Ê¼ïÎà¤Î RAMDAC¤Ç¤¢¤ì¤Ð¡¢\n\ + RAMDAC ¤ÎºÇÂç®ÅÙ¤òÀßÄꤹ¤ë¤³¤È¤â¤Ç¤­¤Þ¤¹¡£¤½¤¦¤·¤Ê¤¤¾ì¹ç¡¢\n\ + ¥µ¡¼¥Ð¡¼¤ÏºÇÂç®ÅÙ¤ò¼«Æ°Ç§¼±¤¹¤ë¤³¤È¤Ï¤Ç¤­¤Ê¤¤¤Î¤Ç¡¢¤½¤Î \n\ + RAMDAC ¤Ç»ÈÍѲÄǽ¤Ê°ìÈÖÃÙ¤¤Â®ÅÙ¤¬»È¤ï¤ì¤ë¤³¤È¤Ë¤Ê¤ê¤Þ¤¹¡£\n\n\ + ¤½¤Î¾¤Ë¡¢VRAM ¤ÎÎ̤òÀßÄꤹ¤ë¤³¤È¤â¤Ç¤­¤Þ¤¹¡£¤¿¤À¤·¡¢\n\ + Ä̾ï¤Ï¥µ¡¼¥Ð¡¼¤¬¼«Æ°Ç§¼±¤·¤Æ¤¯¤ì¤ë¤Î¤Ç¤½¤ÎɬÍפÏ\n\ + ¤¢¤ê¤Þ¤»¤ó¡£" + } *** /dev/null Tue Jun 30 11:44:04 1998 --- xc/programs/Xserver/hw/xfree86/XF86Setup/texts/ja/help_done.tcl Fri Mar 6 16:29:49 1998 *************** *** 0 **** --- 1,11 ---- + # $TOG: help_done.tcl /main/1 1998/03/06 16:31:27 kaleb $ + + + + + # $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/texts/ja/help_done.tcl,v 1.1.2.2 1998/02/26 20:11:21 hohndel Exp $ + # + set message "\n\n\ + ¤¹¤Ù¤Æ¤ÎÀßÄ꤬½ªÎ»¤·¤¿¤Ê¤é¡¢<´°Î»> ¥Ü¥¿¥ó¤ò²¡¤·¤Æ²¼¤µ¤¤¡£\n\n\ + ¤Þ¤ÀÀßÄê¤ò³¤±¤¿¤¤¾ì¹ç¤Ï²èÌ̾å¤Ë¤¢¤ë¥Ü¥¿¥ó¤ò²¡¤·¤ÆÀßÄê¤ò³¤±¡¢\n\ + ÀßÄ꤬½ª¤Ã¤¿¤éºÇ¸å¤Ë¤â¤¦°ìÅÙ <ÀßÄ꽪λ> ¥Ü¥¿¥ó¤ò²¡¤·¤Æ²¼¤µ¤¤¡£" *** /dev/null Tue Jun 30 11:44:06 1998 --- xc/programs/Xserver/hw/xfree86/XF86Setup/texts/ja/help_intro.tcl Fri Mar 6 16:29:53 1998 *************** *** 0 **** --- 1,36 ---- + # $TOG: help_intro.tcl /main/1 1998/03/06 16:31:31 kaleb $ + + + + + # $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/texts/ja/help_intro.tcl,v 1.1.2.2 1998/02/26 20:11:22 hohndel Exp $ + # + if !$pc98 { + set message "\n\ + ÀßÄê¤Ï¡¢£¶¤Ä¤ÎÉôʬ¤Ë¤ï¤«¤ì¤Æ¤¤¤Þ¤¹¡£¾å¤Ë¤Ê¤é¤ó¤Ç¤¤¤ë¥Ü¥¿¥ó¤ò\n\ + ²¡¤»¤Ð¡¢¤½¤Î¹àÌܤÎÀßÄ꤬¤Ï¤¸¤Þ¤ê¤Þ¤¹¡£¤É¤ó¤Ê½çÈÖ¤ÇÀßÄê¤ò\n\ + ¤·¤Æ¤¤¤Ã¤Æ¤â¹½¤ï¤Ê¤¤¤·¡¢²¿ÅÙÀßÄê¤ò¤ä¤êľ¤·¤Æ¤â¹½¤¤¤Þ¤»¤ó¤¬¡¢\n\ + ¤Þ¤º¤Ï¥Þ¥¦¥¹¤òÆ°¤«¤»¤ë¤è¤¦¤Ë¤·¤¿¤Û¤¦¤¬¤¤¤¤¤Ç¤·¤ç¤¦¡£¥­¡¼¥Ü¡¼¥É\n\ + ¤À¤±¤ÇÀßÄê¤ò¤¹¤Ù¤Æ¹Ô¤Ê¤¦¤Î¤Ï¡¢ÂçÊѤǤ¹¡£\n\n\ + ¥Þ¥¦¥¹¤ÎÀßÄ꤬ºÑ¤à¤Þ¤Ç¤Î´Ö¤Ï¡¢°Ê²¼¤Î¥­¡¼ÆþÎϤˤè¤Ã¤ÆÁàºî¤·¤Æ¤¯¤À¤µ¤¤ :\n\n\ + \tTAB , Ctrl+TAB\t¼¡¤Î¹àÌܤ˰ÜÆ°¤·¤Þ¤¹\n\ + \tSHIFT+TAB\tÁ°¤Î¹àÌܤ˰ÜÆ°¤·¤Þ¤¹\n\ + \t¥«¡¼¥½¥ë¥­¡¼\t²¡¤·¤¿Êý¸þ¤Ë°ÜÆ°¤·¤Þ¤¹\n\ + \t¥ê¥¿¡¼¥ó(ENTER)\t¸½ºß¡¢¥«¡¼¥½¥ë¤Î¤¢¤ë¹àÌܤòÍ­¸ú¤Ë¤·¤Þ¤¹\n\n\ + ¤½¤Î¤Û¤«¤Ë¡¢ALT ¤È¡¢¹àÌܤÎÃæ¤Î¥¢¥ó¥À¡¼¥é¥¤¥ó¤Î°ú¤¤¤Æ¤¢¤ë\n\ + ʸ»ú¤ò²¡¤»¤Ð¡¢¤½¤Î¹àÌܤ¬Í­¸ú¤Ë¤Ê¤ê¤Þ¤¹¡£" + } else { + set message "\n\ + ÀßÄê¤Ï¡¢£µ¤Ä¤ÎÉôʬ¤Ë¤ï¤«¤ì¤Æ¤¤¤Þ¤¹¡£¾å¤Ë¤Ê¤é¤ó¤Ç¤¤¤ë¥Ü¥¿¥ó¤ò\n\ + ²¡¤»¤Ð¡¢¤½¤Î¹àÌܤÎÀßÄ꤬¤Ï¤¸¤Þ¤ê¤Þ¤¹¡£¤É¤ó¤Ê½çÈÖ¤ÇÀßÄê¤ò\n\ + ¤·¤Æ¤¤¤Ã¤Æ¤â¹½¤ï¤Ê¤¤¤·¡¢²¿ÅÙÀßÄê¤ò¤ä¤êľ¤·¤Æ¤â¹½¤¤¤Þ¤»¤ó¤¬¡¢\n\ + ¤Þ¤º¤Ï¥Þ¥¦¥¹¤òÆ°¤«¤»¤ë¤è¤¦¤Ë¤·¤¿¤Û¤¦¤¬¤¤¤¤¤Ç¤·¤ç¤¦¡£¥­¡¼¥Ü¡¼¥É\n\ + ¤À¤±¤ÇÀßÄê¤ò¤¹¤Ù¤Æ¹Ô¤Ê¤¦¤Î¤Ï¡¢ÂçÊѤǤ¹¡£\n\n\ + ¥Þ¥¦¥¹¤ÎÀßÄ꤬ºÑ¤à¤Þ¤Ç¤Î´Ö¤Ï¡¢°Ê²¼¤Î¥­¡¼ÆþÎϤˤè¤Ã¤ÆÁàºî¤·¤Æ¤¯¤À¤µ¤¤ :\n\n\ + \tTAB , Ctrl+TAB\t¼¡¤Î¹àÌܤ˰ÜÆ°¤·¤Þ¤¹\n\ + \tSHIFT+TAB\tÁ°¤Î¹àÌܤ˰ÜÆ°¤·¤Þ¤¹\n\ + \t¥«¡¼¥½¥ë¥­¡¼\t²¡¤·¤¿Êý¸þ¤Ë°ÜÆ°¤·¤Þ¤¹\n\ + \t¥ê¥¿¡¼¥ó\t¸½ºß¡¢¥«¡¼¥½¥ë¤Î¤¢¤ë¹àÌܤòÍ­¸ú¤Ë¤·¤Þ¤¹\n\n\ + ¤½¤Î¤Û¤«¤Ë¡¢GRPH ¤È¡¢¹àÌܤÎÃæ¤Î¥¢¥ó¥À¡¼¥é¥¤¥ó¤Î°ú¤¤¤Æ¤¢¤ë\n\ + ʸ»ú¤ò²¡¤»¤Ð¡¢¤½¤Î¹àÌܤ¬Í­¸ú¤Ë¤Ê¤ê¤Þ¤¹¡£" + } *** /dev/null Tue Jun 30 11:44:10 1998 --- xc/programs/Xserver/hw/xfree86/XF86Setup/texts/ja/help_keyboard.tcl Fri Mar 6 16:29:57 1998 *************** *** 0 **** --- 1,18 ---- + # $TOG: help_keyboard.tcl /main/1 1998/03/06 16:31:34 kaleb $ + + + + + # $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/texts/ja/help_keyboard.tcl,v 1.1.2.2 1998/02/26 20:11:22 hohndel Exp $ + # + set message "\n\n\n\ + ¤Þ¤º¡¢¥­¡¼¥Ü¡¼¥É¤Î¥â¥Ç¥ë¤«¤é¡¢»È¤Ã¤Æ¤¤¤ë¼ïÎà¤ò\n\ + Áª¤ó¤Ç²¼¤µ¤¤¡£¤â¤·¤â¥ê¥¹¥È¤ÎÃæ¤Ë¤Ê¤±¤ì¤Ð¡¢°ìÈÖ\n\ + ¶á¤¤¤â¤Î¤òÁª¤Ù¤Ð¤¤¤¤¤Ç¤·¤ç¤¦¡£\n\ + ¥°¥é¥Õ¥£¥Ã¥¯¤¬Éϼå¤Ê¤Î¤Ï¤½¤Î¤¦¤Á½¤Àµ¤µ¤ì¤ë¤Ï¤º¤Ç¤¹¡£\n\n\ + ¤Ä¤®¤Ë¡¢¥­¡¼¤Î¥ì¥¤¥¢¥¦¥È¤È¤½¤Î¾¤Î¥ª¥×¥·¥ç¥ó¤ò¡¢\n\ + ɬÍפ˱þ¤¸¤ÆÀßÄꤷ¤Æ²¼¤µ¤¤¡£\n\ + <ÀßÄê¼Â¹Ô> ¤ò²¡¤¹¤È¡¢¸½ºßÁªÂò¤µ¤ì¤Æ¤¤¤ë¾õÂÖ¤¬\n\ + ¼ÂºÝ¤Ë¥µ¡¼¥Ð¡¼¤ËÈ¿±Ç¤µ¤ì¤Þ¤¹¡£¤½¤¦¤¹¤ì¤Ð¡¢¤½¤ì°Ê¹ß¤Ï\n\ + ¥­¡¼¥È¥Ã¥×¤Ë½ñ¤«¤ì¤¿Ä̤ê¤Îʸ»ú¤¬ÆþÎϤǤ­¤ë¤è¤¦¤Ë\n\ + ¤Ê¤ë¤Ï¤º¤Ç¤¹¡£" *** /dev/null Tue Jun 30 11:44:14 1998 --- xc/programs/Xserver/hw/xfree86/XF86Setup/texts/ja/help_modeselect.tcl Fri Mar 6 16:30:00 1998 *************** *** 0 **** --- 1,24 ---- + # $TOG: help_modeselect.tcl /main/1 1998/03/06 16:31:38 kaleb $ + + + + + # $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/texts/ja/help_modeselect.tcl,v 1.1.2.3 1998/02/26 20:11:22 hohndel Exp $ + # + set message "\n\n\n\ + »È¤¤¤¿¤¤²òÁüÅÙ¤ò¤¹¤Ù¤ÆÁªÂò¤·¡¢Ä̾ï»ÈÍѤ¹¤ë¿§¿ô¤ò°ì¤ÄÁªÂò\n\ + ¤·¤Æ¤¯¤À¤µ¤¤¡£¤³¤³¤ÇÁªÂò¤·¤¿¿§¿ô¤Ï¡¢X ¥µ¡¼¥Ð¡¼¤òµ¯Æ°¤¹¤ëºÝ\n\ + ¤Ë¥ª¥×¥·¥ç¥ó¤Ë¤è¤Ã¤ÆÌÀ¼¨Åª¤Ë»ØÄꤹ¤ë¤³¤È¤ÇÊѹ¹¤¹¤ë¤³¤È¤â\n\ + ¤Ç¤­¤Þ¤¹¡£¤Þ¤¿¡¢¥°¥é¥Õ¥£¥Ã¥¯¥«¡¼¥É¤È VRAM ¤ÎÎ̤ˤè¤Ã¤Æ²ò\n\ + ÁüÅ٤ȿ§¿ô¤ÏÀ©¸Â¤µ¤ì¤Þ¤¹¡£É½¼¨¤Ç¤­¤Ê¤¤Áȹ礻¤òÁª¤ó¤À¤È¤·\n\ + ¤Æ¤â¼ÂºÝ¤Ë»ÈÍѤ¹¤ë¤³¤È¤Ï¤Ç¤­¤Ê¤¤¤Î¤ÇÃí°Õ¤·¤Æ²¼¤µ¤¤¡£\n\n\ + ¤Ê¤ª¡¢¥Ç¥£¥¹¥×¥ì¥¤¤ÎÀ­Ç½¤ò±Û¤¨¤¿²òÁüÅÙ¤¬ÁªÂò¤µ¤ì¤Æ\n\ + ¤¤¤ë¾ì¹ç¡¢¥µ¡¼¥Ð¡¼¤Ï¤½¤ì¤ò¼«Æ°Åª¤Ë¸¡ÃΤµ¤ì¤ÆÀßÄ꤬\n\ + ºï½ü¤µ¤ì¤ë¤Î¤Ç¤½¤Î¤è¤¦¤Ê²òÁüÅÙ¤òÁª¤Ö¤Î¤â°ÕÌ£¤¬¤¢¤ê¤Þ¤»¤ó¡£\n\n\ + Ê£¿ô¤Î²òÁüÅÙ¤òÁªÂò¤·¤¿¾ì¹ç¡¢¡Ö¤½¤Î¾¡×¤Î¥»¥¯¥·¥ç¥ó¤Ç \n\ + ¥µ¡¼¥Ð¡¼¤¬Î©¤Á¾å¤¬¤Ã¤Æ¤¤¤ë¾õÂ֤ǤβòÁüÅÙÊѹ¹¤òÍ­¸ú¤Ë¤·¤Æ\n\ + ¤¤¤ì¤Ð¡¢¥µ¡¼¥Ð¡¼¤ò»ÈÍÑÃæ¤Ë CTRL+ALT(GRPH)+'+' ¤ò²¡¤¹¤³¤È\n\ + ¤Ç²òÁüÅÙ¤ÎÊѹ¹¤¬²Äǽ¤Ç¤¹¡£¤â¤·¡¢¼ÂºÝ¤Ëµ¯Æ°¤·¤Æ¤ß¤Æ²èÌÌ\n\ + ¤¬¤ß¤À¤ì¤¿¤ê¤·¤¿¾ì¹ç¤â¤è¤êÄ㤤²òÁüÅÙ¤ËÀÚÂؤ¨¤ì¤Ðɽ¼¨¤Ç\n\ + ¤­¤ë¤³¤È¤¬Â¿¤¤¤Î¤Ç¡¢¤½¤Î¾ì¹ç¤³¤Î¥Û¥Ã¥È¥­¡¼¤ò»î¤·¤Æ¤ß¤ë\n\ + ¤È¤è¤¤¤Ç¤·¤ç¤¦¡£\n" *** /dev/null Tue Jun 30 11:44:16 1998 --- xc/programs/Xserver/hw/xfree86/XF86Setup/texts/ja/help_monitor.tcl Fri Mar 6 16:30:04 1998 *************** *** 0 **** --- 1,21 ---- + # $TOG: help_monitor.tcl /main/1 1998/03/06 16:31:42 kaleb $ + + + + + # $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/texts/ja/help_monitor.tcl,v 1.1.2.2 1998/02/26 20:11:22 hohndel Exp $ + # + set message "\n\n\n\ + »ÈÍѤ·¤Æ¤¤¤ë¥Ç¥£¥¹¥×¥ì¥¤¤Î¿åÊ¿¡¿¿âľ¼þÇÈ¿ô¤òÆþÎÏ\n\ + ¤·¤Æ¤¯¤À¤µ¤¤¡£¥Ç¥£¥¹¥×¥ì¥¤¤Î¥Þ¥Ë¥å¥¢¥ë¤Î¡Ö»ÅÍ͡פÎ\n\ + Íó¤Ê¤É¤Ëµ­ºÜ¤·¤Æ¤¢¤ë¤Ï¤º¤Ç¤¹¡£\n\n\ + ¤â¤·¡¢¤½¤ì¤¬¸«¤Ä¤«¤é¤Ê¤«¤Ã¤¿¾ì¹ç¤Ë¤Ï°ìÈÌŪ¤Ê¥Ç¥£¥¹¥×¥ì¥¤¤Î\n\ + »ÅÍͤΰìÍ÷¤«¤é¡¢¼«Ê¬¤Î¥Ç¥£¥¹¥×¥ì¥¤¤Ë¹ç¤Ã¤Æ¤¤¤ë¤È»×¤¦\n\ + ¤â¤Î¤òÁª¤ó¤Ç²¼¤µ¤¤¡£\n\n\ + ¤³¤ì¤é¤ÎÃͤϡ¢Àµ³Î¤Ç¤Ê¤±¤ì¤Ð¤Ê¤ê¤Þ¤»¤ó¡£¥Ç¥£¥¹¥×¥ì¥¤¤Î\n\ + »ÅÍͤò±Û¤¨¤¿¼þÇÈ¿ô¤Ç²èÌ̤òɽ¼¨¤·¤è¤¦¤È¤¹¤ë¤È¡¢ºÇ°­¤Î\n\ + ¾ì¹ç¡¢¥Ç¥£¥¹¥×¥ì¥¤¤¬±ì¤ò¿á¤¯¤«¤âÃΤì¤Þ¤»¤ó¡£¤½¤¦¤Ç¤Ê¤¯¤Æ¤â\n\ + ¥Ç¥£¥¹¥×¥ì¥¤¤Ë°­±Æ¶Á¤òµÚ¤Ü¤¹¤ª¤½¤ì¤Ï½½Ê¬¤Ë¤¢¤ê¤Þ¤¹¡£\n\ + ¤³¤³¤ËÆþÎϤ¹¤ëÃͤ¬Àµ³Î¤Ç¤¢¤ì¤Ð¡¢¥µ¡¼¥Ð¡¼¤Ï¥Ç¥£¥¹¥×¥ì¥¤¤Î\n\ + ¸ÂÅÙ¤ò±Û¤¨¤¿²òÁüÅÙ¡¦¿§¿ô¤Ê¤É¤ò¼«Æ°Åª¤Ë¸¡ÃΤ·¡¢É½¼¨¤Ç¤­¤ë\n\ + ¥â¡¼¥É¤Î¤ß¤ò»ÈÍѤ·¤Þ¤¹¡£" *** /dev/null Tue Jun 30 11:44:17 1998 --- xc/programs/Xserver/hw/xfree86/XF86Setup/texts/ja/help_mouse.tcl Fri Mar 6 16:30:08 1998 *************** *** 0 **** --- 1,87 ---- + # $TOG: help_mouse.tcl /main/1 1998/03/06 16:31:46 kaleb $ + + + + + # $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/texts/ja/help_mouse.tcl,v 1.1.2.3 1998/02/26 20:11:23 hohndel Exp $ + # + if !$pc98 { + set message "\ + (Ãí¡§PageDown / Up ¥­¡¼¤Ë¤è¤Ã¤Æ¡¢¥¹¥¯¥í¡¼¥ë¤·¤Þ¤¹)\n\ + »Ï¤á¤Ë¡¢p ¤ò²¡¤·¤Æ¥Þ¥¦¥¹¤Î¼ïÎà¤òÁª¤ó¤Ç²¼¤µ¤¤¡£¤½¤Î¸å¡¢É¬Íפʤé\n\ + ¤Ð¥Þ¥¦¥¹¤Î¤Ä¤Ê¤¬¤Ã¤Æ¤¤¤ë¥Ç¥Ð¥¤¥¹Ì¾¤òÊѹ¹¤·¤Æ²¼¤µ¤¤¡£¤Þ¤¿¡¢¥Ü¡¼¥ì\n\ + ¡¼¥È¤òÀßÄꤷ¤Æ¤â¤¤¤¤¤Ç¤·¤ç¤¦¡£¤Ê¤ª¡¢ÁªÂò¤ò¤·¤Æ¤¤¤ë´Ö¡¢¥Þ¥¦¥¹¤ò¿¨\n\ + ¤é¤Ê¤¤¤Ç¤¯¤À¤µ¤¤¡£Àµ¤·¤¯ÀßÄê¤Ç¤­¤¿¤é¡¢a ¤ò²¡¤·¤ÆÀßÄê¤ò¼ÂºÝ¤Ë¹Ô¤Ê\n\ + ¤¤¤Þ¤¹¡£¤½¤Î¸å¡¢¥Þ¥¦¥¹¤òÆ°¤«¤·¤Æ¡¢Æ°¤¯¤«³Î¤«¤á¤Æ²¼¤µ¤¤¡£Æ°¤«¤Ê¤±\n\ + ¤ì¤Ð¡¢ÀßÄê¤ò¤â¤¦°ìÅÙ¤ä¤êľ¤·¤Æ²¼¤µ¤¤¡£\n\n\ + ¥Þ¥¦¥¹¤¬Æ°¤¤¤¿¤é¡¢¥Þ¥¦¥¹¤Î¥Ü¥¿¥ó¤ò²¡¤·¤ÆÀµ¤·¤¯Æ°¤¤¤Æ¤¤¤ë¤«³Î¤«\n\ + ¤á¤Æ²¼¤µ¤¤¡£¤â¤·¡¢3¥Ü¥¿¥ó¥Þ¥¦¥¹¤ò»È¤Ã¤Æ¤¤¤Æ¡¢¿¿Ãæ¤Î¥Ü¥¿¥ó¤¬Æ°¤«\n\ + ¤Ê¤¤¤Ê¤é¡¢ChordMiddle ¤ä Emulate3Buttons ¤ò»î¤·¤Æ¤ß¤Æ²¼¤µ¤¤¡£\n\n\ + Ãí¡§Logitech ¤È¤¤¤¦¼ïÎà¤Ï¡¢¸Å¤¤¥í¥¸¥Æ¥Ã¥¯¤Î¥Þ¥¦¥¹ÍѤǤ¹¡£\n\ + ¸½ºß¤Î¤â¤Î¤Ï¡¢Microsoft ¤« MouseMan ¤È¤¤¤¦¼ïÎà¤òÁª¤ó\n\ + ¤Ç²¼¤µ¤¤¡£\n\n\ + ¤Ê¤ª¡¢Emulate3Buttons ¤òÁª¤Ö¤È¡¢¥Þ¥¦¥¹¤Îº¸±¦¥Ü¥¿¥ó¤òƱ»þ¤Ë²¡¤¹\n\ + ¤³¤È¤ÇÃæ±û¤Î¥Ü¥¿¥ó¤¬²¡¤µ¤ì¤¿¤³¤È¤Ë¤Ê¤ê¤Þ¤¹¡£3-button timeout ¤ò\n\ + ŬÅö¤ËÊѹ¹¤·¤Æ¡¢»È¤¤¤ä¤¹¤¤¤è¤¦¤Ë¤·¤Æ²¼¤µ¤¤¡£\n\n\ + \t¥­¡¼\t\tÆ°ºî\n\ + ------------------------------------------------------\n\ + \ta\t-\tÀßÄê¤ÎÊѹ¹¤ò¼ÂºÝ¤Ë¹Ô¤Ê¤¦\n\ + \tb\t-\t¥Ü¡¼¥ì¡¼¥È¤òÊѹ¹¤¹¤ë\n\ + \tc\t-\tChord Middle ¥Ü¥¿¥ó¤ò²¡¤¹¡¿Î¥¤¹\n\ + \td\t-\tClearDTR ¥Ü¥¿¥ó¤ò²¡¤¹¡¿Î¥¤¹\n\ + \te\t-\tEmulate3button ¥Ü¥¿¥ó¤ò²¡¤¹¡¿Î¥¤¹\n\ + \tl\t-\t¥Þ¥¦¥¹¤Î´¶ÅÙ¤òÊѹ¹¤¹¤ë\n\ + \tn\t-\t¥Þ¥¦¥¹¤Î¥Ç¥Ð¥¤¥¹Ì¾¤òÀßÄꤹ¤ë\n\ + \tp\t-\t¥Þ¥¦¥¹¤Î¼ïÎà¤òÁª¤Ö\n\ + \tr\t-\tClearRTS ¥Ü¥¿¥ó¤ò²¡¤¹¡¿Î¥¤¹\n\ + \ts\t-\t¥µ¥ó¥×¥ë¥ì¡¼¥È¤òÁý¤ä¤¹\n\ + \tt\t-\t3¥Ü¥¿¥ó¥¨¥ß¥å¥ì¡¼¥·¥ç¥ó¤ÎïçÃͤòÁý¤ä¤¹\n\ + \t3\t-\t¥Ü¥¿¥ó¿ô¤ò£³¸Ä¤Ë¤¹¤ë\n\ + \t4\t-\t¥Ü¥¿¥ó¿ô¤ò£´¸Ä¤Ë¤¹¤ë\n\ + \t5\t-\t¥Ü¥¿¥ó¿ô¤ò£µ¸Ä¤Ë¤¹¤ë\n\ + ------------------------------------------------------\n\ + TAB ¤ä SHIFT-TAB ¤ò»È¤¦¤³¤È¤Ç¥Ü¥¿¥ó¤òÁª¤Ö¤³¤È¤¬¤Ç¤­¡¢¤½¤³¤Ç\n\ + Enter ¤ò²¡¤¹¤³¤È¤Ç¥Ü¥¿¥ó¤ò²¡¤¹¤³¤È¤¬¤Ç¤­¤Þ¤¹¡£\n\n\ + ¤è¤ê¾Ü¤·¤¤ÀâÌÀ¤Ï¡¢¥É¥­¥å¥á¥ó¥È¥Õ¥¡¥¤¥ë¤òÆɤó¤Ç²¼¤µ¤¤¡£\n\n" + } else { + set message "\ + (Ãí¡§ROLL UP/DOWN ¥­¡¼¤Ë¤è¤Ã¤Æ¡¢¥¹¥¯¥í¡¼¥ë¤·¤Þ¤¹)\n\ + ¤â¤·¤â¡¢£¹£¸É¸½à¥Þ¥¦¥¹¡Ê¥Ð¥¹¥Þ¥¦¥¹¡Ë¤ò»È¤Ã¤Æ¤¤¤ë¤Ê¤é¡¢¥Þ¥¦¥¹¤ò\n\ + Æ°¤«¤·¤Æ¤ß¤Æ²¼¤µ¤¤¡£¤â¤·Æ°¤«¤Ê¤±¤ì¤Ð¡¢¥Þ¥¦¥¹¤Î»É¤µ¤Ã¤Æ¤¤¤ë\n\ + ¥Ç¥Ð¥¤¥¹¤òÁªÂò¤·¤Æ¡¢<ÀßÄê¼Â¹Ô> ¤Î¥Ü¥¿¥ó¤ò²¡¤·¤Æ¤ß¤Æ²¼¤µ¤¤¡£\n\ + ¤½¤ì¤Ç¤âÆ°¤«¤Ê¤±¤ì¤Ð¡¢¥Ç¥Ð¥¤¥¹¤¬¥«¡¼¥Í¥ë¤Ëǧ¼±¤µ¤ì¤Æ¤¤¤ë¤«¡¢\n\ + ³Îǧ¤·¤Æ²¼¤µ¤¤¡£\n\n\ + ¤½¤¦¤Ç¤Ê¤¤¾ì¹ç¡¢»Ï¤á¤Ë¡¢p ¤ò²¡¤·¤Æ¥Þ¥¦¥¹¤Î¼ïÎà¤òÁª¤ó¤Ç²¼¤µ¤¤¡£\n\ + ¤½¤Î¸å¡¢É¬Íפʤé¤Ð¥Þ¥¦¥¹¤Î¤Ä¤Ê¤¬¤Ã¤Æ¤¤¤ë¥Ç¥Ð¥¤¥¹Ì¾¤òÊѹ¹¤·¤Æ\n\ + ²¼¤µ¤¤¡£¤Þ¤¿¡¢¥Ü¡¼¥ì¡¼¥È¤òÀßÄꤷ¤Æ¤â¤¤¤¤¤Ç¤·¤ç¤¦¡£¤Ê¤ª¡¢ÁªÂò¤ò\n\ + ¤·¤Æ¤¤¤ë´Ö¡¢¥Þ¥¦¥¹¤ò¿¨¤é¤Ê¤¤¤Ç¤¯¤À¤µ¤¤¡£Àµ¤·¤¯ÀßÄê¤Ç¤­¤¿¤é¡¢\n\ + a ¤ò²¡¤·¤ÆÀßÄê¤ò¼ÂºÝ¤Ë¹Ô¤Ê¤¤¤Þ¤¹¡£¤½¤Î¸å¡¢¥Þ¥¦¥¹¤òÆ°¤«¤·¤Æ¡¢\n\ + Æ°¤¯¤«³Î¤«¤á¤Æ²¼¤µ¤¤¡£Æ°¤«¤Ê¤±¤ì¤Ð¡¢ÀßÄê¤ò¤â¤¦°ìÅÙ¤ä¤êľ¤·¤Æ\n\ + ²¼¤µ¤¤¡£\n\n\ + ¥Þ¥¦¥¹¤¬Æ°¤¤¤¿¤é¡¢¥Þ¥¦¥¹¤Î¥Ü¥¿¥ó¤ò²¡¤·¤ÆÀµ¤·¤¯Æ°¤¤¤Æ¤¤¤ë¤«³Î¤«\n\ + ¤á¤Æ²¼¤µ¤¤¡£¤â¤·¡¢3¥Ü¥¿¥ó¥Þ¥¦¥¹¤ò»È¤Ã¤Æ¤¤¤Æ¡¢¿¿Ãæ¤Î¥Ü¥¿¥ó¤¬Æ°¤«\n\ + ¤Ê¤¤¤Ê¤é¡¢ChordMiddle ¤ä Emulate3Buttons ¤ò»î¤·¤Æ¤ß¤Æ²¼¤µ¤¤¡£\n\n\ + ¤Ê¤ª¡¢Emulate3Buttons ¤òÁª¤Ö¤È¡¢¥Þ¥¦¥¹¤Îº¸±¦¥Ü¥¿¥ó¤òƱ»þ¤Ë²¡¤¹\n\ + ¤³¤È¤ÇÃæ±û¤Î¥Ü¥¿¥ó¤¬²¡¤µ¤ì¤¿¤³¤È¤Ë¤Ê¤ê¤Þ¤¹¡£3-button timeout ¤ò\n\ + ŬÅö¤ËÊѹ¹¤·¤Æ¡¢»È¤¤¤ä¤¹¤¤¤è¤¦¤Ë¤·¤Æ²¼¤µ¤¤¡£\n\ + \t¥­¡¼\t\tÆ°ºî\n\ + ------------------------------------------------------\n\ + \ta\t-\tÀßÄê¤ÎÊѹ¹¤ò¼ÂºÝ¤Ë¹Ô¤Ê¤¦\n\ + \tb\t-\t¥Ü¡¼¥ì¡¼¥È¤òÊѹ¹¤¹¤ë\n\ + \tc\t-\tChord Middle ¥Ü¥¿¥ó¤ò²¡¤¹¡¿Î¥¤¹\n\ + \td\t-\tClearDTR ¥Ü¥¿¥ó¤ò²¡¤¹¡¿Î¥¤¹\n\ + \te\t-\tEmulate3button ¥Ü¥¿¥ó¤ò²¡¤¹¡¿Î¥¤¹\n\ + \tl\t-\t¥Þ¥¦¥¹¤Î´¶ÅÙ¤òÊѹ¹¤¹¤ë\n\ + \tn\t-\t¥Þ¥¦¥¹¤Î¥Ç¥Ð¥¤¥¹Ì¾¤òÀßÄꤹ¤ë\n\ + \tp\t-\t¥Þ¥¦¥¹¤Î¼ïÎà¤òÁª¤Ö\n\ + \tr\t-\tClearRTS ¥Ü¥¿¥ó¤ò²¡¤¹¡¿Î¥¤¹\n\ + \ts\t-\t¥µ¥ó¥×¥ë¥ì¡¼¥È¤òÁý¤ä¤¹\n\ + \tt\t-\t3¥Ü¥¿¥ó¥¨¥ß¥å¥ì¡¼¥·¥ç¥ó¤ÎïçÃͤòÁý¤ä¤¹\n\ + \t3\t-\t¥Ü¥¿¥ó¿ô¤ò£³¸Ä¤Ë¤¹¤ë\n\ + \t4\t-\t¥Ü¥¿¥ó¿ô¤ò£´¸Ä¤Ë¤¹¤ë\n\ + \t5\t-\t¥Ü¥¿¥ó¿ô¤ò£µ¸Ä¤Ë¤¹¤ë\n\ + ------------------------------------------------------\n\ + TAB ¤ä SHIFT-TAB ¤ò»È¤¦¤³¤È¤Ç¥Ü¥¿¥ó¤òÁª¤Ö¤³¤È¤¬¤Ç¤­¡¢¤½¤³¤Ç\n\ + ¥ê¥¿¡¼¥ó¥­¡¼¤ò²¡¤¹¤³¤È¤Ç¥Ü¥¿¥ó¤ò²¡¤¹¤³¤È¤¬¤Ç¤­¤Þ¤¹¡£\n\n\ + ¤è¤ê¾Ü¤·¤¤ÀâÌÀ¤Ï¡¢¥É¥­¥å¥á¥ó¥È¥Õ¥¡¥¤¥ë¤òÆɤó¤Ç²¼¤µ¤¤¡£\n\n" + } *** /dev/null Tue Jun 30 11:44:18 1998 --- xc/programs/Xserver/hw/xfree86/XF86Setup/texts/ja/help_other.tcl Fri Mar 6 16:30:12 1998 *************** *** 0 **** --- 1,13 ---- + # $TOG: help_other.tcl /main/1 1998/03/06 16:31:50 kaleb $ + + + + + # $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/texts/ja/help_other.tcl,v 1.1.2.2 1998/02/26 20:11:23 hohndel Exp $ + # + set message "\n\n\ + ¤³¤³¤Ç¤Ï¡¢¥µ¡¼¥Ð¡¼¤Î¤¤¤í¤¤¤í¤Ê¥ª¥×¥·¥ç¥ó¤òÀßÄꤷ¤Þ¤¹¡£\n\ + ¥ª¥×¥·¥ç¥ó¤Ï¤¹¤Ç¤Ë¡¢ÉáÄ̻Ȥï¤ì¤ë¾õÂÖ¤ËÀßÄꤷ¤Æ¤¢¤ë¤Î¤Ç\n\ + Êѹ¹¤ò¤¹¤ëɬÍפϤ¢¤Þ¤ê¤Ê¤¤¤Ç¤·¤ç¤¦¡£\n\n\ + ¤â¤·¡¢¥ª¥×¥·¥ç¥ó¤Ë¤Ä¤¤¤Æ¤Î¾Ü¤·¤¤¾ðÊ󤬤ۤ·¤±¤ì¤Ð¡¢\n\ + XF86Config ¤Î man page ¤ò»²¾È¤·¤Æ²¼¤µ¤¤¡£" *** /dev/null Tue Jun 30 11:44:19 1998 --- xc/programs/Xserver/hw/xfree86/XF86Setup/texts/ja/messages.tcl Fri Mar 6 16:30:20 1998 *************** *** 0 **** --- 1,229 ---- + # $TOG: messages.tcl /main/1 1998/03/06 16:31:58 kaleb $ + + + + + # $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/texts/ja/messages.tcl,v 1.1.2.4 1998/02/26 20:11:23 hohndel Exp $ + # + # messages in done.tcl : + set messages(done.1) "\n\ + ÀßÄê¤ò¤¹¤Ù¤Æ´°Î»¤·¤Æ¤è¤í¤·¤¤¤Ç¤¹¤«¡©\n\n\ + ¤è¤±¤ì¤Ð <´°Î»> ¥Ü¥¿¥ó¤ò²¡¤¹¤³¤È¤Ç¡¢¤³¤ÎÀßÄê¤Ç X ¥µ¡¼¥Ð¡¼¤ò\n\ + Ω¤Á¤¢¤²¤ë¤³¤È¤¬¤Ç¤­¤Þ¤¹¡£\n\ + ¤Þ¤ÀÀßÄê¤ò³¤±¤¿¤¤¾ì¹ç¤Ï²èÌ̾å¤Ë¤¢¤ë¥Ü¥¿¥ó¤ò²¡¤·¤ÆÀßÄê¤ò³¤±¡¢\n\ + ÀßÄ꤬½ª¤Ã¤¿¤éºÇ¸å¤Ë¤â¤¦°ìÅÙ <ÀßÄ꽪λ> ¥Ü¥¿¥ó¤ò²¡¤·¤Æ²¼¤µ¤¤¡£" + set messages(done.2) "´°Î»" + + # messages in srvflags : + set messages(srvflags.1) "¥µ¡¼¥Ð¡¼ÀßÄê¤Î¥ª¥×¥·¥ç¥ó\n\n\ + ¤³¤ì¤é¤Î¥ª¥×¥·¥ç¥ó¤Ï¤¢¤é¤«¤¸¤á¡¢Ä̾ï¤ÎÀßÄ꤬ÁªÂò¤µ¤ì¤Æ¤¤¤Þ¤¹¡£\n\ + ¤ª¤½¤é¤¯¡¢Êѹ¹¤ÎɬÍפϤʤ¤¤Ç¤·¤ç¤¦¡£" + set messages(srvflags.2) "Ctrl-Alt-Backspace ¤Î»°¤Ä¤Î¥­¡¼¤ò²¡¤¹¤³¤È¤Ç\n\ + ¥µ¡¼¥Ð¡¼¤ò¶¯À©½ªÎ»¤Ç¤­¤ë¤è¤¦¤Ë¤¹¤ë¡£" + set messages(srvflags.3) "¥µ¡¼¥Ð¡¼¤¬Î©¤Á¾å¤¬¤Ã¤¿¾õÂ֤ǤβòÁüÅÙÊѹ¹¤ò\n\ + ¤Ç¤­¤ë¤è¤¦¤Ë¤¹¤ë¡£ " + set messages(srvflags.4) "¥·¥°¥Ê¥ë¤ò̵»ë¤¹¤ë ¡Ä \n\ + ¡¡¡¡¡¡¡¡¡¡ prevents the server from exitting cleanly" + set messages(srvflags.5) "¾¤Î¥Û¥¹¥È¤Ë¤è¤Ã¤Æ²òÁüÅÙ¤òÊѹ¹¤Ç¤­¤ë¤è¤¦¤Ë¤¹¤ë" + set messages(srvflags.6) "¾¤Î¥Û¥¹¥È¤Ë¤è¤Ã¤Æ¥­¡¼¥Ü¡¼¥É¤È¥Þ¥¦¥¹¤Î\n\ + ÀßÄê¤òÊѹ¹¤Ç¤­¤ë¤è¤¦¤Ë¤¹¤ë" + + # messages in phase2 : + set messages(phase2.1) "Ω¤Á¤¢¤²¤Æ¤¤¤Þ¤¹¡£¤·¤Ð¤é¤¯¤ªÂÔ¤Á²¼¤µ¤¤¡£\n\n\n" + set messages(phase2.2) \ + "¥µ¡¼¥Ð¡¼¤«¤é¥­¡¼¥Ü¡¼¥É¾ðÊó¤òÆɤ߹þ¤à¤³¤È¤¬¤Ç¤­¤Þ¤»¤ó¤Ç¤·¤¿¡£\n\n\ + XKEYBOARD extension ¤òÁȤ߹þ¤ó¤Ç¤¤¤Ê¤¤¤«¡¢Ìµ¸ú¤Ë \ + ¤·¤Æ¤¤¤ë¥µ¡¼¥Ð¡¼¤ò»ÈÍѤ·¤Æ¤¤¤Þ¤»¤ó¤«¡©\n\n\ + XKEYBOARD extension ¤ÏÉԲķç¤Ç¤Ï¤¢¤ê¤Þ¤»¤ó¤¬¡¢¤Ê¤¤¾ì¹ç¤Ë \ + ¥­¡¼¥Ü¡¼¥ÉÀßÄ꤬½½Ê¬¤Ë¤Ç¤­¤Ê¤¤¤ª¤½¤ì¤¬¤¢¤ê¤Þ¤¹¡£\n\n\ + ³¹Ô¤·¤Þ¤¹¡Ä" + set messages(phase2.3) ¥Þ¥¦¥¹(M) + set messages(phase2.4) ¥­¡¼¥Ü¡¼¥É(K) + set messages(phase2.5) ¥«¡¼¥É(C) + set messages(phase2.6) ¥Ç¥£¥¹¥×¥ì¥¤(D) + set messages(phase2.7) ²òÁüÅÙ(M) + set messages(phase2.8) ¤½¤Î¾(O) + set messages(phase2.9) Ãæ»ß(A) + set messages(phase2.10) ÀßÄ꽪λ(D) + set messages(phase2.11) ¥Ø¥ë¥×(H) + if !$pc98 { + set messages(phase2.12) "\n\ + ¤Þ¤º¡¢¤³¤Î¥á¥Ã¥»¡¼¥¸¤ä¥Ø¥ë¥×¤Î²¼¤ÎÊý¤¬Æɤá¤Ê¤¤¾ì¹ç¡¢PageUp/Down¤Ê¤É¤Î¥­¡¼¤ò\n\ + ²¡¤¹¤³¤È¤Ç¥¹¥¯¥í¡¼¥ë¤¹¤ë¤³¤È¤¬¤Ç¤­¤Þ¤¹¡£\n\n\ + ¥µ¡¼¥Ð¡¼¤ÎÀßÄê¤Ï¡¢6¤Ä¤ÎÉôʬ¤Ë¤ï¤«¤ì¤Æ¤¤¤Þ¤¹¡£\n\ + \t¥Þ¥¦¥¹\t\t¡Ä ¥Þ¥¦¥¹¤Î¥×¥í¥È¥³¥ë¡¢ÄÌ¿®Â®Å٤ʤɤòÀßÄꤷ¤Þ¤¹¡£\n\ + \t¥­¡¼¥Ü¡¼¥É\t\t¡Ä ¥­¡¼¥Ü¡¼¥É¤Î¸À¸ì¤È¥ì¥¤¥¢¥¦¥È¤òÀßÄꤷ¤Þ¤¹¡£\n\ + \t¥«¡¼¥É\t\t¡Ä »ÈÍѤ¹¤ë¥°¥é¥Õ¥£¥Ã¥¯¡¦¥¢¥¯¥»¥é¥ì¡¼¥¿(SVGA ¥«¡¼¥É) \n\ + \t\t\t ¤ÎÀßÄê¤ò¹Ô¤Ê¤¤¤Þ¤¹¡£\n\ + \t¥Ç¥£¥¹¥×¥ì¥¤\t¡Ä ¥Ç¥£¥¹¥×¥ì¥¤¤¬É½¼¨¤Ç¤­¤ë¿åÊ¿¡¦¿âľ¼þÇÈ¿ô¤ò\n\ + \t\t\t ÀßÄꤷ¤Þ¤¹¡£\n\ + \t²òÁüÅÙ\t\t¡Ä ²èÌ̤βòÁüÅ٤ȿ§¿ô¤òÀßÄꤷ¤Þ¤¹¡£\n\ + \t¤½¤Î¾\t\t¡Ä ¤½¤Î¾¤ÎÀßÄê¤ò¹Ô¤Ê¤¤¤Þ¤¹¡£\n\n\ + ¤Þ¤º¡¢¥Þ¥¦¥¹¤ÎÀßÄ꤫¤é»Ï¤á¤ë¤³¤È¤ò¤ª´«¤á¤·¤Þ¤¹¡£(Enter ¥­¡¼¤ò²¡¤»¤Ð\n\ + ÀßÄ꤬»Ï¤Þ¤ê¤Þ¤¹¡£)\n\ + ¤¹¤Ù¤Æ¤ÎÀßÄ꤬½ª¤Ã¤¿¤é¡¢²¼¤Ë¤¢¤ë<ÀßÄ꽪λ> ¤Î¥Ü¥¿¥ó¤ò²¡¤·¤Æ²¼¤µ¤¤¡£\n\n\ + ¥Ü¥¿¥ó¤òÁª¤Ö»þ¤Ï¡¢CTRL ¤Þ¤¿¤Ï ALT ¥­¡¼¤È²¼Àþ¤¬°ú¤¤¤Æ¤¢¤ëʸ»ú¡Ê¤¿¤È¤¨¤Ð¡¢\n\ + ¥Þ¥¦¥¹¤Ê¤é CTRL+'M' ¥­¡¼¡Ë¤ò²¡¤¹¡¢¥«¡¼¥½¥ë¥­¡¼¤äTAB ¥­¡¼¤Ç¤½¤ÎÁªÂò»è¤Ë\n\ + ¥«¡¼¥½¥ë¤ò¹ç¤ï¤»¤Æ ENTER ¤ò²¡¤¹¡¢¥Þ¥¦¥¹¤Ç¥Ü¥¿¥ó¤òº¸¥¯¥ê¥Ã¥¯¤¹¤ë¡¢¤Ê¤É¤ò\n\ + ¤·¤Æ²¼¤µ¤¤¡£¤Þ¤¿¡¢'?'¥­¡¼¤ò²¡¤¹¤«¡¢HELP ¥Ü¥¿¥ó¤ò¥¯¥ê¥Ã¥¯¤¹¤ì¤Ð³ÆÀßÄê¤Ë\n\ + ¤Ä¤¤¤Æ¡¢¥Ø¥ë¥×¤ò¸«¤ë¤³¤È¤¬¤Ç¤­¤Þ¤¹¡£" + } else { + set messages(phase2.12) "\n\ + ¤Þ¤º¡¢¤³¤Î¥á¥Ã¥»¡¼¥¸¤ä¥Ø¥ë¥×¤Î²¼¤ÎÊý¤¬Æɤá¤Ê¤¤¾ì¹ç¡¢ROLLUP/DOWN¤Ê¤É¤Î¥­¡¼¤ò\n\ + ²¡¤¹¤³¤È¤Ç¥¹¥¯¥í¡¼¥ë¤¹¤ë¤³¤È¤¬¤Ç¤­¤Þ¤¹¡£\n\n\ + ¥µ¡¼¥Ð¡¼¤ÎÀßÄê¤Ï¡¢5¤Ä¤ÎÉôʬ¤Ë¤ï¤«¤ì¤Æ¤¤¤Þ¤¹¡£\n\ + \t¥Þ¥¦¥¹\t\t¡Ä ¥Þ¥¦¥¹¤Î¥×¥í¥È¥³¥ë¡¢ÄÌ¿®Â®Å٤ʤɤòÀßÄꤷ¤Þ¤¹¡£\n\ + \t¥«¡¼¥É\t\t¡Ä »ÈÍѤ¹¤ë¥°¥é¥Õ¥£¥Ã¥¯¡¦¥¢¥¯¥»¥é¥ì¡¼¥¿(SVGA ¥«¡¼¥É) \n\ + \t\t\t ¤ÎÀßÄê¤ò¹Ô¤Ê¤¤¤Þ¤¹¡£\n\ + \t¥Ç¥£¥¹¥×¥ì¥¤\t¡Ä ¥Ç¥£¥¹¥×¥ì¥¤¤¬É½¼¨¤Ç¤­¤ë¿åÊ¿¡¦¿âľ¼þÇÈ¿ô¤ò\n\ + \t\t\t ÀßÄꤷ¤Þ¤¹¡£\n\ + \t²òÁüÅÙ\t\t¡Ä ²èÌ̤βòÁüÅ٤ȿ§¿ô¤òÀßÄꤷ¤Þ¤¹¡£\n\ + \t¤½¤Î¾\t\t¡Ä ¤½¤Î¾¤ÎÀßÄê¤ò¹Ô¤Ê¤¤¤Þ¤¹¡£\n\n\ + ¤Þ¤º¡¢¥Þ¥¦¥¹¤ÎÀßÄ꤫¤é»Ï¤á¤ë¤³¤È¤ò¤ª´«¤á¤·¤Þ¤¹¡£\n\ + \t¡Ê¥ê¥¿¡¼¥ó¥­¡¼¤ò²¡¤»¤ÐÀßÄ꤬»Ï¤Þ¤ê¤Þ¤¹¡£¡Ë\n\ + ¤¹¤Ù¤Æ¤ÎÀßÄ꤬½ª¤Ã¤¿¤é¡¢²¼¤Ë¤¢¤ë<ÀßÄ꽪λ> ¤Î¥Ü¥¿¥ó¤ò²¡¤·¤Æ²¼¤µ¤¤¡£\n\n\ + ¥Ü¥¿¥ó¤òÁª¤Ö»þ¤Ï¡¢CTRL ¤Þ¤¿¤Ï GRPH ¥­¡¼¤È²¼Àþ¤¬°ú¤¤¤Æ¤¢¤ëʸ»ú(¤¿¤È¤¨¤Ð¡¢\n\ + ¥Þ¥¦¥¹¤Ê¤é CTRL+'M' ¥­¡¼¡Ë¤ò²¡¤¹¡¢¥«¡¼¥½¥ë¥­¡¼¤ä TAB ¥­¡¼¤Ç¤½¤ÎÁªÂò»è¤Ë\n\ + ¥«¡¼¥½¥ë¤ò¹ç¤ï¤»¤Æ ¥ê¥¿¡¼¥ó¥­¡¼¤ò²¡¤¹¡¢¥Þ¥¦¥¹¤Ç¥Ü¥¿¥ó¤òº¸¥¯¥ê¥Ã¥¯¤¹¤ë¡¢\n\ + ¤Ê¤É¤ò¤·¤Æ²¼¤µ¤¤¡£¤Þ¤¿¡¢'?'¥­¡¼¤ò²¡¤¹¤«¡¢HELP ¥Ü¥¿¥ó¤ò¥¯¥ê¥Ã¥¯¤¹¤ì¤Ð\n\ + ³ÆÀßÄê¤Ë¤Ä¤¤¤Æ¡¢¥Ø¥ë¥×¤ò¸«¤ë¤³¤È¤¬¤Ç¤­¤Þ¤¹¡£" + } + set messages(phase2.13) "¥Ø¥ë¥×½ªÎ»" + # messages in phase4 : + set messages(phase4.1) "Ω¤Á¤¢¤²¤Æ¤¤¤Þ¤¹¡£¤·¤Ð¤é¤¯¤ªÂÔ¤Á²¼¤µ¤¤¡£" + # phase.2-5 is generated by proc 'make_message_phase4'. + set messages(phase4.6) "Okey" + set messages(phase4.7) \ + "²èÌ̤ÎÂ礭¤µ¤ä¥Ç¥£¥¹¥×¥ì¥¤¾å¤Ç¤Î²èÌ̤ΰÌÃ֤ʤɡ¢²èÌ̤ÎÀßÄê¤ò\n\ + Êѹ¹¤¹¤ë¤¿¤á¤Ë xvidtune ¤ò»ÈÍѤ¹¤ë¤³¤È¤¬¤Ç¤­¤Þ¤¹¡£\n\ + Êѹ¹¤ÎɬÍפ¬¤Ê¤¤¤Ê¤é½ªÎ»¤·¤Æ²¼¤µ¤¤¡£\n\n\n\ + ÀßÄê¤òÊݸ¤¹¤ë¤È¤­¡¢¤¹¤Ç¤Ë¾¤ÎÀßÄ꤬¸ºß¤·¤Æ¤¤¤ì¤Ð¥Ð¥Ã¥¯¥¢¥Ã¥×\n\ + ¤È¤·¤ÆÊݸ¤µ¤ì¤Þ¤¹¡£" + set messages(phase4.8) "ÀßÄê¤òÊݸ¤¹¤ë¥Õ¥¡¥¤¥ë̾" + set messages(phase4.9) "xvidtune ¤ò»ÈÍѤ¹¤ë" + set messages(phase4.10) "ÀßÄê¤ò¥Õ¥¡¥¤¥ë¤ËÊݸ¤·¤Æ¡¢½ªÎ»¤¹¤ë" + set messages(phase4.11) "ÃæÃÇ ¡Ä ÀßÄê¤òÊݸ¤·¤Ê¤¤¤Ç½ªÎ»¤¹¤ë" + set messages(phase4.12) "ÀßÄê¤òÃæÃǤ·¤Þ¤·¤¿¡£" + set messages(phase4.13) "¤ª¤á¤Ç¤È¤¦¤´¤¶¤¤¤Þ¤¹¡¢\ + ¥µ¡¼¥Ð¡¼¤ÎÀßÄ꤬´°Î»¤·¤Þ¤·¤¿\n\n" + + # messages in card.tcl : + set messages(card.1) "ÁªÂò¤µ¤ì¤¿¥°¥é¥Õ¥£¥Ã¥¯¥«¡¼¥É :" + set messages(card.2) "¥°¥é¥Õ¥£¥Ã¥¯¥«¡¼¥É¤ÏÁªÂò¤µ¤ì¤Æ¤¤¤Þ¤»¤ó¡£" + set messages(card.3) "README ¥Õ¥¡¥¤¥ë¤òÆɤà" + set messages(card.4) "¾ÜºÙÀßÄê" + set messages(card.5) ¥µ¡¼¥Ð¡¼: + set messages(card.7) ¥Á¥Ã¥×¥»¥Ã¥È + set messages(card.8) RamDac + set messages(card.9) ¥¯¥í¥Ã¥¯¥Á¥Ã¥× + set messages(card.10) "RAMDAC Max Speed" + set messages(card.11) "Probed" + set messages(card.12) "Video RAM" + set messages(card.13) "Probed" + set messages(card.14) "256 ¥­¥í" + set messages(card.15) "512 ¥­¥í" + set messages(card.16) "1 ¥á¥¬" + set messages(card.17) "2 ¥á¥¬" + set messages(card.18) "3 ¥á¥¬" + set messages(card.19) "4 ¥á¥¬" + set messages(card.20) "6 ¥á¥¬" + set messages(card.21) "8 ¥á¥¬" + set messages(card.22) "ÁªÂò¤µ¤ì¤¿\n¥ª¥×¥·¥ç¥ó:" + set messages(card.23) "XF86Config ¤Î Device ¤Î¹à¤ËÉÕ¤±²Ã¤¨¤ëÀßÄê:" + #set messages(card.24) "Probed: Yes" + #set messages(card.25) "Probed: No" + set messages(card.26) "¥«¡¼¥É¤ÎÁªÂò" + set messages(card.27) "¾ÜºÙÀßÄê" + set messages(card.28) "ÁªÂò¤µ¤ì¤¿¥°¥é¥Õ¥£¥Ã¥¯¥«¡¼¥É: " + set messages(card.29) "½ªÎ»" + set messages(card.30) \ + " ¤Þ¤º¡¢¥µ¡¼¥Ð¡¼¤¬Àµ¤·¤¤¤«¤É¤¦¤«¤¿¤·¤«¤á¤Æ¤«¤é¡¢\n\ + ɬÍפʤéÀßÄê¤òÊѹ¹¤·¤Æ²¼¤µ¤¤¡£¥Á¥Ã¥×¥»¥Ã¥È¡¢RamDac ¡¢\n\ + ¥¯¥í¥Ã¥¯¥Á¥Ã¥×¤¬¶õÍó¤Î¾ì¹ç¡¢¼«Æ°Ç§¼±¤µ¤ì¤Þ¤¹¡£" + set messages(card.31) \ + " ¥ê¥¹¥È¤«¤é»È¤Ã¤Æ¤¤¤ë¥°¥é¥Õ¥£¥Ã¥¯¥«¡¼¥É¤òÁª¤ó¤Ç²¼¤µ¤¤¡£\n\ + ¤â¤·¡¢»È¤Ã¤Æ¤¤¤ë¥«¡¼¥É¤¬¥ê¥¹¥È¤Ë¤Ê¤¤¾ì¹ç¡¢¾ÜºÙÀßÄê¤Î \n\ + ¥Ü¥¿¥ó¤ò²¡¤·¤Æ²¼¤µ¤¤¡£" + set messages(card.32) \ + "Ä̾ï¤ÎÀßÄê¤Ç¤è¤±¤ì¤Ð¡¢¥«¡¼¥É¤ÎÀßÄê¤Ï¤³¤ì¤Ç½½Ê¬¤Ç¤¹¡£\n\ + Ä̾ï¤È°ã¤¦ÀßÄê¤ò¤·¤¿¤¤¾ì¹ç¡¢¾ÜºÙÀßÄê¤Î¥Ü¥¿¥ó¤ò²¡¤·¤Æ²¼¤µ¤¤¡£" + set messages(card.33) \ + "Ä̾ï¤ÎÀßÄê¤Ç¤è¤±¤ì¤Ð¡¢¥«¡¼¥É¤ÎÀßÄê¤Ï¤³¤ì¤Ç½½Ê¬¤Ç¤¹¡£\n\ + ¤¿¤À¤·¡¢³Îǧ¤Î¤¿¤á¤Ë README ¤òÆɤà¤è¤¦¤Ë¤·¤Þ¤·¤ç¤¦¡£\n\ + ¤â¤·¡¢¤Ê¤ó¤é¤«¤ÎÊѹ¹¤¬É¬ÍפǤ¢¤ì¤Ð¾ÜºÙÀßÄê¤Î¥Ü¥¿¥ó¤ò\n\ + ²¡¤·¤Æ²¼¤µ¤¤¡£" + set messages(card.34) \ + "¤³¤Î¥«¡¼¥É¤Ï¡¢XFree86 ¤Ç¤Ï¤Þ¤À´°Á´¤Ë¤Ï¥µ¥Ý¡¼¥È¤µ¤ì¤Æ\n\ + ¤¤¤Þ¤»¤ó¡£¤¿¤À¤·¡¢Ä̾ï¤ÎVGA ¥â¡¼¥É¤ÇÆ°¤¯¤è¤¦¤Ë\n\ + ÀßÄê¤ÏºÑ¤ó¤Ç¤¤¤Þ¤¹¡£" + + # messages in keyboard.tcl : + set messages(keyboard.1) "¥â¥Ç¥ë:" + set messages(keyboard.2) "¥ì¥¤¥¢¥¦¥È (¸À¸ì):" + set messages(keyboard.3) "ÀßÄê¼Â¹Ô" + set messages(keyboard.4) \ + "Àµ¤·¤¤¥â¥Ç¥ë¤È¥ì¥¤¥¢¥¦¥È¤òÁª¤ó¤Ç²¼¤µ¤¤¡£" + set messages(keyboard.5) "»È¤¦¤³¤È¤Î¤Ç¤­¤ë¥ª¥×¥·¥ç¥ó :" + set messages(keyboard.6) \ + "Variant (non U.S. Keyboards only):" + set messages(keyboard.7) "´ûÄêÃͤò»ÈÍѤ¹¤ë" + set messages(keyboard.8) "¼ºÇÔ¤·¤Þ¤·¤¿¡£¤ä¤êľ¤·¤Æ²¼¤µ¤¤¡£" + set messages(keyboard.9) "ÀßÄêÃæ¤Ç¤¹¡Ä" + set messages(keyboard.10) "¤ªÂÔ¤Á²¼¤µ¤¤¡Ä" + + # messages in modeselect.tcl : + + set messages(modeselect.1) "ÍøÍѤ·¤¿¤¤²òÁüÅÙ¤òÁªÂò¤·¤Æ²¼¤µ¤¤" + set messages(modeselect.2) 640x480 + set messages(modeselect.3) 800x600 + set messages(modeselect.4) 1024x768 + set messages(modeselect.5) 1152x864 + set messages(modeselect.6) 1280x1024 + set messages(modeselect.7) 1600x1200 + set messages(modeselect.8) 640x400 + set messages(modeselect.9) 320x200 + set messages(modeselect.10) 320x240 + set messages(modeselect.11) 400x300 + set messages(modeselect.12) 480x300 + set messages(modeselect.13) 512x384 + set messages(modeselect.14) "»ÈÍѤ¹¤ë¿§¿ô¤òÁªÂò¤·¤Æ²¼¤µ¤¤" + set messages(modeselect.15) " 256¿§ " + set messages(modeselect.16) " 65536¿§ " + set messages(modeselect.17) " 1600Ëü¿§(Packed) " + set messages(modeselect.18) " 1600Ëü¿§ " + + # messages in monitor.tcl : + + set messages(monitor.1) "¥Ç¥£¥¹¥×¥ì¥¤¤Î¼þÇÈ¿ô" + set messages(monitor.2) "ÁªÂò¤µ¤ì¤¿¥Ç¥£¥¹¥×¥ì¥¤:" + set messages(monitor.3) "¿åÊ¿¼þÇÈ¿ô" + set messages(monitor.4) "¿âľ¼þÇÈ¿ô" + set messages(monitor.5) \ + "¥Ç¥£¥¹¥×¥ì¥¤¤Ëɽ¼¨²Äǽ¤Ê¿åÊ¿¡¦¿âľ¼þÇÈ¿ô¤òÆþÎϤ·¤Æ²¼¤µ¤¤¡£\n\ + ¤ï¤«¤é¤Ê¤±¤ì¤Ð¡¢¥ê¥¹¥È¤«¤éºÇŬ¤È»×¤ï¤ì¤ë¤â¤Î¤òÁªÂò¤·¤Æ²¼¤µ¤¤¡£" + + # messages in mouse.tcl : + + set messages(mouse.1) "Lines/inch" + set messages(mouse.2) "¥µ¥ó¥×¥ë\n¥ì¡¼¥È" + set messages(mouse.3) "¥Þ¥¦¥¹¤Î¼ïÎà¤òÁª¤ó¤Ç²¼¤µ¤¤" + set messages(mouse.4) "ÀßÄêÃæ¡Ä" + set messages(mouse.5) "¥Þ¥¦¥¹¤Î¤¢¤ë¥Ç¥Ð¥¤¥¹" + set messages(mouse.6) "Emulate3Buttons" + set messages(mouse.7) ChordMiddle + set messages(mouse.8) "ÄÌ¿®Â®ÅÙ" + set messages(mouse.9) "? ¤Þ¤¿¤Ï CTRL-H ¤ò²¡¤»¤Ð¡¢¥­¡¼¥Ü¡¼¥É¤Î»È¤¤Êý¤¬É½¼¨¤µ¤ì¤Þ¤¹¡£" + set messages(mouse.10) ¥Õ¥é¥° + set messages(mouse.11) "DTR¤ò\n¥¯¥ê¥¢¤¹¤ë" + set messages(mouse.12) "RTS¤ò\n¥¯¥ê¥¢¤¹¤ë" + set messages(mouse.13) "¥µ¥ó¥×¥ë\n¥ì¡¼¥È" + set messages(mouse.14) "3¥Ü¥¿¥ó¥¨¥ß¥å\n¥ì¡¼¥È¤ÎïçÃÍ" + set messages(mouse.15) "ÀßÄê¼Â¹Ô" + set messages(mouse.16) "? ¤Þ¤¿¤Ï CTRL-H ¤ò²¡¤»¤Ð¡¢¥­¡¼¥Ü¡¼¥É¤Î»È¤¤Êý¤¬É½¼¨¤µ¤ì¤Þ¤¹¡£" + set messages(mouse.17) "½ªÎ»(X)" + set messages(mouse.18) 3 + set messages(mouse.19) "´¶ÅÙ" + set messages(mouse.20) "¹â" + set messages(mouse.21) "Ãæ" + set messages(mouse.22) "Äã" + set messages(mouse.23) "¥Ü¥¿¥ó¿ô" *** /dev/null Tue Jun 30 11:44:21 1998 --- xc/programs/Xserver/hw/xfree86/XF86Setup/texts/ja/message_proc.tcl Fri Mar 6 16:30:16 1998 *************** *** 0 **** --- 1,93 ---- + # $TOG: message_proc.tcl /main/1 1998/03/06 16:31:54 kaleb $ + + + + + # $XFree86: xc/programs/Xserver/hw/xfree86/XF86Setup/texts/ja/message_proc.tcl,v 1.1.2.2 1998/02/26 20:11:23 hohndel Exp $ + # + # These procedures generate local messages with arguments + + proc make_message_phase4 { saveto } { + global messages + set messages(phase4.2) \ + "¥Õ¥¡¥¤¥ë $saveto ¤Î¥Ð¥Ã¥¯¥¢¥Ã¥×¥Õ¥¡¥¤¥ë¡¢$saveto.bak ¤¬\n\ + ºî¤ì¤Ê¤¤¤Î¤Ç¡¢ÀßÄê¤ÏÊݸ¤µ¤ì¤Þ¤»¤ó¤Ç¤·¤¿¡£\n\ + ¥Õ¥¡¥¤¥ë̾¤òÊѹ¹¤·¤Æ¡¢Êݸ¤·Ä¾¤·¤Æ²¼¤µ¤¤¡£" + set messages(phase4.3) "º£¤Þ¤Ç¤ÎÀßÄê¥Õ¥¡¥¤¥ë¤Ï $saveto.bak ¤Ë \n\ + ¥Ð¥Ã¥¯¥¢¥Ã¥×¤È¤·¤ÆÊݸ¤µ¤ì¤Þ¤·¤¿¡£" + set messages(phase4.4) \ + "¥Õ¥¡¥¤¥ë $saveto ¤ËÀßÄê¤òÊݸ¤¹¤ë¤³¤È¤¬¤Ç¤­¤Þ¤»¤ó¡£\n\n\ + ¥Õ¥¡¥¤¥ë̾¤òÊѹ¹¤·¤ÆÊݸ¤·Ä¾¤·¤Æ²¼¤µ¤¤" + set messages(phase4.5) "X ¤ÎÀßÄ꤬´°Î»¤·¤Þ¤·¤¿¡£\n\n" + } + proc make_message_card { args } { + global pc98 messages Xwinhome + global cardServer + + set mes "" + if !$pc98 { + if ![file exists $Xwinhome/bin/XF86_$cardServer] { + if ![string compare $args cardselected] { + set mes \ + "!!! ¤³¤Î¥°¥é¥Õ¥£¥Ã¥¯¥«¡¼¥É¤ËɬÍפʥµ¡¼¥Ð¡¼¤Ï\ + ¥¤¥ó¥¹¥È¡¼¥ë¤µ¤ì¤Æ¤¤¤Þ¤»¤ó¡£ÀßÄê¤òÃæÃǤ·¤Æ¡¢\ + $cardServer ¥µ¡¼¥Ð¡¼¤ò $Xwinhome/bin/XF86_$cardServer \ + ¤Î̾Á°¤Ç¥¤¥ó¥¹¥È¡¼¥ë¤·¡¢¤â¤¦°ìÅÙÀßÄê¤ò \ + ¤ä¤êľ¤·¤Æ²¼¤µ¤¤¡£ !!!" + } else { + set mes \ + "!!! ÁªÂò¤µ¤ì¤¿¥µ¡¼¥Ð¡¼¤Ï¥¤¥ó¥¹¥È¡¼¥ë \ + ¤µ¤ì¤Æ¤¤¤Þ¤»¤ó¡£ÀßÄê¤òÃæÃǤ·¤Æ¡¢\ + $cardServer ¥µ¡¼¥Ð¡¼¤ò $Xwinhome/bin/XF86_$cardServer \ + ¤Î̾Á°¤Ç¥¤¥ó¥¹¥È¡¼¥ë¤·¡¢¤â¤¦°ìÅÙÀßÄê¤ò \ + ¤ä¤êľ¤·¤Æ²¼¤µ¤¤¡£ !!!" + } + bell + } + } else { + if ![file exists $Xwinhome/bin/XF98_$cardServer] { + if ![string compare $args cardselected] { + set mes \ + "!!! ¤³¤Î¥°¥é¥Õ¥£¥Ã¥¯¥«¡¼¥É¤ËɬÍפʥµ¡¼¥Ð¡¼¤Ï\ + ¥¤¥ó¥¹¥È¡¼¥ë¤µ¤ì¤Æ¤¤¤Þ¤»¤ó¡£ÀßÄê¤òÃæÃǤ·¤Æ¡¢\ + $cardServer ¥µ¡¼¥Ð¡¼¤ò $Xwinhome/bin/XF98_$cardServer \ + ¤Î̾Á°¤Ç¥¤¥ó¥¹¥È¡¼¥ë¤·¡¢¤â¤¦°ìÅÙÀßÄê¤ò \ + ¤ä¤êľ¤·¤Æ²¼¤µ¤¤¡£ !!!" + } else { + set mes \ + "!!! ÁªÂò¤µ¤ì¤¿¥µ¡¼¥Ð¡¼¤Ï¥¤¥ó¥¹¥È¡¼¥ë \ + ¤µ¤ì¤Æ¤¤¤Þ¤»¤ó¡£ÀßÄê¤òÃæÃǤ·¤Æ¡¢\ + $cardServer ¥µ¡¼¥Ð¡¼¤ò $Xwinhome/bin/XF98_$cardServer \ + ¤Î̾Á°¤Ç¥¤¥ó¥¹¥È¡¼¥ë¤·¡¢¤â¤¦°ìÅÙÀßÄê¤ò \ + ¤ä¤êľ¤·¤Æ²¼¤µ¤¤¡£ !!!" + } + bell + } + } + return $mes + } + + proc make_intro_headline { win } { + global pc98 + $win tag configure heading \ + -font -jis-fixed-medium-r-normal--24-230-*-*-c-*-jisx0208.1983-0 + if !$pc98 { + $win insert end \ + "£Ø£Æ£¸£¶£Ó£å£ô£õ£ð¤Ë¤Ä¤¤¤Æ" heading + } else { + $win insert end \ + "£Ø£Æ£¹£¸£Ó£å£ô£õ£ð¤Ë¤Ä¤¤¤Æ" heading + } + } + + proc make_underline { win } { + $win.menu.mouse configure -underline 4 + $win.menu.keyboard configure -underline 6 + $win.menu.card configure -underline 4 + $win.menu.monitor configure -underline 7 + $win.menu.modeselect configure -underline 4 + $win.menu.other configure -underline 4 + $win.buttons.abort configure -underline 3 + $win.buttons.done configure -underline 5 + $win.buttons.help configure -underline 4 + } *** ./programs/Xserver/hw/xfree86/XF86_Acc.man@@/PUBLIC-LATEST Tue Nov 4 21:17:04 1997 --- xc/programs/Xserver/hw/xfree86/XF86_Acc.man Fri Mar 6 16:25:22 1998 *************** *** 1,5 **** ! .\" $XFree86: xc/programs/Xserver/hw/xfree86/XF86_Acc.man,v 3.58.2.5 1997/07/26 09:21:13 dawes Exp $ ! .TH XF86_Accel 1 "Release 6.4 (XFree86 3.3.1)" "X Version 11" .SH NAME XF86_Accel - accelerated X Window System servers for UNIX on x86 and Alpha platforms with an S3, Mach8, Mach32, Mach64, P9000, AGX, --- 1,5 ---- ! .\" $XFree86: xc/programs/Xserver/hw/xfree86/XF86_Acc.man,v 3.58.2.7 1998/02/26 20:11:14 hohndel Exp $ ! .TH XF86_Accel 1 "Version 3.3.2" "XFree86" .SH NAME XF86_Accel - accelerated X Window System servers for UNIX on x86 and Alpha platforms with an S3, Mach8, Mach32, Mach64, P9000, AGX, *************** *** 113,119 **** ATI Mach32 .TP 13 XF86_Mach64: ! ATI Mach64 (GX, CT, ET, VT, GT) .TP 13 XF86_P9000: Diamond Viper VLB, Diamond Viper PCI, Orchid P9000, and some clones --- 113,119 ---- ATI Mach32 .TP 13 XF86_Mach64: ! ATI Mach64 (GX, CT, ET, VT, GT, 3D Rage II, 3D Rage II+DVD, Rage Pro) .TP 13 XF86_P9000: Diamond Viper VLB, Diamond Viper PCI, Orchid P9000, and some clones *************** *** 714,726 **** don't get a picture at all. .sp \fBno_block_write\fP - (Mach64) Disables the block write mode on ! certain types of VRAM Mach64 cards. If noise or shadows appear on the ! screen, this option should remove them. .sp \fBblock_write\fP - (Mach64) Enables the block write mode on certain ! types of VRAM Mach64 cards. Normally the Mach64 server will ! automatically determine if the card can handle block write mode, but ! this option will override the probe result. .sp \fBno_bios_clocks\fP - (Mach64) The Mach64 server normally reads the clocks from the BIOS. This option overrides the BIOS clocks and --- 714,726 ---- don't get a picture at all. .sp \fBno_block_write\fP - (Mach64) Disables the block write mode on ! certain types of VRAM-based Mach64 and on Rage Pro-based cards. If ! noise or shadows appear on the screen, this option should remove them. .sp \fBblock_write\fP - (Mach64) Enables the block write mode on certain ! types of VRAM-based Mach64 and on Rage Pro-based cards. Normally the ! Mach64 server will automatically determine if the card can handle ! block write mode, but this option will override the probe result. .sp \fBno_bios_clocks\fP - (Mach64) The Mach64 server normally reads the clocks from the BIOS. This option overrides the BIOS clocks and *************** *** 942,945 **** \fIXFree86\fP source is available from the FTP server \fIftp.XFree86.Org\fP and mirrors. Send email to \fIXFree86@XFree86.Org\fP for details. ! .\" $TOG: XF86_Acc.man /main/29 1997/11/04 21:19:59 kaleb $ --- 942,945 ---- \fIXFree86\fP source is available from the FTP server \fIftp.XFree86.Org\fP and mirrors. Send email to \fIXFree86@XFree86.Org\fP for details. ! .\" $TOG: XF86_Acc.man /main/30 1998/03/06 16:27:00 kaleb $ *** ./programs/Xserver/hw/xfree86/XF86_Mono.man@@/PUBLIC-LATEST Tue Nov 4 21:17:09 1997 --- xc/programs/Xserver/hw/xfree86/XF86_Mono.man Fri Mar 6 16:25:27 1998 *************** *** 1,5 **** ! .\" $XFree86: xc/programs/Xserver/hw/xfree86/XF86_Mono.man,v 3.23.2.1 1997/05/21 15:02:21 dawes Exp $ ! .TH XF86_Mono 1 "Release 6.4 (XFree86 3.3.1)" "X Version 11" .SH NAME XF86_Mono - 1 bit non-accelerated X Window System servers for UNIX on x86 platforms --- 1,5 ---- ! .\" $XFree86: xc/programs/Xserver/hw/xfree86/XF86_Mono.man,v 3.23.2.3 1998/02/26 13:58:53 dawes Exp $ ! .TH XF86_Mono 1 "Version 3.3.2" "XFree86" .SH NAME XF86_Mono - 1 bit non-accelerated X Window System servers for UNIX on x86 platforms *************** *** 20,26 **** ATI: 18800, 18800-1, 28800-2, 28800-4, 28800-5, 28800-6, 68800-3, 68800-6, 68800AX, 68800LX, 88800GX-C, 88800GX-D, 88800GX-E, 88800GX-F, 88800CX, 264CT, 264ET, ! 264VT, 264VT2, 264GT .TP 4 Tseng: ET3000, ET4000, ET4000/W32 --- 20,27 ---- ATI: 18800, 18800-1, 28800-2, 28800-4, 28800-5, 28800-6, 68800-3, 68800-6, 68800AX, 68800LX, 88800GX-C, 88800GX-D, 88800GX-E, 88800GX-F, 88800CX, 264CT, 264ET, ! 264VT, 264GT (a.k.a. 3D Rage), 264VT-B, 264VT3, 264GT-B (a.k.a. 3D Rage II), ! 264GT3 (a.k.a. 3D Rage Pro) .TP 4 Tseng: ET3000, ET4000, ET4000/W32 *************** *** 276,279 **** Refer to the .I XFree86(1) manual page. ! .\" $TOG: XF86_Mono.man /main/17 1997/11/04 21:20:04 kaleb $ --- 277,280 ---- Refer to the .I XFree86(1) manual page. ! .\" $TOG: XF86_Mono.man /main/18 1998/03/06 16:27:05 kaleb $ *** ./programs/Xserver/hw/xfree86/XF86_SVGA.man@@/PUBLIC-LATEST Tue Nov 4 21:17:13 1997 --- xc/programs/Xserver/hw/xfree86/XF86_SVGA.man Fri Mar 6 16:25:32 1998 *************** *** 1,5 **** ! .\" $XFree86: xc/programs/Xserver/hw/xfree86/XF86_SVGA.man,v 3.42.2.5 1997/05/24 08:35:57 dawes Exp $ ! .TH XF86_SVGA 1 "Release 6.4 (XFree86 3.3.1)" "X Version 11" .SH NAME XF86_SVGA - SVGA X Window System servers for UNIX on x86 platforms --- 1,5 ---- ! .\" $XFree86: xc/programs/Xserver/hw/xfree86/XF86_SVGA.man,v 3.42.2.7 1998/02/26 13:58:54 dawes Exp $ ! .TH XF86_SVGA 1 "Version 3.3.2" "XFree86" .SH NAME XF86_SVGA - SVGA X Window System servers for UNIX on x86 platforms *************** *** 31,43 **** support 16bpp and 24bpp (truecolor) modes. The ET6000 and some ET4000W32i or ET4000W32p chips supports all color depths. Generic VGA cards are also supported at 8bpp 320x200 only. The Matrox Millennium supports all color depths. .RS .5i .TP 4 ATI: 18800, 18800-1, 28800-2, 28800-4, 28800-5, 28800-6, 68800-3, 68800-6, 68800AX, ! 68800LX, 88800GX-C, 88800GX_D, 88800GX-E, 88800GX-F, 88800CX, 264CT, 264ET, ! 264VT, 264VT2, 264GT .TP 4 Tseng: ET3000, ET4000, ET4000/W32, ET6000 --- 31,45 ---- support 16bpp and 24bpp (truecolor) modes. The ET6000 and some ET4000W32i or ET4000W32p chips supports all color depths. Generic VGA cards are also supported at 8bpp 320x200 only. The Matrox Millennium supports all color + depths. ATI adapters based on integrated controllers also support all colour depths. .RS .5i .TP 4 ATI: 18800, 18800-1, 28800-2, 28800-4, 28800-5, 28800-6, 68800-3, 68800-6, 68800AX, ! 68800LX, 88800GX-C, 88800GX-D, 88800GX-E, 88800GX-F, 88800CX, 264CT, 264ET, ! 64VT, 264GT (a.k.a. 3D Rage), 264VT-B, 264VT3, 264GT-B (a.k.a. 3D Rage II), ! 264GT3 (a.k.a. 3D Rage Pro) .TP 4 Tseng: ET3000, ET4000, ET4000/W32, ET6000 *************** *** 462,465 **** Refer to the .I XFree86(1) manual page. ! .\" $TOG: XF86_SVGA.man /main/22 1997/11/04 21:20:08 kaleb $ --- 464,467 ---- Refer to the .I XFree86(1) manual page. ! .\" $TOG: XF86_SVGA.man /main/23 1998/03/06 16:27:10 kaleb $ *** ./programs/Xserver/hw/xfree86/XF86_VGA16.man@@/PUBLIC-LATEST Tue Nov 4 21:17:17 1997 --- xc/programs/Xserver/hw/xfree86/XF86_VGA16.man Fri Mar 6 16:25:37 1998 *************** *** 1,5 **** ! .\" $XFree86: xc/programs/Xserver/hw/xfree86/XF86_VGA16.man,v 3.22.2.1 1997/05/21 15:02:22 dawes Exp $ ! .TH XF86_VGA16 1 "Release 6.4 (XFree86 3.3.1)" "X Version 11" .SH NAME XF86_VGA16 - 4 bit non-accelerated X Window System server for UNIX on x86 platforms --- 1,5 ---- ! .\" $XFree86: xc/programs/Xserver/hw/xfree86/XF86_VGA16.man,v 3.22.2.3 1998/02/26 13:58:54 dawes Exp $ ! .TH XF86_VGA16 1 "Version 3.3.2" "XFree86" .SH NAME XF86_VGA16 - 4 bit non-accelerated X Window System server for UNIX on x86 platforms *************** *** 23,29 **** ATI: 18800, 18800-1, 28800-2, 28800-4, 28800-5, 28800-6, 68800-3, 68800-6, 68800AX, 68800LX, 88800GX-C, 88800GX-D, 88800GX-E, 88800GX-F, 88800CX, 264CT, 264ET, ! 264VT, 264VT2, 264GT .TP 4 Tseng: ET4000 --- 23,30 ---- ATI: 18800, 18800-1, 28800-2, 28800-4, 28800-5, 28800-6, 68800-3, 68800-6, 68800AX, 68800LX, 88800GX-C, 88800GX-D, 88800GX-E, 88800GX-F, 88800CX, 264CT, 264ET, ! 264VT, 264GT (a.k.a. 3D Rage), 264VT-B, 264VT3, 264GT-B (a.k.a. 3D Rage II), ! 264GT3 (a.k.a. 3D Rage Pro) .TP 4 Tseng: ET4000 *************** *** 188,191 **** See also the .I XFree86(1) manual page. ! .\" $TOG: XF86_VGA16.man /main/16 1997/11/04 21:20:12 kaleb $ --- 189,192 ---- See also the .I XFree86(1) manual page. ! .\" $TOG: XF86_VGA16.man /main/17 1998/03/06 16:27:15 kaleb $ *** ./programs/Xserver/hw/xfree86/XFree86.man@@/PUBLIC-LATEST Sun Aug 10 12:57:50 1997 --- xc/programs/Xserver/hw/xfree86/XFree86.man Fri Mar 6 16:25:41 1998 *************** *** 1,5 **** ! .\" $XFree86: xc/programs/Xserver/hw/xfree86/XFree86.man,v 3.36.2.6 1997/07/26 09:21:14 dawes Exp $ ! .TH XFree86 1 "Version 3.3.1" "XFree86" .SH NAME XFree86 - X11R6 for UNIX on x86 platforms .SH DESCRIPTION --- 1,5 ---- ! .\" $XFree86: xc/programs/Xserver/hw/xfree86/XFree86.man,v 3.36.2.8 1998/02/26 13:58:55 dawes Exp $ ! .TH XFree86 1 "Version 3.3.2" "XFree86" .SH NAME XFree86 - X11R6 for UNIX on x86 platforms .SH DESCRIPTION *************** *** 16,29 **** .PP -- SVR3.2: SCO 3.2.2, 3.2.4, ISC 3.x, 4.x .br ! -- SVR4.0: ESIX, Microport, Dell, UHC, Consensys, MST, ISC, AT&T, NCR .br -- SVR4.2: Consensys, Univel (UnixWare) .br ! -- Solaris (x86) 2.1, 2.4 .br ! -- FreeBSD 1.1.5, 2.0, 2.0.5, NetBSD 1.0 (i386 port only) .br -- BSD/386 version 1.1 and BSD/OS 2.0 .br -- Mach (from CMU) --- 16,33 ---- .PP -- SVR3.2: SCO 3.2.2, 3.2.4, ISC 3.x, 4.x .br ! -- SVR4.0: ESIX, Microport, Dell, UHC, Consensys, MST, ISC, AT&T, NCR, PANIX .br -- SVR4.2: Consensys, Univel (UnixWare) .br ! -- Solaris (x86) 2.1, 2.4, 2.5, 2.5.1, 2.6 .br ! -- FreeBSD 2.0.5, 2.1, 2.1.5, 2.1.6, 2.1.7, 2.1.7.1, 2.2, 2.2.1, 2.2.2, 2.2.5, 2.2.6, 3.0-current .br + -- NetBSD 1.0, 1.1, 1.2, 1.2.1, 1.3 (i386 port only) + .br + -- OpenBSD 2.0, 2.1 + .br -- BSD/386 version 1.1 and BSD/OS 2.0 .br -- Mach (from CMU) *************** *** 403,409 **** Philip Homburg, \fIphilip@cs.vu.nl\fP Ported to \fBMinix-386vm\fP. .TP 8 ! Thomas Mueller, \fItm@systrix.de\fP Ported to \fBLynxOS\fP. .TP 8 Jon Tombs, \fItombs@XFree86.org\fP --- 407,413 ---- Philip Homburg, \fIphilip@cs.vu.nl\fP Ported to \fBMinix-386vm\fP. .TP 8 ! Thomas Mueller, \fItmueller@sysgo.de\fP Ported to \fBLynxOS\fP. .TP 8 Jon Tombs, \fItombs@XFree86.org\fP *************** *** 566,569 **** \fIXFree86\fP source is available from the FTP server \fIftp.XFree86.org\fP, among others. Send email to \fIXFree86@XFree86.org\fP for details. ! .\" $TOG: XFree86.man /main/27 1997/08/10 12:56:26 kaleb $ --- 570,573 ---- \fIXFree86\fP source is available from the FTP server \fIftp.XFree86.org\fP, among others. Send email to \fIXFree86@XFree86.org\fP for details. ! .\" $TOG: XFree86.man /main/28 1998/03/06 16:27:19 kaleb $ *** ./programs/Xserver/hw/xfree86/accel/agx/agx.c@@/PUBLIC-LATEST Sat Jul 19 09:27:35 1997 --- xc/programs/Xserver/hw/xfree86/accel/agx/agx.c Fri Mar 6 16:30:24 1998 *************** *** 1,4 **** ! /* $XFree86: xc/programs/Xserver/hw/xfree86/accel/agx/agx.c,v 3.53.2.3 1997/05/11 02:56:01 dawes Exp $ */ /* * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany. * Copyright 1993 by Kevin E. Martin, Chapel Hill, North Carolina. --- 1,4 ---- ! /* $XFree86: xc/programs/Xserver/hw/xfree86/accel/agx/agx.c,v 3.53.2.4 1998/02/07 10:05:04 hohndel Exp $ */ /* * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany. * Copyright 1993 by Kevin E. Martin, Chapel Hill, North Carolina. *************** *** 31,37 **** * Rewritten for the AGX by Henry A. Worth (haw30@eng.amdahl.com) * */ ! /* $TOG: agx.c /main/21 1997/07/19 09:27:36 kaleb $ */ #include "X.h" --- 31,37 ---- * Rewritten for the AGX by Henry A. Worth (haw30@eng.amdahl.com) * */ ! /* $TOG: agx.c /main/22 1998/03/06 16:32:02 kaleb $ */ #include "X.h" *************** *** 146,152 **** 0, /* int textClockFreq */ NULL, /* char* DCConfig */ NULL, /* char* DCOptions */ ! 0 /* int MemClk */ #ifdef XFreeXDGA ,0, /* int directMode */ agxSetVidPage, /* Set Vid Page */ --- 146,153 ---- 0, /* int textClockFreq */ NULL, /* char* DCConfig */ NULL, /* char* DCOptions */ ! 0, /* int MemClk */ ! 0 /* int LCDClk */ #ifdef XFreeXDGA ,0, /* int directMode */ agxSetVidPage, /* Set Vid Page */ *** ./programs/Xserver/hw/xfree86/accel/agx/agxCmap.c@@/PUBLIC-LATEST Sun Oct 19 15:00:39 1997 --- xc/programs/Xserver/hw/xfree86/accel/agx/agxCmap.c Fri Mar 6 16:30:30 1998 *************** *** 25,31 **** * Rewritten for the AGX by Henry A Worth (haw30@eng.amdahl.com) * */ ! /* $TOG: agxCmap.c /main/11 1997/10/19 15:02:43 kaleb $ */ #include "X.h" #include "Xproto.h" --- 25,31 ---- * Rewritten for the AGX by Henry A Worth (haw30@eng.amdahl.com) * */ ! /* $TOG: agxCmap.c /main/12 1998/03/06 16:32:08 kaleb $ */ #include "X.h" #include "Xproto.h" *************** *** 66,72 **** int ndef; xColorItem *pdefs; { ! int i,nshift; xColorItem directDefs[256]; extern LUTENTRY agxsavedLUT[256]; unsigned char oldIndex; --- 66,72 ---- int ndef; xColorItem *pdefs; { ! int i; xColorItem directDefs[256]; extern LUTENTRY agxsavedLUT[256]; unsigned char oldIndex; *************** *** 97,109 **** palDataIdx = 0; palDataReg = VGA_PAL_DATA; } - - nshift = ((xf86Dac8Bit) ? 8 : 10); for (i = 0; i < ndef; i++) { ! unsigned char red, green, blue, idx; ! idx = pdefs[i].pixel & 0xff; if (idx == overScan) newOverScan = TRUE; /* --- 97,107 ---- palDataIdx = 0; palDataReg = VGA_PAL_DATA; } for (i = 0; i < ndef; i++) { ! unsigned int red, green, blue, idx; ! idx = pdefs[i].pixel; if (idx == overScan) newOverScan = TRUE; /* *************** *** 111,119 **** * The original XGA used most-significant 6-bits (unlike VGA's LS 6-bits) * */ ! red = agxsavedLUT[idx].r = pdefs[i].red >> nshift; ! green = agxsavedLUT[idx].g = pdefs[i].green >> nshift; ! blue = agxsavedLUT[idx].b = pdefs[i].blue >> nshift; if ( xf86VTSema #ifdef XFreeXDGA --- 109,124 ---- * The original XGA used most-significant 6-bits (unlike VGA's LS 6-bits) * */ ! if (xf86Dac8Bit) { /* XGA 8-bit or 6-bit */ ! red = agxsavedLUT[idx].r = pdefs[i].red >> 8; ! green = agxsavedLUT[idx].g = pdefs[i].green >> 8; ! blue = agxsavedLUT[idx].b = pdefs[i].blue >> 8; ! } ! else { /* VGA style 6-bit */ ! red = agxsavedLUT[idx].r = pdefs[i].red >> 10; ! green = agxsavedLUT[idx].g = pdefs[i].green >> 10; ! blue = agxsavedLUT[idx].b = pdefs[i].blue >> 10; ! } if ( xf86VTSema #ifdef XFreeXDGA *************** *** 197,203 **** Pixel * ppix; xrgb * prgb; xColorItem *defs; ! int i,j; if (pmap == oldmap) --- 202,208 ---- Pixel * ppix; xrgb * prgb; xColorItem *defs; ! int i; if (pmap == oldmap) *************** *** 221,263 **** for ( i=0; iclass == GrayScale || pmap->class == PseudoColor) ! { ! for ( i=j=0; ired[i].fShared || pmap->red[i].refcnt != 0) ! { ! defs[j].pixel = i; ! defs[j].flags = DoRed|DoGreen|DoBlue; ! if (pmap->red[i].fShared) ! { ! defs[j].red = pmap->red[i].co.shco.red->color; ! defs[j].green = pmap->red[i].co.shco.green->color; ! defs[j].blue = pmap->red[i].co.shco.blue->color; ! } ! else if (pmap->red[i].refcnt != 0) ! { ! defs[j].red = pmap->red[i].co.local.red; ! defs[j].green = pmap->red[i].co.local.green; ! defs[j].blue = pmap->red[i].co.local.blue; ! } ! j++; ! } ! } ! entries = j; ! } ! else ! { ! QueryColors( pmap, entries, ppix, prgb); ! for ( i=0; iclass == GrayScale || pmap->class == PseudoColor) ! { ! for ( i=j=0; ired[i].fShared || pmap->red[i].refcnt != 0) ! { ! defs[j].pixel = i; ! defs[j].flags = DoRed|DoGreen|DoBlue; ! if (pmap->red[i].fShared) ! { ! defs[j].red = pmap->red[i].co.shco.red->color; ! defs[j].green = pmap->red[i].co.shco.green->color; ! defs[j].blue = pmap->red[i].co.shco.blue->color; ! } ! else if (pmap->red[i].refcnt != 0) ! { ! defs[j].red = pmap->red[i].co.local.red; ! defs[j].green = pmap->red[i].co.local.green; ! defs[j].blue = pmap->red[i].co.local.blue; ! } ! j++; ! } ! } ! entries = j; ! } ! else ! { ! QueryColors( pmap, entries, ppix, prgb); ! for ( i=0; iclass == GrayScale || pmap->class == PseudoColor) ! { ! for ( i=j=0; ired[i].fShared || pmap->red[i].refcnt != 0) ! { ! defs[j].pixel = i; ! defs[j].flags = DoRed|DoGreen|DoBlue; ! if (pmap->red[i].fShared) ! { ! defs[j].red = pmap->red[i].co.shco.red->color; ! defs[j].green = pmap->red[i].co.shco.green->color; ! defs[j].blue = pmap->red[i].co.shco.blue->color; ! } ! else if (pmap->red[i].refcnt != 0) ! { ! defs[j].red = pmap->red[i].co.local.red; ! defs[j].green = pmap->red[i].co.local.green; ! defs[j].blue = pmap->red[i].co.local.blue; ! } ! j++; ! } ! } ! entries = j; ! } ! else ! { ! QueryColors( pmap, entries, ppix, prgb); ! for ( i=0; i * --- 1,4 ---- ! /* $TOG: i128.c /main/19 1998/03/07 14:24:38 kaleb $ */ /* * Copyright 1995 by Robin Cutshaw * *************** *** 22,34 **** * */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/accel/i128/i128.c,v 3.22.2.9 1997/07/26 06:39:27 dawes Exp $ */ #include "i128.h" #include "i128reg.h" #include "xf86_HWlib.h" #include "xf86_PCI.h" - #define XCONFIG_FLAGS_ONLY #include "xf86_Config.h" #include "Ti302X.h" #include "IBMRGB.h" --- 22,33 ---- * */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/accel/i128/i128.c,v 3.22.2.11 1998/02/07 10:05:06 hohndel Exp $ */ #include "i128.h" #include "i128reg.h" #include "xf86_HWlib.h" #include "xf86_PCI.h" #include "xf86_Config.h" #include "Ti302X.h" #include "IBMRGB.h" *************** *** 37,42 **** --- 36,42 ---- extern char *xf86VisualNames[]; extern int defaultColorVisualClass; + extern Bool xf86ProbeFailed; static int i128ValidMode( *************** *** 111,117 **** 0, /* int textClockFreq */ NULL, /* char* DCConfig */ NULL, /* char* DCOptions */ ! 0 /* int MemClk */ #ifdef XFreeXDGA ,0, /* int directMode */ 0, /* Set Vid Page */ --- 111,118 ---- 0, /* int textClockFreq */ NULL, /* char* DCConfig */ NULL, /* char* DCOptions */ ! 0, /* int MemClk */ ! 0 /* int LCDClk */ #ifdef XFreeXDGA ,0, /* int directMode */ 0, /* Set Vid Page */ *************** *** 146,155 **** Bool i128BlockCursor, i128ReloadCursor; int i128CursorStartX, i128CursorStartY, i128CursorLines; int i128DeviceType; ! int i128MemoryTypeDram = 0; int i128RamdacType = UNKNOWN_DAC; ! extern Bool xf86Exiting, xf86Resetting, xf86ProbeFailed, xf86Verbose; void (*i128ImageReadFunc)( #if NeedFunctionPrototypes --- 147,156 ---- Bool i128BlockCursor, i128ReloadCursor; int i128CursorStartX, i128CursorStartY, i128CursorLines; int i128DeviceType; ! int i128MemoryType = I128_MEMORY_UNKNOWN; int i128RamdacType = UNKNOWN_DAC; ! extern Bool xf86Exiting, xf86Resetting; void (*i128ImageReadFunc)( #if NeedFunctionPrototypes *************** *** 167,172 **** --- 168,174 ---- #endif ); + /* * i128PrintIdent -- print identification message */ *************** *** 177,182 **** --- 179,189 ---- i128InfoRec.name, i128InfoRec.patchLevel); } + + /* + * i128Probe -- find the card on the PCI bus + */ + #ifdef DPMSExtension extern BOOL DPMSEnabledSwitch; extern BOOL DPMSDisabledSwitch; *************** *** 183,192 **** extern BOOL DPMSEnabled; #endif - /* - * i128Probe -- find the card on the PCI bus - */ - Bool i128Probe() { --- 190,195 ---- *************** *** 195,210 **** int maxDisplayWidth, maxDisplayHeight; unsigned short ioaddr; OFlagSet validOptions; ! unsigned PCI_CtrlIOPorts[] = { 0xCF8, 0xCFA }; ! int Num_PCI_CtrlIOPorts = 2; ! unsigned PCI_DevIOPorts[16]; ! int Num_PCI_DevIOPorts = 16; ! unsigned I128_IOPorts[] = { 0x0000, 0x0000 }; ! int Num_I128_IOPorts = 2; ! unsigned char n, m, p, mdc; float mclk; pciConfigPtr pcrp, *pcrpp; ! unsigned char tmpl, tmph, tmp; extern i128Registers iR; pcrpp = xf86scanpci(i128InfoRec.scrnIndex); --- 198,207 ---- int maxDisplayWidth, maxDisplayHeight; unsigned short ioaddr; OFlagSet validOptions; ! unsigned char n, m, p, mdc, df; float mclk; pciConfigPtr pcrp, *pcrpp; ! CARD32 tmpl, tmph, tmp; extern i128Registers iR; pcrpp = xf86scanpci(i128InfoRec.scrnIndex); *************** *** 215,221 **** i = 0; while ((pcrp = pcrpp[i]) != (pciConfigPtr)NULL) { if ((pcrp->_device_vendor == I128_DEVICE_ID1) || ! (pcrp->_device_vendor == I128_DEVICE_ID2)) break; i++; } --- 212,219 ---- i = 0; while ((pcrp = pcrpp[i]) != (pciConfigPtr)NULL) { if ((pcrp->_device_vendor == I128_DEVICE_ID1) || ! (pcrp->_device_vendor == I128_DEVICE_ID2) || ! (pcrp->_device_vendor == I128_DEVICE_ID3)) break; i++; } *************** *** 227,240 **** i128DeviceType = pcrp->_device_vendor; - if (((pcrp->_status_command & 0x03) == 0x03) && - ((pcrp->rsvd2 >>16) == 0x08)) - i128MemoryTypeDram = 1; - - for (i=0; i<11; i++) /* 11 32bit I/O address registers (0x00-0x28) */ - PCI_DevIOPorts[i] = iR.iobase + (i*4); - - xf86AddIOPorts(i128InfoRec.scrnIndex, 11, PCI_DevIOPorts); xf86EnableIOPorts(i128InfoRec.scrnIndex); i128io.rbase_g = inl(iR.iobase) & 0xFFFFFF00; --- 225,230 ---- *************** *** 245,251 **** i128io.rbase_e = inl(iR.iobase + 0x14) & 0xFFFF8003; i128io.id = inl(iR.iobase + 0x18) & /* 0x7FFFFFFF */ 0xFFFFFFFF; i128io.config1 = inl(iR.iobase + 0x1C) & /* 0xF3333F1F */ 0xFF333F1F; ! i128io.config2 = inl(iR.iobase + 0x20) & /* 0xFFF70F03 */ 0xC1F70FFF; i128io.soft_sw = inl(iR.iobase + 0x28) & 0x0000FFFF; i128io.vga_ctl = inl(iR.iobase + 0x30) & 0x0000FFFF; --- 235,241 ---- i128io.rbase_e = inl(iR.iobase + 0x14) & 0xFFFF8003; i128io.id = inl(iR.iobase + 0x18) & /* 0x7FFFFFFF */ 0xFFFFFFFF; i128io.config1 = inl(iR.iobase + 0x1C) & /* 0xF3333F1F */ 0xFF333F1F; ! i128io.config2 = inl(iR.iobase + 0x20) & 0xC1F70FFF; i128io.soft_sw = inl(iR.iobase + 0x28) & 0x0000FFFF; i128io.vga_ctl = inl(iR.iobase + 0x30) & 0x0000FFFF; *************** *** 309,321 **** i128io.config2 |= 0x00500000; outl(iR.iobase + 0x20, i128io.config2); xf86DisableIOPorts(i128InfoRec.scrnIndex); - xf86ClearIOPortList(i128InfoRec.scrnIndex); xf86ProbeFailed = FALSE; ! ErrorF("%s %s: I128 revision (%d)\n", ! XCONFIG_PROBED, i128InfoRec.name, i128io.id&0x7); OFLG_ZERO(&validOptions); OFLG_SET(OPTION_SHOWCACHE, &validOptions); --- 299,324 ---- i128io.config2 |= 0x00500000; outl(iR.iobase + 0x20, i128io.config2); + if (i128DeviceType == I128_DEVICE_ID3) { + if ((i128io.config2&6) == 2) + i128MemoryType = I128_MEMORY_SGRAM; + else + i128MemoryType = I128_MEMORY_WRAM; + } else if (i128DeviceType == I128_DEVICE_ID2) { + if (((pcrp->_status_command & 0x03) == 0x03) && + ((pcrp->rsvd2 >>16) == 0x08)) + i128MemoryType = I128_MEMORY_DRAM; + } + xf86DisableIOPorts(i128InfoRec.scrnIndex); xf86ProbeFailed = FALSE; ! ErrorF("%s %s: I128%s revision (%d)\n", ! XCONFIG_PROBED, i128InfoRec.name, ! i128DeviceType == I128_DEVICE_ID2 ? "-II" : ! i128DeviceType == I128_DEVICE_ID3 ? "-T2R" : "", ! i128io.id&0x7); OFLG_ZERO(&validOptions); OFLG_SET(OPTION_SHOWCACHE, &validOptions); *************** *** 328,339 **** if (xf86Verbose) ErrorF("%s %s: card type: PCI\n", XCONFIG_PROBED, i128InfoRec.name); ! i128InfoRec.videoRam = 2048; /* default to 2MB */ ! if (i128io.config1 & 0x04) /* 128 bit mode */ ! i128InfoRec.videoRam <<= 1; ! if (i128io.id & 0x0400) /* 2 banks VRAM */ ! i128InfoRec.videoRam <<= 1; if (xf86Verbose) ErrorF("%s %s: videoram: %dk\n", XCONFIG_GIVEN, i128InfoRec.name, i128InfoRec.videoRam); --- 331,367 ---- if (xf86Verbose) ErrorF("%s %s: card type: PCI\n", XCONFIG_PROBED, i128InfoRec.name); ! i128InfoRec.videoRam = 0; + if (i128DeviceType == I128_DEVICE_ID3) { + switch ((pcrp->rsvd2>>16)&0xFFF7) { + case 0x00: /* 4MB card, no daughtercard */ + i128InfoRec.videoRam = 4 * 1024; break; + case 0x01: /* 4MB card, 4MB daughtercard */ + case 0x04: /* 8MB card, no daughtercard */ + i128InfoRec.videoRam = 8 * 1024; break; + case 0x02: /* 4MB card, 8MB daughtercard */ + case 0x05: /* 8MB card, 4MB daughtercard */ + i128InfoRec.videoRam = 12 * 1024; break; + case 0x06: /* 8MB card, 8MB daughtercard */ + i128InfoRec.videoRam = 16 * 1024; break; + case 0x03: /* 4MB card, 16 daughtercard */ + i128InfoRec.videoRam = 20 * 1024; break; + case 0x07: /* 8MB card, 16MB daughtercard */ + i128InfoRec.videoRam = 24 * 1024; break; + default: + break; + } + } + + if (i128InfoRec.videoRam == 0) { + i128InfoRec.videoRam = 2048; /* default to 2MB */ + if (i128io.config1 & 0x04) /* 128 bit mode */ + i128InfoRec.videoRam <<= 1; + if (i128io.id & 0x0400) /* 2 banks VRAM */ + i128InfoRec.videoRam <<= 1; + } + if (xf86Verbose) ErrorF("%s %s: videoram: %dk\n", XCONFIG_GIVEN, i128InfoRec.name, i128InfoRec.videoRam); *************** *** 393,399 **** } maxDisplayWidth = 4096; ! maxDisplayHeight = 2048; if (i128InfoRec.virtualX > maxDisplayWidth) { ErrorF("%s: Virtual width (%d) is too large. Maximum is %d\n", --- 421,427 ---- } maxDisplayWidth = 4096; ! maxDisplayHeight = 4096; if (i128InfoRec.virtualX > maxDisplayWidth) { ErrorF("%s: Virtual width (%d) is too large. Maximum is %d\n", *************** *** 431,437 **** i128mem.rbase_a = i128mem.rbase_g + (16 * 1024)/4; i128mem.rbase_b = i128mem.rbase_g + (24 * 1024)/4; i128mem.rbase_i = i128mem.rbase_g + (32 * 1024)/4; - i128mem.rbase_g_b = (unsigned char *)i128mem.rbase_g; if (pcrp->_device_vendor == I128_DEVICE_ID1) { if (i128io.id & 0x0400) /* 2 banks VRAM */ --- 459,464 ---- *************** *** 443,448 **** --- 470,477 ---- i128RamdacType = IBM528_DAC; else i128RamdacType = IBM526_DAC; + } else if (pcrp->_device_vendor == I128_DEVICE_ID3) { + i128RamdacType = IBM526_DAC; } else { ErrorF("%s: Unknown I128 rev (%x).\n", i128InfoRec.name, pcrp->_device_vendor); *************** *** 453,460 **** case TI3025_DAC: /* verify that the ramdac is a TVP3025 */ ! i128mem.rbase_g_b[INDEX_TI] = TI_ID; ! if (i128mem.rbase_g_b[DATA_TI] != TI_VIEWPOINT25_ID) { ErrorF("%s: Ti3025 Ramdac not found.\n", i128InfoRec.name); return(FALSE); } --- 482,489 ---- case TI3025_DAC: /* verify that the ramdac is a TVP3025 */ ! i128mem.rbase_g[INDEX_TI] = TI_ID; MB; ! if ((i128mem.rbase_g[DATA_TI]&0xFF) != TI_VIEWPOINT25_ID) { ErrorF("%s: Ti3025 Ramdac not found.\n", i128InfoRec.name); return(FALSE); } *************** *** 461,480 **** OFLG_SET(CLOCK_OPTION_TI3025, &i128InfoRec.clockOptions); i128InfoRec.ramdac = "ti3025"; ! i128mem.rbase_g_b[INDEX_TI] = TI_PLL_CONTROL; ! i128mem.rbase_g_b[DATA_TI] = 0x00; ! i128mem.rbase_g_b[INDEX_TI] = TI_MCLK_PLL_DATA; ! n = i128mem.rbase_g_b[DATA_TI]&0x7f; ! i128mem.rbase_g_b[INDEX_TI] = TI_PLL_CONTROL; ! i128mem.rbase_g_b[DATA_TI] = 0x01; ! i128mem.rbase_g_b[INDEX_TI] = TI_MCLK_PLL_DATA; ! m = i128mem.rbase_g_b[DATA_TI]&0x7f; ! i128mem.rbase_g_b[INDEX_TI] = TI_PLL_CONTROL; ! i128mem.rbase_g_b[DATA_TI] = 0x02; ! i128mem.rbase_g_b[INDEX_TI] = TI_MCLK_PLL_DATA; ! p = i128mem.rbase_g_b[DATA_TI]&0x03; ! i128mem.rbase_g_b[INDEX_TI] = TI_MCLK_DCLK_CONTROL; ! mdc = i128mem.rbase_g_b[DATA_TI]; if (mdc&0x08) mdc = (mdc&0x07)*2 + 2; else --- 490,509 ---- OFLG_SET(CLOCK_OPTION_TI3025, &i128InfoRec.clockOptions); i128InfoRec.ramdac = "ti3025"; ! i128mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB; ! i128mem.rbase_g[DATA_TI] = 0x00; MB; ! i128mem.rbase_g[INDEX_TI] = TI_MCLK_PLL_DATA; MB; ! n = i128mem.rbase_g[DATA_TI]&0x7f; ! i128mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB; ! i128mem.rbase_g[DATA_TI] = 0x01; MB; ! i128mem.rbase_g[INDEX_TI] = TI_MCLK_PLL_DATA; MB; ! m = i128mem.rbase_g[DATA_TI]&0x7f; ! i128mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB; ! i128mem.rbase_g[DATA_TI] = 0x02; MB; ! i128mem.rbase_g[INDEX_TI] = TI_MCLK_PLL_DATA; MB; ! p = i128mem.rbase_g[DATA_TI]&0x03; ! i128mem.rbase_g[INDEX_TI] = TI_MCLK_DCLK_CONTROL; MB; ! mdc = i128mem.rbase_g[DATA_TI]&0xFF; if (mdc&0x08) mdc = (mdc&0x07)*2 + 2; else *************** *** 497,517 **** /* verify that the ramdac is an IBM526 */ i128InfoRec.ramdac = "ibm526"; ! tmph = i128mem.rbase_g_b[IDXH_I]; ! tmpl = i128mem.rbase_g_b[IDXL_I]; ! i128mem.rbase_g_b[IDXH_I] = 0; ! i128mem.rbase_g_b[IDXL_I] = IBMRGB_id; ! tmp = i128mem.rbase_g_b[DATA_I]; ! i128mem.rbase_g_b[IDXL_I] = tmpl; ! i128mem.rbase_g_b[IDXH_I] = tmph; if (tmp != 2) { ErrorF("%s: %s Ramdac not found.\n", i128InfoRec.name, i128InfoRec.ramdac); return(FALSE); } ! /* Set MClock speed?? */ OFLG_SET(CLOCK_OPTION_IBMRGB, &i128InfoRec.clockOptions); break; case IBM528_DAC: --- 526,559 ---- /* verify that the ramdac is an IBM526 */ i128InfoRec.ramdac = "ibm526"; ! tmph = i128mem.rbase_g[IDXH_I] & 0xFF; ! tmpl = i128mem.rbase_g[IDXL_I] & 0xFF; ! i128mem.rbase_g[IDXH_I] = 0; MB; ! i128mem.rbase_g[IDXL_I] = IBMRGB_id; MB; ! tmp = i128mem.rbase_g[DATA_I] & 0xFF; ! ! i128mem.rbase_g[IDXL_I] = IBMRGB_sysclk_ref_div; MB; ! n = i128mem.rbase_g[DATA_I] & 0x1f; ! i128mem.rbase_g[IDXL_I] = IBMRGB_sysclk_vco_div; MB; ! m = i128mem.rbase_g[DATA_I]; ! df = m>>6; ! m &= 0x3f; ! if (n == 0) { m=0; n=1; } ! mclk = ((2517500 * (m+65)) / n / (8>>df) + 50) / 100; ! ! i128mem.rbase_g[IDXL_I] = tmpl; MB; ! i128mem.rbase_g[IDXH_I] = tmph; MB; if (tmp != 2) { ErrorF("%s: %s Ramdac not found.\n", i128InfoRec.name, i128InfoRec.ramdac); return(FALSE); } ! OFLG_SET(CLOCK_OPTION_IBMRGB, &i128InfoRec.clockOptions); + if (xf86Verbose) + ErrorF("%s %s: Using IBM 526 programmable clock (MCLK %1.3f MHz)\n", + XCONFIG_PROBED, i128InfoRec.name, mclk / 1000.0); break; case IBM528_DAC: *************** *** 518,538 **** /* verify that the ramdac is an IBM528 */ i128InfoRec.ramdac = "ibm528"; ! tmph = i128mem.rbase_g_b[IDXH_I]; ! tmpl = i128mem.rbase_g_b[IDXL_I]; ! i128mem.rbase_g_b[IDXH_I] = 0; ! i128mem.rbase_g_b[IDXL_I] = IBMRGB_id; ! tmp = i128mem.rbase_g_b[DATA_I]; ! i128mem.rbase_g_b[IDXL_I] = tmpl; ! i128mem.rbase_g_b[IDXH_I] = tmph; if (tmp != 2) { ErrorF("%s: %s Ramdac not found.\n", i128InfoRec.name, i128InfoRec.ramdac); return(FALSE); } ! /* Set MClock speed?? */ OFLG_SET(CLOCK_OPTION_IBMRGB, &i128InfoRec.clockOptions); break; default: --- 560,593 ---- /* verify that the ramdac is an IBM528 */ i128InfoRec.ramdac = "ibm528"; ! tmph = i128mem.rbase_g[IDXH_I] & 0xFF; ! tmpl = i128mem.rbase_g[IDXL_I] & 0xFF; ! i128mem.rbase_g[IDXH_I] = 0; MB; ! i128mem.rbase_g[IDXL_I] = IBMRGB_id; MB; ! tmp = i128mem.rbase_g[DATA_I] & 0xFF; ! ! i128mem.rbase_g[IDXL_I] = IBMRGB_sysclk_ref_div; MB; ! n = i128mem.rbase_g[DATA_I] & 0x1f; ! i128mem.rbase_g[IDXL_I] = IBMRGB_sysclk_vco_div; MB; ! m = i128mem.rbase_g[DATA_I] & 0xFF; ! df = m>>6; ! m &= 0x3f; ! if (n == 0) { m=0; n=1; } ! mclk = ((2517500 * (m+65)) / n / (8>>df) + 50) / 100; ! ! i128mem.rbase_g[IDXL_I] = tmpl; MB; ! i128mem.rbase_g[IDXH_I] = tmph; MB; if (tmp != 2) { ErrorF("%s: %s Ramdac not found.\n", i128InfoRec.name, i128InfoRec.ramdac); return(FALSE); } ! OFLG_SET(CLOCK_OPTION_IBMRGB, &i128InfoRec.clockOptions); + if (xf86Verbose) + ErrorF("%s %s: Using IBM 528 programmable clock (MCLK %1.3f MHz)\n", + XCONFIG_PROBED, i128InfoRec.name, mclk / 1000.0); break; default: *************** *** 550,555 **** --- 605,611 ---- */ if (i128InfoRec.dacSpeeds[0] <= 0) { if ((pcrp->_device_vendor == I128_DEVICE_ID2) || + (pcrp->_device_vendor == I128_DEVICE_ID3) || (i128InfoRec.videoRam == 8192)) i128InfoRec.dacSpeeds[0] = 220000; else *************** *** 620,626 **** if ((tx != i128InfoRec.virtualX) || (ty != i128InfoRec.virtualY)) OFLG_CLR(XCONFIG_VIRTUAL,&i128InfoRec.xconfigFlag); ! if (i128InfoRec.virtualX <= 640) i128DisplayWidth = 640; else if (i128InfoRec.virtualX <= 800) i128DisplayWidth = 800; --- 676,686 ---- if ((tx != i128InfoRec.virtualX) || (ty != i128InfoRec.virtualY)) OFLG_CLR(XCONFIG_VIRTUAL,&i128InfoRec.xconfigFlag); ! if (pcrp->_device_vendor == I128_DEVICE_ID3) { ! i128DisplayWidth = i128InfoRec.virtualX; ! if ((i128InfoRec.virtualX % 128) != 0) ! i128DisplayWidth += 128 - (i128InfoRec.virtualX % 128); ! } else if (i128InfoRec.virtualX <= 640) i128DisplayWidth = 640; else if (i128InfoRec.virtualX <= 800) i128DisplayWidth = 800; *************** *** 641,647 **** i128DisplayOffset = 0x400000L % (i128DisplayWidth * (i128InfoRec.bitsPerPixel/8)); ! i128VideoMem = (pointer)((CARD32)i128VideoMem + i128DisplayOffset); if (OFLG_ISSET(OPTION_DAC_8_BIT, &i128InfoRec.options) || (i128InfoRec.bitsPerPixel > 8)) --- 701,707 ---- i128DisplayOffset = 0x400000L % (i128DisplayWidth * (i128InfoRec.bitsPerPixel/8)); ! i128VideoMem = (pointer)&((char *)i128VideoMem)[i128DisplayOffset]; if (OFLG_ISSET(OPTION_DAC_8_BIT, &i128InfoRec.options) || (i128InfoRec.bitsPerPixel > 8)) *************** *** 705,711 **** { unsigned char tmp, tmp2, m, n, df, best_m, best_n, best_df, max_n; ! unsigned char tmpl, tmph, tmpc; long f, vrf, outf, best_vrf, best_diff, best_outf, diff; long requested_freq; --- 765,771 ---- { unsigned char tmp, tmp2, m, n, df, best_m, best_n, best_df, max_n; ! CARD32 tmpl, tmph, tmpc; long f, vrf, outf, best_vrf, best_diff, best_outf, diff; long requested_freq; *************** *** 775,849 **** return(FALSE); } ! i128mem.rbase_g_b[PEL_MASK] = 0xff; ! tmpc = i128mem.rbase_g_b[IDXCTL_I]; ! tmph = i128mem.rbase_g_b[IDXH_I]; ! tmpl = i128mem.rbase_g_b[IDXL_I]; ! i128mem.rbase_g_b[IDXH_I] = 0; ! i128mem.rbase_g_b[IDXCTL_I] = 0; ! i128mem.rbase_g_b[IDXL_I] = IBMRGB_misc_clock; ! tmp2 = i128mem.rbase_g_b[DATA_I]; ! i128mem.rbase_g_b[DATA_I] = tmp2 | 0x81; ! i128mem.rbase_g_b[IDXL_I] = IBMRGB_m0+4; ! i128mem.rbase_g_b[DATA_I] = (best_df<<6) | (best_m&0x3f); ! i128mem.rbase_g_b[IDXL_I] = IBMRGB_n0+4; ! i128mem.rbase_g_b[DATA_I] = best_n; ! i128mem.rbase_g_b[IDXL_I] = IBMRGB_pll_ctrl1; ! tmp2 = i128mem.rbase_g_b[DATA_I]; ! i128mem.rbase_g_b[DATA_I] = (tmp2&0xf8) | 3; /* 8 M/N pairs in PLL */ ! i128mem.rbase_g_b[IDXL_I] = IBMRGB_pll_ctrl2; ! tmp2 = i128mem.rbase_g_b[DATA_I]; ! i128mem.rbase_g_b[DATA_I] = (tmp2&0xf0) | 2; /* clock number 2 */ ! i128mem.rbase_g_b[IDXL_I] = IBMRGB_misc_clock; ! tmp2 = i128mem.rbase_g_b[DATA_I] & 0xf0; ! i128mem.rbase_g_b[DATA_I] = tmp2 | ((flags & V_DBLCLK) ? 0x03 : 0x01); ! i128mem.rbase_g_b[IDXL_I] = IBMRGB_sync; ! i128mem.rbase_g_b[DATA_I] = 0x00; /* Use 0x10 for +Hsync, 0x20 for +Vsync */ ! i128mem.rbase_g_b[IDXL_I] = IBMRGB_hsync_pos; ! i128mem.rbase_g_b[DATA_I] = 0x01; /* Delay syncs by 1 pclock */ ! i128mem.rbase_g_b[IDXL_I] = IBMRGB_pwr_mgmt; ! i128mem.rbase_g_b[DATA_I] = 0x00; ! i128mem.rbase_g_b[IDXL_I] = IBMRGB_dac_op; tmp2 = (i128RamdacType == IBM528_DAC) ? 0x02 : 0x00; /* fast slew */ if (i128DACSyncOnGreen) tmp2 |= 0x08; ! i128mem.rbase_g_b[DATA_I] = tmp2; ! i128mem.rbase_g_b[IDXL_I] = IBMRGB_pal_ctrl; ! i128mem.rbase_g_b[DATA_I] = 0x00; ! i128mem.rbase_g_b[IDXL_I] = IBMRGB_sysclk; ! i128mem.rbase_g_b[DATA_I] = 0x01; ! i128mem.rbase_g_b[IDXL_I] = IBMRGB_misc1; ! tmp2 = i128mem.rbase_g_b[DATA_I] & 0xbc; ! if (!i128MemoryTypeDram) tmp2 |= (i128RamdacType == IBM528_DAC) ? 3 : 1; ! i128mem.rbase_g_b[DATA_I] = tmp2; ! i128mem.rbase_g_b[IDXL_I] = IBMRGB_misc2; tmp2 = 0x03; if (i128DAC8Bit) tmp2 |= 0x04; ! if (!(i128MemoryTypeDram && (i128InfoRec.bitsPerPixel > 16))) tmp2 |= 0x40; ! i128mem.rbase_g_b[DATA_I] = tmp2; ! i128mem.rbase_g_b[IDXL_I] = IBMRGB_misc3; ! i128mem.rbase_g_b[DATA_I] = 0x00; ! i128mem.rbase_g_b[IDXL_I] = IBMRGB_misc4; ! i128mem.rbase_g_b[DATA_I] = 0x00; /* ?? There is no write to cursor control register */ if (i128RamdacType == IBM526_DAC) { /* program mclock to 52MHz */ ! i128mem.rbase_g_b[IDXL_I] = IBMRGB_sysclk_ref_div; ! i128mem.rbase_g_b[DATA_I] = 0x08; ! i128mem.rbase_g_b[IDXL_I] = IBMRGB_sysclk_vco_div; ! i128mem.rbase_g_b[DATA_I] = 0x41; /* should delay at least a millisec so we'll wait 50 */ usleep(50000); } --- 835,910 ---- return(FALSE); } ! i128mem.rbase_g[PEL_MASK] = 0xFF; MB; ! tmpc = i128mem.rbase_g[IDXCTL_I] & 0xFF; ! tmph = i128mem.rbase_g[IDXH_I] & 0xFF; ! tmpl = i128mem.rbase_g[IDXL_I] & 0xFF; ! i128mem.rbase_g[IDXH_I] = 0; MB; ! i128mem.rbase_g[IDXCTL_I] = 0; MB; ! i128mem.rbase_g[IDXL_I] = IBMRGB_misc_clock; MB; ! tmp2 = i128mem.rbase_g[DATA_I] & 0xFF; ! i128mem.rbase_g[DATA_I] = tmp2 | 0x81; MB; ! i128mem.rbase_g[IDXL_I] = IBMRGB_m0+4; MB; ! i128mem.rbase_g[DATA_I] = (best_df<<6) | (best_m&0x3f); MB; ! i128mem.rbase_g[IDXL_I] = IBMRGB_n0+4; MB; ! i128mem.rbase_g[DATA_I] = best_n; MB; ! i128mem.rbase_g[IDXL_I] = IBMRGB_pll_ctrl1; MB; ! tmp2 = i128mem.rbase_g[DATA_I] & 0xFF; ! i128mem.rbase_g[DATA_I] = (tmp2&0xf8) | 3; /* 8 M/N pairs in PLL */ MB; ! i128mem.rbase_g[IDXL_I] = IBMRGB_pll_ctrl2; MB; ! tmp2 = i128mem.rbase_g[DATA_I] & 0xFF; ! i128mem.rbase_g[DATA_I] = (tmp2&0xf0) | 2; /* clock number 2 */ MB; ! i128mem.rbase_g[IDXL_I] = IBMRGB_misc_clock; MB; ! tmp2 = i128mem.rbase_g[DATA_I] & 0xf0; ! i128mem.rbase_g[DATA_I] = tmp2 | ((flags & V_DBLCLK) ? 0x03 : 0x01); MB; ! i128mem.rbase_g[IDXL_I] = IBMRGB_sync; MB; ! i128mem.rbase_g[DATA_I] = 0x00; /* 0x10 +Hsync, 0x20 +Vsync */ MB; ! i128mem.rbase_g[IDXL_I] = IBMRGB_hsync_pos; MB; ! i128mem.rbase_g[DATA_I] = 0x01; /* Delay syncs by 1 pclock */ MB; ! i128mem.rbase_g[IDXL_I] = IBMRGB_pwr_mgmt; MB; ! i128mem.rbase_g[DATA_I] = 0x00; MB; ! i128mem.rbase_g[IDXL_I] = IBMRGB_dac_op; MB; tmp2 = (i128RamdacType == IBM528_DAC) ? 0x02 : 0x00; /* fast slew */ if (i128DACSyncOnGreen) tmp2 |= 0x08; ! i128mem.rbase_g[DATA_I] = tmp2; MB; ! i128mem.rbase_g[IDXL_I] = IBMRGB_pal_ctrl; MB; ! i128mem.rbase_g[DATA_I] = 0x00; MB; ! i128mem.rbase_g[IDXL_I] = IBMRGB_sysclk; MB; ! i128mem.rbase_g[DATA_I] = 0x01; MB; ! i128mem.rbase_g[IDXL_I] = IBMRGB_misc1; MB; ! tmp2 = i128mem.rbase_g[DATA_I] & 0xbc; ! if (i128MemoryType != I128_MEMORY_DRAM) tmp2 |= (i128RamdacType == IBM528_DAC) ? 3 : 1; ! i128mem.rbase_g[DATA_I] = tmp2; MB; ! i128mem.rbase_g[IDXL_I] = IBMRGB_misc2; MB; tmp2 = 0x03; if (i128DAC8Bit) tmp2 |= 0x04; ! if (!((i128MemoryType == I128_MEMORY_DRAM) && ! (i128InfoRec.bitsPerPixel > 16))) tmp2 |= 0x40; ! i128mem.rbase_g[DATA_I] = tmp2; MB; ! i128mem.rbase_g[IDXL_I] = IBMRGB_misc3; MB; ! i128mem.rbase_g[DATA_I] = 0x00; MB; ! i128mem.rbase_g[IDXL_I] = IBMRGB_misc4; MB; ! i128mem.rbase_g[DATA_I] = 0x00; MB; /* ?? There is no write to cursor control register */ if (i128RamdacType == IBM526_DAC) { /* program mclock to 52MHz */ ! i128mem.rbase_g[IDXL_I] = IBMRGB_sysclk_ref_div; MB; ! i128mem.rbase_g[DATA_I] = 0x08; MB; ! i128mem.rbase_g[IDXL_I] = IBMRGB_sysclk_vco_div; MB; ! i128mem.rbase_g[DATA_I] = 0x41; MB; /* should delay at least a millisec so we'll wait 50 */ usleep(50000); } *************** *** 850,887 **** switch (i128InfoRec.depth) { case 24: /* 32 bit */ ! i128mem.rbase_g_b[IDXL_I] = IBMRGB_pix_fmt; ! tmp2 = i128mem.rbase_g_b[DATA_I] & 0xf8; ! i128mem.rbase_g_b[DATA_I] = tmp2 | 0x06; ! i128mem.rbase_g_b[IDXL_I] = IBMRGB_32bpp; ! i128mem.rbase_g_b[DATA_I] = 0x03; break; case 16: ! i128mem.rbase_g_b[IDXL_I] = IBMRGB_pix_fmt; ! tmp2 = i128mem.rbase_g_b[DATA_I] & 0xf8; ! i128mem.rbase_g_b[DATA_I] = tmp2 | 0x04; ! i128mem.rbase_g_b[IDXL_I] = IBMRGB_16bpp; ! i128mem.rbase_g_b[DATA_I] = 0xC7; break; case 15: ! i128mem.rbase_g_b[IDXL_I] = IBMRGB_pix_fmt; ! tmp2 = i128mem.rbase_g_b[DATA_I] & 0xf8; ! i128mem.rbase_g_b[DATA_I] = tmp2 | 0x04; ! i128mem.rbase_g_b[IDXL_I] = IBMRGB_16bpp; ! i128mem.rbase_g_b[DATA_I] = 0xC5; break; default: /* 8 bit */ ! i128mem.rbase_g_b[IDXL_I] = IBMRGB_pix_fmt; ! tmp2 = i128mem.rbase_g_b[DATA_I] & 0xf8; ! i128mem.rbase_g_b[DATA_I] = tmp2 | 0x03; ! i128mem.rbase_g_b[IDXL_I] = IBMRGB_8bpp; ! i128mem.rbase_g_b[DATA_I] = 0x00; break; } ! i128mem.rbase_g_b[IDXCTL_I] = tmpc; ! i128mem.rbase_g_b[IDXH_I] = tmph; ! i128mem.rbase_g_b[IDXL_I] = tmpl; return(TRUE); } --- 911,948 ---- switch (i128InfoRec.depth) { case 24: /* 32 bit */ ! i128mem.rbase_g[IDXL_I] = IBMRGB_pix_fmt; MB; ! tmp2 = i128mem.rbase_g[DATA_I] & 0xf8; ! i128mem.rbase_g[DATA_I] = tmp2 | 0x06; MB; ! i128mem.rbase_g[IDXL_I] = IBMRGB_32bpp; MB; ! i128mem.rbase_g[DATA_I] = 0x03; MB; break; case 16: ! i128mem.rbase_g[IDXL_I] = IBMRGB_pix_fmt; MB; ! tmp2 = i128mem.rbase_g[DATA_I] & 0xf8; ! i128mem.rbase_g[DATA_I] = tmp2 | 0x04; MB; ! i128mem.rbase_g[IDXL_I] = IBMRGB_16bpp; MB; ! i128mem.rbase_g[DATA_I] = 0xC7; MB; break; case 15: ! i128mem.rbase_g[IDXL_I] = IBMRGB_pix_fmt; MB; ! tmp2 = i128mem.rbase_g[DATA_I] & 0xf8; ! i128mem.rbase_g[DATA_I] = tmp2 | 0x04; MB; ! i128mem.rbase_g[IDXL_I] = IBMRGB_16bpp; MB; ! i128mem.rbase_g[DATA_I] = 0xC5; MB; break; default: /* 8 bit */ ! i128mem.rbase_g[IDXL_I] = IBMRGB_pix_fmt; MB; ! tmp2 = i128mem.rbase_g[DATA_I] & 0xf8; ! i128mem.rbase_g[DATA_I] = tmp2 | 0x03; MB; ! i128mem.rbase_g[IDXL_I] = IBMRGB_8bpp; MB; ! i128mem.rbase_g[DATA_I] = 0x00; MB; break; } ! i128mem.rbase_g[IDXCTL_I] = tmpc; MB; ! i128mem.rbase_g[IDXH_I] = tmph; MB; ! i128mem.rbase_g[IDXL_I] = tmpl; MB; return(TRUE); } *************** *** 953,982 **** m = (unsigned char )best_m; p = (unsigned char )pi; ! tmp = i128mem.rbase_g_b[INDEX_TI]; /* * Reset the clock data index */ ! i128mem.rbase_g_b[INDEX_TI] = TI_PLL_CONTROL; ! i128mem.rbase_g_b[DATA_TI] = 0x00; /* * Now output the clock frequency */ ! i128mem.rbase_g_b[INDEX_TI] = TI_PIXEL_CLOCK_PLL_DATA; ! i128mem.rbase_g_b[DATA_TI] = n; ! i128mem.rbase_g_b[DATA_TI] = m; ! i128mem.rbase_g_b[DATA_TI] = p | TI_PLL_ENABLE; #ifdef NOTYET /* * Program the MCLK to 57MHz */ ! i128mem.rbase_g_b[INDEX_TI] = TI_MCLK_PLL_DATA; ! i128mem.rbase_g_b[DATA_TI] = 0x05; ! i128mem.rbase_g_b[DATA_TI] = 0x05; ! i128mem.rbase_g_b[DATA_TI] = 0x05; #endif switch (i128InfoRec.bitsPerPixel) { --- 1014,1043 ---- m = (unsigned char )best_m; p = (unsigned char )pi; ! tmp = i128mem.rbase_g[INDEX_TI] & 0xFF; /* * Reset the clock data index */ ! i128mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB; ! i128mem.rbase_g[DATA_TI] = 0x00; MB; /* * Now output the clock frequency */ ! i128mem.rbase_g[INDEX_TI] = TI_PIXEL_CLOCK_PLL_DATA; MB; ! i128mem.rbase_g[DATA_TI] = n; MB; ! i128mem.rbase_g[DATA_TI] = m; MB; ! i128mem.rbase_g[DATA_TI] = p | TI_PLL_ENABLE; MB; #ifdef NOTYET /* * Program the MCLK to 57MHz */ ! i128mem.rbase_g[INDEX_TI] = TI_MCLK_PLL_DATA; ! i128mem.rbase_g[DATA_TI] = 0x05; ! i128mem.rbase_g[DATA_TI] = 0x05; ! i128mem.rbase_g[DATA_TI] = 0x05; #endif switch (i128InfoRec.bitsPerPixel) { *************** *** 1019,1056 **** break; } ! i128mem.rbase_g_b[INDEX_TI] = TI_CURS_CONTROL; ! i128mem.rbase_g_b[DATA_TI] = TI_CURS_SPRITE_ENABLE | TI_CURS_X_WINDOW_MODE; ! i128mem.rbase_g_b[INDEX_TI] = TI_TRUE_COLOR_CONTROL; ! i128mem.rbase_g_b[DATA_TI] = 0x00; /* 3025 mode, vga, 8/4bit */ ! i128mem.rbase_g_b[INDEX_TI] = TI_VGA_SWITCH_CONTROL; ! i128mem.rbase_g_b[DATA_TI] = 0x00; ! i128mem.rbase_g_b[INDEX_TI] = TI_GENERAL_CONTROL; ! i128mem.rbase_g_b[DATA_TI] = 0x00; ! i128mem.rbase_g_b[INDEX_TI] = TI_MISC_CONTROL; ! i128mem.rbase_g_b[DATA_TI] = misc_ctrl; ! i128mem.rbase_g_b[INDEX_TI] = TI_AUXILIARY_CONTROL; ! i128mem.rbase_g_b[DATA_TI] = aux_ctrl; ! i128mem.rbase_g_b[INDEX_TI] = TI_COLOR_KEY_CONTROL; ! i128mem.rbase_g_b[DATA_TI] = col_key; ! i128mem.rbase_g_b[INDEX_TI] = TI_MUX_CONTROL_1; ! i128mem.rbase_g_b[DATA_TI] = mux1_ctrl; ! i128mem.rbase_g_b[INDEX_TI] = TI_MUX_CONTROL_2; ! i128mem.rbase_g_b[DATA_TI] = mux2_ctrl; ! i128mem.rbase_g_b[INDEX_TI] = TI_INPUT_CLOCK_SELECT; ! i128mem.rbase_g_b[DATA_TI] = TI_ICLK_PLL; ! i128mem.rbase_g_b[INDEX_TI] = TI_OUTPUT_CLOCK_SELECT; ! i128mem.rbase_g_b[DATA_TI] = oclk; usleep(150000); return(TRUE); --- 1080,1117 ---- break; } ! i128mem.rbase_g[INDEX_TI] = TI_CURS_CONTROL; MB; ! i128mem.rbase_g[DATA_TI] = TI_CURS_SPRITE_ENABLE | TI_CURS_X_WINDOW_MODE;MB; ! i128mem.rbase_g[INDEX_TI] = TI_TRUE_COLOR_CONTROL; MB; ! i128mem.rbase_g[DATA_TI] = 0x00; /* 3025 mode, vga, 8/4bit */ MB; ! i128mem.rbase_g[INDEX_TI] = TI_VGA_SWITCH_CONTROL; MB; ! i128mem.rbase_g[DATA_TI] = 0x00; MB; ! i128mem.rbase_g[INDEX_TI] = TI_GENERAL_CONTROL; MB; ! i128mem.rbase_g[DATA_TI] = 0x00; MB; ! i128mem.rbase_g[INDEX_TI] = TI_MISC_CONTROL; MB; ! i128mem.rbase_g[DATA_TI] = misc_ctrl; MB; ! i128mem.rbase_g[INDEX_TI] = TI_AUXILIARY_CONTROL; MB; ! i128mem.rbase_g[DATA_TI] = aux_ctrl; MB; ! i128mem.rbase_g[INDEX_TI] = TI_COLOR_KEY_CONTROL; MB; ! i128mem.rbase_g[DATA_TI] = col_key; MB; ! i128mem.rbase_g[INDEX_TI] = TI_MUX_CONTROL_1; MB; ! i128mem.rbase_g[DATA_TI] = mux1_ctrl; MB; ! i128mem.rbase_g[INDEX_TI] = TI_MUX_CONTROL_2; MB; ! i128mem.rbase_g[DATA_TI] = mux2_ctrl; MB; ! i128mem.rbase_g[INDEX_TI] = TI_INPUT_CLOCK_SELECT; MB; ! i128mem.rbase_g[DATA_TI] = TI_ICLK_PLL; MB; ! i128mem.rbase_g[INDEX_TI] = TI_OUTPUT_CLOCK_SELECT; MB; ! i128mem.rbase_g[DATA_TI] = oclk; MB; usleep(150000); return(TRUE); *** ./programs/Xserver/hw/xfree86/accel/i128/i128.h@@/PUBLIC-LATEST Sat Jul 19 09:35:48 1997 --- xc/programs/Xserver/hw/xfree86/accel/i128/i128.h Fri Mar 6 16:30:58 1998 *************** *** 1,4 **** ! /* $TOG: i128.h /main/5 1997/07/19 09:35:49 kaleb $ */ /* * Copyright 1994 by Robin Cutshaw * --- 1,4 ---- ! /* $TOG: i128.h /main/6 1998/03/06 16:32:36 kaleb $ */ /* * Copyright 1994 by Robin Cutshaw * *************** *** 22,28 **** * */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/accel/i128/i128.h,v 3.5 1996/12/23 06:35:36 dawes Exp $ */ #ifndef _I128_H_ #define _I128_H_ --- 22,28 ---- * */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/accel/i128/i128.h,v 3.5.2.1 1998/02/15 23:31:57 robin Exp $ */ #ifndef _I128_H_ #define _I128_H_ *************** *** 95,101 **** #endif ); ! extern short i128alu[]; extern pointer i128VideoMem; extern ScreenPtr i128savepScreen; --- 95,101 ---- #endif ); ! extern CARD32 i128alu[]; extern pointer i128VideoMem; extern ScreenPtr i128savepScreen; *** ./programs/Xserver/hw/xfree86/accel/i128/i128IBMCurs.c@@/PUBLIC-LATEST Sun Aug 10 12:58:03 1997 --- xc/programs/Xserver/hw/xfree86/accel/i128/i128IBMCurs.c Fri Mar 6 16:31:03 1998 *************** *** 1,4 **** ! /* $TOG: i128IBMCurs.c /main/5 1997/08/10 12:56:38 kaleb $ */ /* * Copyright 1996 by Robin Cutshaw * --- 1,4 ---- ! /* $TOG: i128IBMCurs.c /main/6 1998/03/06 16:32:40 kaleb $ */ /* * Copyright 1996 by Robin Cutshaw * *************** *** 22,28 **** * */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/accel/i128/i128IBMCurs.c,v 3.0.4.2 1997/06/11 12:08:51 dawes Exp $ */ #include "servermd.h" --- 22,28 ---- * */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/accel/i128/i128IBMCurs.c,v 3.0.4.3 1998/01/12 03:02:12 robin Exp $ */ #include "servermd.h" *************** *** 123,136 **** void i128IBMCursorOn() { ! unsigned char tmp; /* Enable cursor - X11 mode */ ! tmp = i128mem.rbase_g_b[IDXL_I]; ! i128mem.rbase_g_b[IDXL_I] = IBMRGB_curs; ! i128mem.rbase_g_b[DATA_I] = 0x27; ! i128mem.rbase_g_b[IDXL_I] = tmp; return; } --- 123,136 ---- void i128IBMCursorOn() { ! CARD32 tmp; /* Enable cursor - X11 mode */ ! tmp = i128mem.rbase_g[IDXL_I] & 0xFF; ! i128mem.rbase_g[IDXL_I] = IBMRGB_curs; MB; ! i128mem.rbase_g[DATA_I] = 0x27; MB; ! i128mem.rbase_g[IDXL_I] = tmp; MB; return; } *************** *** 138,151 **** void i128IBMCursorOff() { ! unsigned char tmp, tmp1; ! tmp = i128mem.rbase_g_b[IDXL_I]; ! i128mem.rbase_g_b[IDXL_I] = IBMRGB_curs; ! tmp1 = i128mem.rbase_g_b[DATA_I] & ~3; ! i128mem.rbase_g_b[DATA_I] = tmp1; ! i128mem.rbase_g_b[IDXL_I] = tmp; return; } --- 138,151 ---- void i128IBMCursorOff() { ! CARD32 tmp, tmp1; ! tmp = i128mem.rbase_g[IDXL_I] & 0xFF; ! i128mem.rbase_g[IDXL_I] = IBMRGB_curs; MB; ! tmp1 = i128mem.rbase_g[DATA_I] & 0xFC; ! i128mem.rbase_g[DATA_I] = tmp1; MB; ! i128mem.rbase_g[IDXL_I] = tmp; MB; return; } *************** *** 155,161 **** ScreenPtr pScr; int x, y; { ! unsigned char tmp; extern int i128AdjustCursorXPos, i128hotX, i128hotY; if (i128BlockCursor) --- 155,161 ---- ScreenPtr pScr; int x, y; { ! CARD32 tmp; extern int i128AdjustCursorXPos, i128hotX, i128hotY; if (i128BlockCursor) *************** *** 169,189 **** if (y < 0) return; ! tmp = i128mem.rbase_g_b[IDXL_I]; ! i128mem.rbase_g_b[IDXL_I] = IBMRGB_curs_hot_x; ! i128mem.rbase_g_b[DATA_I] = i128hotX & 0xFF; ! i128mem.rbase_g_b[IDXL_I] = IBMRGB_curs_hot_y; ! i128mem.rbase_g_b[DATA_I] = i128hotY & 0xFF; ! i128mem.rbase_g_b[IDXL_I] = IBMRGB_curs_xl; ! i128mem.rbase_g_b[DATA_I] = x & 0xFF; ! i128mem.rbase_g_b[IDXL_I] = IBMRGB_curs_xh; ! i128mem.rbase_g_b[DATA_I] = (x >> 8) & 0x0F; ! i128mem.rbase_g_b[IDXL_I] = IBMRGB_curs_yl; ! i128mem.rbase_g_b[DATA_I] = y & 0xFF; ! i128mem.rbase_g_b[IDXL_I] = IBMRGB_curs_yh; ! i128mem.rbase_g_b[DATA_I] = (y >> 8) & 0x0F; ! i128mem.rbase_g_b[IDXL_I] = tmp; return; } --- 169,189 ---- if (y < 0) return; ! tmp = i128mem.rbase_g[IDXL_I] & 0xFF; ! i128mem.rbase_g[IDXL_I] = IBMRGB_curs_hot_x; MB; ! i128mem.rbase_g[DATA_I] = i128hotX & 0xFF; MB; ! i128mem.rbase_g[IDXL_I] = IBMRGB_curs_hot_y; MB; ! i128mem.rbase_g[DATA_I] = i128hotY & 0xFF; MB; ! i128mem.rbase_g[IDXL_I] = IBMRGB_curs_xl; MB; ! i128mem.rbase_g[DATA_I] = x & 0xFF; MB; ! i128mem.rbase_g[IDXL_I] = IBMRGB_curs_xh; MB; ! i128mem.rbase_g[DATA_I] = (x >> 8) & 0x0F; MB; ! i128mem.rbase_g[IDXL_I] = IBMRGB_curs_yl; MB; ! i128mem.rbase_g[DATA_I] = y & 0xFF; MB; ! i128mem.rbase_g[IDXL_I] = IBMRGB_curs_yh; MB; ! i128mem.rbase_g[DATA_I] = (y >> 8) & 0x0F; MB; ! i128mem.rbase_g[IDXL_I] = tmp; MB; return; } *************** *** 193,199 **** CursorPtr pCurs; Bool displayed; { ! unsigned char tmp; if (!xf86VTSema) { miRecolorCursor(pScr, pCurs, displayed); --- 193,199 ---- CursorPtr pCurs; Bool displayed; { ! CARD32 tmp; if (!xf86VTSema) { miRecolorCursor(pScr, pCurs, displayed); *************** *** 200,224 **** return; } ! tmp = i128mem.rbase_g_b[IDXL_I]; /* Background color */ ! i128mem.rbase_g_b[IDXL_I] = IBMRGB_curs_col1_r; ! i128mem.rbase_g_b[DATA_I] = (pCurs->backRed >> 8) & 0xFF; ! i128mem.rbase_g_b[IDXL_I] = IBMRGB_curs_col1_g; ! i128mem.rbase_g_b[DATA_I] = (pCurs->backGreen >> 8) & 0xFF; ! i128mem.rbase_g_b[IDXL_I] = IBMRGB_curs_col1_b; ! i128mem.rbase_g_b[DATA_I] = (pCurs->backBlue >> 8) & 0xFF; /* Foreground color */ ! i128mem.rbase_g_b[IDXL_I] = IBMRGB_curs_col2_r; ! i128mem.rbase_g_b[DATA_I] = (pCurs->foreRed >> 8) & 0xFF; ! i128mem.rbase_g_b[IDXL_I] = IBMRGB_curs_col2_g; ! i128mem.rbase_g_b[DATA_I] = (pCurs->foreGreen >> 8) & 0xFF; ! i128mem.rbase_g_b[IDXL_I] = IBMRGB_curs_col2_b; ! i128mem.rbase_g_b[DATA_I] = (pCurs->foreBlue >> 8) & 0xFF; ! i128mem.rbase_g_b[IDXL_I] = tmp; return; } --- 200,224 ---- return; } ! tmp = i128mem.rbase_g[IDXL_I] & 0xFF; /* Background color */ ! i128mem.rbase_g[IDXL_I] = IBMRGB_curs_col1_r; MB; ! i128mem.rbase_g[DATA_I] = (pCurs->backRed >> 8) & 0xFF; MB; ! i128mem.rbase_g[IDXL_I] = IBMRGB_curs_col1_g; MB; ! i128mem.rbase_g[DATA_I] = (pCurs->backGreen >> 8) & 0xFF; MB; ! i128mem.rbase_g[IDXL_I] = IBMRGB_curs_col1_b; MB; ! i128mem.rbase_g[DATA_I] = (pCurs->backBlue >> 8) & 0xFF; MB; /* Foreground color */ ! i128mem.rbase_g[IDXL_I] = IBMRGB_curs_col2_r; MB; ! i128mem.rbase_g[DATA_I] = (pCurs->foreRed >> 8) & 0xFF; MB; ! i128mem.rbase_g[IDXL_I] = IBMRGB_curs_col2_g; MB; ! i128mem.rbase_g[DATA_I] = (pCurs->foreGreen >> 8) & 0xFF; MB; ! i128mem.rbase_g[IDXL_I] = IBMRGB_curs_col2_b; MB; ! i128mem.rbase_g[DATA_I] = (pCurs->foreBlue >> 8) & 0xFF; MB; ! i128mem.rbase_g[IDXL_I] = tmp; MB; return; } *************** *** 232,238 **** extern int i128hotX, i128hotY; int index = pScr->myNum; register int i; ! unsigned char *ram, *p, tmph, tmpl, tmpc, tmpcurs; extern int i128InitCursorFlag; if (!xf86VTSema) --- 232,239 ---- extern int i128hotX, i128hotY; int index = pScr->myNum; register int i; ! unsigned char *ram, *p; ! CARD32 tmph, tmpl, tmpc, tmpcurs; extern int i128InitCursorFlag; if (!xf86VTSema) *************** *** 241,253 **** if (!pCurs) return; ! tmpc = i128mem.rbase_g_b[IDXCTL_I]; ! tmph = i128mem.rbase_g_b[IDXH_I]; ! tmpl = i128mem.rbase_g_b[IDXL_I]; /* turn the cursor off */ ! i128mem.rbase_g_b[IDXL_I] = IBMRGB_curs; ! if ((tmpcurs = i128mem.rbase_g_b[DATA_I]) & 0x03) i128IBMCursorOff(); /* load colormap */ --- 242,254 ---- if (!pCurs) return; ! tmpc = i128mem.rbase_g[IDXCTL_I] & 0xFF; ! tmph = i128mem.rbase_g[IDXH_I] & 0xFF; ! tmpl = i128mem.rbase_g[IDXL_I] & 0xFF; /* turn the cursor off */ ! i128mem.rbase_g[IDXL_I] = IBMRGB_curs; MB; ! if ((tmpcurs = i128mem.rbase_g[DATA_I]) & 0x03) i128IBMCursorOff(); /* load colormap */ *************** *** 257,281 **** i128BlockCursor = TRUE; ! i128mem.rbase_g_b[IDXCTL_I] = 0; ! i128mem.rbase_g_b[IDXL_I] = IBMRGB_curs_hot_x; ! i128mem.rbase_g_b[DATA_I] = 0x00; ! i128mem.rbase_g_b[IDXL_I] = IBMRGB_curs_hot_y; ! i128mem.rbase_g_b[DATA_I] = 0x00; ! i128mem.rbase_g_b[IDXL_I] = IBMRGB_curs_xl; ! i128mem.rbase_g_b[DATA_I] = 0xFF; ! i128mem.rbase_g_b[IDXL_I] = IBMRGB_curs_xh; ! i128mem.rbase_g_b[DATA_I] = 0x7F; ! i128mem.rbase_g_b[IDXL_I] = IBMRGB_curs_yl; ! i128mem.rbase_g_b[DATA_I] = 0xFF; ! i128mem.rbase_g_b[IDXL_I] = IBMRGB_curs_yh; ! i128mem.rbase_g_b[DATA_I] = 0x7F; ! i128mem.rbase_g_b[IDXH_I] = (IBMRGB_curs_array >> 8) & 0xFF; ! i128mem.rbase_g_b[IDXL_I] = IBMRGB_curs_array & 0xFF; ! i128mem.rbase_g_b[IDXCTL_I] = 1; /* enable auto-inc */ /* * Output the cursor data. The realize function has put the planes into --- 258,282 ---- i128BlockCursor = TRUE; ! i128mem.rbase_g[IDXCTL_I] = 0; MB; ! i128mem.rbase_g[IDXL_I] = IBMRGB_curs_hot_x; MB; ! i128mem.rbase_g[DATA_I] = 0x00; MB; ! i128mem.rbase_g[IDXL_I] = IBMRGB_curs_hot_y; MB; ! i128mem.rbase_g[DATA_I] = 0x00; MB; ! i128mem.rbase_g[IDXL_I] = IBMRGB_curs_xl; MB; ! i128mem.rbase_g[DATA_I] = 0xFF; MB; ! i128mem.rbase_g[IDXL_I] = IBMRGB_curs_xh; MB; ! i128mem.rbase_g[DATA_I] = 0x7F; MB; ! i128mem.rbase_g[IDXL_I] = IBMRGB_curs_yl; MB; ! i128mem.rbase_g[DATA_I] = 0xFF; MB; ! i128mem.rbase_g[IDXL_I] = IBMRGB_curs_yh; MB; ! i128mem.rbase_g[DATA_I] = 0x7F; MB; ! i128mem.rbase_g[IDXH_I] = (IBMRGB_curs_array >> 8) & 0xFF; MB; ! i128mem.rbase_g[IDXL_I] = IBMRGB_curs_array & 0xFF; MB; ! i128mem.rbase_g[IDXCTL_I] = 1; /* enable auto-inc */ MB; /* * Output the cursor data. The realize function has put the planes into *************** *** 282,289 **** * their correct order, so we can just blast this out. */ p = ram; ! for (i = 0; i < 1024; i++,p++) ! i128mem.rbase_g_b[DATA_I] = *p; if (i128hotX >= MAX_CURS_WIDTH) i128hotX = MAX_CURS_WIDTH - 1; --- 283,291 ---- * their correct order, so we can just blast this out. */ p = ram; ! for (i = 0; i < 1024; i++,p++) { ! i128mem.rbase_g[DATA_I] = (CARD32 )*p; MB; ! } if (i128hotX >= MAX_CURS_WIDTH) i128hotX = MAX_CURS_WIDTH - 1; *************** *** 294,302 **** else if (i128hotY < 0) i128hotY = 0; ! i128mem.rbase_g_b[IDXCTL_I] = tmpc; ! i128mem.rbase_g_b[IDXH_I] = tmph; ! i128mem.rbase_g_b[IDXL_I] = tmpl; i128BlockCursor = FALSE; --- 296,304 ---- else if (i128hotY < 0) i128hotY = 0; ! i128mem.rbase_g[IDXCTL_I] = tmpc; MB; ! i128mem.rbase_g[IDXH_I] = tmph; MB; ! i128mem.rbase_g[IDXL_I] = tmpl; MB; i128BlockCursor = FALSE; *** ./programs/Xserver/hw/xfree86/accel/i128/i128TiCurs.c@@/PUBLIC-LATEST Sat Jul 19 09:36:08 1997 --- xc/programs/Xserver/hw/xfree86/accel/i128/i128TiCurs.c Fri Mar 6 16:31:07 1998 *************** *** 1,4 **** ! /* $TOG: i128TiCurs.c /main/4 1997/07/19 09:36:09 kaleb $ */ /* * Copyright 1995 by Robin Cutshaw * --- 1,4 ---- ! /* $TOG: i128TiCurs.c /main/5 1998/03/06 16:32:45 kaleb $ */ /* * Copyright 1995 by Robin Cutshaw * *************** *** 22,28 **** * */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/accel/i128/i128TiCurs.c,v 3.4 1996/12/23 06:35:39 dawes Exp $ */ #include "servermd.h" --- 22,28 ---- * */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/accel/i128/i128TiCurs.c,v 3.4.2.1 1998/01/12 03:02:10 robin Exp $ */ #include "servermd.h" *************** *** 123,138 **** void i128TiCursorOn() { ! unsigned char tmp, tmp1; /* Enable cursor - sprite enable, X11 mode */ ! tmp = i128mem.rbase_g_b[INDEX_TI]; ! i128mem.rbase_g_b[INDEX_TI] = TI_CURS_CONTROL; ! tmp1 = i128mem.rbase_g_b[DATA_TI] & ~TI_CURS_CTRL_MASK; ! i128mem.rbase_g_b[DATA_TI] = tmp1 | (TI_CURS_SPRITE_ENABLE | TI_CURS_X_WINDOW_MODE); ! i128mem.rbase_g_b[INDEX_TI] = tmp; return; } --- 123,139 ---- void i128TiCursorOn() { ! CARD32 tmp, tmp1; /* Enable cursor - sprite enable, X11 mode */ ! tmp = i128mem.rbase_g[INDEX_TI] & 0xFF; ! i128mem.rbase_g[INDEX_TI] = TI_CURS_CONTROL; MB; ! tmp1 = (i128mem.rbase_g[DATA_TI] & ~TI_CURS_CTRL_MASK) & 0xFF; ! i128mem.rbase_g[DATA_TI] = tmp1 | (TI_CURS_SPRITE_ENABLE | TI_CURS_X_WINDOW_MODE); + MB; ! i128mem.rbase_g[INDEX_TI] = tmp; MB; return; } *************** *** 140,154 **** void i128TiCursorOff() { ! unsigned char tmp, tmp1; /* Enable cursor - sprite enable, X11 mode */ ! tmp = i128mem.rbase_g_b[INDEX_TI]; ! i128mem.rbase_g_b[INDEX_TI] = TI_CURS_CONTROL; ! tmp1 = i128mem.rbase_g_b[DATA_TI] & ~TI_CURS_CTRL_MASK; ! i128mem.rbase_g_b[DATA_TI] = tmp1; ! i128mem.rbase_g_b[INDEX_TI] = tmp; return; } --- 141,155 ---- void i128TiCursorOff() { ! CARD32 tmp, tmp1; /* Enable cursor - sprite enable, X11 mode */ ! tmp = i128mem.rbase_g[INDEX_TI] & 0xFF; ! i128mem.rbase_g[INDEX_TI] = TI_CURS_CONTROL; MB; ! tmp1 = (i128mem.rbase_g[DATA_TI] & ~TI_CURS_CTRL_MASK) & 0xFF; ! i128mem.rbase_g[DATA_TI] = tmp1; MB; ! i128mem.rbase_g[INDEX_TI] = tmp; MB; return; } *************** *** 158,164 **** ScreenPtr pScr; int x, y; { ! unsigned char tmp; extern int i128AdjustCursorXPos; if (i128BlockCursor) --- 159,165 ---- ScreenPtr pScr; int x, y; { ! CARD32 tmp; extern int i128AdjustCursorXPos; if (i128BlockCursor) *************** *** 174,190 **** /* Output position - "only" 12 bits of location documented */ ! tmp = i128mem.rbase_g_b[INDEX_TI]; ! i128mem.rbase_g_b[INDEX_TI] = TI_CURS_X_LOW; ! i128mem.rbase_g_b[DATA_TI] = x & 0xFF; ! i128mem.rbase_g_b[INDEX_TI] = TI_CURS_X_HIGH; ! i128mem.rbase_g_b[DATA_TI] = (x >> 8) & 0x0F; ! i128mem.rbase_g_b[INDEX_TI] = TI_CURS_Y_LOW; ! i128mem.rbase_g_b[DATA_TI] = y & 0xFF; ! i128mem.rbase_g_b[INDEX_TI] = TI_CURS_Y_HIGH; ! i128mem.rbase_g_b[DATA_TI] = (y >> 8) & 0x0F; ! i128mem.rbase_g_b[INDEX_TI] = tmp; return; } --- 175,191 ---- /* Output position - "only" 12 bits of location documented */ ! tmp = i128mem.rbase_g[INDEX_TI] & 0xFF; ! i128mem.rbase_g[INDEX_TI] = TI_CURS_X_LOW; MB; ! i128mem.rbase_g[DATA_TI] = x & 0xFF; MB; ! i128mem.rbase_g[INDEX_TI] = TI_CURS_X_HIGH; MB; ! i128mem.rbase_g[DATA_TI] = (x >> 8) & 0x0F; MB; ! i128mem.rbase_g[INDEX_TI] = TI_CURS_Y_LOW; MB; ! i128mem.rbase_g[DATA_TI] = y & 0xFF; MB; ! i128mem.rbase_g[INDEX_TI] = TI_CURS_Y_HIGH; MB; ! i128mem.rbase_g[DATA_TI] = (y >> 8) & 0x0F; MB; ! i128mem.rbase_g[INDEX_TI] = tmp; MB; return; } *************** *** 194,200 **** CursorPtr pCurs; Bool displayed; { ! unsigned char tmp; if (!xf86VTSema) { miRecolorCursor(pScr, pCurs, displayed); --- 195,201 ---- CursorPtr pCurs; Bool displayed; { ! CARD32 tmp; if (!xf86VTSema) { miRecolorCursor(pScr, pCurs, displayed); *************** *** 204,228 **** if (!displayed) return; ! tmp = i128mem.rbase_g_b[INDEX_TI]; /* The TI 3020 cursor is always 8 bits so shift 8, not 10 */ /* Background color */ ! i128mem.rbase_g_b[INDEX_TI] = TI_CURSOR_COLOR_0_RED; ! i128mem.rbase_g_b[DATA_TI] = (pCurs->backRed >> 8) & 0xFF; ! i128mem.rbase_g_b[INDEX_TI] = TI_CURSOR_COLOR_0_GREEN; ! i128mem.rbase_g_b[DATA_TI] = (pCurs->backGreen >> 8) & 0xFF; ! i128mem.rbase_g_b[INDEX_TI] = TI_CURSOR_COLOR_0_BLUE; ! i128mem.rbase_g_b[DATA_TI] = (pCurs->backBlue >> 8) & 0xFF; /* Foreground color */ ! i128mem.rbase_g_b[INDEX_TI] = TI_CURSOR_COLOR_1_RED; ! i128mem.rbase_g_b[DATA_TI] = (pCurs->foreRed >> 8) & 0xFF; ! i128mem.rbase_g_b[INDEX_TI] = TI_CURSOR_COLOR_1_GREEN; ! i128mem.rbase_g_b[DATA_TI] = (pCurs->foreGreen >> 8) & 0xFF; ! i128mem.rbase_g_b[INDEX_TI] = TI_CURSOR_COLOR_1_BLUE; ! i128mem.rbase_g_b[DATA_TI] = (pCurs->foreBlue >> 8) & 0xFF; return; } --- 205,229 ---- if (!displayed) return; ! tmp = i128mem.rbase_g[INDEX_TI] & 0xFF; /* The TI 3020 cursor is always 8 bits so shift 8, not 10 */ /* Background color */ ! i128mem.rbase_g[INDEX_TI] = TI_CURSOR_COLOR_0_RED; MB; ! i128mem.rbase_g[DATA_TI] = (pCurs->backRed >> 8) & 0xFF; MB; ! i128mem.rbase_g[INDEX_TI] = TI_CURSOR_COLOR_0_GREEN; MB; ! i128mem.rbase_g[DATA_TI] = (pCurs->backGreen >> 8) & 0xFF; MB; ! i128mem.rbase_g[INDEX_TI] = TI_CURSOR_COLOR_0_BLUE; MB; ! i128mem.rbase_g[DATA_TI] = (pCurs->backBlue >> 8) & 0xFF; MB; /* Foreground color */ ! i128mem.rbase_g[INDEX_TI] = TI_CURSOR_COLOR_1_RED; MB; ! i128mem.rbase_g[DATA_TI] = (pCurs->foreRed >> 8) & 0xFF; MB; ! i128mem.rbase_g[INDEX_TI] = TI_CURSOR_COLOR_1_GREEN; MB; ! i128mem.rbase_g[DATA_TI] = (pCurs->foreGreen >> 8) & 0xFF; MB; ! i128mem.rbase_g[INDEX_TI] = TI_CURSOR_COLOR_1_BLUE; MB; ! i128mem.rbase_g[DATA_TI] = (pCurs->foreBlue >> 8) & 0xFF; MB; return; } *************** *** 236,242 **** extern int i128hotX, i128hotY; int index = pScr->myNum; register int i; ! unsigned char *ram, *p, tmp, tmp1, tmpcurs; extern int i128InitCursorFlag; if (!xf86VTSema) --- 237,244 ---- extern int i128hotX, i128hotY; int index = pScr->myNum; register int i; ! unsigned char *ram, *p; ! CARD32 tmp, tmp1, tmpcurs; extern int i128InitCursorFlag; if (!xf86VTSema) *************** *** 245,255 **** if (!pCurs) return; ! tmp = i128mem.rbase_g_b[INDEX_TI]; /* turn the cursor off */ ! i128mem.rbase_g_b[INDEX_TI] = TI_CURS_CONTROL; ! if ((tmpcurs = i128mem.rbase_g_b[DATA_TI]) & TI_CURS_SPRITE_ENABLE) i128TiCursorOff(); /* load colormap */ --- 247,257 ---- if (!pCurs) return; ! tmp = i128mem.rbase_g[INDEX_TI] & 0xFF; /* turn the cursor off */ ! i128mem.rbase_g[INDEX_TI] = TI_CURS_CONTROL; MB; ! if ((tmpcurs = i128mem.rbase_g[DATA_TI]) & TI_CURS_SPRITE_ENABLE) i128TiCursorOff(); /* load colormap */ *************** *** 259,269 **** i128BlockCursor = TRUE; ! i128mem.rbase_g_b[INDEX_TI] = TI_CURS_RAM_ADDR_LOW; ! i128mem.rbase_g_b[DATA_TI] = 0x00; ! i128mem.rbase_g_b[INDEX_TI] = TI_CURS_RAM_ADDR_HIGH; ! i128mem.rbase_g_b[DATA_TI] = 0x00; ! i128mem.rbase_g_b[INDEX_TI] = TI_CURS_RAM_DATA; /* * Output the cursor data. The realize function has put the planes into --- 261,271 ---- i128BlockCursor = TRUE; ! i128mem.rbase_g[INDEX_TI] = TI_CURS_RAM_ADDR_LOW; MB; ! i128mem.rbase_g[DATA_TI] = 0x00; MB; ! i128mem.rbase_g[INDEX_TI] = TI_CURS_RAM_ADDR_HIGH; MB; ! i128mem.rbase_g[DATA_TI] = 0x00; MB; ! i128mem.rbase_g[INDEX_TI] = TI_CURS_RAM_DATA; MB; /* * Output the cursor data. The realize function has put the planes into *************** *** 270,277 **** * their correct order, so we can just blast this out. */ p = ram; ! for (i = 0; i < 1024; i++,p++) ! i128mem.rbase_g_b[DATA_TI] = *p; if (i128hotX >= MAX_CURS_WIDTH) i128hotX = MAX_CURS_WIDTH - 1; --- 272,280 ---- * their correct order, so we can just blast this out. */ p = ram; ! for (i = 0; i < 1024; i++,p++) { ! i128mem.rbase_g[DATA_TI] = (CARD32 )*p; MB; ! } if (i128hotX >= MAX_CURS_WIDTH) i128hotX = MAX_CURS_WIDTH - 1; *************** *** 282,292 **** else if (i128hotY < 0) i128hotY = 0; ! i128mem.rbase_g_b[INDEX_TI] = TI_SPRITE_ORIGIN_X; ! i128mem.rbase_g_b[DATA_TI] = i128hotX; ! i128mem.rbase_g_b[INDEX_TI] = TI_SPRITE_ORIGIN_Y; ! i128mem.rbase_g_b[DATA_TI] = i128hotY; ! i128mem.rbase_g_b[INDEX_TI] = tmp; i128BlockCursor = FALSE; --- 285,295 ---- else if (i128hotY < 0) i128hotY = 0; ! i128mem.rbase_g[INDEX_TI] = TI_SPRITE_ORIGIN_X; MB; ! i128mem.rbase_g[DATA_TI] = i128hotX; MB; ! i128mem.rbase_g[INDEX_TI] = TI_SPRITE_ORIGIN_Y; MB; ! i128mem.rbase_g[DATA_TI] = i128hotY; MB; ! i128mem.rbase_g[INDEX_TI] = tmp; MB; i128BlockCursor = FALSE; *** ./programs/Xserver/hw/xfree86/accel/i128/i128cmap.c@@/PUBLIC-LATEST Sun Oct 19 15:00:58 1997 --- xc/programs/Xserver/hw/xfree86/accel/i128/i128cmap.c Fri Mar 6 16:31:16 1998 *************** *** 1,4 **** ! /* $TOG: i128cmap.c /main/4 1997/10/19 15:03:02 kaleb $ */ /* * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany. * --- 1,4 ---- ! /* $TOG: i128cmap.c /main/5 1998/03/06 16:32:54 kaleb $ */ /* * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany. * *************** *** 24,30 **** * */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/accel/i128/i128cmap.c,v 3.2 1996/12/23 06:35:40 dawes Exp $ */ /* * Modified by Amancio Hasty and Jon Tombs --- 24,30 ---- * */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/accel/i128/i128cmap.c,v 3.2.2.1 1998/01/12 03:02:10 robin Exp $ */ /* * Modified by Amancio Hasty and Jon Tombs *************** *** 79,90 **** if (xf86VTSema) { BLOCK_CURSOR; ! i128mem.rbase_g_b[WR_ADR] = 0x00; for (i=0; i < 256; i++) { ! i128mem.rbase_g_b[PAL_DAT] = currenti128dac[i].r; ! i128mem.rbase_g_b[PAL_DAT] = currenti128dac[i].g; ! i128mem.rbase_g_b[PAL_DAT] = currenti128dac[i].b; } UNBLOCK_CURSOR; } --- 79,90 ---- if (xf86VTSema) { BLOCK_CURSOR; ! i128mem.rbase_g[WR_ADR] = 0x00; MB; for (i=0; i < 256; i++) { ! i128mem.rbase_g[PAL_DAT] = currenti128dac[i].r; MB; ! i128mem.rbase_g[PAL_DAT] = currenti128dac[i].g; MB; ! i128mem.rbase_g[PAL_DAT] = currenti128dac[i].b; MB; } UNBLOCK_CURSOR; } *************** *** 137,146 **** xf86bGammaMap[pdefs[i].blue >> 8] >> 2; } if (xf86VTSema) { ! i128mem.rbase_g_b[WR_ADR] = pdefs[i].pixel; ! i128mem.rbase_g_b[PAL_DAT] = r; ! i128mem.rbase_g_b[PAL_DAT] = g; ! i128mem.rbase_g_b[PAL_DAT] = b; } } UNBLOCK_CURSOR; --- 137,146 ---- xf86bGammaMap[pdefs[i].blue >> 8] >> 2; } if (xf86VTSema) { ! i128mem.rbase_g[WR_ADR] = pdefs[i].pixel; MB; ! i128mem.rbase_g[PAL_DAT] = r; MB; ! i128mem.rbase_g[PAL_DAT] = g; MB; ! i128mem.rbase_g[PAL_DAT] = b; MB; } } UNBLOCK_CURSOR; *************** *** 262,276 **** QueryColors(InstalledMaps[pScreen->myNum], 1, &pix, &rgb); BLOCK_CURSOR; ! i128mem.rbase_g_b[WR_ADR] = 0x00; if (i128DAC8Bit) { ! i128mem.rbase_g_b[PAL_DAT] = xf86rGammaMap[rgb.red >> 8]; ! i128mem.rbase_g_b[PAL_DAT] = xf86gGammaMap[rgb.green >> 8]; ! i128mem.rbase_g_b[PAL_DAT] = xf86bGammaMap[rgb.blue >> 8]; } else { ! i128mem.rbase_g_b[PAL_DAT] = xf86rGammaMap[rgb.red >> 8] >> 2; ! i128mem.rbase_g_b[PAL_DAT] = xf86gGammaMap[rgb.green >> 8] >> 2; ! i128mem.rbase_g_b[PAL_DAT] = xf86bGammaMap[rgb.blue >> 8] >> 2; } UNBLOCK_CURSOR; } --- 262,276 ---- QueryColors(InstalledMaps[pScreen->myNum], 1, &pix, &rgb); BLOCK_CURSOR; ! i128mem.rbase_g[WR_ADR] = 0x00; MB; if (i128DAC8Bit) { ! i128mem.rbase_g[PAL_DAT] = xf86rGammaMap[rgb.red >> 8]; MB; ! i128mem.rbase_g[PAL_DAT] = xf86gGammaMap[rgb.green >> 8]; MB; ! i128mem.rbase_g[PAL_DAT] = xf86bGammaMap[rgb.blue >> 8]; MB; } else { ! i128mem.rbase_g[PAL_DAT] = xf86rGammaMap[rgb.red >> 8] >> 2; MB; ! i128mem.rbase_g[PAL_DAT] = xf86gGammaMap[rgb.green >> 8] >> 2; MB; ! i128mem.rbase_g[PAL_DAT] = xf86bGammaMap[rgb.blue >> 8] >> 2; MB; } UNBLOCK_CURSOR; } *** ./programs/Xserver/hw/xfree86/accel/i128/i128gc.c@@/PUBLIC-LATEST Tue Feb 10 17:23:19 1998 --- xc/programs/Xserver/hw/xfree86/accel/i128/i128gc.c Fri Mar 6 16:31:20 1998 *************** *** 1,4 **** ! /* $TOG: i128gc.c /main/4 1998/02/10 17:23:37 kaleb $ */ /*********************************************************** Copyright 1987, 1998 The Open Group --- 1,4 ---- ! /* $TOG: i128gc.c /main/5 1998/03/06 16:32:58 kaleb $ */ /*********************************************************** Copyright 1987, 1998 The Open Group *************** *** 47,53 **** ******************************************************************/ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/accel/i128/i128gc.c,v 3.2 1996/12/23 06:35:41 dawes Exp $ */ #include "X.h" --- 47,53 ---- ******************************************************************/ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/accel/i128/i128gc.c,v 3.2.2.1 1998/02/16 01:34:33 robin Exp $ */ #include "X.h" *************** *** 242,265 **** void i128InitGC() { - /* Initialize ALU->MINTERM mappings for raster operations */ - i128alu[GXclear] = 0; /* 0 */ - i128alu[GXand] = IGM_S_MASK & IGM_D_MASK; /* src AND dst */ - i128alu[GXandReverse] = IGM_S_MASK & ~IGM_D_MASK; /* src AND NOT dst */ - i128alu[GXcopy] = IGM_S_MASK; /* src */ - i128alu[GXandInverted] = ~IGM_S_MASK & IGM_D_MASK; /* NOT src AND dst */ - i128alu[GXnoop] = IGM_D_MASK; /* dst */ - i128alu[GXxor] = IGM_S_MASK ^ IGM_D_MASK; /* src XOR dst */ - i128alu[GXor] = IGM_S_MASK | IGM_D_MASK; /* src OR dst */ - i128alu[GXnor] = ~IGM_S_MASK & ~IGM_D_MASK; /* NOT src AND NOT dst */ - i128alu[GXequiv] = ~IGM_S_MASK ^ IGM_D_MASK; /* NOT src XOR dst */ - i128alu[GXinvert] = ~IGM_D_MASK; /* NOT dst */ - i128alu[GXorReverse] = IGM_S_MASK | ~IGM_D_MASK; /* src OR NOT dst */ - i128alu[GXcopyInverted] = ~IGM_S_MASK; /* NOT src */ - i128alu[GXorInverted] = ~IGM_S_MASK | IGM_D_MASK; /* NOT src OR dst */ - i128alu[GXnand] = ~IGM_S_MASK | ~IGM_D_MASK; /* NOT src OR NOT dst */ - i128alu[GXset] = IGM_S_MASK | ~IGM_S_MASK; /* 1 */ - i128BytesPerPixel = i128InfoRec.bitsPerPixel / 8; } --- 242,247 ---- *** ./programs/Xserver/hw/xfree86/accel/i128/i128init.c@@/PUBLIC-LATEST Sun Aug 10 12:58:13 1997 --- xc/programs/Xserver/hw/xfree86/accel/i128/i128init.c Fri Mar 6 16:31:25 1998 *************** *** 1,4 **** ! /* $XFree86: xc/programs/Xserver/hw/xfree86/accel/i128/i128init.c,v 3.6.2.5 1997/07/26 06:30:46 dawes Exp $ */ /* * Copyright 1995 by Robin Cutshaw * --- 1,4 ---- ! /* $XFree86: xc/programs/Xserver/hw/xfree86/accel/i128/i128init.c,v 3.6.2.7 1998/02/10 22:35:49 robin Exp $ */ /* * Copyright 1995 by Robin Cutshaw * *************** *** 21,27 **** * PERFORMANCE OF THIS SOFTWARE. * */ ! /* $TOG: i128init.c /main/7 1997/08/10 12:56:48 kaleb $ */ #include "i128.h" --- 21,27 ---- * PERFORMANCE OF THIS SOFTWARE. * */ ! /* $TOG: i128init.c /main/8 1998/03/06 16:33:02 kaleb $ */ #include "i128.h" *************** *** 37,43 **** static int i128LUTSaved = 0; static Bool LUTInited = FALSE; static LUTENTRY oldlut[256]; ! #define VGA_SAVE_COUNT 64*1024 static unsigned char vgamem[VGA_SAVE_COUNT]; /* vga text memory */ int i128InitCursorFlag = TRUE; int i128HDisplay; --- 37,43 ---- static int i128LUTSaved = 0; static Bool LUTInited = FALSE; static LUTENTRY oldlut[256]; ! #define VGA_SAVE_COUNT 512*1024 static unsigned char vgamem[VGA_SAVE_COUNT]; /* vga text memory */ int i128InitCursorFlag = TRUE; int i128HDisplay; *************** *** 47,53 **** extern int i128Weight; extern int i128DisplayWidth; extern int i128DisplayOffset; ! extern int i128MemoryTypeDram; extern int i128RamdacType; --- 47,54 ---- extern int i128Weight; extern int i128DisplayWidth; extern int i128DisplayOffset; ! extern int i128DeviceType; ! extern int i128MemoryType; extern int i128RamdacType; *************** *** 61,71 **** #endif { /* iobase is filled in during the device probe (as well as config 1&2)*/ ! if ((i128io.id&0x7) > 1) { ! unsigned PCI_DevIOPorts[1]; - PCI_DevIOPorts[0] = iR.iobase + 0x30; - xf86AddIOPorts(i128InfoRec.scrnIndex, 1, PCI_DevIOPorts); xf86EnableIOPorts(i128InfoRec.scrnIndex); iR.vga_ctl = inl(iR.iobase + 0x30); --- 62,69 ---- #endif { /* iobase is filled in during the device probe (as well as config 1&2)*/ ! if ((i128io.id&0x7) > 0) { xf86EnableIOPorts(i128InfoRec.scrnIndex); iR.vga_ctl = inl(iR.iobase + 0x30); *************** *** 73,92 **** } if (i128RamdacType == TI3025_DAC) { ! iR.i128_base_g[INDEX_TI/4] = ! i128mem.rbase_g[INDEX_TI/4]; /* 0x0018 */ ! iR.i128_base_g[DATA_TI/4] = ! i128mem.rbase_g[DATA_TI/4]; /* 0x001C */ } else if ((i128RamdacType == IBM526_DAC) || (i128RamdacType == IBM528_DAC)) { ! iR.i128_base_g[IDXL_I/4] = ! i128mem.rbase_g[IDXL_I/4]; /* 0x0010 */ ! iR.i128_base_g[IDXH_I/4] = ! i128mem.rbase_g[IDXH_I/4]; /* 0x0014 */ ! iR.i128_base_g[DATA_I/4] = ! i128mem.rbase_g[DATA_I/4]; /* 0x0018 */ ! iR.i128_base_g[IDXCTL_I/4] = ! i128mem.rbase_g[IDXCTL_I/4]; /* 0x001C */ } iR.i128_base_g[INT_VCNT] = i128mem.rbase_g[INT_VCNT]; /* 0x0020 */ --- 71,90 ---- } if (i128RamdacType == TI3025_DAC) { ! iR.i128_base_g[INDEX_TI] = ! i128mem.rbase_g[INDEX_TI]; /* 0x0018 */ ! iR.i128_base_g[DATA_TI] = ! i128mem.rbase_g[DATA_TI]; /* 0x001C */ } else if ((i128RamdacType == IBM526_DAC) || (i128RamdacType == IBM528_DAC)) { ! iR.i128_base_g[IDXL_I] = ! i128mem.rbase_g[IDXL_I]; /* 0x0010 */ ! iR.i128_base_g[IDXH_I] = ! i128mem.rbase_g[IDXH_I]; /* 0x0014 */ ! iR.i128_base_g[DATA_I] = ! i128mem.rbase_g[DATA_I]; /* 0x0018 */ ! iR.i128_base_g[IDXCTL_I] = ! i128mem.rbase_g[IDXCTL_I]; /* 0x001C */ } iR.i128_base_g[INT_VCNT] = i128mem.rbase_g[INT_VCNT]; /* 0x0020 */ *************** *** 116,203 **** iR.i128_base_w[MW0_MASK] = i128mem.rbase_w[MW0_MASK]; /* 0x0024 */ if (i128RamdacType == TI3025_DAC) { ! i128mem.rbase_g_b[INDEX_TI] = TI_CURS_CONTROL; ! iR.Ti302X[TI_CURS_CONTROL] = i128mem.rbase_g_b[DATA_TI]; ! i128mem.rbase_g_b[INDEX_TI] = TI_TRUE_COLOR_CONTROL; ! iR.Ti302X[TI_TRUE_COLOR_CONTROL] = i128mem.rbase_g_b[DATA_TI]; ! i128mem.rbase_g_b[INDEX_TI] = TI_VGA_SWITCH_CONTROL; ! iR.Ti302X[TI_VGA_SWITCH_CONTROL] = i128mem.rbase_g_b[DATA_TI]; ! i128mem.rbase_g_b[INDEX_TI] = TI_MUX_CONTROL_1; ! iR.Ti302X[TI_MUX_CONTROL_1] = i128mem.rbase_g_b[DATA_TI]; ! i128mem.rbase_g_b[INDEX_TI] = TI_MUX_CONTROL_2; ! iR.Ti302X[TI_MUX_CONTROL_2] = i128mem.rbase_g_b[DATA_TI]; ! i128mem.rbase_g_b[INDEX_TI] = TI_INPUT_CLOCK_SELECT; ! iR.Ti302X[TI_INPUT_CLOCK_SELECT] = i128mem.rbase_g_b[DATA_TI]; ! i128mem.rbase_g_b[INDEX_TI] = TI_OUTPUT_CLOCK_SELECT; ! iR.Ti302X[TI_OUTPUT_CLOCK_SELECT] = i128mem.rbase_g_b[DATA_TI]; ! i128mem.rbase_g_b[INDEX_TI] = TI_PALETTE_PAGE; ! iR.Ti302X[TI_PALETTE_PAGE] = i128mem.rbase_g_b[DATA_TI]; ! i128mem.rbase_g_b[INDEX_TI] = TI_GENERAL_CONTROL; ! iR.Ti302X[TI_GENERAL_CONTROL] = i128mem.rbase_g_b[DATA_TI]; ! i128mem.rbase_g_b[INDEX_TI] = TI_MISC_CONTROL; ! iR.Ti302X[TI_MISC_CONTROL] = i128mem.rbase_g_b[DATA_TI]; ! i128mem.rbase_g_b[INDEX_TI] = TI_AUXILIARY_CONTROL; ! iR.Ti302X[TI_AUXILIARY_CONTROL] = i128mem.rbase_g_b[DATA_TI]; ! i128mem.rbase_g_b[INDEX_TI] = TI_GENERAL_IO_CONTROL; ! iR.Ti302X[TI_GENERAL_IO_CONTROL] = i128mem.rbase_g_b[DATA_TI]; ! i128mem.rbase_g_b[INDEX_TI] = TI_GENERAL_IO_DATA; ! iR.Ti302X[TI_GENERAL_IO_DATA] = i128mem.rbase_g_b[DATA_TI]; ! i128mem.rbase_g_b[INDEX_TI] = TI_MCLK_DCLK_CONTROL; ! iR.Ti302X[TI_MCLK_DCLK_CONTROL] = i128mem.rbase_g_b[DATA_TI]; ! i128mem.rbase_g_b[INDEX_TI] = TI_COLOR_KEY_CONTROL; ! iR.Ti302X[TI_COLOR_KEY_CONTROL] = i128mem.rbase_g_b[DATA_TI]; ! i128mem.rbase_g_b[INDEX_TI] = TI_PLL_CONTROL; ! i128mem.rbase_g_b[DATA_TI] = 0x00; ! i128mem.rbase_g_b[INDEX_TI] = TI_PIXEL_CLOCK_PLL_DATA; ! iR.Ti3025[0] = i128mem.rbase_g_b[DATA_TI]; ! i128mem.rbase_g_b[INDEX_TI] = TI_PLL_CONTROL; ! i128mem.rbase_g_b[DATA_TI] = 0x01; ! i128mem.rbase_g_b[INDEX_TI] = TI_PIXEL_CLOCK_PLL_DATA; ! iR.Ti3025[1] = i128mem.rbase_g_b[DATA_TI]; ! i128mem.rbase_g_b[INDEX_TI] = TI_PLL_CONTROL; ! i128mem.rbase_g_b[DATA_TI] = 0x02; ! i128mem.rbase_g_b[INDEX_TI] = TI_PIXEL_CLOCK_PLL_DATA; ! iR.Ti3025[2] = i128mem.rbase_g_b[DATA_TI]; ! i128mem.rbase_g_b[INDEX_TI] = TI_PLL_CONTROL; ! i128mem.rbase_g_b[DATA_TI] = 0x00; ! i128mem.rbase_g_b[INDEX_TI] = TI_MCLK_PLL_DATA; ! iR.Ti3025[3] = i128mem.rbase_g_b[DATA_TI]; ! i128mem.rbase_g_b[INDEX_TI] = TI_PLL_CONTROL; ! i128mem.rbase_g_b[DATA_TI] = 0x01; ! i128mem.rbase_g_b[INDEX_TI] = TI_MCLK_PLL_DATA; ! iR.Ti3025[4] = i128mem.rbase_g_b[DATA_TI]; ! i128mem.rbase_g_b[INDEX_TI] = TI_PLL_CONTROL; ! i128mem.rbase_g_b[DATA_TI] = 0x02; ! i128mem.rbase_g_b[INDEX_TI] = TI_MCLK_PLL_DATA; ! iR.Ti3025[5] = i128mem.rbase_g_b[DATA_TI]; ! i128mem.rbase_g_b[INDEX_TI] = TI_PLL_CONTROL; ! i128mem.rbase_g_b[DATA_TI] = 0x00; ! i128mem.rbase_g_b[INDEX_TI] = TI_LOOP_CLOCK_PLL_DATA; ! iR.Ti3025[6] = i128mem.rbase_g_b[DATA_TI]; ! i128mem.rbase_g_b[INDEX_TI] = TI_PLL_CONTROL; ! i128mem.rbase_g_b[DATA_TI] = 0x01; ! i128mem.rbase_g_b[INDEX_TI] = TI_LOOP_CLOCK_PLL_DATA; ! iR.Ti3025[7] = i128mem.rbase_g_b[DATA_TI]; ! i128mem.rbase_g_b[INDEX_TI] = TI_PLL_CONTROL; ! i128mem.rbase_g_b[DATA_TI] = 0x02; ! i128mem.rbase_g_b[INDEX_TI] = TI_LOOP_CLOCK_PLL_DATA; ! iR.Ti3025[8] = i128mem.rbase_g_b[DATA_TI]; } else if ((i128RamdacType == IBM526_DAC) || (i128RamdacType == IBM528_DAC)) { CARD32 i; for (i=0; i<0x100; i++) { ! i128mem.rbase_g_b[IDXL_I] = i; ! iR.IBMRGB[i] = i128mem.rbase_g_b[DATA_I]; } } --- 114,201 ---- iR.i128_base_w[MW0_MASK] = i128mem.rbase_w[MW0_MASK]; /* 0x0024 */ if (i128RamdacType == TI3025_DAC) { ! i128mem.rbase_g[INDEX_TI] = TI_CURS_CONTROL; MB; ! iR.Ti302X[TI_CURS_CONTROL] = i128mem.rbase_g[DATA_TI]; ! i128mem.rbase_g[INDEX_TI] = TI_TRUE_COLOR_CONTROL; MB; ! iR.Ti302X[TI_TRUE_COLOR_CONTROL] = i128mem.rbase_g[DATA_TI]; ! i128mem.rbase_g[INDEX_TI] = TI_VGA_SWITCH_CONTROL; MB; ! iR.Ti302X[TI_VGA_SWITCH_CONTROL] = i128mem.rbase_g[DATA_TI]; ! i128mem.rbase_g[INDEX_TI] = TI_MUX_CONTROL_1; MB; ! iR.Ti302X[TI_MUX_CONTROL_1] = i128mem.rbase_g[DATA_TI]; ! i128mem.rbase_g[INDEX_TI] = TI_MUX_CONTROL_2; MB; ! iR.Ti302X[TI_MUX_CONTROL_2] = i128mem.rbase_g[DATA_TI]; ! i128mem.rbase_g[INDEX_TI] = TI_INPUT_CLOCK_SELECT; MB; ! iR.Ti302X[TI_INPUT_CLOCK_SELECT] = i128mem.rbase_g[DATA_TI]; ! i128mem.rbase_g[INDEX_TI] = TI_OUTPUT_CLOCK_SELECT; MB; ! iR.Ti302X[TI_OUTPUT_CLOCK_SELECT] = i128mem.rbase_g[DATA_TI]; ! i128mem.rbase_g[INDEX_TI] = TI_PALETTE_PAGE; MB; ! iR.Ti302X[TI_PALETTE_PAGE] = i128mem.rbase_g[DATA_TI]; ! i128mem.rbase_g[INDEX_TI] = TI_GENERAL_CONTROL; MB; ! iR.Ti302X[TI_GENERAL_CONTROL] = i128mem.rbase_g[DATA_TI]; ! i128mem.rbase_g[INDEX_TI] = TI_MISC_CONTROL; MB; ! iR.Ti302X[TI_MISC_CONTROL] = i128mem.rbase_g[DATA_TI]; ! i128mem.rbase_g[INDEX_TI] = TI_AUXILIARY_CONTROL; MB; ! iR.Ti302X[TI_AUXILIARY_CONTROL] = i128mem.rbase_g[DATA_TI]; ! i128mem.rbase_g[INDEX_TI] = TI_GENERAL_IO_CONTROL; MB; ! iR.Ti302X[TI_GENERAL_IO_CONTROL] = i128mem.rbase_g[DATA_TI]; ! i128mem.rbase_g[INDEX_TI] = TI_GENERAL_IO_DATA; MB; ! iR.Ti302X[TI_GENERAL_IO_DATA] = i128mem.rbase_g[DATA_TI]; ! i128mem.rbase_g[INDEX_TI] = TI_MCLK_DCLK_CONTROL; MB; ! iR.Ti302X[TI_MCLK_DCLK_CONTROL] = i128mem.rbase_g[DATA_TI]; ! i128mem.rbase_g[INDEX_TI] = TI_COLOR_KEY_CONTROL; MB; ! iR.Ti302X[TI_COLOR_KEY_CONTROL] = i128mem.rbase_g[DATA_TI]; ! i128mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB; ! i128mem.rbase_g[DATA_TI] = 0x00; MB; ! i128mem.rbase_g[INDEX_TI] = TI_PIXEL_CLOCK_PLL_DATA; MB; ! iR.Ti3025[0] = i128mem.rbase_g[DATA_TI]; ! i128mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB; ! i128mem.rbase_g[DATA_TI] = 0x01; MB; ! i128mem.rbase_g[INDEX_TI] = TI_PIXEL_CLOCK_PLL_DATA; MB; ! iR.Ti3025[1] = i128mem.rbase_g[DATA_TI]; ! i128mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB; ! i128mem.rbase_g[DATA_TI] = 0x02; MB; ! i128mem.rbase_g[INDEX_TI] = TI_PIXEL_CLOCK_PLL_DATA; MB; ! iR.Ti3025[2] = i128mem.rbase_g[DATA_TI]; ! i128mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB; ! i128mem.rbase_g[DATA_TI] = 0x00; MB; ! i128mem.rbase_g[INDEX_TI] = TI_MCLK_PLL_DATA; MB; ! iR.Ti3025[3] = i128mem.rbase_g[DATA_TI]; ! i128mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB; ! i128mem.rbase_g[DATA_TI] = 0x01; MB; ! i128mem.rbase_g[INDEX_TI] = TI_MCLK_PLL_DATA; MB; ! iR.Ti3025[4] = i128mem.rbase_g[DATA_TI]; ! i128mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB; ! i128mem.rbase_g[DATA_TI] = 0x02; MB; ! i128mem.rbase_g[INDEX_TI] = TI_MCLK_PLL_DATA; MB; ! iR.Ti3025[5] = i128mem.rbase_g[DATA_TI]; ! i128mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB; ! i128mem.rbase_g[DATA_TI] = 0x00; MB; ! i128mem.rbase_g[INDEX_TI] = TI_LOOP_CLOCK_PLL_DATA; MB; ! iR.Ti3025[6] = i128mem.rbase_g[DATA_TI]; ! i128mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB; ! i128mem.rbase_g[DATA_TI] = 0x01; MB; ! i128mem.rbase_g[INDEX_TI] = TI_LOOP_CLOCK_PLL_DATA; MB; ! iR.Ti3025[7] = i128mem.rbase_g[DATA_TI]; ! i128mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB; ! i128mem.rbase_g[DATA_TI] = 0x02; MB; ! i128mem.rbase_g[INDEX_TI] = TI_LOOP_CLOCK_PLL_DATA; MB; ! iR.Ti3025[8] = i128mem.rbase_g[DATA_TI]; } else if ((i128RamdacType == IBM526_DAC) || (i128RamdacType == IBM528_DAC)) { CARD32 i; for (i=0; i<0x100; i++) { ! i128mem.rbase_g[IDXL_I] = i; MB; ! iR.IBMRGB[i] = i128mem.rbase_g[DATA_I]; } } *************** *** 213,296 **** #endif { int i; - unsigned PCI_DevIOPorts[3]; if (i128RamdacType == TI3025_DAC) { ! i128mem.rbase_g_b[INDEX_TI] = TI_PLL_CONTROL; ! i128mem.rbase_g_b[DATA_TI] = 0x00; ! i128mem.rbase_g_b[INDEX_TI] = TI_PIXEL_CLOCK_PLL_DATA; ! i128mem.rbase_g_b[DATA_TI] = iR.Ti3025[0]; ! i128mem.rbase_g_b[INDEX_TI] = TI_PLL_CONTROL; ! i128mem.rbase_g_b[DATA_TI] = 0x01; ! i128mem.rbase_g_b[INDEX_TI] = TI_PIXEL_CLOCK_PLL_DATA; ! i128mem.rbase_g_b[DATA_TI] = iR.Ti3025[1]; ! i128mem.rbase_g_b[INDEX_TI] = TI_PLL_CONTROL; ! i128mem.rbase_g_b[DATA_TI] = 0x02; ! i128mem.rbase_g_b[INDEX_TI] = TI_PIXEL_CLOCK_PLL_DATA; ! i128mem.rbase_g_b[DATA_TI] = iR.Ti3025[2]; ! i128mem.rbase_g_b[INDEX_TI] = TI_PLL_CONTROL; ! i128mem.rbase_g_b[DATA_TI] = 0x00; ! i128mem.rbase_g_b[INDEX_TI] = TI_MCLK_PLL_DATA; ! i128mem.rbase_g_b[DATA_TI] = iR.Ti3025[3]; ! i128mem.rbase_g_b[INDEX_TI] = TI_PLL_CONTROL; ! i128mem.rbase_g_b[DATA_TI] = 0x01; ! i128mem.rbase_g_b[INDEX_TI] = TI_MCLK_PLL_DATA; ! i128mem.rbase_g_b[DATA_TI] = iR.Ti3025[4]; ! i128mem.rbase_g_b[INDEX_TI] = TI_PLL_CONTROL; ! i128mem.rbase_g_b[DATA_TI] = 0x02; ! i128mem.rbase_g_b[INDEX_TI] = TI_MCLK_PLL_DATA; ! i128mem.rbase_g_b[DATA_TI] = iR.Ti3025[5]; ! i128mem.rbase_g_b[INDEX_TI] = TI_PLL_CONTROL; ! i128mem.rbase_g_b[DATA_TI] = 0x00; ! i128mem.rbase_g_b[INDEX_TI] = TI_LOOP_CLOCK_PLL_DATA; ! i128mem.rbase_g_b[DATA_TI] = iR.Ti3025[6]; ! i128mem.rbase_g_b[INDEX_TI] = TI_PLL_CONTROL; ! i128mem.rbase_g_b[DATA_TI] = 0x01; ! i128mem.rbase_g_b[INDEX_TI] = TI_LOOP_CLOCK_PLL_DATA; ! i128mem.rbase_g_b[DATA_TI] = iR.Ti3025[7]; ! i128mem.rbase_g_b[INDEX_TI] = TI_PLL_CONTROL; ! i128mem.rbase_g_b[DATA_TI] = 0x02; ! i128mem.rbase_g_b[INDEX_TI] = TI_LOOP_CLOCK_PLL_DATA; ! i128mem.rbase_g_b[DATA_TI] = iR.Ti3025[8]; ! i128mem.rbase_g_b[INDEX_TI] = TI_CURS_CONTROL; ! i128mem.rbase_g_b[DATA_TI] = iR.Ti302X[TI_CURS_CONTROL]; ! i128mem.rbase_g_b[INDEX_TI] = TI_TRUE_COLOR_CONTROL; ! i128mem.rbase_g_b[DATA_TI] = iR.Ti302X[TI_TRUE_COLOR_CONTROL]; ! i128mem.rbase_g_b[INDEX_TI] = TI_VGA_SWITCH_CONTROL; ! i128mem.rbase_g_b[DATA_TI] = iR.Ti302X[TI_VGA_SWITCH_CONTROL]; ! i128mem.rbase_g_b[INDEX_TI] = TI_MUX_CONTROL_1; ! i128mem.rbase_g_b[DATA_TI] = iR.Ti302X[TI_MUX_CONTROL_1]; ! i128mem.rbase_g_b[INDEX_TI] = TI_MUX_CONTROL_2; ! i128mem.rbase_g_b[DATA_TI] = iR.Ti302X[TI_MUX_CONTROL_2]; ! i128mem.rbase_g_b[INDEX_TI] = TI_INPUT_CLOCK_SELECT; ! i128mem.rbase_g_b[DATA_TI] = iR.Ti302X[TI_INPUT_CLOCK_SELECT]; ! i128mem.rbase_g_b[INDEX_TI] = TI_OUTPUT_CLOCK_SELECT; ! i128mem.rbase_g_b[DATA_TI] = iR.Ti302X[TI_OUTPUT_CLOCK_SELECT]; ! i128mem.rbase_g_b[INDEX_TI] = TI_PALETTE_PAGE; ! i128mem.rbase_g_b[DATA_TI] = iR.Ti302X[TI_PALETTE_PAGE]; ! i128mem.rbase_g_b[INDEX_TI] = TI_GENERAL_CONTROL; ! i128mem.rbase_g_b[DATA_TI] = iR.Ti302X[TI_GENERAL_CONTROL]; ! i128mem.rbase_g_b[INDEX_TI] = TI_MISC_CONTROL; ! i128mem.rbase_g_b[DATA_TI] = iR.Ti302X[TI_MISC_CONTROL]; ! i128mem.rbase_g_b[INDEX_TI] = TI_AUXILIARY_CONTROL; ! i128mem.rbase_g_b[DATA_TI] = iR.Ti302X[TI_AUXILIARY_CONTROL]; ! i128mem.rbase_g_b[INDEX_TI] = TI_GENERAL_IO_CONTROL; ! i128mem.rbase_g_b[DATA_TI] = iR.Ti302X[TI_GENERAL_IO_CONTROL]; ! i128mem.rbase_g_b[INDEX_TI] = TI_GENERAL_IO_DATA; ! i128mem.rbase_g_b[DATA_TI] = iR.Ti302X[TI_GENERAL_IO_DATA]; ! i128mem.rbase_g_b[INDEX_TI] = TI_MCLK_DCLK_CONTROL; ! i128mem.rbase_g_b[DATA_TI] = iR.Ti302X[TI_MCLK_DCLK_CONTROL]; ! i128mem.rbase_g_b[INDEX_TI] = TI_COLOR_KEY_CONTROL; ! i128mem.rbase_g_b[DATA_TI] = iR.Ti302X[TI_COLOR_KEY_CONTROL]; } else if ((i128RamdacType == IBM526_DAC) || (i128RamdacType == IBM528_DAC)) { CARD32 i; --- 211,293 ---- #endif { int i; if (i128RamdacType == TI3025_DAC) { ! i128mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB; ! i128mem.rbase_g[DATA_TI] = 0x00; MB; ! i128mem.rbase_g[INDEX_TI] = TI_PIXEL_CLOCK_PLL_DATA; MB; ! i128mem.rbase_g[DATA_TI] = iR.Ti3025[0]; MB; ! i128mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB; ! i128mem.rbase_g[DATA_TI] = 0x01; MB; ! i128mem.rbase_g[INDEX_TI] = TI_PIXEL_CLOCK_PLL_DATA; MB; ! i128mem.rbase_g[DATA_TI] = iR.Ti3025[1]; MB; ! i128mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB; ! i128mem.rbase_g[DATA_TI] = 0x02; MB; ! i128mem.rbase_g[INDEX_TI] = TI_PIXEL_CLOCK_PLL_DATA; MB; ! i128mem.rbase_g[DATA_TI] = iR.Ti3025[2]; MB; ! i128mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB; ! i128mem.rbase_g[DATA_TI] = 0x00; MB; ! i128mem.rbase_g[INDEX_TI] = TI_MCLK_PLL_DATA; MB; ! i128mem.rbase_g[DATA_TI] = iR.Ti3025[3]; MB; ! i128mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB; ! i128mem.rbase_g[DATA_TI] = 0x01; MB; ! i128mem.rbase_g[INDEX_TI] = TI_MCLK_PLL_DATA; MB; ! i128mem.rbase_g[DATA_TI] = iR.Ti3025[4]; MB; ! i128mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB; ! i128mem.rbase_g[DATA_TI] = 0x02; MB; ! i128mem.rbase_g[INDEX_TI] = TI_MCLK_PLL_DATA; MB; ! i128mem.rbase_g[DATA_TI] = iR.Ti3025[5]; MB; ! i128mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB; ! i128mem.rbase_g[DATA_TI] = 0x00; MB; ! i128mem.rbase_g[INDEX_TI] = TI_LOOP_CLOCK_PLL_DATA; MB; ! i128mem.rbase_g[DATA_TI] = iR.Ti3025[6]; MB; ! i128mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB; ! i128mem.rbase_g[DATA_TI] = 0x01; MB; ! i128mem.rbase_g[INDEX_TI] = TI_LOOP_CLOCK_PLL_DATA; MB; ! i128mem.rbase_g[DATA_TI] = iR.Ti3025[7]; MB; ! i128mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB; ! i128mem.rbase_g[DATA_TI] = 0x02; MB; ! i128mem.rbase_g[INDEX_TI] = TI_LOOP_CLOCK_PLL_DATA; MB; ! i128mem.rbase_g[DATA_TI] = iR.Ti3025[8]; MB; ! i128mem.rbase_g[INDEX_TI] = TI_CURS_CONTROL; MB; ! i128mem.rbase_g[DATA_TI] = iR.Ti302X[TI_CURS_CONTROL]; MB; ! i128mem.rbase_g[INDEX_TI] = TI_TRUE_COLOR_CONTROL; MB; ! i128mem.rbase_g[DATA_TI] = iR.Ti302X[TI_TRUE_COLOR_CONTROL]; MB; ! i128mem.rbase_g[INDEX_TI] = TI_VGA_SWITCH_CONTROL; MB; ! i128mem.rbase_g[DATA_TI] = iR.Ti302X[TI_VGA_SWITCH_CONTROL]; MB; ! i128mem.rbase_g[INDEX_TI] = TI_MUX_CONTROL_1; MB; ! i128mem.rbase_g[DATA_TI] = iR.Ti302X[TI_MUX_CONTROL_1]; MB; ! i128mem.rbase_g[INDEX_TI] = TI_MUX_CONTROL_2; MB; ! i128mem.rbase_g[DATA_TI] = iR.Ti302X[TI_MUX_CONTROL_2]; MB; ! i128mem.rbase_g[INDEX_TI] = TI_INPUT_CLOCK_SELECT; MB; ! i128mem.rbase_g[DATA_TI] = iR.Ti302X[TI_INPUT_CLOCK_SELECT]; MB; ! i128mem.rbase_g[INDEX_TI] = TI_OUTPUT_CLOCK_SELECT; MB; ! i128mem.rbase_g[DATA_TI] = iR.Ti302X[TI_OUTPUT_CLOCK_SELECT];MB; ! i128mem.rbase_g[INDEX_TI] = TI_PALETTE_PAGE; MB; ! i128mem.rbase_g[DATA_TI] = iR.Ti302X[TI_PALETTE_PAGE]; MB; ! i128mem.rbase_g[INDEX_TI] = TI_GENERAL_CONTROL; MB; ! i128mem.rbase_g[DATA_TI] = iR.Ti302X[TI_GENERAL_CONTROL]; MB; ! i128mem.rbase_g[INDEX_TI] = TI_MISC_CONTROL; MB; ! i128mem.rbase_g[DATA_TI] = iR.Ti302X[TI_MISC_CONTROL]; MB; ! i128mem.rbase_g[INDEX_TI] = TI_AUXILIARY_CONTROL; MB; ! i128mem.rbase_g[DATA_TI] = iR.Ti302X[TI_AUXILIARY_CONTROL]; MB; ! i128mem.rbase_g[INDEX_TI] = TI_GENERAL_IO_CONTROL; MB; ! i128mem.rbase_g[DATA_TI] = iR.Ti302X[TI_GENERAL_IO_CONTROL]; MB; ! i128mem.rbase_g[INDEX_TI] = TI_GENERAL_IO_DATA; MB; ! i128mem.rbase_g[DATA_TI] = iR.Ti302X[TI_GENERAL_IO_DATA]; MB; ! i128mem.rbase_g[INDEX_TI] = TI_MCLK_DCLK_CONTROL; MB; ! i128mem.rbase_g[DATA_TI] = iR.Ti302X[TI_MCLK_DCLK_CONTROL]; MB; ! i128mem.rbase_g[INDEX_TI] = TI_COLOR_KEY_CONTROL; MB; ! i128mem.rbase_g[DATA_TI] = iR.Ti302X[TI_COLOR_KEY_CONTROL]; MB; } else if ((i128RamdacType == IBM526_DAC) || (i128RamdacType == IBM528_DAC)) { CARD32 i; *************** *** 299,326 **** if ((i == IBMRGB_sysclk_vco_div) || (i == IBMRGB_sysclk_ref_div)) continue; ! i128mem.rbase_g_b[IDXL_I] = i; ! i128mem.rbase_g_b[DATA_I] = iR.IBMRGB[i]; } ! i128mem.rbase_g_b[IDXL_I] = IBMRGB_sysclk_ref_div; ! i128mem.rbase_g_b[DATA_I] = ! iR.IBMRGB[IBMRGB_sysclk_ref_div]; ! i128mem.rbase_g_b[IDXL_I] = IBMRGB_sysclk_vco_div; ! i128mem.rbase_g_b[DATA_I] = ! iR.IBMRGB[IBMRGB_sysclk_vco_div]; usleep(50000); } - PCI_DevIOPorts[0] = iR.iobase + 0x1C; - PCI_DevIOPorts[1] = iR.iobase + 0x20; - PCI_DevIOPorts[2] = iR.iobase + 0x30; - - xf86AddIOPorts(i128InfoRec.scrnIndex, 3, PCI_DevIOPorts); xf86EnableIOPorts(i128InfoRec.scrnIndex); /* iobase is filled in during the device probe (as well as config 1&2)*/ ! if ((i128io.id&0x7) > 1) { int i; unsigned char *vidmem = (unsigned char *)i128mem.mw0_ad; --- 296,318 ---- if ((i == IBMRGB_sysclk_vco_div) || (i == IBMRGB_sysclk_ref_div)) continue; ! i128mem.rbase_g[IDXL_I] = i; MB; ! i128mem.rbase_g[DATA_I] = iR.IBMRGB[i]; MB; } ! i128mem.rbase_g[IDXL_I] = IBMRGB_sysclk_ref_div; MB; ! i128mem.rbase_g[DATA_I] = ! iR.IBMRGB[IBMRGB_sysclk_ref_div]; MB; ! i128mem.rbase_g[IDXL_I] = IBMRGB_sysclk_vco_div; MB; ! i128mem.rbase_g[DATA_I] = ! iR.IBMRGB[IBMRGB_sysclk_vco_div]; MB; usleep(50000); } xf86EnableIOPorts(i128InfoRec.scrnIndex); /* iobase is filled in during the device probe (as well as config 1&2)*/ ! if ((i128io.id&0x7) > 0) { int i; unsigned char *vidmem = (unsigned char *)i128mem.mw0_ad; *************** *** 331,343 **** /* restore the LUT */ ! i128mem.rbase_g_b[PEL_MASK] = 0xff; ! i128mem.rbase_g_b[WR_ADR] = 0x00; for (i=0; i<256; i++) { ! i128mem.rbase_g_b[PAL_DAT] = oldlut[i].r; ! i128mem.rbase_g_b[PAL_DAT] = oldlut[i].g; ! i128mem.rbase_g_b[PAL_DAT] = oldlut[i].b; } i128mem.rbase_w[MW0_CTRL] = iR.i128_base_w[MW0_CTRL]; /* 0x0000 */ --- 323,335 ---- /* restore the LUT */ ! i128mem.rbase_g[PEL_MASK] = 0xff; MB; ! i128mem.rbase_g[WR_ADR] = 0x00; MB; for (i=0; i<256; i++) { ! i128mem.rbase_g[PAL_DAT] = oldlut[i].r; MB; ! i128mem.rbase_g[PAL_DAT] = oldlut[i].g; MB; ! i128mem.rbase_g[PAL_DAT] = oldlut[i].b; MB; } i128mem.rbase_w[MW0_CTRL] = iR.i128_base_w[MW0_CTRL]; /* 0x0000 */ *************** *** 348,369 **** i128mem.rbase_w[MW0_WKEY] = iR.i128_base_w[MW0_WKEY]; /* 0x001C */ i128mem.rbase_w[MW0_KDAT] = iR.i128_base_w[MW0_KDAT]; /* 0x0020 */ i128mem.rbase_w[MW0_MASK] = iR.i128_base_w[MW0_MASK]; /* 0x0024 */ if (i128RamdacType == TI3025_DAC) { ! i128mem.rbase_g[INDEX_TI/4] = ! iR.i128_base_g[INDEX_TI/4]; /* 0x0018 */ ! i128mem.rbase_g[DATA_TI/4] = ! iR.i128_base_g[DATA_TI/4]; /* 0x001C */ } else if ((i128RamdacType == IBM526_DAC) || (i128RamdacType == IBM528_DAC)) { ! i128mem.rbase_g[IDXL_I/4] = ! iR.i128_base_g[IDXL_I/4]; /* 0x0010 */ ! i128mem.rbase_g[IDXH_I/4] = ! iR.i128_base_g[IDXH_I/4]; /* 0x0014 */ ! i128mem.rbase_g[DATA_I/4] = ! iR.i128_base_g[DATA_I/4]; /* 0x0018 */ ! i128mem.rbase_g[IDXCTL_I/4] = ! iR.i128_base_g[IDXCTL_I/4]; /* 0x001C */ } i128mem.rbase_g[INT_VCNT] = iR.i128_base_g[INT_VCNT]; /* 0x0020 */ --- 340,362 ---- i128mem.rbase_w[MW0_WKEY] = iR.i128_base_w[MW0_WKEY]; /* 0x001C */ i128mem.rbase_w[MW0_KDAT] = iR.i128_base_w[MW0_KDAT]; /* 0x0020 */ i128mem.rbase_w[MW0_MASK] = iR.i128_base_w[MW0_MASK]; /* 0x0024 */ + MB; if (i128RamdacType == TI3025_DAC) { ! i128mem.rbase_g[INDEX_TI] = ! iR.i128_base_g[INDEX_TI]; /* 0x0018 */ MB; ! i128mem.rbase_g[DATA_TI] = ! iR.i128_base_g[DATA_TI]; /* 0x001C */ MB; } else if ((i128RamdacType == IBM526_DAC) || (i128RamdacType == IBM528_DAC)) { ! i128mem.rbase_g[IDXL_I] = ! iR.i128_base_g[IDXL_I]; /* 0x0010 */ MB; ! i128mem.rbase_g[IDXH_I] = ! iR.i128_base_g[IDXH_I]; /* 0x0014 */ MB; ! i128mem.rbase_g[DATA_I] = ! iR.i128_base_g[DATA_I]; /* 0x0018 */ MB; ! i128mem.rbase_g[IDXCTL_I] = ! iR.i128_base_g[IDXCTL_I]; /* 0x001C */ MB; } i128mem.rbase_g[INT_VCNT] = iR.i128_base_g[INT_VCNT]; /* 0x0020 */ *************** *** 382,387 **** --- 375,381 ---- i128mem.rbase_g[CRT_ZOOM] = iR.i128_base_g[CRT_ZOOM]; /* 0x0054 */ i128mem.rbase_g[CRT_1CON] = iR.i128_base_g[CRT_1CON]; /* 0x0058 */ i128mem.rbase_g[CRT_2CON] = iR.i128_base_g[CRT_2CON]; /* 0x005C */ + MB; outl(iR.iobase + 0x20, iR.config2); outl(iR.iobase + 0x1C, iR.config1); *************** *** 413,419 **** #endif { int pitch_multiplier, iclock; - unsigned PCI_DevIOPorts[2]; Bool ret; CARD32 tmp; --- 407,412 ---- *************** *** 423,435 **** * we reset here again in case there was a VT switch */ ! PCI_DevIOPorts[0] = iR.iobase + 0x1C; ! PCI_DevIOPorts[1] = iR.iobase + 0x20; ! xf86AddIOPorts(i128InfoRec.scrnIndex, 2, PCI_DevIOPorts); ! xf86EnableIOPorts(i128InfoRec.scrnIndex); outl(iR.iobase + 0x1C, i128io.config1); outl(iR.iobase + 0x20, i128io.config2); ! xf86DisableIOPorts(i128InfoRec.scrnIndex); if (!i128Initialized) saveI128state(); --- 416,425 ---- * we reset here again in case there was a VT switch */ ! xf86EnableIOPorts(i128InfoRec.scrnIndex); outl(iR.iobase + 0x1C, i128io.config1); outl(iR.iobase + 0x20, i128io.config2); ! xf86DisableIOPorts(i128InfoRec.scrnIndex); if (!i128Initialized) saveI128state(); *************** *** 442,448 **** iclock = 4; else if (i128RamdacType == IBM528_DAC) iclock = 128 / i128InfoRec.bitsPerPixel; ! else if (i128MemoryTypeDram) iclock = 32 / i128InfoRec.bitsPerPixel; /* IBM526 DAC 32b bus */ else iclock = 64 / i128InfoRec.bitsPerPixel; /* IBM524/526 DAC */ --- 432,438 ---- iclock = 4; else if (i128RamdacType == IBM528_DAC) iclock = 128 / i128InfoRec.bitsPerPixel; ! else if (i128MemoryType == I128_MEMORY_DRAM) iclock = 32 / i128InfoRec.bitsPerPixel; /* IBM526 DAC 32b bus */ else iclock = 64 / i128InfoRec.bitsPerPixel; /* IBM524/526 DAC */ *************** *** 460,468 **** i128mem.rbase_g[CRT_VFP] = mode->VSyncStart - mode->VDisplay; i128mem.rbase_g[CRT_VS] = mode->VSyncEnd - mode->VSyncStart; i128mem.rbase_g[CRT_BORD] = 0x00; ! i128mem.rbase_g[CRT_1CON] = 0x00000070; ! if (i128MemoryTypeDram) tmp = 0x20000100; else { tmp = 0x00040101; if (i128InfoRec.videoRam == 2048) --- 450,464 ---- i128mem.rbase_g[CRT_VFP] = mode->VSyncStart - mode->VDisplay; i128mem.rbase_g[CRT_VS] = mode->VSyncEnd - mode->VSyncStart; i128mem.rbase_g[CRT_BORD] = 0x00; ! tmp = 0x00000070; ! if (i128DeviceType == I128_DEVICE_ID3) ! tmp |= 0x00000100; ! i128mem.rbase_g[CRT_1CON] = tmp; ! if ((i128MemoryType == I128_MEMORY_DRAM) || ! (i128MemoryType == I128_MEMORY_SGRAM)) tmp = 0x20000100; + else if (i128MemoryType == I128_MEMORY_WRAM) + tmp = 0x00040100; else { tmp = 0x00040101; if (i128InfoRec.videoRam == 2048) *************** *** 472,485 **** tmp |= 0x01000000; /* split transfer */ } i128mem.rbase_g[CRT_2CON] = tmp; i128mem.rbase_w[MW0_CTRL] = 0x00000000; ! if (i128InfoRec.videoRam == 2048) ! i128mem.rbase_w[MW0_SZ] = 0x00000009; ! else if (i128InfoRec.videoRam == 8192) ! i128mem.rbase_w[MW0_SZ] = 0x0000000B; ! else ! i128mem.rbase_w[MW0_SZ] = 0x0000000A; /* default to 4MB */ i128mem.rbase_w[MW0_PGE] = 0x00000000; i128mem.rbase_w[MW0_ORG] = 0x00000000; i128mem.rbase_w[MW0_MSRC] = 0x00000000; --- 468,494 ---- tmp |= 0x01000000; /* split transfer */ } i128mem.rbase_g[CRT_2CON] = tmp; + i128mem.rbase_g[CRT_ZOOM] = 0x00000000; i128mem.rbase_w[MW0_CTRL] = 0x00000000; ! switch (i128InfoRec.videoRam) { ! case 2048: ! i128mem.rbase_w[MW0_SZ] = 0x00000009; ! break; ! case 8192: ! i128mem.rbase_w[MW0_SZ] = 0x0000000B; ! break; ! case 8192+4096: ! /* no break */ ! case 16384: ! i128mem.rbase_w[MW0_SZ] = 0x0000000C; ! break; ! case 4096: ! /* no break */ ! default: ! i128mem.rbase_w[MW0_SZ] = 0x0000000A;/* default 4MB */ ! break; ! } i128mem.rbase_w[MW0_PGE] = 0x00000000; i128mem.rbase_w[MW0_ORG] = 0x00000000; i128mem.rbase_w[MW0_MSRC] = 0x00000000; *************** *** 486,495 **** i128mem.rbase_w[MW0_WKEY] = 0x00000000; i128mem.rbase_w[MW0_KDAT] = 0x00000000; i128mem.rbase_w[MW0_MASK] = 0xFFFFFFFF; ! if ((i128io.id&0x7) > 1) { ! PCI_DevIOPorts[0] = iR.iobase + 0x30; ! xf86AddIOPorts(i128InfoRec.scrnIndex, 1, PCI_DevIOPorts); xf86EnableIOPorts(i128InfoRec.scrnIndex); i128io.vga_ctl &= 0x0000FF00; --- 495,504 ---- i128mem.rbase_w[MW0_WKEY] = 0x00000000; i128mem.rbase_w[MW0_KDAT] = 0x00000000; i128mem.rbase_w[MW0_MASK] = 0xFFFFFFFF; + MB; ! if ((i128io.id&0x7) > 0) { ! xf86EnableIOPorts(i128InfoRec.scrnIndex); i128io.vga_ctl &= 0x0000FF00; *************** *** 531,554 **** { short i, j; ! i128mem.rbase_g_b[PEL_MASK] = 0xff; if (!i128LUTSaved) { ! i128mem.rbase_g_b[RD_ADR] = 0x00; for (i=0; i<256; i++) { ! oldlut[i].r = i128mem.rbase_g_b[PAL_DAT]; ! oldlut[i].g = i128mem.rbase_g_b[PAL_DAT]; ! oldlut[i].b = i128mem.rbase_g_b[PAL_DAT]; } i128LUTSaved = 1; } ! i128mem.rbase_g_b[WR_ADR] = 0x00; for (i=0; i<256; i++) { ! i128mem.rbase_g_b[PAL_DAT] = 0x00; ! i128mem.rbase_g_b[PAL_DAT] = 0x00; ! i128mem.rbase_g_b[PAL_DAT] = 0x00; } if (i128InfoRec.bitsPerPixel > 8) { --- 540,563 ---- { short i, j; ! i128mem.rbase_g[PEL_MASK] = 0xff; MB; if (!i128LUTSaved) { ! i128mem.rbase_g[RD_ADR] = 0x00; MB; for (i=0; i<256; i++) { ! oldlut[i].r = i128mem.rbase_g[PAL_DAT]; MB; ! oldlut[i].g = i128mem.rbase_g[PAL_DAT]; MB; ! oldlut[i].b = i128mem.rbase_g[PAL_DAT]; MB; } i128LUTSaved = 1; } ! i128mem.rbase_g[WR_ADR] = 0x00; MB; for (i=0; i<256; i++) { ! i128mem.rbase_g[PAL_DAT] = 0x00; MB; ! i128mem.rbase_g[PAL_DAT] = 0x00; MB; ! i128mem.rbase_g[PAL_DAT] = 0x00; MB; } if (i128InfoRec.bitsPerPixel > 8) { *************** *** 582,592 **** } } ! i128mem.rbase_g[WR_ADR] = 0x00; for(i=0; i<256; i++) { ! i128mem.rbase_g_b[PAL_DAT] = currenti128dac[i].r; ! i128mem.rbase_g_b[PAL_DAT] = currenti128dac[i].g; ! i128mem.rbase_g_b[PAL_DAT] = currenti128dac[i].b; } } LUTInited = TRUE; --- 591,601 ---- } } ! i128mem.rbase_g[WR_ADR] = 0x00; MB; for(i=0; i<256; i++) { ! i128mem.rbase_g[PAL_DAT] = currenti128dac[i].r; MB; ! i128mem.rbase_g[PAL_DAT] = currenti128dac[i].g; MB; ! i128mem.rbase_g[PAL_DAT] = currenti128dac[i].b; MB; } } LUTInited = TRUE; *** ./programs/Xserver/hw/xfree86/accel/i128/i128misc.c@@/PUBLIC-LATEST Sun Aug 10 12:58:18 1997 --- xc/programs/Xserver/hw/xfree86/accel/i128/i128misc.c Fri Mar 6 16:31:29 1998 *************** *** 1,4 **** ! /* $TOG: i128misc.c /main/4 1997/08/10 12:56:54 kaleb $ */ /* * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany. * --- 1,4 ---- ! /* $TOG: i128misc.c /main/5 1998/03/06 16:33:07 kaleb $ */ /* * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany. * *************** *** 27,33 **** * */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/accel/i128/i128misc.c,v 3.5.2.3 1997/07/26 06:30:47 dawes Exp $ */ #include "servermd.h" --- 27,33 ---- * */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/accel/i128/i128misc.c,v 3.5.2.4 1998/01/12 03:02:09 robin Exp $ */ #include "servermd.h" *************** *** 52,58 **** extern pointer i128VideoMem; extern struct i128mem i128mem; ! extern Bool xf86Exiting, xf86Resetting, xf86ProbeFailed, xf86Verbose; static Bool AlreadyInited = FALSE; static Bool i128ModeSwitched = FALSE; --- 52,58 ---- extern pointer i128VideoMem; extern struct i128mem i128mem; ! extern Bool xf86Exiting, xf86Resetting; static Bool AlreadyInited = FALSE; static Bool i128ModeSwitched = FALSE; *************** *** 265,274 **** /* the server is running on the current vt */ /* so just go for it */ ! if (on) ! i128mem.rbase_g[0x58/4] |= 0x40; ! else ! i128mem.rbase_g[0x58/4] &= ~0x40; } return (TRUE); } --- 265,275 ---- /* the server is running on the current vt */ /* so just go for it */ ! if (on) { ! i128mem.rbase_g[CRT_1CON] |= 0x40; MB; ! } else { ! i128mem.rbase_g[CRT_1CON] &= ~0x40; MB; ! } } return (TRUE); } *************** *** 320,326 **** x = i128DisplayWidth - i128HDisplay; Base = ((y*i128DisplayWidth + x) * (i128InfoRec.bitsPerPixel/8)); ! i128mem.rbase_g[DB_ADR] = (Base & I128_PAN_MASK) + i128DisplayOffset; /* now warp the cursor after the screen move */ i128AdjustCursorXPos = Base - (Base & I128_PAN_MASK); --- 321,327 ---- x = i128DisplayWidth - i128HDisplay; Base = ((y*i128DisplayWidth + x) * (i128InfoRec.bitsPerPixel/8)); ! i128mem.rbase_g[DB_ADR] = (Base & I128_PAN_MASK) + i128DisplayOffset; MB; /* now warp the cursor after the screen move */ i128AdjustCursorXPos = Base - (Base & I128_PAN_MASK); *** ./programs/Xserver/hw/xfree86/accel/i128/i128reg.h@@/PUBLIC-LATEST Sun Aug 10 12:58:24 1997 --- xc/programs/Xserver/hw/xfree86/accel/i128/i128reg.h Fri Mar 6 16:31:34 1998 *************** *** 1,4 **** ! /* $XFree86: xc/programs/Xserver/hw/xfree86/accel/i128/i128reg.h,v 3.5.2.2 1997/06/25 08:16:55 hohndel Exp $ */ /* * Copyright 1994 by Robin Cutshaw * --- 1,4 ---- ! /* $XFree86: xc/programs/Xserver/hw/xfree86/accel/i128/i128reg.h,v 3.5.2.4 1998/02/15 23:31:57 robin Exp $ */ /* * Copyright 1994 by Robin Cutshaw * *************** *** 21,27 **** * PERFORMANCE OF THIS SOFTWARE. * */ ! /* $TOG: i128reg.h /main/6 1997/08/10 12:56:59 kaleb $ */ struct i128pci { --- 21,27 ---- * PERFORMANCE OF THIS SOFTWARE. * */ ! /* $TOG: i128reg.h /main/7 1998/03/06 16:33:12 kaleb $ */ struct i128pci { *************** *** 68,74 **** CARD32 *rbase_a; CARD32 *rbase_b; CARD32 *rbase_i; - unsigned char *rbase_g_b; /* special byte pointer for ramdac registers */ }; /* save the registers needed for restoration in this structure */ --- 68,73 ---- *************** *** 85,93 **** --- 84,118 ---- } i128Registers; + /* display list processor instruction formats */ + typedef union { + struct { + CARD8 aad; + CARD8 bad; + CARD8 cad; + CARD8 control; + CARD32 rad; + CARD32 rbd; + CARD32 rcd; + } f0; + struct { + CARD32 xy0; + CARD32 xy2; + CARD32 xy3; + CARD32 xy1; + } f1; + CARD32 f4[4]; + } i128dlpu; + #define I128_DEVICE_ID1 0x2309105D #define I128_DEVICE_ID2 0x2339105D + #define I128_DEVICE_ID3 0x493D105D + #define I128_MEMORY_UNKNOWN 0x01 + #define I128_MEMORY_DRAM 0x02 + #define I128_MEMORY_WRAM 0x04 + #define I128_MEMORY_SGRAM 0x08 + /* RBASE_I register offsets */ #define GINTP 0x0000 *************** *** 95,110 **** /* RBASE_G register offsets (divided by four for double word indexing */ ! #define WR_ADR 0x0000 /* use rbase_g_b for byte indexing */ ! #define PAL_DAT 0x0004 /* use rbase_g_b for byte indexing */ ! #define PEL_MASK 0x0008 /* use rbase_g_b for byte indexing */ ! #define RD_ADR 0x000C /* use rbase_g_b for byte indexing */ ! #define INDEX_TI 0x0018 /* TI ramdac use rbase_g_b for byte indexing */ ! #define DATA_TI 0x001C /* TI ramdac use rbase_g_b for byte indexing */ ! #define IDXL_I 0x0010 /* IBM ramdac use rbase_g_b for byte indexing */ ! #define IDXH_I 0x0014 /* IBM ramdac use rbase_g_b for byte indexing */ ! #define DATA_I 0x0018 /* IBM ramdac use rbase_g_b for byte indexing */ ! #define IDXCTL_I 0x001C /* IBM ramdac use rbase_g_b for byte indexing */ #define INT_VCNT 0x0020/4 #define INT_HCNT 0x0024/4 #define DB_ADR 0x0028/4 --- 120,135 ---- /* RBASE_G register offsets (divided by four for double word indexing */ ! #define WR_ADR 0x0000/4 ! #define PAL_DAT 0x0004/4 ! #define PEL_MASK 0x0008/4 ! #define RD_ADR 0x000C/4 ! #define INDEX_TI 0x0018/4 /* TI ramdac */ ! #define DATA_TI 0x001C/4 /* TI ramdac */ ! #define IDXL_I 0x0010/4 /* IBM ramdac */ ! #define IDXH_I 0x0014/4 /* IBM ramdac */ ! #define DATA_I 0x0018/4 /* IBM ramdac */ ! #define IDXCTL_I 0x001C/4 /* IBM ramdac */ #define INT_VCNT 0x0020/4 #define INT_HCNT 0x0024/4 #define DB_ADR 0x0028/4 *************** *** 174,179 **** --- 199,205 ---- #define BC_MDM_MSK 0x00600000 #define BC_MDM_KEY 0x00200000 #define BC_MDM_PLN 0x00400000 + #define BC_BLK_ENA 0x00800000 #define BC_PSIZ_MSK 0x03000000 #define BC_PSIZ_8B 0x00000000 #define BC_PSIZ_16B 0x01000000 *************** *** 198,204 **** #define CMD_CLP_MSK 0x00E00000 #define CMD_PAT_MSK 0x0F000000 #define CMD_HDF_MSK 0x70000000 - #define CMD_BLIT 0x00000C01 #define CMD_OPC 0x0050/4 #define CO_NOOP 0x00 #define CO_BITBLT 0x01 --- 224,229 ---- *************** *** 278,283 **** --- 303,310 ---- #define XY_X_DATA 0xFFFF0000 #define XY_I_DATA1 0x0000FFFF #define XY_I_DATA2 0xFFFF0000 + #define DL_ADR 0x00F8/4 + #define DL_CNTRL 0x00FC/4 #define I128_WAIT_READY 1 #define I128_WAIT_DONE 2 *************** *** 290,292 **** --- 317,321 ---- #define RGB16_565 0 #define RGB16_555 1 #define RGB32_888 2 + + #define MB mem_barrier() *** ./programs/Xserver/hw/xfree86/accel/ibm8514/cmap.c@@/PUBLIC-LATEST Sun Oct 19 15:00:22 1997 --- xc/programs/Xserver/hw/xfree86/accel/ibm8514/cmap.c Fri Mar 6 16:31:38 1998 *************** *** 24,30 **** * Modified by Tiago Gons (tiago@comosjn.hobby.nl) * */ ! /* $TOG: cmap.c /main/5 1997/10/19 15:02:26 kaleb $ */ #include "X.h" --- 24,30 ---- * Modified by Tiago Gons (tiago@comosjn.hobby.nl) * */ ! /* $TOG: cmap.c /main/6 1998/03/06 16:33:16 kaleb $ */ #include "X.h" *************** *** 92,107 **** } for (i = 0; i < ndef; i++) { ! unsigned char red, green, blue; ! ! red = current8514dac[pdefs[i].pixel].r = pdefs[i].red >> 10; ! green = current8514dac[pdefs[i].pixel].g = pdefs[i].green >> 10; ! blue = current8514dac[pdefs[i].pixel].b = pdefs[i].blue >> 10; if (xf86VTSema) { outb(DAC_W_INDEX, pdefs[i].pixel); ! outb(DAC_DATA, red); ! outb(DAC_DATA, green); ! outb(DAC_DATA, blue); } } } --- 92,105 ---- } for (i = 0; i < ndef; i++) { ! current8514dac[pdefs[i].pixel].r = pdefs[i].red >> 10; ! current8514dac[pdefs[i].pixel].g = pdefs[i].green >> 10; ! current8514dac[pdefs[i].pixel].b = pdefs[i].blue >> 10; if (xf86VTSema) { outb(DAC_W_INDEX, pdefs[i].pixel); ! outb(DAC_DATA, pdefs[i].red >> 10); ! outb(DAC_DATA, pdefs[i].green >> 10); ! outb(DAC_DATA, pdefs[i].blue >> 10); } } } *************** *** 116,122 **** Pixel * ppix; xrgb * prgb; xColorItem *defs; ! int i,j; if (pmap == oldmap) --- 114,120 ---- Pixel * ppix; xrgb * prgb; xColorItem *defs; ! int i; if (pmap == oldmap) *************** *** 140,182 **** for ( i=0; iclass == GrayScale || pmap->class == PseudoColor) ! { ! for ( i=j=0; ired[i].fShared || pmap->red[i].refcnt != 0) ! { ! defs[j].pixel = i; ! defs[j].flags = DoRed|DoGreen|DoBlue; ! if (pmap->red[i].fShared) ! { ! defs[j].red = pmap->red[i].co.shco.red->color; ! defs[j].green = pmap->red[i].co.shco.green->color; ! defs[j].blue = pmap->red[i].co.shco.blue->color; ! } ! else if (pmap->red[i].refcnt != 0) ! { ! defs[j].red = pmap->red[i].co.local.red; ! defs[j].green = pmap->red[i].co.local.green; ! defs[j].blue = pmap->red[i].co.local.blue; ! } ! j++; ! } ! } ! entries = j; ! } ! else ! { ! QueryColors( pmap, entries, ppix, prgb); ! for ( i=0; i> nshift; ! green = mach32savedLUT[pdefs[i].pixel].g = pdefs[i].green >> nshift; ! blue = mach32savedLUT[pdefs[i].pixel].b = pdefs[i].blue >> nshift; ! if (xf86VTSema #ifdef XFreeXDGA || ((mach32InfoRec.directMode & XF86DGADirectGraphics) --- 90,108 ---- pdefs = directDefs; } for (i = 0; i < ndef; i++) { /* Return the n most significant bits from a 16-bit value. * For VGA, n = 6. For 8-bit DACs, n = 8. */ ! if (mach32DAC8Bit) { ! mach32savedLUT[pdefs[i].pixel].r = pdefs[i].red >> 8; ! mach32savedLUT[pdefs[i].pixel].g = pdefs[i].green >> 8; ! mach32savedLUT[pdefs[i].pixel].b = pdefs[i].blue >> 8; ! } else { ! mach32savedLUT[pdefs[i].pixel].r = pdefs[i].red >> 10; ! mach32savedLUT[pdefs[i].pixel].g = pdefs[i].green >> 10; ! mach32savedLUT[pdefs[i].pixel].b = pdefs[i].blue >> 10; ! } if (xf86VTSema #ifdef XFreeXDGA || ((mach32InfoRec.directMode & XF86DGADirectGraphics) *************** *** 109,117 **** #endif ) { outb(DAC_W_INDEX, pdefs[i].pixel); ! outb(DAC_DATA, red); ! outb(DAC_DATA, green); ! outb(DAC_DATA, blue); } } checkCursorColor = TRUE; --- 111,125 ---- #endif ) { outb(DAC_W_INDEX, pdefs[i].pixel); ! if (mach32DAC8Bit) { ! outb(DAC_DATA, pdefs[i].red >> 8); ! outb(DAC_DATA, pdefs[i].green >> 8); ! outb(DAC_DATA, pdefs[i].blue >> 8); ! } else { ! outb(DAC_DATA, pdefs[i].red >> 10); ! outb(DAC_DATA, pdefs[i].green >> 10); ! outb(DAC_DATA, pdefs[i].blue >> 10); ! } } } checkCursorColor = TRUE; *************** *** 127,133 **** Pixel * ppix; xrgb * prgb; xColorItem *defs; ! int i,j; if (pmap == oldmap) --- 135,141 ---- Pixel * ppix; xrgb * prgb; xColorItem *defs; ! int i; if (pmap == oldmap) *************** *** 151,193 **** for ( i=0; iclass == GrayScale || pmap->class == PseudoColor) ! { ! for ( i=j=0; ired[i].fShared || pmap->red[i].refcnt != 0) ! { ! defs[j].pixel = i; ! defs[j].flags = DoRed|DoGreen|DoBlue; ! if (pmap->red[i].fShared) ! { ! defs[j].red = pmap->red[i].co.shco.red->color; ! defs[j].green = pmap->red[i].co.shco.green->color; ! defs[j].blue = pmap->red[i].co.shco.blue->color; ! } ! else if (pmap->red[i].refcnt != 0) ! { ! defs[j].red = pmap->red[i].co.local.red; ! defs[j].green = pmap->red[i].co.local.green; ! defs[j].blue = pmap->red[i].co.local.blue; ! } ! j++; ! } ! } ! entries = j; ! } ! else ! { ! QueryColors( pmap, entries, ppix, prgb); ! for ( i=0; i> 3; info.DAC_Type = (tmp & CFG_INIT_DAC_TYPE) >> 9; --- 508,514 ---- #endif tmp = inl(ioCONFIG_STAT0); ! if (info.ChipType == MACH64_GX_ID || info.ChipType == MACH64_CX_ID) { info.Bus_Type = tmp & CFG_BUS_TYPE; info.Mem_Type = (tmp & CFG_MEM_TYPE) >> 3; info.DAC_Type = (tmp & CFG_INIT_DAC_TYPE) >> 9; *************** *** 519,526 **** } tmp = inl(ioMEM_CNTL); ! if ((info.ChipType == MACH64_VT || info.ChipType == MACH64_GT) && ! (info.ChipRev & 0x07)) { switch (tmp & MEM_SIZE_ALIAS_GTB) { case MEM_SIZE_512K: info.Mem_Size = 512; --- 524,538 ---- } tmp = inl(ioMEM_CNTL); ! if (((info.ChipType == MACH64_VT_ID || ! info.ChipType == MACH64_GT_ID) && (info.ChipRev & 0x07)) || ! info.ChipType == MACH64_VU_ID || ! info.ChipType == MACH64_GU_ID || ! info.ChipType == MACH64_GB_ID || ! info.ChipType == MACH64_GD_ID || ! info.ChipType == MACH64_GI_ID || ! info.ChipType == MACH64_GP_ID || ! info.ChipType == MACH64_GQ_ID) { switch (tmp & MEM_SIZE_ALIAS_GTB) { case MEM_SIZE_512K: info.Mem_Size = 512; *************** *** 540,545 **** --- 552,560 ---- case MEM_SIZE_8M_GTB: info.Mem_Size = 8*1024; break; + case MEM_SIZE_16M_GTB: + info.Mem_Size = 16*1024; + break; } } else { switch (tmp & MEM_SIZE_ALIAS) { *************** *** 636,669 **** if (pcrp->_vendor == PCI_ATI_VENDOR_ID) { found = TRUE; devid = pcrp->_device; ! switch (pcrp->_device) { ! case PCI_MACH64_GX: ! info.ChipType = MACH64_GX; break; ! case PCI_MACH64_CX: ! info.ChipType = MACH64_CX; break; ! case PCI_MACH64_CT: ! info.ChipType = MACH64_CT; break; - case PCI_MACH64_ET: - info.ChipType = MACH64_ET; - break; - case PCI_MACH64_VT: - case PCI_MACH64_VU: - info.ChipType = MACH64_VT; - break; - case PCI_MACH64_GT: - case PCI_MACH64_GU: - case PCI_MACH64_GP: - info.ChipType = MACH64_GT; - break; default: ! info.ChipType = MACH64_UNKNOWN; break; } info.ChipRev = pcrp->_rev_id; info.ApertureBase = pcrp->_base0 & 0xFFFFFFF0; /* * The docs say check (pcrp->_user_config_0 & 0x04) for BlockIO * but this doesn't seem to be reliable. Instead check if --- 651,695 ---- if (pcrp->_vendor == PCI_ATI_VENDOR_ID) { found = TRUE; devid = pcrp->_device; ! switch (devid) { ! case PCI_MACH64_GX_ID: ! info.ChipType = MACH64_GX_ID; break; ! case PCI_MACH64_CX_ID: ! info.ChipType = MACH64_CX_ID; break; ! case PCI_MACH64_CT_ID: ! case PCI_MACH64_ET_ID: ! case PCI_MACH64_VT_ID: ! case PCI_MACH64_VU_ID: ! case PCI_MACH64_GT_ID: ! case PCI_MACH64_GU_ID: ! case PCI_MACH64_GB_ID: ! case PCI_MACH64_GD_ID: ! case PCI_MACH64_GI_ID: ! case PCI_MACH64_GP_ID: ! case PCI_MACH64_GQ_ID: ! info.ChipType = devid; break; default: ! info.ChipType = MACH64_UNKNOWN_ID; break; } info.ChipRev = pcrp->_rev_id; info.ApertureBase = pcrp->_base0 & 0xFFFFFFF0; + if (((info.ChipType == PCI_MACH64_VT_ID || + info.ChipType == PCI_MACH64_GT_ID) && (info.ChipRev & 0x07)) || + info.ChipType == PCI_MACH64_VU_ID || + info.ChipType == PCI_MACH64_GU_ID || + info.ChipType == PCI_MACH64_GB_ID || + info.ChipType == PCI_MACH64_GD_ID || + info.ChipType == PCI_MACH64_GI_ID || + info.ChipType == PCI_MACH64_GP_ID || + info.ChipType == PCI_MACH64_GQ_ID) { + info.RegisterBase = pcrp->_base2 & 0xFFFFF000; + } else { + info.RegisterBase = 0; + } /* * The docs say check (pcrp->_user_config_0 & 0x04) for BlockIO * but this doesn't seem to be reliable. Instead check if *************** *** 712,723 **** xf86cleanpci(); if (found && xf86Verbose) { ! if (info.ChipType != MACH64_UNKNOWN) { ! ErrorF("%s %s: PCI: %s rev %d, Aperture @ 0x%08x," ! " %s I/O @ 0x%04x\n", XCONFIG_PROBED, mach64InfoRec.name, ! xf86TokenToString(mach64ChipTable, info.ChipType), ! info.ChipRev, info.ApertureBase, ! info.BlockIO ? "Block" : "Sparse", info.IOBase); } else { ErrorF("%s %s: PCI: unknown ATI (0x%04x) rev %d, Aperture @ 0x%08x," " %s I/O @ 0x%04x\n", XCONFIG_PROBED, mach64InfoRec.name, --- 738,758 ---- xf86cleanpci(); if (found && xf86Verbose) { ! if (info.ChipType != MACH64_UNKNOWN_ID) { ! if (info.RegisterBase) { ! ErrorF("%s %s: PCI: %s rev %d, Aperture @ 0x%08x," ! " Registers @ 0x%08x, %s I/O @ 0x%04x\n", ! XCONFIG_PROBED, mach64InfoRec.name, ! xf86TokenToString(mach64ChipTable, info.ChipType), ! info.ChipRev, info.ApertureBase, info.RegisterBase, ! info.BlockIO ? "Block" : "Sparse", info.IOBase); ! } else { ! ErrorF("%s %s: PCI: %s rev %d, Aperture @ 0x%08x," ! " %s I/O @ 0x%04x\n", XCONFIG_PROBED, mach64InfoRec.name, ! xf86TokenToString(mach64ChipTable, info.ChipType), ! info.ChipRev, info.ApertureBase, ! info.BlockIO ? "Block" : "Sparse", info.IOBase); ! } } else { ErrorF("%s %s: PCI: unknown ATI (0x%04x) rev %d, Aperture @ 0x%08x," " %s I/O @ 0x%04x\n", XCONFIG_PROBED, mach64InfoRec.name, *************** *** 748,755 **** M = pll[PLL_REF_DIV]; N = pll[VCLK0_FB_DIV]; ! if ((mach64ChipType == MACH64_VT || mach64ChipType == MACH64_GT) && ! (mach64ChipRev & 0x07) && (pll[PLL_XCLK_CNTL] & 0x10)) { switch (pll[VCLK_POST_DIV] & VCLK0_POST) { case 0: P = 3; break; case 1: P = 2; break; /* Unknown */ --- 783,789 ---- M = pll[PLL_REF_DIV]; N = pll[VCLK0_FB_DIV]; ! if (mach64HasDSP && (pll[PLL_XCLK_CNTL] & 0x10)) { switch (pll[VCLK_POST_DIV] & VCLK0_POST) { case 0: P = 3; break; case 1: P = 2; break; /* Unknown */ *************** *** 762,769 **** ErrorF("VCLK0: M=%d, N=%d, P=%d, Clk=%.2f\n", M, N, P, (double)((2 * R * N)/(M * P)) / 100.0); N = pll[VCLK1_FB_DIV]; ! if ((mach64ChipType == MACH64_VT || mach64ChipType == MACH64_GT) && ! (mach64ChipRev & 0x07) && (pll[PLL_XCLK_CNTL] & 0x20)) { switch ((pll[VCLK_POST_DIV] & VCLK1_POST) >> 2) { case 0: P = 3; break; case 1: P = 2; break; /* Unknown */ --- 796,802 ---- ErrorF("VCLK0: M=%d, N=%d, P=%d, Clk=%.2f\n", M, N, P, (double)((2 * R * N)/(M * P)) / 100.0); N = pll[VCLK1_FB_DIV]; ! if (mach64HasDSP && (pll[PLL_XCLK_CNTL] & 0x20)) { switch ((pll[VCLK_POST_DIV] & VCLK1_POST) >> 2) { case 0: P = 3; break; case 1: P = 2; break; /* Unknown */ *************** *** 776,783 **** ErrorF("VCLK1: M=%d, N=%d, P=%d, Clk=%.2f\n", M, N, P, (double)((2 * R * N)/(M * P)) / 100.0); N = pll[VCLK2_FB_DIV]; ! if ((mach64ChipType == MACH64_VT || mach64ChipType == MACH64_GT) && ! (mach64ChipRev & 0x07) && (pll[PLL_XCLK_CNTL] & 0x40)) { switch ((pll[VCLK_POST_DIV] & VCLK2_POST) >> 4) { case 0: P = 3; break; case 1: P = 2; break; /* Unknown */ --- 809,815 ---- ErrorF("VCLK1: M=%d, N=%d, P=%d, Clk=%.2f\n", M, N, P, (double)((2 * R * N)/(M * P)) / 100.0); N = pll[VCLK2_FB_DIV]; ! if (mach64HasDSP && (pll[PLL_XCLK_CNTL] & 0x40)) { switch ((pll[VCLK_POST_DIV] & VCLK2_POST) >> 4) { case 0: P = 3; break; case 1: P = 2; break; /* Unknown */ *************** *** 790,797 **** ErrorF("VCLK2: M=%d, N=%d, P=%d, Clk=%.2f\n", M, N, P, (double)((2 * R * N)/(M * P)) / 100.0); N = pll[VCLK3_FB_DIV]; ! if ((mach64ChipType == MACH64_VT || mach64ChipType == MACH64_GT) && ! (mach64ChipRev & 0x07) && (pll[PLL_XCLK_CNTL] & 0x80)) { switch ((pll[VCLK_POST_DIV] & VCLK3_POST) >> 6) { case 0: P = 3; break; case 1: P = 2; break; /* Unknown */ --- 822,828 ---- ErrorF("VCLK2: M=%d, N=%d, P=%d, Clk=%.2f\n", M, N, P, (double)((2 * R * N)/(M * P)) / 100.0); N = pll[VCLK3_FB_DIV]; ! if (mach64HasDSP && (pll[PLL_XCLK_CNTL] & 0x80)) { switch ((pll[VCLK_POST_DIV] & VCLK3_POST) >> 6) { case 0: P = 3; break; case 1: P = 2; break; /* Unknown */ *************** *** 935,946 **** "Sparse", 0x2EC); } ! if (mach64ChipType == MACH64_GX || mach64ChipType == MACH64_CX) mach64IntegratedController = FALSE; else ! /* Even for MACH64_UNKNOWN more than likely */ mach64IntegratedController = TRUE; #ifdef DEBUG if (mach64IntegratedController) mach64PrintCTPLL(); --- 966,991 ---- "Sparse", 0x2EC); } ! if (mach64ChipType == MACH64_GX_ID || mach64ChipType == MACH64_CX_ID) mach64IntegratedController = FALSE; else ! /* Even for MACH64_UNKNOWN_ID more than likely */ mach64IntegratedController = TRUE; + if (((mach64ChipType == MACH64_VT_ID || + mach64ChipType == MACH64_GT_ID) && (mach64ChipRev & 0x07)) || + mach64ChipType == MACH64_VU_ID || + mach64ChipType == MACH64_GU_ID || + mach64ChipType == MACH64_GB_ID || + mach64ChipType == MACH64_GD_ID || + mach64ChipType == MACH64_GI_ID || + mach64ChipType == MACH64_GP_ID || + mach64ChipType == MACH64_GQ_ID) { + mach64HasDSP = TRUE; + } else { + mach64HasDSP = FALSE; + } + #ifdef DEBUG if (mach64IntegratedController) mach64PrintCTPLL(); *************** *** 1067,1075 **** mach64InfoRec.maxClock = 135000; break; case DAC_INTERNAL: ! if ((mach64ChipType == MACH64_VT || mach64ChipType == MACH64_GT) && (mach64ChipRev & 0x07)) { mach64InfoRec.maxClock = 170000; } else { if (xf86bpp == 8) mach64InfoRec.maxClock = 135000; --- 1112,1129 ---- mach64InfoRec.maxClock = 135000; break; case DAC_INTERNAL: ! if ((mach64ChipType == MACH64_VT_ID || mach64ChipType == MACH64_GT_ID) && (mach64ChipRev & 0x07)) { mach64InfoRec.maxClock = 170000; + } else if (mach64ChipType == MACH64_VU_ID || + mach64ChipType == MACH64_GU_ID) { + mach64InfoRec.maxClock = 200000; + } else if (mach64ChipType == MACH64_GB_ID || + mach64ChipType == MACH64_GD_ID || + mach64ChipType == MACH64_GI_ID || + mach64ChipType == MACH64_GP_ID || + mach64ChipType == MACH64_GQ_ID) { + mach64InfoRec.maxClock = 230000; } else { if (xf86bpp == 8) mach64InfoRec.maxClock = 135000; *************** *** 1085,1090 **** --- 1139,1147 ---- break; } + if (mach64InfoRec.dacSpeeds[0] > 0) + mach64InfoRec.maxClock = mach64InfoRec.dacSpeeds[0]; + OFLG_ZERO(&validOptions); OFLG_SET(OPTION_CLKDIV2, &validOptions); OFLG_SET(OPTION_HW_CURSOR, &validOptions); *************** *** 1095,1101 **** } OFLG_SET(OPTION_DAC_6_BIT, &validOptions); OFLG_SET(OPTION_OVERRIDE_BIOS, &validOptions); ! if (!mach64IntegratedController) { OFLG_SET(OPTION_NO_BLOCK_WRITE, &validOptions); OFLG_SET(OPTION_BLOCK_WRITE, &validOptions); } --- 1152,1163 ---- } OFLG_SET(OPTION_DAC_6_BIT, &validOptions); OFLG_SET(OPTION_OVERRIDE_BIOS, &validOptions); ! if (!mach64IntegratedController || ! mach64ChipType == MACH64_GB_ID || ! mach64ChipType == MACH64_GD_ID || ! mach64ChipType == MACH64_GI_ID || ! mach64ChipType == MACH64_GP_ID || ! mach64ChipType == MACH64_GQ_ID) { OFLG_SET(OPTION_NO_BLOCK_WRITE, &validOptions); OFLG_SET(OPTION_BLOCK_WRITE, &validOptions); } *************** *** 1120,1126 **** if (xf86Verbose) { ! ErrorF("%s %s: card type: ", XCONFIG_PROBED, mach64InfoRec.name); switch(mach64BusType) { case ISA: --- 1182,1188 ---- if (xf86Verbose) { ! ErrorF("%s %s: Card type: ", XCONFIG_PROBED, mach64InfoRec.name); switch(mach64BusType) { case ISA: *************** *** 1133,1139 **** ErrorF("VESA LocalBus\n"); break; case PCI: ! ErrorF("PCI\n"); break; default: ErrorF("Unknown\n"); --- 1195,1205 ---- ErrorF("VESA LocalBus\n"); break; case PCI: ! if (mach64ChipType == MACH64_GB_ID || ! mach64ChipType == MACH64_GD_ID) ! ErrorF("AGP\n"); ! else ! ErrorF("PCI\n"); break; default: ErrorF("Unknown\n"); *************** *** 1256,1262 **** for (i = 0; i < mach64InfoRec.clocks; i++) { if (i % 8 == 0) ! ErrorF("\n%s %s: clocks:", (OFLG_ISSET(XCONFIG_CLOCKS,&mach64InfoRec.xconfigFlag) && OFLG_ISSET(OPTION_NO_BIOS_CLOCKS, &mach64InfoRec.options)) ? XCONFIG_GIVEN : XCONFIG_PROBED, --- 1322,1328 ---- for (i = 0; i < mach64InfoRec.clocks; i++) { if (i % 8 == 0) ! ErrorF("\n%s %s: Clocks:", (OFLG_ISSET(XCONFIG_CLOCKS,&mach64InfoRec.xconfigFlag) && OFLG_ISSET(OPTION_NO_BIOS_CLOCKS, &mach64InfoRec.options)) ? XCONFIG_GIVEN : XCONFIG_PROBED, *************** *** 1307,1316 **** xf86DeleteMode(&mach64InfoRec, pMode); pMode = pModeSv; } else if ((pMode->Flags & V_DBLSCAN) && ! (mach64ChipType == MACH64_GX || ! mach64ChipType == MACH64_CX || ! mach64ChipType == MACH64_CT || ! mach64ChipType == MACH64_ET)) { pModeSv=pMode->next; ErrorF("%s %s: Doublescan mode not supported on the %s\n", XCONFIG_PROBED, mach64InfoRec.name, --- 1373,1382 ---- xf86DeleteMode(&mach64InfoRec, pMode); pMode = pModeSv; } else if ((pMode->Flags & V_DBLSCAN) && ! (mach64ChipType == MACH64_GX_ID || ! mach64ChipType == MACH64_CX_ID || ! mach64ChipType == MACH64_CT_ID || ! mach64ChipType == MACH64_ET_ID)) { pModeSv=pMode->next; ErrorF("%s %s: Doublescan mode not supported on the %s\n", XCONFIG_PROBED, mach64InfoRec.name, *************** *** 1408,1418 **** mach64MemorySize = MEM_SIZE_4M; else if (mach64InfoRec.videoRam <= 6144) mach64MemorySize = MEM_SIZE_6M; ! else mach64MemorySize = MEM_SIZE_8M; if (xf86Verbose) { ! ErrorF("%s %s: videoram: %dk\n", OFLG_ISSET(XCONFIG_VIDEORAM, &mach64InfoRec.xconfigFlag) ? XCONFIG_GIVEN : XCONFIG_PROBED, mach64InfoRec.name, mach64InfoRec.videoRam ); --- 1474,1486 ---- mach64MemorySize = MEM_SIZE_4M; else if (mach64InfoRec.videoRam <= 6144) mach64MemorySize = MEM_SIZE_6M; ! else if (mach64InfoRec.videoRam <= 8192) mach64MemorySize = MEM_SIZE_8M; + else + mach64MemorySize = MEM_SIZE_16M; if (xf86Verbose) { ! ErrorF("%s %s: Video RAM: %dk\n", OFLG_ISSET(XCONFIG_VIDEORAM, &mach64InfoRec.xconfigFlag) ? XCONFIG_GIVEN : XCONFIG_PROBED, mach64InfoRec.name, mach64InfoRec.videoRam ); *************** *** 1436,1443 **** mach64MaxY = (mach64InfoRec.videoRam * 1024) / (mach64VirtX * (mach64InfoRec.bitsPerPixel / 8)) - 1; ! /* Reserve space for the registers at the end of video memory */ ! mach64InfoRec.videoRam--; available_ram = mach64InfoRec.videoRam * 1024; --- 1504,1515 ---- mach64MaxY = (mach64InfoRec.videoRam * 1024) / (mach64VirtX * (mach64InfoRec.bitsPerPixel / 8)) - 1; ! /* No need to reserve space for the registers in the frame buffer */ ! /* if we are using the auxilliary register aperture */ ! if (!pciInfo || !(pciInfo->RegisterBase)) { ! /* Reserve space for the registers at the end of video memory */ ! mach64InfoRec.videoRam--; ! } available_ram = mach64InfoRec.videoRam * 1024; *************** *** 1508,1519 **** mach64ApertureAddr = 0x04000000; /* for VLB */ } ! if ((mach64BusType == ISA) && (mach64ChipType != MACH64_VT)) { mach64ApertureSize = MEM_SIZE_4M; if (xf86Verbose) { ErrorF("%s %s: Using 4 MB aperture @ 0x%08x\n", XCONFIG_PROBED, mach64InfoRec.name, mach64ApertureAddr); } } else { mach64ApertureSize = MEM_SIZE_8M; if (xf86Verbose) { --- 1580,1598 ---- mach64ApertureAddr = 0x04000000; /* for VLB */ } ! if ((mach64BusType == ISA) && (mach64ChipType != MACH64_VT_ID)) { mach64ApertureSize = MEM_SIZE_4M; if (xf86Verbose) { ErrorF("%s %s: Using 4 MB aperture @ 0x%08x\n", XCONFIG_PROBED, mach64InfoRec.name, mach64ApertureAddr); } + } else if ((mach64BusType == PCI) && (mach64IntegratedController)) { + mach64ApertureSize = MEM_SIZE_16M; + if (xf86Verbose) { + ErrorF("%s %s: Using 16 MB aperture @ 0x%08x\n", + XCONFIG_PROBED, + mach64InfoRec.name, mach64ApertureAddr); + } } else { mach64ApertureSize = MEM_SIZE_8M; if (xf86Verbose) { *************** *** 1521,1529 **** mach64InfoRec.name, mach64ApertureAddr); } } } else { ErrorF("To use the Mach64 X server you need to be able to use\n"); ! ErrorF("a 4 or 8 Mb memory aperture.\n"); xf86DisableIOPorts(mach64InfoRec.scrnIndex); return(FALSE); } --- 1600,1617 ---- mach64InfoRec.name, mach64ApertureAddr); } } + + if (pciInfo && pciInfo->RegisterBase) { + mach64RegisterAddr = pciInfo->RegisterBase; + if (xf86Verbose) { + ErrorF("%s %s: Using 4 KB register aperture @ 0x%08x\n", + XCONFIG_PROBED, + mach64InfoRec.name, mach64RegisterAddr); + } + } } else { ErrorF("To use the Mach64 X server you need to be able to use\n"); ! ErrorF("a 4, 8 or 16 Mb memory aperture.\n"); xf86DisableIOPorts(mach64InfoRec.scrnIndex); return(FALSE); } *************** *** 1544,1549 **** --- 1632,1642 ---- mach64InfoRec.name, mach64RamdacTable[i].name); } + ErrorF("%s %s: Ramdac speed: %d MHz\n", + OFLG_ISSET(XCONFIG_DACSPEED, &mach64InfoRec.xconfigFlag) ? + XCONFIG_GIVEN : XCONFIG_PROBED, + mach64InfoRec.name, + mach64InfoRec.maxClock / 1000); } mach64DAC8Bit = ((!OFLG_ISSET(OPTION_DAC_6_BIT, &mach64InfoRec.options) && *************** *** 1649,1655 **** mach64VirtX, mach64VirtY, displayResolution, displayResolution, mach64VirtX)) - return(FALSE); savepScreen = pScreen; --- 1742,1747 ---- *** ./programs/Xserver/hw/xfree86/accel/mach64/mach64.h@@/PUBLIC-LATEST Sat Jul 19 09:42:58 1997 --- xc/programs/Xserver/hw/xfree86/accel/mach64/mach64.h Fri Mar 6 16:32:03 1998 *************** *** 1,6 **** ! /* $XFree86: xc/programs/Xserver/hw/xfree86/accel/mach64/mach64.h,v 3.14 1997/01/18 06:54:36 dawes Exp $ */ /* ! * Copyright 1992,1993,1994,1995,1996 by Kevin E. Martin, Chapel Hill, North Carolina. * * Permission to use, copy, modify, distribute, and sell this software and * its documentation for any purpose is hereby granted without fee, --- 1,6 ---- ! /* $XFree86: xc/programs/Xserver/hw/xfree86/accel/mach64/mach64.h,v 3.14.2.2 1998/02/23 19:06:00 hohndel Exp $ */ /* ! * Copyright 1992,1993,1994,1995,1996,1997 by Kevin E. Martin, Chapel Hill, North Carolina. * * Permission to use, copy, modify, distribute, and sell this software and * its documentation for any purpose is hereby granted without fee, *************** *** 24,30 **** * Modified for the Mach32 by Kevin E. Martin (martin@cs.unc.edu) * Modified for the Mach64 by Kevin E. Martin (martin@cs.unc.edu) */ ! /* $TOG: mach64.h /main/10 1997/07/19 09:42:59 kaleb $ */ #ifndef MACH64 #define MACH64_H --- 24,30 ---- * Modified for the Mach32 by Kevin E. Martin (martin@cs.unc.edu) * Modified for the Mach64 by Kevin E. Martin (martin@cs.unc.edu) */ ! /* $TOG: mach64.h /main/11 1998/03/06 16:33:40 kaleb $ */ #ifndef MACH64 #define MACH64_H *************** *** 86,95 **** --- 86,97 ---- extern int mach64MemCycle; extern Bool mach64IntegratedController; + extern Bool mach64HasDSP; extern unsigned int mach64MemorySize; extern unsigned int mach64ApertureSize; extern unsigned long mach64ApertureAddr; + extern unsigned long mach64RegisterAddr; extern short mach64WeightMask; *** ./programs/Xserver/hw/xfree86/accel/mach64/mach64cmap.c@@/PUBLIC-LATEST Sun Oct 19 15:00:55 1997 --- xc/programs/Xserver/hw/xfree86/accel/mach64/mach64cmap.c Fri Mar 6 16:32:07 1998 *************** *** 30,36 **** * Modified for the Mach64 by Kevin E. Martin (martin@cs.unc.edu) * */ ! /* $TOG: mach64cmap.c /main/10 1997/10/19 15:02:58 kaleb $ */ #include "X.h" #include "Xproto.h" --- 30,36 ---- * Modified for the Mach64 by Kevin E. Martin (martin@cs.unc.edu) * */ ! /* $TOG: mach64cmap.c /main/11 1998/03/06 16:33:45 kaleb $ */ #include "X.h" #include "Xproto.h" *************** *** 79,85 **** int ndef; xColorItem *pdefs; { ! int i,nshift; xColorItem directDefs[256]; extern LUTENTRY mach64savedLUT[256]; --- 79,85 ---- int ndef; xColorItem *pdefs; { ! int i; xColorItem directDefs[256]; extern LUTENTRY mach64savedLUT[256]; *************** *** 91,107 **** pdefs = directDefs; } - nshift = ((mach64DAC8Bit) ? 8 : 10); - for (i = 0; i < ndef; i++) { - unsigned char red, green, blue; /* Return the n most significant bits from a 16-bit value. * For VGA, n = 6. For 8-bit DACs, n = 8. */ ! red = mach64savedLUT[pdefs[i].pixel].r = pdefs[i].red >> nshift; ! green = mach64savedLUT[pdefs[i].pixel].g = pdefs[i].green >> nshift; ! blue = mach64savedLUT[pdefs[i].pixel].b = pdefs[i].blue >> nshift; ! if (xf86VTSema #ifdef XFreeXDGA || ((mach64InfoRec.directMode & XF86DGADirectGraphics) --- 91,109 ---- pdefs = directDefs; } for (i = 0; i < ndef; i++) { /* Return the n most significant bits from a 16-bit value. * For VGA, n = 6. For 8-bit DACs, n = 8. */ ! if (mach64DAC8Bit) { ! mach64savedLUT[pdefs[i].pixel].r = pdefs[i].red >> 8; ! mach64savedLUT[pdefs[i].pixel].g = pdefs[i].green >> 8; ! mach64savedLUT[pdefs[i].pixel].b = pdefs[i].blue >> 8; ! } else { ! mach64savedLUT[pdefs[i].pixel].r = pdefs[i].red >> 10; ! mach64savedLUT[pdefs[i].pixel].g = pdefs[i].green >> 10; ! mach64savedLUT[pdefs[i].pixel].b = pdefs[i].blue >> 10; ! } if (xf86VTSema #ifdef XFreeXDGA || ((mach64InfoRec.directMode & XF86DGADirectGraphics) *************** *** 111,119 **** ) { /* WaitQueue(4); */ outb(ioDAC_REGS, pdefs[i].pixel); ! outb(ioDAC_REGS+1, red); ! outb(ioDAC_REGS+1, green); ! outb(ioDAC_REGS+1, blue); } } checkCursorColor = TRUE; --- 113,127 ---- ) { /* WaitQueue(4); */ outb(ioDAC_REGS, pdefs[i].pixel); ! if (mach64DAC8Bit) { ! outb(ioDAC_REGS+1, pdefs[i].red >> 8); ! outb(ioDAC_REGS+1, pdefs[i].green >> 8); ! outb(ioDAC_REGS+1, pdefs[i].blue >> 8); ! } else { ! outb(ioDAC_REGS+1, pdefs[i].red >> 10); ! outb(ioDAC_REGS+1, pdefs[i].green >> 10); ! outb(ioDAC_REGS+1, pdefs[i].blue >> 10); ! } } } checkCursorColor = TRUE; *************** *** 128,134 **** Pixel * ppix; xrgb * prgb; xColorItem *defs; ! int i,j; if (pmap == oldmap) --- 136,142 ---- Pixel * ppix; xrgb * prgb; xColorItem *defs; ! int i; if (pmap == oldmap) *************** *** 152,194 **** for ( i=0; iclass == GrayScale || pmap->class == PseudoColor) ! { ! for ( i=j=0; ired[i].fShared || pmap->red[i].refcnt != 0) ! { ! defs[j].pixel = i; ! defs[j].flags = DoRed|DoGreen|DoBlue; ! if (pmap->red[i].fShared) ! { ! defs[j].red = pmap->red[i].co.shco.red->color; ! defs[j].green = pmap->red[i].co.shco.green->color; ! defs[j].blue = pmap->red[i].co.shco.blue->color; ! } ! else if (pmap->red[i].refcnt != 0) ! { ! defs[j].red = pmap->red[i].co.local.red; ! defs[j].green = pmap->red[i].co.local.green; ! defs[j].blue = pmap->red[i].co.local.blue; ! } ! j++; ! } ! } ! entries = j; ! } ! else ! { ! QueryColors( pmap, entries, ppix, prgb); ! for ( i=0; iCrtcHTotal > 2048) { isMuxMode = TRUE; crtcRegs->h_total_disp = --- 122,128 ---- int i; int pixel_delay; ! if ((mode->CrtcHTotal > 2048) && (mach64RamdacSubType != DAC_INTERNAL)) { isMuxMode = TRUE; crtcRegs->h_total_disp = *************** *** 342,360 **** { int fifo_depth; ! if (mach64ChipType == MACH64_VT) { if (mach64ChipRev == 0x48) { /* VTA4 */ fifo_depth = mach64FIFOdepthVTA4(cdepth, clock, width); } else { /* VTA3 */ fifo_depth = mach64FIFOdepthVTA3(cdepth, clock, width); } ! } else if (mach64ChipType == MACH64_GT) { fifo_depth = mach64FIFOdepthGT(cdepth, clock, width); ! } else if (mach64ChipType == MACH64_CT && mach64ChipRev == 0x0a) { /* CT-D has a larger FIFO and thus requires special code */ fifo_depth = mach64FIFOdepthCTD(cdepth, clock, width); ! } else if (mach64ChipType == MACH64_CT || ! mach64ChipType == MACH64_ET) { fifo_depth = mach64FIFOdepthCT(cdepth, clock, width); } else { fifo_depth = mach64FIFOdepthDefault(cdepth, clock, width); --- 342,360 ---- { int fifo_depth; ! if (mach64ChipType == MACH64_VT_ID) { if (mach64ChipRev == 0x48) { /* VTA4 */ fifo_depth = mach64FIFOdepthVTA4(cdepth, clock, width); } else { /* VTA3 */ fifo_depth = mach64FIFOdepthVTA3(cdepth, clock, width); } ! } else if (mach64ChipType == MACH64_GT_ID) { fifo_depth = mach64FIFOdepthGT(cdepth, clock, width); ! } else if (mach64ChipType == MACH64_CT_ID && mach64ChipRev == 0x0a) { /* CT-D has a larger FIFO and thus requires special code */ fifo_depth = mach64FIFOdepthCTD(cdepth, clock, width); ! } else if (mach64ChipType == MACH64_CT_ID || ! mach64ChipType == MACH64_ET_ID) { fifo_depth = mach64FIFOdepthCT(cdepth, clock, width); } else { fifo_depth = mach64FIFOdepthDefault(cdepth, clock, width); *************** *** 808,815 **** Q = (mhz100 * M)/(2.0 * R); ! if ((mach64ChipType == MACH64_VT || mach64ChipType == MACH64_GT) && ! (mach64ChipRev & 0x07)) { if (Q > 255) { ErrorF("mach64ProgramClkMach64CT: Warning: Q > 255\n"); Q = 255; --- 808,814 ---- Q = (mhz100 * M)/(2.0 * R); ! if (mach64HasDSP) { if (Q > 255) { ErrorF("mach64ProgramClkMach64CT: Warning: Q > 255\n"); Q = 255; *************** *** 886,893 **** outb(ioCLOCK_CNTL + 1, (PLL_VCLK_CNTL << 2) | PLL_WR_EN); outb(ioCLOCK_CNTL + 2, tmp1 & ~0x04); ! if ((mach64ChipType == MACH64_VT || mach64ChipType == MACH64_GT) && ! (mach64ChipRev & 0x07)) { outb(ioCLOCK_CNTL + 1, PLL_XCLK_CNTL << 2); tmp1 = inb(ioCLOCK_CNTL + 2); outb(ioCLOCK_CNTL + 1, (PLL_XCLK_CNTL << 2) | PLL_WR_EN); --- 885,891 ---- outb(ioCLOCK_CNTL + 1, (PLL_VCLK_CNTL << 2) | PLL_WR_EN); outb(ioCLOCK_CNTL + 2, tmp1 & ~0x04); ! if (mach64HasDSP) { outb(ioCLOCK_CNTL + 1, PLL_XCLK_CNTL << 2); tmp1 = inb(ioCLOCK_CNTL + 2); outb(ioCLOCK_CNTL + 1, (PLL_XCLK_CNTL << 2) | PLL_WR_EN); *************** *** 1138,1145 **** regw(CRTC_GEN_CNTL, crtcGenCntl & ~(CRTC_EXT_EN | CRTC_LOCK_REGS)); /* Set the DSP registers on the VT-B and GT-B */ ! if ((mach64ChipType == MACH64_VT || mach64ChipType == MACH64_GT) && ! (mach64ChipRev & 0x07)) mach64SetDSPRegs(crtcRegs); /* Check to see if we need to program the clock chip */ --- 1136,1142 ---- regw(CRTC_GEN_CNTL, crtcGenCntl & ~(CRTC_EXT_EN | CRTC_LOCK_REGS)); /* Set the DSP registers on the VT-B and GT-B */ ! if (mach64HasDSP) mach64SetDSPRegs(crtcRegs); /* Check to see if we need to program the clock chip */ *************** *** 1202,1208 **** depth = CRTC_PIX_WIDTH_32BPP; } ! if (mach64ChipType == MACH64_CT && mach64ChipRev == 0x0a) { /* CT-D only */ CTD_sharedCntl = regrb(SHARED_CNTL+3) & ~(CTD_FIFO5 >> 24); regwb(SHARED_CNTL+3, CTD_sharedCntl | ((crtcRegs->fifo_v1 & 0x10) >> 4)); --- 1199,1205 ---- depth = CRTC_PIX_WIDTH_32BPP; } ! if (mach64ChipType == MACH64_CT_ID && mach64ChipRev == 0x0a) { /* CT-D only */ CTD_sharedCntl = regrb(SHARED_CNTL+3) & ~(CTD_FIFO5 >> 24); regwb(SHARED_CNTL+3, CTD_sharedCntl | ((crtcRegs->fifo_v1 & 0x10) >> 4)); *************** *** 1303,1310 **** N = inb(ioCLOCK_CNTL + 2); outb(ioCLOCK_CNTL + 1, VCLK_POST_DIV << 2); postDiv = (inb(ioCLOCK_CNTL + 2) >> (2 * i)) & 0x03; ! if ((mach64ChipType == MACH64_VT || mach64ChipType == MACH64_GT) && ! (mach64ChipRev & 0x07)) { outb(ioCLOCK_CNTL + 1, PLL_XCLK_CNTL << 2); if ((inb(ioCLOCK_CNTL + 2) >> (4 + i)) & 0x01) { switch (postDiv) { --- 1300,1306 ---- N = inb(ioCLOCK_CNTL + 2); outb(ioCLOCK_CNTL + 1, VCLK_POST_DIV << 2); postDiv = (inb(ioCLOCK_CNTL + 2) >> (2 * i)) & 0x03; ! if (mach64HasDSP) { outb(ioCLOCK_CNTL + 1, PLL_XCLK_CNTL << 2); if ((inb(ioCLOCK_CNTL + 2) >> (4 + i)) & 0x01) { switch (postDiv) { *************** *** 1353,1358 **** --- 1349,1371 ---- regw(GEN_TEST_CNTL, temp | GUI_ENGINE_ENABLE); + /* On RagePro chips we can enable auto block write and auto fast fill + * modes if block write mode is not initialized by the BIOS. + */ + if (mach64ChipType == MACH64_GB_ID || + mach64ChipType == MACH64_GD_ID || + mach64ChipType == MACH64_GI_ID || + mach64ChipType == MACH64_GP_ID || + mach64ChipType == MACH64_GQ_ID) { + temp = regr(HW_DEBUG); + if (OFLG_ISSET(OPTION_BLOCK_WRITE, &mach64InfoRec.options)) { + temp &= ~(AUTO_FF_DIS | AUTO_BLKWRT_DIS); + } else if (OFLG_ISSET(OPTION_NO_BLOCK_WRITE, &mach64InfoRec.options)) { + temp |= AUTO_FF_DIS | AUTO_BLKWRT_DIS; + } + regw(HW_DEBUG, temp); + } + WaitIdleEmpty(); } *************** *** 1436,1442 **** int i; unsigned long apaddr; unsigned long regpage, regoffset; ! long memsize; if (!mach64VideoMem) { old_CONFIG_CNTL = inw(ioCONFIG_CNTL); --- 1449,1455 ---- int i; unsigned long apaddr; unsigned long regpage, regoffset; ! long memsize, regsize; if (!mach64VideoMem) { old_CONFIG_CNTL = inw(ioCONFIG_CNTL); *************** *** 1444,1455 **** apaddr = mach64ApertureAddr; ! if (mach64ApertureSize == MEM_SIZE_4M) { ! mach64MemRegOffset = 0x3ffc00; ! outw(ioCONFIG_CNTL, ((apaddr/(4*1024*1024)) << 4) | 1); } else { ! mach64MemRegOffset = 0x7ffc00; ! outw(ioCONFIG_CNTL, ((apaddr/(4*1024*1024)) << 4) | 2); } switch(mach64MemorySize) { --- 1457,1483 ---- apaddr = mach64ApertureAddr; ! if (mach64RegisterAddr) { /* Use Auxilliary Register Aperture */ ! mach64MemRegOffset = 0x400; ! ! regpage = mach64RegisterAddr; ! regoffset = mach64MemRegOffset; ! regsize = 0x1000; } else { ! if ((mach64BusType == PCI) && (mach64IntegratedController)) { ! mach64MemRegOffset = 0x7ffc00; ! } else if (mach64ApertureSize == MEM_SIZE_4M) { ! mach64MemRegOffset = 0x3ffc00; ! outw(ioCONFIG_CNTL, ((apaddr/(4*1024*1024)) << 4) | 1); ! } else { ! mach64MemRegOffset = 0x7ffc00; ! outw(ioCONFIG_CNTL, ((apaddr/(4*1024*1024)) << 4) | 2); ! } ! ! regpage = mach64MemRegOffset & XF_PAGE_MASK; ! regoffset = mach64MemRegOffset - regpage; ! regpage += apaddr; ! regsize = PAGE_SIZE; } switch(mach64MemorySize) { *************** *** 1471,1489 **** case MEM_SIZE_8M: memsize = 8 * 1024 * 1024; break; } - regpage = mach64MemRegOffset & XF_PAGE_MASK; - regoffset = mach64MemRegOffset - regpage; - if (!mach64MemRegMap) { mach64MemRegMap = xf86MapVidMem(screen_idx, EXTENDED_REGION, ! (pointer)(apaddr + regpage), ! PAGE_SIZE); mach64MemReg = (pointer)((unsigned long)mach64MemRegMap + regoffset); } - if (!mach64VideoMem) { mach64VideoMem = xf86MapVidMem(screen_idx, LINEAR_REGION, (pointer)apaddr, memsize); --- 1499,1515 ---- case MEM_SIZE_8M: memsize = 8 * 1024 * 1024; break; + case MEM_SIZE_16M: + memsize = 16 * 1024 * 1024; + break; } if (!mach64MemRegMap) { mach64MemRegMap = xf86MapVidMem(screen_idx, EXTENDED_REGION, ! (pointer)(regpage), regsize); mach64MemReg = (pointer)((unsigned long)mach64MemRegMap + regoffset); } if (!mach64VideoMem) { mach64VideoMem = xf86MapVidMem(screen_idx, LINEAR_REGION, (pointer)apaddr, memsize); *************** *** 2251,2258 **** old_PLL[i] = inb(ioCLOCK_CNTL+2); } ! if ((mach64ChipType == MACH64_VT || mach64ChipType == MACH64_GT) && ! (mach64ChipRev & 0x07)) { old_DSP_CONFIG = regr(DSP_CONFIG); old_DSP_ON_OFF = regr(DSP_ON_OFF); } --- 2277,2283 ---- old_PLL[i] = inb(ioCLOCK_CNTL+2); } ! if (mach64HasDSP) { old_DSP_CONFIG = regr(DSP_CONFIG); old_DSP_ON_OFF = regr(DSP_ON_OFF); } *************** *** 2281,2288 **** --- 2306,2329 ---- if (!mach64IntegratedController) regw(MEM_CNTL, old_MEM_CNTL & ~(MEM_BNDRY | MEM_BNDRY_EN)); + WaitQueue(2); + + /* Turn off the memory mapped registers in the frame buffer */ + /* (only when there is an auxilliary register aperture) */ + if (mach64RegisterAddr) + regw(BUS_CNTL, old_BUS_CNTL | BUS_APER_REG_DIS); + + /* Save the HW_DEBUG register if on a RagePro */ + if (mach64ChipType == MACH64_GB_ID || + mach64ChipType == MACH64_GD_ID || + mach64ChipType == MACH64_GI_ID || + mach64ChipType == MACH64_GP_ID || + mach64ChipType == MACH64_GQ_ID) + old_HW_DEBUG = regr(HW_DEBUG); + #ifdef DEBUG ErrorF("MEM_CNTL is 0x%08x\n", regr(MEM_CNTL)); + ErrorF("BUS_CNTL is 0x%08x\n", regr(BUS_CNTL)); #endif WaitQueue(4); *************** *** 2333,2340 **** outb(ioCLOCK_CNTL+2, old_PLL[i]); } ! if ((mach64ChipType == MACH64_VT || mach64ChipType == MACH64_GT) && ! (mach64ChipRev & 0x07)) { regw(DSP_CONFIG, old_DSP_CONFIG); regw(DSP_ON_OFF, old_DSP_ON_OFF); } --- 2374,2380 ---- outb(ioCLOCK_CNTL+2, old_PLL[i]); } ! if (mach64HasDSP) { regw(DSP_CONFIG, old_DSP_CONFIG); regw(DSP_ON_OFF, old_DSP_ON_OFF); } *************** *** 2441,2446 **** --- 2481,2495 ---- regw(CRTC_OFF_PITCH, old_CRTC_OFF_PITCH); regw(DST_OFF_PITCH, old_DST_OFF_PITCH); regw(SRC_OFF_PITCH, old_SRC_OFF_PITCH); + + WaitIdleEmpty(); + /* Restore the HW_DEBUG register if on a RagePro */ + if (mach64ChipType == MACH64_GB_ID || + mach64ChipType == MACH64_GD_ID || + mach64ChipType == MACH64_GI_ID || + mach64ChipType == MACH64_GP_ID || + mach64ChipType == MACH64_GQ_ID) + regw(HW_DEBUG, old_HW_DEBUG); /* Was getting set to 0x00020200 */ regw(CRTC_GEN_CNTL, old_CRTC_GEN_CNTL); *** ./programs/Xserver/hw/xfree86/accel/mach64/regmach64.h@@/PUBLIC-LATEST Sun Aug 10 12:58:54 1997 --- xc/programs/Xserver/hw/xfree86/accel/mach64/regmach64.h Fri Mar 6 16:32:17 1998 *************** *** 1,6 **** ! /* $XFree86: xc/programs/Xserver/hw/xfree86/accel/mach64/regmach64.h,v 3.15.2.2 1997/07/27 02:41:12 dawes Exp $ */ /* ! * Copyright 1992,1993,1994,1995,1996 by Kevin E. Martin, Chapel Hill, North Carolina. * * Permission to use, copy, modify, distribute, and sell this software and * its documentation for any purpose is hereby granted without fee, --- 1,6 ---- ! /* $XFree86: xc/programs/Xserver/hw/xfree86/accel/mach64/regmach64.h,v 3.15.2.3 1998/01/18 10:35:24 hohndel Exp $ */ /* ! * Copyright 1992,1993,1994,1995,1996,1997 by Kevin E. Martin, Chapel Hill, North Carolina. * * Permission to use, copy, modify, distribute, and sell this software and * its documentation for any purpose is hereby granted without fee, *************** *** 25,31 **** * Modified for the Mach32 by Kevin E. Martin (martin@cs.unc.edu) * Modified for the Mach64 by Kevin E. Martin (martin@cs.unc.edu) */ ! /* $TOG: regmach64.h /main/15 1997/08/10 12:57:30 kaleb $ */ #ifndef REGMACH64_H #define REGMACH64_H --- 25,31 ---- * Modified for the Mach32 by Kevin E. Martin (martin@cs.unc.edu) * Modified for the Mach64 by Kevin E. Martin (martin@cs.unc.edu) */ ! /* $TOG: regmach64.h /main/16 1998/03/06 16:33:55 kaleb $ */ #ifndef REGMACH64_H #define REGMACH64_H *************** *** 86,91 **** --- 86,93 ---- #define CUR_HORZ_VERT_POSN 0x006C /* Dword offset 1B */ #define CUR_HORZ_VERT_OFF 0x0070 /* Dword offset 1C */ + #define HW_DEBUG 0x007C /* Dword offset 1F */ + #define SCRATCH_REG0 0x0080 /* Dword offset 20 */ #define SCRATCH_REG1 0x0084 /* Dword offset 21 */ *************** *** 268,276 **** --- 270,284 ---- /* Mach64 engine bit constants - these are typically ORed together */ + /* HW_DEBUG register constants */ + /* For RagePro only... */ + #define AUTO_FF_DIS 0x000001000 + #define AUTO_BLKWRT_DIS 0x000002000 + /* BUS_CNTL register constants */ #define BUS_FIFO_ERR_ACK 0x00200000 #define BUS_HOST_ERR_ACK 0x00800000 + #define BUS_APER_REG_DIS 0x00000010 /* GEN_TEST_CNTL register constants */ #define GEN_OVR_OUTPUT_EN 0x20 *************** *** 404,414 **** --- 412,424 ---- #define MEM_SIZE_4M 0x00000003 #define MEM_SIZE_6M 0x00000004 #define MEM_SIZE_8M 0x00000005 + #define MEM_SIZE_16M 0x00000006 #define MEM_SIZE_ALIAS_GTB 0x0000000F #define MEM_SIZE_2M_GTB 0x00000003 #define MEM_SIZE_4M_GTB 0x00000007 #define MEM_SIZE_6M_GTB 0x00000009 #define MEM_SIZE_8M_GTB 0x0000000B + #define MEM_SIZE_16M_GTB 0x0000000F #define MEM_BNDRY 0x00030000 #define MEM_BNDRY_0K 0x00000000 #define MEM_BNDRY_256K 0x00010000 *************** *** 418,432 **** /* ATI PCI constants */ #define PCI_ATI_VENDOR_ID 0x1002 ! #define PCI_MACH64_GX 0x4758 ! #define PCI_MACH64_CX 0x4358 ! #define PCI_MACH64_CT 0x4354 ! #define PCI_MACH64_ET 0x4554 ! #define PCI_MACH64_VT 0x5654 ! #define PCI_MACH64_VU 0x5655 ! #define PCI_MACH64_GT 0x4754 ! #define PCI_MACH64_GU 0x4755 ! #define PCI_MACH64_GP 0x4750 /* CONFIG_CHIP_ID register constants */ #define CFG_CHIP_TYPE 0x0000FFFF --- 428,446 ---- /* ATI PCI constants */ #define PCI_ATI_VENDOR_ID 0x1002 ! #define PCI_MACH64_GX_ID 0x4758 ! #define PCI_MACH64_CX_ID 0x4358 ! #define PCI_MACH64_CT_ID 0x4354 ! #define PCI_MACH64_ET_ID 0x4554 ! #define PCI_MACH64_VT_ID 0x5654 ! #define PCI_MACH64_VU_ID 0x5655 ! #define PCI_MACH64_GT_ID 0x4754 ! #define PCI_MACH64_GU_ID 0x4755 ! #define PCI_MACH64_GB_ID 0x4742 ! #define PCI_MACH64_GD_ID 0x4744 ! #define PCI_MACH64_GI_ID 0x4749 ! #define PCI_MACH64_GP_ID 0x4750 ! #define PCI_MACH64_GQ_ID 0x4751 /* CONFIG_CHIP_ID register constants */ #define CFG_CHIP_TYPE 0x0000FFFF *************** *** 445,460 **** #define MACH64_VU_ID 0x5655 #define MACH64_GT_ID 0x4754 #define MACH64_GU_ID 0x4755 #define MACH64_GP_ID 0x4750 ! ! /* Mach64 chip types */ ! #define MACH64_UNKNOWN 0 ! #define MACH64_GX 1 ! #define MACH64_CX 2 ! #define MACH64_CT 3 ! #define MACH64_ET 4 ! #define MACH64_VT 5 ! #define MACH64_GT 6 /* DST_CNTL register constants */ #define DST_X_RIGHT_TO_LEFT 0 --- 459,470 ---- #define MACH64_VU_ID 0x5655 #define MACH64_GT_ID 0x4754 #define MACH64_GU_ID 0x4755 + #define MACH64_GB_ID 0x4742 + #define MACH64_GD_ID 0x4744 + #define MACH64_GI_ID 0x4749 #define MACH64_GP_ID 0x4750 ! #define MACH64_GQ_ID 0x4751 ! #define MACH64_UNKNOWN_ID 0x0000 /* DST_CNTL register constants */ #define DST_X_RIGHT_TO_LEFT 0 *** ./programs/Xserver/hw/xfree86/accel/mach8/mach8.c@@/PUBLIC-LATEST Sat Jul 19 09:45:17 1997 --- xc/programs/Xserver/hw/xfree86/accel/mach8/mach8.c Fri Mar 6 16:32:22 1998 *************** *** 1,4 **** ! /* $XFree86: xc/programs/Xserver/hw/xfree86/accel/mach8/mach8.c,v 3.34.2.3 1997/05/11 02:56:08 dawes Exp $ */ /* * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany. * --- 1,4 ---- ! /* $XFree86: xc/programs/Xserver/hw/xfree86/accel/mach8/mach8.c,v 3.34.2.4 1998/02/07 10:05:11 hohndel Exp $ */ /* * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany. * *************** *** 29,35 **** * and Tiago Gons (tiago@comosjn.hobby.nl) * */ ! /* $TOG: mach8.c /main/18 1997/07/19 09:45:18 kaleb $ */ #include "X.h" --- 29,35 ---- * and Tiago Gons (tiago@comosjn.hobby.nl) * */ ! /* $TOG: mach8.c /main/19 1998/03/06 16:34:00 kaleb $ */ #include "X.h" *************** *** 132,138 **** 0, /* int textClockFreq */ NULL, /* char* DCConfig */ NULL, /* char* DCOptions */ ! 0 /* int MemClk */ #ifdef XFreeXDGA ,0, /* int directMode */ NULL, /* Set Vid Page */ --- 132,139 ---- 0, /* int textClockFreq */ NULL, /* char* DCConfig */ NULL, /* char* DCOptions */ ! 0, /* int MemClk */ ! 0 /* int LCDClk */ #ifdef XFreeXDGA ,0, /* int directMode */ NULL, /* Set Vid Page */ *** ./programs/Xserver/hw/xfree86/accel/mach8/mach8cmap.c@@/PUBLIC-LATEST Sun Oct 19 15:00:32 1997 --- xc/programs/Xserver/hw/xfree86/accel/mach8/mach8cmap.c Fri Mar 6 16:32:28 1998 *************** *** 26,32 **** * Further modifications by Tiago Gons (tiago@comosjn.hobby.nl) * */ ! /* $TOG: mach8cmap.c /main/5 1997/10/19 15:02:35 kaleb $ */ #include "X.h" --- 26,32 ---- * Further modifications by Tiago Gons (tiago@comosjn.hobby.nl) * */ ! /* $TOG: mach8cmap.c /main/6 1998/03/06 16:34:05 kaleb $ */ #include "X.h" *************** *** 94,109 **** } for (i = 0; i < ndef; i++) { ! unsigned char red, green, blue; ! ! red = currentmach8dac[pdefs[i].pixel].r = pdefs[i].red >> 10; ! green = currentmach8dac[pdefs[i].pixel].g = pdefs[i].green >> 10; ! blue = currentmach8dac[pdefs[i].pixel].b = pdefs[i].blue >> 10; if (xf86VTSema) { outb(DAC_W_INDEX, pdefs[i].pixel); ! outb(DAC_DATA, red); ! outb(DAC_DATA, green); ! outb(DAC_DATA, blue); } } } --- 94,107 ---- } for (i = 0; i < ndef; i++) { ! currentmach8dac[pdefs[i].pixel].r = pdefs[i].red >> 10; ! currentmach8dac[pdefs[i].pixel].g = pdefs[i].green >> 10; ! currentmach8dac[pdefs[i].pixel].b = pdefs[i].blue >> 10; if (xf86VTSema) { outb(DAC_W_INDEX, pdefs[i].pixel); ! outb(DAC_DATA, pdefs[i].red >> 10); ! outb(DAC_DATA, pdefs[i].green >> 10); ! outb(DAC_DATA, pdefs[i].blue >> 10); } } } *************** *** 118,124 **** Pixel * ppix; xrgb * prgb; xColorItem *defs; ! int i,j; if (pmap == oldmap) --- 116,122 ---- Pixel * ppix; xrgb * prgb; xColorItem *defs; ! int i; if (pmap == oldmap) *************** *** 142,184 **** for ( i=0; iclass == GrayScale || pmap->class == PseudoColor) ! { ! for ( i=j=0; ired[i].fShared || pmap->red[i].refcnt != 0) ! { ! defs[j].pixel = i; ! defs[j].flags = DoRed|DoGreen|DoBlue; ! if (pmap->red[i].fShared) ! { ! defs[j].red = pmap->red[i].co.shco.red->color; ! defs[j].green = pmap->red[i].co.shco.green->color; ! defs[j].blue = pmap->red[i].co.shco.blue->color; ! } ! else if (pmap->red[i].refcnt != 0) ! { ! defs[j].red = pmap->red[i].co.local.red; ! defs[j].green = pmap->red[i].co.local.green; ! defs[j].blue = pmap->red[i].co.local.blue; ! } ! j++; ! } ! } ! entries = j; ! } ! else ! { ! QueryColors( pmap, entries, ppix, prgb); ! for ( i=0; i --- 1,4 ---- ! /* $XFree86: xc/programs/Xserver/hw/xfree86/accel/p9000/p9000.c,v 3.44.2.7 1998/02/07 10:05:11 hohndel Exp $ */ /* * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany. * Copyright 1994 by Erik Nygren *************** *** 33,39 **** * Bank switching code for P9000 by David Moews (dmoews@xraysgi.ims.uconn.edu) * */ ! /* $TOG: p9000.c /main/23 1997/11/16 08:37:12 kaleb $ */ #define NEED_EVENTS #include "X.h" --- 33,39 ---- * Bank switching code for P9000 by David Moews (dmoews@xraysgi.ims.uconn.edu) * */ ! /* $TOG: p9000.c /main/25 1998/03/07 14:24:51 kaleb $ */ #define NEED_EVENTS #include "X.h" *************** *** 151,157 **** 0, /* int textClockFreq */ NULL, /* char* DCConfig */ NULL, /* char* DCOptions */ ! 0 /* int MemClk */ #ifdef XFreeXDGA /* Note that the double buffered support is * a hack in the P9000 server. See the README.P9000 --- 151,158 ---- 0, /* int textClockFreq */ NULL, /* char* DCConfig */ NULL, /* char* DCOptions */ ! 0, /* int MemClk */ ! 0 /* int LCDClk */ #ifdef XFreeXDGA /* Note that the double buffered support is * a hack in the P9000 server. See the README.P9000 *** ./programs/Xserver/hw/xfree86/accel/p9000/p9000.h@@/PUBLIC-LATEST Sat Jul 19 17:34:04 1997 --- xc/programs/Xserver/hw/xfree86/accel/p9000/p9000.h Fri Mar 6 16:32:38 1998 *************** *** 26,32 **** * Additional changes by Chris Mason * */ ! /* $TOG: p9000.h /main/11 1997/07/19 17:34:06 kaleb $ */ #ifndef P9000_H #define P9000_H --- 26,32 ---- * Additional changes by Chris Mason * */ ! /* $TOG: p9000.h /main/12 1998/03/06 16:34:15 kaleb $ */ #ifndef P9000_H #define P9000_H *************** *** 184,194 **** --- 184,196 ---- #endif ); + #ifdef DPMSExtension extern void p9000DPMSSet( #if NeedFunctionPrototypes int PowerManagementMode #endif ); + #endif extern Bool p9000CloseScreen( #if NeedFunctionPrototypes *** ./programs/Xserver/hw/xfree86/accel/p9000/p9000cmap.c@@/PUBLIC-LATEST Sun Oct 19 15:00:51 1997 --- xc/programs/Xserver/hw/xfree86/accel/p9000/p9000cmap.c Fri Mar 6 16:32:42 1998 *************** *** 27,33 **** * Modified for the P9000 by Erik Nygren (nygren@mit.edu) * */ ! /* $TOG: p9000cmap.c /main/11 1997/10/19 15:02:55 kaleb $ */ /* Note that the outb's and inb's in here should be changed to use the * p9000OutBtReg, etc routines. It's not needed yet because --- 27,33 ---- * Modified for the P9000 by Erik Nygren (nygren@mit.edu) * */ ! /* $TOG: p9000cmap.c /main/12 1998/03/06 16:34:20 kaleb $ */ /* Note that the outb's and inb's in here should be changed to use the * p9000OutBtReg, etc routines. It's not needed yet because *************** *** 153,163 **** } for (i = 0; i < ndef; i++) { ! unsigned char red, green, blue; ! ! red = currentp9000dac[pdefs[i].pixel].r = pdefs[i].red >> 8; ! green = currentp9000dac[pdefs[i].pixel].g = pdefs[i].green >> 8; ! blue = currentp9000dac[pdefs[i].pixel].b = pdefs[i].blue >> 8; if (xf86VTSema #ifdef XFreeXDGA || ((p9000InfoRec.directMode & XF86DGADirectGraphics) --- 153,161 ---- } for (i = 0; i < ndef; i++) { ! currentp9000dac[pdefs[i].pixel].r = pdefs[i].red >> 8; ! currentp9000dac[pdefs[i].pixel].g = pdefs[i].green >> 8; ! currentp9000dac[pdefs[i].pixel].b = pdefs[i].blue >> 8; if (xf86VTSema #ifdef XFreeXDGA || ((p9000InfoRec.directMode & XF86DGADirectGraphics) *************** *** 166,174 **** #endif ) { outb(BT_WRITE_ADDR, pdefs[i].pixel); ! outb(BT_RAMDAC_DATA, red); ! outb(BT_RAMDAC_DATA, green); ! outb(BT_RAMDAC_DATA, blue); } } --- 164,172 ---- #endif ) { outb(BT_WRITE_ADDR, pdefs[i].pixel); ! outb(BT_RAMDAC_DATA, pdefs[i].red >> 8); ! outb(BT_RAMDAC_DATA, pdefs[i].green >> 8); ! outb(BT_RAMDAC_DATA, pdefs[i].blue >> 8); } } *************** *** 184,190 **** Pixel * ppix; xrgb * prgb; xColorItem *defs; ! int i,j; if (pmap == oldmap) --- 182,188 ---- Pixel * ppix; xrgb * prgb; xColorItem *defs; ! int i; if (pmap == oldmap) *************** *** 208,250 **** for ( i=0; iclass == GrayScale || pmap->class == PseudoColor) ! { ! for ( i=j=0; ired[i].fShared || pmap->red[i].refcnt != 0) ! { ! defs[j].pixel = i; ! defs[j].flags = DoRed|DoGreen|DoBlue; ! if (pmap->red[i].fShared) ! { ! defs[j].red = pmap->red[i].co.shco.red->color; ! defs[j].green = pmap->red[i].co.shco.green->color; ! defs[j].blue = pmap->red[i].co.shco.blue->color; ! } ! else if (pmap->red[i].refcnt != 0) ! { ! defs[j].red = pmap->red[i].co.local.red; ! defs[j].green = pmap->red[i].co.local.green; ! defs[j].blue = pmap->red[i].co.local.blue; ! } ! j++; ! } ! } ! entries = j; ! } ! else ! { ! QueryColors( pmap, entries, ppix, prgb); ! for ( i=0; i_vendor == PCI_VENDOR_SIGMADESIGNS || + pcrp->_vendor == PCI_VENDOR_INTERGRAPHICS) { + char *vendor, chip[80]; + if (pcrp->_vendor == PCI_VENDOR_SIGMADESIGNS) { + vendor = "Sigma Designs"; + if (pcrp->_device == PCI_CHIP_SD_REALMAGIG64GX) + strcpy(chip,"REALmagic64/GX (SD 6425) chip"); + else + sprintf(chip,"unknown chip (chip_id 0x%x)",pcrp->_device); + } + else { + vendor = "Intergraphics"; + if (pcrp->_vendor == PCI_CHIP_INTERG_1680) + strcpy(chip,"IGA-1680 chip"); + else if (pcrp->_vendor == PCI_CHIP_INTERG_1682) + strcpy(chip,"IGA-1682 chip"); + else + sprintf(chip,"unknown chip (chip_id 0x%x)",pcrp->_device); + } + ErrorF("\n%s %s: WARNING: %s %s detected!\n" + "\tNote: this chip is not a product of S3, Inc., and it is not\n" + "\tcompatible with the XFree86 S3 drivers. We understand that\n" + "\tsome video cards are being sold with these chips relabeled\n" + "\tas S3 Inc. chips, including S3's logo. They are NOT S3 chips.\n" + "\tPlease see http://www.s3.com\n\n" + ,XCONFIG_PROBED, s3InfoRec.name); + } + if (pcrp->_vendor == PCI_S3_VENDOR_ID) { found = TRUE; switch (pcrp->_device) { *************** *** 856,864 **** } else if (S3_TRIO32_SERIES(s3ChipId)) { chipname = "Trio32"; } else if (S3_TRIO64UVP_SERIES(s3ChipId)) { ! chipname = "Trio64UV+ (preliminary support; please report)"; } else if (S3_AURORA64VP_SERIES(s3ChipId)) { ! chipname = "Aurora64V+ (preliminary support; please report)"; } else if (S3_TRIO64V_SERIES(s3ChipId /* , s3ChipRev */)) { chipname = "Trio64V+"; } else if (S3_TRIO64V2_SERIES(s3ChipId)) { --- 882,890 ---- } else if (S3_TRIO32_SERIES(s3ChipId)) { chipname = "Trio32"; } else if (S3_TRIO64UVP_SERIES(s3ChipId)) { ! chipname = "Trio64UV+"; } else if (S3_AURORA64VP_SERIES(s3ChipId)) { ! chipname = "Aurora64V+"; } else if (S3_TRIO64V_SERIES(s3ChipId /* , s3ChipRev */)) { chipname = "Trio64V+"; } else if (S3_TRIO64V2_SERIES(s3ChipId)) { *************** *** 1008,1013 **** --- 1034,1042 ---- OFLG_SET(OPTION_MIRO_80SV, &validOptions); OFLG_SET(OPTION_NO_PCI_DISC, &validOptions); OFLG_SET(OPTION_NO_SPLIT_XFER, &validOptions); + if (S3_AURORA64VP_SERIES(s3ChipId)) + OFLG_SET(OPTION_LCD_CENTER, &validOptions); + xf86VerifyOptions(&validOptions, &s3InfoRec); #ifdef __alpha__ *** ./programs/Xserver/hw/xfree86/accel/s3/s3Cursor.h@@/PUBLIC-LATEST Sat Jul 19 09:52:08 1997 --- xc/programs/Xserver/hw/xfree86/accel/s3/s3Cursor.h Fri Mar 6 16:33:06 1998 *************** *** 1,9 **** ! /* $TOG: s3Cursor.h /main/5 1997/07/19 09:52:09 kaleb $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/accel/s3/s3Cursor.h,v 3.0 1996/08/20 12:26:54 dawes Exp $ */ extern Bool s3BlockCursor; extern Bool s3ReloadCursor; --- 1,9 ---- ! /* $TOG: s3Cursor.h /main/6 1998/03/06 16:34:44 kaleb $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/accel/s3/s3Cursor.h,v 3.2 1996/12/27 06:56:20 dawes Exp $ */ extern Bool s3BlockCursor; extern Bool s3ReloadCursor; *** ./programs/Xserver/hw/xfree86/accel/s3/s3cmap.c@@/PUBLIC-LATEST Sun Oct 19 15:00:35 1997 --- xc/programs/Xserver/hw/xfree86/accel/s3/s3cmap.c Fri Mar 6 16:33:10 1998 *************** *** 27,33 **** /* * Modified by Amancio Hasty and Jon Tombs */ ! /* $TOG: s3cmap.c /main/17 1997/10/19 15:02:39 kaleb $ */ #include "X.h" --- 27,33 ---- /* * Modified by Amancio Hasty and Jon Tombs */ ! /* $TOG: s3cmap.c /main/18 1998/03/06 16:34:48 kaleb $ */ #include "X.h" *************** *** 196,202 **** Pixel *ppix; xrgb *prgb; xColorItem *defs; ! int i,j; if (pmap == oldmap) return; --- 196,202 ---- Pixel *ppix; xrgb *prgb; xColorItem *defs; ! int i; if (pmap == oldmap) return; *************** *** 220,263 **** for (i = 0; i < entries; i++) ppix[i] = i; ! if (pmap->class == GrayScale || pmap->class == PseudoColor) ! { ! for ( i=j=0; ired[i].fShared || pmap->red[i].refcnt != 0) ! { ! defs[j].pixel = i; ! defs[j].flags = DoRed|DoGreen|DoBlue; ! if (pmap->red[i].fShared) ! { ! defs[j].red = pmap->red[i].co.shco.red->color; ! defs[j].green = pmap->red[i].co.shco.green->color; ! defs[j].blue = pmap->red[i].co.shco.blue->color; ! } ! else if (pmap->red[i].refcnt != 0) ! { ! defs[j].red = pmap->red[i].co.local.red; ! defs[j].green = pmap->red[i].co.local.green; ! defs[j].blue = pmap->red[i].co.local.blue; ! } ! j++; ! } ! } ! entries = j; ! } ! else ! { ! QueryColors( pmap, entries, ppix, prgb); ! for ( i=0; i>1); /* for 16/32 bpp */ + else if (S3_AURORA64VP_SERIES(s3ChipId)) + pixMuxShift = 0; else if (S3_TRIOxx_SERIES(s3ChipId)) pixMuxShift = -(s3Bpp == 2); else if (S3_x64_SERIES(s3ChipId)) /* XXXX Better to test the DAC type? */ *************** *** 767,774 **** outb(vgaCRReg, 0x35 | pci_disc); } ! outb(vgaCRIndex, 0x3b); ! outb(vgaCRReg, (new->CRTC[0] + new->CRTC[4] + 1) / 2); outb(vgaCRIndex, 0x3c); outb(vgaCRReg, new->CRTC[0]/2); /* Interlace mode frame offset */ --- 769,797 ---- outb(vgaCRReg, 0x35 | pci_disc); } ! if (S3_AURORA64VP_SERIES(s3ChipId)) { ! outb(0x3c4, 0x08); /* unlock extended SEQ regs */ ! outb(0x3c5, 0x06); ! if (OFLG_ISSET(OPTION_LCD_CENTER, &s3InfoRec.options)) { ! outb(0x3c4, 0x54); outb(0x3c5, 0x10); ! outb(0x3c4, 0x55); outb(0x3c5, 0x00); ! outb(0x3c4, 0x56); outb(0x3c5, 0x1c); ! outb(0x3c4, 0x57); outb(0x3c5, 0x00); ! } ! else { ! outb(0x3c4, 0x54); outb(0x3c5, 0x1f); ! outb(0x3c4, 0x55); outb(0x3c5, 0x1f); ! outb(0x3c4, 0x56); outb(0x3c5, 0x1f); ! outb(0x3c4, 0x57); outb(0x3c5, 0xff); ! } ! outb(0x3c4, 0x08); /* lock extended SEQ regs */ ! outb(0x3c5, 0x00); ! } ! ! if (!S3_AURORA64VP_SERIES(s3ChipId)) { ! outb(vgaCRIndex, 0x3b); ! outb(vgaCRReg, (new->CRTC[0] + new->CRTC[4] + 1) / 2); ! } outb(vgaCRIndex, 0x3c); outb(vgaCRReg, new->CRTC[0]/2); /* Interlace mode frame offset */ *************** *** 1078,1085 **** else itmp = new->CRTC[0]+ ((i&0x01)<<8) + 1; } ! outb(vgaCRReg, itmp & 0xff); ! i |= (itmp&0x100) >> 2; outb(vgaCRIndex, 0x3c); outb(vgaCRReg, (new->CRTC[0] + ((i&0x01)<<8)) /2); /* Interlace mode frame offset */ --- 1101,1114 ---- else itmp = new->CRTC[0]+ ((i&0x01)<<8) + 1; } ! if (S3_AURORA64VP_SERIES(s3ChipId)) { ! outb(vgaCRReg, 0); ! i &= ~0x40; ! } ! else { ! outb(vgaCRReg, itmp & 0xff); ! i |= (itmp&0x100) >> 2; ! } outb(vgaCRIndex, 0x3c); outb(vgaCRReg, (new->CRTC[0] + ((i&0x01)<<8)) /2); /* Interlace mode frame offset */ *** ./programs/Xserver/hw/xfree86/accel/s3/s3misc.c@@/PUBLIC-LATEST Sat Jul 19 09:54:13 1997 --- xc/programs/Xserver/hw/xfree86/accel/s3/s3misc.c Fri Mar 6 16:33:21 1998 *************** *** 1,4 **** ! /* $XFree86: xc/programs/Xserver/hw/xfree86/accel/s3/s3misc.c,v 3.68.2.2 1997/05/19 08:06:54 dawes Exp $ */ /* * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany. * --- 1,4 ---- ! /* $XFree86: xc/programs/Xserver/hw/xfree86/accel/s3/s3misc.c,v 3.68.2.3 1998/02/07 10:05:15 hohndel Exp $ */ /* * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany. * *************** *** 30,36 **** * Modified by Amancio Hasty and Jon Tombs * */ ! /* $TOG: s3misc.c /main/37 1997/07/19 09:54:14 kaleb $ */ #include "cfb.h" --- 30,36 ---- * Modified by Amancio Hasty and Jon Tombs * */ ! /* $TOG: s3misc.c /main/38 1998/03/06 16:34:58 kaleb $ */ #include "cfb.h" *************** *** 988,993 **** --- 988,994 ---- Bool on; { unsigned char scrn; + static unsigned char saved_sr31=0x10; if (on) SetTimeSinceLastInputEvent(); *************** *** 1008,1013 **** --- 1009,1026 ---- outw(0x3C4, 0x0100); /* syncronous reset */ outw(0x3C4, (scrn << 8) | 0x01); /* change mode */ outw(0x3C4, 0x0300); /* end reset */ + + if (OFLG_ISSET(CLOCK_OPTION_S3AURORA, &s3InfoRec.clockOptions)) { + outb(0x3c4, 0x08); /* unlock extended SEQ regs */ + outb(0x3c5, 0x06); + outb(0x3c4, 0x31); + if (on) + outb(0x3c5, saved_sr31); /* LCD on */ + else { + saved_sr31 = inb(0x3c5); + outb(0x3c5, saved_sr31 & ~0x10); /* LCD off */ + } + } } return (TRUE); } *************** *** 1145,1150 **** --- 1158,1170 ---- Base &= ~a; } } + + #ifdef XFreeXDGA + if (s3InfoRec.directMode & XF86DGADirectGraphics) { + /* unlock ext. registers */ + s3Unlock(); + } + #endif outb(vgaCRIndex, 0x31); outb(vgaCRReg, ((Base & 0x030000) >> 12) | s3Port31); *** ./programs/Xserver/hw/xfree86/accel/s3_virge/regs3v.h@@/PUBLIC-LATEST Sat Jul 19 09:55:33 1997 --- xc/programs/Xserver/hw/xfree86/accel/s3_virge/regs3v.h Fri Mar 6 16:33:39 1998 *************** *** 1,4 **** ! /* $XFree86: xc/programs/Xserver/hw/xfree86/accel/s3_virge/regs3v.h,v 3.4.2.1 1997/05/06 13:26:29 dawes Exp $ */ /* * regs3v.h * --- 1,4 ---- ! /* $XFree86: xc/programs/Xserver/hw/xfree86/accel/s3_virge/regs3v.h,v 3.4.2.2 1998/01/31 14:23:21 hohndel Exp $ */ /* * regs3v.h * *************** *** 19,25 **** * PERFORMANCE OF THIS SOFTWARE. * */ ! /* $TOG: regs3v.h /main/7 1997/07/19 09:55:34 kaleb $ */ #ifndef _REGS3V_H #define _REGS3V_H --- 19,25 ---- * PERFORMANCE OF THIS SOFTWARE. * */ ! /* $TOG: regs3v.h /main/8 1998/03/06 16:35:17 kaleb $ */ #ifndef _REGS3V_H #define _REGS3V_H *************** *** 41,47 **** #define S3_ViRGE_SERIES(chip) (chip==PCI_ViRGE) #define S3_ViRGE_VX_SERIES(chip) (chip==PCI_ViRGE_VX) ! #define S3_ViRGE_DXGX_SERIES(chip) (chip==PCI_ViRGE_DXGX) #define S3_ANY_ViRGE_SERIES(chip) ( S3_ViRGE_SERIES(chip) \ || S3_ViRGE_VX_SERIES(chip) \ || S3_ViRGE_DXGX_SERIES(chip)) --- 41,49 ---- #define S3_ViRGE_SERIES(chip) (chip==PCI_ViRGE) #define S3_ViRGE_VX_SERIES(chip) (chip==PCI_ViRGE_VX) ! #define S3_ViRGE_DXGX_SERIES(chip) (chip==PCI_ViRGE_DXGX || chip==PCI_ViRGE_GX2 || chip==PCI_ViRGE_MX) ! #define S3_ViRGE_GX2_SERIES(chip) (chip==PCI_ViRGE_GX2) ! #define S3_ViRGE_MX_SERIES(chip) (chip==PCI_ViRGE_MX) #define S3_ANY_ViRGE_SERIES(chip) ( S3_ViRGE_SERIES(chip) \ || S3_ViRGE_VX_SERIES(chip) \ || S3_ViRGE_DXGX_SERIES(chip)) *************** *** 52,57 **** --- 54,61 ---- #define PCI_ViRGE 0x5631 #define PCI_ViRGE_VX 0x883D #define PCI_ViRGE_DXGX 0x8A01 + #define PCI_ViRGE_GX2 0x8A10 + #define PCI_ViRGE_MX 0x8C01 /* Chip tags */ #define S3_UNKNOWN 0 *************** *** 58,63 **** --- 62,69 ---- #define S3_ViRGE 1 #define S3_ViRGE_VX 2 #define S3_ViRGE_DXGX 3 + #define S3_ViRGE_GX2 4 + #define S3_ViRGE_MX 5 /* VESA Approved Register Definitions */ #define DAC_MASK 0x03c6 *** ./programs/Xserver/hw/xfree86/accel/s3_virge/s3.c@@/PUBLIC-LATEST Sun Nov 16 08:33:44 1997 --- xc/programs/Xserver/hw/xfree86/accel/s3_virge/s3.c Sat Mar 7 14:18:00 1998 *************** *** 1,4 **** ! /* $XFree86: xc/programs/Xserver/hw/xfree86/accel/s3_virge/s3.c,v 3.14.2.8 1997/06/01 12:33:31 dawes Exp $ */ /* * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany. * --- 1,4 ---- ! /* $XFree86: xc/programs/Xserver/hw/xfree86/accel/s3_virge/s3.c,v 3.14.2.10 1998/02/07 10:05:18 hohndel Exp $ */ /* * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany. * *************** *** 30,36 **** * Modified by Amancio Hasty and Jon Tombs * */ ! /* $TOG: s3.c /main/12 1997/11/16 08:37:16 kaleb $ */ #include "misc.h" #include "cfb.h" --- 30,36 ---- * Modified by Amancio Hasty and Jon Tombs * */ ! /* $TOG: s3.c /main/14 1998/03/07 14:19:42 kaleb $ */ #include "misc.h" #include "cfb.h" *************** *** 137,143 **** 0, /* int textClockFreq */ NULL, /* char* DCConfig */ NULL, /* char* DCOptions */ ! 0 /* int MemClk */ #ifdef XFreeXDGA ,0, /* int directMode */ s3SetVidPage, /* Set Vid Page */ --- 137,144 ---- 0, /* int textClockFreq */ NULL, /* char* DCConfig */ NULL, /* char* DCOptions */ ! 0, /* int MemClk */ ! 0 /* int LCDClk */ #ifdef XFreeXDGA ,0, /* int directMode */ s3SetVidPage, /* Set Vid Page */ *************** *** 169,174 **** --- 170,177 ---- { S3_ViRGE, "ViRGE" }, { S3_ViRGE_VX, "ViRGE/VX" }, { S3_ViRGE_DXGX, "ViRGE/DX or /GX" }, + { S3_ViRGE_GX2, "ViRGE/GX2" }, + { S3_ViRGE_MX, "ViRGE/MX" }, { -1, "" }, }; *************** *** 351,356 **** --- 354,365 ---- case PCI_ViRGE_DXGX: info.ChipType = S3_ViRGE_DXGX; break; + case PCI_ViRGE_GX2: + info.ChipType = S3_ViRGE_GX2; + break; + case PCI_ViRGE_MX: + info.ChipType = S3_ViRGE_MX; + break; default: info.ChipType = S3_UNKNOWN; info.DevID = pcrp->_device; *************** *** 790,795 **** --- 799,810 ---- if (S3_ViRGE_SERIES(s3ChipId)) { chipname = "ViRGE"; } + else if (S3_ViRGE_GX2_SERIES(s3ChipId)) { + chipname = "ViRGE/GX"; + } + else if (S3_ViRGE_MX_SERIES(s3ChipId)) { + chipname = "ViRGE/MX"; + } else if (S3_ViRGE_DXGX_SERIES(s3ChipId)) { outb(vgaCRIndex, 0x39); outb(vgaCRReg, 0xa5); *************** *** 838,843 **** --- 853,868 ---- break; } s3InfoRec.videoRam -= MemOffScreen; + } + else if (S3_ViRGE_GX2_SERIES(s3ChipId) || S3_ViRGE_MX_SERIES(s3ChipId)) { + switch((config & 0xC0) >> 6) { + case 1: + s3InfoRec.videoRam = 4 * 1024; + break; + case 3: + s3InfoRec.videoRam = 2 * 1024; + break; + } } else { switch((config & 0xE0) >> 5) { *** ./programs/Xserver/hw/xfree86/accel/s3_virge/s3cmap.c@@/PUBLIC-LATEST Sun Oct 19 15:01:03 1997 --- xc/programs/Xserver/hw/xfree86/accel/s3_virge/s3cmap.c Fri Mar 6 16:33:49 1998 *************** *** 27,33 **** /* * Modified by Amancio Hasty and Jon Tombs */ ! /* $TOG: s3cmap.c /main/6 1997/10/19 15:03:06 kaleb $ */ #include "X.h" --- 27,33 ---- /* * Modified by Amancio Hasty and Jon Tombs */ ! /* $TOG: s3cmap.c /main/7 1998/03/06 16:35:27 kaleb $ */ #include "X.h" *************** *** 195,201 **** Pixel *ppix; xrgb *prgb; xColorItem *defs; ! int i,j; if (pmap == oldmap) return; --- 195,201 ---- Pixel *ppix; xrgb *prgb; xColorItem *defs; ! int i; if (pmap == oldmap) return; *************** *** 219,262 **** for (i = 0; i < entries; i++) ppix[i] = i; ! if (pmap->class == GrayScale || pmap->class == PseudoColor) ! { ! for ( i=j=0; ired[i].fShared || pmap->red[i].refcnt != 0) ! { ! defs[j].pixel = i; ! defs[j].flags = DoRed|DoGreen|DoBlue; ! if (pmap->red[i].fShared) ! { ! defs[j].red = pmap->red[i].co.shco.red->color; ! defs[j].green = pmap->red[i].co.shco.green->color; ! defs[j].blue = pmap->red[i].co.shco.blue->color; ! } ! else if (pmap->red[i].refcnt != 0) ! { ! defs[j].red = pmap->red[i].co.local.red; ! defs[j].green = pmap->red[i].co.local.green; ! defs[j].blue = pmap->red[i].co.local.blue; ! } ! j++; ! } ! } ! entries = j; ! } ! else ! { ! QueryColors( pmap, entries, ppix, prgb); ! for ( i=0; i */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/accel/tga/tga.c,v 3.17.2.6 1997/06/01 12:33:32 dawes Exp $ */ #include "X.h" #include "input.h" --- 23,29 ---- * Author: Alan Hourihane, */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/accel/tga/tga.c,v 3.17.2.8 1998/02/15 16:09:03 hohndel Exp $ */ #include "X.h" #include "input.h" *************** *** 39,44 **** --- 39,45 ---- #include "xf86Priv.h" #include "xf86_OSlib.h" #include "xf86_HWlib.h" + #include "xf86_PCI.h" #include "tga.h" #include "tga_presets.h" *************** *** 131,137 **** 0, /* int textClockFreq */ NULL, /* char* DCConfig */ NULL, /* char* DCOptions */ ! 0 /* int MemClk */ #ifdef XFreeXDGA ,0, /* int directMode */ NULL, /* Set Vid Page */ --- 132,140 ---- 0, /* int textClockFreq */ NULL, /* char* DCConfig */ NULL, /* char* DCOptions */ ! 0, /* int MemClk */ ! 0 /* int LCDClk */ ! #ifdef XFreeXDGA ,0, /* int directMode */ NULL, /* Set Vid Page */ *************** *** 238,283 **** pointer Base; DisplayModePtr pMode, pEnd; OFlagSet validOptions; ! int found_device = FALSE; ! char buf[80]; ! char *find_dev = "DEC DC21030"; ! char *find_string = "Prefetchable 32 bit memory"; ! int fin = 0; ! FILE *fd; ! /* Find the base address of the TGA chip through /proc/pci */ ! /* Not very elegant, but it does the job for now. */ ! if (tgaInfoRec.MemBase == 0) { ! fd = fopen("/proc/pci", "r"); ! if (fd != NULL) { ! fgets(buf, 80, fd); /* Grab first line */ ! do { ! if (strstr(buf, "Bus")) ! found_device = FALSE; ! if (strstr(buf, find_dev)) ! found_device = TRUE; ! if (found_device) ! if (strstr(buf, find_string)) ! tgaInfoRec.MemBase = ! strtoul(strstr(buf,"0x"),(char **)NULL,16); ! if (!fgets(buf, 80, fd)) fin = 1; /* End of File */ ! } while (fin == 0); } - } ! /* ! * DEC 21030 TGA is a memory mapped device only..... ! * Therefore we need to mmap device to do the probe. ! * We need PCI routines for the Alpha - We don't as yet have them. ! * Therefore we use MemBase from XF86Config to set base address. ! * But, if we have found it through /proc/pci - we use this. ! */ if (tgaInfoRec.MemBase == 0) ! { ! FatalError("%s %s: MemBase needed for TGA support - " ! "check /proc/pci for base address.\n", ! XCONFIG_PROBED, tgaInfoRec.name); ! } Base = xf86MapVidMem(0,EXTENDED_REGION,(pointer)tgaInfoRec.MemBase,2097152); --- 241,267 ---- pointer Base; DisplayModePtr pMode, pEnd; OFlagSet validOptions; ! pciConfigPtr pcrp, *pcrpp; ! #define TGA_DEVICE_ID1 0x00041011 ! ! pcrpp = xf86scanpci(tgaInfoRec.scrnIndex); ! ! if (!pcrpp) ! return(FALSE); ! ! i = 0; ! while ((pcrp = pcrpp[i]) != (pciConfigPtr)NULL) { ! if (pcrp->_device_vendor == TGA_DEVICE_ID1) ! break; ! i++; } ! if (!pcrp) ! return(FALSE); ! if (tgaInfoRec.MemBase == 0) ! tgaInfoRec.MemBase = pcrp->_base0 & 0xFFFFFF00; Base = xf86MapVidMem(0,EXTENDED_REGION,(pointer)tgaInfoRec.MemBase,2097152); *** ./programs/Xserver/hw/xfree86/accel/tga/tgacmap.c@@/PUBLIC-LATEST Sun Oct 19 15:01:06 1997 --- xc/programs/Xserver/hw/xfree86/accel/tga/tgacmap.c Fri Mar 6 16:33:58 1998 *************** *** 1,4 **** ! /* $TOG: tgacmap.c /main/4 1997/10/19 15:03:10 kaleb $ */ /* * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany. * --- 1,4 ---- ! /* $TOG: tgacmap.c /main/5 1998/03/06 16:35:36 kaleb $ */ /* * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany. * *************** *** 157,163 **** Pixel *ppix; xrgb *prgb; xColorItem *defs; ! int i,j; if (pmap == oldmap) return; --- 157,163 ---- Pixel *ppix; xrgb *prgb; xColorItem *defs; ! int i; if (pmap == oldmap) return; *************** *** 181,224 **** for (i = 0; i < entries; i++) ppix[i] = i; ! if (pmap->class == GrayScale || pmap->class == PseudoColor) ! { ! for ( i=j=0; ired[i].fShared || pmap->red[i].refcnt != 0) ! { ! defs[j].pixel = i; ! defs[j].flags = DoRed|DoGreen|DoBlue; ! if (pmap->red[i].fShared) ! { ! defs[j].red = pmap->red[i].co.shco.red->color; ! defs[j].green = pmap->red[i].co.shco.green->color; ! defs[j].blue = pmap->red[i].co.shco.blue->color; ! } ! else if (pmap->red[i].refcnt != 0) ! { ! defs[j].red = pmap->red[i].co.local.red; ! defs[j].green = pmap->red[i].co.local.green; ! defs[j].blue = pmap->red[i].co.local.blue; ! } ! j++; ! } ! } ! entries = j; ! } ! else ! { ! QueryColors( pmap, entries, ppix, prgb); ! for ( i=0; i --- 21,27 ---- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. */ ! /* $TOG: xf86Config.c /main/65 1998/03/07 13:41:17 kaleb $ */ #ifndef X_NOT_STDC_ENV #include *************** *** 39,44 **** --- 39,45 ---- #include "scrnintstr.h" #ifdef DPMSExtension + #include "opaque.h" extern CARD32 DPMSStandbyTime; extern CARD32 DPMSSuspendTime; extern CARD32 DPMSOffTime; *************** *** 1580,1588 **** { int token; int mtoken; - #if defined(USE_OSMOUSE) || defined(OSMOUSE_ONLY) int i; - #endif char *mouseType = "unknown"; /* Set defaults */ --- 1581,1587 ---- *************** *** 1589,1594 **** --- 1588,1595 ---- mouse_dev->baudRate = 1200; mouse_dev->oldBaudRate = -1; mouse_dev->sampleRate = 0; + mouse_dev->resolution = 0; + mouse_dev->buttons = MSE_DFLTBUTTONS; mouse_dev->emulate3Buttons = FALSE; mouse_dev->emulate3Timeout = 50; mouse_dev->chordMiddle = FALSE; *************** *** 1596,1601 **** --- 1597,1605 ---- mouse_dev->mseProc = (DeviceProc)0; mouse_dev->mseDevice = NULL; mouse_dev->mseType = -1; + mouse_dev->mseModel = 0; + mouse_dev->negativeZ = 0; + mouse_dev->positiveZ = 0; while ((token = xf86GetToken(PointerTab)) != end_tag) { switch (token) { *************** *** 1693,1698 **** --- 1697,1709 ---- #endif mouse_dev->sampleRate = val.num; break; + + case PRESOLUTION: + if (xf86GetToken(NULL) != NUMBER) xf86ConfigError("Resolution expected"); + if (val.num <= 0) + xf86ConfigError("Resolution must be a positive value"); + mouse_dev->resolution = val.num; + break; #endif /* OSMOUSE_ONLY */ case EMULATE3: if (mouse_dev->chordMiddle) *************** *** 1716,1722 **** mouse_dev->chordMiddle = TRUE; } else ! xf86ConfigError("ChordMiddle is only supported for Microsoft and Logiman"); break; case CLEARDTR: --- 1727,1733 ---- mouse_dev->chordMiddle = TRUE; } else ! xf86ConfigError("ChordMiddle is only supported for Microsoft and MouseMan"); break; case CLEARDTR: *************** *** 1758,1763 **** --- 1769,1804 ---- #endif #endif + case ZAXISMAPPING: + switch (xf86GetToken(ZMapTab)) { + case NUMBER: + if (val.num <= 0 || val.num > MSE_MAXBUTTONS) + xf86ConfigError("Button number (1..12) expected"); + mouse_dev->negativeZ = 1 << (val.num - 1); + if (xf86GetToken(NULL) != NUMBER || + val.num <= 0 || val.num > MSE_MAXBUTTONS) + xf86ConfigError("Button number (1..12) expected"); + mouse_dev->positiveZ = 1 << (val.num - 1); + break; + case XAXIS: + mouse_dev->negativeZ = mouse_dev->positiveZ = MSE_MAPTOX; + break; + case YAXIS: + mouse_dev->negativeZ = mouse_dev->positiveZ = MSE_MAPTOY; + break; + default: + xf86ConfigError("Button number (1..12), X or Y expected"); + } + break; + + case PBUTTONS: + if (xf86GetToken(NULL) != NUMBER) + xf86ConfigError("Number of buttons (1..12) expected"); + if (val.num <= 0 || val.num > MSE_MAXBUTTONS) + xf86ConfigError("Number of buttons must be a positive value (1..12)"); + mouse_dev->buttons = val.num; + break; + case EOF: FatalError("Unexpected EOF (missing EndSection?)"); break; /* :-) */ *************** *** 1784,1795 **** xf86ConfigError("No mouse device given"); } if (xf86Verbose && mouse_dev->mseType >= 0) { Bool formatFlag = FALSE; ErrorF("%s Mouse: type: %s, device: %s", XCONFIG_GIVEN, mouseType, mouse_dev->mseDevice); ! if (token != BUSMOUSE && token != PS_2) { formatFlag = TRUE; ErrorF(", baudrate: %d", mouse_dev->baudRate); --- 1825,1861 ---- xf86ConfigError("No mouse device given"); } + switch (mouse_dev->negativeZ) { + case 0: /* none */ + case MSE_MAPTOX: + case MSE_MAPTOY: + break; + default: /* buttons */ + for (i = 0; mouse_dev->negativeZ != (1 << i); ++i) + ; + if (i + 1 > mouse_dev->buttons) + mouse_dev->buttons = i + 1; + for (i = 0; mouse_dev->positiveZ != (1 << i); ++i) + ; + if (i + 1 > mouse_dev->buttons) + mouse_dev->buttons = i + 1; + break; + } + if (xf86Verbose && mouse_dev->mseType >= 0) { Bool formatFlag = FALSE; ErrorF("%s Mouse: type: %s, device: %s", XCONFIG_GIVEN, mouseType, mouse_dev->mseDevice); ! if (mouse_dev->mseType != P_BM ! && mouse_dev->mseType != P_PS2 ! && mouse_dev->mseType != P_IMPS2 ! && mouse_dev->mseType != P_THINKINGPS2 ! && mouse_dev->mseType != P_MMANPLUSPS2 ! && mouse_dev->mseType != P_GLIDEPOINTPS2 ! && mouse_dev->mseType != P_NETPS2 ! && mouse_dev->mseType != P_NETSCROLLPS2 ! && mouse_dev->mseType != P_SYSMOUSE) { formatFlag = TRUE; ErrorF(", baudrate: %d", mouse_dev->baudRate); *************** *** 1796,1811 **** } if (mouse_dev->sampleRate) { ! ErrorF("%ssamplerate: %d", formatFlag ? ",\n " : ", ", ! mouse_dev->sampleRate); formatFlag = !formatFlag; } if (mouse_dev->emulate3Buttons) ! ErrorF("%s3 button emulation (timeout: %dms)", ! formatFlag ? ",\n " : ", ", mouse_dev->emulate3Timeout); if (mouse_dev->chordMiddle) ! ErrorF("%sChorded middle button", formatFlag ? ",\n " : ", "); ErrorF("\n"); } #ifdef NEED_RETURN_VALUE return RET_OKAY; --- 1862,1911 ---- } if (mouse_dev->sampleRate) { ! ErrorF(formatFlag ? "\n%s Mouse: samplerate: %d" : "%ssamplerate: %d", ! formatFlag ? XCONFIG_GIVEN : ", ", mouse_dev->sampleRate); formatFlag = !formatFlag; } + if (mouse_dev->resolution) + { + ErrorF(formatFlag ? "\n%s Mouse: resolution: %d" : "%sresolution: %d", + formatFlag ? XCONFIG_GIVEN : ", ", mouse_dev->resolution); + formatFlag = !formatFlag; + } + ErrorF(formatFlag ? "\n%s Mouse: buttons: %d" : "%sbuttons: %d", + formatFlag ? XCONFIG_GIVEN : ", ", mouse_dev->buttons); + formatFlag = !formatFlag; if (mouse_dev->emulate3Buttons) ! { ! ErrorF(formatFlag ? "\n%s Mouse: 3 button emulation (timeout: %dms)" : ! "%s3 button emulation (timeout: %dms)", ! formatFlag ? XCONFIG_GIVEN : ", ", mouse_dev->emulate3Timeout); ! formatFlag = !formatFlag; ! } if (mouse_dev->chordMiddle) ! ErrorF(formatFlag ? "\n%s Mouse: Chorded middle button" : ! "%sChorded middle button", ! formatFlag ? XCONFIG_GIVEN : ", "); ErrorF("\n"); + + switch (mouse_dev->negativeZ) { + case 0: /* none */ + break; + case MSE_MAPTOX: + ErrorF("%s Mouse: zaxismapping: X\n", XCONFIG_GIVEN); + break; + case MSE_MAPTOY: + ErrorF("%s Mouse: zaxismapping: Y\n", XCONFIG_GIVEN); + break; + default: /* buttons */ + for (i = 0; mouse_dev->negativeZ != (1 << i); ++i) + ; + ErrorF("%s Mouse: zaxismapping: (-)%d", XCONFIG_GIVEN, i + 1); + for (i = 0; mouse_dev->positiveZ != (1 << i); ++i) + ; + ErrorF(" (+)%d\n", i + 1); + break; + } } #ifdef NEED_RETURN_VALUE return RET_OKAY; *************** *** 1867,1872 **** --- 1967,1973 ---- devp->DCConfig = NULL; devp->DCOptions = NULL; devp->MemClk = 0; + devp->LCDClk = 0; while ((token = xf86GetToken(DeviceTab)) != ENDSECTION) { devp->DCConfig = xf86DCSaveLine(devp->DCConfig, token); *************** *** 2133,2138 **** --- 2234,2245 ---- OFLG_SET(XCONFIG_MEMCLOCK,&(devp->xconfigFlag)); break; + case LCDCLOCK: + if (xf86GetToken(NULL) != NUMBER) xf86ConfigError("LCD Clock value in MHz expected"); + devp->LCDClk = (int)(val.realnum * 1000.0 + 0.5); + OFLG_SET(XCONFIG_LCDCLOCK,&(devp->xconfigFlag)); + break; + case CHIPID: if (xf86GetToken(NULL) != NUMBER) xf86ConfigError("ChipID expected"); devp->chipID = val.num; *************** *** 2783,2788 **** --- 2890,2896 ---- screen->s3Nadjust = device_list[i].s3Nadjust; screen->s3MClk = device_list[i].s3MClk; screen->MemClk = device_list[i].MemClk; + screen->LCDClk = device_list[i].LCDClk; screen->chipID = device_list[i].chipID; screen->chipRev = device_list[i].chipRev; screen->s3RefClk = device_list[i].s3RefClk; *************** *** 3471,3476 **** --- 3579,3585 ---- target->HSyncStart = best_mode->HSyncStart; target->HSyncEnd = best_mode->HSyncEnd; target->HTotal = best_mode->HTotal; + target->HSkew = best_mode->HSkew; target->VDisplay = best_mode->VDisplay; target->VSyncStart = best_mode->VSyncStart; target->VSyncEnd = best_mode->VSyncEnd; *************** *** 3480,3485 **** --- 3589,3595 ---- target->CrtcHSyncStart = best_mode->CrtcHSyncStart; target->CrtcHSyncEnd = best_mode->CrtcHSyncEnd; target->CrtcHTotal = best_mode->CrtcHTotal; + target->CrtcHSkew = best_mode->CrtcHSkew; target->CrtcVDisplay = best_mode->CrtcVDisplay; target->CrtcVSyncStart = best_mode->CrtcVSyncStart; target->CrtcVSyncEnd = best_mode->CrtcVSyncEnd; *** ./programs/Xserver/hw/xfree86/common/xf86Events.c@@/PUBLIC-LATEST Fri Nov 14 14:02:08 1997 --- xc/programs/Xserver/hw/xfree86/common/xf86Events.c Sat Mar 7 13:44:32 1998 *************** *** 1,4 **** ! /* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86Events.c,v 3.42.2.3 1997/07/13 14:45:03 dawes Exp $ */ /* * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany. * --- 1,4 ---- ! /* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86Events.c,v 3.42.2.4 1998/02/07 09:23:28 hohndel Exp $ */ /* * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany. * *************** *** 21,27 **** * PERFORMANCE OF THIS SOFTWARE. * */ ! /* $TOG: xf86Events.c /main/50 1997/11/14 14:01:35 kaleb $ */ /* [JCH-96/01/21] Extended std reverse map to four buttons. */ --- 21,27 ---- * PERFORMANCE OF THIS SOFTWARE. * */ ! /* $TOG: xf86Events.c /main/53 1998/03/07 13:46:13 kaleb $ */ /* [JCH-96/01/21] Extended std reverse map to four buttons. */ *************** *** 60,68 **** #endif #include "mipointer.h" ! #ifdef DPMSExtension ! #include #endif #ifdef XKB --- 60,68 ---- #endif #include "mipointer.h" ! #include "opaque.h" #ifdef DPMSExtension ! #include "extensions/dpms.h" #endif #ifdef XKB *************** *** 163,168 **** --- 163,173 ---- ); #endif + #ifdef DPMSExtension + extern BOOL DPMSEnabled; + extern void DPMSSet(CARD16); + #endif + static void xf86VTSwitch( #if NeedFunctionPrototypes void *************** *** 295,301 **** --- 300,308 ---- 4, 6, 5, 7, 12, 14, 13, 15 }; + #define reverseBits(map, b) (((b) & ~0x0f) | map[(b) & 0x0f]) + /* * TimeSinceLastInputEvent -- * Function used for screensaver purposes by the os module. Retruns the *************** *** 1084,1092 **** truebuttons = buttons; if (private->mseType == P_MMHIT) ! buttons = hitachMap[buttons]; else ! buttons = reverseMap[buttons]; if (dx || dy) { --- 1091,1099 ---- truebuttons = buttons; if (private->mseType == P_MMHIT) ! buttons = reverseBits(hitachMap, buttons); else ! buttons = reverseBits(reverseMap, buttons); if (dx || dy) { *************** *** 1136,1144 **** * would nearly double its size, so I'll stick with this fix. - TJW */ if (private->mseType == P_MMHIT) ! change = buttons ^ hitachMap[private->lastButtons]; else ! change = buttons ^ reverseMap[private->lastButtons]; if (change & 02) { #ifdef XINPUT --- 1143,1151 ---- * would nearly double its size, so I'll stick with this fix. - TJW */ if (private->mseType == P_MMHIT) ! change = buttons ^ reverseBits(hitachMap, private->lastButtons); else ! change = buttons ^ reverseBits(reverseMap, private->lastButtons); if (change & 02) { #ifdef XINPUT *************** *** 1255,1263 **** * is the reverse of the button mapping reported to the server. */ if (private->mseType == P_MMHIT) ! change = buttons ^ hitachMap[private->lastButtons]; else ! change = buttons ^ reverseMap[private->lastButtons]; while (change) { id = ffs(change); --- 1262,1270 ---- * is the reverse of the button mapping reported to the server. */ if (private->mseType == P_MMHIT) ! change = buttons ^ reverseBits(hitachMap, private->lastButtons); else ! change = buttons ^ reverseBits(reverseMap, private->lastButtons); while (change) { id = ffs(change); *************** *** 1393,1402 **** FatalError("Caught signal %d. Server aborting\n", signo); } - #ifdef DPMSExtension - extern BOOL DPMSEnabled; - extern void DPMSSet(CARD16); - #endif /* * xf86VTSwitch -- * Handle requests for switching the vt. --- 1400,1405 ---- *** ./programs/Xserver/hw/xfree86/common/xf86Init.c@@/PUBLIC-LATEST Fri Nov 14 13:44:58 1997 --- xc/programs/Xserver/hw/xfree86/common/xf86Init.c Sat Mar 7 13:31:36 1998 *************** *** 21,27 **** * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. */ ! /* $TOG: xf86Init.c /main/43 1997/11/14 13:44:24 kaleb $ */ #ifndef X_NOT_STDC_ENV #include --- 21,27 ---- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. */ ! /* $TOG: xf86Init.c /main/45 1998/03/07 13:33:18 kaleb $ */ #ifndef X_NOT_STDC_ENV #include *************** *** 61,70 **** #include "atKeynames.h" extern int xtest_command_key; #endif /* XTESTEXT1 */ - - #ifdef PC98 - #include "pc98_vers.h" - #endif #ifdef __EMX__ #define seteuid(x) /*nothing*/ --- 61,66 ---- *** ./programs/Xserver/hw/xfree86/common/xf86Io.c@@/PUBLIC-LATEST Sat Jul 19 10:01:32 1997 --- xc/programs/Xserver/hw/xfree86/common/xf86Io.c Fri Mar 6 16:34:56 1998 *************** *** 1,4 **** ! /* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86Io.c,v 3.28.2.1 1997/05/10 07:02:55 hohndel Exp $ */ /* * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany. * --- 1,4 ---- ! /* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86Io.c,v 3.28.2.5 1998/02/24 19:05:55 hohndel Exp $ */ /* * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany. * *************** *** 21,27 **** * PERFORMANCE OF THIS SOFTWARE. * */ ! /* $TOG: xf86Io.c /main/28 1997/07/19 10:01:33 kaleb $ */ #define NEED_EVENTS #include "X.h" --- 21,28 ---- * PERFORMANCE OF THIS SOFTWARE. * */ ! /* $TOG: xf86Io.c /main/29 1998/03/06 16:36:34 kaleb $ */ ! /* Patch for PS/2 Intellimouse - Tim Goodwin 1997-11-06. */ #define NEED_EVENTS #include "X.h" *************** *** 442,448 **** int *fd; PtrCtrlProcPtr ctrl; { ! unsigned char map[6]; int nbuttons; int mousefd; --- 443,449 ---- int *fd; PtrCtrlProcPtr ctrl; { ! unsigned char map[MSE_MAXBUTTONS + 1]; int nbuttons; int mousefd; *************** *** 451,479 **** case DEVICE_INIT: pPointer->public.on = FALSE; - map[1] = 1; - map[2] = 2; - map[3] = 3; - map[4] = 4; - map[5] = 5; - /* ! * [JCH-96/01/21] The ALPS GlidePoint pad, extends the MS protocol ! * with a fourth button activated by tapping the pad. ! * ! * [TVO-97/03/10] the wheel on the intellimouse is sending us button ! * 4 and 5 events, hence we have 5 buttons. */ ! if (mouse->mseType == P_MMHIT || mouse->mseType == P_GLIDEPOINT) ! nbuttons = 4; ! else if (mouse->mseType == P_MSINTELLIMOUSE) ! nbuttons = 5; ! else ! nbuttons = 3; InitPointerDeviceStruct((DevicePtr)pPointer, map, ! nbuttons, miPointerGetMotionEvents, ctrl, miPointerGetMotionBufferSize()); --- 452,467 ---- case DEVICE_INIT: pPointer->public.on = FALSE; /* ! * [KAZU-241097] We don't know exactly how many buttons the ! * device has... */ ! for (nbuttons = 0; nbuttons < MSE_MAXBUTTONS; ++nbuttons) ! map[nbuttons + 1] = nbuttons + 1; InitPointerDeviceStruct((DevicePtr)pPointer, map, ! min(mouse->buttons, MSE_MAXBUTTONS), miPointerGetMotionEvents, ctrl, miPointerGetMotionBufferSize()); *** ./programs/Xserver/hw/xfree86/common/xf86Priv.h@@/PUBLIC-LATEST Sat Jul 19 10:02:09 1997 --- xc/programs/Xserver/hw/xfree86/common/xf86Priv.h Fri Mar 6 16:35:00 1998 *************** *** 1,4 **** ! /* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86Priv.h,v 3.24 1996/12/23 06:43:37 dawes Exp $ */ /* * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany. * --- 1,4 ---- ! /* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86Priv.h,v 3.24.2.1 1998/02/01 16:04:47 robin Exp $ */ /* * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany. * *************** *** 21,27 **** * PERFORMANCE OF THIS SOFTWARE. * */ ! /* $TOG: xf86Priv.h /main/19 1997/07/19 10:02:11 kaleb $ */ #ifndef _XF86PRIV_H #define _XF86PRIV_H --- 21,27 ---- * PERFORMANCE OF THIS SOFTWARE. * */ ! /* $TOG: xf86Priv.h /main/20 1998/03/06 16:36:39 kaleb $ */ #ifndef _XF86PRIV_H #define _XF86PRIV_H *************** *** 154,160 **** extern char xf86ConfigFile[]; extern int xf86Verbose; ! extern Bool xf86ProbeOnly; extern unsigned short xf86MouseCflags[]; extern Bool xf86SupportedMouseTypes[]; extern int xf86NumMouseTypes; --- 154,160 ---- extern char xf86ConfigFile[]; extern int xf86Verbose; ! extern Bool xf86ProbeOnly, xf86ProbeFailed; extern unsigned short xf86MouseCflags[]; extern Bool xf86SupportedMouseTypes[]; extern int xf86NumMouseTypes; *** ./programs/Xserver/hw/xfree86/common/xf86Wacom.c@@/PUBLIC-LATEST Sun Aug 10 13:00:15 1997 --- xc/programs/Xserver/hw/xfree86/common/xf86Wacom.c Fri Mar 6 16:35:05 1998 *************** *** 1,4 **** ! /* $TOG: xf86Wacom.c /main/22 1997/08/10 12:58:51 kaleb $ */ /* * Copyright 1995-1997 by Frederic Lepied, France. * --- 1,4 ---- ! /* $TOG: xf86Wacom.c /main/23 1998/03/06 16:36:43 kaleb $ */ /* * Copyright 1995-1997 by Frederic Lepied, France. * *************** *** 22,28 **** * */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86Wacom.c,v 3.25.2.3 1997/07/31 06:24:00 dawes Exp $ */ /* * This driver is only able to handle the Wacom IV protocol. --- 22,28 ---- * */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86Wacom.c,v 3.25.2.5 1998/02/07 10:05:21 hohndel Exp $ */ /* * This driver is only able to handle the Wacom IV protocol. *************** *** 205,211 **** #define XI_CURSOR "CURSOR" /* X device name for the cursor */ #define XI_ERASER "ERASER" /* X device name for the eraser */ #define MAX_VALUE 100 /* number of positions */ ! #define MAXTRY 50 /* max number of try to receive magic number */ #define SYSCALL(call) while(((call) == -1) && (errno == EINTR)) #define WC_RESET_IV "#\r" /* reset to wacom IV command set */ --- 205,211 ---- #define XI_CURSOR "CURSOR" /* X device name for the cursor */ #define XI_ERASER "ERASER" /* X device name for the eraser */ #define MAX_VALUE 100 /* number of positions */ ! #define MAXTRY 2 /* max number of try to receive magic number */ #define SYSCALL(call) while(((call) == -1) && (errno == EINTR)) #define WC_RESET_IV "#\r" /* reset to wacom IV command set */ *************** *** 220,229 **** #define WC_NO_MACRO1 "~M1\r" /* disable macro buttons of group 1 */ #define WC_RATE "IT0\r" /* max transmit rate (unit of 5 ms) */ #define WC_TILT_MODE "FM1\r" /* enable extra protocol for tilt management */ static const char * setup_string = WC_MULTI WC_UPPER_ORIGIN ! WC_ALL_MACRO WC_NO_MACRO1 WC_RATE; #define COMMAND_SET_MASK 0xc0 #define BAUD_RATE_MASK 0x0a #define PARITY_MASK 0x30 --- 220,235 ---- #define WC_NO_MACRO1 "~M1\r" /* disable macro buttons of group 1 */ #define WC_RATE "IT0\r" /* max transmit rate (unit of 5 ms) */ #define WC_TILT_MODE "FM1\r" /* enable extra protocol for tilt management */ + #define WC_NO_INCREMENT "IN0\r" /* do not enable increment mode */ + #define WC_STREAM_MODE "SR\r" /* enable continuous mode */ + #define WC_PRESSURE_MODE "PH1\r" /* enable pressure mode */ + #define WC_START "ST\r" /* start sending coordinates */ static const char * setup_string = WC_MULTI WC_UPPER_ORIGIN ! WC_ALL_MACRO WC_NO_MACRO1 WC_RATE WC_NO_INCREMENT WC_STREAM_MODE; + static const char * penpartner_setup_string = WC_PRESSURE_MODE WC_START; + #define COMMAND_SET_MASK 0xc0 #define BAUD_RATE_MASK 0x0a #define PARITY_MASK 0x30 *************** *** 255,298 **** static KeySym wacom_map[] = { NoSymbol, /* 0x00 */ ! XK_F1, /* 0x01 */ ! XK_F2, /* 0x02 */ ! XK_F3, /* 0x03 */ ! XK_F4, /* 0x04 */ ! XK_F5, /* 0x05 */ ! XK_F6, /* 0x06 */ ! XK_F7, /* 0x07 */ ! XK_F8, /* 0x08 */ ! XK_F8, /* 0x09 */ ! XK_F10, /* 0x0a */ ! XK_F11, /* 0x0b */ ! XK_F12, /* 0x0c */ ! XK_F13, /* 0x0d */ ! XK_F14, /* 0x0e */ ! XK_F15, /* 0x0f */ ! XK_F16, /* 0x10 */ ! XK_F17, /* 0x11 */ ! XK_F18, /* 0x12 */ ! XK_F19, /* 0x13 */ ! XK_F20, /* 0x14 */ ! XK_F21, /* 0x15 */ ! XK_F22, /* 0x16 */ ! XK_F23, /* 0x17 */ ! XK_F24, /* 0x18 */ ! XK_F25, /* 0x19 */ ! XK_F26, /* 0x1a */ ! XK_F27, /* 0x1b */ ! XK_F28, /* 0x1c */ ! XK_F29, /* 0x1d */ ! XK_F30, /* 0x1e */ ! XK_F31, /* 0x1f */ ! XK_F32 /* 0x20 */ }; /* minKeyCode = 8 because this is the min legal key code */ static KeySymsRec wacom_keysyms = { /* map minKeyCode maxKC width */ ! wacom_map, 8, 0x20, 1 }; /****************************************************************************** --- 261,311 ---- static KeySym wacom_map[] = { NoSymbol, /* 0x00 */ ! NoSymbol, /* 0x01 */ ! NoSymbol, /* 0x02 */ ! NoSymbol, /* 0x03 */ ! NoSymbol, /* 0x04 */ ! NoSymbol, /* 0x05 */ ! NoSymbol, /* 0x06 */ ! NoSymbol, /* 0x07 */ ! XK_F1, /* 0x08 */ ! XK_F2, /* 0x09 */ ! XK_F3, /* 0x0a */ ! XK_F4, /* 0x0b */ ! XK_F5, /* 0x0c */ ! XK_F6, /* 0x0d */ ! XK_F7, /* 0x0e */ ! XK_F8, /* 0x0f */ ! XK_F8, /* 0x10 */ ! XK_F10, /* 0x11 */ ! XK_F11, /* 0x12 */ ! XK_F12, /* 0x13 */ ! XK_F13, /* 0x14 */ ! XK_F14, /* 0x15 */ ! XK_F15, /* 0x16 */ ! XK_F16, /* 0x17 */ ! XK_F17, /* 0x18 */ ! XK_F18, /* 0x19 */ ! XK_F19, /* 0x1a */ ! XK_F20, /* 0x1b */ ! XK_F21, /* 0x1c */ ! XK_F22, /* 0x1d */ ! XK_F23, /* 0x1e */ ! XK_F24, /* 0x1f */ ! XK_F25, /* 0x20 */ ! XK_F26, /* 0x21 */ ! XK_F27, /* 0x22 */ ! XK_F28, /* 0x23 */ ! XK_F29, /* 0x24 */ ! XK_F30, /* 0x25 */ ! XK_F31, /* 0x26 */ ! XK_F32 /* 0x27 */ }; /* minKeyCode = 8 because this is the min legal key code */ static KeySymsRec wacom_keysyms = { /* map minKeyCode maxKC width */ ! wacom_map, 8, 0x27, 1 }; /****************************************************************************** *************** *** 608,657 **** } do { - switch (wait_for_fd(fd)) { - case -1: - ErrorF("Wacom select error : %s\n", strerror(errno)); - return NULL; - break; - case 0: - ErrorF("Timeout while reading Wacom tablet. No tablet connected ???\n"); - return NULL; - break; - } - maxtry = MAXTRY; do { ! wait_for_fd(fd); ! SYSCALL(nr = read(fd, answer, 1)); ! if ((nr == -1) && (errno != EAGAIN)) { ! ErrorF("Wacom read error : %s\n", strerror(errno)); ! return NULL; } - DBG(10, ErrorF("%c err=%d [0]\n", answer[0], nr)); maxtry--; } while ((answer[0] != request[0]) && maxtry); if (maxtry == 0) { ! ErrorF("Wacom unable to read first byte of request '%s' answer after %d tries\n", request, MAXTRY); return NULL; } do { maxtry = MAXTRY; do { ! wait_for_fd(fd); ! SYSCALL(nr = read(fd, answer+1, 1)); ! if ((nr == -1) && (errno != EAGAIN)) { ! ErrorF("Wacom read error : %s\n", strerror(errno)); ! return NULL; } - DBG(10, ErrorF("%c err=%d [1]\n", answer[1], nr)); maxtry--; } while ((nr == -1) && maxtry); if (maxtry == 0) { ! ErrorF("Wacom unable to read second byte of request '%s' answer after %d tries\n", request, MAXTRY); return NULL; } --- 621,669 ---- } do { maxtry = MAXTRY; + /* Read the first byte of the answer which must be equal to the first + * byte of the request. + */ do { ! if ((nr = wait_for_fd(fd)) > 0) { ! SYSCALL(nr = read(fd, answer, 1)); ! if ((nr == -1) && (errno != EAGAIN)) { ! ErrorF("Wacom read error : %s\n", strerror(errno)); ! return NULL; ! } ! DBG(10, ErrorF("%c err=%d [0]\n", answer[0], nr)); } maxtry--; } while ((answer[0] != request[0]) && maxtry); if (maxtry == 0) { ! ErrorF("Wacom unable to read first byte of request '%s' answer after %d tries\n", ! request, MAXTRY); return NULL; } + /* Read the second byte of the answer which must be equal to the second + * byte of the request. + */ do { maxtry = MAXTRY; do { ! if ((nr = wait_for_fd(fd)) > 0) { ! SYSCALL(nr = read(fd, answer+1, 1)); ! if ((nr == -1) && (errno != EAGAIN)) { ! ErrorF("Wacom read error : %s\n", strerror(errno)); ! return NULL; ! } ! DBG(10, ErrorF("%c err=%d [1]\n", answer[1], nr)); } maxtry--; } while ((nr == -1) && maxtry); if (maxtry == 0) { ! ErrorF("Wacom unable to read second byte of request '%s' answer after %d tries\n", ! request, MAXTRY); return NULL; } *************** *** 664,691 **** } while ((answer[0] != request[0]) && (answer[1] != request[1])); ! /* read until carriage return */ len = 2; do { - maxtry = MAXTRY; do { ! wait_for_fd(fd); ! SYSCALL(nr = read(fd, answer+len, 1)); ! if ((nr == -1) && (errno != EAGAIN)) { ! ErrorF("Wacom read error : %s\n", strerror(errno)); ! return NULL; } ! DBG(10, ErrorF("%c err=%d [%d]\n", answer[len], nr, len)); ! maxtry--; ! } while ((nr == -1) && maxtry); if (maxtry == 0) { ! ErrorF("Wacom unable to read last byte of request '%s' answer after %d tries\n", request, MAXTRY); ! return NULL; } - len += nr; } while (answer[len-1] != '\r'); answer[len-1] = '\0'; return answer; --- 676,716 ---- } while ((answer[0] != request[0]) && (answer[1] != request[1])); ! /* Read until carriage return or timeout (to handle broken protocol ! * implementations which don't end with a ). ! */ len = 2; + maxtry = MAXTRY; do { do { ! if ((nr = wait_for_fd(fd)) > 0) { ! SYSCALL(nr = read(fd, answer+len, 1)); ! if ((nr == -1) && (errno != EAGAIN)) { ! ErrorF("Wacom read error : %s\n", strerror(errno)); ! return NULL; ! } ! DBG(10, ErrorF("%c err=%d [%d]\n", answer[len], nr, len)); } ! else { ! DBG(10, ErrorF("timeout remains %d tries\n", maxtry)); ! maxtry--; ! } ! } while ((nr <= 0) && maxtry); + if (nr > 0) { + len += nr; + } + if (maxtry == 0) { ! ErrorF("Wacom unable to read last byte of request '%s' answer after %d tries\n", ! request, MAXTRY); ! break; } } while (answer[len-1] != '\r'); + if (len <= 3) + return NULL; + answer[len-1] = '\0'; return answer; *************** *** 907,917 **** DBG(6, ErrorF("macro=%d buttons=%d wacom_map[%d]=%x\n", macro, buttons, macro, wacom_map[macro])); ! ! xf86PostKeyEvent(local->dev, macro, 1, is_absolute, 0, 5, 0, 0, buttons, rtx, rty); ! xf86PostKeyEvent(local->dev, macro, 0, is_absolute, 0, 5, 0, 0, buttons, rtx, rty); } --- 932,943 ---- DBG(6, ErrorF("macro=%d buttons=%d wacom_map[%d]=%x\n", macro, buttons, macro, wacom_map[macro])); ! ! /* First available Keycode begins at 8 => macro+7 */ ! xf86PostKeyEvent(local->dev, macro+7, 1, is_absolute, 0, 5, 0, 0, buttons, rtx, rty); ! xf86PostKeyEvent(local->dev, macro+7, 0, is_absolute, 0, 5, 0, 0, buttons, rtx, rty); } *************** *** 1112,1121 **** int a, b; int loop, idx; float version = 0.0; ! DBG(1, ErrorF("opening %s\n", common->wcmDevice)); ! SYSCALL(local->fd = open(common->wcmDevice, O_RDWR|O_NDELAY)); if (local->fd == -1) { ErrorF("Error opening %s : %s\n", common->wcmDevice, strerror(errno)); return !Success; --- 1138,1148 ---- int a, b; int loop, idx; float version = 0.0; ! int is_a_penpartner = 0; ! DBG(1, ErrorF("opening %s\n", common->wcmDevice)); ! SYSCALL(local->fd = open(common->wcmDevice, O_RDWR|O_NDELAY, 0)); if (local->fd == -1) { ErrorF("Error opening %s : %s\n", common->wcmDevice, strerror(errno)); return !Success; *************** *** 1191,1214 **** ErrorF("Wacom select error : %s\n", strerror(errno)); return !Success; } - - #ifdef POSIX_TTY - /* send a START just for the case the tablet would have been stopped */ - SYSCALL(err = tcflow(local->fd, TCION)); - if (err == -1) { - ErrorF("Wacom tcflow TCION error : %s\n", strerror(errno)); - } ! /* flush input and output */ ! SYSCALL(err = tcflush(local->fd, TCIOFLUSH)); ! if (err == -1) { ! ErrorF("Wacom tcflush TCIOFLUSH error : %s\n", strerror(errno)); ! } ! #else ! Code for OSs without POSIX tty functions ! #endif ! ! DBG(2, ErrorF("reading model\n")); if (!send_request(local->fd, WC_MODEL, buffer)) return !Success; DBG(2, ErrorF("%s\n", buffer)); --- 1218,1225 ---- ErrorF("Wacom select error : %s\n", strerror(errno)); return !Success; } ! DBG(2, ErrorF("reading model\n")); if (!send_request(local->fd, WC_MODEL, buffer)) return !Success; DBG(2, ErrorF("%s\n", buffer)); *************** *** 1216,1244 **** if (xf86Verbose) ErrorF("%s Wacom tablet model : %s\n", XCONFIG_PROBED, buffer+2); ! /* answer is in the form ~#Tablet-Model ROM_Version */ ! /* loop while not space */ ! for(loop=0; loopwcmFlags, version, buffer+loop+2)); if ((common->wcmFlags & TILT_FLAG) && (version >= (float)1.4)) { common->wcmPktLength = 9; } ! DBG(2, ErrorF("reading config\n")); ! if (!send_request(local->fd, WC_CONFIG, buffer)) ! return !Success; ! DBG(2, ErrorF("%s\n", buffer)); ! sscanf(buffer+19, "%d,%d,%d,%d", &a, &b, &common->wcmResolX, &common->wcmResolY); DBG(2, ErrorF("reading max coordinates\n")); if (!send_request(local->fd, WC_COORD, buffer)) --- 1227,1263 ---- if (xf86Verbose) ErrorF("%s Wacom tablet model : %s\n", XCONFIG_PROBED, buffer+2); ! /* answer is in the form ~#Tablet-Model VRom_Version */ ! /* look for the first V from the end of the string */ ! /* this seems to be the better way to find the version of the ROM */ ! for(loop=strlen(buffer); loop>=0 && *(buffer+loop) != 'V'; loop--); for(idx=loop; idxwcmFlags, version, buffer+loop+1)); if ((common->wcmFlags & TILT_FLAG) && (version >= (float)1.4)) { common->wcmPktLength = 9; } ! /* check for a PenPartner model which doesn't answer WC_CONFIG request */ ! if (buffer[2] == 'C' && buffer[3] == 'T') { ! DBG(2, ErrorF("detected a PenPartner model\n")); ! common->wcmResolX = 1000; ! common->wcmResolY = 1000; ! is_a_penpartner = 1; ! } ! else { ! DBG(2, ErrorF("reading config\n")); ! if (!send_request(local->fd, WC_CONFIG, buffer)) ! return !Success; ! DBG(2, ErrorF("%s\n", buffer)); ! sscanf(buffer+19, "%d,%d,%d,%d", &a, &b, &common->wcmResolX, &common->wcmResolY); ! } DBG(2, ErrorF("reading max coordinates\n")); if (!send_request(local->fd, WC_COORD, buffer)) *************** *** 1251,1257 **** common->wcmResolY)); /* send a setup string to the tablet */ ! SYSCALL(err = write(local->fd, setup_string, strlen(setup_string))); if (err == -1) { ErrorF("Wacom write error : %s\n", strerror(errno)); return !Success; --- 1270,1283 ---- common->wcmResolY)); /* send a setup string to the tablet */ ! if (is_a_penpartner) { ! SYSCALL(err = write(local->fd, penpartner_setup_string, ! strlen(penpartner_setup_string))); ! } ! else { ! SYSCALL(err = write(local->fd, setup_string, strlen(setup_string))); ! } ! if (err == -1) { ErrorF("Wacom write error : %s\n", strerror(errno)); return !Success; *** ./programs/Xserver/hw/xfree86/common/xf86Xinput.c@@/PUBLIC-LATEST Sat Jul 19 10:02:37 1997 --- xc/programs/Xserver/hw/xfree86/common/xf86Xinput.c Fri Mar 6 16:35:12 1998 *************** *** 1,4 **** ! /* $TOG: xf86Xinput.c /main/15 1997/07/19 10:02:38 kaleb $ */ /* * Copyright 1995,1996 by Frederic Lepied, France. * --- 1,4 ---- ! /* $TOG: xf86Xinput.c /main/16 1998/03/06 16:36:49 kaleb $ */ /* * Copyright 1995,1996 by Frederic Lepied, France. * *************** *** 22,28 **** * */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86Xinput.c,v 3.22.2.5 1997/05/27 09:27:48 dawes Exp $ */ #include "Xmd.h" #include "XI.h" --- 22,28 ---- * */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86Xinput.c,v 3.22.2.7 1998/02/07 10:05:22 hohndel Exp $ */ #include "Xmd.h" #include "XI.h" *************** *** 117,122 **** --- 117,131 ---- (device == inputInfo.pointer)); } + static int + xf86IsAlwaysCore(DeviceIntPtr device) + { + LocalDevicePtr local = (LocalDevicePtr) device->public.devicePrivate; + + return(local->always_core_feedback && + local->always_core_feedback->ctrl.integer_displayed); + } + int xf86IsCoreKeyboard(DeviceIntPtr device) { *************** *** 150,156 **** xf86CheckButton(int button, int down) { ! int state = (inputInfo.pointer->button->state & 0x1f00) >> 8; int check = (state & (1 << (button - 1))); if ((check && down) && (!check && !down)) { --- 159,166 ---- xf86CheckButton(int button, int down) { ! /* The device may have up to MSE_MAXBUTTONS (12) buttons. */ ! int state = (inputInfo.pointer->button->state & 0x0fff00) >> 8; int check = (state & (1 << (button - 1))); if ((check && down) && (!check && !down)) { *************** *** 1109,1117 **** int cx, cy; GetSpritePosition(&cx, &cy); xE->u.u.type = is_down ? ButtonPress : ButtonRelease; ! xE->u.u.detail = button; xE->u.keyButtonPointer.rootY = cx; xE->u.keyButtonPointer.rootX = cy; xf86Info.lastEventTime = xE->u.keyButtonPointer.time = GetTimeInMillis(); --- 1119,1144 ---- int cx, cy; GetSpritePosition(&cx, &cy); + + /* Try to find the index in the core buttons map + * which corresponds to the extended button for + * an AlwaysCore device. + */ + if (xf86IsAlwaysCore(device)) { + int loop; + + button = device->button->map[button]; + + for(loop=1; loop<=inputInfo.pointer->button->numButtons; loop++) { + if (inputInfo.pointer->button->map[loop] == button) { + button = loop; + break; + } + } + } xE->u.u.type = is_down ? ButtonPress : ButtonRelease; ! xE->u.u.detail = button; xE->u.keyButtonPointer.rootY = cx; xE->u.keyButtonPointer.rootX = cy; xf86Info.lastEventTime = xE->u.keyButtonPointer.time = GetTimeInMillis(); *** ./programs/Xserver/hw/xfree86/common/xf86_Config.h@@/PUBLIC-LATEST Sat Jul 19 10:02:48 1997 --- xc/programs/Xserver/hw/xfree86/common/xf86_Config.h Fri Mar 6 16:35:17 1998 *************** *** 1,4 **** ! /* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86_Config.h,v 3.59.2.4 1997/05/18 12:00:08 dawes Exp $ */ /* * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany * Copyright 1993 by David Dawes --- 1,4 ---- ! /* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86_Config.h,v 3.59.2.8 1998/02/24 19:05:56 hohndel Exp $ */ /* * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany * Copyright 1993 by David Dawes *************** *** 23,29 **** * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ ! /* $TOG: xf86_Config.h /main/26 1997/07/19 10:02:49 kaleb $ */ #ifndef _xf86_config_h #define _xf86_config_h --- 23,29 ---- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ ! /* $TOG: xf86_Config.h /main/27 1998/03/06 16:36:55 kaleb $ */ #ifndef _xf86_config_h #define _xf86_config_h *************** *** 85,90 **** --- 85,91 ---- char *DCConfig; char *DCOptions; int MemClk; /* General flag used for memory clocking */ + int LCDClk; } GDevRec, *GDevPtr; typedef struct { *************** *** 174,182 **** #define PS_2 1026 #define MMHITTAB 1027 #define GLIDEPOINT 1028 ! #define INTELLIMOUSE 1029 ! #define XQUE 1030 ! #define OSMOUSE 1031 #ifdef INIT_CONFIG static SymTabRec MouseTab[] = { --- 175,192 ---- #define PS_2 1026 #define MMHITTAB 1027 #define GLIDEPOINT 1028 ! #define IMSERIAL 1029 ! #define THINKING 1030 ! #define IMPS2 1031 ! #define THINKINGPS2 1032 ! #define MMANPLUSPS2 1033 ! #define GLIDEPOINTPS2 1034 ! #define NETPS2 1035 ! #define NETSCROLLPS2 1036 ! #define SYSMOUSE 1037 ! #define AUTOMOUSE 1038 ! #define XQUE 1039 ! #define OSMOUSE 1040 #ifdef INIT_CONFIG static SymTabRec MouseTab[] = { *************** *** 189,195 **** { PS_2, "ps/2" }, { MMHITTAB, "mmhittab" }, { GLIDEPOINT, "glidepoint" }, ! { INTELLIMOUSE,"intellimouse" }, { XQUE, "xqueue" }, { OSMOUSE, "osmouse" }, { -1, "" }, --- 199,214 ---- { PS_2, "ps/2" }, { MMHITTAB, "mmhittab" }, { GLIDEPOINT, "glidepoint" }, ! { IMSERIAL, "intellimouse" }, ! { THINKING, "thinkingmouse" }, ! { IMPS2, "imps/2" }, ! { THINKINGPS2,"thinkingmouseps/2" }, ! { MMANPLUSPS2,"mousemanplusps/2" }, ! { GLIDEPOINTPS2,"glidepointps/2" }, ! { NETPS2, "netmouseps/2" }, ! { NETSCROLLPS2,"netscrollps/2" }, ! { SYSMOUSE, "sysmouse" }, ! { AUTOMOUSE, "auto" }, { XQUE, "xqueue" }, { OSMOUSE, "osmouse" }, { -1, "" }, *************** *** 196,204 **** }; #endif /* INIT_CONFIG */ ! #define FONTPATH 1040 ! #define RGBPATH 1041 ! #define MODULEPATH 1042 #ifdef INIT_CONFIG static SymTabRec FilesTab[] = { --- 215,223 ---- }; #endif /* INIT_CONFIG */ ! #define FONTPATH 1045 ! #define RGBPATH 1046 ! #define MODULEPATH 1047 #ifdef INIT_CONFIG static SymTabRec FilesTab[] = { *************** *** 405,410 **** --- 424,430 ---- #define CHIPID 30 #define CHIPREV 31 #define MEMCLOCK 32 + #define LCDCLOCK 33 #define VGABASEADDR 100 #define S3REFCLK 101 #define S3BLANKDELAY 102 *************** *** 444,449 **** --- 464,470 ---- { TEXTCLOCKFRQ, "textclockfreq" }, { MEMCLOCK, "set_memclk" }, { MEMCLOCK, "set_mclk" }, + { LCDCLOCK, "set_lcdclk" }, { -1, "" }, }; #else *************** *** 517,524 **** [CHRIS-211092] */ #define P_PS2 6 /* PS/2 mouse */ #define P_MMHIT 7 /* MM_HitTab */ ! #define P_GLIDEPOINT 8 /* ALPS GlidePoint */ ! #define P_MSINTELLIMOUSE 9 /* Microsoft IntelliMouse */ #define EMULATE3 50 #define BAUDRATE 51 --- 538,554 ---- [CHRIS-211092] */ #define P_PS2 6 /* PS/2 mouse */ #define P_MMHIT 7 /* MM_HitTab */ ! #define P_GLIDEPOINT 8 /* ALPS serial GlidePoint */ ! #define P_IMSERIAL 9 /* Microsoft serial IntelliMouse */ ! #define P_THINKING 10 /* Kensington serial ThinkingMouse */ ! #define P_IMPS2 11 /* Microsoft PS/2 IntelliMouse */ ! #define P_THINKINGPS2 12 /* Kensington PS/2 ThinkingMouse */ ! #define P_MMANPLUSPS2 13 /* Logitech PS/2 MouseMan+ */ ! #define P_GLIDEPOINTPS2 14 /* ALPS PS/2 GlidePoint */ ! #define P_NETPS2 15 /* Genius PS/2 NetMouse */ ! #define P_NETSCROLLPS2 16 /* Genius PS/2 NetScroll */ ! #define P_SYSMOUSE 17 /* SysMouse */ ! #define P_AUTO 18 /* automatic */ #define EMULATE3 50 #define BAUDRATE 51 *************** *** 533,538 **** --- 563,571 ---- #define REPEATEDMIDDLE 59 #define DEVICE_NAME 60 #define ALWAYSCORE 61 + #define PRESOLUTION 62 + #define ZAXISMAPPING 63 + #define PBUTTONS 64 #ifdef INIT_CONFIG static SymTabRec PointerTab[] = { *************** *** 550,564 **** --- 583,611 ---- { CLEARRTS, "clearrts" }, { CHORDMIDDLE,"chordmiddle" }, { REPEATEDMIDDLE,"repeatedmiddle" }, + { PRESOLUTION,"resolution" }, #endif { DEVICE_NAME,"devicename" }, #ifdef XINPUT { ALWAYSCORE,"alwayscore" }, #endif + { ZAXISMAPPING, "zaxismapping" }, + { PBUTTONS, "buttons" }, { -1, "" }, }; #endif /* INIT_CONFIG */ + #define XAXIS 68 + #define YAXIS 69 + + #ifdef INIT_CONFIG + static SymTabRec ZMapTab[] = { + { XAXIS, "x" }, + { YAXIS, "y" }, + { -1, "" }, + }; + #endif /* INIT_CONFIG */ + /* OPTION is defined to 12 above */ #define MODES 70 #define VIRTUAL 71 *************** *** 643,648 **** --- 690,696 ---- #define XCONFIG_VGABASE 20 /* XF86Config or default */ #define XCONFIG_MODULEPATH 21 /* XF86Config or default */ #define XCONFIG_MEMCLOCK 22 /* XF86Config or default */ + #define XCONFIG_LCDCLOCK 23 /* XF86Config or default */ #define XCONFIG_GIVEN "(**)" #define XCONFIG_PROBED "(--)" *** ./programs/Xserver/hw/xfree86/common/xf86_Mouse.c@@/PUBLIC-LATEST Sun Aug 10 13:00:22 1997 --- xc/programs/Xserver/hw/xfree86/common/xf86_Mouse.c Fri Mar 6 16:35:22 1998 *************** *** 1,4 **** ! /* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86_Mouse.c,v 3.21.2.3 1997/07/27 02:41:13 dawes Exp $ */ /* * * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany. --- 1,4 ---- ! /* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86_Mouse.c,v 3.21.2.13 1998/02/24 19:05:56 hohndel Exp $ */ /* * * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany. *************** *** 24,30 **** * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ ! /* $TOG: xf86_Mouse.c /main/23 1997/08/10 12:58:58 kaleb $ */ /* * [JCH-96/01/21] Added fourth button support for P_GLIDEPOINT mouse protocol. --- 24,30 ---- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ ! /* $TOG: xf86_Mouse.c /main/24 1998/03/06 16:36:59 kaleb $ */ /* * [JCH-96/01/21] Added fourth button support for P_GLIDEPOINT mouse protocol. *************** *** 98,105 **** TRUE, /* MouseMan */ TRUE, /* PS/2 */ TRUE, /* Hitachi Tablet */ ! TRUE, /* ALPS GlidePoint */ ! TRUE, /* Microsoft IntelliMouse */ }; int xf86NumMouseTypes = sizeof(xf86SupportedMouseTypes) / --- 98,127 ---- TRUE, /* MouseMan */ TRUE, /* PS/2 */ TRUE, /* Hitachi Tablet */ ! TRUE, /* ALPS GlidePoint (serial) */ ! TRUE, /* Microsoft IntelliMouse (serial) */ ! TRUE, /* Kensington ThinkingMouse (serial) */ ! #if !defined(__FreeBSD__) && !defined(Lynx) ! TRUE, /* Microsoft IntelliMouse (PS/2) */ ! TRUE, /* Kensington ThinkingMouse (PS/2) */ ! TRUE, /* Logitech MouseMan+ (PS/2) */ ! TRUE, /* ALPS GlidePoint (PS/2) */ ! TRUE, /* Genius NetMouse (PS/2) */ ! TRUE, /* Genius NetScroll (PS/2) */ ! #else ! FALSE, /* Microsoft IntelliMouse (PS/2) */ ! FALSE, /* Kensington ThinkingMouse (PS/2) */ ! FALSE, /* Logitech MouseMan+ (PS/2) */ ! FALSE, /* ALPS GlidePoint (PS/2) */ ! FALSE, /* Genius NetMouse (PS/2) */ ! FALSE, /* Genius NetScroll (PS/2) */ ! #endif /* __FreeBSD__ */ ! TRUE, /* sysmouse */ ! #ifdef PNP_MOUSE ! TRUE, /* auto */ ! #else ! FALSE, /* auto */ ! #endif }; int xf86NumMouseTypes = sizeof(xf86SupportedMouseTypes) / *************** *** 126,131 **** --- 148,164 ---- (CS8 | CREAD | CLOCAL | HUPCL ), /* mmhitablet */ (CS7 | CREAD | CLOCAL | HUPCL ), /* GlidePoint */ (CS7 | CREAD | CLOCAL | HUPCL ), /* IntelliMouse */ + (CS7 | CREAD | CLOCAL | HUPCL ), /* ThinkingMouse */ + /* PS/2 variants */ + 0, /* IntelliMouse */ + 0, /* ThinkingMouse */ + 0, /* MouseMan+ */ + 0, /* GlidePoint */ + 0, /* NetMouse */ + 0, /* NetScroll */ + + (CS8 | CSTOPB | CREAD | CLOCAL | HUPCL ), /* sysmouse */ + 0, /* auto */ }; #endif /* ! MOUSE_PROTOCOL_IN_KERNEL */ *************** *** 151,156 **** --- 184,215 ---- * Sets up the mouse parameters */ + #ifndef MOUSE_PROTOCOL_IN_KERNEL + static unsigned char proto[][7] = { + /* hd_mask hd_id dp_mask dp_id bytes b4_mask b4_id */ + { 0x40, 0x40, 0x40, 0x00, 3, ~0x23, 0x00 }, /* MicroSoft */ + { 0xf8, 0x80, 0x00, 0x00, 5, 0x00, 0xff }, /* MouseSystems */ + { 0xe0, 0x80, 0x80, 0x00, 3, 0x00, 0xff }, /* MMSeries */ + { 0xe0, 0x80, 0x80, 0x00, 3, 0x00, 0xff }, /* Logitech */ + { 0xf8, 0x80, 0x00, 0x00, 5, 0x00, 0xff }, /* BusMouse */ + { 0x40, 0x40, 0x40, 0x00, 3, ~0x23, 0x00 }, /* MouseMan */ + { 0xc0, 0x00, 0x00, 0x00, 3, 0x00, 0xff }, /* PS/2 mouse */ + { 0xe0, 0x80, 0x80, 0x00, 3, 0x00, 0xff }, /* MM_HitTablet */ + { 0x40, 0x40, 0x40, 0x00, 3, ~0x33, 0x00 }, /* GlidePoint */ + { 0x40, 0x40, 0x40, 0x00, 3, ~0x3f, 0x00 }, /* IntelliMouse */ + { 0x40, 0x40, 0x40, 0x00, 3, ~0x33, 0x00 }, /* ThinkingMouse */ + /* PS/2 variants */ + { 0xc0, 0x00, 0x00, 0x00, 4, 0x00, 0xff }, /* IntelliMouse */ + { 0x80, 0x80, 0x00, 0x00, 3, 0x00, 0xff }, /* ThinkingMouse */ + { 0x08, 0x08, 0x00, 0x00, 3, 0x00, 0xff }, /* MouseMan+ */ + { 0xc0, 0x00, 0x00, 0x00, 3, 0x00, 0xff }, /* GlidePoint */ + { 0xc0, 0x00, 0x00, 0x00, 4, 0x00, 0xff }, /* NetMouse */ + { 0xc0, 0x00, 0x00, 0x00, 6, 0x00, 0xff }, /* NetScroll */ + + { 0xf8, 0x80, 0x00, 0x00, 5, 0x00, 0xff }, /* sysmouse */ + }; + #endif /* ! MOUSE_PROTOCOL_IN_KERNEL */ + void xf86SetupMouse(mouse) MouseDevPtr mouse; *************** *** 196,289 **** ** [CHRIS-211092] */ ! ! if (mouse->mseType == P_LOGIMAN) { ! xf86SetMouseSpeed(mouse, 1200, 1200, xf86MouseCflags[P_LOGIMAN]); ! write(mouse->mseFd, "*X", 2); ! xf86SetMouseSpeed(mouse, 1200, mouse->baudRate, ! xf86MouseCflags[P_LOGIMAN]); } ! else if (mouse->mseType != P_BM && mouse->mseType != P_PS2) { ! xf86SetMouseSpeed(mouse, 9600, mouse->baudRate, ! xf86MouseCflags[mouse->mseType]); ! xf86SetMouseSpeed(mouse, 4800, mouse->baudRate, ! xf86MouseCflags[mouse->mseType]); ! xf86SetMouseSpeed(mouse, 2400, mouse->baudRate, ! xf86MouseCflags[mouse->mseType]); ! xf86SetMouseSpeed(mouse, 1200, mouse->baudRate, ! xf86MouseCflags[mouse->mseType]); ! if (mouse->mseType == P_LOGI) ! { ! write(mouse->mseFd, "S", 1); ! xf86SetMouseSpeed(mouse, mouse->baudRate, mouse->baudRate, ! xf86MouseCflags[P_MM]); ! } ! if (mouse->mseType == P_MMHIT) ! { ! char speedcmd; ! /* ! * Initialize Hitachi PUMA Plus - Model 1212E to desired settings. ! * The tablet must be configured to be in MM mode, NO parity, ! * Binary Format. mouse->sampleRate controls the sensativity ! * of the tablet. We only use this tablet for it's 4-button puck ! * so we don't run in "Absolute Mode" ! */ ! write(mouse->mseFd, "z8", 2); /* Set Parity = "NONE" */ ! usleep(50000); ! write(mouse->mseFd, "zb", 2); /* Set Format = "Binary" */ ! usleep(50000); ! write(mouse->mseFd, "@", 1); /* Set Report Mode = "Stream" */ ! usleep(50000); ! write(mouse->mseFd, "R", 1); /* Set Output Rate = "45 rps" */ ! usleep(50000); ! write(mouse->mseFd, "I\x20", 2); /* Set Incrememtal Mode "20" */ ! usleep(50000); ! write(mouse->mseFd, "E", 1); /* Set Data Type = "Relative */ ! usleep(50000); ! /* These sample rates translate to 'lines per inch' on the Hitachi ! tablet */ ! if (mouse->sampleRate <= 40) speedcmd = 'g'; ! else if (mouse->sampleRate <= 100) speedcmd = 'd'; ! else if (mouse->sampleRate <= 200) speedcmd = 'e'; ! else if (mouse->sampleRate <= 500) speedcmd = 'h'; ! else if (mouse->sampleRate <= 1000) speedcmd = 'j'; ! else speedcmd = 'd'; ! write(mouse->mseFd, &speedcmd, 1); ! usleep(50000); ! write(mouse->mseFd, "\021", 1); /* Resume DATA output */ ! } ! else ! { ! if (mouse->sampleRate <= 0) write(mouse->mseFd, "O", 1); ! else if (mouse->sampleRate <= 15) write(mouse->mseFd, "J", 1); ! else if (mouse->sampleRate <= 27) write(mouse->mseFd, "K", 1); ! else if (mouse->sampleRate <= 42) write(mouse->mseFd, "L", 1); ! else if (mouse->sampleRate <= 60) write(mouse->mseFd, "R", 1); ! else if (mouse->sampleRate <= 85) write(mouse->mseFd, "M", 1); ! else if (mouse->sampleRate <= 125) write(mouse->mseFd, "Q", 1); ! else write(mouse->mseFd, "N", 1); ! } ! } ! #ifdef CLEARDTR_SUPPORT ! if (mouse->mseType == P_MSC && (mouse->mouseFlags & MF_CLEAR_DTR)) { ! int val = TIOCM_DTR; ! ioctl(mouse->mseFd, TIOCMBIC, &val); } ! if (mouse->mseType == P_MSC && (mouse->mouseFlags & MF_CLEAR_RTS)) ! { ! int val = TIOCM_RTS; ! ioctl(mouse->mseFd, TIOCMBIC, &val); ! } #endif #endif /* !MOUSE_PROTOCOL_IN_KERNEL || MACH386 */ } --- 255,610 ---- ** [CHRIS-211092] */ ! #if defined(__FreeBSD__) && defined(MOUSE_PROTO_SYSMOUSE) ! static struct { ! int dproto; ! int proto; ! } devproto[] = { ! { MOUSE_PROTO_MS, P_MS }, ! { MOUSE_PROTO_MSC, P_MSC }, ! { MOUSE_PROTO_LOGI, P_LOGI }, ! { MOUSE_PROTO_MM, P_MM }, ! { MOUSE_PROTO_LOGIMOUSEMAN, P_LOGIMAN }, ! { MOUSE_PROTO_BUS, P_BM }, ! { MOUSE_PROTO_INPORT, P_BM }, ! { MOUSE_PROTO_PS2, P_PS2 }, ! { MOUSE_PROTO_HITTAB, P_MMHIT }, ! { MOUSE_PROTO_GLIDEPOINT, P_GLIDEPOINT }, ! { MOUSE_PROTO_INTELLI, P_IMSERIAL }, ! { MOUSE_PROTO_THINK, P_THINKING }, ! { MOUSE_PROTO_SYSMOUSE, P_SYSMOUSE }, ! }; ! mousehw_t hw; ! mousemode_t mode; ! #endif /* __FreeBSD__ */ ! unsigned char *param; ! int paramlen; ! int ps2param; ! int i; ! ! if (mouse->mseType != P_AUTO) ! memcpy(mouse->protoPara, proto[mouse->mseType], ! sizeof(mouse->protoPara)); ! else ! memset(mouse->protoPara, 0, sizeof(mouse->protoPara)); ! ! #if defined(__FreeBSD__) && defined(MOUSE_PROTO_SYSMOUSE) ! /* set the driver operation level, if applicable */ ! i = 1; ! ioctl(mouse->mseFd, MOUSE_SETLEVEL, &i); ! ! /* interrogate the driver and get some intelligence on the device... */ ! hw.iftype = MOUSE_IF_UNKNOWN; ! hw.model = MOUSE_MODEL_GENERIC; ! ioctl(mouse->mseFd, MOUSE_GETHWINFO, &hw); ! mouse->mseModel = hw.model; ! if (ioctl(mouse->mseFd, MOUSE_GETMODE, &mode) == 0) { ! for (i = 0; i < sizeof(devproto)/sizeof(devproto[0]); ++i) ! if (mode.protocol == devproto[i].dproto) ! { ! mouse->mseType = devproto[i].proto; ! memcpy(mouse->protoPara, proto[mouse->mseType], ! sizeof(mouse->protoPara)); ! /* override some paramters */ ! mouse->protoPara[4] = mode.packetsize; ! mouse->protoPara[0] = mode.syncmask[0]; ! mouse->protoPara[1] = mode.syncmask[1]; ! break; ! } ! if (i >= sizeof(devproto)/sizeof(devproto[0])) ! ErrorF("xf86SetupMouse: Unknown mouse device protocol - %d\n", ! mode.protocol); } ! #endif /* __FreeBSD__ */ ! ! #ifdef PNP_MOUSE ! if (mouse->mseType == P_AUTO) { ! /* a PnP serial mouse? */ ! mouse->mseType = xf86GetPnPMouseProtocol(mouse); ! if (mouse->mseType < 0) ! mouse->mseType = P_AUTO; ! else ! memcpy(mouse->protoPara, proto[mouse->mseType], ! sizeof(mouse->protoPara)); ! } ! #endif ! param = NULL; ! paramlen = 0; ! ps2param = FALSE; ! switch (mouse->mseType) { ! case P_AUTO: ! if (!xf86AllowMouseOpenFail) ! FatalError("xf86SetupMouse: Cannot determine the mouse protocol\n"); ! else ! ErrorF("xf86SetupMouse: Cannot determine the mouse protocol\n"); ! break; ! case P_LOGI: /* Logitech Mice */ ! /* ! * The baud rate selection command must be sent at the current ! * baud rate; try all likely settings ! */ ! xf86SetMouseSpeed(mouse, 9600, mouse->baudRate, ! xf86MouseCflags[mouse->mseType]); ! xf86SetMouseSpeed(mouse, 4800, mouse->baudRate, ! xf86MouseCflags[mouse->mseType]); ! xf86SetMouseSpeed(mouse, 2400, mouse->baudRate, ! xf86MouseCflags[mouse->mseType]); ! xf86SetMouseSpeed(mouse, 1200, mouse->baudRate, ! xf86MouseCflags[mouse->mseType]); ! /* select MM series data format */ ! write(mouse->mseFd, "S", 1); ! xf86SetMouseSpeed(mouse, mouse->baudRate, mouse->baudRate, ! xf86MouseCflags[P_MM]); ! /* select report rate/frequency */ ! if (mouse->sampleRate <= 0) write(mouse->mseFd, "O", 1); ! else if (mouse->sampleRate <= 15) write(mouse->mseFd, "J", 1); ! else if (mouse->sampleRate <= 27) write(mouse->mseFd, "K", 1); ! else if (mouse->sampleRate <= 42) write(mouse->mseFd, "L", 1); ! else if (mouse->sampleRate <= 60) write(mouse->mseFd, "R", 1); ! else if (mouse->sampleRate <= 85) write(mouse->mseFd, "M", 1); ! else if (mouse->sampleRate <= 125) write(mouse->mseFd, "Q", 1); ! else write(mouse->mseFd, "N", 1); ! break; ! case P_LOGIMAN: ! xf86SetMouseSpeed(mouse, 1200, 1200, xf86MouseCflags[mouse->mseType]); ! write(mouse->mseFd, "*X", 2); ! xf86SetMouseSpeed(mouse, 1200, mouse->baudRate, ! xf86MouseCflags[mouse->mseType]); ! break; ! case P_MMHIT: /* MM_HitTablet */ ! { ! char speedcmd; ! xf86SetMouseSpeed(mouse, mouse->baudRate, mouse->baudRate, ! xf86MouseCflags[mouse->mseType]); ! /* ! * Initialize Hitachi PUMA Plus - Model 1212E to desired settings. ! * The tablet must be configured to be in MM mode, NO parity, ! * Binary Format. mouse->sampleRate controls the sensativity ! * of the tablet. We only use this tablet for it's 4-button puck ! * so we don't run in "Absolute Mode" ! */ ! write(mouse->mseFd, "z8", 2); /* Set Parity = "NONE" */ ! usleep(50000); ! write(mouse->mseFd, "zb", 2); /* Set Format = "Binary" */ ! usleep(50000); ! write(mouse->mseFd, "@", 1); /* Set Report Mode = "Stream" */ ! usleep(50000); ! write(mouse->mseFd, "R", 1); /* Set Output Rate = "45 rps" */ ! usleep(50000); ! write(mouse->mseFd, "I\x20", 2); /* Set Incrememtal Mode "20" */ ! usleep(50000); ! write(mouse->mseFd, "E", 1); /* Set Data Type = "Relative */ ! usleep(50000); ! /* These sample rates translate to 'lines per inch' on the Hitachi ! tablet */ ! if (mouse->sampleRate <= 40) speedcmd = 'g'; ! else if (mouse->sampleRate <= 100) speedcmd = 'd'; ! else if (mouse->sampleRate <= 200) speedcmd = 'e'; ! else if (mouse->sampleRate <= 500) speedcmd = 'h'; ! else if (mouse->sampleRate <= 1000) speedcmd = 'j'; ! else speedcmd = 'd'; ! write(mouse->mseFd, &speedcmd, 1); ! usleep(50000); ! write(mouse->mseFd, "\021", 1); /* Resume DATA output */ ! } ! break; ! ! case P_THINKING: /* ThinkingMouse */ { ! fd_set fds; ! char *s; ! char c; ! ! xf86SetMouseSpeed(mouse, 1200, mouse->baudRate, ! xf86MouseCflags[mouse->mseType]); ! /* this mouse may send a PnP ID string, ignore it */ ! usleep(200000); ! xf86FlushInput(mouse->mseFd); ! /* send the command to initialize the beast */ ! for (s = "E5E5"; *s; ++s) { ! write(mouse->mseFd, s, 1); ! FD_ZERO(&fds); ! FD_SET(mouse->mseFd, &fds); ! if (select(FD_SETSIZE, &fds, NULL, NULL, NULL) <= 0) ! break; ! read(mouse->mseFd, &c, 1); ! if (c != *s) ! break; ! } } ! break; ! ! case P_MSC: /* MouseSystems Corp */ ! xf86SetMouseSpeed(mouse, mouse->baudRate, mouse->baudRate, ! xf86MouseCflags[mouse->mseType]); ! #ifdef CLEARDTR_SUPPORT ! if (mouse->mouseFlags & MF_CLEAR_DTR) ! { ! i = TIOCM_DTR; ! ioctl(mouse->mseFd, TIOCMBIC, &i); ! } ! if (mouse->mouseFlags & MF_CLEAR_RTS) ! { ! i = TIOCM_RTS; ! ioctl(mouse->mseFd, TIOCMBIC, &i); ! } #endif + break; + + #if defined(__FreeBSD__) && defined(MOUSE_PROTO_SYSMOUSE) + case P_SYSMOUSE: + if (hw.iftype == MOUSE_IF_SYSMOUSE || hw.iftype == MOUSE_IF_UNKNOWN) + xf86SetMouseSpeed(mouse, mouse->baudRate, mouse->baudRate, + xf86MouseCflags[mouse->mseType]); + /* fall through */ + + case P_PS2: /* standard PS/2 mouse */ + case P_BM: /* bus/InPort mouse */ + mode.rate = + (mouse->sampleRate > 0) ? mouse->sampleRate : -1; + mode.resolution = + (mouse->resolution > 0) ? mouse->resolution : -1; + mode.accelfactor = -1; + mode.level = -1; + ioctl(mouse->mseFd, MOUSE_SETMODE, &mode); + break; + #else + case P_SYSMOUSE: + xf86SetMouseSpeed(mouse, mouse->baudRate, mouse->baudRate, + xf86MouseCflags[mouse->mseType]); + break; + + case P_PS2: /* standard PS/2 mouse */ + ps2param = TRUE; + break; + + case P_BM: /* bus/InPort mouse */ + break; + #endif /* __FreeBSD__ */ + + case P_IMPS2: /* IntelliMouse */ + { + static unsigned char s[] = { 243, 200, 243, 100, 243, 80, }; + + param = s; + paramlen = sizeof(s); + ps2param = TRUE; + } + break; + + case P_NETPS2: /* NetMouse, NetMouse Pro, Mie Mouse */ + case P_NETSCROLLPS2: /* NetScroll */ + { + static unsigned char s[] = { 232, 3, 230, 230, 230, }; + + param = s; + paramlen = sizeof(s); + ps2param = TRUE; + } + break; + + case P_MMANPLUSPS2: /* MouseMan+, FirstMouse+ */ + { + static unsigned char s[] = { 230, 232, 0, 232, 3, 232, 2, 232, 1, + 230, 232, 3, 232, 1, 232, 2, 232, 3, }; + param = s; + paramlen = sizeof(s); + ps2param = TRUE; + } + break; + + case P_GLIDEPOINTPS2: /* GlidePoint */ + ps2param = TRUE; + break; + + case P_THINKINGPS2: /* ThinkingMouse */ + { + static unsigned char s[] = { 243, 10, 232, 0, 243, 20, 243, 60, + 243, 40, 243, 20, 243, 20, 243, 60, + 243, 40, 243, 20, 243, 20, }; + param = s; + paramlen = sizeof(s); + ps2param = TRUE; + } + break; + + default: + xf86SetMouseSpeed(mouse, mouse->baudRate, mouse->baudRate, + xf86MouseCflags[mouse->mseType]); + break; + } + + if (paramlen > 0) + { + #ifdef EXTMOUSEDEBUG + char c[2]; + for (i = 0; i < paramlen; ++i) + { + if (write(mouse->mseFd, ¶m[i], 1) != 1) + ErrorF("xf86SetupMouse: Write to mouse failed (%s)\n", + strerror(errno)); + usleep(30000); + read(mouse->mseFd, c, 1); + ErrorF("xf86SetupMouse: got %02x\n", c[0]); + } + #else + if (write(mouse->mseFd, param, paramlen) != paramlen) + ErrorF("xf86SetupMouse: Write to mouse failed (%s)\n", + strerror(errno)); + #endif + usleep(30000); + xf86FlushInput(mouse->mseFd); + } + if (ps2param) + { + unsigned char c[2]; + + c[0] = 246; /* default settings */ + write(mouse->mseFd, c, 1); + c[0] = 230; /* 1:1 scaling */ + write(mouse->mseFd, c, 1); + c[0] = 244; /* enable mouse */ + write(mouse->mseFd, c, 1); + if (mouse->sampleRate > 0) + { + c[0] = 243; /* set sampling rate */ + if (mouse->sampleRate >= 200) + c[1] = 200; + else if (mouse->sampleRate >= 100) + c[1] = 100; + else if (mouse->sampleRate >= 60) + c[1] = 60; + else if (mouse->sampleRate >= 40) + c[1] = 40; + else + c[1] = 20; + write(mouse->mseFd, c, 2); + } + if (mouse->resolution > 0) + { + c[0] = 232; /* set device resolution */ + if (mouse->resolution >= 200) + c[1] = 3; + else if (mouse->resolution >= 100) + c[1] = 2; + else if (mouse->resolution >= 50) + c[1] = 1; + else + c[1] = 0; + write(mouse->mseFd, c, 2); + } + usleep(30000); + xf86FlushInput(mouse->mseFd); + } + #endif /* !MOUSE_PROTOCOL_IN_KERNEL || MACH386 */ } *************** *** 294,319 **** unsigned char *rBuf; int nBytes; { ! int i, buttons, dx, dy; static int pBufP = 0; static unsigned char pBuf[8]; MouseDevPtr mouse = MOUSE_DEV(device); ! static unsigned char proto[10][5] = { ! /* hd_mask hd_id dp_mask dp_id nobytes */ ! { 0x40, 0x40, 0x40, 0x00, 3 }, /* MicroSoft */ ! { 0xf8, 0x80, 0x00, 0x00, 5 }, /* MouseSystems */ ! { 0xe0, 0x80, 0x80, 0x00, 3 }, /* MMSeries */ ! { 0xe0, 0x80, 0x80, 0x00, 3 }, /* Logitech */ ! { 0xf8, 0x80, 0x00, 0x00, 5 }, /* BusMouse */ ! { 0x40, 0x40, 0x40, 0x00, 3 }, /* MouseMan ! [CHRIS-211092] */ ! { 0xc0, 0x00, 0x00, 0x00, 3 }, /* PS/2 mouse */ ! { 0xe0, 0x80, 0x80, 0x00, 3 }, /* MM_HitTablet */ ! { 0x40, 0x40, 0x40, 0x00, 3 }, /* GlidePoint */ ! { 0x40, 0x40, 0x40, 0x00, 4 } /* IntelliMouse */ ! }; ! for ( i=0; i < nBytes; i++) { /* * Hack for resyncing: We check here for a package that is: --- 615,631 ---- unsigned char *rBuf; int nBytes; { ! int i, buttons, dx, dy, dz; static int pBufP = 0; static unsigned char pBuf[8]; MouseDevPtr mouse = MOUSE_DEV(device); ! #ifdef EXTMOUSEDEBUG ! ErrorF("received %d bytes ",nBytes); ! for ( i=0; i < nBytes; i++) ! ErrorF("%2x ",rBuf[i]); ! ErrorF("\n"); ! #endif for ( i=0; i < nBytes; i++) { /* * Hack for resyncing: We check here for a package that is: *************** *** 340,353 **** #if !defined(__NetBSD__) mouse->mseType != P_PS2 && #endif ! ((rBuf[i] & proto[mouse->mseType][2]) != proto[mouse->mseType][3] || rBuf[i] == 0x80)) { pBufP = 0; /* skip package */ } ! if (pBufP == 0 && ! (rBuf[i] & proto[mouse->mseType][0]) != proto[mouse->mseType][1]) { /* * Hack for Logitech MouseMan Mouse - Middle button --- 652,668 ---- #if !defined(__NetBSD__) mouse->mseType != P_PS2 && #endif ! ((rBuf[i] & mouse->protoPara[2]) != mouse->protoPara[3] || rBuf[i] == 0x80)) { pBufP = 0; /* skip package */ } ! if (pBufP == 0 && (rBuf[i] & mouse->protoPara[0]) != mouse->protoPara[1]) ! continue; ! ! if (pBufP >= mouse->protoPara[4] ! && (rBuf[i] & mouse->protoPara[0]) != mouse->protoPara[1]) { /* * Hack for Logitech MouseMan Mouse - Middle button *************** *** 374,407 **** * half of the reverse-map may remain unchanged. */ ! /* ! * The order of tests in the following expression ! * is an attempt to optimize wrt the likeliness of the ! * various cases, think twice before simplifying. */ ! if ( ( (char)(rBuf[i] & ~0x23) != 0 ! && ( (char) (rBuf[i] & ~0x33) != 0 ! || mouse->mseType != P_GLIDEPOINT)) ! || ( mouse->mseType != P_MS ! && mouse->mseType != P_LOGIMAN ! && mouse->mseType != P_GLIDEPOINT)) continue; ! buttons = ((int)(rBuf[i] & 0x20) >> 4) ! | (mouse->lastButtons & 0x05); ! if (mouse->mseType == P_GLIDEPOINT) ! buttons |= ((int)(rBuf[i] & 0x10) >> 1); ! xf86PostMseEvent(device, buttons, 0, 0); ! continue; /* skip package */ ! } pBuf[pBufP++] = rBuf[i]; ! if (pBufP != proto[mouse->mseType][4]) continue; /* * assembly full package */ switch(mouse->mseType) { case P_LOGIMAN: /* MouseMan / TrackMan [CHRIS-211092] */ --- 689,755 ---- * half of the reverse-map may remain unchanged. */ ! /* ! * [KAZU-030897] ! * Receive the fourth byte only when preceeding three bytes have ! * been detected (pBufP >= mouse->protoPara[4]). In the previous ! * versions, the test was pBufP == 0; we may have mistakingly ! * received a byte even if we didn't see anything preceeding ! * the byte. */ ! if ((rBuf[i] & mouse->protoPara[5]) != mouse->protoPara[6]) ! { ! pBufP = 0; ! continue; ! } ! dx = dy = dz = 0; ! buttons = 0; ! switch(mouse->mseType) { ! /* ! * [KAZU-221197] ! * IntelliMouse, NetMouse (including NetMouse Pro) and Mie Mouse ! * always send the fourth byte, whereas the fourth byte is ! * optional for GlidePoint and ThinkingMouse. The fourth byte ! * is also optional for MouseMan+ and FirstMouse+ in their ! * native mode. It is always sent if they are in the IntelliMouse ! * compatible mode. ! */ ! case P_IMSERIAL: /* IntelliMouse, NetMouse, Mie Mouse, ! MouseMan+ */ ! dz = (rBuf[i] & 0x08) ? (rBuf[i] & 0x0f) - 16 : (rBuf[i] & 0x0f); ! buttons |= ((int)(rBuf[i] & 0x10) >> 3) ! | ((int)(rBuf[i] & 0x20) >> 2) ! | (mouse->lastButtons & 0x05); ! break; + case P_GLIDEPOINT: + case P_THINKING: + buttons |= ((int)(rBuf[i] & 0x10) >> 1); + /* fall through */ + default: + buttons |= ((int)(rBuf[i] & 0x20) >> 4) | (mouse->lastButtons & 0x05); + break; + } + pBufP = 0; + goto post_event; + } + + if (pBufP >= mouse->protoPara[4]) + pBufP = 0; pBuf[pBufP++] = rBuf[i]; ! if (pBufP != mouse->protoPara[4]) continue; ! /* * assembly full package */ + dz = 0; + #ifdef EXTMOUSEDEBUG + ErrorF("packet %2x %2x %2x %2x\n",pBuf[0],pBuf[1],pBuf[2],pBuf[3]); + #endif switch(mouse->mseType) { case P_LOGIMAN: /* MouseMan / TrackMan [CHRIS-211092] */ *************** *** 410,426 **** buttons = (((int) pBuf[0] & 0x30) == 0x30) ? 2 : ((int)(pBuf[0] & 0x20) >> 3) | ((int)(pBuf[0] & 0x10) >> 4); ! else { buttons = (mouse->lastButtons & 2) | ((int)(pBuf[0] & 0x20) >> 3) | ((int)(pBuf[0] & 0x10) >> 4); - } dx = (char)(((pBuf[0] & 0x03) << 6) | (pBuf[1] & 0x3F)); dy = (char)(((pBuf[0] & 0x0C) << 4) | (pBuf[2] & 0x3F)); break; case P_GLIDEPOINT: /* ALPS GlidePoint */ ! buttons = (mouse->lastButtons & (8 + 2)) | ((int)(pBuf[0] & 0x20) >> 3) | ((int)(pBuf[0] & 0x10) >> 4); dx = (char)(((pBuf[0] & 0x03) << 6) | (pBuf[1] & 0x3F)); --- 758,775 ---- buttons = (((int) pBuf[0] & 0x30) == 0x30) ? 2 : ((int)(pBuf[0] & 0x20) >> 3) | ((int)(pBuf[0] & 0x10) >> 4); ! else buttons = (mouse->lastButtons & 2) | ((int)(pBuf[0] & 0x20) >> 3) | ((int)(pBuf[0] & 0x10) >> 4); dx = (char)(((pBuf[0] & 0x03) << 6) | (pBuf[1] & 0x3F)); dy = (char)(((pBuf[0] & 0x0C) << 4) | (pBuf[2] & 0x3F)); break; case P_GLIDEPOINT: /* ALPS GlidePoint */ ! case P_THINKING: /* ThinkingMouse */ ! case P_IMSERIAL: /* IntelliMouse, NetMouse, Mie Mouse, MouseMan+ */ ! buttons = (mouse->lastButtons & (8 + 2)) | ((int)(pBuf[0] & 0x20) >> 3) | ((int)(pBuf[0] & 0x10) >> 4); dx = (char)(((pBuf[0] & 0x03) << 6) | (pBuf[1] & 0x3F)); *************** *** 458,464 **** break; #if !defined(__NetBSD__) ! case P_PS2: /* PS/2 mouse */ buttons = (pBuf[0] & 0x04) >> 1 | /* Middle */ (pBuf[0] & 0x02) >> 1 | /* Right */ (pBuf[0] & 0x01) << 2; /* Left */ --- 807,813 ---- break; #if !defined(__NetBSD__) ! case P_PS2: /* PS/2 mouse */ buttons = (pBuf[0] & 0x04) >> 1 | /* Middle */ (pBuf[0] & 0x02) >> 1 | /* Right */ (pBuf[0] & 0x01) << 2; /* Left */ *************** *** 465,505 **** dx = (pBuf[0] & 0x10) ? pBuf[1]-256 : pBuf[1]; dy = (pBuf[0] & 0x20) ? -(pBuf[2]-256) : -pBuf[2]; break; ! #endif ! case P_MSINTELLIMOUSE: /* Microsoft IntelliMouse */ ! dx = (char) ((pBuf[0] & 0x03) << 6 | pBuf[1]); ! dy = (char) ((pBuf[0] & 0x0c) << 4 | pBuf[2]); ! buttons = ! ((pBuf[0] & 0x10) ? 1 : 0) | ! ((pBuf[3] & 0x10) ? 2 : 0) | ! ((pBuf[0] & 0x20) ? 4 : 0) | ! ((pBuf[3] & 0x08) ? 8 : 0) | ! (((!(pBuf[3] & 0x08)) && (pBuf[3] & 0x07)) ? 16 : 0); ! /* ! * { ! * static int seqno = 0; ! * fprintf (stderr, "%d - dx=%4d dy=%4d buttons=%c%c%c%c%c\n", ! * seqno++, dx, dy, ! * (buttons & 1) ? 'R' : ' ', ! * (buttons & 2) ? 'M' : ' ', ! * (buttons & 4) ? 'L' : ' ', ! * (buttons & 8) ? 'U' : ' ', ! * (buttons & 16) ? 'D' : ' '); ! * } ! */ break; default: /* There's a table error */ ! continue; } xf86PostMseEvent(device, buttons, dx, dy); ! if ((mouse->mseType == P_MSINTELLIMOUSE) && ! (buttons & (8 + 16))) { ! xf86PostMseEvent(device, buttons & ~ (8 + 16), 0, 0); ! } ! pBufP = 0; } } #endif /* MOUSE_PROTOCOL_IN_KERNEL */ --- 814,943 ---- dx = (pBuf[0] & 0x10) ? pBuf[1]-256 : pBuf[1]; dy = (pBuf[0] & 0x20) ? -(pBuf[2]-256) : -pBuf[2]; break; ! ! /* PS/2 mouse variants */ ! case P_IMPS2: /* IntelliMouse PS/2 */ ! case P_NETPS2: /* NetMouse PS/2 */ ! buttons = (pBuf[0] & 0x04) >> 1 | /* Middle */ ! (pBuf[0] & 0x02) >> 1 | /* Right */ ! (pBuf[0] & 0x01) << 2; /* Left */ ! dx = (pBuf[0] & 0x10) ? pBuf[1]-256 : pBuf[1]; ! dy = (pBuf[0] & 0x20) ? -(pBuf[2]-256) : -pBuf[2]; ! dz = (char)pBuf[3]; break; + + case P_MMANPLUSPS2: /* MouseMan+ PS/2 */ + if ((pBuf[0] & ~0x07) == 0xc8) { + /* extended data packet */ + buttons = (pBuf[0] & 0x04) >> 1 | /* Middle */ + (pBuf[0] & 0x02) >> 1 | /* Right */ + (pBuf[0] & 0x01) << 2 | /* Left */ + ((pBuf[2] & 0x10) ? 0x08 : 0);/* fourth button */ + dx = dy = 0; + dz = (pBuf[1] & 0x08) ? (pBuf[2] & 0x0f) - 16 : (pBuf[2] & 0x0f); + } else { + buttons = (pBuf[0] & 0x04) >> 1 | /* Middle */ + (pBuf[0] & 0x02) >> 1 | /* Right */ + (pBuf[0] & 0x01) << 2 | /* Left */ + (mouse->lastButtons & ~0x07); + dx = (pBuf[0] & 0x10) ? pBuf[1]-256 : pBuf[1]; + dy = (pBuf[0] & 0x20) ? -(pBuf[2]-256) : -pBuf[2]; + } + break; + + case P_GLIDEPOINTPS2: /* GlidePoint PS/2 */ + buttons = (pBuf[0] & 0x04) >> 1 | /* Middle */ + (pBuf[0] & 0x02) >> 1 | /* Right */ + (pBuf[0] & 0x01) << 2 | /* Left */ + ((pBuf[0] & 0x08) ? 0 : 0x08);/* fourth button */ + dx = (pBuf[0] & 0x10) ? pBuf[1]-256 : pBuf[1]; + dy = (pBuf[0] & 0x20) ? -(pBuf[2]-256) : -pBuf[2]; + break; + + case P_NETSCROLLPS2: /* NetScroll PS/2 */ + buttons = (pBuf[0] & 0x04) >> 1 | /* Middle */ + (pBuf[0] & 0x02) >> 1 | /* Right */ + (pBuf[0] & 0x01) << 2 | /* Left */ + ((pBuf[3] & 0x02) ? 0x08 : 0);/* fourth button */ + dx = (pBuf[0] & 0x10) ? pBuf[1]-256 : pBuf[1]; + dy = (pBuf[0] & 0x20) ? -(pBuf[2]-256) : -pBuf[2]; + dz = (pBuf[3] & 0x10) ? pBuf[4] - 256 : pBuf[4]; + break; + + case P_THINKINGPS2: /* ThinkingMouse PS/2 */ + buttons = (pBuf[0] & 0x04) >> 1 | /* Middle */ + (pBuf[0] & 0x02) >> 1 | /* Right */ + (pBuf[0] & 0x01) << 2 | /* Left */ + ((pBuf[0] & 0x08) ? 0x08 : 0);/* fourth button */ + dx = (pBuf[0] & 0x10) ? pBuf[1]-256 : pBuf[1]; + dy = (pBuf[0] & 0x20) ? -(pBuf[2]-256) : -pBuf[2]; + break; + + #endif /* !__NetBSD__ */ + + case P_SYSMOUSE: /* sysmouse */ + buttons = (~pBuf[0]) & 0x07; + dx = (char)(pBuf[1]) + (char)(pBuf[3]); + dy = - ((char)(pBuf[2]) + (char)(pBuf[4])); + /* FreeBSD sysmouse sends additional data bytes */ + if (mouse->protoPara[4] >= 8) + { + dz = ((char)(pBuf[5] << 1) + (char)(pBuf[6] << 1))/2; + buttons |= (int)(~pBuf[7] & 0x07) << 3; + } + break; + default: /* There's a table error */ ! continue; } + post_event: + /* map the Z axis movement */ + switch (mouse->negativeZ) { + case 0: /* do nothing */ + break; + case MSE_MAPTOX: + if (dz != 0) + { + dx = dz; + dz = 0; + } + break; + case MSE_MAPTOY: + if (dz != 0) + { + dy = dz; + dz = 0; + } + break; + default: /* buttons */ + buttons &= ~(mouse->negativeZ | mouse->positiveZ); + if (dz < 0) + buttons |= mouse->negativeZ; + else if (dz > 0) + buttons |= mouse->positiveZ; + dz = 0; + break; + } + + /* post an event */ xf86PostMseEvent(device, buttons, dx, dy); ! /* ! * If dz has been mapped to a button `down' event, we need to cook ! * up a corresponding button `up' event. ! */ ! if ((mouse->negativeZ > 0) ! && (buttons & (mouse->negativeZ | mouse->positiveZ))) ! { ! buttons &= ~(mouse->negativeZ | mouse->positiveZ); ! xf86PostMseEvent(device, buttons, 0, 0); ! } ! /* ! * We don't reset pBufP here yet, as there may be an additional data ! * byte in some protocols. See above. ! */ } } #endif /* MOUSE_PROTOCOL_IN_KERNEL */ *************** *** 624,629 **** --- 1062,1068 ---- { LocalDevicePtr local = (LocalDevicePtr) xalloc(sizeof(LocalDeviceRec)); MouseDevPtr mouse = (MouseDevPtr) xalloc(sizeof(MouseDevRec)); + int i; local->name = "MOUSE"; local->type_name = "Mouse"; *************** *** 646,654 **** --- 1085,1098 ---- mouse->mseFd = -1; mouse->mseDevice = ""; mouse->mseType = -1; + mouse->mseModel = 0; mouse->baudRate = -1; mouse->oldBaudRate = -1; mouse->sampleRate = -1; + mouse->resolution = 0; + mouse->buttons = MSE_DFLTBUTTONS; + mouse->negativeZ = 0; + mouse->positiveZ = 0; mouse->local = local; #ifdef EXTMOUSEDEBUG *** /dev/null Tue Jun 30 11:45:43 1998 --- xc/programs/Xserver/hw/xfree86/common/xf86_PnPMouse.c Fri Mar 6 16:35:32 1998 *************** *** 0 **** --- 1,517 ---- + /* $TOG: xf86_PnPMouse.c /main/1 1998/03/06 16:37:10 kaleb $ */ + + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86_PnPMouse.c,v 1.1.2.4 1998/03/02 09:58:23 dawes Exp $ */ + + /* + * Copyright 1998 by Kazutaka YOKOTA + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Kazutaka YOKOTA not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Kazutaka YOKOTA makes no representations + * about the suitability of this software for any purpose. It is provided + * "as is" without express or implied warranty. + * + * KAZUTAKA YOKOTA DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL KAZUTAKA YOKOTA BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + #define NEED_EVENTS + #include "X.h" + #include "Xproto.h" + #include "inputstr.h" + #include "scrnintstr.h" + + #include "compiler.h" + + #include "xf86Procs.h" + #include "xf86_OSlib.h" + #include "xf86_Config.h" + + #ifdef ISC + #define TIOCMGET 0x5415 + #define TIOCMBIS 0x5416 + #define TIOCMSET 0x5418 + #define TIOCM_DTR 0x002 + #define TIOCM_RTS 0x004 + #endif + + /* serial PnP ID string */ + typedef struct { + int revision; /* PnP revision, 100 for 1.00 */ + char *eisaid; /* EISA ID including mfr ID and product ID */ + char *serial; /* serial No, optional */ + char *class; /* device class, optional */ + char *compat; /* list of compatible drivers, optional */ + char *description; /* product description, optional */ + int neisaid; /* length of the above fields... */ + int nserial; + int nclass; + int ncompat; + int ndescription; + } pnpid_t; + + /* symbol table entry */ + typedef struct { + char *name; + int val; + } symtab_t; + + /* PnP EISA/product IDs */ + static symtab_t pnpprod[] = { + { "KML0001", P_THINKING }, /* Kensignton ThinkingMouse */ + { "MSH0001", P_IMSERIAL }, /* MS IntelliMouse */ + { "MSH0004", P_IMSERIAL }, /* MS IntelliMouse TrackBall */ + { "KYEEZ00", P_MS }, /* Genius EZScroll */ + { "KYE0001", P_MS }, /* Genius PnP Mouse */ + { "KYE0003", P_IMSERIAL }, /* Genius NetMouse */ + { "LGI800C", P_IMSERIAL }, /* Logitech MouseMan (4 button model) */ + { "LGI8050", P_IMSERIAL }, /* Logitech MouseMan+ */ + { "LGI8051", P_IMSERIAL }, /* Logitech FirstMouse+ */ + { "LGI8001", P_LOGIMAN }, /* Logitech serial */ + + { "PNP0F00", P_BM }, /* MS bus */ + { "PNP0F01", P_MS }, /* MS serial */ + { "PNP0F02", P_BM }, /* MS InPort */ + { "PNP0F03", P_PS2 }, /* MS PS/2 */ + /* + * EzScroll returns PNP0F04 in the compatible device field; but it + * doesn't look compatible... XXX + */ + { "PNP0F04", P_MSC }, /* MouseSystems */ + { "PNP0F05", P_MSC }, /* MouseSystems */ + #if notyet + { "PNP0F06", P_??? }, /* Genius Mouse */ + { "PNP0F07", P_??? }, /* Genius Mouse */ + #endif + { "PNP0F08", P_LOGIMAN }, /* Logitech serial */ + { "PNP0F09", P_MS }, /* MS BallPoint serial */ + { "PNP0F0A", P_MS }, /* MS PnP serial */ + { "PNP0F0B", P_MS }, /* MS PnP BallPoint serial */ + { "PNP0F0C", P_MS }, /* MS serial comatible */ + { "PNP0F0D", P_BM }, /* MS InPort comatible */ + { "PNP0F0E", P_PS2 }, /* MS PS/2 comatible */ + { "PNP0F0F", P_MS }, /* MS BallPoint comatible */ + #if notyet + { "PNP0F10", P_??? }, /* TI QuickPort */ + #endif + { "PNP0F11", P_BM }, /* MS bus comatible */ + { "PNP0F12", P_PS2 }, /* Logitech PS/2 */ + { "PNP0F13", P_PS2 }, /* PS/2 */ + #if notyet + { "PNP0F14", P_??? }, /* MS Kids Mouse */ + #endif + { "PNP0F15", P_BM }, /* Logitech bus */ + #if notyet + { "PNP0F16", P_??? }, /* Logitech SWIFT */ + #endif + { "PNP0F17", P_LOGIMAN }, /* Logitech serial compat */ + { "PNP0F18", P_BM }, /* Logitech bus compatible */ + { "PNP0F19", P_PS2 }, /* Logitech PS/2 compatible */ + #if notyet + { "PNP0F1A", P_??? }, /* Logitech SWIFT compatible */ + { "PNP0F1B", P_??? }, /* HP Omnibook */ + { "PNP0F1C", P_??? }, /* Compaq LTE TrackBall PS/2 */ + { "PNP0F1D", P_??? }, /* Compaq LTE TrackBall serial */ + { "PNP0F1E", P_??? }, /* MS Kidts Trackball */ + #endif + { NULL, -1 }, + }; + + static int + pnpgets( + #if NeedFunctionPrototypes + MouseDevPtr, + char * + #endif + ); + + static int + pnpparse( + #if NeedFunctionPrototypes + pnpid_t *, + char *, + int + #endif + ); + + static symtab_t * + pnpproto( + #if NeedFunctionPrototypes + pnpid_t * + #endif + ); + + static symtab_t * + gettoken( + #if NeedFunctionPrototypes + symtab_t *, + char *, + int + #endif + ); + + int + xf86GetPnPMouseProtocol(mouse) + MouseDevPtr mouse; + { + char buf[256]; /* PnP ID string may be up to 256 bytes long */ + pnpid_t pnpid; + symtab_t *t; + int len; + + if (((len = pnpgets(mouse, buf)) <= 0) || !pnpparse(&pnpid, buf, len)) + return -1; + if ((t = pnpproto(&pnpid)) == NULL) + return -1; + ErrorF("Mouse: protocol: %d\n", t->val); + return (t->val); + } + + /* + * Try to elicit a PnP ID as described in + * Microsoft, Hayes: "Plug and Play External COM Device Specification, + * rev 1.00", 1995. + * + * The routine does not fully implement the COM Enumerator as par Section + * 2.1 of the document. In particular, we don't have idle state in which + * the driver software monitors the com port for dynamic connection or + * removal of a device at the port, because `moused' simply quits if no + * device is found. + * + * In addition, as PnP COM device enumeration procedure slightly has + * changed since its first publication, devices which follow earlier + * revisions of the above spec. may fail to respond if the rev 1.0 + * procedure is used. XXX + */ + static int + pnpgets(mouse, buf) + MouseDevPtr mouse; + char *buf; + { + struct timeval timeout; + fd_set fds; + int i; + char c; + + #if 0 + /* + * This is the procedure described in rev 1.0 of PnP COM device spec. + * Unfortunately, some devices which comform to earlier revisions of + * the spec gets confused and do not return the ID string... + */ + + /* port initialization (2.1.2) */ + ioctl(mouse->mseFd, TIOCMGET, &i); + i |= TIOCM_DTR; /* DTR = 1 */ + i &= ~TIOCM_RTS; /* RTS = 0 */ + ioctl(mouse->mseFd, TIOCMSET, &i); + usleep(200000); + if ((ioctl(mouse->mseFd, TIOCMGET, &i) == -1) || ((i & TIOCM_DSR) == 0)) + goto disconnect_idle; + + /* port setup, 1st phase (2.1.3) */ + xf86SetMouseSpeed(mouse, 1200, 1200, (CS7 | CREAD | CLOCAL | HUPCL)); + i = TIOCM_DTR | TIOCM_RTS; /* DTR = 0, RTS = 0 */ + ioctl(mouse->mseFd, TIOCMBIC, &i); + usleep(200000); + i = TIOCM_DTR; /* DTR = 1, RTS = 0 */ + ioctl(mouse->mseFd, TIOCMBIS, &i); + usleep(200000); + + /* wait for response, 1st phase (2.1.4) */ + xf86FlushInput(mouse->mseFd); + i = TIOCM_RTS; /* DTR = 1, RTS = 1 */ + ioctl(mouse->mseFd, TIOCMBIS, &i); + + /* try to read something */ + FD_ZERO(&fds); + FD_SET(mouse->mseFd, &fds); + timeout.tv_sec = 0; + timeout.tv_usec = 200000; + if (select(FD_SETSIZE, &fds, NULL, NULL, &timeout) <= 0) { + + /* port setup, 2nd phase (2.1.5) */ + i = TIOCM_DTR | TIOCM_RTS; /* DTR = 0, RTS = 0 */ + ioctl(mouse->mseFd, TIOCMBIC, &i); + usleep(200000); + + /* wait for respose, 2nd phase (2.1.6) */ + xf86FlushInput(mouse->mseFd); + i = TIOCM_DTR | TIOCM_RTS; /* DTR = 1, RTS = 1 */ + ioctl(mouse->mseFd, TIOCMBIS, &i); + + /* try to read something */ + FD_ZERO(&fds); + FD_SET(mouse->mseFd, &fds); + timeout.tv_sec = 0; + timeout.tv_usec = 200000; + if (select(FD_SETSIZE, &fds, NULL, NULL, &timeout) <= 0) + goto connect_idle; + } + #else + /* + * This is a simplified procedure; it simply toggles RTS. + */ + xf86SetMouseSpeed(mouse, 1200, 1200, (CS7 | CREAD | CLOCAL | HUPCL)); + + ioctl(mouse->mseFd, TIOCMGET, &i); + i |= TIOCM_DTR; /* DTR = 1 */ + i &= ~TIOCM_RTS; /* RTS = 0 */ + ioctl(mouse->mseFd, TIOCMSET, &i); + usleep(200000); + + /* wait for response */ + xf86FlushInput(mouse->mseFd); + i = TIOCM_DTR | TIOCM_RTS; /* DTR = 1, RTS = 1 */ + ioctl(mouse->mseFd, TIOCMBIS, &i); + + /* try to read something */ + FD_ZERO(&fds); + FD_SET(mouse->mseFd, &fds); + timeout.tv_sec = 0; + timeout.tv_usec = 200000; + if (select(FD_SETSIZE, &fds, NULL, NULL, &timeout) <= 0) + goto connect_idle; + #endif + + /* collect PnP COM device ID (2.1.7) */ + i = 0; + usleep(200000); /* the mouse must send `Begin ID' within 200msec */ + while (read(mouse->mseFd, &c, 1) == 1) { + /* we may see "M", or "M3..." before `Begin ID' */ + if ((c == 0x08) || (c == 0x28)) { /* Begin ID */ + buf[i++] = c; + break; + } + } + if (i <= 0) { + /* we haven't seen `Begin ID' in time... */ + goto connect_idle; + } + + ++c; /* make it `End ID' */ + for (;;) { + FD_ZERO(&fds); + FD_SET(mouse->mseFd, &fds); + timeout.tv_sec = 0; + timeout.tv_usec = 200000; + if (select(FD_SETSIZE, &fds, NULL, NULL, &timeout) <= 0) + break; + + read(mouse->mseFd, &buf[i], 1); + if (buf[i++] == c) /* End ID */ + break; + if (i >= 256) + break; + } + if (buf[i - 1] != c) + goto connect_idle; + return i; + + /* + * According to PnP spec, we should set DTR = 1 and RTS = 0 while + * in idle state. But, `moused' shall set DTR = RTS = 1 and proceed, + * assuming there is something at the port even if it didn't + * respond to the PnP enumeration procedure. + */ + disconnect_idle: + i = TIOCM_DTR | TIOCM_RTS; /* DTR = 1, RTS = 1 */ + ioctl(mouse->mseFd, TIOCMBIS, &i); + connect_idle: + return 0; + } + + static int + pnpparse(id, buf, len) + pnpid_t *id; + char *buf; + int len; + { + char s[3]; + int offset; + int sum = 0; + int i, j; + + id->revision = 0; + id->eisaid = NULL; + id->serial = NULL; + id->class = NULL; + id->compat = NULL; + id->description = NULL; + id->neisaid = 0; + id->nserial = 0; + id->nclass = 0; + id->ncompat = 0; + id->ndescription = 0; + + offset = 0x28 - buf[0]; + + /* calculate checksum */ + for (i = 0; i < len - 3; ++i) { + sum += buf[i]; + buf[i] += offset; + } + sum += buf[len - 1]; + for (; i < len; ++i) + buf[i] += offset; + ErrorF("Mouse: PnP ID string: '%*.*s'\n", len, len, buf); + + /* revision */ + buf[1] -= offset; + buf[2] -= offset; + id->revision = ((buf[1] & 0x3f) << 6) | (buf[2] & 0x3f); + ErrorF("Mouse: PnP rev %d.%02d\n", id->revision / 100, id->revision % 100); + + /* EISA vender and product ID */ + id->eisaid = &buf[3]; + id->neisaid = 7; + + /* option strings */ + i = 10; + if (buf[i] == '\\') { + /* device serial # */ + for (j = ++i; i < len; ++i) { + if (buf[i] == '\\') + break; + } + if (i >= len) + i -= 3; + if (i - j == 8) { + id->serial = &buf[j]; + id->nserial = 8; + } + } + if (buf[i] == '\\') { + /* PnP class */ + for (j = ++i; i < len; ++i) { + if (buf[i] == '\\') + break; + } + if (i >= len) + i -= 3; + if (i > j + 1) { + id->class = &buf[j]; + id->nclass = i - j; + } + } + if (buf[i] == '\\') { + /* compatible driver */ + for (j = ++i; i < len; ++i) { + if (buf[i] == '\\') + break; + } + /* + * PnP COM spec prior to v0.96 allowed '*' in this field, + * it's not allowed now; just igore it. + */ + if (buf[j] == '*') + ++j; + if (i >= len) + i -= 3; + if (i > j + 1) { + id->compat = &buf[j]; + id->ncompat = i - j; + } + } + if (buf[i] == '\\') { + /* product description */ + for (j = ++i; i < len; ++i) { + if (buf[i] == ';') + break; + } + if (i >= len) + i -= 3; + if (i > j + 1) { + id->description = &buf[j]; + id->ndescription = i - j; + } + } + + /* checksum exists if there are any optional fields */ + if ((id->nserial > 0) || (id->nclass > 0) + || (id->ncompat > 0) || (id->ndescription > 0)) { + #if 0 + ErrorF("Mouse: PnP checksum: 0x%02X\n", sum); + #endif + sprintf(s, "%02X", sum & 0x0ff); + if (strncmp(s, &buf[len - 3], 2) != 0) { + #if 0 + /* + * Checksum error!! + * I found some mice do not comply with the PnP COM device + * spec regarding checksum... XXX + */ + return FALSE; + #endif + } + } + + return TRUE; + } + + static symtab_t * + pnpproto(id) + pnpid_t *id; + { + symtab_t *t; + int i, j; + + if (id->nclass > 0) + if (strncmp(id->class, "MOUSE", id->nclass) != 0) + /* this is not a mouse! */ + return NULL; + + if (id->neisaid > 0) { + t = gettoken(pnpprod, id->eisaid, id->neisaid); + if (t->val != -1) + return t; + } + + /* + * The 'Compatible drivers' field may contain more than one + * ID separated by ','. + */ + if (id->ncompat <= 0) + return NULL; + for (i = 0; i < id->ncompat; ++i) { + for (j = i; id->compat[i] != ','; ++i) + if (i >= id->ncompat) + break; + if (i > j) { + t = gettoken(pnpprod, id->compat + j, i - j); + if (t->val != -1) + return t; + } + } + + return NULL; + } + + /* name/val mapping */ + + static symtab_t * + gettoken(tab, s, len) + symtab_t *tab; + char *s; + int len; + { + int i; + + for (i = 0; tab[i].name != NULL; ++i) { + if (strncmp(tab[i].name, s, len) == 0) + break; + } + return &tab[i]; + } *** ./programs/Xserver/hw/xfree86/common/xf86_Option.h@@/PUBLIC-LATEST Sun Aug 10 13:00:28 1997 --- xc/programs/Xserver/hw/xfree86/common/xf86_Option.h Fri Mar 6 16:35:27 1998 *************** *** 1,4 **** ! /* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86_Option.h,v 3.65.2.8 1997/07/10 08:02:09 hohndel Exp $ */ /* * Copyright 1993 by David Wexelblat * --- 1,4 ---- ! /* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86_Option.h,v 3.65.2.12 1998/02/24 19:05:57 hohndel Exp $ */ /* * Copyright 1993 by David Wexelblat * *************** *** 21,27 **** * PERFORMANCE OF THIS SOFTWARE. * */ ! /* $TOG: xf86_Option.h /main/28 1997/08/10 12:59:03 kaleb $ */ #ifndef _XF86_OPTION_H #define _XF86_OPTION_H --- 21,27 ---- * PERFORMANCE OF THIS SOFTWARE. * */ ! /* $TOG: xf86_Option.h /main/29 1998/03/06 16:37:05 kaleb $ */ #ifndef _XF86_OPTION_H #define _XF86_OPTION_H *************** *** 155,160 **** --- 155,161 ---- #define OPTION_PCI_RETRY 137 /* Use PCI-retry instead of busy-waiting */ #define OPTION_NO_PCI_DISC 138 /* Disable PCI disconnect (S3) */ #define OPTION_NO_SPLIT_XFER 139 /* Disable split VRAM transfers to avoid pixel wrapping (S3) */ + #define OPTION_MGA_24BPP_FIX 140 /* change PLL for higher clocks at 24bpp */ /* Debugging options */ #define OPTION_SHOWCACHE 150 /* Allow cache to be seen (S3) */ *************** *** 211,217 **** #define OPTION_TGUI_PCI_READ_ON 211 /* Trident TGUI PCI burst read */ #define OPTION_TGUI_PCI_WRITE_ON 212 /* Trident TGUI PCI burst write */ ! #define OPTION_TGUI_MCLK_66 213 /* Run the TGUI at 66MHz MCLK */ /* more Memory options */ #define OPTION_FPM_VRAM 220 /* (s3v) */ --- 212,220 ---- #define OPTION_TGUI_PCI_READ_ON 211 /* Trident TGUI PCI burst read */ #define OPTION_TGUI_PCI_WRITE_ON 212 /* Trident TGUI PCI burst write */ ! #define OPTION_TGUI_TVOUT 213 /* Trident TV output force */ ! #define OPTION_CYBER_SHADOW 214 /* Trident Cyber Shadow registers */ ! #define OPTION_TGUI_MCLK_66 215 /* Trident MCLK at 66MHz */ /* more Memory options */ #define OPTION_FPM_VRAM 220 /* (s3v) */ *************** *** 250,255 **** --- 253,259 ---- #define CLOCK_OPTION_ICS1562 20 /* used for TGA server */ #define CLOCK_OPTION_S3AURORA 21 /* use S3 Aurora64V+ programmable clocks */ #define CLOCK_OPTION_S3TRIO64V2 22 /* use S3 Trio64V2 or ViRGE/DX/GX 170MHz clocks */ + #define CLOCK_OPTION_ICS5301 23 /* use ICS 5301 (ET4000W32i) */ /* * Table to map option strings to tokens. *************** *** 312,317 **** --- 316,323 ---- { "w32_interleave_off",OPTION_W32_INTERLEAVE_OFF }, { "tgui_pci_read_on", OPTION_TGUI_PCI_READ_ON }, { "tgui_pci_write_on",OPTION_TGUI_PCI_WRITE_ON }, + { "tgui_tvout", OPTION_TGUI_TVOUT }, + { "cyber_shadow", OPTION_CYBER_SHADOW }, { "tgui_mclk_66", OPTION_TGUI_MCLK_66 }, { "noaccel", OPTION_NOACCEL }, *************** *** 375,380 **** --- 381,387 ---- { "pci_retry", OPTION_PCI_RETRY }, { "no_pci_disconnect", OPTION_NO_PCI_DISC }, { "no_split_xfer", OPTION_NO_SPLIT_XFER }, + { "mga_24bpp_fix", OPTION_MGA_24BPP_FIX }, { "showcache", OPTION_SHOWCACHE }, { "fb_debug", OPTION_FB_DEBUG }, *************** *** 463,468 **** --- 470,476 ---- { "ch8398", CLOCK_OPTION_CH8398 }, /* Chrontel 8398 */ { "ati18818", CLOCK_OPTION_ICS2595 }, /* ATI18818, ICS2595 compatible */ { "et6000", CLOCK_OPTION_ET6000 }, /* ET6000 */ + { "ics5301", CLOCK_OPTION_ICS5301 }, /* ET4000 W32i version of S3 GenDAC/ICS5301 */ { "", -1 }, }; *** ./programs/Xserver/hw/xfree86/common_hw/Ch8391clk.c@@/PUBLIC-LATEST Sat Jul 19 10:03:20 1997 --- xc/programs/Xserver/hw/xfree86/common_hw/Ch8391clk.c Fri Mar 6 16:35:36 1998 *************** *** 1,4 **** ! /* $XFree86: xc/programs/Xserver/hw/xfree86/common_hw/Ch8391clk.c,v 3.6 1996/12/23 06:44:02 dawes Exp $ */ /* * Copyright 1995 The XFree86 Project, Inc * --- 1,4 ---- ! /* $XFree86: xc/programs/Xserver/hw/xfree86/common_hw/Ch8391clk.c,v 3.6.2.1 1998/02/01 16:04:48 robin Exp $ */ /* * Copyright 1995 The XFree86 Project, Inc * *************** *** 6,12 **** * chrontel8391 program from Richard Burdick * Harald Koenig */ ! /* $TOG: Ch8391clk.c /main/6 1997/07/19 10:03:22 kaleb $ */ /* * --- 6,12 ---- * chrontel8391 program from Richard Burdick * Harald Koenig */ ! /* $TOG: Ch8391clk.c /main/7 1998/03/06 16:37:14 kaleb $ */ /* * *************** *** 24,29 **** --- 24,33 ---- * Harald Koenig * 14 January 1995 * + * modified to be used by the Tseng code by + * Krajcsovits Gyorgy + * 19 August 1997 + * */ *************** *** 236,263 **** ie: 0-7, 8 values are restricted. 10-15, 6 values are restricted. 19-23, 5 values ; 28-31, 4 values; 37-39, 3 values; 46-47, 2; 55, 1 if I have interpreted this pattern correctly, there aren't any other ! values, but then I could be wrong the chrontel literature also says use of M values of 10 or less for ! best circuit performance */ - - #if NeedFunctionPrototypes ! void Chrontel8391SetClock(long freq, int clk) #else void ! Chrontel8391SetClock(freq, clk) long freq; ! int clk; #endif { double ffreq; ! int n, nmin, nmax, k, m, m0; ! int best_n, best_m; ! double diff, mindiff; if (freq < FREQ_MIN) ffreq = FREQ_MIN / 1000.0; --- 240,270 ---- ie: 0-7, 8 values are restricted. 10-15, 6 values are restricted. 19-23, 5 values ; 28-31, 4 values; 37-39, 3 values; 46-47, 2; 55, 1 if I have interpreted this pattern correctly, there aren't any other ! values, but then I could be wrong. + Note that the Chrontel 8398A clockchip doesn't have these restrictions. + [krajo] + the chrontel literature also says use of M values of 10 or less for ! best circuit performance ( 8391, 8398, 8398A ) */ #if NeedFunctionPrototypes ! void Chrontel8391CalcClock(long freq, int *best_m, int *best_n, int *best_k) #else void ! Chrontel8391CalcClock(freq, best_m, best_n, best_k) long freq; ! int *best_m; ! int *best_n; ! int *best_k; #endif { double ffreq; ! int n, nmin, nmax, m, m0; ! int bbest_n, bbest_m, kk; ! double diff, mindiff; if (freq < FREQ_MIN) ffreq = FREQ_MIN / 1000.0; *************** *** 266,276 **** else ffreq = freq / 1000.0; ! /* work out suitable timings */ ! /* pick the right p value */ ! for(k=0; k<4 && ffreq <= 67.5; k++) ffreq *= 2; /* now 67.5 <= ffreq <= 135.0 */ --- 273,283 ---- else ffreq = freq / 1000.0; ! /* work out suitable timings */ ! /* pick the right p value */ ! for(kk=0; kk<4 && ffreq <= 67.5; kk++) ffreq *= 2; /* now 67.5 <= ffreq <= 135.0 */ *************** *** 284,321 **** if (nmin<8) nmin = 8; /* because (n <= 7) isn't allowed */ nmax = (int)(ffreq * (32+2)) -8 +1; if (nmax > 255) nmax = 255; ! mindiff = ffreq; for (n = nmin; n <= nmax; n++) { if ( /* (n <= 7) || */ ! (n >= 10 && n <= 15) || ! (n >= 19 && n <= 23) || (n >= 28 && n <= 31) || ! (n >= 37 && n <= 39) || (n == 46) || (n == 47) || ! (n == 51)) ! continue; /* the above numbers are not allowed, skip */ m0 = (int)((n+8) / ffreq) - 2; for (m=m0-1; m<=m0+1; m++) { ! if (m<1 || m>31) continue; ! ! diff = (n+8.0) / (m+2) - ffreq; ! if (diff<0) ! diff = -diff; ! if (diff < mindiff) { ! mindiff = diff; ! best_n = n; ! best_m = m; ! } } } #ifdef DEBUG ! diff = freq/1000.0 - (CHRONTEL_REF_FREQ * (best_n+8.0) / ((best_m + 2) * (1 << k))); if (diff<0) diff = -diff; ErrorF("clk %d, setting to %12f, m %3d, n %3d, k %d, err %12f\n", clk, ! CHRONTEL_REF_FREQ * (best_n+8.0) / ((best_m + 2) * (1 << k)), ! best_m, best_n, k, diff); #endif s3ProgramChrontel8391Clock(best_m, best_n, k, clk); return; } --- 291,350 ---- if (nmin<8) nmin = 8; /* because (n <= 7) isn't allowed */ nmax = (int)(ffreq * (32+2)) -8 +1; if (nmax > 255) nmax = 255; ! mindiff = ffreq; for (n = nmin; n <= nmax; n++) { if ( /* (n <= 7) || */ ! (n >= 10 && n <= 15) || ! (n >= 19 && n <= 23) || (n >= 28 && n <= 31) || ! (n >= 37 && n <= 39) || (n == 46) || (n == 47) || ! (n == 51)) ! continue; /* the above numbers are not allowed, skip */ m0 = (int)((n+8) / ffreq) - 2; for (m=m0-1; m<=m0+1; m++) { ! if (m<1 || m>31) continue; ! ! diff = (n+8.0) / (m+2) - ffreq; ! if (diff<0) ! diff = -diff; if (diff < mindiff) { ! mindiff = diff; ! bbest_n = n; ! bbest_m = m; ! } } } + *best_m = bbest_m; + *best_n = bbest_n; + *best_k = kk; + } + + + + #if NeedFunctionPrototypes + void Chrontel8391SetClock(long freq, int clk) + #else + void + Chrontel8391SetClock(freq, clk) + long freq; + int clk; + #endif + { + int best_m, best_n, k; + Chrontel8391CalcClock(freq, &best_m, &best_n, &k); + #ifdef DEBUG ! ! diff = freq/1000.0 - (CHRONTEL_REF_FREQ * (best_n+8.0) / ((best_m + 2) * (1 \\<< k))); if (diff<0) diff = -diff; ErrorF("clk %d, setting to %12f, m %3d, n %3d, k %d, err %12f\n", clk, ! CHRONTEL_REF_FREQ * (best_n+8.0) / ((best_m + 2) * (1 << k)), ! best_m, best_n, k, diff); #endif + s3ProgramChrontel8391Clock(best_m, best_n, k, clk); return; } + + *** ./programs/Xserver/hw/xfree86/common_hw/I2061Aalt.c@@/PUBLIC-LATEST Sat Jul 19 10:03:38 1997 --- xc/programs/Xserver/hw/xfree86/common_hw/I2061Aalt.c Fri Mar 6 16:35:41 1998 *************** *** 1,9 **** ! /* $XFree86: xc/programs/Xserver/hw/xfree86/common_hw/I2061Aalt.c,v 3.12 1996/12/23 06:44:07 dawes Exp $ */ /* * This code is derived from code available from the STB bulletin board */ ! /* $TOG: I2061Aalt.c /main/13 1997/07/19 10:03:40 kaleb $ */ /*#define EXTENDED_DEBUG*/ --- 1,9 ---- ! /* $XFree86: xc/programs/Xserver/hw/xfree86/common_hw/I2061Aalt.c,v 3.12.2.1 1998/02/01 16:04:48 robin Exp $ */ /* * This code is derived from code available from the STB bulletin board */ ! /* $TOG: I2061Aalt.c /main/14 1998/03/06 16:37:18 kaleb $ */ /*#define EXTENDED_DEBUG*/ *************** *** 15,20 **** --- 15,21 ---- #include "compiler.h" #define NO_OSLIB_PROTOTYPES #include "xf86_OSlib.h" + #include "xf86_HWlib.h" #define SEQREG 0x03C4 #define MISCREG 0x03C2 *************** *** 29,35 **** unsigned short crtcaddr; unsigned short clockreg; ! static double range[15] = {50.0, 51.0, 53.2, 58.5, 60.7, 64.4, 66.8, 73.5, 75.6, 80.9, 83.2, 91.5, 100.0, 120.0, 120.0000001}; #if NeedFunctionPrototypes --- 30,36 ---- unsigned short crtcaddr; unsigned short clockreg; ! static double _range[15] = {50.0, 51.0, 53.2, 58.5, 60.7, 64.4, 66.8, 73.5, 75.6, 80.9, 83.2, 91.5, 100.0, 120.0, 120.0000001}; #if NeedFunctionPrototypes *************** *** 38,44 **** #endif static void wrt_clk_bit(unsigned int value); static void s3_init_clock(unsigned long setup, unsigned short crtcport); - static void et4000_init_clock(unsigned long setup); #else #if 0 static void prtbinary(); --- 39,44 ---- *************** *** 45,51 **** #endif static void wrt_clk_bit(); static void s3_init_clock(); - static void et4000_init_clock(); #endif #ifdef PC98_PW static void PWClockSet(short,unsigned long); --- 45,50 ---- *************** *** 54,60 **** static void PWLBClockSet(short,unsigned long); #endif ! static unsigned long AltICD2061CalcClock(frequency) register long frequency; /* in Hz */ { --- 53,59 ---- static void PWLBClockSet(short,unsigned long); #endif ! unsigned long AltICD2061CalcClock(frequency) register long frequency; /* in Hz */ { *************** *** 86,93 **** #endif freq = ((double)frequency)/1000000.0; ! if (freq > range[13]) ! freq = range[13]; else if (freq < 7.0) freq = 7.0; --- 85,92 ---- #endif freq = ((double)frequency)/1000000.0; ! if (freq > _range[13]) ! freq = _range[13]; else if (freq < 7.0) freq = 7.0; *************** *** 111,119 **** if (deltax < 0) deltax = -deltax; if (deltax <= delta) { for (i = 13; i >= 0; i--) ! if (fvco >= range[i]) break; ! devx = (fvco - (range[i] + range[i+1])/2)/fvco; if (devx < 0) devx = -devx; if (deltax < delta || devx < dev) { --- 110,118 ---- if (deltax < 0) deltax = -deltax; if (deltax <= delta) { for (i = 13; i >= 0; i--) ! if (fvco >= _range[i]) break; ! devx = (fvco - (_range[i] + _range[i+1])/2)/fvco; if (devx < 0) devx = -devx; if (deltax < delta || devx < dev) { *************** *** 397,403 **** * included in XFREE code base by Koen Gadeyne */ ! static void et4000_init_clock(unsigned long setup) { register unsigned char a=inb(0x3CC) & ~0x0C; --- 396,402 ---- * included in XFREE code base by Koen Gadeyne */ ! void et4000_init_clock(unsigned long setup) { register unsigned char a=inb(0x3CC) & ~0x0C; *************** *** 421,425 **** #undef S } - - --- 420,422 ---- *** ./programs/Xserver/hw/xfree86/common_hw/Imakefile@@/PUBLIC-LATEST Sat Jul 19 10:04:32 1997 --- xc/programs/Xserver/hw/xfree86/common_hw/Imakefile Fri Mar 6 16:35:45 1998 *************** *** 1,9 **** ! XCOMM $TOG: Imakefile /main/17 1997/07/19 10:04:33 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree86/common_hw/Imakefile,v 3.24 1997/01/05 11:58:22 dawes Exp $ #include --- 1,9 ---- ! XCOMM $TOG: Imakefile /main/18 1998/03/06 16:37:23 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree86/common_hw/Imakefile,v 3.24.2.1 1998/02/24 13:54:16 hohndel Exp $ #include *************** *** 51,56 **** --- 51,58 ---- InstallLinkKitLibrary(xf86_hw,$(LINKKITDIR)/lib86) InstallLinkKitNonExecFile(xf86_HWlib.h,$(LINKKITDIR)/include) InstallLinkKitNonExecFile(xf86_PCI.h,$(LINKKITDIR)/include) + InstallLinkKitNonExecFile(IBMRGB.h,$(LINKKITDIR)/drivers) + InstallLinkKitNonExecFile(Ti302X.h,$(LINKKITDIR)/drivers) DependTarget() *** ./programs/Xserver/hw/xfree86/common_hw/Ti302X.h@@/PUBLIC-LATEST Sat Jul 19 10:21:18 1997 --- xc/programs/Xserver/hw/xfree86/common_hw/Ti302X.h Fri Mar 6 16:35:49 1998 *************** *** 1,4 **** ! /* $XFree86: xc/programs/Xserver/hw/xfree86/common_hw/Ti302X.h,v 3.9.2.1 1997/05/11 02:56:21 dawes Exp $ */ /* * Copyright 1994 by Robin Cutshaw * --- 1,4 ---- ! /* $XFree86: xc/programs/Xserver/hw/xfree86/common_hw/Ti302X.h,v 3.9.2.2 1998/01/25 05:06:13 robin Exp $ */ /* * Copyright 1994 by Robin Cutshaw * *************** *** 21,27 **** * PERFORMANCE OF THIS SOFTWARE. * */ ! /* $TOG: Ti302X.h /main/9 1997/07/19 10:21:19 kaleb $ */ #include "compiler.h" #include --- 21,27 ---- * PERFORMANCE OF THIS SOFTWARE. * */ ! /* $TOG: Ti302X.h /main/10 1998/03/06 16:37:27 kaleb $ */ #include "compiler.h" #include *************** *** 87,92 **** --- 87,94 ---- #define TI_MUX1_3026D_888 0x06 /* 3026 only */ #define TI_MUX1_3026D_565 0x05 /* 3026 only */ #define TI_MUX1_3026D_555 0x04 /* 3026 only */ + #define TI_MUX1_3026D_888_P8 0x16 /* 3026 only */ + #define TI_MUX1_3026D_888_P5 0x1e /* 3026 only */ #define TI_MUX1_3026T_888 0x46 /* 3026 only */ #define TI_MUX1_3026T_565 0x45 /* 3026 only */ #define TI_MUX1_3026T_555 0x44 /* 3026 only */ *************** *** 157,162 **** --- 159,165 ---- #define TI_MC_DOTCLK_DISABLE 0x02 #define TI_MC_INT_6_8_CONTROL 0x04 /* 00 == external 6/8 pin */ #define TI_MC_8_BPP 0x08 /* 00 == 6bpp */ + #define TI_MC_PSEL_POLARITY 0x20 /* 3026 only, PSEL polarity select */ #define TI_MC_VCLK_POLARITY 0x20 #define TI_MC_LCLK_LATCH 0x40 /* VCLK == 00, default */ #define TI_MC_LOOP_PLL_RCLK 0x80 *** ./programs/Xserver/hw/xfree86/common_hw/xf86_HWlib.h@@/PUBLIC-LATEST Sat Jul 19 10:21:29 1997 --- xc/programs/Xserver/hw/xfree86/common_hw/xf86_HWlib.h Fri Mar 6 16:35:53 1998 *************** *** 1,4 **** ! /* $XFree86: xc/programs/Xserver/hw/xfree86/common_hw/xf86_HWlib.h,v 3.31.2.1 1997/05/06 13:27:29 dawes Exp $ */ /* * Copyright 1990, 1991 by Thomas Roell, Dinkelscherben, Germany * Copyright 1993 by David Wexelblat --- 1,4 ---- ! /* $XFree86: xc/programs/Xserver/hw/xfree86/common_hw/xf86_HWlib.h,v 3.31.2.2 1998/02/01 16:04:49 robin Exp $ */ /* * Copyright 1990, 1991 by Thomas Roell, Dinkelscherben, Germany * Copyright 1993 by David Wexelblat *************** *** 28,34 **** * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ ! /* $TOG: xf86_HWlib.h /main/22 1997/07/19 10:21:32 kaleb $ */ #ifndef _XF86_HWLIB_H #define _XF86_HWLIB_H --- 28,34 ---- * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ ! /* $TOG: xf86_HWlib.h /main/23 1998/03/06 16:37:31 kaleb $ */ #ifndef _XF86_HWLIB_H #define _XF86_HWLIB_H *************** *** 49,58 **** --- 49,61 ---- /***************************************************************************/ #include + #include "xf86.h" _XFUNCPROTOBEGIN /* ICD2061Aalt.c */ + extern unsigned long AltICD2061CalcClock(long); + extern void AltICD2061SetClock( #if NeedFunctionPrototypes long, *************** *** 67,72 **** --- 70,87 ---- #endif ); + extern void et4000_init_clock(unsigned long); + + /* Ch8391clk.c --> used in drivers/tseng/tseng_driver.c */ + extern void Chrontel8391CalcClock( + #if NeedFunctionPrototypes + long, + int *, + int *, + int * + #endif + ); + /* ICD2061Acal.c */ extern long ICD2061ACalcClock( #if NeedFunctionPrototypes *************** *** 179,185 **** #endif ); ! extern int ET4000stg1703SetClock( #if NeedFunctionPrototypes long, int --- 194,200 ---- #endif ); ! extern void ET4000stg1703SetClock( #if NeedFunctionPrototypes long, int *************** *** 308,319 **** ); /* STG1703clk.c */ ! extern void STG1703SetClock( ! #if NeedFunctionPrototypes ! long, ! int ! #endif ! ); /* BUSmemcpy.s */ extern void BusToMem( --- 323,334 ---- ); /* STG1703clk.c */ ! extern void ET4000stg1703SetClock(long, int); ! extern void STG1703CalcProgramWord(long, unsigned int *); ! extern void STG1703SetClock(long, int); ! extern unsigned char STG1703getIndex(unsigned int); ! extern void STG1703magic(int); ! extern void STG1703setIndex(unsigned int, unsigned char); /* BUSmemcpy.s */ extern void BusToMem( *** ./programs/Xserver/hw/xfree86/common_hw/xf86_PCI.c@@/PUBLIC-LATEST Sun Aug 10 13:00:33 1997 --- xc/programs/Xserver/hw/xfree86/common_hw/xf86_PCI.c Fri Mar 6 16:35:57 1998 *************** *** 1,4 **** ! /* $XFree86: xc/programs/Xserver/hw/xfree86/common_hw/xf86_PCI.c,v 3.16.2.5 1997/07/26 06:30:48 dawes Exp $ */ /* * Copyright 1995 by Robin Cutshaw * --- 1,4 ---- ! /* $XFree86: xc/programs/Xserver/hw/xfree86/common_hw/xf86_PCI.c,v 3.16.2.6 1998/02/01 16:04:49 robin Exp $ */ /* * Copyright 1995 by Robin Cutshaw * *************** *** 22,28 **** * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ ! /* $TOG: xf86_PCI.c /main/16 1997/08/10 12:59:09 kaleb $ */ /* #define DEBUGPCI 1 */ --- 22,28 ---- * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ ! /* $TOG: xf86_PCI.c /main/17 1998/03/06 16:37:35 kaleb $ */ /* #define DEBUGPCI 1 */ *************** *** 36,43 **** --- 36,45 ---- #ifdef PC98 #define outb(port,data) _outb(port,data) + #define outw(port,data) _outw(port,data) #define outl(port,data) _outl(port,data) #define inb(port) _inb(port) + #define inw(port) _inw(port) #define inl(port) _inl(port) #endif *** ./programs/Xserver/hw/xfree86/doc/COPYRIGHT@@/PUBLIC-LATEST Wed Feb 11 10:13:36 1998 --- xc/programs/Xserver/hw/xfree86/doc/COPYRIGHT Fri Mar 6 16:36:08 1998 *************** *** 18,24 **** XFree86 code without an explicit copyright is covered by the following copy- right: ! Copyright (C) 1994-1997 The XFree86 Project, Inc. All Rights Reserved. Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in --- 18,24 ---- XFree86 code without an explicit copyright is covered by the following copy- right: ! Copyright (C) 1994-1998 The XFree86 Project, Inc. All Rights Reserved. Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in *************** *** 153,159 **** 2.3 NVidia Corp ! Copyright (c) 1996 NVIDIA, Corp. All rights reserved. NOTICE TO USER: The source code is copyrighted under U.S. and international laws. NVIDIA, Corp. of Sunnyvale, California owns the copyright and as design --- 153,159 ---- 2.3 NVidia Corp ! Copyright (c) 1996-1998 NVIDIA, Corp. All rights reserved. NOTICE TO USER: The source code is copyrighted under U.S. and international laws. NVIDIA, Corp. of Sunnyvale, California owns the copyright and as design *************** *** 165,172 **** Any use of this source code must include, in the user documentation and inter- nal comments to the code, notices to the end user as follows: ! Copyright (c) 1996 NVIDIA, Corp. NVIDIA design patents pending in the U.S. and ! foreign countries. NVIDIA, CORP. MAKES NO REPRESENTATION ABOUT THE SUITABILITY OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" WITHOUT EXPRESS OR IMPLIED WAR- --- 165,172 ---- Any use of this source code must include, in the user documentation and inter- nal comments to the code, notices to the end user as follows: ! Copyright (c) 1996-1998 NVIDIA, Corp. NVIDIA design patents pending in the ! U.S. and foreign countries. NVIDIA, CORP. MAKES NO REPRESENTATION ABOUT THE SUITABILITY OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" WITHOUT EXPRESS OR IMPLIED WAR- *************** *** 190,202 **** CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. ! Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/CPYRIGHT.sgml,v 3.9.2.1 1997/06/08 15:41:26 dawes Exp $ ! $TOG: COPYRIGHT /main/13 1998/02/11 10:13:58 kaleb $ --- 190,202 ---- CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. ! Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/CPYRIGHT.sgml,v 3.9.2.2 1998/01/24 11:55:06 dawes Exp $ ! $TOG: COPYRIGHT /main/14 1998/03/06 16:37:45 kaleb $ *************** *** 379,382 **** ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/COPYRIGHT,v 3.16.2.1 1997/06/08 15:42:54 dawes Exp $ --- 379,382 ---- ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/COPYRIGHT,v 3.16.2.2 1998/01/25 04:06:33 dawes Exp $ *** ./programs/Xserver/hw/xfree86/doc/Imakefile@@/PUBLIC-LATEST Sun Aug 10 13:00:45 1997 --- xc/programs/Xserver/hw/xfree86/doc/Imakefile Sat Mar 7 17:40:52 1998 *************** *** 1,10 **** ! XCOMM $TOG: Imakefile /main/36 1997/08/10 12:59:20 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree86/doc/Imakefile,v 3.44.2.2 1997/07/27 02:41:13 dawes Exp $ #include XCOMM #include --- 1,10 ---- ! XCOMM $TOG: Imakefile /main/38 1998/03/07 17:42:33 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree86/doc/Imakefile,v 3.44.2.5 1998/02/25 12:20:22 dawes Exp $ #include XCOMM #include *************** *** 81,95 **** #if !BuildLinuxDocText HWREADME = README.ati README.trident README.tseng README.WstDig \ ! README.DECtga \ README.chips README.cirrus README.Video7 README.P9000 README.agx \ README.S3 README.S3V README.SiS README.W32 README.Oak \ README.Mach32 \ ! README.Mach64 README.ark README.MGA README.NV1 MAINDOCS = COPYRIGHT README README.Config BUILD RELNOTES ! OTHERDOCS = /*VideoModes.doc*/ QuickStart.doc README.clkprog xinput #endif MISCDOCS = ServersOnly /*LbxproxyOnly*/ $(REPORTFORM) README.DGA --- 81,95 ---- #if !BuildLinuxDocText HWREADME = README.ati README.trident README.tseng README.WstDig \ ! README.DECtga README.apm \ README.chips README.cirrus README.Video7 README.P9000 README.agx \ README.S3 README.S3V README.SiS README.W32 README.Oak \ README.Mach32 \ ! README.Mach64 README.ark README.MGA README.NV1 README.mouse MAINDOCS = COPYRIGHT README README.Config BUILD RELNOTES ! OTHERDOCS = VideoModes.doc QuickStart.doc README.clkprog xinput #endif MISCDOCS = ServersOnly /*LbxproxyOnly*/ $(REPORTFORM) README.DGA *************** *** 103,108 **** --- 103,109 ---- LinkFile(README.Mach32,READ.Mach32) LinkFile(README.Mach64,READ.Mach64) LinkFile(README.FreeBSD,READ.FreeBSD) + LinkFile(README.Riva128,README.NV1) #ifdef IHaveSubdirs MakeSubdirs($(SUBDIRS)) *** ./programs/Xserver/hw/xfree86/doc/Japanese/sgml/README.sgml@@/PUBLIC-LATEST Sun Aug 10 13:01:48 1997 --- xc/programs/Xserver/hw/xfree86/doc/Japanese/sgml/README.sgml Fri Mar 6 16:38:48 1998 *************** *** 376,382 **** ! Thomas Mueller <tm@systrix.de> --- 376,382 ---- ! Thomas Mueller <tmueller@sysgo.de> *************** *** 987,993 **** ¤Ë¤Ä¤¤¤Æµ­ºÜ¤µ¤ì¤Æ¤¤¤Þ¤¹¡£ ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/Japanese/sgml/README.sgml,v 3.2.2.1 1997/07/06 07:28:17 dawes Exp $ --- 987,993 ---- ¤Ë¤Ä¤¤¤Æµ­ºÜ¤µ¤ì¤Æ¤¤¤Þ¤¹¡£ ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/Japanese/sgml/README.sgml,v 3.2.2.2 1998/02/15 23:32:01 robin Exp $ *** ./programs/Xserver/hw/xfree86/doc/OS2.Notes@@/PUBLIC-LATEST Sat Jul 19 10:26:01 1997 --- xc/programs/Xserver/hw/xfree86/doc/OS2.Notes Fri Mar 6 16:36:16 1998 *************** *** 11,17 **** Holger Veit ! Last modified 17 May 1997 --- 11,17 ---- Holger Veit ! Last modified 26 Mar 1998 *************** *** 27,44 **** Please also read README.OS2 for end-user information, and set at least the environment variables described there. ! At the current time, the most recent version available is XFree86-3.3. This is ! a full and unrestricted version which comes with complete source code. 3.3 is ! an intermediate version which was released because the last beta version (3.2A) ! was about to expire and the new 4.0 version was not completely finished in ! time. 3.3 is the last ``classical'' version which has separate Xservers for ! different video cards. If you want to join the XFree86 developer team, e.g. to add support for certain hardware, please send a request to BOD@XFree86.org. Please think about such a step carefully before, though, since much work is involved. Please use the ! XFree86-3.3 source code as a test example how to compile the system. The abil- ! ity to manage that is a basic requirement for becoming a developer. 2. Tools required --- 27,43 ---- Please also read README.OS2 for end-user information, and set at least the environment variables described there. ! At the current time, the most recent version available is XFree86-3.3.2. This ! is a full and unrestricted version which comes with complete source code. 3.3.2 ! is not only a bugfix release, but also supports new hardware, some of which ! might not even supported by OS/2 itself. See the RELEASE NOTES document for ! details. If you want to join the XFree86 developer team, e.g. to add support for certain hardware, please send a request to BOD@XFree86.org. Please think about such a step carefully before, though, since much work is involved. Please use the ! XFree86-3.3.2 source code as a test example how to compile the system. The ! ability to manage that is a basic requirement for becoming a developer. 2. Tools required *************** *** 50,56 **** ftp.leo.org via anonymous FTP. The following shopping list shows what you will need: ! o gcc EMX/gcc emx 0.9C patch2 or later o gzip GNU zip/unzip --- 49,55 ---- ftp.leo.org via anonymous FTP. The following shopping list shows what you will need: ! o gcc EMX/gcc emx 0.9C patch4 or later o gzip GNU zip/unzip *************** *** 61,66 **** --- 60,66 ---- + Notes on Rebuilding XFree86/OS2 from Scratch *************** *** 85,91 **** o gawk GNU awk ! o make GNU make 3.71/3.72 (use the one coming with XFree86!) o flex GNU flex --- 85,91 ---- o gawk GNU awk ! o make GNU make 3.71/3.72 (use the one from X332prog.zip!) o flex GNU flex *************** *** 252,259 **** xmake install.man ! Well, you see, this was quite easy :-) --- 252,262 ---- xmake install.man ! 15. There are a few minor glitches in the installation: + 1. The xdm and linkkit directories will fail in compile and installa- + tion. This is no problem and has no effect on the rest of the sys- + tem. *************** *** 262,281 **** - - - Notes on Rebuilding XFree86/OS2 from Scratch ! Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/OS2note.sgml,v 3.4.2.2 1997/05/24 08:36:06 dawes Exp $ ! $TOG: OS2.Notes /main/5 1997/07/19 10:26:03 kaleb $ --- 265,292 ---- Notes on Rebuilding XFree86/OS2 from Scratch ! 2. The imake.exe which is installed in \XFree86\bin is usually defec- ! tive. The one which was built initially and installed in the root ! directory of the drive where you have the source tree is okay. So ! simply copy this \imake.exe to the \XFree86\bin directory manually. ! Some day this might be fixed. + 3. XF86Setup is not ported yet and won't work with the tcl/tk port + available for XFree86/OS2. My idea was to replace this by some + native installation tool, which I didn't find the time to do yet. + Feel free to spend a bit of time to play with XF86Setup if you + like. + Well, you see, this was quite easy :-) + Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/OS2note.sgml,v 3.4.2.3 1998/02/26 20:11:29 hohndel Exp $ ! $TOG: OS2.Notes /main/6 1998/03/06 16:37:54 kaleb $ *************** *** 320,336 **** - - - - - - - - - - - Notes on Rebuilding XFree86/OS2 from Scratch --- 331,336 ---- *************** *** 461,464 **** ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/OS2.Notes,v 3.8.2.2 1997/05/24 09:12:05 dawes Exp $ --- 461,464 ---- ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/OS2.Notes,v 3.8.2.3 1998/02/27 02:54:55 dawes Exp $ *** ./programs/Xserver/hw/xfree86/doc/QuickStart.doc@@/PUBLIC-LATEST Sat Jul 19 10:26:07 1997 --- xc/programs/Xserver/hw/xfree86/doc/QuickStart.doc Fri Mar 6 16:36:20 1998 *************** *** 13,19 **** Joe Moss ! 26 August 1996 --- 13,19 ---- Joe Moss ! 27 February 1998 *************** *** 57,66 **** It will help speed up the process, if you know which protocol is used by your mouse to communicate. Some mice are capable of using two different protocols, although the method of switching between ! them varies. - Quick-Start Guide to XFree86 Setup --- 57,66 ---- It will help speed up the process, if you know which protocol is used by your mouse to communicate. Some mice are capable of using two different protocols, although the method of switching between ! them varies. In some cases, with new Plug-n-Play mice, the proto- ! col can be determined automatically. Quick-Start Guide to XFree86 Setup *************** *** 116,130 **** and exit. Correct the problem (e.g. install the missing files) and run it again. 3.1 Initial questions If you have an existing XF86Config file, you will be asked if you would like to - use it to set the default values of various configuration settings. If you've - already got an (at least somewhat) working configuration you will want to do - this. - If you are running on an OS which has a mouse driver in the kernel (e.g. SCO or - SVR4), you may be asked if you'd like to use it. --- 116,131 ---- and exit. Correct the problem (e.g. install the missing files) and run it again. + XF86Setup is internationalized. If you are Japanese and set the LANG environ- + ment variable to ja, japan, japanese, etc., XF86Setup's screen can be + Japanized. But it is necessary that XF86Setup is built with Japanized Tcl/Tk. + Other language can be added, if you prepare its own directory under the direc- + tory XF86Setup/texts. Please see under the directory XF86Setup/texts/generic. + 3.1 Initial questions If you have an existing XF86Config file, you will be asked if you would like to *************** *** 132,142 **** - Quick-Start Guide to XFree86 Setup Once the questions (if any) are completed, you will see a message indicating that the program is ready to switch into graphics mode. Just press Enter. If you don't get a graphics screen saying Welcome to XFree86 Setup within a --- 133,149 ---- Quick-Start Guide to XFree86 Setup + use it to set the default values of various configuration settings. If you've + already got an (at least somewhat) working configuration you will want to do + this. + + If you are running on an OS which has a mouse driver in the kernel (e.g. SCO or + SVR4), you may be asked if you'd like to use it. + Once the questions (if any) are completed, you will see a message indicating that the program is ready to switch into graphics mode. Just press Enter. If you don't get a graphics screen saying Welcome to XFree86 Setup within a *************** *** 147,153 **** 3.2 Configuration areas Once the VGA16 server is started, and once the program has finished loading, ! you will see a screen with five buttons along the top and three along the bot- tom. The buttons along the top correspond to the general categories of config- uration settings. They can be done in any order. Each of these areas is explained in detail below. The bottom row consists of the Abort, Done, and --- 154,160 ---- 3.2 Configuration areas Once the VGA16 server is started, and once the program has finished loading, ! you will see a screen with six buttons along the top and three along the bot- tom. The buttons along the top correspond to the general categories of config- uration settings. They can be done in any order. Each of these areas is explained in detail below. The bottom row consists of the Abort, Done, and *************** *** 177,196 **** buttons should turn black as you press the corresponding button on your mouse. If that is not happening, then your mouse is not correctly configured. ! Along the top is a row of buttons corresponding to the various possible proto- ! cols. There will also be several buttons and a couple of sliders for other set- ! tings, a visual representation of the mouse, and a button to apply any changes. ! There may also be an entry box in which the device can be set along with a list ! of possible devices. First try moving your mouse around and see if the pointer moves correctly. If - so, try testing that the buttons are working properly. If those are working as - desired, go ahead and go on to another configuration area. - If the mouse pointer doesn't move at all, you need to fix either the mouse - device or the protocol (or both). You can press 'n' followed by a Tab, to move - to the list of mouse devices and select a different one. Pressing 'p' will - pick the next available protocol on the list. After changing these, press 'a' --- 184,197 ---- buttons should turn black as you press the corresponding button on your mouse. If that is not happening, then your mouse is not correctly configured. ! Along the top are some rows of buttons corresponding to the various possible ! protocols. There will also be several buttons and a couple of sliders for other ! settings, a visual representation of the mouse, and a button to apply any ! changes. There may also be an entry box in which the device can be set along ! with a list of possible devices. First try moving your mouse around and see if the pointer moves correctly. If *************** *** 198,211 **** - Quick-Start Guide to XFree86 Setup ! to apply the changes and try again. Repeat the process until you are getting ! some response from your mouse. If the mouse pointer or button indicators do something when you move the mouse, but the pointer is not moving properly, you probably have the wrong protocol selected. Try with a different one. --- 199,220 ---- Quick-Start Guide to XFree86 Setup ! so, try testing that the buttons are working properly. If those are working as ! desired, go ahead and go on to another configuration area. + If the mouse pointer doesn't move at all, you need to fix either the mouse + device or the protocol (or both). You can press 'n' followed by a Tab, to move + to the list of mouse devices and select a different one. Pressing 'p' will + pick the next available protocol on the list (protocols that are not available + on your OS will be greyed-out). If you have a PnP mouse, it may be easiest to + just select "Auto" as the protocol. After changing these, press 'a' to apply + the changes and try again. Repeat the process until you are getting some + response from your mouse. + If the mouse pointer or button indicators do something when you move the mouse, but the pointer is not moving properly, you probably have the wrong protocol selected. Try with a different one. *************** *** 248,262 **** If your card is not in the list, or if there are any special settings listed in the README file as required by your card, you can press the 'Detailed Setup' button to make sure that the required settings are selected. Otherwise, you're - finished with configuring your card. - To use 'Detailed Setup': First select the appropriate server for your card. - Then read the README file corresponding to the selected server by pressing the - 'Read README file' button (it won't do anything, if there is no README). - Next, pick the chipset, and Ramdac of your card, if directed by the README - file. In most cases, you don't need to select these, as the server will detect - (probe) them automatically. --- 257,264 ---- *************** *** 263,274 **** - Quick-Start Guide to XFree86 Setup The clockchip should generally be picked, if your card has one, as these are often impossible to probe (the exception is when the clockchip is built into one of the other chips). --- 265,284 ---- + Quick-Start Guide to XFree86 Setup + finished with configuring your card. + To use 'Detailed Setup': First select the appropriate server for your card. + Then read the README file corresponding to the selected server by pressing the + 'Read README file' button (it won't do anything, if there is no README). + Next, pick the chipset, and Ramdac of your card, if directed by the README + file. In most cases, you don't need to select these, as the server will detect + (probe) them automatically. + The clockchip should generally be picked, if your card has one, as these are often impossible to probe (the exception is when the clockchip is built into one of the other chips). *************** *** 283,290 **** Additionally, you can also specify the amount of RAM on your card, though the server will usually be able to detect this. ! 3.2.4 Monitor Enter the horizontal and vertical frequency ranges that your monitor supports in the corresponding entry boxes near the top of the screen. You can enter specific frequencies or ranges of frequencies (separated by hyphens). If the --- 293,312 ---- Additionally, you can also specify the amount of RAM on your card, though the server will usually be able to detect this. ! 3.2.4 Modeselect + Use this one to pick which depth you prefer to use (this determines how many + colors can be displayed at a time) and to select all of the modes you are + interested in possibly using. + + Your hardware may not be able to support all of depth and mode combinations + that can be selected. Any unsupported combinations will automatically be + rejected by the server when it tries to startup. Note also that if you select + multiple modes, you will get a virtual screen as large as the largest of the + usable modes. + + 3.2.5 Monitor + Enter the horizontal and vertical frequency ranges that your monitor supports in the corresponding entry boxes near the top of the screen. You can enter specific frequencies or ranges of frequencies (separated by hyphens). If the *************** *** 296,307 **** conservative values for each of these, so you'll get better performance if you type in the correct values from your monitor manual. ! 3.2.5 Other You can probably just skip this one. - 3.2.6 Completing the configuration Once you've finished with the above, press the 'Done' button and then the 'Okay' button which will appear. You will then be switched back to text mode. --- 318,342 ---- conservative values for each of these, so you'll get better performance if you type in the correct values from your monitor manual. ! 3.2.6 Other You can probably just skip this one. + + + + + + + + + Quick-Start Guide to XFree86 Setup + + + + 3.2.7 Completing the configuration + Once you've finished with the above, press the 'Done' button and then the 'Okay' button which will appear. You will then be switched back to text mode. *************** *** 323,340 **** The first button allows you to run xvidtune to adjust your video modes. One important point to keep in mind when using xvidtune is that switching video - - - - - - - - - Quick-Start Guide to XFree86 Setup - - - modes with Ctrl-Alt-+ is disabled while xvidtune is running. You must use the 'Next' and 'Prev' buttons to switch modes. Because of this, you should be careful not to move the mouse when pressing either of these. If by some chance --- 358,363 ---- *************** *** 366,371 **** --- 389,406 ---- just start it over again. The xf86config program provides instructions on screen as to what you need to + + + + + + + + + Quick-Start Guide to XFree86 Setup + + + do. Following are some notes that document the various stages in the process. They should help you get through the process quickly and provide some documen- tation for those people who like to know what they're getting themselves into, *************** *** 390,406 **** If everything is okay, just press Enter and go on, otherwise press Control-C to exit and make any necessary changes and restart xf86config. - - - - - - - - Quick-Start Guide to XFree86 Setup - - - 4.3 Mouse setup Pick the mouse type from the menu and enter the name of the device to which --- 425,430 ---- *************** *** 416,421 **** --- 440,449 ---- likely) and then see the troubleshooting section if it doesn't work when you run the server. + The xf86config program has not been updated to allow you to select the latest + mouse protocols, so you may have to edit the config file by hand after xf86con- + fig has finished. + 4.4 Keyboard setup Simply answer yes to the question regarding keyboard setup. *************** *** 428,433 **** --- 456,472 ---- Setting up a monitor consists of entering the specifications of your monitor and a description of the model and manufacturer. + + + + + + + + Quick-Start Guide to XFree86 Setup + + + You are first asked for the horizontal sync rate. It is VERY important to enter the correct value(s) from the manual. If one of the ranges given matches the rate of your monitor, then pick it, otherwise pick custom and enter the *************** *** 456,475 **** If you selected your card in the previous step, then server selection is easy - just use the recommendation from the database. - - - - - - - - Quick-Start Guide to XFree86 Setup - - - If you have a card which uses one of the chipsets for which a specific server ! exists (Mach8, Mach32, Mach64, AGX/XGA, 8514/A, S3, ET4000/W32, I128, P9000) ! you'll want to pick the accel option. Otherwise you'll probably want to use the SVGA server. --- 495,503 ---- If you selected your card in the previous step, then server selection is easy - just use the recommendation from the database. If you have a card which uses one of the chipsets for which a specific server ! exists (Mach8, Mach32, Mach64, AGX/XGA, 8514/A, S3, I128, P9000) you'll want to ! pick the accel option. Otherwise you'll probably want to use the SVGA server. *************** *** 494,499 **** --- 522,538 ---- clock chip, the program will next attempt to probe to find out what clock rates are supported by your clock chip. + + + + + + + + Quick-Start Guide to XFree86 Setup + + + 4.9 Mode Selection Now you get to tell the program which video modes you would like to be able to *************** *** 521,538 **** The program will now ask if you would like to write the configuration settings you've selected to the file XF86Config. Answer yes. - - - - - - - - - Quick-Start Guide to XFree86 Setup - - - 4.11 Some final notes Lastly, the program tells you that it's finished its part of this process and --- 560,565 ---- *************** *** 559,568 **** You should now have a running X server. If it's running but the display doesn't look as good as you think it should (i.e. it doesn't fill the whole screen, it's off-center, it's wrapping around on one side, etc.) see the sec- ! tion on xvidtune. If there is some other problem, see the troubleshooting sec- ! tion. 6. Running xvidtune If you need to make adjustments to the video display, xvidtune is the tool to --- 586,607 ---- You should now have a running X server. If it's running but the display doesn't look as good as you think it should (i.e. it doesn't fill the whole screen, it's off-center, it's wrapping around on one side, etc.) see the sec- ! tion on xvidtune. If there is some other problem, see the troubleshooting + + + + + + + Quick-Start Guide to XFree86 Setup + + + + section. + + 6. Running xvidtune If you need to make adjustments to the video display, xvidtune is the tool to *************** *** 587,604 **** If you would like to adjust your other modes, you can click on the Next and Prev buttons to switch modes. - - - - - - - - - Quick-Start Guide to XFree86 Setup - - - When you are through using xvidtune simply press on the Quit button. --- 626,631 ---- *************** *** 626,631 **** --- 653,670 ---- If all else fails, you can try posting a message to comp.windows.x.i386unix or comp.os.linux.x or send email to XFree86@XFree86.org. + + + + + + + + + Quick-Start Guide to XFree86 Setup + + + 7.1 The mouse doesn't move correctly, it stays in one area of the screen You've selected the wrong protocol for your mouse. Try a different one. *************** *** 651,670 **** See the Pointer section of the XF86Config man page for a complete list of set- tings. - - - - - - - - - - - Quick-Start Guide to XFree86 Setup - - - 7.4 The display is shifted to the left/right/top/bottom See the section on xvidtune. --- 690,695 ---- *************** *** 671,690 **** 7.5 I don't appear to have xf86config or xvidtune on my system ! Hmmm. Three possibilities: ! 1. You have a version of XFree86 that is older than 3.1.2. If this is the ! case then you probably aren't reading this document either, because it ! wasn't included in 3.1.2 and earlier releases. Please upgrade to the ! latest version. ! ! 2. Your PATH is not set correctly. Make sure it includes the bin directory for the XFree86 binaries (usually, /usr/X11R6/bin ! 3. You don't have a complete installation of XFree86. Go back to wherever you got XFree86 and get the missing pieces. ! Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/QStart.sgml,v 3.4 1997/01/25 03:22:04 dawes Exp $ --- 696,710 ---- 7.5 I don't appear to have xf86config or xvidtune on my system ! Hmmm. A couple of possibilities: ! 1. Your PATH is not set correctly. Make sure it includes the bin directory for the XFree86 binaries (usually, /usr/X11R6/bin ! 2. You don't have a complete installation of XFree86. Go back to wherever you got XFree86 and get the missing pieces. ! Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/QStart.sgml,v 3.4.2.2 1998/02/28 04:47:08 dawes Exp $ *************** *** 707,732 **** - - - - - - - - - - - - - - - - - - - - Quick-Start Guide to XFree86 Setup --- 727,732 ---- *************** *** 808,839 **** 3. Using XF86Setup .......................................................... 2 3.1 Initial questions ................................................... 2 3.2 Configuration areas ................................................. 3 ! 3.3 Back to text mode ................................................... 5 ! 3.4 The second server ................................................... 5 3.5 Ending text ......................................................... 6 4. Running xf86config ....................................................... 6 ! 4.1 The intro screen .................................................... 6 ! 4.2 Getting your PATH right ............................................. 6 4.3 Mouse setup ......................................................... 7 4.4 Keyboard setup ...................................................... 7 4.5 Monitor setup ....................................................... 7 ! 4.6 Selecting your card ................................................. 7 ! 4.7 Server selection .................................................... 7 4.8 Screen/Video configuration .......................................... 8 ! 4.9 Mode Selection ...................................................... 8 ! 4.10 Creating the XF86Config file ........................................ 8 4.11 Some final notes .................................................... 9 5. Fixing the XF86Config file ............................................... 9 ! 6. Running xvidtune ......................................................... 9 7. Troubleshooting ......................................................... 10 7.1 The mouse doesn't move correctly, it stays in one area of the ! screen ............................................................. 10 ! 7.2 The server doesn't start, it says the mouse is busy. ............... 10 ! 7.3 The middle button doesn't work. .................................... 10 7.4 The display is shifted to the left/right/top/bottom ................ 11 7.5 I don't appear to have xf86config or xvidtune on my system ......... 11 --- 808,839 ---- 3. Using XF86Setup .......................................................... 2 3.1 Initial questions ................................................... 2 3.2 Configuration areas ................................................. 3 ! 3.3 Back to text mode ................................................... 6 ! 3.4 The second server ................................................... 6 3.5 Ending text ......................................................... 6 4. Running xf86config ....................................................... 6 ! 4.1 The intro screen .................................................... 7 ! 4.2 Getting your PATH right ............................................. 7 4.3 Mouse setup ......................................................... 7 4.4 Keyboard setup ...................................................... 7 4.5 Monitor setup ....................................................... 7 ! 4.6 Selecting your card ................................................. 8 ! 4.7 Server selection .................................................... 8 4.8 Screen/Video configuration .......................................... 8 ! 4.9 Mode Selection ...................................................... 9 ! 4.10 Creating the XF86Config file ........................................ 9 4.11 Some final notes .................................................... 9 5. Fixing the XF86Config file ............................................... 9 ! 6. Running xvidtune ........................................................ 10 7. Troubleshooting ......................................................... 10 7.1 The mouse doesn't move correctly, it stays in one area of the ! screen ............................................................. 11 ! 7.2 The server doesn't start, it says the mouse is busy. ............... 11 ! 7.3 The middle button doesn't work. .................................... 11 7.4 The display is shifted to the left/right/top/bottom ................ 11 7.5 I don't appear to have xf86config or xvidtune on my system ......... 11 *************** *** 857,860 **** ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/QuickStart.doc,v 3.6 1997/01/27 22:12:29 dawes Exp $ --- 857,860 ---- ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/QuickStart.doc,v 3.6.2.2 1998/02/28 13:05:33 dawes Exp $ *** ./programs/Xserver/hw/xfree86/doc/READ.FreeBSD@@/PUBLIC-LATEST Sat Jul 19 10:26:15 1997 --- xc/programs/Xserver/hw/xfree86/doc/READ.FreeBSD Fri Mar 6 16:36:26 1998 *************** *** 11,17 **** Rich Murphey, David Dawes ! 16 May 1997 --- 11,17 ---- Rich Murphey, David Dawes ! 25 Feb 1998 *************** *** 41,60 **** you can't decide what to pick and you have 52Mb of disk space, it's safe to unpack everything. ! At a minimum you need to unpack the 'required' X33*.tgz archives plus at least one server that matches your vga card. You'll need 13Mb for the minimum required run-time binaries only. Required: ! X33bin.tgz all the executable X client applications and shared libs ! X33fnts.tgz the misc, 75 dpi and PEX fonts ! X33lib.tgz data files needed at runtime Required unless you have already customized your configuration files: --- 41,60 ---- you can't decide what to pick and you have 52Mb of disk space, it's safe to unpack everything. ! At a minimum you need to unpack the 'required' X332*.tgz archives plus at least one server that matches your vga card. You'll need 13Mb for the minimum required run-time binaries only. Required: ! X332bin.tgz all the executable X client applications and shared libs ! X332fnts.tgz the misc, 75 dpi and PEX fonts ! X332lib.tgz data files needed at runtime Required unless you have already customized your configuration files: *************** *** 71,127 **** ! X33cfg.tgz customizable xinit and xdm runtime configuration files Choose at least one server: ! X338514.tgz 8-bit color for IBM 8514 and true compatibles. ! X33AGX.tgz 8 and 16-bit color for AGX and XGA boards. ! X33I128.tgz 8 and 16-bit color for I128 boards. ! X33Ma32.tgz 8 and 16-bit color for ATI Mach32 boards. ! X33Ma64.tgz 8, 16 and 32-bit color for ATI Mach64 boards. ! X33Ma8.tgz 8-bit color for ATI Mach8 boards. ! X33Mono.tgz 1-bit monochrome for VGA, Super-VGA, Hercules, and oth- ers. ! X33P9K.tgz 8, 16, and 32-bit color for Weitek P9000 boards (Dia- mond Viper). ! X33S3.tgz 8, 16 and 32-bit color for S3 boards. ! X33S3V.tgz 8 and 16-bit color for S3 ViRGE boards. ! X33SVGA.tgz >=8-bit color for Super-VGA cards. ! X33VG16.tgz 4-bit color for VGA and Super-VGA cards ! X33W32.tgz 8-bit Color for ET4000/W32, /W32i, /W32p and ET6000 cards. ! X339GAN.tgz 8-bit color for PC98 GA-98NB/WAP boards ! X339480.tgz 8-bit color for PC98 PEGC --- 71,127 ---- ! X332cfg.tgz customizable xinit and xdm runtime configuration files Choose at least one server: ! X3328514.tgz 8-bit color for IBM 8514 and true compatibles. ! X332AGX.tgz 8 and 16-bit color for AGX and XGA boards. ! X332I128.tgz 8 and 16-bit color for I128 boards. ! X332Ma32.tgz 8 and 16-bit color for ATI Mach32 boards. ! X332Ma64.tgz 8, 16 and 32-bit color for ATI Mach64 boards. ! X332Ma8.tgz 8-bit color for ATI Mach8 boards. ! X332Mono.tgz 1-bit monochrome for VGA, Super-VGA, Hercules, and oth- ers. ! X332P9K.tgz 8, 16, and 32-bit color for Weitek P9000 boards (Dia- mond Viper). ! X332S3.tgz 8, 16 and 32-bit color for S3 boards. ! X332S3V.tgz 8 and 16-bit color for S3 ViRGE boards. ! X332SVGA.tgz >=8-bit color for Super-VGA cards. ! X332VG16.tgz 4-bit color for VGA and Super-VGA cards ! X332W32.tgz 8-bit Color for ET4000/W32, /W32i, /W32p and ET6000 cards. ! X3329GAN.tgz 8-bit color for PC98 GA-98NB/WAP boards ! X3329480.tgz 8-bit color for PC98 PEGC *************** *** 137,196 **** ! X339NKV.tgz 8-bit color for PC98 NEC-CIRRUS/EPSON NKV/NKV2 boards ! X339WBS.tgz 8-bit color for PC98 WAB-S boards ! X339WEP.tgz 8-bit color for PC98 WAB-EP boards ! X339WSN.tgz 8-bit color for PC98 WSN-A2F boards ! X339EGC.tgz 4-bit color for PC98 EGC ! X339TGU.tgz ! 8 and 16-bit color for PC98 Trident Cyber9320/9680 boards ! X339NS3.tgz 8 and 16-bit color for PC98 NEC S3 boards ! X339SPW.tgz 8 and 16-bit color for PC98 S3 PW/PCSKB boards ! X339LPW.tgz 8 and 16-bit color for PC98 S3 PW/LB boards ! X339GA9.tgz ! 8 and 16-bit color for PC98 S3 GA-968 boards ! X33nest.tgz A nested server running as a client window on another display. Optional: ! X32doc.tgz READMEs ! X32ps.tgz READMEs in PostScript ! X32html.tgz READMEs in HTML ! X32man.tgz man pages - X32f100.tgz - 100dpi fonts - X32fscl.tgz - Speedo and Type1 fonts --- 137,198 ---- ! X3329NKV.tgz 8-bit color for PC98 NEC-CIRRUS/EPSON NKV/NKV2 boards ! X3329WBS.tgz 8-bit color for PC98 WAB-S boards ! X3329WEP.tgz 8-bit color for PC98 WAB-EP boards ! X3329WSN.tgz 8-bit color for PC98 WSN-A2F boards ! X3329EGC.tgz 4-bit color for PC98 EGC ! X3329TGU.tgz ! 8 and 16-bit color for PC98 Trident Cyber9320/968x boards ! X3329MGA.tgz ! >=8-bit color for PC98 Millennium/Mystique cards. ! ! X3329SVG.tgz ! 8-bit color for PC98 Cirrus755x boards ! ! X3329NS3.tgz 8 and 16-bit color for PC98 NEC S3 boards ! X3329SPW.tgz 8 and 16-bit color for PC98 S3 PW/PCSKB boards ! X3329LPW.tgz 8 and 16-bit color for PC98 S3 PW/LB boards ! X3329GA9.tgz ! 8, 16 and 32-bit color for PC98 S3 GA-968 boards ! X332nest.tgz A nested server running as a client window on another display. Optional: ! X332doc.tgz READMEs ! X332ps.tgz READMEs in PostScript ! X332html.tgz READMEs in HTML ! X332man.tgz man pages *************** *** 197,218 **** - README for XFree86 on FreeBSD ! X32fnon.tgz Japanese, Chinese and other non-english fonts ! X32fcyr.tgz Cyrillic fonts ! X32fsrv.tgz the font server and its man page ! X32prog.tgz config, lib*.a and *.h files needed only for compiling 2.1 Full Install: --- 199,224 ---- + README for XFree86 on FreeBSD + X332f100.tgz + 100dpi fonts + X332fscl.tgz + Speedo and Type1 fonts ! X332fnon.tgz Japanese, Chinese and other non-english fonts ! X332fcyr.tgz Cyrillic fonts ! X332fsrv.tgz the font server and its man page ! X332prog.tgz config, lib*.a and *.h files needed only for compiling 2.1 Full Install: *************** *** 250,262 **** If you are using sh (as root usually does): - # for i in X33*.tgz; do - # tar -x -z --unlink -f $i - # done - Else, if you are using csh: --- 256,264 ---- *************** *** 263,275 **** - README for XFree86 on FreeBSD ! % foreach i (X33*.tgz) % tar -x -z --unlink -f $i % end --- 265,283 ---- + README for XFree86 on FreeBSD + # for i in X332*.tgz; do + # tar -x -z --unlink -f $i + # done ! ! Else, if you are using csh: ! ! % foreach i (X332*.tgz) % tar -x -z --unlink -f $i % end *************** *** 288,294 **** First do numbers 1, 2 and 4 above. Then unpack the required archives: # for i in bin fnts lib xicf; do ! # tar -x -z --unlink -f X33$i.tgz # done Then unpack a server archive corresponding to your vga card. The server man --- 296,302 ---- First do numbers 1, 2 and 4 above. Then unpack the required archives: # for i in bin fnts lib xicf; do ! # tar -x -z --unlink -f X332$i.tgz # done Then unpack a server archive corresponding to your vga card. The server man *************** *** 296,302 **** For example, if you have an ET4000 based card you will use the XF86_SVGA server: ! # tar -x -z --unlink -f X33SVGA.tgz # cd /usr/X11R6/bin; rm X; ln -s XF86_SVGA X 2.3 After either Full or Minimal Install above: --- 304,310 ---- For example, if you have an ET4000 based card you will use the XF86_SVGA server: ! # tar -x -z --unlink -f X332SVGA.tgz # cd /usr/X11R6/bin; rm X; ln -s XF86_SVGA X 2.3 After either Full or Minimal Install above: *************** *** 315,328 **** # ldconfig /usr/lib /usr/local/lib /usr/X11R6/lib - If you had already configured X11R6/lib/X11/xinit/xinitrc or - X11R6/lib/X11/xdm/* omit the xinit-config or xdm-config archive or unpack it - separately and merge in your customizations. - The fscl and f100 archives are optional and can be omitted if you are short on - space. The optional link archive allows you to reconfigure and customize a X - server binary. The optional prog archive is needed only for writing or compil- - ing X applications. The optional pex archive contains pex clients and --- 323,329 ---- *************** *** 330,340 **** - README for XFree86 on FreeBSD libraries for building 3D graphics applications. NOTE: You don't need to uncompress the font files, but if you uncom- --- 331,348 ---- README for XFree86 on FreeBSD + If you had already configured X11R6/lib/X11/xinit/xinitrc or + X11R6/lib/X11/xdm/* omit the xinit-config or xdm-config archive or unpack it + separately and merge in your customizations. + + The fscl and f100 archives are optional and can be omitted if you are short on + space. The optional link archive allows you to reconfigure and customize a X + server binary. The optional prog archive is needed only for writing or compil- + ing X applications. The optional pex archive contains pex clients and libraries for building 3D graphics applications. NOTE: You don't need to uncompress the font files, but if you uncom- *************** *** 380,394 **** You'll need info on your hardware: - o Your mouse type, baud rate and its /dev entry. - o The video card's chipset (e.g. ET4000, S3, etc). - o Your monitor's sync frequencies. - The easiest way to find which device your mouse is plugged into is to use - ``cat'' or ``kermit'' to look at the output of the mouse. Connect to it and - just make sure that it generates output when the mouse is moved or clicked: --- 388,396 ---- *************** *** 395,410 **** - README for XFree86 on FreeBSD % cat < /dev/tty00 If you can't find the right mouse device then use ``dmesg|grep sio'' to get a ! list of devices that were detected upon booting: % dmesg|grep sio sio0 at 0x3f8-0x3ff irq 4 on isa --- 397,451 ---- + README for XFree86 on FreeBSD + o Your mouse type, baud rate and its /dev entry. + o The video card's chipset (e.g. ET4000, S3, etc). + o Your monitor's sync frequencies. + + If you plan to fine tune the screen size or position on your monitor you'll + need the specs for sync frequencies from your monitor's manual. + + When you run the `XF86Setup' utility, do NOT touch the mouse until you are fin- + ished with mouse set up. Otherwise, the VGA16 server and the mouse device + driver may get confused and you may experience mouse and/or keyboard input + problems. + + If you are running ``moused'' (see the man page for moused(8)) in FreeBSD ver- + sions 2.2.1 or later, you MUST specify SysMouse as the mouse protocol type and + /dev/sysmouse as the mouse device name, regardless of the brand and model of + your mouse. + + If you are NOT running ``moused'', you need to know the interface type of your + mouse, /dev entry and the protocol type to use. + + The interface type can be determined by looking at the connector of the mouse. + The serial mouse has a D-Sub female 9- or 25-pin connector. The bus mouse has + either a D-Sub male 9-pin connector or a round DIN 9-pin connector. The PS/2 + mouse is equipped with a small, round DIN 6-pin connector. Some mice come with + adapters with which the connector can be converted to another. If you are to + use such an adapter, remember the connector at the very end of the + mouse/adapter pair is what matters. + + The next thing to decide is a /dev entry for the given interface. For the bus + and PS/2 mice, there is little choice: the bus mouse always use /dev/mse0, and + the PS/2 mouse is always at /dev/psm0. There may be more than one serial port + to which the serial mouse can be attached. Many people often assign the first, + built-in serial port /dev/cuaa0 to the mouse. + + If you are not sure which serial device your mouse is plugged into, the easiest + way to find out the device is to use ``cat'' or ``kermit'' to look at the out- + put of the mouse. Connect to it and just make sure that it generates output + when the mouse is moved or clicked: + % cat < /dev/tty00 If you can't find the right mouse device then use ``dmesg|grep sio'' to get a ! list of serial devices that were detected upon booting: % dmesg|grep sio sio0 at 0x3f8-0x3ff irq 4 on isa *************** *** 415,429 **** % cd /dev % sh MAKEDEV tty00 - If you plan to fine tune the screen size or position on your monitor you'll - need the specs for sync frequencies from your monitor's manual. 5. Running X 8mb of memory is a recommended minimum for running X. The server, window man- ager, display manager and an xterm take about 8Mb of virtual memory themselves. Even if their resident set size is smaller, on a 8Mb system that leaves very space for other applications such as gcc that expect a few meg free. The R6 X servers may work with 4Mb of memory, but in practice compilation while running X can take 5 or 10 times as long due to constant paging. --- 456,538 ---- % cd /dev % sh MAKEDEV tty00 + + + + + + README for XFree86 on FreeBSD + + + + You may want to create a symbolic link /dev/mouse pointing to the real port to + which the mouse is connected, so that you can easily distinguish which is your + ``mouse'' port later. + + The next step is to guess the appropriate protocol type for the mouse. In + FreeBSD 2.2.6 or later, the X server may be able to automatically determine the + appropriate protocol type, unless your mouse is of a relatively old model. Use + the ``Auto'' protocol in these versions. + + In other versions of FreeBSD or if the ``Auto'' protocol doesn't work in 2.2.6, + you have to guess a protocol type and try. + + There is rule of thumb: + + 1. The bus mice always use the ``BusMouse'' protocol regardless of the brand + of the mouse. + + 2. The ``PS/2'' protocol should always be specified for the PS/2 mouse + regardless of the brand of the mouse. + + NOTE: There are quite a few PS/2 mouse protocols listed in the + man page for XF86Config. But, ``PS/2'' is the only PS/2 mouse + protocol type useful in XF86Config for FreeBSD. The other PS/2 + mouse protocol types are not supported in FreeBSD. FreeBSD + version 2.2.6 and later directly support these protocol types + in the PS/2 mouse driver psm and it is not necessary to tell + the X server which PS/2 mouse protocol type is to be used; + ``Auto'' should work, otherwise use ``PS/2''. + + 3. The ``Logitech'' protocol is for old mouse models from Logitech. Modern + Logitech mice use either the ``MouseMan'' or ``Microsoft'' protocol. + + 4. Most 2-button serial mice support the ``Microsoft'' protocol. + + 5. 3-button serial mice may work with the ``MouseSystems'' protocol. If it + doesn't, it may work with the ``Microsoft'' protocol although the third + (middle) button won't function. 3-button serial mice may also work with + the ``MouseMan'' protocol under which the third button may function as + expected. + + 6. 3-button serial mice may have a small switch to choose between ``MS'' and + ``PC'', or ``2'' and ``3''. ``MS'' or ``2'' usually mean the + ``Microsoft'' protocol. ``PC'' or ``3'' will choose the ``MouseSystems'' + protocol. + + 7. If the serial mouse has a roller or a wheel, it may be compatible with + the ``IntelliMouse'' protocol. + + 5. Running X 8mb of memory is a recommended minimum for running X. The server, window man- ager, display manager and an xterm take about 8Mb of virtual memory themselves. Even if their resident set size is smaller, on a 8Mb system that leaves very + + + + + + + + + README for XFree86 on FreeBSD + + + space for other applications such as gcc that expect a few meg free. The R6 X servers may work with 4Mb of memory, but in practice compilation while running X can take 5 or 10 times as long due to constant paging. *************** *** 449,490 **** system maintainers manual. If you do decide to reduce your kernel configuration file, do not remove the ! two lines below (in /sys/arch/i386/conf). They are both required for X sup- ! port: - options XSERVER #Xserver options UCONSOLE #X Console support ! README for XFree86 on FreeBSD - The generic FreeBSD kernels are configured by default with the syscons driver. - To configure your kernel similarly it should have a line like this in - /usr/src/sys/i386/conf/GENERIC: - device sc0 at isa? port "IO_KBD" tty irq 1 vector scintr - The number of virtual consoles can be set using the NCONS option: - options "NCONS=4" #4 virtual consoles - Otherwise, the default without a line like this is 12. You must have more VTs - than gettys as described in the end of section 3, and 4 is a reasonable mini- - mum. - The server supports several console drivers: pccons, syscons and pcvt. The - syscons driver is the default in FreeBSD 1.1.5 and higher. They are detected - at runtime and no configuration of the server itself is required. The XFree86 servers include support for the MIT-SHM extension. The GENERIC kernel does not support this, so if you want to make use of this, you will need a kernel configured with SYSV shared memory support. To do this, add the fol- --- 558,619 ---- system maintainers manual. If you do decide to reduce your kernel configuration file, do not remove the ! line below (in /sys/arch/i386/conf). It is required for X support: options UCONSOLE #X Console support + The generic FreeBSD kernels are configured by default with the syscons driver. + To configure your kernel similarly it should have a line like this in + /usr/src/sys/i386/conf/GENERIC: + device sc0 at isa? port "IO_KBD" tty irq 1 vector scintr + The number of virtual consoles can be set using the MAXCONS option: + options "MAXCONS=4" #4 virtual consoles + Otherwise, the default without a line like this is 16. You must have more VTs + than gettys as described in the end of section 3, and 4 is a reasonable mini- + mum. + The server supports two console drivers: syscons and pcvt. The syscons driver + is the default in FreeBSD 1.1.5 and higher. They are detected at runtime and + no configuration of the server itself is required. + If you intend to use pcvt as the console driver, be sure to include the follow- + ing option in your kernel configuration file. + options XSERVER #Xserver ! The number of virtual consoles in pcvt can be set using the following option: + README for XFree86 on FreeBSD + + + + options "PCVT_NSCREENS=10" #10 virtual consoles + + The bus mouse driver and the PS/2 mouse driver may not be included, or may be + included but disabled in your kernel. If you intend to use these mice, verify + the following lines in the kernel configuration file: + + device mse0 at isa? port 0x23c tty irq 5 vector mseintr + device psm0 at isa? port "IO_KBD" conflicts tty irq 12 vector psmintr + + The mse0 device is for the bus mouse and the psm device is for the PS/2 mouse. + Your bus mouse interface card may allow you to change IRQ and the port address. + Please refer to the manual of the bus mouse and the manual page for mse(4) for + details. There is no provision to change IRQ and the port address of the PS/2 + mouse. + The XFree86 servers include support for the MIT-SHM extension. The GENERIC kernel does not support this, so if you want to make use of this, you will need a kernel configured with SYSV shared memory support. To do this, add the fol- *************** *** 520,527 **** To ensure that this symbol is correctly defined, include in the source that requires it. Note that the symbol CSRG_BASED is defined for *BSD ! systems in XFree86 3.1.1 and later. This should be used to protect the --- 649,658 ---- To ensure that this symbol is correctly defined, include in the source that requires it. Note that the symbol CSRG_BASED is defined for *BSD ! systems in XFree86 3.1.1 and later. This should be used to protect the inclu- ! sion of . + For code that really is specific to a particular i386 BSD port, use __FreeBSD__ *************** *** 529,541 **** README for XFree86 on FreeBSD - inclusion of . - - For code that really is specific to a particular i386 BSD port, use __FreeBSD__ for FreeBSD, __NetBSD__ for NetBSD, __OpenBSD__ for OpenBSD, __386BSD__ for 386BSD, and __bsdi__ for BSD/386. --- 660,670 ---- + README for XFree86 on FreeBSD for FreeBSD, __NetBSD__ for NetBSD, __OpenBSD__ for OpenBSD, __386BSD__ for 386BSD, and __bsdi__ for BSD/386. *************** *** 556,568 **** o Orest Zborowski, Simon Cooper and Dirk Hohndel for ideas from the Linux distribution. ! Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/FreeBSD.sgml,v 3.25.2.1 1997/05/17 12:03:29 dawes Exp $ ! $TOG: READ.FreeBSD /main/16 1997/07/19 10:26:17 kaleb $ --- 685,697 ---- o Orest Zborowski, Simon Cooper and Dirk Hohndel for ideas from the Linux distribution. ! Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/FreeBSD.sgml,v 3.25.2.3 1998/02/26 13:59:06 dawes Exp $ ! $TOG: READ.FreeBSD /main/17 1998/03/06 16:38:03 kaleb $ *************** *** 595,600 **** --- 724,732 ---- + + + README for XFree86 on FreeBSD *************** *** 680,692 **** 4. Configuring X for Your Hardware .......................................... 6 ! 5. Running X ................................................................ 7 ! 6. Rebuilding Kernels for X ................................................. 7 ! 7. Building X Clients ....................................................... 8 ! 8. Thanks ................................................................... 9 --- 812,824 ---- 4. Configuring X for Your Hardware .......................................... 6 ! 5. Running X ................................................................ 8 ! 6. Rebuilding Kernels for X ................................................. 9 ! 7. Building X Clients ...................................................... 10 ! 8. Thanks .................................................................. 11 *************** *** 725,728 **** ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/READ.FreeBSD,v 3.31.2.1 1997/05/17 12:25:11 dawes Exp $ --- 857,860 ---- ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/READ.FreeBSD,v 3.31.2.3 1998/02/27 02:54:55 dawes Exp $ *** ./programs/Xserver/hw/xfree86/doc/READ.Mach64@@/PUBLIC-LATEST Sat Jul 19 10:26:28 1997 --- xc/programs/Xserver/hw/xfree86/doc/READ.Mach64 Fri Mar 6 16:36:31 1998 *************** *** 11,17 **** Kevin E. Martin (martin@cs.unc.edu) ! 23 January 1997 --- 11,17 ---- Kevin E. Martin (martin@cs.unc.edu) ! 25 February 1998 *************** *** 22,27 **** --- 22,76 ---- able (see the table below). What determines this support is the RAMDAC on your card. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Mach64 X Server Release Notes + + + + + + Mach64 X Server Release Notes + + + RAMDAC Max Dot Clock BPP Max Resolution Video RAM Required -------- ------------- --- -------------- ------------------ ATI68860 135MHz 8 1280x1024 2Mb *************** *** 46,55 **** AT&T20C408 80MHz 16 1024x768 2Mb AT&T20C408 40MHz 32 800x600 2Mb ! 3D Rage II (Int) 170MHz 8 1600x1200 4Mb ! 3D Rage II (Int) 170MHz 16 1600x1200 4Mb ! 3D Rage II (Int) 135MHz 32 1024x768 4Mb Internal 135MHz 8 1280x1024 2Mb Internal 80MHz 16 1024x768 2Mb Internal 40MHz 32 800x600 2Mb --- 95,112 ---- AT&T20C408 80MHz 16 1024x768 2Mb AT&T20C408 40MHz 32 800x600 2Mb ! 3D Rage II 170MHz 8 1600x1200 4Mb ! 3D Rage II 170MHz 16 1600x1200 4Mb ! 3D Rage II 170MHz 32 1024x768 4Mb + 3D Rage II+DVD 200MHz 8 1600x1200 4Mb + 3D Rage II+DVD 200MHz 16 1600x1200 4Mb + 3D Rage II+DVD 200MHz 32 1024x768 4Mb + + Rage Pro 230MHz 8 1600x1200 8Mb + Rage Pro 230MHz 16 1600x1200 8Mb + Rage Pro 230MHz 32 1600x1200 8Mb + Internal 135MHz 8 1280x1024 2Mb Internal 80MHz 16 1024x768 2Mb Internal 40MHz 32 800x600 2Mb *************** *** 61,83 **** All Others[*] 80MHz 8 1280x1024 2Mb ! Mach64 X Server Release Notes - Mach64 X Server Release Notes - [*] - The dot clocks are limited to 80MHz and the bpp is limited to 8. - The table above specifies the maximum resolution and the video memory required - to run this maximum resolution. Smaller resolutions will require less video - memory. ! The RAMDAC is reported when you run the Mach64 X server with the "-probeonly" command line option. The RAMDAC reported should be correct for all Mach64 cards. It can also be specified in the XF86Config file, but this is not recom- mended unless the RAMDAC reported in the probeonly output is incorrect. Before --- 118,142 ---- All Others[*] 80MHz 8 1280x1024 2Mb ! [*] - The dot clocks are limited to 80MHz and the bpp is limited to 8. + The table above specifies the maximum resolution and the video memory required + to run this maximum resolution. Smaller resolutions will require less video + memory. + The RAMDAC is reported when you run the Mach64 X server with the "-probeonly" ! Mach64 X Server Release Notes ! ! ! command line option. The RAMDAC reported should be correct for all Mach64 cards. It can also be specified in the XF86Config file, but this is not recom- mended unless the RAMDAC reported in the probeonly output is incorrect. Before *************** *** 91,99 **** The ATI68860 RAMDACs are usually found on ATI Graphics Pro Turbo and ATI Win- Turbo cards. The IBM RGB514 RAMDAC is found on the ATI Graphics Pro Turbo 1600 card. The other RAMDACs are usually found on ATI Graphics Xpression, ATI Video ! Xpression and ATI 3d Xpression cards. Mach64 CT, ET, VT, GT (3D Rage) and 3D ! Rage II chips have an "Internal" RAMDAC (i.e., it is built into the Mach64 ! chip). As advertised, Mach64 graphics cards can use a special 24bpp mode (packed pixel mode), but this is not currently supported in the Mach64 X server. This will --- 150,158 ---- The ATI68860 RAMDACs are usually found on ATI Graphics Pro Turbo and ATI Win- Turbo cards. The IBM RGB514 RAMDAC is found on the ATI Graphics Pro Turbo 1600 card. The other RAMDACs are usually found on ATI Graphics Xpression, ATI Video ! Xpression and ATI 3d Xpression cards. Mach64 CT, ET, VT, GT (3D Rage), 3D Rage ! II, 3D Rage II+DVD and Rage Pro chips have an "Internal" RAMDAC (i.e., it is ! built into the Mach64 chip). As advertised, Mach64 graphics cards can use a special 24bpp mode (packed pixel mode), but this is not currently supported in the Mach64 X server. This will *************** *** 104,113 **** will not work. If you have a PCI based Mach64 card or a VLB based Mach64 card, then the Mach64 X server will work with any amount of main memory. ! Accelerated doublescan modes are supported on VT, GT and 3D Rage II based ! Mach64 cards. Mach64 cards with other chips cannot handle accelerated double ! scan modes due to a hardware limitation. Non-accelerated doublescan modes ! should work with the ATI driver in the SVGA X server for all Mach64 cards. 2. Optimizing the speed of the Mach64 X server --- 163,173 ---- will not work. If you have a PCI based Mach64 card or a VLB based Mach64 card, then the Mach64 X server will work with any amount of main memory. ! Accelerated doublescan modes are supported on VT, GT, 3D Rage II, 3D Rage ! II+DVD and Rage Pro based Mach64 cards. Mach64 cards with other chips cannot ! handle accelerated double scan modes due to a hardware limitation. Non-accel- ! erated doublescan modes should work with the ATI driver in the SVGA X server ! for all Mach64 cards. 2. Optimizing the speed of the Mach64 X server *************** *** 116,142 **** lowing maximum resolutions. This will allow room for the font and pixmap caches and a hardware cursor. - - - - - - - - - - - - - - - - - - Mach64 X Server Release Notes - - - Max Resolution BPP Video RAM -------------- --- --------- 1280x1024 8 4Mb --- 176,181 ---- *************** *** 152,157 **** --- 191,208 ---- [*] - With a 2MB video card, the only way to use the font and pixmap caches is to have a virtual resolution of 1024x480 with a 640x480 mode. I suggest using + + + + + + + + + Mach64 X Server Release Notes + + + 800x600 to maximize your screen size at the cost of the speed gained from the caches. The same argument can be made for 1MB video cards running in 16bpp mode. Note that it is not possible to run in 32bpp mode with 1MB of video mem- *************** *** 181,187 **** preprogrammed clocks, you can turn off the clock programming with the "no_pro- gram_clocks" option. In this case, the Mach64 X server reads the Clocks from the BIOS. The "Clocks" lines in the XF86Config file are normally ignored by ! the Mach64 X server unless the "no_bios_clocks" option is given. Option "sw_cursor" This option allows you to use the software cursor instead of the --- 232,241 ---- preprogrammed clocks, you can turn off the clock programming with the "no_pro- gram_clocks" option. In this case, the Mach64 X server reads the Clocks from the BIOS. The "Clocks" lines in the XF86Config file are normally ignored by ! the Mach64 X server unless the "no_bios_clocks" option is given. Note on newer ! Mach64 cards (CT, ET, VT, GT, 3D Rage II, 3D Rage II+DVD and Rage Pro) the ! "Ramdac", "ClockChip" and "Clocks" lines have no meaning and should not be ! included in your XF86Config file. Option "sw_cursor" This option allows you to use the software cursor instead of the *************** *** 192,198 **** --- 246,260 ---- essary since the hardware cursor is used by default unless the "sw_cursor" option is specified. + Option "composite" + This option will set the composite sync for monitors that require + this. + Option "dac_8_bit" + This option enables 8 bits per RGB value. Note that this does not + work with the Chrontel 8398 RAMDAC. This options is not necessary + since 8 bits per RGB value is the default for the Mach64 X server + for all Mach64 cards except those with the Chrontel 8398 RAMDAC. *************** *** 199,218 **** - Mach64 X Server Release Notes - Option "composite" - This option will set the composite sync for monitors that require - this. ! Option "dac_8_bit" ! This option enables 8 bits per RGB value. Note that this does not ! work with the Chrontel 8398 RAMDAC. This options is not necessary ! since 8 bits per RGB value is the default for the Mach64 X server ! for all Mach64 cards except those with the Chrontel 8398 RAMDAC. Option "dac_6_bit" This option enables 6 bits per RGB value. --- 261,274 ---- ! Mach64 X Server Release Notes + + Option "dac_6_bit" This option enables 6 bits per RGB value. *************** *** 257,263 **** --- 313,328 ---- BIOS clocks and the clocks specified in the Clocks line unless the "no_program_clocks" options is set (see above). + Option "no_font_cache" + This option allows you to disable the font cache. By default the + font cache is turned on if the horizontal resolution is 1024 pixels + or greater and there is enough off-screen video memory to hold the + cache. + Option "no_pixmap_cache" + This option allows you to disable the pixmap cache. By default the + pixmap cache is turned on if the horizontal resolution is 1024 pix- + els or greater and there is enough off-screen video memory to hold *************** *** 265,284 **** Mach64 X Server Release Notes - Option "no_font_cache" - This option allows you to disable the font cache. By default the - font cache is turned on if the horizontal resolution is 1024 pixels - or greater and there is enough off-screen video memory to hold the - cache. - - Option "no_pixmap_cache" - This option allows you to disable the pixmap cache. By default the - pixmap cache is turned on if the horizontal resolution is 1024 pix- - els or greater and there is enough off-screen video memory to hold the cache. MemBase baseaddress --- 330,340 ---- + Mach64 X Server Release Notes the cache. MemBase baseaddress *************** *** 323,340 **** o ibm_rgb514 - - - - - - - - - Mach64 X Server Release Notes - - - o internal o stg1702 --- 379,384 ---- *************** *** 343,426 **** o tlc34075 - 4. Known Problems and Bug Reports - There are several known problems with the current version of the Mach64 X - server. They include: - o Screen blanking in 16bpp and 32bpp modes on certain Mach64 CT cards does - not work. - o In doublescan modes, only the top half of the hardware cursor is dis- - played. The hardware cursor works fine in all other modes. - o Text may not be displayed correctly in certain programs. - o Some RAMDACs are incorrectly reported by the BIOS. This can be handled by - explicitly specifying the RAMDAC in the XF86Config file. This should no - longer be a problem. - o ISA cards with more than 12Mb of main memory cannot use the server due to - the requirement of a video memory aperture. This a major project. - If you are experiencing problems, first check to make sure that you have the - very latest available release (including beta releases). ATI releases new - cards throughout the year. Each of these new cards require additional program- - ming to support the new Mach64 chips, RAMDACs and clock chips that appear on - them. The most recent release is most likely to support your video card. - - Second, please check the RELNOTES and README files (as well as the other docu- - mentation available with the release). Third, make sure you do not have any - Ramdac, ClockChip or Clocks lines in your XF86Config file (all of these are - automatically detected by the Mach64 X server). - - If you are still experiencing problems, please send e-mail to - XFree86@XFree86.org or post to the comp.windows.x.i386unix newsgroup. - - Please do NOT send e-mail to me since the developers who answer e-mail sent to - XFree86@XFree86.org are better able to answer most questions and I would like - to spend my minimal free time working on new enhancements to the X server. - Thanks! - - - - - - - - - - - - - - - Mach64 X Server Release Notes ! Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/Mach64.sgml,v 3.15 1997/01/25 03:21:59 dawes Exp $ ! $TOG: READ.Mach64 /main/10 1997/07/19 10:26:30 kaleb $ --- 387,460 ---- o tlc34075 + DacSpeed "MHz" + This entry allows you to override the default maximum dot clock. Mach64 X Server Release Notes ! Use this option with extreme caution. If you specify a MHz value ! too large for your card, you can damage it. + 4. Enhancements for this release + With this release, the following enhancements have been made: + o Proper identification of all current Mach64 chips ! o Support for 16MB boards + o Increased max DAC speed settings for newer chips + o Support for RagePro cards (including AGP cards) + o Block write mode for RagePro based cards + o 1600x1200, 1600x1280 and other high resolution mode support for VT and + newer chips + o Use of the auxiliary register aperture on chips that support it + o Use of 16MB memory aperture on PCI Mach64s with integrated controllers + 5. Cards known to work with this release + The following is a list of cards that have been tested with this release. Many + other cards should work including All-In-Wonder and All-In-Wonder Pro cards as + well as motherboards with Mach64, 3D Rage II and Rage Pro included on them. If + you have a new card that does not appear to work, see the Known Problems and + Bug Reports section below. + ATI Xpert@Play 8MB 3D Rage Pro (PCI, rev 92) + ATI Xpert@Work 2MB 3D Rage Pro (PCI, rev 92) + ATI Pro Turbo+PC2TV 4MB 3D Rage II+DVD (rev 154) + ATI 3D Xpression+ 4MB 3D Rage II (GT-B, SGRAM, rev 65) + ATI 3D Xpression+ 2MB 3D Rage II (GT-B, SDRAM, rev 65) + ATI 3D Xpression 2MB 3D Rage (GT-A, rev 72) + ATI Video Xpression+ 2MB Mach64 VT-A3 (rev 8) + ATI Video Xpression 2MB Mach64 VT-A4 (rev 72) + ATI Graphics Xpression 2MB Mach64 CT (rev 9) + ATI Graphics Xpression 2MB Mach64 CT-C (rev 65) + ATI Graphics Xpression 2MB Mach64 CT-D (rev 10) + ATI Graphics Xpression 2MB Mach64 GX (rev 1) with Chrontel8398 RAMDAC + ATI Graphics Pro Turbo 2MB Mach64 GX (rev 0) with 68860-B RAMDAC + ATI Graphics Pro Turbo 2MB Mach64 CX (rev 1) with AT RAMDAC + ATI WinTurbo 2MB Mach64 GX (rev 1) with 68860-C RAMDAC + 6. Known Problems and Bug Reports + There are several known problems with the current version of the Mach64 X *************** *** 429,452 **** --- 463,518 ---- + Mach64 X Server Release Notes + server. They include: + o Screen blanking in 16bpp and 32bpp modes on certain Mach64 CT cards does + not work. + o In doublescan modes, only the top half of the hardware cursor is dis- + played. The hardware cursor works fine in all other modes. + o Text may not be displayed correctly in certain programs. + o With high refresh rates on certain cards (VT-A3 and CT-D) noise can become + a problem in 32bpp mode. This usually only happens with refresh rates of + 85Hz or greater and can be fixed by using a lower refresh rate (e.g., 72Hz + or 75Hz). + o ISA cards with more than 12Mb of main memory cannot use the server due to + the requirement of a video memory aperture. This a major project. + If you are experiencing problems, first check to make sure that you have the + very latest available release (including beta releases). ATI releases new + cards throughout the year. Each of these new cards require additional program- + ming to support the new Mach64 chips, RAMDACs and clock chips that appear on + them. The most recent release is most likely to support your video card. + Second, please check the RELNOTES and README files (as well as the other docu- + mentation available with the release). Third, make sure you do not have any + Ramdac, ClockChip or Clocks lines in your XF86Config file (all of these are + automatically detected by the Mach64 X server). The "Device" section should + only contain the Identifier, VendorName and BoardName. All other options + should be automatically detected. + If you are still experiencing problems, please send e-mail to + XFree86@XFree86.org or post to the comp.windows.x.i386unix newsgroup. + Please do NOT send e-mail to me since the developers who answer e-mail sent to + XFree86@XFree86.org are better able to answer most questions and I would like + to spend my minimal free time working on new enhancements to the X server. + Thanks! + Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/Mach64.sgml,v 3.15.2.2 1998/02/26 23:32:28 dawes Exp $ + $TOG: READ.Mach64 /main/11 1998/03/06 16:38:09 kaleb $ *************** *** 539,551 **** 1. Supported Cards, RAMDACs, and Bits Per Pixel ............................. 1 ! 2. Optimizing the speed of the Mach64 X server .............................. 2 ! 3. XF86Config options ....................................................... 3 ! 4. Known Problems and Bug Reports ........................................... 6 --- 605,619 ---- 1. Supported Cards, RAMDACs, and Bits Per Pixel ............................. 1 ! 2. Optimizing the speed of the Mach64 X server .............................. 3 ! 3. XF86Config options ....................................................... 4 ! 4. Enhancements for this release ............................................ 7 + 5. Cards known to work with this release .................................... 7 + 6. Known Problems and Bug Reports ........................................... 7 *************** *** 587,596 **** - - i ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/READ.Mach64,v 3.10 1997/01/27 22:12:32 dawes Exp $ --- 655,662 ---- i ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/READ.Mach64,v 3.10.2.1 1998/02/27 02:54:56 dawes Exp $ *** ./programs/Xserver/hw/xfree86/doc/README@@/PUBLIC-LATEST Sun Aug 10 13:02:20 1997 --- xc/programs/Xserver/hw/xfree86/doc/README Fri Mar 6 16:36:36 1998 *************** *** 1,19 **** ! README for XFree86[tm] 3.3.1 ! README for XFree86[tm] 3.3.1 The XFree86 Project, Inc ! 26 July 1997 --- 1,19 ---- ! README for XFree86[tm] 3.3.2 ! README for XFree86[tm] 3.3.2 The XFree86 Project, Inc ! 28 January 1998 *************** *** 21,43 **** XFree86 is a port of X11R6.3 that supports several Unix and Unix-like operating systems on Intel and other platforms. This release is a ! maintenance release, fixing bugs found in XFree86 3.3. It also ! includes the latest public patch for X11R6.3 (patch 2). The release is available as source patches against the X Consortium X11R6.3 code ! and the XFree86 3.3 release. Binary distributions for many architec- ! tures are also available, including a binary upgrade for XFree86 3.3. ! 1. What's new in XFree86 3.3.1 For a summary of new features in this release, please refer to the RELNOTES ! file. - For a detailed list of changes, refer to the CHANGELOG file in the source dis- - tribution. - 2. Systems XFree86 has been tested on Note: Not all systems listed here have been tested with the current release. --- 21,41 ---- XFree86 is a port of X11R6.3 that supports several Unix and Unix-like operating systems on Intel and other platforms. This release is a ! maintenance release, fixing bugs found in XFree86 3.3.1. The release is available as source patches against the X Consortium X11R6.3 code ! and the XFree86 3.3.1 release. Binary distributions for many archi- ! tectures are also available, including a binary upgrade for XFree86 ! 3.3.1. ! 1. What's new in XFree86 3.3.2 For a summary of new features in this release, please refer to the RELNOTES ! file. For a detailed list of changes, refer to the CHANGELOG file in the ! source distribution. 2. Systems XFree86 has been tested on Note: Not all systems listed here have been tested with the current release. *************** *** 58,81 **** o ISC: 4.0.3 - README for XFree86[tm] 3.3.1 - README for XFree86[tm] 3.3.1 - o AT&T: 2.1, 4.0 o NCR: MP-RAS ! o SunSoft: Solaris x86 2.1, 2.4, 2.5, 2.5.1 o PANIX 5.0 for AT --- 56,79 ---- o ISC: 4.0.3 + o AT&T: 2.1, 4.0 + README for XFree86[tm] 3.3.2 + README for XFree86[tm] 3.3.2 o NCR: MP-RAS ! o SunSoft: Solaris x86 2.1, 2.4, 2.5, 2.5.1, 2.6 o PANIX 5.0 for AT *************** *** 94,105 **** Others: ! o NetBSD 1.0, 1.1, 1.2, 1.2.1 o OpenBSD 2.0, 2.1 o FreeBSD 2.0.5, 2.1, 2.1.5, 2.1.6, 2.1.7, 2.1.7.1, 2.2, 2.2.1, ! 2.2.2, 3.0-current o Linux (Intel x86, DEC Alpha/AXP and m68k) --- 92,103 ---- Others: ! o NetBSD 1.0, 1.1, 1.2, 1.2.1, 1.3 o OpenBSD 2.0, 2.1 o FreeBSD 2.0.5, 2.1, 2.1.5, 2.1.6, 2.1.7, 2.1.7.1, 2.2, 2.2.1, ! 2.2.2, 2.2.5, 3.0-current o Linux (Intel x86, DEC Alpha/AXP and m68k) *************** *** 114,129 **** PC98: ! o FreeBSD(98) 2.0.5, 2.1, 2.1.5, 2.2, 2.2.1 ! o NetBSD/pc98 (based on NetBSD 1.2) o PANIX 5.0 for 98 3. Supported video-card chip-sets ! At this time, XFree86 3.3.1 supports the following chipsets: --- 112,130 ---- PC98: ! o FreeBSD(98) 2.0.5, 2.1, 2.1.5, 2.1.7.1, 2.2, 2.2.1, 2.2.2, ! 2.2.5 ! o NetBSD/pc98 (based on NetBSD 1.2, 1.2.1) o PANIX 5.0 for 98 + o Linux/98 + 3. Supported video-card chip-sets ! At this time, XFree86 3.3.2 supports the following chipsets: *************** *** 132,142 **** - README for XFree86[tm] 3.3.1 - Ark Logic ARK1000PV, ARK1000VL, ARK2000PV, ARK2000MT --- 133,142 ---- + README for XFree86[tm] 3.3.2 Ark Logic ARK1000PV, ARK1000VL, ARK2000PV, ARK2000MT *************** *** 146,153 **** ATI 18800, 18800-1, 28800-2, 28800-4, 28800-5, 28800-6, 68800-3, 68800-6, 68800AX, 68800LX, 88800GX-C, 88800GX-D, 88800GX-E, ! 88800GX-F, 88800CX, 264CT, 264ET, 264VT, 264VT2, 264GT (this list ! includes the Mach8, Mach32, Mach64, 3D Rage and 3D Rage II) Avance Logic ALG2101, ALG2228, ALG2301, ALG2302, ALG2308, ALG2401 --- 146,154 ---- ATI 18800, 18800-1, 28800-2, 28800-4, 28800-5, 28800-6, 68800-3, 68800-6, 68800AX, 68800LX, 88800GX-C, 88800GX-D, 88800GX-E, ! 88800GX-F, 88800CX, 264CT, 264ET, 264VT, 264GT, 264VT-B, 264VT3, ! 264GT-B, 264GT3 (this list includes the Mach8, Mach32, Mach64, 3D ! Rage, 3D Rage II and 3D Rage Pro) Avance Logic ALG2101, ALG2228, ALG2301, ALG2302, ALG2308, ALG2401 *************** *** 154,160 **** Chips & Technologies 65520, 65530, 65540, 65545, 65520, 65530, 65540, 65545, 65546, ! 65548, 65550, 65554, 65555, 68554 Cirrus Logic CLGD5420, CLGD5422, CLGD5424, CLGD5426, CLGD5428, CLGD5429, --- 155,161 ---- Chips & Technologies 65520, 65530, 65540, 65545, 65520, 65530, 65540, 65545, 65546, ! 65548, 65550, 65554, 65555, 68554, 64200, 64300 Cirrus Logic CLGD5420, CLGD5422, CLGD5424, CLGD5426, CLGD5428, CLGD5429, *************** *** 179,185 **** AGX-014, AGX-015, AGX-016 Matrox ! MGA2064W (Millennium), MGA1064SG (Mystique) MX MX68000(*), MX680010(*) --- 180,187 ---- AGX-014, AGX-015, AGX-016 Matrox ! MGA2064W (Millennium), MGA1064SG (Mystique and Mystique 220), ! MGA2164W (Millennium II PCI and AGP) MX MX68000(*), MX680010(*) *************** *** 188,194 **** 77C22(*), 77C22E(*), 77C22E+(*) Number Nine ! I128 (series I and II) --- 190,196 ---- 77C22(*), 77C22E(*), 77C22E+(*) Number Nine ! I128 (series I and II), Revolution 3D (T2R) *************** *** 197,210 **** - README for XFree86[tm] 3.3.1 - - NVidia/SGS Thomson ! NV1, STG2000 OAK OTI067, OTI077, OTI087 --- 199,210 ---- + README for XFree86[tm] 3.3.2 NVidia/SGS Thomson ! NV1, STG2000, RIVA128 OAK OTI067, OTI077, OTI087 *************** *** 214,234 **** S3 86C911, 86C924, 86C801, 86C805, 86C805i, 86C928, 86C864, 86C964, ! 86C732, 86C764, 86C765, 86C767, 86C775, 86C868, 86C968, 86C325, ! 86C375, 86C385, 86C988, 86CM65 SiS 86C201, 86C202, 86C205 Tseng ! ET3000, ET4000AX, ET4000/W32, ET4000/W32i, ET4000/W32p, ET6000 Trident TVGA8800CS, TVGA8900B, TVGA8900C, TVGA8900CL, TVGA9000, TVGA9000i, ! TVGA9100B, TVGA9200CXR, TVGA9320(*), TVGA9400CXi, TVGA9420, TGUI9420DGi, TGUI9430DGi, TGUI9440AGi, TGUI9660XGi, TGUI9680, Pro- ! Vidia 9682, ProVidia 9685, ProVidia 9692, Cyber 9382(*), Cyber ! 9385(*) Video 7/Headland Technologies HT216-32(*) --- 214,235 ---- S3 86C911, 86C924, 86C801, 86C805, 86C805i, 86C928, 86C864, 86C964, ! 86C732, 86C764, 86C765, 86C767, 86C775, 86C785, 86C868, 86C968, ! 86C325, 86C357, 86C375, 86C375, 86C385, 86C988, 86CM65, 86C260 SiS 86C201, 86C202, 86C205 Tseng ! ET3000, ET4000AX, ET4000/W32, ET4000/W32i, ET4000/W32p, ET6000, ! ET6100 Trident TVGA8800CS, TVGA8900B, TVGA8900C, TVGA8900CL, TVGA9000, TVGA9000i, ! TVGA9100B, TVGA9200CXR, Cyber9320(*), TVGA9400CXi, TVGA9420, TGUI9420DGi, TGUI9430DGi, TGUI9440AGi, TGUI9660XGi, TGUI9680, Pro- ! Vidia 9682, ProVidia 9685(*), Cyber 9382, Cyber 9385, Cyber 9388, ! 3DImage975(PCI), 3DImage985(AGP), Cyber 9397, Cyber 9520 Video 7/Headland Technologies HT216-32(*) *************** *** 256,262 **** The monochrome server also supports generic VGA cards, using 64k of video mem- ory in a single bank, the Hercules monochrome card, the Hyundai HGC1280, Sigma - LaserView, Visa and Apollo monochrome cards. --- 257,262 ---- *************** *** 265,288 **** ! README for XFree86[tm] 3.3.1 The VGA16 server supports memory banking with the ET4000, Trident, ATI, NCR, OAK and Cirrus 6420 chipsets allowing virtual display sizes up to about 1600x1200 (with 1MB of video memory). For other chipsets the display size is limited to approximately 800x600. ! Note: The Diamond SpeedStar 24 (and possibly some SpeedStar+) boards are NOT supported, even though they use the ET4000. The Weitek 9100 and 9130 chipsets are not supported (these are used on the Dia- ! mond Viper Pro and Viper SE boards). The chips used on the FireGL boards are ! not currently supported. Most other Diamond boards will work with this release ! of XFree86. Diamond is actively supporting The XFree86 Project, Inc. 4. Where to get more information Additional documentation is available in the XFree86(1), XF86Config(4/5), --- 265,304 ---- ! README for XFree86[tm] 3.3.2 + LaserView, Visa and Apollo monochrome cards. + The VGA16 server supports memory banking with the ET4000, Trident, ATI, NCR, OAK and Cirrus 6420 chipsets allowing virtual display sizes up to about 1600x1200 (with 1MB of video memory). For other chipsets the display size is limited to approximately 800x600. ! Notes: The Diamond SpeedStar 24 (and possibly some SpeedStar+) boards are NOT supported, even though they use the ET4000. The Weitek 9100 and 9130 chipsets are not supported (these are used on the Dia- ! mond Viper Pro and Viper SE boards). Most other Diamond boards will work with ! this release of XFree86. Diamond is actively supporting The XFree86 Project, ! Inc. + 3DLabs GLINT, Permedia and Permedia 2 support could unfortunately not be + included in XFree86 3.3.2 since there are open issues regarding the documenta- + tion and whether or not they were provided to us under NDA. + S.u.S.E. will continue to make available binary only servers for these cards. + These servers can be freely distributed just like XFree86, but sources cannot + be made available. S.u.S.E. will continue to develop these servers and will + continue to try to donate the code back to XFree86. For the time being S.u.S.E. + will try to not only make Linux binaries available, but binaries for other + platforms as well. + + Please contact x@suse.de with further questions. You can find the servers at + http://www.suse.de/XSuSE/XSuSE_E.html + + 4. Where to get more information Additional documentation is available in the XFree86(1), XF86Config(4/5), *************** *** 307,340 **** the latest release of XFree86. Check the versions listed on ftp://ftp.xfree86.org/pub/XFree86. - There is a Usenet news group comp.windows.x.i386unix that contains mostly dis- - cussions about XFree86 and related topics. Many questions can be answered - there. - 5. Thanks - The XFree86 Project wants to express a special thanks to S.u.S.E. GmbH, Fürth, - Germany, for hiring our Core Team member and Vice President Dirk Hohndel as an - employee and allowing him to work more or less full time on XFree86 for the - past 5 months. Without this significant investment from S.u.S.E. into XFree86 - the 3.3 release would not have been possible in this form and at this time, and - the work on our 4.0 branch wouldn't be where it is today. ! README for XFree86[tm] 3.3.1 - 6. Credits XFree86 was originally put together by: --- 323,357 ---- the latest release of XFree86. Check the versions listed on ftp://ftp.xfree86.org/pub/XFree86. + README for XFree86[tm] 3.3.2 + There is a Usenet news group comp.windows.x.i386unix that contains mostly dis- + cussions about XFree86 and related topics. Many questions can be answered + there. + 5. Thanks ! The XFree86 Project wants to express a special thanks to S.u.S.E. GmbH, Fuerth, ! Germany, for the long and successful cooperation over the last few years. ! S.u.S.E. GmbH at one point hired our Core Team member and Vice President Dirk ! Hohndel as an employee and allowed him to work more or less full time on ! XFree86 for almost nine months. S.u.S.E. continues to be a significant source ! of input and help to XFree86. This manifested itself in the XSuSE series of X ! servers that have all except for the GLINT server (due to unresolved legal ! issues) been integrated into XFree86 3.3.2. 6. Credits XFree86 was originally put together by: *************** *** 371,406 **** o David Holland - o Alan Hourihane - o Jeffrey Hsu - o Glenn Lai - o Ted Lemon - o Rich Murphey - o Hans Nasten - o Mark Snitily - o Randy Terbush - o Jon Tombs ! README for XFree86[tm] 3.3.1 o Kees Verstoep o Paul Vixie --- 388,424 ---- o David Holland + README for XFree86[tm] 3.3.2 + o Alan Hourihane + o Jeffrey Hsu + o Glenn Lai + o Ted Lemon + o Rich Murphey ! o Hans Nasten + o Mark Snitily + o Randy Terbush + o Jon Tombs + o Kees Verstoep o Paul Vixie *************** *** 437,471 **** o Orest Zborowski - SCO Unix support by: - o David McCullough - Amoeba support by: - o Kees Verstoep - Minix-386 support by: - o Philip Homburg - OSF/1 support by: - o Marc Evans ! BSD/OS support by: ! README for XFree86[tm] 3.3.1 o Hans Nasten , --- 455,489 ---- o Orest Zborowski ! README for XFree86[tm] 3.3.2 + SCO Unix support by: + o David McCullough + Amoeba support by: + o Kees Verstoep + Minix-386 support by: + o Philip Homburg ! OSF/1 support by: + o Marc Evans + BSD/OS support by: o Hans Nasten , *************** *** 483,489 **** LynxOS support by: ! o Thomas Mueller OS/2 support by: --- 501,507 ---- LynxOS support by: ! o Thomas Mueller OS/2 support by: *************** *** 503,537 **** o Hiroyuki Aizu , - o Tetsuya Kakefuda , - o Takefumi Tsukada , - o H.Komatsuzaki, - o Naoki Katsurakawa , - o Shuichiro Urata , - o Yasuyuki Kato , - o Michio Jinbo , - o Tatsuya Koike , ! o Koichiro Suzuki , ! README for XFree86[tm] 3.3.1 o Tsuyoshi Tamaki , --- 521,555 ---- o Hiroyuki Aizu , ! README for XFree86[tm] 3.3.2 + o Tetsuya Kakefuda , + o Takefumi Tsukada , + o H.Komatsuzaki, + o Naoki Katsurakawa , + o Shuichiro Urata , + o Yasuyuki Kato , ! o Michio Jinbo , + o Tatsuya Koike , + o Koichiro Suzuki , o Tsuyoshi Tamaki , *************** *** 549,555 **** o Ishida Kazuo , ! o Takaaki Nomura , o Tadaaki Nagao , --- 567,573 ---- o Ishida Kazuo , ! o Takaaki Nomura , o Tadaaki Nagao , *************** *** 563,604 **** o Yasuhiro Ichikawa , ! o Kazunori Ueno , o Yasushi Suzuki , ! o Masato Yoshida (Contributor of PW805i support) - Original accelerated code by: - o Kevin Martin , - o Rik Faith , - o Jon Tombs - XFree86 Acceleration Architecture (XAA) by: - o Harm Hanemaayer , - S3 accelerated code by: - o Jon Tombs , ! o Harald Koenig , ! README for XFree86[tm] 3.3.1 o David Wexelblat , o David Dawes , --- 581,632 ---- o Yasuhiro Ichikawa , ! o Kazunori Ueno , o Yasushi Suzuki , ! o Satoshi Kimura , ! README for XFree86[tm] 3.3.2 + o Kazuhiko Uno , + o Tomiharu Takigami , + o Tomomi Suzuki , + o Toshihiko Yagi , + o Masato Yoshida (Contributor of PW805i support) + Original accelerated code by: ! o Kevin Martin , + o Rik Faith , + o Jon Tombs + XFree86 Acceleration Architecture (XAA) by: + + o Harm Hanemaayer , + + S3 accelerated code by: + + o Jon Tombs , + + o Harald Koenig , + o David Wexelblat , o David Dawes , *************** *** 625,630 **** --- 653,670 ---- o Berry Dijk + + + + + + + + + README for XFree86[tm] 3.3.2 + + + o Dirk Hohndel o Huver Hu *************** *** 653,670 **** o Kevin Martin , - - - - - - - - - README for XFree86[tm] 3.3.1 - - - o Rik Faith , o Tiago Gons , --- 693,698 ---- *************** *** 681,687 **** o Bill Reynolds , ! o Corin Anderson Western Digital accelerated code by: --- 709,715 ---- o Bill Reynolds , ! o Corin Anderson Western Digital accelerated code by: *************** *** 691,696 **** --- 719,736 ---- P9000 accelerated code by: + + + + + + + + + README for XFree86[tm] 3.3.2 + + + o Erik Nygren , o Harry Langenbacher *************** *** 719,736 **** o Jorge Delgado , - - - - - - - - - README for XFree86[tm] 3.3.1 - - - 16 color VGA server by: o Gertjan Akkerman --- 759,764 ---- *************** *** 746,752 **** o Ported to X11R5 by Rik Faith . ! o Rewritten by Marc La France WD90C24 support by: --- 774,780 ---- o Ported to X11R5 by Rik Faith . ! o Rewritten by Marc Aurele La France WD90C24 support by: *************** *** 756,761 **** --- 784,802 ---- o Alan Hourihane + + + + + + + + + + README for XFree86[tm] 3.3.2 + + + SiS SVGA driver by: o Alan Hourihane *************** *** 783,802 **** o Harm Hanemaayer , ! o Corin Anderson - - - - - - - - - README for XFree86[tm] 3.3.1 - - - Cirrus CL64xx driver by: o Manfred Brands --- 824,831 ---- o Harm Hanemaayer , ! o Corin Anderson Cirrus CL64xx driver by: o Manfred Brands *************** *** 821,826 **** --- 850,868 ---- ARK Logic SVGA driver by: + + + + + + + + + + README for XFree86[tm] 3.3.2 + + + o Harm Hanemaayer o Leon Bottou *************** *** 851,868 **** MX SVGA driver by: - - - - - - - - - README for XFree86[tm] 3.3.1 - - - o Frank Dikker Video7 SVGA driver by: --- 893,898 ---- *************** *** 887,892 **** --- 917,934 ---- o Angsar Hockmann + + + + + + + + + README for XFree86[tm] 3.3.2 + + + o Michael Will o Andrew Mileski *************** *** 917,934 **** o [Unknown authors] - - - - - - - - - README for XFree86[tm] 3.3.1 - - - o Dirk Hohndel o Koen Gadeyne --- 959,964 ---- *************** *** 953,958 **** --- 983,1000 ---- XFree86-DGA extension by: + + + + + + + + + README for XFree86[tm] 3.3.2 + + + o Jon Tombs o Mark Vojkovich *************** *** 982,1000 **** o Eric Raymond (new video mode documen- tation), - - - - - - - - - - README for XFree86[tm] 3.3.1 - - - o and an entire horde of beta-testers around the world! --- 1024,1029 ---- *************** *** 1019,1024 **** --- 1048,1066 ---- o Jon Tombs + + + + + + + + + + README for XFree86[tm] 3.3.2 + + + o David Wexelblat Mail sent to will reach the core team. Please note that *************** *** 1050,1066 **** release. The version of XFree86 in the initial X11R6 core is 3.0. The version of XFree86 in the current X11R6.3 release is 3.2. - - - - - - - - README for XFree86[tm] 3.3.1 - - - An additional benefit of this incorporation is that The XFree86 Project, Inc has obtained outside financial support for our work. This will hopefully give us the freedom to be more pro-active in obtaining new video hardware, and --- 1092,1097 ---- *************** *** 1084,1089 **** --- 1115,1132 ---- o David Wexelblat, Director + + + + + + + + + README for XFree86[tm] 3.3.2 + + + Email to reaches the board of directors. Our bylaws have been crafted in such a way to ensure that XFree86 is and always *************** *** 1115,1132 **** nation with the Core Team) of the servers they are actively working on available to external testers for specific testing. - - - - - - - - - README for XFree86[tm] 3.3.1 - - - o Commercial members. Commercial members are non-voting members of The XFree86 Project who donate US$5000/year to the Project. Addition- ally, companies who contribute significantly to the development --- 1158,1163 ---- *************** *** 1149,1159 **** o UUNET Communications Services, Inc. ! UUNET Communications Services, Inc, deserves special mention. This organiza- ! tion stepped forward and contributed the entire 1994 X Consortium membership ! fee on a moment's notice. This single act ensured XFree86's involvement in ! X11R6. o GUUG -- 1st German Linux Congress Also deserving of special mention are the organizers and attendees of the 1st --- 1180,1202 ---- o UUNET Communications Services, Inc. ! UUNET Communications Services, Inc, deserves special mention. This + + + + + + + + README for XFree86[tm] 3.3.2 + + + + organization stepped forward and contributed the entire 1994 X Consortium mem- + bership fee on a moment's notice. This single act ensured XFree86's involve- + ment in X11R6. + o GUUG -- 1st German Linux Congress Also deserving of special mention are the organizers and attendees of the 1st *************** *** 1181,1218 **** o Diamond Multimedia Systems, Inc. ! README for XFree86[tm] 3.3.1 - o Digital Equipment Corporation - o Elsa GmbH , Aachen, Germany - o Genoa Systems Corporation - o Helius, Inc. - o Hercules Computer Technology, Inc. - o Ralf Hockens - o Dirk Hohndel - o InfoMagic , Flagstaff, AZ - o Daniel Kraemer ! o Frank & Paige McCormick o Linux International o Linux Support Team, Erlangen, Germany --- 1224,1266 ---- o Diamond Multimedia Systems, Inc. + o Digital Equipment Corporation + o Elsa GmbH , Aachen, Germany + o Genoa Systems Corporation + o Helius, Inc. + o Hercules Computer Technology, Inc. + o Ralf Hockens + o Dirk Hohndel + o InfoMagic , Flagstaff, AZ ! o Daniel Kraemer + o Epoch Networks, Inc. , Irvine, CA + o Frank & Paige McCormick ! README for XFree86[tm] 3.3.2 + + + o Internet Labs, Inc. + o Linux International o Linux Support Team, Erlangen, Germany *************** *** 1247,1281 **** o Clifford M Stein ! README for XFree86[tm] 3.3.1 - o Joel Storm - o S.u.S.E. GmbH , Fuerth, Germany - o Tekelec Airtronic GmbH , Muenchen, Germany - o Jim Tsillas - o Trans-Ameritech Enterprises, Inc., Santa Clara, CA - o Unifix Software GmbH, Braunschweig, Germany ! o Vixie Enterprises , La Honda, CA - o Walnut Creek CDROM , Concord, CA - o Xtreme s.a.s. , Livorno, Italy The XFree86 Project, Inc, welcomes the additional contribution of funding and/or equipment. Such contributions should be tax-deductible; we will know --- 1295,1329 ---- o Clifford M Stein + o Joel Storm + o S.u.S.E. GmbH , Fuerth, Germany + o Tekelec Airtronic GmbH , Muenchen, Germany + o Jim Tsillas + o Trans-Ameritech Enterprises, Inc., Santa Clara, CA + o Unifix Software GmbH, Braunschweig, Germany + o Vixie Enterprises , La Honda, CA + o Walnut Creek CDROM , Concord, CA ! o Xtreme s.a.s. , Livorno, Italy ! README for XFree86[tm] 3.3.2 The XFree86 Project, Inc, welcomes the additional contribution of funding and/or equipment. Such contributions should be tax-deductible; we will know *************** *** 1286,1292 **** 9. Source and binary archive sites Source patches are available to upgrade X11R6.3 PL2 from the X Consortium (now ! The Open Group) to XFree86 3.3.1. Binaries for many OSs are also available. The distribution is available from: o ftp://ftp.XFree86.org/pub/XFree86 --- 1334,1340 ---- 9. Source and binary archive sites Source patches are available to upgrade X11R6.3 PL2 from the X Consortium (now ! The Open Group) to XFree86 3.3.2. Binaries for many OSs are also available. The distribution is available from: o ftp://ftp.XFree86.org/pub/XFree86 *************** *** 1312,1330 **** o Europe: - - - - - - - - - - README for XFree86[tm] 3.3.1 - - - o ftp://fvkma.tu-graz.ac.at/pub/XFree86 (source and binaries) o ftp://gd.tuwien.ac.at/hci/X11/XFree86 and --- 1360,1365 ---- *************** *** 1344,1349 **** --- 1379,1396 ---- o ftp://ftp.uni-stuttgart.de/pub/X11/Xfree86 (source and binaries) + + + + + + + + + README for XFree86[tm] 3.3.2 + + + o ftp://ftp.funet.fi/pub/X11/XFree86 (source and binaries) o ftp://ftp.ibp.fr/pub/X11/XFree86 (source and binaries) *************** *** 1368,1384 **** o ftp://ftp.kreonet.re.kr/pub/Linux/xfree86 (source and binaries) ! Ensure that you are getting XFree86 3.3.1 - some of these sites may archive older releases as well. Check the RELNOTES to find which files you need to take from the archive. ! Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/README.sgml,v 3.75.2.24 1997/07/26 11:49:28 dawes Exp $ ! $TOG: README /main/35 1997/08/10 13:00:55 kaleb $ --- 1415,1431 ---- o ftp://ftp.kreonet.re.kr/pub/Linux/xfree86 (source and binaries) ! Ensure that you are getting XFree86 3.3.2 - some of these sites may archive older releases as well. Check the RELNOTES to find which files you need to take from the archive. ! Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/README.sgml,v 3.75.2.33 1998/02/28 15:49:46 robin Exp $ ! $TOG: README /main/36 1998/03/06 16:38:14 kaleb $ *************** *** 1387,1393 **** - README for XFree86[tm] 3.3.1 --- 1434,1439 ---- *************** *** 1407,1412 **** --- 1453,1459 ---- + README for XFree86[tm] 3.3.2 *************** *** 1457,1467 **** CONTENTS ! 1. What's new in XFree86 3.3.1 .............................................. 1 2. Systems XFree86 has been tested on ....................................... 1 --- 1504,1533 ---- + + + + + + + + + + + + + + + + + + + CONTENTS ! 1. What's new in XFree86 3.3.2 .............................................. 1 2. Systems XFree86 has been tested on ....................................... 1 *************** *** 1469,1483 **** 4. Where to get more information ............................................ 5 ! 5. Thanks ................................................................... 5 6. Credits .................................................................. 6 7. Contact information ..................................................... 16 ! 8. The XFree86 Project, Inc. ............................................... 16 ! 9. Source and binary archive sites ......................................... 20 --- 1535,1549 ---- 4. Where to get more information ............................................ 5 ! 5. Thanks ................................................................... 6 6. Credits .................................................................. 6 7. Contact information ..................................................... 16 ! 8. The XFree86 Project, Inc. ............................................... 17 ! 9. Source and binary archive sites ......................................... 21 *************** *** 1517,1520 **** ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/README,v 3.76.2.21 1997/07/26 12:55:58 dawes Exp $ --- 1583,1586 ---- ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/README,v 3.76.2.28 1998/03/01 13:58:20 dawes Exp $ *** ./programs/Xserver/hw/xfree86/doc/README.DECtga@@/PUBLIC-LATEST Sat Jul 19 10:26:56 1997 --- xc/programs/Xserver/hw/xfree86/doc/README.DECtga Fri Mar 6 16:36:42 1998 *************** *** 11,17 **** The XFree86 Project, Inc. ! 20th May 1997 --- 11,17 ---- The XFree86 Project, Inc. ! 26th February 1998 *************** *** 45,51 **** If the server does not detect the base address of the 21030, then Check /proc/pci for the 21030 and look for the "Prefetch- able 32 bit memory at 0x???????" and enter this as your Mem- ! Base setting. o No acceleration features of the 21030 have been taken advantage of yet! --- 45,53 ---- If the server does not detect the base address of the 21030, then Check /proc/pci for the 21030 and look for the "Prefetch- able 32 bit memory at 0x???????" and enter this as your Mem- ! Base setting. In XFree86 v3.3.2, if you are using Linux > ! v2.0.27 with the PCI routines the server should detect the ! base address automatically. o No acceleration features of the 21030 have been taken advantage of yet! *************** *** 55,66 **** The code for the 21030 as yet - has only been tested on DEC's UDB box, better known as the Multia, in a Linux environment. ! Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/DECtga.sgml,v 3.6.2.1 1997/05/21 15:02:39 dawes Exp $ - - Information for DEC 21030 Users (aka TGA) --- 57,66 ---- The code for the 21030 as yet - has only been tested on DEC's UDB box, better known as the Multia, in a Linux environment. ! Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/DECtga.sgml,v 3.6.2.3 1998/02/26 20:11:25 hohndel Exp $ Information for DEC 21030 Users (aka TGA) *************** *** 197,200 **** ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/README.DECtga,v 3.8.2.1 1997/05/21 15:07:28 dawes Exp $ --- 197,200 ---- ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/README.DECtga,v 3.8.2.3 1998/02/27 02:54:58 dawes Exp $ *** ./programs/Xserver/hw/xfree86/doc/README.Linux@@/PUBLIC-LATEST Sat Jul 19 10:27:02 1997 --- xc/programs/Xserver/hw/xfree86/doc/README.Linux Fri Mar 6 16:36:46 1998 *************** *** 11,26 **** Orest Zborowski, Dirk Hohndel ! May 13, 1997 1. Linux versions on which XFree86 has been tested ! XFree86 has been tested with Linux version 2.0.30. It should work with any ver- ! sion since 1.0 without change. The binaries and libraries are based on the ! 5.4.7 Elf C libraries, and the 1.7.14 dynamic linker ld.so. You will at least ! need the 5.2.x Elf C libraries to successfully use the servers. 2. Backwards Compatibility --- 11,30 ---- Orest Zborowski, Dirk Hohndel ! February 26, 1997 1. Linux versions on which XFree86 has been tested ! XFree86 has been tested with Linux version 2.0.32 and several 2.1xx kernels. ! It is known not to compile with kernel sources newer then somewhere around ! 2.1.70, due to incompatibilities in the joystick driver. Except for the joy- ! stick driver, it works just fine with all 2.1.x kernels tested (including ! 2.1.88). It should work with any version since 1.0 without change. The binaries ! and libraries are based on the 5.3.12 Elf C libraries, and the 1.7.14 dynamic ! linker ld.so. You will at least need the 5.2.x Elf C libraries to successfully ! use the servers. 2. Backwards Compatibility *************** *** 54,64 **** the sources. - 4. Running XFree86 - XFree86 requires about 4mb of virtual memory to run, although having 8mb of RAM - is probably the minimum comfortable configuration. A 387 coprocessor is helpful - for 386 machines, although greater gains in interactive performance are Information for Linux Users --- 58,64 ---- *************** *** 71,76 **** --- 71,81 ---- + 4. Running XFree86 + + XFree86 requires about 4mb of virtual memory to run, although having 8mb of RAM + is probably the minimum comfortable configuration. A 387 coprocessor is helpful + for 386 machines, although greater gains in interactive performance are obtained with an increase in physical memory. Also, a faster graphics card, bus or RAM, will improve server performance. *************** *** 120,129 **** kernel-specific, multiple keysym, and dead keys are not handled by the server. All others are translated to their X equivalents. Note that the XFree86 server only allows for four modifier maps: unshifted, shifted, modeswitch unshifted - and modeswitch shifted. Depending on what the modeswitch key is (it is config- - urable in your XF86Config and defaults to Alt), XFree86 will read those tables - into its keymaps. This means if you use certain keys, like left-Control, for - Linux modeswitch, that will not be mappable to X. --- 125,130 ---- *************** *** 132,142 **** - Information for Linux Users 5. Installing Xdm, the display manager Since xdm is dynamically linked, there's no issue on export restriction outside --- 133,148 ---- Information for Linux Users + and modeswitch shifted. Depending on what the modeswitch key is (it is config- + urable in your XF86Config and defaults to Alt), XFree86 will read those tables + into its keymaps. This means if you use certain keys, like left-Control, for + Linux modeswitch, that will not be mappable to X. + + 5. Installing Xdm, the display manager Since xdm is dynamically linked, there's no issue on export restriction outside *************** *** 163,169 **** 6. xterm ! The XFree86-3.3 binary release contains an xterm binary that has been linked statically against libtermcap. This was done to make sure that it will cor- rectly work with all distributions, regardless whether they rely on libtermcap or libncurses. Contrary to the xterm binaries in some beta version following --- 169,175 ---- 6. xterm ! The XFree86-3.3.2 binary release contains an xterm binary that has been linked statically against libtermcap. This was done to make sure that it will cor- rectly work with all distributions, regardless whether they rely on libtermcap or libncurses. Contrary to the xterm binaries in some beta version following *************** *** 186,208 **** To use a specific device, add the line - load "module" - in the Module section of XF86Config, where module is the name of the .so file - corresponding to your device. You also need to set up a XInput section in ! Information for Linux Users ! XF86Config. Refer to the XF86Config(5) man page for detailed configuration instructions. --- 192,213 ---- To use a specific device, add the line + Information for Linux Users ! load "module" ! in the Module section of XF86Config, where module is the name of the .so file ! corresponding to your device. You also need to set up a XInput section in XF86Config. Refer to the XF86Config(5) man page for detailed configuration instructions. *************** *** 229,235 **** 8. Compiling XFree86 There are no special instructions required for compiling XFree86. This version ! was compiled with gcc-2.7.2.1, the 5.4.7 Elf libraries and the 1.7.14 shared, dynamic linker ld.so. The server has been compiled with -m486, which optimizes it for the 486 processor, but the binary will run on the 386 processor (there is a slight increase in binary size over using -m386, but no loss of perfor- --- 234,240 ---- 8. Compiling XFree86 There are no special instructions required for compiling XFree86. This version ! was compiled with gcc-2.7.2.1, the 5.3.12 Elf libraries and the 1.7.14 shared, dynamic linker ld.so. The server has been compiled with -m486, which optimizes it for the 486 processor, but the binary will run on the 386 processor (there is a slight increase in binary size over using -m386, but no loss of perfor- *************** *** 242,255 **** compiled into the server. Alternately, the link kit can be used to craft modi- fied servers. - The distribution is very large, but it is possible to compile XFree86 on a sin- - gle 64mb partition, if the source tree is carefully trimmed (no manpages, PEX - or large clients). Simply run ``make Makefiles'' to create the Makefiles, then - stop the make and run each piece individually. It is not necessary to run - ``make depend'' as well, which saves some space. Having 150mb available makes - compiling XFree86 a lot easier. You will need about 10mb of virtual memory to - compile the entire server. - If an aout version of XFree86 is to be built and patches are applied which sig- nificantly change the libraries, modified jump_xxx files will be needed. Those can be generated according to instructions given in the DLL tools package, and --- 247,252 ---- *************** *** 256,262 **** will be made available as XFree86 patches. The JUMP_xxx defines used to compile the X libraries can also be used to com- ! pile external X shared libraries, like Xaw3d. Detailed instructions are --- 253,261 ---- will be made available as XFree86 patches. The JUMP_xxx defines used to compile the X libraries can also be used to com- ! pile external X shared libraries, like Xaw3d. Detailed instructions are pro- ! vided in /usr/X11R6/lib/X11/config/lnxLib.rules, where the X library defini- ! tions are provided, as an example. *************** *** 265,290 **** Information for Linux Users - provided in /usr/X11R6/lib/X11/config/lnxLib.rules, where the X library defini- - tions are provided, as an example. - - 9. Bug Notification Bug reports should be sent to XFree86@XFree86.org or posted to the comp.win- dows.x.i386unix newsgroup. ! Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/Linux.sgml,v 3.13.2.3 1997/05/23 12:19:40 dawes Exp $ ! $TOG: README.Linux /main/13 1997/07/19 10:27:04 kaleb $ --- 264,286 ---- + Information for Linux Users 9. Bug Notification Bug reports should be sent to XFree86@XFree86.org or posted to the comp.win- dows.x.i386unix newsgroup. ! Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/Linux.sgml,v 3.13.2.4 1998/02/26 20:11:26 hohndel Exp $ ! $TOG: README.Linux /main/14 1998/03/06 16:38:23 kaleb $ *************** *** 331,336 **** --- 327,336 ---- + + + + Information for Linux Users *************** *** 411,417 **** 3. Installing XFree86 ...................................................... 1 ! 4. Running XFree86 ......................................................... 1 5. Installing Xdm, the display manager ...................................... 3 --- 411,417 ---- 3. Installing XFree86 ...................................................... 1 ! 4. Running XFree86 ......................................................... 2 5. Installing Xdm, the display manager ...................................... 3 *************** *** 461,464 **** ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/README.Linux,v 3.21.2.3 1997/05/23 12:24:15 dawes Exp $ --- 461,464 ---- ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/README.Linux,v 3.21.2.4 1998/02/27 02:54:58 dawes Exp $ *** ./programs/Xserver/hw/xfree86/doc/README.LynxOS@@/PUBLIC-LATEST Sat Jul 19 10:27:09 1997 --- xc/programs/Xserver/hw/xfree86/doc/README.LynxOS Fri Mar 6 16:36:50 1998 *************** *** 7,17 **** ! README for XFree86 3.3 on LynxOS Thomas Mueller ! Last modified on: 26 May 1997 --- 7,17 ---- ! README for XFree86 3.3.2 on LynxOS Thomas Mueller ! Last modified on: 24 February 1998 *************** *** 30,36 **** ftp://ftp.XFree86.org/pub/XFree86/current ! Binaries of the 3.3 release for LynxOS AT are available from: ftp://ftp.XFree86.org/pub/XFree86/current/binaries/LynxOS --- 30,36 ---- ftp://ftp.XFree86.org/pub/XFree86/current ! Binaries of the 3.3.2 release for LynxOS AT are available from: ftp://ftp.XFree86.org/pub/XFree86/current/binaries/LynxOS *************** *** 37,54 **** The binaries are built on `LynxOS 2.5.0 012797-G i386'. These binaries don't run on earlier LynxOS versions because of the changes made to the networking code in LynxOS 2.5.0. This XFree86 version has never been tested on LynxOS ver- ! sions earlier than 2.3.0. XFree86 supports LynxOS on the AT, on the microSPARC and on the PowerPC plat- form. X servers are currently available on the AT and microSPARC platform. ! Refer to section Building on microSPARC and PowerPC (section 7., page 13) for details on XFree86 on the non-AT platforms. If you need binaries for other platforms than the one on the XFree86 FTP server ! contact me (tm@systrix.de). ! Send email to tm@systrix.de (Thomas Mueller) or XFree86@XFree86.org if you have ! comments or suggestions about this file and we'll revise it. 2. Installing the Binaries --- 37,54 ---- The binaries are built on `LynxOS 2.5.0 012797-G i386'. These binaries don't run on earlier LynxOS versions because of the changes made to the networking code in LynxOS 2.5.0. This XFree86 version has never been tested on LynxOS ver- ! sions earlier than 2.4.0. XFree86 supports LynxOS on the AT, on the microSPARC and on the PowerPC plat- form. X servers are currently available on the AT and microSPARC platform. ! Refer to section Building on microSPARC and PowerPC (section 7., page 15) for details on XFree86 on the non-AT platforms. If you need binaries for other platforms than the one on the XFree86 FTP server ! contact me (tmueller@sysgo.de). ! Send email to tmueller@sysgo.de (Thomas Mueller) or XFree86@XFree86.org if you ! have comments or suggestions about this file and we'll revise it. 2. Installing the Binaries *************** *** 57,73 **** executables, servers, fonts, libraries, include files, man pages, config files, and the server link kit. The full distribution takes over 95MB of disk space. ! At minimum you need to unpack the 'required' X33*.tgz archives plus at least one server that matches your vga card. If you will be using the new XF86Setup ! README for XFree86 3.3 on LynxOS ! README for XFree86 3.3 on LynxOS --- 57,73 ---- executables, servers, fonts, libraries, include files, man pages, config files, and the server link kit. The full distribution takes over 95MB of disk space. ! At minimum you need to unpack the 'required' X332*.tgz archives plus at least one server that matches your vga card. If you will be using the new XF86Setup ! README for XFree86 3.3.2 on LynxOS ! README for XFree86 3.3.2 on LynxOS *************** *** 76,130 **** REQUIRED: ! X33bin Clients, run-time libs, and app-defaults files ! X33doc Documentation ! X33fnts 75dpi and misc fonts ! X33lib Data files required at run-time ! X33cfg ! sample config files for xinit, xdm ! ! X33set XF86Setup utility ! X33VG16 16 colour VGA server (XF86Setup needs this server) ! Choose at least one of the following server to match your hardware: ! X338514 ! 8514/A server ! X33AGX ! AGX server ! X33I128 ! I128 server ! X33Ma64 ! Mach 64 server ! X33Ma32 ! Mach 32 server ! X33Ma8 ! Mach 8 server - X33Mono - Monochrome server - X33P9K - P9000 server - X33S3 - S3 server --- 76,132 ---- REQUIRED: ! preinst.sh ! Pre-installation script ! ! postinst.sh ! Post-installation script ! ! extract ! XFree86 extraction utility ! ! X332bin Clients, run-time libs, and app-defaults files ! X332doc Documentation ! X332cfg ! sample config files for xinit, xdm ! ! X332fnts 75dpi and misc fonts ! X332lib Data files required at run-time ! X332set XF86Setup utility ! X332VG16 16 colour VGA server (XF86Setup needs this server) ! The following are required for an upgrade from XFree86 3.3.1: ! UPDATE from 3.3.1: ! preinst.sh ! Pre-installation script ! postinst.sh ! Post-installation script ! extract ! XFree86 extraction utility ! X332upd.tgz ! Changes since 3.3.1 (except the servers) ! X332doc.tgz ! Documentation *************** *** 131,196 **** - README for XFree86 3.3 on LynxOS ! X33S3V ! S3 ViRGE server ! X33SVGA ! SVGA server ! X33VG16 ! 16 colour VGA server ! X33W32 ! ET4000W32, ET6000 server ! OPTIONAL: ! X33f100 ! 100dpi fonts ! X33fcyr ! Cyrillic fonts ! X33fnon ! Other fonts (Chinese, Japanese, Korean, Hebrew) ! X33fscl ! Scalable fonts (Speedo and Type1) ! X33fsrv ! Font server and config files ! X33prog ! X header files, config files and compile-time libs ! X33man ! Manual pages ! X33nest ! Nested X server ! X33prt ! X Print server ! X33vfb ! Virtual frame buffer X server - X33lkit - The server LinkKit - X33ps - PostScript version of the documentation - X33html - HTML version of the documentation - If this is your first time, then you can safely install all of the packages. --- 133,198 ---- + README for XFree86 3.3.2 on LynxOS + X332set.tgz + XF86Setup utility + X332VG16.tgz + 16 colour VGA server (XF86Setup needs this + server) ! Choose at least one of the following server to match ! your hardware: ! X3328514 ! 8514/A server ! X332AGX ! AGX server ! X332I128 ! I128 server ! X332Ma64 ! Mach 64 server ! X332Ma32 ! Mach 32 server ! X332Ma8 ! Mach 8 server ! X332Mono ! Monochrome server ! X332P9K ! P9000 server ! X332S3 ! S3 server ! X332S3V ! old S3 ViRGE server (please use SVGA ! server) ! X332SVGA ! SVGA server ! X332VG16 ! 16 colour VGA server (XF86Setup needs this ! server) ! X332W32 ! ET4000W32, ET6000 server ! OPTIONAL: *************** *** 197,222 **** - README for XFree86 3.3 on LynxOS ! As a minimal install, you'll need doc, bin, fonts lib, config, and one X ! server. ! If you plan to install XF86Setup you'll have to install X33prog as well since ! XF86Setup checks for the existence of a certain file name pattern which is sat- ! isfied only if you install the library files from X33prog. This restriction ! will be fixed in future XFree86 releases for LynxOS. ! It may be necessary to increase the process stack limit in order to run XFree86 ! on your system. Edit /etc/startab and reboot your system to make the changes ! active before you begin the installation. ! Also, be sure to include /usr/X11R6/bin in your PATH environment variable. 2.1 Full Install 1. You must be logged in as root to unpack the archives because several exe- --- 199,289 ---- + README for XFree86 3.3.2 on LynxOS + X332f100 + 100dpi fonts + X332fcyr + Cyrillic fonts ! X332fnon ! Other fonts (Chinese, Japanese, Korean, ! Hebrew) ! X332fscl ! Scalable fonts (Speedo and Type1) ! X332fsrv ! Font server and config files ! X332prog ! X header files, config files and compile- ! time libs + X332man + Manual pages + + X332nest + Nested X server + + X332prt + X Print server + + X332vfb + Virtual frame buffer X server + + X332lkit + The X server LinkKit + + X332ps + PostScript version of the documentation + + X332html + HTML version of the documentation + + X332jdoc + Documentation in Japanese + + X332jhtm + HTML version of the documentation in + Japanese + + If this is your first time, then you can safely install all of the + packages. As a minimal install, you'll need doc, bin, fonts lib, + config, and one X server. If you already have a version of XFree86 + installed, MAKE A BACKUP OF /usr/X11R6 BEFORE DOING ANYTHING ELSE. + The standard installation procedure will overwrite your existing + version of XFree86. Also, be sure to read the Release Notes + + + + + + + + + README for XFree86 3.3.2 on LynxOS + + + + Release Notes before installing. + + If you plan to install XF86Setup you'll have to install X332prog as + well since XF86Setup checks for the existence of a certain file + name pattern which is satisfied only if you install the library + files from X332prog. This restriction will be fixed in future + XFree86 releases for LynxOS. + + It may be necessary to increase the process stack limit in order to + run XFree86 on your system. Edit /etc/startab and reboot your sys- + tem to make the changes active before you begin the installation. + + Also, be sure to include /usr/X11R6/bin in your PATH environment + variable. + 2.1 Full Install 1. You must be logged in as root to unpack the archives because several exe- *************** *** 223,228 **** --- 290,300 ---- cutables are set-user-id. Otherwise the server may abort if you unpack it as an ordinary user. + For the purposes of these installation instructions, it is assumed that + you have downloaded all the files to the /usr/tmp directory. If you've + put them in another directory, that's fine -- just replace all occur- + rences of ``/usr/tmp'' with the name of that directory. + 2. If you have about 80Mb free in the /usr partition create a directory /usr/X11R6 and skip to no. 3. Otherwise, create a directory on another partition and sym link it into /usr: *************** *** 236,274 **** 3. Unpack everything: ! If you are using bash: - # cd /usr/X11R6 - # for i in X33*.tgz; do - # gnutar -xzpPf $i - # done - Else, if you are using csh: - % cd /usr/X11R6 - % foreach i (X33*.tgz) - % gnutar -xzpPf $i - % end - 4. Create a symbolic link ``X'' that points to the server that matches your - video card. The XF86_* man pages list which vga chip sets are supported - README for XFree86 3.3 on LynxOS by each server. For example, if you have an ET4000 based card you will use the XF86_SVGA server: --- 308,368 ---- 3. Unpack everything: ! Make the installation utility executable. To do this, make sure the ! `extract' file is in the same directory as all the X332*.tgz files, and ! run the following from that directory: + chmod 755 /usr/tmp/extract + The installation utility ``extract'' is used to unpack the .tgz files + that make up the XFree86 distribution. The .tgz files are gzipped tar + files. However, ``tar'' in its standard form on most OSs is not well- + suited to the task of installing XFree86. The extract utility is a modi- + fied version of GNU tar 1.12 built with the options required to make it + suitable for installing XFree86. The source for extract is available + from the same place you got the XFree86 distribution. + README for XFree86 3.3.2 on LynxOS + It is strongly recommended that you use the provided extract utility to + unpack the XFree86 distribution. If you choose to ignore this and use + something else, we don't want to hear from you if you run into problems. + It is also important that you do not rename the extract utility. If + renamed, it behaves just like the normal GNU tar. + To extract the XFree86 binaries, run the following as root: If you are + using bash: + # cd /usr/X11R6 + # for i in /usr/tmp/X332*.tgz; do + # extract $i + # done + + Else, if you are using csh: + + % cd /usr/X11R6 + % foreach i (/usr/tmp/X332*.tgz) + % /usr/tmp/extract $i + % end + + + + 4. Create a symbolic link ``X'' that points to the server that matches your + video card. The XF86_* man pages list which vga chip sets are supported by each server. For example, if you have an ET4000 based card you will use the XF86_SVGA server: *************** *** 280,287 **** First do numbers 1 and 2 above. Then unpack the required archives: # cd /usr/X11R6 ! # for i in bin fnts lib xicf; do ! # gnutar -xzpPf X33$i.tgz # done Then unpack a server archive corresponding to your vga card. The server man --- 374,381 ---- First do numbers 1 and 2 above. Then unpack the required archives: # cd /usr/X11R6 ! # for i in bin fnts lib cfg prog; do ! # /usr/tmp/extract /usr/tmp/X332$i.tgz # done Then unpack a server archive corresponding to your vga card. The server man *************** *** 289,300 **** For example, if you have an ET4000 based card you will use the XF86_SVGA server: ! # gnutar -xzpPf X33SVGA.tgz # cd /usr/X11R6/bin; rm -f X; ln -s XF86_SVGA X 2.3 After either Full or Minimal Install above Be sure to include /usr/X11R6/bin in your PATH environment variable. If you plan to use clients of the MetroLink X package with the XFree86 X server make sure to remove /usr/bin/X11/X file or put /usr/bin/X11 after /usr/X11R6/bin in your PATH environment variable. --- 383,406 ---- For example, if you have an ET4000 based card you will use the XF86_SVGA server: ! # /usr/tmp/extract /usr/tmp/X332SVGA.tgz # cd /usr/X11R6/bin; rm -f X; ln -s XF86_SVGA X 2.3 After either Full or Minimal Install above Be sure to include /usr/X11R6/bin in your PATH environment variable. If you + + + + + + + + + README for XFree86 3.3.2 on LynxOS + + + plan to use clients of the MetroLink X package with the XFree86 X server make sure to remove /usr/bin/X11/X file or put /usr/bin/X11 after /usr/X11R6/bin in your PATH environment variable. *************** *** 312,318 **** correct settings for OSMajorVersion, OSMinorVersion and OSTeenyVersion for your operating system version. ! Refer to section Running XFree86 (section 4., page 9) for further information on necessary configuration steps before running XFree86 on LynxOS. --- 418,424 ---- correct settings for OSMajorVersion, OSMinorVersion and OSTeenyVersion for your operating system version. ! Refer to section Running XFree86 (section 4., page 10) for further information on necessary configuration steps before running XFree86 on LynxOS. *************** *** 323,340 **** Currently there is no support for shared libraries in the LynxOS XFree86 port. A complete binary installation along with manual pages will require approxi- mately 90-100 MBytes of disk space. To compile the system you will need at - - - - - - - - - README for XFree86 3.3 on LynxOS - - - least 230 MBytes of free disk space. 3.2 Changes to system environment (LynxOS AT) --- 429,434 ---- *************** *** 362,367 **** --- 456,472 ---- to find out the correct path. Set the file mode of /lib/cpp with + + + + + + + + README for XFree86 3.3.2 on LynxOS + + + # chown root /lib/cpp # chmod 755 /lib/cpp *************** *** 382,406 **** ! LynxOS AT 2.3 and 2.4 o Use the CYGNUS GNU-C Compiler to build XFree86. With LynxOS ! 2.3.0 and 2.4.0 you must execute the shell script /CYGNUS.bash ! to apply the necessary changes to your environment. - - - - - - - - - - README for XFree86 3.3 on LynxOS - - - o Create a shell script named /lib/cpp as follows: #!/bin/sh --- 487,498 ---- ! LynxOS AT 2.4 o Use the CYGNUS GNU-C Compiler to build XFree86. With LynxOS ! 2.4.0 you must execute the shell script /CYGNUS.bash to apply ! the necessary changes to your environment. o Create a shell script named /lib/cpp as follows: #!/bin/sh *************** *** 423,430 **** --- 515,538 ---- # chmod 755 /lib/cpp + LynxOS AT 2.3 + This has actually not been tested, but the steps for described for + 2.4 should apply to 2.3 as well. + LynxOS AT 2.2.1 This has actually never been tested, be prepared that the build + + + + + + + + + README for XFree86 3.3.2 on LynxOS + + + will fail somewhere! o Create a shell script named /lib/cpp as follows: *************** *** 452,472 **** /usr/include/uio.h surrounded by - - - - - - - - - - - - README for XFree86 3.3 on LynxOS - - - #ifndef _UIO_H #define _UIO_H ... --- 560,565 ---- *************** *** 490,496 **** --- 583,604 ---- 3.3 make World + Read Building XFree86 before trying to rebuild XFree86 from the source distri- + bution. + Before you start compilation you must edit xc/config/cf/lynx.cf to match your + + + + + + + + + README for XFree86 3.3.2 on LynxOS + + + operating system version (defaults set up for 2.5.0). Change the definitions of OSMajorVersion, OSMinorVersion and OSTeenyVersion accordingly. *************** *** 516,562 **** due to a problem with the strip program which shows up when installing across file system boundaries. ! Refer to section Installing XFree86 manual pages (section 5., page 11) for man- ual page installation. On LynxOS AT 2.5.0 you may encounter problems with make in deeply nested subdi- rectories (eg core dumps, hangups). In this case update to GNU make version ! README for XFree86 3.3 on LynxOS ! 3.75 or higher. - 4. Running XFree86 - 4.1 System requirements - A minimum of 8MB of memory is required to run X. If you want to run real-world - applications you should think of upgrading to 16MB. If you plan to develop - software under X take 32MB into consideration. - 4.2 System tuning - 4.2.1 Tunable parameters - To reasonably run XFree86 you may have to adjust a few system parameters. - On LynxOS 2.5.0 include a line ! #define X_WINDOWS - in /sys/lynx.os/uparam.h. - For earlier versions you'll have to edit /usr/include/param.h: Tunable Old New USR_NFDS number of open files per process 20 64 --- 624,669 ---- due to a problem with the strip program which shows up when installing across file system boundaries. ! Refer to section Installing XFree86 manual pages (section 5., page 12) for man- ual page installation. On LynxOS AT 2.5.0 you may encounter problems with make in deeply nested subdi- rectories (eg core dumps, hangups). In this case update to GNU make version + 3.75 or higher. + 4. Running XFree86 + 4.1 System requirements + A minimum of 16MB of memory is required to run X. If you want to run real-world + applications you should think of upgrading to 32MB (or more). + 4.2 System tuning + 4.2.1 Tunable parameters + To reasonably run XFree86 you may have to adjust a few system parameters. ! On LynxOS 2.5.0 include a line + #define X_WINDOWS + in /sys/lynx.os/uparam.h. ! For earlier versions you'll have to edit /usr/include/param.h: ! README for XFree86 3.3.2 on LynxOS Tunable Old New USR_NFDS number of open files per process 20 64 *************** *** 585,606 **** # reboot -N - - - - - - - - README for XFree86 3.3 on LynxOS - - - - 4.3 Bus mouse drivers - Starting with LynxOS AT 2.4.0 LynxOS includes a PS/2 mouse driver. Currently this driver is not fully supported by XFree86 (you'll probably have to specify a mouse type which doesn't match the real mouse type and in some cases lose --- 692,706 ---- # reboot -N + 4.3 Mouse support in 3.3.2 + XFree86 3.3.2 includes support for PnP mice (see also Mouse Support in + XFree86). The current LynxOS TTY device driver doesn't allow the necessary + manipulation of the RTS line and therefore the support for PnP mice has been + disabled for LynxOS. + 4.4 Bus mouse drivers Starting with LynxOS AT 2.4.0 LynxOS includes a PS/2 mouse driver. Currently this driver is not fully supported by XFree86 (you'll probably have to specify a mouse type which doesn't match the real mouse type and in some cases lose *************** *** 617,624 **** The XFree86 PS/2 mouse driver works also with MetroLink X 2.3.3.1 as shipped with LynxOS AT 2.4.0 unless you have the LynxOS patch 000055-00 installed. - 4.4 ATC console driver and VT switching The XFree86 servers will only run with the default LynxOS console driver, sorry for those of you who use the alternative vdt console driver. Currently there is no support for virtual terminal switching once the server has started. --- 717,738 ---- The XFree86 PS/2 mouse driver works also with MetroLink X 2.3.3.1 as shipped with LynxOS AT 2.4.0 unless you have the LynxOS patch 000055-00 installed. + + + + + + + + + + README for XFree86 3.3.2 on LynxOS + + + + 4.5 ATC console driver and VT switching + The XFree86 servers will only run with the default LynxOS console driver, sorry for those of you who use the alternative vdt console driver. Currently there is no support for virtual terminal switching once the server has started. *************** *** 639,645 **** ^ ! 4.5 X Server debug diagnostics output and other VT peculiarities The XFree86 X servers will produce a lot of diagnostics output on stderr during startup. This output will be lost after the server reached a certain point in --- 753,759 ---- ^ ! 4.6 X Server debug diagnostics output and other VT peculiarities The XFree86 X servers will produce a lot of diagnostics output on stderr during startup. This output will be lost after the server reached a certain point in *************** *** 651,687 **** what one would expect (i.e. random). - README for XFree86 3.3 on LynxOS - 5. Installing XFree86 manual pages - LynxOS uses cat-able manual pages, and because a doc preparation system is def- - initely not a vital component of a real-time operating system you must first - install groff-1.09 (or newer). Starting with LynxOS 2.3.0 it should compile - right out of the box (or better tar archive). - XFree86 manual pages may be installed using - make install.man - The index and whatis database for the XFree86 manual pages will be created - automatically. If you already have a whatis database or index file in the des- - tination directories you should perform a sort/uniq operation to remove dupli- - cate entries: for i in 1 3 5 do rm -f /tmp/tmpfile --- 765,802 ---- what one would expect (i.e. random). + 5. Installing XFree86 manual pages + LynxOS uses cat-able manual pages, and because a doc preparation system is def- + initely not a vital component of a real-time operating system you must first + install groff-1.09 (or newer). Starting with LynxOS 2.3.0 it should compile + right out of the box (or better tar archive). + XFree86 manual pages may be installed using + make install.man + The index and whatis database for the XFree86 manual pages will be created + automatically. If you already have a whatis database or index file in the des- + tination directories you should perform a sort/uniq operation to remove dupli- + cate entries: + README for XFree86 3.3.2 on LynxOS + for i in 1 3 5 do rm -f /tmp/tmpfile *************** *** 718,736 **** XFree86 libraries. Follow the steps outlined below after you have installed XFree86 and LynxOS Motif on your system. - - - - - - - - - - README for XFree86 3.3 on LynxOS - - - 6.1 Copy Motif files You must create symbolic links for the Motif libraries and utilities in the --- 833,838 ---- *************** *** 749,754 **** --- 851,868 ---- The Motif imake-configuration files are part of the LynxOS X Window package. They must be copied to the /usr/X11R6 directory tree. + + + + + + + + + README for XFree86 3.3.2 on LynxOS + + + cp /usr/lib/X11/config/Motif.* /usr/X11R6/lib/X11/config *************** *** 784,821 **** #define HasMotif YES ! README for XFree86 3.3 on LynxOS - 6.4 Motif config file patch - The file Motif.tmpl shipped with LynxOS Motif must be modified to work with - XFree86. In every reference to UnsharedLibReferences the first argument must be - changed from - UnsharedLibReferences(LIB, Arg2, Arg3) - to - UnsharedLibReferences(, Arg2, Arg3) - Be sure to apply the change to the file copied to /usr/X11R6/lib/X11/config. - 7. Building on microSPARC and PowerPC XFree86 3.3 compiles on LynxOS microSPARC and on LynxOS PPC as well. On the --- 898,934 ---- #define HasMotif YES + 6.4 Motif config file patch + The file Motif.tmpl shipped with LynxOS Motif must be modified to work with + XFree86. In every reference to UnsharedLibReferences the first argument must be + changed from + UnsharedLibReferences(LIB, Arg2, Arg3) + to + UnsharedLibReferences(, Arg2, Arg3) ! Be sure to apply the change to the file copied to /usr/X11R6/lib/X11/config. + README for XFree86 3.3.2 on LynxOS 7. Building on microSPARC and PowerPC XFree86 3.3 compiles on LynxOS microSPARC and on LynxOS PPC as well. On the *************** *** 852,894 **** to - README for XFree86 3.3 on LynxOS - #define SparcConsoleDefines /* -DPATCHED_CONSOLE */ - 7.2 Known Bug of the microSPARC server - On the first start of the X server on the microSPARC you will notice that the - pointer follows mouse movements with a certain delay (especially if you're mov- - ing the mouse real fast). You will also notice that moving windows with certain - window managers (eg mwm) is not working correctly. These effects should go - away on the next server start. - The server for monochrome cards builds properly if you enable it in lynx.cf but - it has never been tested (reports are welcome). - Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/LynxOS.sgml,v 3.14.2.2 1997/05/26 14:36:18 dawes Exp $ ! $TOG: README.LynxOS /main/11 1997/07/19 10:27:11 kaleb $ --- 965,1007 ---- to + #define SparcConsoleDefines /* -DPATCHED_CONSOLE */ + 7.2 Known Bug of the microSPARC server + On the first start of the X server on the microSPARC you will notice that the + pointer follows mouse movements with a certain delay (especially if you're mov- + ing the mouse real fast). You will also notice that moving windows with certain + window managers (eg mwm) is not working correctly. These effects should go + away on the next server start. + The server for monochrome cards builds properly if you enable it in lynx.cf but + it has never been tested (reports are welcome). + README for XFree86 3.3.2 on LynxOS ! Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/LynxOS.sgml,v 3.14.2.5 1998/02/26 13:59:06 dawes Exp $ + $TOG: README.LynxOS /main/12 1998/03/06 16:38:28 kaleb $ *************** *** 925,931 **** - README for XFree86 3.3 on LynxOS --- 1038,1043 ---- *************** *** 945,950 **** --- 1057,1063 ---- + README for XFree86 3.3.2 on LynxOS *************** *** 995,1000 **** --- 1108,1132 ---- + + + + + + + + + + + + + + + + + + + CONTENTS *************** *** 1002,1034 **** 1. What and Where is XFree86? ............................................... 1 2. Installing the Binaries .................................................. 1 ! 2.1 Full Install ......................................................... 4 ! 2.2 Minimal Install ...................................................... 5 ! 2.3 After either Full or Minimal Install above ........................... 5 ! 3. Compiling the XFree86 Distribution ....................................... 5 ! 3.1 Disk space requirements .............................................. 5 ! 3.2 Changes to system environment (LynxOS AT) ............................ 6 ! 3.3 make World ........................................................... 8 ! 4. Running XFree86 .......................................................... 9 ! 4.1 System requirements .................................................. 9 ! 4.2 System tuning ........................................................ 9 ! 4.3 Bus mouse drivers ................................................... 10 ! 4.4 ATC console driver and VT switching ................................. 10 ! 4.5 X Server debug diagnostics output and other VT peculiarities ........ 10 ! 5. Installing XFree86 manual pages ......................................... 11 ! 6. Using XFree86 with Motif ................................................ 11 ! 6.1 Copy Motif files .................................................... 12 ! 6.2 Motif library patch for LynxOS AT 2.3.0 ............................. 12 ! 6.3 X11R6 config file patch ............................................. 12 ! 6.4 Motif config file patch ............................................. 13 ! 7. Building on microSPARC and PowerPC ...................................... 13 ! 7.1 Console driver patch for microSPARC ................................. 13 ! 7.2 Known Bug of the microSPARC server .................................. 14 --- 1134,1167 ---- 1. What and Where is XFree86? ............................................... 1 2. Installing the Binaries .................................................. 1 ! 2.1 Full Install ......................................................... 5 ! 2.2 Minimal Install ...................................................... 6 ! 2.3 After either Full or Minimal Install above ........................... 6 ! 3. Compiling the XFree86 Distribution ....................................... 7 ! 3.1 Disk space requirements .............................................. 7 ! 3.2 Changes to system environment (LynxOS AT) ............................ 7 ! 3.3 make World ........................................................... 9 ! 4. Running XFree86 ......................................................... 10 ! 4.1 System requirements ................................................. 10 ! 4.2 System tuning ....................................................... 10 ! 4.3 Mouse support in 3.3.2 .............................................. 11 ! 4.4 Bus mouse drivers ................................................... 11 ! 4.5 ATC console driver and VT switching ................................. 12 ! 4.6 X Server debug diagnostics output and other VT peculiarities ........ 12 ! 5. Installing XFree86 manual pages ......................................... 12 ! 6. Using XFree86 with Motif ................................................ 13 ! 6.1 Copy Motif files .................................................... 13 ! 6.2 Motif library patch for LynxOS AT 2.3.0 ............................. 14 ! 6.3 X11R6 config file patch ............................................. 14 ! 6.4 Motif config file patch ............................................. 14 ! 7. Building on microSPARC and PowerPC ...................................... 15 ! 7.1 Console driver patch for microSPARC ................................. 15 ! 7.2 Known Bug of the microSPARC server .................................. 15 *************** *** 1050,1058 **** - i ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/README.LynxOS,v 3.18.2.2 1997/05/26 14:53:32 dawes Exp $ --- 1183,1190 ---- i ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/README.LynxOS,v 3.18.2.5 1998/02/27 02:54:58 dawes Exp $ *** ./programs/Xserver/hw/xfree86/doc/README.MGA@@/PUBLIC-LATEST Sun Aug 10 13:02:26 1997 --- xc/programs/Xserver/hw/xfree86/doc/README.MGA Fri Mar 6 16:36:55 1998 *************** *** 11,66 **** The XFree86 Project Inc. ! 2 August 1997 1. Supported hardware ! The current MGA driver in the SVGA server supports the Matrox Millennium ! (MGA2064W) with Ti3026 RAMDAC. It has been tested with 175, 220MHz, and 250MHz ! cards with 2MB, 4MB and 8MB WRAM. It supports the Matrox Mystique with 170 and ! 220 MHz RAMDACs. ! There is experimental support for the Matrox Millennium II, which for the most ! part works, but DO NOT USE THIS ON PRODUCTION SYSTEMS - it is no where near ! tested enough for that role. We do not yet have the card's documentation, so ! this is a alpha quality addition - test this support at your own risk. ! This version of the server does not support the rev 3 Matrox Millennium I. ! NOTE: This driver is pretty new, and not everything works like you expect it ! to. It shouldn't crash your machine, but you may have video artifacts or miss- ! ing lines. Please report any and all problems to XFree86@Xfree86.org using the ! appropriate bug report sheet. 2. Features: ! o Basic support for the Matrox Millennium video adapter ! o uses linear frame buffer ! o it should be possible to reach resolutions up to 1920x1024 ! o it should be possible to use pixel depths of 8, 16, 24, and 32 bits ! per pixel (256 pseudo colour, "high colour", "packed true colour", ! "true colour"). ! o supports VESA Display Power Management Signaling (DPMS) ! o supports RGB Sync-on-Green ! o supports DGA - o has the following accelerations: ! o lines Information for Matrox Millennium/Mystique Users --- 11,66 ---- The XFree86 Project Inc. ! 21 February 1998 1. Supported hardware ! The current MGA driver in the SVGA server supports ! o Matrox Millennium (MGA2064W) with Ti3026 RAMDAC. It has been tested with ! 175, 220MHz, and 250MHz cards with 2MB, 4MB and 8MB WRAM. ! o Millennium II both PCI and AGP. It has been tested with up to 16MB RAM. ! o Matrox Mystique with 170 and 220 MHz RAMDACs. Both 1064SG and 1164SG ! should work. 2. Features: ! o uses linear frame buffer + o it should be possible to reach resolutions up to 1920x1024 ! o it should be possible to use pixel depths of 8, 16, 24, and 32 bits per ! pixel (256 pseudo colour, "high colour", "packed true colour", "true ! colour"). ! o supports VESA Display Power Management Signaling (DPMS) ! o supports RGB Sync-on-Green ! o supports DGA ! o full accelerations: ! This server is very well accelerated, and is one of the fastest XFree86 3.3.2 ! Xservers. Future work will concentrate on fixing remaining bugs. ! 3. Technical Note: + This driver only supports: + o the MGA Storm (MGA2064W) chipset with the TI (TVP) 3026 RAMDAC. Matrox + have only so far made 175, 220 and 250 MHz boards with these two compo- + nents, although a 135 MHz RAMDAC part exists. + + Information for Matrox Millennium/Mystique Users *************** *** 71,128 **** ! o most bitblts ! o filled rectangles ! o cached pixmaps ! o many more... - The Millennium server is fairly well accelerated, and is one of the - fastest XFree86 3.3.1 Xservers. Future work will concentrate on fix- - ing remaining bugs. ! o Basic support for the Matrox Mystique video adapter ! o uses linear frame buffer ! o it should be possible to reach resolutions up to 1280x1024 - o it should be possible to use pixel depths of 8, 16, 24, and 32 bits - per pixel (256 pseudo colour, "high colour", "packed true colour", - "true colour"). ! o supports VESA Display Power Management Signaling (DPMS) ! o has the following accelerations (may be with some bugs): ! o lines - o most bitblts ! o filled rectangles ! o cached pixmaps ! o NOTE: If acceleration do not work properly, you had rather to ! insert: Option "noaccel" line in the Device section of XF86Con- ! fig file. It will be slower but will work better. ! o Experimental Support for the Matrox Millennium II ! o Provided ONLY as a test and to provide early access to Mill II owners ! o Works as if it is a Millennium I ! o We don't have the card's tech docs yet, so no specific Mill II speedups ! o Has plenty of bugs: - o May corrupt your text font when you exit X - o May not work correctly at 24 bpp --- 71,130 ---- ! o the MGA Storm (MGA1064SG) chipset with integrated 170 and 220 MHz RAMDAC ! o the MGA Storm (MGA1164SG) chipset with integrated 170 and 220 MHz RAMDAC ! o the MGA Storm (MGA2164W) chipset with the TI TVP 3026 RAMDAC. ! o We are still interested to provide support for the other Matrox chipsets ! including the Impression, Atlas, Genesis etc. but at this time have not ! been able to obtain the docs for them. + 4. Configuration: ! The server auto-detects WRAM size and RAMDAC speed. Do not bother putting these ! in your "Device" section, as they will be overridden. The TVP3026 and MGA1064SG ! have a programmable clock generator, so probing and setting clocks is unneces- ! sary as well. ! The "nolinear" option is not a valid option for the MGA server. The driver now ! ignores this directive. ! The options "noaccel" or "no_bitblt" turn off BitBlt Engine and other acceler- ! ated functions. ! 5. Known solutions for some problems: ! o the driver doesn't support some values of HTotal parameter in Modelines in ! the XF86Config file. If you get flickering vertical stripes on the screen, ! try to change this parameter +/- 8. ! o On some Millennium II cards the driver shows severe distortions with 24bpp ! in modes above about 1024x768. We hope to have automated the detection and ! fix of this problem. If it still occurs, please use Option "mga_24bpp_fix" ! in the Device Section to get a stable picture. ! 6. Authors ! Radoslaw Kapitan, kapitan@student.uci.agh.edu.pl ! Mark Vojkovich, mvojkovi@sdcc10.ucsd.edu ! and: ! o Andrew Vanderstock, vanderaj@mail2.svhm.org.au ! o Angsar Hockmann, Ansgar.Hockmann@hrz.uni-dortmund.de ! o Michael Will, Michael.Will@student.uni-tuebingen.de ! o Andrew Mileski, aem@ott.hookup.net *************** *** 131,195 **** - - Information for Matrox Millennium/Mystique Users ! o Lots more where that came from... :-) ! 3. Future Features (in order from highest to lowest priority) ! o more hardware acceleration (more primitive operations, etc) ! o hw cursor for Mystique board ! o more chipsets and RAMDACs ! o 3D acceleration using Mesa - 4. Technical Note: - This driver only supports: - o the MGA Storm (MGA2064W) chipset with the TI (TVP) 3026 RAMDAC. Matrox - have only so far made 175, 220 and 250 MHz boards with these two compo- - nents, although a 135 MHz RAMDAC part exists. - o the MGA Storm (MGA1064SG) chipset with integrated 170 and 220 MHz RAMDAC - o the MGA Storm (MGA2164W) chipset with the TI TVP 3026 RAMDAC. This is - experimental - o We will eventually provide support for the other Matrox chipsets (once the - Millennium driver is at a far enough stage and more people with other - cards join the effort), including the Impression, Atlas, Genesis etc. - At the moment, however, only the Millennium and Mystique are supported. - 5. Configuration: - The server auto-detects WRAM size and RAMDAC speed. Do not bother putting these - in your "Device" section, as they will be overridden. The TVP3026 and MGA1064SG - have a programmable clock generator, so probing and setting clocks is unneces- - sary as well. - The "nolinear" option is not a valid option for the MGA server. The driver now - ignores this directive. - The options "noaccel" or "no_bitblt" turn off BitBlt Engine and other acceler- - ated functions. - 6. Known solutions for some problems: - o the driver doesn't support some values of HTotal parameter in Modelines in - the XF86Config file. If you get flickering vertical stripes on the screen, - try to change this parameter +/- 8. --- 133,171 ---- Information for Matrox Millennium/Mystique Users ! o Stephen Pitts, pitts2@memphisonline.com + o Dirk Hohndel, hohndel@XFree86.Org ! o Leonard N. Zubkoff, lnz@dandelion.com ! o Harm Hanemaayer, H.Hanemaayer@inter.nl.net ! o Guy Desbief, g.desbief@aix.pacwan.net ! o Takaaki Nomura, tnomura@sfc.keio.ac.jp ! Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/MGA.sgml,v 3.4.2.8 1998/02/26 20:11:26 hohndel Exp $ *************** *** 199,239 **** - Information for Matrox Millennium/Mystique Users - 7. Authors - Radoslaw Kapitan, kapitan@student.uci.agh.edu.pl - and: - o Andrew Vanderstock, vanderaj@mail2.svhm.org.au - o Angsar Hockmann, Ansgar.Hockmann@hrz.uni-dortmund.de - o Michael Will, Michael.Will@student.uni-tuebingen.de - o Andrew Mileski, aem@ott.hookup.net - o Stephen Pitts, pitts2@memphisonline.com - o Dirk Hohndel, hohndel@XFree86.Org - o Leonard N. Zubkoff, lnz@dandelion.com - o Mark Vojkovich, mvojkovi@sdcc10.ucsd.edu - o Harm Hanemaayer, H.Hanemaayer@inter.nl.net - o Guy Desbief, g.desbief@aix.pacwan.net - Visit the Matrox Millennium XServer for XFree86 Home Page - to keep up to date with - the latest news, new sources, etc. - Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/MGA.sgml,v 3.4.2.5 1997/08/02 13:48:14 dawes Exp $ --- 175,197 ---- *************** *** 241,270 **** - - - - - - - - - - - - - - - - - - - - - - - - Information for Matrox Millennium/Mystique Users --- 199,204 ---- *************** *** 343,357 **** 2. Features: ................................................................ 1 ! 3. Future Features (in order from highest to lowest priority) ............... 3 ! 4. Technical Note: .......................................................... 3 ! 5. Configuration: ........................................................... 3 ! 6. Known solutions for some problems: ....................................... 3 - 7. Authors .................................................................. 4 --- 277,290 ---- 2. Features: ................................................................ 1 ! 3. Technical Note: .......................................................... 1 ! 4. Configuration: ........................................................... 2 ! 5. Known solutions for some problems: ....................................... 2 ! 6. Authors .................................................................. 2 *************** *** 391,398 **** i ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/README.MGA,v 3.6.2.4 1997/08/02 13:53:31 dawes Exp $ --- 324,332 ---- + i ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/README.MGA,v 3.6.2.7 1998/02/27 02:54:59 dawes Exp $ *** ./programs/Xserver/hw/xfree86/doc/README.NV1@@/PUBLIC-LATEST Sat Jul 19 10:27:30 1997 --- xc/programs/Xserver/hw/xfree86/doc/README.NV1 Fri Mar 6 16:36:59 1998 *************** *** 7,50 **** ! Information for NVidia NV1 / SGS-Thomson STG2000 Users ! David McKay ! 23 October 1996 ! 1. XFree driver for NVidia NV1 / SGS-Thomson STG2000 v1.0 ! This is the first release of a driver for the above chips. This driver has very ! basic functionality, and does not use the accelerated features of the chip. 1.1 Notes ! o THE DRIVER DOES NOT SUPPORT THE VIRTUAL DESKTOP FEATURES OF XFREE86 This ! is because the NV1 does not have the necessary hardware to support this ! feature. If you want to change resolutions, you will have to modify your ! config file. Comment out all but the mode you wish to use. o The generic VGA16 server will not work with the NV1. For this reason XF86Setup cannot be used to configure the server. Use xf86config instead. Select `Diamond Edge 3D' as your board, and select only ONE mode for each of 8bpp and 16bpp. Do not select a virtual desktop. Also, make sure you ! don't select a RAMDAC or clock chip. ! o The NV1 only supports a 555 RGB Weight in 16 bpp, the hardware does not do ! 565. You must put a Weight 555 in the Display section. ! o 24/32 bpp mode is not yet supported. ! 1.2 Known Bugs ! o Corruption of a single pixel in 8bpp mode when switching VCs ! o The driver should force Weight 555 in 16 bpp mode ! Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/NV1.sgml,v 3.2 1997/01/24 09:32:15 dawes Exp $ --- 7,60 ---- ! Information for NVidia NV1 / SGS-Thomson STG2000 and Riva128 Users ! David McKay, Dirk Hohndel ! 26 February 1998 ! 1. XFree86 driver for NVidia NV1 / SGS-Thomson STG2000 and Riva128 ! This driver supports good acceleration for both the NV1/STG2000 as well as the ! Riva128. It is known to work on PCI and AGP versions of the Riva128. 1.1 Notes ! o On the NV1/STG2000, the driver does not support the virtual desktop fea- ! tures of xfree86. This is because the NV1 does not have the necessary ! hardware to support this feature. If you want to change resolutions, you ! will have to modify your config file. Comment out all but the mode you ! wish to use. o The generic VGA16 server will not work with the NV1. For this reason XF86Setup cannot be used to configure the server. Use xf86config instead. Select `Diamond Edge 3D' as your board, and select only ONE mode for each of 8bpp and 16bpp. Do not select a virtual desktop. Also, make sure you ! don't select a RAMDAC or clock chip. This does not apply if you own a ! Riva128 card, as the VGA16 server works just fine on that. ! o Both the NV1 and the Riva128 only support a 555 RGB Weight in 16 bpp, the ! hardware does not do 565. If you run into problems with some window man- ! agers in 16bpp, try putting a Weight 555 in the Display section. ! o 24 bpp is not supported. ! o In some modes the hardware cursor gets out of sync with the display. Use ! Option "sw_cursor" to work around this problem. ! o There are modelines that confuse the Riva128 chip. This results in a ! greenish display. Slightly modifying the modeline usually fixes the prob- ! lem. In most cases all that is needed is to reduce the HTotal. You can use ! xvidtune to do that. ! o The dotclock limits for this driver seem to be lower than the hardware ! specs (and drivers for other graphical user interfaces) seem to indicate. ! If you get a flickery screen with flashes, try to limit the modes you use ! to about 160MHz in 16bpp and about 100MHz in 32bpp. ! Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/NV1.sgml,v 3.2.2.3 1998/02/26 20:11:27 hohndel Exp $ *************** *** 51,73 **** - Information for NVidia NV1 / SGS-Thomson STG2000 Users - Information for NVidia NV1 / SGS-Thomson STG2000 Users --- 61,83 ---- + Information for NVidia NV1 / SGS-Thomson STG2000 and Riva128 Users + Information for NVidia NV1 / SGS-Thomson STG2000 and Riva128 Users *************** *** 127,149 **** - - - - - - - - - - CONTENTS ! 1. XFree driver for NVidia NV1 / SGS-Thomson STG2000 v1.0 ................... 1 1.1 Notes ................................................................ 1 - 1.2 Known Bugs ........................................................... 1 --- 137,148 ---- CONTENTS ! 1. XFree86 driver for NVidia NV1 / SGS-Thomson STG2000 and Riva128 .......... 1 1.1 Notes ................................................................ 1 *************** *** 193,200 **** i ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/README.NV1,v 3.5 1997/01/27 22:12:41 dawes Exp $ --- 192,200 ---- + i ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/README.NV1,v 3.5.2.3 1998/02/27 02:54:59 dawes Exp $ *** ./programs/Xserver/hw/xfree86/doc/README.NetBSD@@/PUBLIC-LATEST Sun Aug 10 13:02:31 1997 --- xc/programs/Xserver/hw/xfree86/doc/README.NetBSD Fri Mar 6 16:37:04 1998 *************** *** 7,23 **** ! README for XFree86 3.3.1 on NetBSD Rich Murphey, David Dawes, Marc Wandschneider, Mark Weaver, Matthieu Herrb ! Last modified on: 26 July 1997 1. What and Where is XFree86? ! XFree86 3.3.1 is a port of X11R6.3 that supports several versions of Intel- based Unix. It is derived from X386 1.2, which was the X server distributed with X11R5. This release consists of many new features and performance improvements as well as many bug fixes. The release is available as source --- 7,23 ---- ! README for XFree86 3.3.2 on NetBSD Rich Murphey, David Dawes, Marc Wandschneider, Mark Weaver, Matthieu Herrb ! Last modified on: 21 February 1998 1. What and Where is XFree86? ! XFree86 3.3.2 is a port of X11R6.3 that supports several versions of Intel- based Unix. It is derived from X386 1.2, which was the X server distributed with X11R5. This release consists of many new features and performance improvements as well as many bug fixes. The release is available as source *************** *** 43,57 **** version of NetBSD first. If you don't upgrade, you'll have to build XFree86 from the sources. XFree86 ! 3.3.1 should compile cleanly under earlier versions of NetBSD, although this has not been tested. ! XFree86 3.3.1 also builds on NetBSD/sparc. See section Building on sparc (sec- ! tion 8.5, page 8) for details. ! The client side of XFree86 also builds on NetBSD/alpha. ! XFree86 3.3.1 also supports NetBSD on PC98 machines. 2. Bug Reports for This Document --- 43,58 ---- version of NetBSD first. If you don't upgrade, you'll have to build XFree86 from the sources. XFree86 ! 3.3.2 should compile cleanly under earlier versions of NetBSD, although this has not been tested. ! XFree86 3.3.2 also builds on NetBSD/sparc. See section Building on other archi- ! tectures (section 8.5, page 8) for details. ! The client side of XFree86 also builds on NetBSD/alpha and many other architec- ! ture supported by NetBSD. ! XFree86 3.3.2 also supports NetBSD on PC98 machines. 2. Bug Reports for This Document *************** *** 60,84 **** have comments or suggestions about this file and we'll revise it. - README for XFree86 3.3.1 on NetBSD - README for XFree86 3.3.1 on NetBSD - 3. New features in this release ! 1. See the Release Notes for non-OS dependent new features in XFree86 3.3.1. 4. Installing the Binaries ! Refer to section 4 of the Release Notes for detailed installation instruc- tions. 4.1 Installing Xdm, the display manager --- 61,84 ---- have comments or suggestions about this file and we'll revise it. + README for XFree86 3.3.2 on NetBSD + README for XFree86 3.3.2 on NetBSD 3. New features in this release ! 1. See the Release Notes for non-OS dependent new features in XFree86 3.3.2. 4. Installing the Binaries ! Refer to section 5 of the Release Notes for detailed installation instruc- tions. 4.1 Installing Xdm, the display manager *************** *** 133,139 **** ! README for XFree86 3.3.1 on NetBSD --- 133,139 ---- ! README for XFree86 3.3.2 on NetBSD *************** *** 162,167 **** --- 162,173 ---- protocol busmouse in the mouse section of your XF86Config file if you're using a PS/2 mouse. + Only standard PS/2 mice are supported by this driver. Newest PS/2 mice that + send more than three bytes at a time (especially intellimouse, or mouseman+ + with a "3D" roller) are not supported yet. + + See README.mouse for general instruction on mouse configuration in XFree86. + 5.2 Other input devices XFree86 supports the dynamic loading of drivers for external input devices *************** *** 185,195 **** XF86Config. Refer to the XF86Config(5) man page for detailed configuration instructions. - You can then change the device used to drive the X pointer with the xset- - pointer(1) command. - For joystick support, you'll need to install the joystick device driver in the - kernel. It is included in NetBSD 1.2. See joy(4) for details. --- 191,197 ---- *************** *** 197,207 **** - README for XFree86 3.3.1 on NetBSD 5.3 Configuring PEX and XIE extensions --- 199,213 ---- + README for XFree86 3.3.2 on NetBSD + You can then change the device used to drive the X pointer with the xset- + pointer(1) command. + For joystick support, you'll need to install the joystick device driver in the + kernel. It is included in NetBSD 1.2. See joy(4) for details. 5.3 Configuring PEX and XIE extensions *************** *** 252,274 **** to - device vt0 at isa? port "IO_KBD" irq 1 - in your kernel config file, and rebuild and install your kernel. - When not using XKB, the server can read the actual keymap from the keyboard ! README for XFree86 3.3.1 on NetBSD ! driver and use to build the X keymap. Be sure to use ``RightAlt ModeShift'' in XF86Config to have the right Alt key behave as AltGr. --- 258,279 ---- to + README for XFree86 3.3.2 on NetBSD ! device vt0 at isa? port "IO_KBD" irq 1 + in your kernel config file, and rebuild and install your kernel. ! When not using XKB, the server can read the actual keymap from the keyboard driver and use to build the X keymap. Be sure to use ``RightAlt ModeShift'' in XF86Config to have the right Alt key behave as AltGr. *************** *** 317,326 **** Add the following lines to the end of /etc/rc.local: - KERNDIR=/usr/X11R6/lib/X11/kernel - if [ -f ${KERNDIR}/ap.o ]; then - modload -o ${KERNDIR}/ap -e ap -p ${KERNDIR}/apinstall ${KERNDIR}/ap.o - fi --- 322,327 ---- *************** *** 330,339 **** - README for XFree86 3.3.1 on NetBSD o NetBSD 1.2D and later --- 331,344 ---- + README for XFree86 3.3.2 on NetBSD + KERNDIR=/usr/X11R6/lib/X11/kernel + if [ -f ${KERNDIR}/ap.o ]; then + modload -o ${KERNDIR}/ap -e ap -p ${KERNDIR}/apinstall ${KERNDIR}/ap.o + fi o NetBSD 1.2D and later *************** *** 343,349 **** ! o NetBSD 1.2G and later The lkm.conf format changed in 1.2G. Add the following line to /etc/lkm.conf: --- 348,354 ---- ! o NetBSD 1.2G, 1.3 and later The lkm.conf format changed in 1.2G. Add the following line to /etc/lkm.conf: *************** *** 383,393 **** to your kernel config file. Then from /sys/arch/i386/config, type: - # rm -f ../compile//* - # config - # cd ../compile/ - # make depend - # make --- 388,393 ---- *************** *** 397,406 **** ! README for XFree86 3.3.1 on NetBSD Then install your new kernel and re-boot: # cp /netbsd /onetbsd --- 397,412 ---- ! README for XFree86 3.3.2 on NetBSD + # rm -f ../compile//* + # config + # cd ../compile/ + # make depend + # make + Then install your new kernel and re-boot: # cp /netbsd /onetbsd *************** *** 424,430 **** 8.1 Console drivers ! XFree86 3.3.1 has a configuration option to select the console drivers to use in xf86site.def: o if you're using pccons put: --- 430,436 ---- 8.1 Console drivers ! XFree86 3.3.2 has a configuration option to select the console drivers to use in xf86site.def: o if you're using pccons put: *************** *** 447,460 **** If you don't define XFree86ConsoleDefines in xf86site.def the pccons and pcvt drivers will be supported. - 8.2 pcvt_ioctl.h file: - XFree86's defaults config includes support for the PCVT console driver. Unfor- - tunately, NetBSD doesn't install the pcvt_ioctl.h file in /usr/include/machine. - If you want to build XFree86 with PCVT support, execute the following command - as root before starting make World: - cp /usr/src/sys/arch/i386/isa/pcvt/pcvt_ioctl.h /usr/include/machine --- 453,460 ---- *************** *** 463,472 **** ! README for XFree86 3.3.1 on NetBSD If you don't have kernel sources, you can grab this file from ftp.netbsd.org or one of its mirrors. If you're not running PCVT, you can remove -DPCVT_SUPPORT from XFree86ConsoleDefines in xf86site.def too. --- 463,481 ---- ! README for XFree86 3.3.2 on NetBSD + 8.2 pcvt_ioctl.h file: + + XFree86's defaults config includes support for the PCVT console driver. Unfor- + tunately, NetBSD doesn't install the pcvt_ioctl.h file in /usr/include/machine. + If you want to build XFree86 with PCVT support, execute the following command + as root before starting make World: + + cp /usr/src/sys/arch/i386/isa/pcvt/pcvt_ioctl.h /usr/include/machine + If you don't have kernel sources, you can grab this file from ftp.netbsd.org or one of its mirrors. If you're not running PCVT, you can remove -DPCVT_SUPPORT from XFree86ConsoleDefines in xf86site.def too. *************** *** 494,500 **** 8.4 Support for shared libs under NetBSD 1.0 and later ! By default XFree86 3.3.1 builds for NetBSD with shared libraries support. If you're building on 0.9 or don't want shared libraries add the following line to xf86site.def: --- 503,509 ---- 8.4 Support for shared libs under NetBSD 1.0 and later ! By default XFree86 3.3.2 builds for NetBSD with shared libraries support. If you're building on 0.9 or don't want shared libraries add the following line to xf86site.def: *************** *** 501,509 **** #define BuildBsdSharedLibs NO ! 8.5 Building on Sparc ! XFree86 3.3.1 also compiles on NetBSD/sparc. The Sun server patches from Dennis Ferguson and Matthew Green have been integrated in xc/programs/Xserver/hw/sun. Small modifications to xf86site.def are needed: --- 510,518 ---- #define BuildBsdSharedLibs NO ! 8.5 Building on other architectures ! XFree86 3.3.2 also compiles on NetBSD/sparc. The Sun server patches from Dennis Ferguson and Matthew Green have been integrated in xc/programs/Xserver/hw/sun. Small modifications to xf86site.def are needed: *************** *** 511,523 **** trolling the Sun servers to build Xsun24Server, XsunServer and Xsun- MonoServer are defined at the end of NetBSD.cf.) - o Set ServerToInstall to the sun server of your choice. (Xsun or XsunMono). - o Look at other applicable options in the INSTALL document. - Problems with this port should be reported to the port-sparc@NetBSD.Org mailing - list or directly to me matthieu@laas.fr rather than to the xfree86 mailing - list. --- 520,527 ---- *************** *** 525,538 **** ! README for XFree86 3.3.1 on NetBSD 9. Building New X Clients The easiest way to build a new client (X application) is to use xmkmf if an --- 529,553 ---- + README for XFree86 3.3.2 on NetBSD + o Set ServerToInstall to the sun server of your choice. (Xsun or XsunMono). ! o Look at other applicable options in the INSTALL document. + Problems with this port should be reported to the port-sparc@NetBSD.Org mailing + list or directly to me matthieu@laas.fr rather than to the xfree86 mailing + list. + Note that the NetBSD project has now its own source tree, based on the XFree86 + source tree, with some local modifications. You may want to start with this + tree to rebuild from sources. The NetBSD xsrc source tree is available at: + ftp://ftp.netbsd.org/pub/NetBSD/NetBSD-current/xsrc/ + + 9. Building New X Clients The easiest way to build a new client (X application) is to use xmkmf if an *************** *** 572,616 **** at run-time, you've stumbled on a semantic weakness of the NetBSD dynamic linker. Applications that use libXmu also need libXt. If the client uses a standard Imakefile, this dependency will probably by included in the Makefile - automagically -- you'll not see the problem. Otherwise, just add ``-lXt'' to - your library list in the Imakefile or Makefile and relink. - 10. Thanks - Many thanks to: - o Pace Willison for providing the initial port to 386BSD. - o Amancio Hasty for fixing cursor restoration, mouse bugs and many others. - o Christoph Robitschko for fixing com.c and thus select(). ! README for XFree86 3.3.1 on NetBSD - o Nate Williams for the patchkit support for X. o Rod Grimes and Jack Velte of Walnut Creek Cdrom for use of their machines in preparing the FreeBSD binary release. ! Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/NetBSD.sgml,v 3.45.2.5 1997/07/27 02:41:16 dawes Exp $ ! $TOG: README.NetBSD /main/33 1997/08/10 13:01:07 kaleb $ --- 587,630 ---- at run-time, you've stumbled on a semantic weakness of the NetBSD dynamic linker. Applications that use libXmu also need libXt. If the client uses a standard Imakefile, this dependency will probably by included in the Makefile + README for XFree86 3.3.2 on NetBSD + automagically -- you'll not see the problem. Otherwise, just add ``-lXt'' to + your library list in the Imakefile or Makefile and relink. + 10. Thanks + Many thanks to: + o Pace Willison for providing the initial port to 386BSD. ! o Amancio Hasty for fixing cursor restoration, mouse bugs and many others. + o Christoph Robitschko for fixing com.c and thus select(). o Nate Williams for the patchkit support for X. o Rod Grimes and Jack Velte of Walnut Creek Cdrom for use of their machines in preparing the FreeBSD binary release. ! Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/NetBSD.sgml,v 3.45.2.7 1998/02/26 13:59:07 dawes Exp $ ! $TOG: README.NetBSD /main/34 1998/03/06 16:38:42 kaleb $ *************** *** 647,652 **** --- 661,667 ---- + README for XFree86 3.3.2 on NetBSD *************** *** 661,667 **** - README for XFree86 3.3.1 on NetBSD --- 676,681 ---- *************** *** 717,736 **** - - - - - - - - - - - - - - CONTENTS --- 731,736 ---- *************** *** 757,770 **** 8. Rebuilding the XFree86 Distribution ..................................... 7 8.1 Console drivers ..................................................... 7 ! 8.2 pcvt_ioctl.h file: .................................................. 7 8.3 console.h and ioctl_pc.h files: ..................................... 8 8.4 Support for shared libs under NetBSD 1.0 and later .................. 8 ! 8.5 Building on Sparc ................................................... 8 9. Building New X Clients .................................................. 9 ! 10. Thanks .................................................................. 9 --- 757,770 ---- 8. Rebuilding the XFree86 Distribution ..................................... 7 8.1 Console drivers ..................................................... 7 ! 8.2 pcvt_ioctl.h file: .................................................. 8 8.3 console.h and ioctl_pc.h files: ..................................... 8 8.4 Support for shared libs under NetBSD 1.0 and later .................. 8 ! 8.5 Building on other architectures ..................................... 8 9. Building New X Clients .................................................. 9 ! 10. Thanks ................................................................. 10 *************** *** 791,794 **** ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/README.NetBSD,v 3.57.2.6 1997/07/27 02:43:22 dawes Exp $ --- 791,794 ---- ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/README.NetBSD,v 3.57.2.8 1998/02/27 02:55:00 dawes Exp $ *** ./programs/Xserver/hw/xfree86/doc/README.OS2@@/PUBLIC-LATEST Sun Aug 10 13:02:37 1997 --- xc/programs/Xserver/hw/xfree86/doc/README.OS2 Fri Mar 6 16:37:09 1998 *************** *** 7,21 **** ! README for XFree86 3.3.1 on OS/2 Holger Veit ! Last modified on: 2 August 1997 ! 1. Introductory Note about the release 3.3.1 Before looking into this file, please check for any LATEST.OS2 files that may come with the binary distribution. Please also check out the following --- 7,21 ---- ! README for XFree86 3.3.2 on OS/2 Holger Veit ! Last modified on: 15 February 1998 ! 1. Introductory Note about the release 3.3.2 Before looking into this file, please check for any LATEST.OS2 files that may come with the binary distribution. Please also check out the following *************** *** 29,43 **** before you claim to have found any problems. ! This version of the code is called XFree86/OS2 3.3.1. This is a bugfix release ! for 3.3. It is a full, unrestricted version which does not expire, and for ! which the complete source code is available. In contrast to beta versions, we ! consider this code as sufficiently stable for use by an end user. Since there ! have been numerous bugfixes, we recommend this version, even if you had ! XFree86/OS2 3.2 before and it worked satisfyingly with your hardware. By the ! time 3.3.1 is released, the older version 3.3 will be withdrawn, and archives ! will be updated to this version. There may still be references to 3.3 still in ! documents; these apply to 3.3.1 as well, unless otherwise noted. Previous versions have been tested in a large number of configurations and have been found to be working, with some bugs left, rather flawlessly. --- 29,45 ---- before you claim to have found any problems. ! This version of the code is called XFree86/OS2 3.3.2. This is a bugfix release ! for 3.3.1 which also adds hardware support for some newer cards (including AGP ! boards. See the RELNOTES document for details. Xfree86/OS2-3.3.2 is a full, ! unrestricted version which does not expire, and for which the complete source ! code is available. In contrast to beta versions, we consider this code as suf- ! ficiently stable for use by an end user. Since there have been numerous bug- ! fixes, we recommend this version, even if you had XFree86/OS2 3.3 before and it ! worked satisfyingly with your hardware. By the time 3.3.2 is released, the ! older version 3.3 will be withdrawn, and archives will be updated to this ver- ! sion. There may still be references to 3.3 still in documents; these apply to ! 3.3.2 as well, unless otherwise noted. Previous versions have been tested in a large number of configurations and have been found to be working, with some bugs left, rather flawlessly. *************** *** 56,76 **** o even with a code we consider stable there is no explicit or implicit war- ranty that certain code works correctly or works at all - o although no damage reports are known, it does not mean that it is impossi- - ble to damage hardware with this code; some deeply hidden bugs may still - be present in the software. - README for XFree86 3.3.1 on OS/2 - README for XFree86 3.3.1 on OS/2 It is recommended that you backup essential data of your system before installing this software, but this should be your general precautions before ANY installation. No reports exist that a crashing X server itself actively --- 58,80 ---- o even with a code we consider stable there is no explicit or implicit war- ranty that certain code works correctly or works at all + README for XFree86 3.3.2 on OS/2 + README for XFree86 3.3.2 on OS/2 + + o although no damage reports are known, it does not mean that it is impossi- + ble to damage hardware with this code; some deeply hidden bugs may still + be present in the software. + It is recommended that you backup essential data of your system before installing this software, but this should be your general precautions before ANY installation. No reports exist that a crashing X server itself actively *************** *** 83,93 **** 2. What and Where is XFree86? ! XFree86 is a port of X11R6 that supports several versions of Intel-based Unix. ! It is derived from X386 1.2, which was the X server distributed with X11R5. ! This release consists of many new features and performance improvements as well ! as many bug fixes. The release is available as source patches against the X ! Consortium X11R6 code, as well as binary distributions for many architectures. XFree86/OS2 is the name of the implementation of XFree86 on OS/2 based systems. --- 87,98 ---- 2. What and Where is XFree86? ! XFree86 is a port of X11R6.3 that supports several versions of Intel-based ! Unix. It is derived from X386 1.2, which was the X server distributed with ! X11R5. This release consists of many new features and performance improvements ! as well as many bug fixes. The release is available as source patches against ! the X Consortium X11R6 code, as well as binary distributions for many architec- ! tures. XFree86/OS2 is the name of the implementation of XFree86 on OS/2 based systems. *************** *** 94,100 **** See the Copyright Notice. Binaries for OS/2 Warp and Merlin are available from: ! ftp.XFree86.org:/pub/XFree86/beta/OS2 The WWW page http://borneo.gmd.de/~veit/os2/xf86os2.html will usually show more references to FTP or WWW sites to retrieve sources or binaries. --- 99,105 ---- See the Copyright Notice. Binaries for OS/2 Warp and Merlin are available from: ! ftp.XFree86.org:/pub/XFree86/3.3.2/OS2 The WWW page http://borneo.gmd.de/~veit/os2/xf86os2.html will usually show more references to FTP or WWW sites to retrieve sources or binaries. *************** *** 106,126 **** For Warp 3 installing fixpack level 17 is strongly recommended, newer fixpacks like 22 also work. There have been a few reports that the installation of FP26 ! causes XFree86 no longer to work, but I am not sure about a real reason. ! Warp 4 may be used with or without the recent public fixpack FP1. Please check in all cases a LATEST.OS2 file. OS/2 2.11 is not supported any longer with this release, due to lack of a work- ! ing test environment. Consequently, OS/2 SMP is not supported either, because ! this is currently based on OS/2 2.11. Warp Server SMP is supported, but SMP ! does not give significant advantage, other than the general speedup because of ! multiple processors working. OS/2 versions 1.X are definitely not supported ! and will never be. It is possible to build XFree86/OS2 from the sources. Read about this in the - document OS2.NOTES. --- 111,130 ---- For Warp 3 installing fixpack level 17 is strongly recommended, newer fixpacks like 22 also work. There have been a few reports that the installation of FP26 ! causes XFree86 no longer to work, but I am not sure about a real reason. Cur- ! rent fixpacks for Warp 3, like FP32, seem to work well also. ! Warp 4 may be used with or without the recent public fixpack FP5. Please check in all cases a LATEST.OS2 file. OS/2 2.11 is not supported any longer with this release, due to lack of a work- ! ing test environment. Consequently, OS/2 SMP 2.11 is not supported either. Warp ! Server SMP is supported, but SMP does not give significant advantage, other ! than the general speedup because of multiple processors working. OS/2 versions ! 1.X are definitely not supported and will never be. It is possible to build XFree86/OS2 from the sources. Read about this in the *************** *** 129,142 **** - README for XFree86 3.3.1 on OS/2 - - 3. Bug Reports for This Document Send email to Holger.Veit@gmd.de (Holger Veit) or XFree86@XFree86.org if you --- 133,145 ---- + README for XFree86 3.3.2 on OS/2 + document OS2.NOTES. 3. Bug Reports for This Document Send email to Holger.Veit@gmd.de (Holger Veit) or XFree86@XFree86.org if you *************** *** 169,175 **** o Any version of Warp 3 with at least fixpack 17, or Warp 4 is required ! o XFree86/OS2-3.3.1 may use a local named-pipe connection or a TCP/IP based network connection. 1. Warp comes with the Internet Access Kit (IAK), which is sufficient. --- 172,178 ---- o Any version of Warp 3 with at least fixpack 17, or Warp 4 is required ! o XFree86/OS2-3.3.2 may use a local named-pipe connection or a TCP/IP based network connection. 1. Warp comes with the Internet Access Kit (IAK), which is sufficient. *************** *** 178,184 **** 2. Warp 4 comes with TCP/IP 4.0 which should also work. ! 3. The old IBM TCP/IP 2.0, that comes with the IBM PMX product may be used with Warp as well, although it is no longer supported by IBM. Please ensure that you have the latest CSDs installed. --- 181,190 ---- 2. Warp 4 comes with TCP/IP 4.0 which should also work. ! 3. There are reports that with EMX 0.9 fix 4, you can also use the new ! 32 bit IBM TCP/IP 4.1 product. ! ! 4. The old IBM TCP/IP 2.0, that comes with the IBM PMX product may be used with Warp as well, although it is no longer supported by IBM. Please ensure that you have the latest CSDs installed. *************** *** 185,196 **** Other versions of TCP/IP, such as FTP's, DEC's, or Hummingbird's TCP/IP versions, as well as IBM TCP/IP 1.X are not supported. Nor does any net- working support from DOS (packet drivers, winsock), Netware, or NetBIOS - work, and I won't to provide support for that in the future. - o If you want to write or port applications for XFree86, you are encouraged - to do so. You will need a complete installation of EMX/gcc 0.9C fix2 or - later for doing so. Neither the second (obsolete) implementation of gcc, - nor any commercial package, including Cset/2, VAC++, Borland C++/OS2, --- 191,197 ---- *************** *** 198,210 **** - README for XFree86 3.3.1 on OS/2 ! Watcom C++, Metaware C, and others, is suitable for porting, because vari- ! ous parts of the X DLLs rely on certain features only present with EMX. 5. Installing the System --- 199,216 ---- + README for XFree86 3.3.2 on OS/2 + work, and I won't to provide support for that in the future. ! o If you want to write or port applications for XFree86, you are encouraged ! to do so. You will need a complete installation of EMX/gcc 0.9C fix4 or ! later for doing so. Neither the second (obsolete) implementation of gcc, ! nor any commercial package, including Cset/2, VAC++, Borland C++/OS2, Wat- ! com C++, Metaware C, and others, is suitable for porting, because various ! parts of the X DLLs rely on certain features only present with EMX. 5. Installing the System *************** *** 214,222 **** files. The full distribution requires about 40-55MB of disk space. All archives of this alpha version are packed with the info-zip utility, which ! is available under the name UNZ512X2.EXE from many OS/2 archives. Please ! obtain a native OS/2 version of this unpacker. DOS PKUNZIP does not work, ! because it cannot unpack long file names and extended attributes. At this moment, the distribution covers only the ``core'' distribution which somewhat reduces the usability. Refer to WWW sites and archives listed in the --- 220,229 ---- files. The full distribution requires about 40-55MB of disk space. All archives of this alpha version are packed with the info-zip utility, which ! is available under the name UNZ512X2.EXE (or a later version) from many OS/2 ! archives. Please obtain a native OS/2 version of this unpacker. DOS PKUNZIP ! does not work, because it cannot unpack long file names and extended ! attributes. At this moment, the distribution covers only the ``core'' distribution which somewhat reduces the usability. Refer to WWW sites and archives listed in the *************** *** 227,243 **** REQUIRED: ! X331base A special device driver and the SuperProbe program ! X331doc READMEs and XFree86 specific man pages. ! X331bin all of the executable X client applications and shared libs ! X331fnts the misc and 75dpi fonts emxrt --- 234,250 ---- REQUIRED: ! X332base A special device driver and the SuperProbe program ! X332doc READMEs and XFree86 specific man pages. ! X332bin all of the executable X client applications and shared libs ! X332fnts the misc and 75dpi fonts emxrt *************** *** 245,261 **** Choose at least one of the following to match your hardware: ! X3318514 the X server for IBM 8514/A and compatible boards ! X331AGX the X server for AGX boards - X331I128 - the X server for #9 Imagination 128 boards - X331Ma32 - the X server for ATI Mach32 graphics boards --- 252,264 ---- Choose at least one of the following to match your hardware: ! X3328514 the X server for IBM 8514/A and compatible boards ! X332AGX the X server for AGX boards *************** *** 262,328 **** ! README for XFree86 3.3.1 on OS/2 ! ! X331Ma64 the X server for ATI Mach64 graphics boards ! X331Ma8 the X server for ATI Mach8 graphics boards ! X331Mono the Monochrome X Server ! X331P9K the X server for P9000 based boards ! X331S3 the X server for S3 based boards (excluding S3 ViRGE) ! X331S3V the X server for S3 ViRGE based boards ! X331SVGA the 8-bit pseudo-color X server for Super VGA cards ! X331VG16 the 4-bit pseudo-color X server for VGA & SVGA cards. ! X331W32 the X server for et4000w32 based boards OPTIONAL: ! X331man pre-formatted man pages for the X11 interface and clients ! X331f100 100dpi fonts ! X331fscl Speedo and Type1 fonts ! X331fnon Japanese, Chinese and other fonts ! X331fcyr Cyrillic fonts ! X331fsrv the font server with man pages. - X331prog - the X11 header files and programmer's utilities for - compiling other X applications - X331pex - PEX fonts and libraries required for PEX applications --- 265,329 ---- + README for XFree86 3.3.2 on OS/2 ! X332I128 ! the X server for #9 Imagination 128 boards + X332Ma32 + the X server for ATI Mach32 graphics boards ! X332Ma64 the X server for ATI Mach64 graphics boards ! X332Ma8 the X server for ATI Mach8 graphics boards ! X332Mono the Monochrome X Server ! X332P9K the X server for P9000 based boards ! X332S3 the X server for S3 based boards (excluding S3 ViRGE) ! X332S3V the X server for S3 ViRGE based boards ! X332SVGA the 8-bit pseudo-color X server for Super VGA cards ! X332VG16 the 4-bit pseudo-color X server for VGA & SVGA cards. ! X332W32 the X server for et4000w32 based boards OPTIONAL: ! X332man pre-formatted man pages for the X11 interface and clients ! X332f100 100dpi fonts ! X332fscl Speedo and Type1 fonts ! X332fnon Japanese, Chinese and other fonts ! X332fcyr Cyrillic fonts ! X332fsrv the font server with man pages. *************** *** 330,346 **** - README for XFree86 3.3.1 on OS/2 In order to save space on your disk and reduce net bandwidth, choose the soft- ware to obtain carefully. Each X server is an archive of about 1.2MB and occu- pies 3.0MB on the disk. You won't normally need more than the single Xserver tailored to your video card. ! If it is your first time install, get the X331base archive before any of the other packages. This package contains a driver and a test program, which ana- lyzes your video hardware. If this program fails or reports an incompatible hardware, it makes no sense to obtain the other packages in the hope that they --- 331,353 ---- + README for XFree86 3.3.2 on OS/2 + X332prog + the X11 header files and programmer's utilities for + compiling other X applications + X332pex + PEX fonts and libraries required for PEX applications + In order to save space on your disk and reduce net bandwidth, choose the soft- ware to obtain carefully. Each X server is an archive of about 1.2MB and occu- pies 3.0MB on the disk. You won't normally need more than the single Xserver tailored to your video card. ! If it is your first time install, get the X332base archive before any of the other packages. This package contains a driver and a test program, which ana- lyzes your video hardware. If this program fails or reports an incompatible hardware, it makes no sense to obtain the other packages in the hope that they *************** *** 383,394 **** drive with the letter Y: (which you probably don't have). Change the letter in all commands accordingly. - 1. Obtain the package X331base and install it from the root directory of the - Y: drive, by entering the following commands: - [C:\] Y: - [Y:\] cd \ - [Y:\] unzip \path_of_package\X331base.zip --- 390,396 ---- *************** *** 395,406 **** - README for XFree86 3.3.1 on OS/2 2. Edit your CONFIG.SYS file to contain the following line somewhere: DEVICE=Y:\XFree86\lib\xf86sup.sys --- 397,415 ---- + README for XFree86 3.3.2 on OS/2 + 1. Obtain the package X332base and install it from the root directory of the + Y: drive, by entering the following commands: + [C:\] Y: + [Y:\] cd \ + [Y:\] unzip \path_of_package\X332base.zip + + 2. Edit your CONFIG.SYS file to contain the following line somewhere: DEVICE=Y:\XFree86\lib\xf86sup.sys *************** *** 446,487 **** obtain the rest of the software. - 8. Installing the packages - XFree86/OS2 assumes a directory hierarchy starting from drive:\XFree86. This - can be changed, but is strictly discouraged. - 1. Choose a HPFS partition with sufficient free space. - 2. For each package to install, go to the root directory of this drive, and - type: ! README for XFree86 3.3.1 on OS/2 drive:> cd \ ! drive:> unzip \path_of_packages\X331xxxx.zip 3. You might encounter that some packages report duplicate files, e.g. the X server packages install corresponding README files, which are also in ! the X331doc package. This is okay, the files are the same. Let unzip replace the files. ! 4. There is no special sequence of installing packages required. 9. Adding Variables to CONFIG.SYS XFree86/OS2 requires a number of settings in the CONFIG.SYS file to work cor- ! rectly. Please add the following settings: TERM Set the preferred terminal type for the xterm or editor to be used. --- 455,498 ---- obtain the rest of the software. + README for XFree86 3.3.2 on OS/2 ! 8. Installing the packages + XFree86/OS2 assumes a directory hierarchy starting from drive:\XFree86. This + can be changed, but is strictly discouraged. + 1. Choose a HPFS partition with sufficient free space. + 2. For each package to install, go to the root directory of this drive, and + type: + drive:> cd \ ! drive:> unzip \path_of_packages\X332xxxx.zip 3. You might encounter that some packages report duplicate files, e.g. the X server packages install corresponding README files, which are also in ! the X332doc package. This is okay, the files are the same. Let unzip replace the files. ! 4. No special sequence to unpack the files is required. 9. Adding Variables to CONFIG.SYS XFree86/OS2 requires a number of settings in the CONFIG.SYS file to work cor- ! rectly. Please add the following settings, and in particular take care to set ! forward versus backward slashes correctly: TERM Set the preferred terminal type for the xterm or editor to be used. *************** *** 510,540 **** SET ETC=C:\TCPIP\ETC - TMP - Set to an TMP directory. Normally, this is already set to the TMP - directory of the TCP/IP code, such as - SET TMP=C:\TCPIP\TMP - HOSTNAME - Set to the internet hostname. Normally, this is already set by the - TCP/IP installation program, such as - SET HOSTNAME=myhost ! README for XFree86 3.3.1 on OS/2 With IAK, you would normally run a loopback configuration Network ! configuration (section 10., page 10) and would then set this to SET HOSTNAME=localhost --- 521,553 ---- SET ETC=C:\TCPIP\ETC + README for XFree86 3.3.2 on OS/2 ! TMP ! Set to an TMP directory. Normally, this is already set to the TMP ! directory of the TCP/IP code, such as + SET TMP=C:\TCPIP\TMP + HOSTNAME + Set to the internet hostname. Normally, this is already set by the + TCP/IP installation program, such as + SET HOSTNAME=myhost + + With IAK, you would normally run a loopback configuration Network ! configuration (section 10., page 11) and would then set this to SET HOSTNAME=localhost *************** *** 575,604 **** , but this is discouraged, since some utilities might not accept this. Note the forward ``/'' as a directory separator here. - DISPLAY - This variable may be set to the display to be used for displaying - clients. Normally you will set this variable to the same value as - the HOSTNAME variable and simply add a :0.0 after it, such as - SET DISPLAY=myhost:0.0 - Read the X11 man page on the exact meaning of these postfixes and - other options. ! README for XFree86 3.3.1 on OS/2 - - XSERVER Set this to the executable name of the X server to be used. This must be a complete path. My setting is as follows: --- 588,615 ---- , but this is discouraged, since some utilities might not accept this. Note the forward ``/'' as a directory separator here. + README for XFree86 3.3.2 on OS/2 + DISPLAY + This variable may be set to the display to be used for displaying + clients. Normally you will set this variable to the same value as + the HOSTNAME variable and simply add a :0.0 after it, such as + SET DISPLAY=myhost:0.0 ! Read the X11 man page on the exact meaning of these postfixes and ! other options. XSERVER Set this to the executable name of the X server to be used. This must be a complete path. My setting is as follows: *************** *** 642,657 **** It is beyond the scope of this document to even give an introduction about the correct installation of the TCP/IP networking system. You must do this yourself or seek assistance elsewhere. It is only possible to say here that a PC working - well in a TCP/IP based LAN network will also work with XFree86/OS2 (when all - other prerequisites are matched as well). - With IAK, there is a special configuration necessary, unless you want to use - XFree86/OS2 only during a hot link to your Internet provider, the so called - ``localhost'' or ``loopback'' configuration. This is a local network interface - which ``loops'' back to the same host. The following settings are necessary for - this: - 1. Create a file \tcpip\etc\hosts with the following content: --- 653,660 ---- *************** *** 658,669 **** ! README for XFree86 3.3.1 on OS/2 127.0.0.1 localhost --- 661,680 ---- + README for XFree86 3.3.2 on OS/2 ! well in a TCP/IP based LAN network will also work with XFree86/OS2 (when all ! other prerequisites are matched as well). + With IAK, there is a special configuration necessary, unless you want to use + XFree86/OS2 only during a hot link to your Internet provider, the so called + ``localhost'' or ``loopback'' configuration. This is a local network interface + which ``loops'' back to the same host. The following settings are necessary for + this: + 1. Create a file \tcpip\etc\hosts with the following content: 127.0.0.1 localhost *************** *** 671,692 **** ifconfig lo 127.0.0.1 up - 3. Uncomment the inetd process in the same file. ! 4. Set the HOSTNAME environment variable to localhost as described in the last section. ! 5. Add the following line to CONFIG.SYS: SET USE_HOSTS_FIRST=1 ! 6. After rebooting, verify that the following command works: [C:\] ping localhost ! The checkinstall.cmd script coming with XFree86/OS2 gives some advice here as ! well. If you have problems to get this or other basic networking things running, seek assistance elsewhere. --- 682,713 ---- ifconfig lo 127.0.0.1 up ! If you don't have such a tcpstart.cmd file (Warp 4 calls this file ! \MPTN\BIN\MPTSTART.CMD), create one, and add a line like the following to ! your config.sys file: CALL=C:\OS2\CMD.EXE /Q /C C:\tcpip\bin\tcpstart.cmd ! >NUL: (implying that your bootdrive is C:). ! ! 3. Set the HOSTNAME environment variable to localhost as described in the last section. ! 4. Add the following line to CONFIG.SYS: SET USE_HOSTS_FIRST=1 ! 5. After rebooting, verify that the following command works: [C:\] ping localhost ! You don't need this ``loopback'' interface if your PC is connected to a LAN ! (either directly or through SLIP/PPP). + In case of a SLIP/PPP line, you have to establish this connection BEFORE you + start XFree86. + + The checkinstall.cmd script coming with XFree86/OS2 gives some advice on the + configuration as well. + If you have problems to get this or other basic networking things running, seek assistance elsewhere. *************** *** 695,736 **** After you have added the required settings and setup a working network, run the xf86config program to create a standard configuration file in ! Y:\XFree86\lib\X11\XConfig from a windowed or full screen OS/2 text session: [C:\] xf86config - The xf86config program will ask a number of questions. You will need the infor- - mation obtained from the SuperProbe program here. The program should be self - explanatory; if you have problems to understand something though, seek assis- - tance in the newsgroups. - It is possible, but strongly discouraged for the non-expert, to edit the XCon- - fig file with a text editor. In a few situations, as described in the FAQ, this - might even be mandatory. This file is not a hacker's area, such as the Win95 - registry, but it has in common with it that you can easily cause damage. - For details about the XF86Config file format, refer to the XF86Config(4/5) man- - ual page. - If you know the configuration process from Linux or other XFree86 platform, you - will encounter a few differences: - o The configuration file is named XF86Config in Unix environments. - o There is no configuration for the mouse type or device. The mouse device - name is fixed to OSMOUSE, and this cannot be changed. If you have a ! README for XFree86 3.3.1 on OS/2 ! ! three-button-mouse, install the correct OS/2 driver for it, such as DEVICE=D:\OS2\BOOT\PCLOGIC.SYS SERIAL=COM1 --- 716,755 ---- After you have added the required settings and setup a working network, run the xf86config program to create a standard configuration file in ! Y:\XFree86\lib\X11\XF86Config from a windowed or full screen OS/2 text session: [C:\] xf86config + README for XFree86 3.3.2 on OS/2 + The xf86config program will ask a number of questions. You will need the infor- + mation obtained from the SuperProbe program here. The program should be self + explanatory; if you have problems to understand something though, seek assis- + tance in the newsgroups. + It is possible, but strongly discouraged for the non-expert, to edit the + XF86Config file with a text editor. In a few situations as described in the + FAQ, however, this might even be mandatory. This file is not a hacker's area, + such as the Win95 registry, but it has in common with it that you can easily + cause damage. + For details about the XF86Config file format, refer to the XF86Config(4/5) man- + ual page. ! If you know the configuration process from Linux or other XFree86 platform, you ! will encounter a few differences: ! o There is no configuration for the mouse type or device. The mouse device ! name is fixed to OSMOUSE, and this cannot be changed. If you have a three-button-mouse, install the correct OS/2 driver for it, such as DEVICE=D:\OS2\BOOT\PCLOGIC.SYS SERIAL=COM1 *************** *** 739,749 **** for a MouseSystems compatible mouse, for instance. ! o The X server does not read the native OS/2 keyboard map, so you need a ! xmodmap file for a non-us keyboard. Fortunately, it is the same you use ! for Linux. Alternatively, for standard keyboards, you can also use the XKB ! extension which is offered during the xf86config dialogue, provided your ! language is available. o There is no support for the Wacom and Elographics input devices yet. --- 758,771 ---- for a MouseSystems compatible mouse, for instance. ! o The X server does not read the native OS/2 keyboard map, but the new XKB ! server extension might already give you a correct keyboard layout, pro- ! vided your language was selectable in the xf86config program. If you ! encounter incorrect settings, please send a mail to XFree86@XFree86.org ! describing in detail what is wrong. Even with XKB, you have the option to ! replace some key settings with a xmodmap file. See the man page for ! xmodmap for details (or use some available xmodmap file from Linux - they ! are the same). o There is no support for the Wacom and Elographics input devices yet. *************** *** 758,769 **** MemBase 0x12345678 ! to the XConfig file. Once you've set up a XF86Config file, you can fine tune the video modes with the xvidtune utility. 12. Running X 16mb of memory is a recommended minimum for running the network software, X and --- 780,802 ---- MemBase 0x12345678 ! to the XF86Config file. Once you've set up a XF86Config file, you can fine tune the video modes with the xvidtune utility. + + + + + + + + README for XFree86 3.3.2 on OS/2 + + + 12. Running X 16mb of memory is a recommended minimum for running the network software, X and *************** *** 784,804 **** tory that the HOME environment variable points to. These files are described in the xinit and startx man pages. ! By default, the systemwide xinitrc file (in ! ! ! ! ! ! ! ! ! README for XFree86 3.3.1 on OS/2 ! ! ! ! Y:/XFree86/lib/X11/xinit/xinitrc.cmd) installs the rather simplistic twm window ! manager. You can find better window managers on the ported software page at http://set.gmd.de/~veit/os2/xf86ported.html . --- 817,825 ---- tory that the HOME environment variable points to. These files are described in the xinit and startx man pages. ! By default, the systemwide xinitrc file (in Y:/XFree86/lib/X11/xinit/xini- ! trc.cmd) installs the rather simplistic twm window manager. You can find better ! window managers on the ported software page at http://set.gmd.de/~veit/os2/xf86ported.html . *************** *** 829,841 **** o ME - no, no, forget this: I won't praise myself :-) - Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/OS2.sgml,v 3.9.2.4 1997/08/04 02:10:42 dawes Exp $ ! $TOG: README.OS2 /main/9 1997/08/10 13:01:13 kaleb $ --- 850,861 ---- o ME - no, no, forget this: I won't praise myself :-) ! $TOG: README.OS2 /main/10 1998/03/06 16:38:47 kaleb $ *************** *** 859,865 **** - README for XFree86 3.3.1 on OS/2 --- 879,884 ---- *************** *** 904,909 **** --- 923,929 ---- + README for XFree86 3.3.2 on OS/2 *************** *** 929,939 **** CONTENTS ! 1. Introductory Note about the release 3.3.1 ............................... 1 2. What and Where is XFree86? .............................................. 2 --- 949,1003 ---- + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CONTENTS ! 1. Introductory Note about the release 3.3.2 ............................... 1 2. What and Where is XFree86? .............................................. 2 *************** *** 949,955 **** 7. Checking Compatibility of Video Hardware ................................ 6 ! 8. Installing the packages ................................................. 7 9. Adding Variables to CONFIG.SYS ......................................... 8 --- 1013,1019 ---- 7. Checking Compatibility of Video Hardware ................................ 6 ! 8. Installing the packages ................................................. 8 9. Adding Variables to CONFIG.SYS ......................................... 8 *************** *** 957,963 **** 11. Configuring X for Your Hardware ........................................ 11 ! 12. Running X .............................................................. 12 13. Rebuilding the XFree86 Distribution .................................... 13 --- 1021,1027 ---- 11. Configuring X for Your Hardware ........................................ 11 ! 12. Running X .............................................................. 13 13. Rebuilding the XFree86 Distribution .................................... 13 *************** *** 989,992 **** ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/README.OS2,v 3.13.2.4 1997/08/04 02:12:39 dawes Exp $ --- 1053,1056 ---- ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/README.OS2,v 3.13.2.5 1998/02/22 13:06:04 dawes Exp $ *** ./programs/Xserver/hw/xfree86/doc/README.Oak@@/PUBLIC-LATEST Sat Jul 19 10:27:52 1997 --- xc/programs/Xserver/hw/xfree86/doc/README.Oak Fri Mar 6 16:37:14 1998 *************** *** 11,17 **** Jorge F. Delgado Mendoza (ernar@dit.upm.es) ! 12 March 1996 --- 11,17 ---- Jorge F. Delgado Mendoza (ernar@dit.upm.es) ! 27 February 1998 *************** *** 21,29 **** The following chipsets for Oak Tech. Inc. are supported: OTI037C ! 8-bit SVGA chipset, with up to 256Kbytes of DRAM, only preliminary ! support is included in the driver as I don't have a 037c to test ! it. OTI067 ISA SVGA chipset, up to 512Kbytes of DRAM (usually 70/80 ns). --- 21,30 ---- The following chipsets for Oak Tech. Inc. are supported: OTI037C ! 8-bit VGA chipset, with up to 256Kbytes of DRAM. All the boards I ! have seen are only able to do standard VGA modes. (ie. up to ! 320x200x256 and up to 640x480x16). Currently the probe for this ! chip is disabled, so use the generic VGA driver instead. OTI067 ISA SVGA chipset, up to 512Kbytes of DRAM (usually 70/80 ns). *************** *** 30,53 **** OTI077 Enhanced version of the 067, with support for 1Mbyte and up to 65 ! Mhz dot-clock, this chipset supports up to 1024x768x256 colors in ! Non-Interlaced mode, and up to 1280x1024x16 colors Interlaced. OTI087 One of the first VLB chipsets available, it has a 16-bit external ! data path, and a 32-bit internal memory-controller data path, it ! also has register-based color expansion, hardware cursor, a primi- ! tive BitBlt engine, a 64 bit graphic latch and some other new (on ! its time) features. Maximum BIOS resolutions are 1024x768x256 Non- ! Interlaced and 1280x1024x256 interlaced. Maximum Dot-Clock is ! 80Mhz, but is usually coupled with the OTI068 clock generator whose ! highest frequency is 78Mhz. Supports up to 2MBytes of 70/70R ns ! DRAM. OTI107 and OTI111 These are new, PCI chipsets by Oak Tech. Inc. Support is not ! included for them, as they are very rare, and I haven't had the ! chance to look at one of these boards. All the chipsets up to the OTI087 are "Backwards compatible", in fact some early drivers for the OTI087 based chipsets were those made for the 077. --- 31,58 ---- OTI077 Enhanced version of the 067, with support for 1Mbyte and up to 65 ! Mhz dot-clock. This chipset is capable of resolutions up to ! 1024x768x256 colors in Non-Interlaced mode, and up to 1280x1024x16 ! colors Interlaced. OTI087 One of the first VLB chipsets available, it has a 16-bit external ! data path, and a 32-bit internal memory-controller data path. It ! features some acceleration hardware: register-based color expan- ! sion, hardware cursor, a primitive BitBlt engine, a 64 bit graphic ! latch and some other new (on its time) features. Maximum BIOS res- ! olutions are 1024x768x256 Non-Interlaced and 1280x1024x256 inter- ! laced. Maximum Dot-Clock is 80Mhz, but is usually coupled with the ! OTI068 clock generator capable of frequencies up to 78Mhz. This ! chipset supports up to 2MBytes of 70/70R ns DRAM. OTI107 and OTI111 These are new, PCI chipsets by Oak Tech. Inc. Support is not ! included for them, as they are very rare and I haven't had the ! chance to look at one of these boards. We have been unable to ! locate either 107's or 111's (also called "Spitfire 64111"). If ! anybody has such a board and can donate it to XFree86, I would be ! more than glad to add support for them. All the chipsets up to the OTI087 are "Backwards compatible", in fact some early drivers for the OTI087 based chipsets were those made for the 077. *************** *** 56,66 **** only included for 067/077 chipsets. - 2. XF86Config options - - The following options are of particular interest to the Oak driver. Each of - - Information for Oak Technologies Inc. Chipset Users --- 61,66 ---- *************** *** 71,76 **** --- 71,79 ---- + 2. XF86Config options + + The following options are of particular interest to the Oak driver. Each of them must be specified in the 'svga' driver section of the XF86Config file, within the Screen subsections to which they are applicable (you can enable options for all depths by specifying them in the Device section). *************** *** 104,110 **** less 100%, (double BlitStones on xbench). Most OTI087 boards seem to have this feature broken, corrupting text from xterms and leav- ing mouse droppings throughout the screen. As a rule of thumb, ! enable it, if it works badly, disable it ;). Option "clock_50" (OTI087) This one will force the internal speed to 50 Mhz. --- 107,113 ---- less 100%, (double BlitStones on xbench). Most OTI087 boards seem to have this feature broken, corrupting text from xterms and leav- ing mouse droppings throughout the screen. As a rule of thumb, ! enable it, if it works badly, disable it. Option "clock_50" (OTI087) This one will force the internal speed to 50 Mhz. *************** *** 123,130 **** Makes the VLB interface to add one wait state to the first read or write of a given burst. - Option "first_wwait" (OTI087) - Similar to the previous one, this only inserts a wait state in the --- 126,131 ---- *************** *** 132,142 **** - Information for Oak Technologies Inc. Chipset Users first 'write' of a given burst. reads are not affected. This is the default behaviour of the server. --- 133,144 ---- Information for Oak Technologies Inc. Chipset Users + Option "first_wwait" (OTI087) + Similar to the previous one, this only inserts a wait state in the first 'write' of a given burst. reads are not affected. This is the default behaviour of the server. *************** *** 189,196 **** it. The aperture is selected from the VideoRam parameter of the XF86Config or from the amount of memory that is detected if VideoRam is not found. - I hope (because I have not tested it very thoroughly) that linear addressing - will work on ISA boards, VLB ones are fine (I am writing this stuff on mine). --- 191,196 ---- *************** *** 203,217 **** ! GOOD LUCK!!!! ! Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/Oak.sgml,v 3.12 1997/01/25 03:22:02 dawes Exp $ ! $TOG: README.Oak /main/9 1997/07/19 10:27:54 kaleb $ --- 203,218 ---- ! I hope (because I have not tested it very thoroughly) that linear addressing ! will work on all ISA boards, VLB ones work flawlessly. ! Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/Oak.sgml,v 3.12.2.2 1998/02/28 13:29:46 dawes Exp $ ! $TOG: README.Oak /main/10 1998/03/06 16:38:52 kaleb $ *************** *** 264,270 **** - Information for Oak Technologies Inc. Chipset Users --- 265,270 ---- *************** *** 341,347 **** 1. Supported chipsets ...................................................... 1 ! 2. XF86Config options ...................................................... 1 3. Mode issues ............................................................. 3 --- 341,347 ---- 1. Supported chipsets ...................................................... 1 ! 2. XF86Config options ...................................................... 2 3. Mode issues ............................................................. 3 *************** *** 395,398 **** ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/README.Oak,v 3.17 1997/01/27 22:12:44 dawes Exp $ --- 395,398 ---- ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/README.Oak,v 3.17.2.2 1998/02/28 13:31:06 dawes Exp $ *** ./programs/Xserver/hw/xfree86/doc/README.S3@@/PUBLIC-LATEST Sat Jul 19 10:28:06 1997 --- xc/programs/Xserver/hw/xfree86/doc/README.S3 Fri Mar 6 16:37:23 1998 *************** *** 11,17 **** The XFree86 Project Inc. ! 15 January 1996 --- 11,17 ---- The XFree86 Project Inc. ! 27 February 1998 *************** *** 18,26 **** 1. Supported hardware The current S3 Server supports the following S3 chipsets: 911, 924, 801/805, ! 928, 732 (Trio32), 764 (Trio64), 864, 868, 964 and 968. The S3 server will ! also recognise the 866, but it has not been tested with this chipset. If you ! have any problems or success with these, please report it to us. Nevertheless, this is not enough to support every board using one of these chipsets. The following list contains some data points on boards that are known --- 18,27 ---- 1. Supported hardware The current S3 Server supports the following S3 chipsets: 911, 924, 801/805, ! 928, 732 (Trio32), 764, 765, 775, 785 (Trio64*), 864, 868, 964, 968 and M65 ! (Aurora64V+). The S3 server will also recognise the 866, but it has not been ! tested with this chipset. If you have any problems or success with these, ! please report it to us. Nevertheless, this is not enough to support every board using one of these chipsets. The following list contains some data points on boards that are known *************** *** 57,63 **** S3 801/805, AT&T 20C490 RAMDAC, ICD2061A Clockchip - o STB PowerGraph X.24 S3 (ISA) --- 58,63 ---- *************** *** 71,76 **** --- 71,78 ---- + o STB PowerGraph X.24 S3 (ISA) + 8 and 15/16 bpp Note: Real AT&T20C490 RAMDACs should be automatically detected by *************** *** 123,130 **** RAMDAC probe reportedly causes problems with some of these boards, and a RamDac entry should be used to avoid the probe. - Real AT&T 20C490 or 20C491 RAMDACs work with the "dac_8_bit" - option. Some clones (like the Winbond 82C490) do not. --- 125,130 ---- *************** *** 137,142 **** --- 137,145 ---- + Real AT&T 20C490 or 20C491 RAMDACs work with the "dac_8_bit" + option. Some clones (like the Winbond 82C490) do not. + S3 928, Sierra SC15025 RAMDAC, ICD2061A Clockchip o ELSA Winner 1000 ISA/EISA (``TwinBus'', not Winner1000ISA!!) *************** *** 188,194 **** S3 928, Bt485 RAMDAC, ICD2061A Clockchip - o #9 GXE Level 10, 11, 12 --- 191,196 ---- *************** *** 197,206 **** - Information for S3 Chipset Users 8, 15/16 and 24(32) bpp --- 199,209 ---- + Information for S3 Chipset Users + o #9 GXE Level 10, 11, 12 8, 15/16 and 24(32) bpp *************** *** 212,218 **** S3 928, Ti3020 RAMDAC, ICD2061A Clockchip o #9 GXE Level 14, 16 - 8, 15/16 and 24(32) bpp Supports RGB with sync-on-green --- 215,220 ---- *************** *** 255,261 **** Clockchip support is still sometimes flaky and on some machines problems with the first mode after startup of XF86_S3 or after switching back from VT have been seen; switching to next mode with - CTRL+ALT+``KP+'' and back seems to solve this problem. --- 257,262 ---- *************** *** 264,274 **** - Information for S3 Chipset Users Interlaced modes don't work correctly. Mirage P64 with BIOS 4.xx uses the S3 SDAC. --- 265,276 ---- Information for S3 Chipset Users + CTRL+ALT+``KP+'' and back seems to solve this problem. + Interlaced modes don't work correctly. Mirage P64 with BIOS 4.xx uses the S3 SDAC. *************** *** 320,328 **** S3 964, Bt485 RAMDAC, ICD2061A Clockchip - o Diamond Stealth 64 - 8, 15/16, 24(32) bpp --- 322,328 ---- *************** *** 335,340 **** --- 335,344 ---- + o Diamond Stealth 64 + + 8, 15/16, 24(32) bpp + ClockChip "icd2061a" *************** *** 385,393 **** 8/15/16/24 bpp - Note: The Trio64 has a builtin RAMDAC and clockchip, so the server - should work with all Trio64 cards, and there is no need to specify - the RAMDAC or clockchip in the XF86Config file. --- 389,394 ---- *************** *** 396,406 **** - Information for S3 Chipset Users S3 732 (Trio32) o Diamond Stealth 64 DRAM SE --- 397,410 ---- Information for S3 Chipset Users + Note: The Trio64 has a builtin RAMDAC and clockchip, so the server + should work with all Trio64 cards, and there is no need to specify + the RAMDAC or clockchip in the XF86Config file. + S3 732 (Trio32) o Diamond Stealth 64 DRAM SE *************** *** 450,458 **** S3 964, IBM RGB 514/524/525/528 RAMDAC & Clockchip - o Hercules Graphics Terminator 64 - 8/15/16/24 bpp --- 454,460 ---- *************** *** 461,471 **** - Information for S3 Chipset Users s3RefClk 50 DACspeed 170 --- 463,475 ---- + Information for S3 Chipset Users + o Hercules Graphics Terminator 64 + 8/15/16/24 bpp s3RefClk 50 DACspeed 170 *************** *** 516,525 **** in each Display subsection. - o MIRO 80SV - s3RefClk 16 - DACspeed 250 --- 520,526 ---- *************** *** 528,538 **** - Information for S3 Chipset Users 8/15/16/24 bpp ELSA Winner 2000PRO/X-8 (S3 968, 8MB VRAM, 220MHz for 32bpp) --- 529,544 ---- Information for S3 Chipset Users + o MIRO 80SV + + s3RefClk 16 + DACspeed 250 + + 8/15/16/24 bpp ELSA Winner 2000PRO/X-8 (S3 968, 8MB VRAM, 220MHz for 32bpp) *************** *** 580,591 **** o Full server startup output. - 2. 16bpp and 32bpp - On 801/805 + AT&T490 Cards (like the Fahrenheit 1280+ VLB) only 15 and 16bpp - are supported. 32bpp isn't available on this type of card. (There is a 24 bit - mode under MS Windows, but it's not a 32bpp sparse mode but a real 3 - bytes/pixel mode). --- 586,592 ---- *************** *** 594,604 **** - Information for S3 Chipset Users 3. List of Supported Clock Chips ICD2061A ==> ClockChip "icd2061a" --- 595,612 ---- Information for S3 Chipset Users + 2. 16bpp and 32bpp + + On 801/805 + AT&T490 Cards (like the Fahrenheit 1280+ VLB) only 15 and 16bpp + are supported. 32bpp isn't available on this type of card. (There is a 24 bit + mode under MS Windows, but it's not a 32bpp sparse mode but a real 3 + bytes/pixel mode). + + 3. List of Supported Clock Chips ICD2061A ==> ClockChip "icd2061a" *************** *** 653,666 **** - - - - - - - - Information for S3 Chipset Users --- 661,666 ---- *************** *** 870,877 **** probing fails! ! 7. How to avoid ``snowing'' display while performing graphics operations For cards with the S3 Vision864 chip, there is an automatic correction which depends on the pixel clock and the memory clock MCLK at which the S3 chip oper- ates. For most clock chips this value can't be read (only the S3 SDAC allows --- 870,914 ---- probing fails! ! 7. Hints for LCD configuration (S3 Aurora64V+) + If LCD is active the CRT will always output 1024x768 (or whatever is the _phys- + ical_ LCD size) and smaller modes are zoomed to fit on the LCD unless you spec- + ify Option "lcd_center" in the device section. + + The pixel clock for this physical size (e.g. 1024x768) mode... + + o ...can explicitly set in the config file (device section) with e.g. + `Set_LCDClk 70' (resulting 70 MHz pixel clock being used for all modes + when LCD is on) + + o ...is taken from the _first_ mode in the modes line iff this mode's dis- + play size is the same as the physical LCD size + + o ...the default LCD pixel clock of BIOS initialisation setup is used. This + value is output at server startup in the line `LCD size ...' unless you're + specifying a value using `Set_LCDClk ...' + + If LCD is _not_ active, the normal mode lines and pixel clocks are used for the + VGA output. + + Whenever you switch output sources with Fn-F5, the Xserver won't get informed + and pixel clock and other settings are wrong. Because of this you have to + switch modes _after_ switch output sources! Then the server will check which + outputs are active and select the correct clocks etc. So the recommended key + sequence to switch output is + + Fn-F5 Ctrl-Alt-Plus Ctrl-Alt-Minus + + and everything should be ok.. + + on the Toshiba keypad you can first hold down Ctrl-Alt, then press `Fn' addi- + tionally before pressing Plus/Minus too to avoid to explicitly enable/disable + the numeric keypad for mode switching. + + + 8. How to avoid ``snowing'' display while performing graphics operations + For cards with the S3 Vision864 chip, there is an automatic correction which depends on the pixel clock and the memory clock MCLK at which the S3 chip oper- ates. For most clock chips this value can't be read (only the S3 SDAC allows *************** *** 880,885 **** --- 917,934 ---- With the new `s3MCLK' entry for your XF86Config file, now you can specify e.g. + + + + + + + + + Information for S3 Chipset Users + + + s3MCLK 55 *************** *** 925,930 **** --- 974,996 ---- + + + + + + + + + + + + + + + + + Information for S3 Chipset Users *************** *** 966,978 **** exit - Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/S3.sgml,v 3.37.2.1 1997/05/27 06:22:23 dawes Exp $ ! $TOG: README.S3 /main/17 1997/07/19 10:28:08 kaleb $ --- 1032,1056 ---- exit + 9. New S3 SVGA driver + There is a new experimental S3 driver for non-ViRGE S3 chipsets in the + XF86_SVGA server. This is definitely an ALPHA quality driver and hasn't been + well tested, and has some known problems. Because of this, the configuration + programs will install XF86_S3 by default rather than this one. But if you're + adventurous or had some problems with XF86_S3, you might want to give it a try. + The driver includes generic S3 support which should work on all non-ViRGE S3 + chips (in theory, that is). It also has improved support for chips that sup- + port S3's new style memory mapped I/O. These chips include the 868, 968 and + recent Trio64 variants (not the plain old Trio64s). Chips that are capable of + using the new style MMIO will use it automatically. The option "NO_MMIO" can + be used to turn this off. + Performance for chips using the new style MMIO is expected to be better than ! $TOG: README.S3 /main/18 1998/03/06 16:39:01 kaleb $ *************** *** 980,996 **** --- 1058,1129 ---- + Information for S3 Chipset Users + XF86_S3, especially on a PCI bus. Performance without MMIO, however, is + expected to be roughly comparable to XF86_S3 (faster in some areas, slower in + others). + All color depths achievable with XF86_S3 should be possible with these drivers. + Additionally, packed 24 bpp "sort of" works for the 868 and 968. Your results + may vary. + Nearly all the options and features supported by XF86_S3 are supported by this + driver. Additionally, the standard XAA/SVGA server options such as NO_ACCEL, + SW_CURSOR, and NO_PIXMAP_CACHE are also supported. XF86_S3 features which are + NOT supported in this driver are DPMS support and gamma correction. + The driver supports the PCI_RETRY option when using MMIO and a PCI card. This + option can give large performance boosts for some operations, but has a ten- + dency to hog the bus. Because of this, the option is not set by default. Most + hardware combinations may not have any problems using this option, but sound + card glitches during intensive graphics operations have been reported on some. + One shortcoming worth noting is that this driver does not yet contain the work- + around for some S3 PCI BIOSs that report their memory usage incorrectly. This + can result in conflicting address spaces. If this is the case on your hardware + you should run XF86_S3 once and write down the address that your card is relo- + cated to (as printed out in the server output). Then you can force the server + to use this address with the MemBase field in the XF86Config (see the man page + on XF86Config). + Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/S3.sgml,v 3.37.2.4 1998/02/27 02:34:38 dawes Exp $ + + + $TOG: README.S3 /main/18 1998/03/06 16:39:01 kaleb $ + + + + + + + + + + + + + + + + + + + + + + + + + + + + Information for S3 Chipset Users *************** *** 1067,1073 **** 1. Supported hardware ....................................................... 1 ! 2. 16bpp and 32bpp .......................................................... 9 3. List of Supported Clock Chips ........................................... 10 --- 1200,1206 ---- 1. Supported hardware ....................................................... 1 ! 2. 16bpp and 32bpp ......................................................... 10 3. List of Supported Clock Chips ........................................... 10 *************** *** 1077,1085 **** 6. Reference clock value for IBM RGB 5xx RAMDACs .......................... 13 ! 7. How to avoid ``snowing'' display while performing graphics operations ... 14 --- 1210,1220 ---- 6. Reference clock value for IBM RGB 5xx RAMDACs .......................... 13 ! 7. Hints for LCD configuration (S3 Aurora64V+) ............................. 14 + 8. How to avoid ``snowing'' display while performing graphics operations ... 14 + 9. New S3 SVGA driver ...................................................... 16 *************** *** 1115,1124 **** - - i ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/README.S3,v 3.51.2.1 1997/05/27 06:26:58 dawes Exp $ --- 1250,1257 ---- i ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/README.S3,v 3.51.2.3 1998/02/27 02:55:01 dawes Exp $ *** ./programs/Xserver/hw/xfree86/doc/README.S3V@@/PUBLIC-LATEST Sat Jul 19 10:28:13 1997 --- xc/programs/Xserver/hw/xfree86/doc/README.S3V Fri Mar 6 16:37:29 1998 *************** *** 7,39 **** ! Information for S3 ViRGE, ViRGE/DX, ViRGE/GX and ViRGE/VX Users The XFree86 Project Inc. ! 1 June 1997 1. Supported hardware ! With release 3.3 of XFree86, there are now two servers which support the ViRGE ! family of chips. The XF86_S3V server (also available in 3.2A) is a dedicated ! server which supports the S3 ViRGE (86C325), the ViRGE/DX (86C375), ViRGE/GX ! (86C385) and the ViRGE/VX (86C988) chips. New with this release, the above ! ViRGE chipsets are also supported in the XF86_SVGA server, which includes a new ! ViRGE driver making use of the XAA acceleration architecture. 2. XF86_S3V server ! The S3V server has many enhancements and bug fixes since 3.2A. With the release ! of 3.3 you should find that the ViRGE server is stable at all depths. Sup- ! ported for 24bpp has been enhanced. The server now supports 1 and 32 bpp ! pixmap formats (3.2A supported 1 and 24bpp pixmaps). This fixes known problems ! with xanim and Netscape clients in 3.2A. It has been tested with ViRGE cards ! with 2 and 4MB DRAM, ViRGE/DX 4M, ViRGE/VX 8M (4M VRAM/4M DRAM), and with a ! 220MHz ViRGE/VX card with 2MB VRAM up to 1600x1200 with 8/15/16bpp. NOTE: This driver is pretty new, and not everything might work like you expect it to. It shouldn't crash your machine, but you may have video artifacts or --- 7,45 ---- ! Information for S3 ViRGE, ViRGE/DX, ViRGE/GX, ViRGE/GX2, ViRGE/MX and ViRGE/VX ! Users The XFree86 Project Inc. ! 1 March 1998 1. Supported hardware ! With release 3.3.2 of XFree86, there are now two servers which support the ! ViRGE family of chips. The XF86_S3V server is a dedicated server which supports ! the S3 ViRGE (86C325), the ViRGE/DX (86C375), ViRGE/GX (86C385) and the ! ViRGE/VX (86C988) chips. New with this release, the above ViRGE chipsets are ! also supported in the XF86_SVGA server, which includes a new ViRGE driver mak- ! ing use of the XAA acceleration architecture and also supports ViRGE/GX2 ! (86C357) and ViRGE/MX (86C260) chips now. + The following sections describe details of ViRGE support. Be aware that there + are two servers described. XF86_S3V is the ViRGE specific server and was cre- + ated first. The new acceleration architecture support is found in the + XF86_SVGA server using the s3_virge driver. Each has strengths and weaknesses. + 2. XF86_S3V server ! The S3V server has some minor fixes since 3.3.1. You should find that the ! ViRGE server is stable at all depths. The server supports 1 and 32 bpp pixmap ! formats. This fixes known problems with xanim and Netscape clients in early ! versions of the S3V server. It has been tested with ViRGE cards with 2 and 4MB ! DRAM, ViRGE/DX 4M, ViRGE/VX 8M (4M VRAM/4M DRAM), and with a 220MHz ViRGE/VX ! card with 2MB VRAM up to 1600x1200 with 8/15/16bpp. NOTE: This driver is pretty new, and not everything might work like you expect it to. It shouldn't crash your machine, but you may have video artifacts or *************** *** 53,75 **** o it should be possible to use pixel depths of 8, 15, 16, 24, and 32 bits per pixel. - o 32 bpp is implemented as translation to 24 bpp - 2.2 Known limitations ! o No support for external RAMDACs on the ViRGE/VX. - Information for S3 ViRGE, ViRGE/DX, ViRGE/GX and ViRGE/VX Users ! Information for S3 ViRGE, ViRGE/DX, ViRGE/GX and ViRGE/VX Users o No support for VLB cards. --- 59,81 ---- o it should be possible to use pixel depths of 8, 15, 16, 24, and 32 bits per pixel. ! Information for S3 ViRGE, ViRGE/DX, ViRGE/GX, ViRGE/GX2, ViRGE/MX and ViRGE/VX Users + Information for S3 ViRGE, ViRGE/DX, ViRGE/GX, ViRGE/GX2, ViRGE/MX and ViRGE/VX Users ! o 32 bpp is implemented as translation to 24 bpp + 2.2 Known limitations + o No support for external RAMDACs on the ViRGE/VX. o No support for VLB cards. *************** *** 109,130 **** chipset. It uses the XAA acceleration architecture for acceleration, and allows color depths of 8, 15, 16, 24 and 32 bpp. It has been tested on several 2MB and 4MB ViRGE cards, a 4MB ViRGE/DX card and a ViRGE/VX card. Resolutions ! of up to 1600x1200 have been achieved. As this is the first release of this ! driver, not everything may work as expected. Please report any problems to XFree86@Xfree86.org using the appropriate bug report sheet. 3.1 Features ! o Supports PCI hardware, ViRGE, ViRGE/DX, ViRGE/GX and ViRGE/VX. - o Supports 8bpp, 15/16bpp, 24bpp and 32bpp. - o VT switching seems to work well, no corruption reported at all color - depths. - o Acceleration is pretty complete: Screen-to-screen copy, solid rectangle - fills, CPU-to-screen color expansion, 8x8 pattern mono and color fills. - Currently, the color expansion appears to be substantially faster than the --- 115,131 ---- chipset. It uses the XAA acceleration architecture for acceleration, and allows color depths of 8, 15, 16, 24 and 32 bpp. It has been tested on several 2MB and 4MB ViRGE cards, a 4MB ViRGE/DX card and a ViRGE/VX card. Resolutions ! of up to 1600x1200 have been achieved. This is an early release of this driver, ! and not everything may work as expected. Please report any problems to XFree86@Xfree86.org using the appropriate bug report sheet. 3.1 Features ! o Supports PCI hardware, ViRGE, ViRGE/DX, ViRGE/GX, ViRGE/GX2, ViRGE/MX and ! ViRGE/VX. *************** *** 132,142 **** - Information for S3 ViRGE, ViRGE/DX, ViRGE/GX and ViRGE/VX Users accel server due to the optimized XAA routines. o Acceleration at 32bpp is limited: only ScreenToScreen bitblit and solid --- 133,150 ---- + Information for S3 ViRGE, ViRGE/DX, ViRGE/GX, ViRGE/GX2, ViRGE/MX and ViRGE/VX Users + o Supports 8bpp, 15/16bpp, 24bpp and 32bpp. + o VT switching seems to work well, no corruption reported at all color + depths. + + o Acceleration is pretty complete: Screen-to-screen copy, solid rectangle + fills, CPU-to-screen color expansion, 8x8 pattern mono and color fills. + Currently, the color expansion appears to be substantially faster than the accel server due to the optimized XAA routines. o Acceleration at 32bpp is limited: only ScreenToScreen bitblit and solid *************** *** 183,196 **** and XFree86 does not encourage exceeding those specs. *** Note: This option should not be preceded by the "Option" keyword! - Acceleration and graphic engine: - o "noaccel" turns off all acceleration - o "fifo_aggressive", "fifo_moderate" and "fifo_conservative" alter the set- - tings for the threshold at which the pixel FIFO takes over the internal - memory bus to refill itself. The smaller this threshold, the better the - acceleration performance of the card. You may try the fastest setting --- 191,198 ---- *************** *** 197,208 **** - Information for S3 ViRGE, ViRGE/DX, ViRGE/GX and ViRGE/VX Users ("aggressive") and move down if you encounter pixel corruption. The opti- mal setting will probably depend on dot-clock and on color depth. Note that specifying any of these options will also alter other memory settings --- 199,216 ---- + Information for S3 ViRGE, ViRGE/DX, ViRGE/GX, ViRGE/GX2, ViRGE/MX and ViRGE/VX Users + Acceleration and graphic engine: + o "noaccel" turns off all acceleration + o "fifo_aggressive", "fifo_moderate" and "fifo_conservative" alter the set- + tings for the threshold at which the pixel FIFO takes over the internal + memory bus to refill itself. The smaller this threshold, the better the + acceleration performance of the card. You may try the fastest setting ("aggressive") and move down if you encounter pixel corruption. The opti- mal setting will probably depend on dot-clock and on color depth. Note that specifying any of these options will also alter other memory settings *************** *** 239,245 **** --- 247,303 ---- o Both 24bpp and 32bpp do not support interlace modes. + o 32bpp is limited to a width of < 1024 pixels. (1024x768 is not possible, + even if you have the memory.) This is a hardware limit of ViRGE chips. + 3.4 Hints for LCD configuration (S3 ViRGE/MX) + + If LCD is active the CRT will always output 1024x768 (or whatever is the _phys- + ical_ LCD size) and smaller modes are zoomed to fit on the LCD unless you spec- + ify Option "lcd_center" in the device section. + + The pixel clock for this physical size (e.g. 1024x768) mode... + + + + + + + + + Information for S3 ViRGE, ViRGE/DX, ViRGE/GX, ViRGE/GX2, ViRGE/MX and ViRGE/VX Users + + + + o ...can explicitly set in the config file (device section) with e.g. + `Set_LCDClk 70' (resulting 70 MHz pixel clock being used for all modes + when LCD is on) + + o ...is taken from the _first_ mode in the modes line iff this mode's dis- + play size is the same as the physical LCD size + + o ...the default LCD pixel clock of BIOS initialisation setup is used. This + value is output at server startup in the line `LCD size ...' unless you're + specifying a value using `Set_LCDClk ...' + + If LCD is _not_ active, the normal mode lines and pixel clocks are used for the + VGA output. + + Whenever you switch output sources with Fn-F5 or similar, the Xserver won't get + informed and pixel clock and other settings are wrong. Because of this you + have to switch modes _after_ switch output sources! Then the server will check + which outputs are active and select the correct clocks etc. So the recommended + key sequence to switch output is + + Fn-F5 Ctrl-Alt-Plus Ctrl-Alt-Minus + + and everything should be ok.. + + on the Toshiba keypad you can first hold down Ctrl-Alt, then press `Fn' addi- + tionally before pressing Plus/Minus too to avoid to explicitly enable/disable + the numeric keypad for mode switching. + + 4. Authors 4.1 XF86_S3V server *************** *** 248,254 **** and: ! o Kevin Brosius 70247.1640@compuserve.com o Berry Dijk berry_dijk@tasking.nl --- 306,312 ---- and: ! o Kevin Brosius Cobra@compuserve.com o Berry Dijk berry_dijk@tasking.nl *************** *** 256,264 **** --- 314,326 ---- o Huver Hu huver@amgraf.com + o Dirk Vangestel gesteld@sh.bel.alcatel.be + 4.2 XF86_SVGA ViRGE driver + Sebastien Marineau + and: *************** *** 265,286 **** - Information for S3 ViRGE, ViRGE/DX, ViRGE/GX and ViRGE/VX Users - o Dirk Vangestel gesteld@sh.bel.alcatel.be ! 4.2 XF86_SVGA ViRGE driver - Sebastien Marineau - and: ! Harald Koenig ! Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/S3V.sgml,v 3.3.2.5 1997/06/02 01:44:14 dawes Exp $ --- 327,345 ---- ! Information for S3 ViRGE, ViRGE/DX, ViRGE/GX, ViRGE/GX2, ViRGE/MX and ViRGE/VX Users ! o Harald Koenig ! o Kevin Brosius Cobra@compuserve.com + Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/S3V.sgml,v 3.3.2.8 1998/02/27 04:53:51 dawes Exp $ *************** *** 331,337 **** - Information for S3 ViRGE, ViRGE/DX, ViRGE/GX and ViRGE/VX Users --- 390,395 ---- *************** *** 339,344 **** --- 397,403 ---- + Information for S3 ViRGE, ViRGE/DX, ViRGE/GX, ViRGE/GX2, ViRGE/MX and ViRGE/VX Users *************** *** 401,406 **** --- 460,472 ---- + + + + + + + CONTENTS *************** *** 409,415 **** 2. XF86_S3V server .......................................................... 1 2.1 Features: ............................................................ 1 ! 2.2 Known limitations .................................................... 1 2.3 Future Features (in order from highest to lowest priority) ........... 2 2.4 Configuration: ....................................................... 2 --- 475,481 ---- 2. XF86_S3V server .......................................................... 1 2.1 Features: ............................................................ 1 ! 2.2 Known limitations .................................................... 2 2.3 Future Features (in order from highest to lowest priority) ........... 2 2.4 Configuration: ....................................................... 2 *************** *** 417,425 **** 3.1 Features ............................................................. 2 3.2 Known limitations .................................................... 3 3.3 Configuration ........................................................ 3 ! 4. Authors .................................................................. 4 ! 4.1 XF86_S3V server ...................................................... 4 4.2 XF86_SVGA ViRGE driver ............................................... 5 --- 483,492 ---- 3.1 Features ............................................................. 2 3.2 Known limitations .................................................... 3 3.3 Configuration ........................................................ 3 + 3.4 Hints for LCD configuration (S3 ViRGE/MX) ............................ 4 ! 4. Authors .................................................................. 5 ! 4.1 XF86_S3V server ...................................................... 5 4.2 XF86_SVGA ViRGE driver ............................................... 5 *************** *** 456,464 **** - i ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/README.S3V,v 3.5.2.5 1997/06/02 01:46:14 dawes Exp $ --- 523,530 ---- i ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/README.S3V,v 3.5.2.7 1998/02/27 05:00:05 dawes Exp $ *** ./programs/Xserver/hw/xfree86/doc/README.SOLX86@@/PUBLIC-LATEST Sat Jul 19 10:28:25 1997 --- xc/programs/Xserver/hw/xfree86/doc/README.SOLX86 Fri Mar 6 16:37:33 1998 *************** *** 11,27 **** David Holland ! 16 May 1997 ! 1. What is XFree86 3.3 ! XFree86 3.3 is a port of X11R6.3 that supports several versions of Intel-based ! Unix. It is derived from X386 1.2 which was the X server distributed with ! X11R5. This release consists of many new features and performance improvements ! as well as many bug fixes. The release is available as source patches against ! the X Consortium code, as well as binary distributions for many architectures. The sources for XFree86 are available by anonymous ftp from: --- 11,28 ---- David Holland ! 25 Feb 1998 ! 1. What is XFree86 3.3.2 ! XFree86 3.3.2 is a port of X11R6.3 that supports several versions of Intel- ! based Unix. It is derived from X386 1.2 which was the X server distributed ! with X11R5. This release consists of many new features and performance ! improvements as well as many bug fixes. The release is available as source ! patches against the X Consortium code, as well as binary distributions for many ! architectures. The sources for XFree86 are available by anonymous ftp from: *************** *** 33,46 **** ftp://ftp.XFree86.org/pub/XFree86/current/binaries/Solaris ! 2. Solaris for x86, versions on which XFree86 3.3 has been tested ! XFree86 3.3 has been actively tested on: o Solaris 2.4 for x86 FCS o Solaris 2.5.1 for x86 And is expected to run under: o Solaris 2.4 EA2 for x86 --- 34,49 ---- ftp://ftp.XFree86.org/pub/XFree86/current/binaries/Solaris ! 2. Solaris for x86, versions on which XFree86 3.3.2 has been tested ! XFree86 3.3.2 has been actively tested on: o Solaris 2.4 for x86 FCS o Solaris 2.5.1 for x86 + o Solaris 2.6 for x86 + And is expected to run under: o Solaris 2.4 EA2 for x86 *************** *** 56,66 **** The virtual terminals of Solaris work basically the same way as most other Intel based SVR4 VT sub-systems. However, there are a number of limitations - documented below. - First, if you are running a Solaris 2.4 x86 system, and you want VT's, you will - Information for Solaris for x86 Users --- 59,66 ---- *************** *** 71,76 **** --- 71,79 ---- + documented below. + + First, if you are running a Solaris 2.4 x86 system, and you want VT's, you will have to create the necessary devices first, so become root. First verify the chanmux device driver's major number is 100: *************** *** 130,138 **** - - - Information for Solaris for x86 Users --- 133,138 ---- *************** *** 168,174 **** ~xc/config/cf/xf86site.def. ! 2. Both Gcc, and ProWorks are supported by XFree86. Gcc-2.5.8 or gcc-2.7.2 are suggested, Gcc-2.6.0 is known not to work. You also need to set Has- Gcc2 correctly in ~xc/config/cf/xf86site.def. --- 168,174 ---- ~xc/config/cf/xf86site.def. ! 2. Both Gcc, and ProWorks are supported by XFree86. Gcc-2.5.8 or gcc-2.7.2.3 are suggested, Gcc-2.6.0 is known not to work. You also need to set Has- Gcc2 correctly in ~xc/config/cf/xf86site.def. *************** *** 187,193 **** GNU binutils. Don't install gas or ld from GNU binutils, use the one pro- vided by Sun. ! With XFree86 3.3, you will need to setup a /opt/SUNWspro/bin directory containing symbolic links named cc, CC, and c++filt pointing respectively to the actual gcc, g++ and c++filt commands. --- 187,193 ---- GNU binutils. Don't install gas or ld from GNU binutils, use the one pro- vided by Sun. ! With XFree86 3.3.2, you will need to setup a /opt/SUNWspro/bin directory containing symbolic links named cc, CC, and c++filt pointing respectively to the actual gcc, g++ and c++filt commands. *************** *** 228,234 **** to enable the aperture driver. ! Under Solaris 2.5 and 2.5.1, there's a system driver (/dev/xsvc that pro- vides this functionality. It will be detected automatically by the server, so you don't need to install the driver. --- 228,234 ---- to enable the aperture driver. ! Under Solaris 2.5 and later, there's a system driver (/dev/xsvc that pro- vides this functionality. It will be detected automatically by the server, so you don't need to install the driver. *************** *** 305,317 **** dows.x.i386unix newsgroup. Questions or comments about the Solaris support, or the Solaris distribution need to be made to davidh@use.com, or danson@lgc.com. ! Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/SOLX86.sgml,v 3.12.2.4 1997/05/24 08:36:08 dawes Exp $ ! $TOG: README.SOLX86 /main/11 1997/07/19 10:28:27 kaleb $ --- 305,317 ---- dows.x.i386unix newsgroup. Questions or comments about the Solaris support, or the Solaris distribution need to be made to davidh@use.com, or danson@lgc.com. ! Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/SOLX86.sgml,v 3.12.2.6 1998/02/28 04:47:09 dawes Exp $ ! $TOG: README.SOLX86 /main/12 1998/03/06 16:39:11 kaleb $ *************** *** 405,413 **** ! 1. What is XFree86 3.3 ...................................................... 1 ! 2. Solaris for x86, versions on which XFree86 3.3 has been tested ........... 1 3. The VT-switching sub-system in Solaris x86 ............................... 1 --- 405,413 ---- ! 1. What is XFree86 3.3.2 .................................................... 1 ! 2. Solaris for x86, versions on which XFree86 3.3.2 has been tested ......... 1 3. The VT-switching sub-system in Solaris x86 ............................... 1 *************** *** 461,464 **** ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/README.SOLX86,v 3.20.2.4 1997/05/24 09:12:07 dawes Exp $ --- 461,464 ---- ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/README.SOLX86,v 3.20.2.6 1998/02/28 13:05:35 dawes Exp $ *** ./programs/Xserver/hw/xfree86/doc/README.SVR4@@/PUBLIC-LATEST Sat Jul 19 10:28:32 1997 --- xc/programs/Xserver/hw/xfree86/doc/README.SVR4 Fri Mar 6 16:37:38 1998 *************** *** 11,17 **** The XFree86 Project, Inc ! 1 June 1997 --- 11,17 ---- The XFree86 Project, Inc ! 27 Feb 1998 *************** *** 51,57 **** o Consensys ! o Novell UnixWare 1.x and 2.0 Basically, we believe that XFree86 binaries will run unmodified on any ISA, EISA, or MCA platform version version of SVR4.0 (Solaris 2.x is an exception), --- 51,57 ---- o Consensys ! o Novell/SCO UnixWare 1.x and 2.0 Basically, we believe that XFree86 binaries will run unmodified on any ISA, EISA, or MCA platform version version of SVR4.0 (Solaris 2.x is an exception), *************** *** 501,517 **** Some accelerated drivers may cause the machine to lockup when starting up the server on some versions of SVR4.0. The problem seems to be related to the ker- nel checking for the presence of physical memory when mmaping /dev/pmem. This ! can cause problems when mapping memory mapped registers. This is known to be a ! problem with the MGA driver in the SVGA server. Some other drivers may be ! affected too. We currently have no workaround for this. ! Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/SVR4.sgml,v 3.13.2.1 1997/06/01 12:33:36 dawes Exp $ ! $TOG: README.SVR4 /main/13 1997/07/19 10:28:34 kaleb $ --- 501,517 ---- Some accelerated drivers may cause the machine to lockup when starting up the server on some versions of SVR4.0. The problem seems to be related to the ker- nel checking for the presence of physical memory when mmaping /dev/pmem. This ! can cause problems when mapping memory mapped registers. This was known to be ! a problem with the MGA driver in the SVGA server. Some other drivers may be ! affected too. The problem with the MGA driver is now fixed. ! Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/SVR4.sgml,v 3.13.2.3 1998/02/28 08:54:11 dawes Exp $ ! $TOG: README.SVR4 /main/14 1998/03/06 16:39:15 kaleb $ *************** *** 659,662 **** ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/README.SVR4,v 3.22.2.1 1997/06/01 12:41:31 dawes Exp $ --- 659,662 ---- ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/README.SVR4,v 3.22.2.2 1998/02/28 13:05:35 dawes Exp $ *** /dev/null Tue Jun 30 11:46:26 1998 --- xc/programs/Xserver/hw/xfree86/doc/README.apm Fri Mar 6 16:37:47 1998 *************** *** 0 **** --- 1,271 ---- + + + + + + + + + + Information for Alliance Promotion chipset users + + Henrik Harmsen (Henrik.Harmsen@erv.ericsson.se) + + 23 February 1998 + + + + 1. Support chipsets + + The apm driver in the SVGA server is for Alliance Promotion (www.alsc.com) + graphics chipsets. The following chipsets are supported: + + o 6422 + + Old chipset without color expansion hardware (text accel). + + o AT24 + + As found in Diamond Stealth Video 2500. Quite similar to AT3D. + + o AT25, AT3D + + AT3D is found in Hercules Stingray 128/3D. Most other Voodoo Rush based + cards use the AT25 which is identical except it doesn't have the 3D stuff + in it. + + + 2. Acceleration + + The apm driver uses the XAA (XFree86 Acceleration Architecture) in the SVGA + server. It has support for the following acceleration: + + o Bitblts (rectangle copy operation) + + o Lines (solid, single pixel) + + o Filled rectangles + + o CPU->Screen colour expansion (text accel). Not for 6422. + + o Hardware cursor + + All in 8, 16 and 32 bpp modes. No 24bpp mode is supported. Also VESA DPMS + power save mode is fully supported with "standby", "suspend" and "off" modes + (set with with the "xset dpms" command). + + + 3. Configuration + + First: Please run the XF86Setup program to create a correct configuration. + + + + Information for Alliance Promotion chipset users + + + + + + Information for Alliance Promotion chipset users + + + + You can turn off hardware cursor by inserting the following line in the Device + section of the XF86Config file: + + Option "sw_cursor" + + Or turn off hardware acceleration: + + Option "noaccel" + + Please don't specify the amount of video RAM you have or which chipset you have + in the config file, let the driver probe for this. Also please don't put any + "clocks" line in the device section since these chips have a fully programmable + clock that can take (almost) any modeline you throw at it. It might fail at + some specific clock values but you should just try a slightly different clock + and it should work. + + Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/apm.sgml,v 1.1.2.2 1998/02/25 12:20:30 dawes Exp $ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Information for Alliance Promotion chipset users + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CONTENTS + + + + 1. Support chipsets ......................................................... 1 + + 2. Acceleration ............................................................. 1 + + 3. Configuration ............................................................ 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + i + + + + $XFree86: xc/programs/Xserver/hw/xfree86/doc/README.apm,v 1.1.2.2 1998/02/27 02:55:02 dawes Exp $ + + + + + $TOG: README.apm /main/1 1998/03/06 16:39:25 kaleb $ *** ./programs/Xserver/hw/xfree86/doc/README.ati@@/PUBLIC-LATEST Sat Jul 19 10:29:14 1997 --- xc/programs/Xserver/hw/xfree86/doc/README.ati Fri Mar 6 16:37:51 1998 *************** *** 7,142 **** ! ATI adapters README Marc Aurele La France ! 23 March 1996 Abstract ! This is the README for the XFree86 ATI VGA driver used in the ! XF86_Mono, XF86_VGA16 and XF86_SVGA servers. Users of ATI adapters ! based on the Mach8, Mach32 or Mach64 (including 3D Rage and 3D Rage ! II) accelerators should be using the accelerated servers (XF86_Mach8, ! XF86_Mach32 or XF86_Mach64). The unaccelerated servers (XF86_Mono, ! XF86_VGA16 and XF86_SVGA) should still work, but are a waste of capa- ! bilities. ! 1. What is the ATI VGA driver? ! The ATI VGA driver is a 256-colour, 16-colour and monochrome driver for ! XFree86. The driver is intended for all ATI video adapters except those that ! do not provide SuperVGA functionality (such as some early Mach8 and Mach32 ! adapters). The following approximate maximum resolutions (based on the Golden ! Ratio of x/y = (1 + sqrt(5))/2) are possible depending on the video memory ! available on the adapter (and the capabilities of your monitor): ! 256k 640x409x256 896x585x16 ! 512k 896x585x256 1280x819x16 ! 1M 1280x819x256 1824x1149x16 ! Maximum monochrome resolutions are the same as those for 16-colour mode, ! because the monochrome server uses a maximum of one fourth of the available ! video memory. ! 2. What is the ATI VGA driver *not*? ! This driver does not yet support more than 8 bits of pixel depth. Even if your ! manual says that your graphics adapter supports modes using more than 256 ! colours, the ATI VGA driver will not use these modes. ! The ATI VGA driver is not an accelerated driver. If your adapter is based on ! the Mach8, Mach32 or Mach64 video controllers, this driver will not use the ! accelerated functions of the hardware. It will only use the VGA hardware ! (which, for Mach32's and Mach64's, is integrated into the accelerator). This ! can make opaque moves, for example, quite jerky. - ATI adapters README - ATI adapters README - 3. What video adapters will the driver work with? ! Most adapters harbouring the following ATI video controller chips will work ! with this driver: ! VGA Wonder series: 18800, 18800-1, 28800-2, 28800-4, 28800-5, 28800-6 ! Mach32 series: 68800-3, 68800-6, 68800AX, 68800LX ! Mach64 series: 88800GX-C, 88800GX-D, 88800GX-E, 88800GX-F, 88800CX, ! 264CT, 264ET, 264VT, 264VT2, 264GT - The 264xT series are integrated controllers, meaning that they include an - internal RAMDAC and clock generator. Some early Mach32 adapters will not work - with this driver because they do not provide VGA functionality. Also, early - Mach8 adapters will not work for the same reason, unless the adapter also has a - video controller from the VGA Wonder series (or is connected to one through the - VGA passthrough connector). These adapters are available with a variety of clock generators and RAMDACs. ! See the XF86Config section below for details. These adapters are available ! with or without a mouse. ! VGA Wonder V3 adapters use a 18800 video controller and generate dot clocks ! with crystals. VGA Wonder V4 adapters have a 18800-1 and also use crystals. ! VGA Wonder V5 adapters also use a 18800-1, but have a 18810 clock generator. ! VGA Wonder+ adapters use a 28800-2 and a 18810. Other than these, ATI's ! adapter naming convention (if it can be said that one exists) starts to fall ! apart. ! The VGA Wonder series was also available through ATI's OEM channel under the ! name VGA1024. Thus, the ATI VGA driver also supports VGA1024, VGA1024D, ! VGA1024XL, VGA1024DXL and VGA1024VLB adapters, among others. ! 4. What should I put in my XF86Config file? ! The chipset will be automatically detected. The chipset name for this driver ! is "ati". The driver also recognizes "vgawonder", "mach8", "mach32" and ! "mach64" as chipset names. In this version of the driver, all names are equiv- ! alent. In some future version each name will have a different meaning to be ! documented at that time. ! The clocks line to be specified in your XF86Config depends on what the adapter ! uses to generate dot clocks. - For all adapters, one of the following clocks specifications (or an initial - subset thereof) can be used depending on what the adapter uses to generate dot - clocks: - Crystals (VGA Wonder V3 and V4 adapters only): - Clocks 50.000 56.644 0.000 44.900 44.900 50.000 0.000 36.000 - 25.000 28.322 0.000 22.450 22.450 25.000 0.000 18.000 - 16.667 18.881 0.000 14.967 14.967 16.667 0.000 12.000 ! ATI adapters README 12.500 14.161 0.000 11.225 11.225 12.500 0.000 9.000 --- 7,356 ---- ! ATI Adapters README file Marc Aurele La France ! 1998 January 28 Abstract ! This is the README for the XFree86 ATI driver included in this ! release. ! 1. Statement of intent ! Generally speaking, the driver is intended for all ATI video adapters, provid- ! ing maximum video function within hardware limitations. The driver is also ! intended to optionally provide the same level of support for generic VGA or ! 8514/A adapters. This driver is still being actively developed, meaning that ! it currently does not yet fully meet these goals. ! The driver will provide + o accelerated support if an ATI accelerator is detected and the user has not + requested that this support be disabled; otherwise ! o accelerated support if a non-ATI 8514/A-capable adapter is detected and ! the user has requested such support; otherwise + o unaccelerated SuperVGA support if an ATI VGA-capable adapter is detected; + otherwise ! o generic VGA support if a non-ATI VGA-capable adapter is detected and the ! user has requested such support. ! Thus, the support provided not only depends on what the driver detects in the ! system, but also, on what the user specifies in the XF86Config file. See the ! "XF86Config specifications" section below for details. ! If none of the above conditions are met, the ATI driver will essentially dis- ! able itself to allow other drivers to examine the system. + 2. A note on acceleration + The meaning of "acceleration", as used in this document, needs to be clarified. + Two of the many components in an accelerator are the CRT controller (CRTC) and + the Draw Engine. This is in addition to another CRTC that, generally, is also + present in the system (often in the same chip) and typically provides EGA, VGA + or SuperVGA functionality. + ATI Adapters README file + ATI Adapters README file ! A CRTC is the component of a graphics controller that is responsible for read- ! ing video memory for output to the screen. A Draw Engine is an accelerator ! component that can be programmed to manipulate video memory contents, thus ! freeing the CPU for other tasks. ! When the VGA CRTC is used, all drawing operations into video memory are the ! responsibility of the system's CPU, i.e. no Draw Engine can be used. On the ! other hand, if the accelerator's CRTC is chosen to drive the screen, the Draw ! Engine can also be used for drawing operations, although the CPU can still be ! used for this purpose if it can access the accelerator's video memory. + Video acceleration refers to the programming of an accelerator's Draw Engine to + offload drawing operations from the CPU, and thus also implies the use of the + accelerator's CRTC. + 3. Current implementation for ATI adapters + + The driver currently supports the SuperVGA capabilities of all ATI adapters + except some early Mach8 and Mach32 adapters that do not provide the required + functionality. This support works for monochrome, 16-colour and 256-colour + video modes, if one of the following ATI graphics controller chips is present: + + VGAWonder series: 18800, 18800-1, 28800-2, 28800-4, 28800-5, 28800-6 + Mach32 series: 68800-3, 68800-6, 68800AX, 68800LX + Mach64 series: 88800GX-C, 88800GX-D, 88800GX-E, 88800GX-F, 88800CX, + 264CT, 264ET, 264VT, 264GT (a.k.a. 3D Rage), 264VT-B, + 264VT3, 264GT-B (a.k.a. 3D Rage II), 264GT3 (a.k.a. + 3D Rage Pro) + + + There is some support for the 264LT (ATI's recent entry into the laptop world), + but it is untested. + + The driver also supports 32K, 64K and 16M-colour modes on the 264xT series of + adapters using the accelerator CRTC (but not the VGA CRTC). This support is as + yet unaccelerated. + + Adapters based on the above chips have been marketed under a rather large num- + ber of names over the years. Among them are: + + + + + + + + + + + + + + + + + + + + + + + ATI Adapters README file + + + + VGAWonder series: VGAWonder V3, VGAWonder V4, VGAWonder V5, VGAWonder+, + VGAWonder XL, VGAWonder XL24, VGA Basic 16, VGA Edge, + VGA Edge 16, VGA Integra, VGA Charger, VGAStereo F/X, + VGA 640, VGA 800, VGA 1024, VGA 1024D, VGA 1024 XL, + VGA 1024 DXL, VGA 1024 VLB + Mach8 series: Graphics Ultra, Graphics Vantage, VGAWonder GT + (None of the 8514/Ultra and 8514 Vantage series is + supported at this time) + Mach32 series: Graphics Ultra+, Graphics Ultra Pro, Graphics Wonder, + Graphics Ultra XLR, Graphics Ultra AXO, VLB mach32-D, + PCI mach32-D, ISA mach32 + Mach64 series: Graphics Xpression, Graphics Pro Turbo, Win Boost, + Win Turbo, Graphics Pro Turbo 1600, Video Xpression, + 3D Xpression, Video Xpression+, 3D Xpression+, + All-In-Wonder, All-In-Wonder PRO, 3D Pro Turbo, ATI-TV, + XPERT@Play, XPERT@Work, XPERT XL + + + VGAWonder, Mach8 and Mach32 ISA adapters are available with or without a mouse. + These adapters are available with a variety of clock generators and RAMDACs. ! The 264xT series of chips are integrated controllers, meaning that they include ! a programmable clock generator and a RAMDAC. See the "XF86Config specifica- ! tions" section below for details. ! This driver still does not provide support for accelerated drawing to the ! screen. This means that all drawing is done by the CPU, rather than by any ! accelerator present in the system. This can make opaque moves, for example, ! quite "jerky". Thus, given that IBM 8514/A and ATI Mach8 do not allow CPU ! access to their frame buffer, the driver will currently ignore these accelera- ! tors. Most Mach32 adapters provide both accelerated function and VGA function- ! ality, but the driver currently only uses the VGA. ! The driver *does* however support the accelerator CRTC present in all ATI ! Mach64 adapters. For 256-colour, and higher depth modes, this support will be ! used by default, although an XF86Config option can be specified to use the ! SuperVGA CRTC instead. A linear video memory aperture is also available in ! 256-colour and higher depth modes and enabled by default if a 264xT controller ! is detected or, on 88800 controllers, if the accelerator CRTC is used. ! XF86Config options are available to disable this aperture, or (on non-PCI ! adapters) enable it or move it to some other address. ! 4. Current implementation of generic VGA support for non-ATI adapters ! Support for generic VGA with non-ATI adapters is also implemented, but has ! undergone only limited testing. The driver will intentionally disallow the use ! of this support with ATI adapters. This support must be explicitly requested ! through an XF86Config ChipSet specification. This prevents the current generic ! driver from being disabled. ! This driver's generic VGA support is intended as an extension of that provided ! by the current generic driver. Specifically, within the architectural bounds ! defined by IBM's VGA standard, this driver will allow the use of any 256-colour + ATI Adapters README file ! mode, and any dot clock frequencies both of which allow for many more mode pos- ! sibilities. + The driver will enforce the following limitations derived from IBM's original + VGA implementation: + o There can only be a set of four (non-programmable) clocks to choose from. + o Video memory is limited to 256kB in monochrome and 16-colour modes. + + o Video memory is limited to 64kB in 256-colour modes. + + o Interlaced modes are not available. + + + 5. XF86Config specifications + + Except for clocks, the driver does not require any XF86Config specifications of + its own for default operation. The driver's behaviour can however be modified + by the following specifications. + + 5.1 ChipSet "name" + + The default ChipSet name for this driver is "ati". + + If "ativga" is specified instead, the driver will not use any ATI accelerator + CRTC it detects, relying instead on any detected ATI VGA CRTC to provide the + screen image. + + A ChipSet name of "ibmvga" enables the driver's generic VGA support, but only + for non-ATI adapters. If an ATI adapter is detected, the driver will operate + as if "ativga" had been specified instead. + + For compatibility with other XFree86 servers, both past and present, that sup- + port ATI adapters, the driver also recognizes "vgawonder", "mach8", "mach32" + and "mach64" as chipset names. In this version of the driver, all such names + are equivalent to "ati". In some future release, each name will have a differ- + ent meaning to be documented at that time. + + 5.2 Clocks + + For the purpose of specifying a clock line in your XF86Config, one of four dif- + ferent situations can occur, as follows. + + Those configuring the driver's generic VGA support for a non-ATI adapter, can + skip ahead to the "Clocks for non-ATI adapters" section below. Those not try- + ing to configure the driver for a Mach64 adapter, can skip ahead to the "Clocks + for fixed clock generators on ATI adapters" section below. + + The very earliest Mach64 adapters use fixed (i.e. non-programmable) clock gen- + erators. Very few of these (mostly prototypes) are known to exist, but if you + have one of these, you can also skip ahead to the "Clocks for fixed clock gen- + erators on ATI adapters" section below. + + + + + + + + + + ATI Adapters README file + + + + The two cases that are left deal with programmable clock generators, which are + used on the great majority of Mach64 adapters. + + If you are uncertain which situation applies to your adapter, you can run a + clock probe with the command "X -probeonly". + + 5.2.1 Clocks for supported programmable clock generators + + At bootup, video BIOS initialization programmes an initial set of frequencies. + Two of these are reserved to allow the setting of modes that do not use a fre- + quency from this initial set. One of these reserved slots is used by the BIOS + mode set routine, the other by the particular driver used (e.g. MS-Windows, + AutoCAD, X, etc.). The clock numbers reserved in this way are dependent on the + particular clock generator used by the adapter. + + The driver currently supports all programmable clock generators known to exist + on Mach64 adapters. In this case, the driver will completely ignore any + XF86Config clock specification, and programme the clock generator as needed by + the modes used during the X session. + + 5.2.2 Clocks for unsupported programmable clock generators + + This case is unlikely to occur, but is documented for the sake of completeness. + + In this situation, the driver will probe the adapter for clock frequencies + unless XF86Config clocks are already specified. In either case, the driver + will then attempt to normalize the clocks to one of the following specifica- + tions: + + BIOS setting 1: + + Clocks 0.000 110.000 126.000 135.000 50.350 56.640 63.000 72.000 + 0.000 80.000 75.000 65.000 40.000 44.900 49.500 50.000 + 0.000 55.000 63.000 67.500 25.180 28.320 31.500 36.000 + 0.000 40.000 37.500 32.500 20.000 22.450 24.750 25.000 + + + + BIOS setting 2: + + Clocks 0.000 110.000 126.000 135.000 25.180 28.320 31.500 36.000 + 0.000 80.000 75.000 65.000 40.000 44.900 49.500 50.000 + 0.000 55.000 63.000 67.500 12.590 14.160 15.750 18.000 + 0.000 40.000 37.500 32.500 20.000 22.450 24.750 25.000 + + + + BIOS setting 3: + + Clocks 0.000 0.000 0.000 0.000 25.180 28.320 0.000 0.000 + 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 + 0.000 0.000 0.000 0.000 12.590 14.160 0.000 0.000 + 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 + + + + + + + + + + ATI Adapters README file + + + + If the driver matches the clocks to the third setting above, functionality will + be *extremely* limited (assuming the driver works at all). + + 5.2.3 Clocks for fixed clock generators on ATI adapters + + This section applies to all ATI adapters except all but the very earliest + Mach64's. + + One of the following clocks specifications (or an initial subset thereof) can + be used depending on what the adapter uses to generate dot clocks: + + Crystals (VGA Wonder V3 and V4 adapters only): + + Clocks 50.000 56.644 0.000 44.900 44.900 50.000 0.000 36.000 + 25.000 28.322 0.000 22.450 22.450 25.000 0.000 18.000 + 16.667 18.881 0.000 14.967 14.967 16.667 0.000 12.000 12.500 14.161 0.000 11.225 11.225 12.500 0.000 9.000 *************** *** 167,172 **** --- 381,406 ---- + + + + + + + + + + + + + + + + + ATI Adapters README file + + + ATI 18811-1 and ATI 18811-2 clock generators: Clocks 135.000 32.000 110.000 80.000 100.000 126.000 92.400 36.000 *************** *** 181,330 **** Mach32 and Mach64 owners should only specify up to the first 32 frequencies. ! The oldest Mach64 adapters use one of the clock generators described above. ! The possibilities for Mach64 adapters also include programmable clock genera- ! tors. At bootup, video BIOS initialization programmes an initial set of fre- ! quencies. Two of these are reserved to allow the setting of modes that do not ! use a frequency from this initial set. One of these reserved slots is used by ! the BIOS mode set routine, the other by the particular driver used (MS-Windows, ! AutoCAD, X, etc.). The clock numbers reserved in this way are dependent on the ! particular clock generator used on the adapter. ! If the driver does not support the adapter's clock generator, it will try to ! ATI adapters README - match the clocks to one of the following specifications. This matching will - occur whether or not the user specifies the clocks in XF86Config. - BIOS setting 1: - Clocks 0.000 110.000 126.000 135.000 50.350 56.640 63.000 72.000 - 0.000 80.000 75.000 65.000 40.000 44.900 49.500 50.000 - 0.000 55.000 63.000 67.500 25.180 28.320 31.500 36.000 - 0.000 40.000 37.500 32.500 20.000 22.450 24.750 25.000 - BIOS setting 2: ! Clocks 0.000 110.000 126.000 135.000 25.180 28.320 31.500 36.000 ! 0.000 80.000 75.000 65.000 40.000 44.900 49.500 50.000 ! 0.000 55.000 63.000 67.500 12.590 14.160 15.750 18.000 ! 0.000 40.000 37.500 32.500 20.000 22.450 24.750 25.000 ! BIOS setting 3: - Clocks 0.000 0.000 0.000 0.000 25.180 28.320 0.000 0.000 - 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 - 0.000 0.000 0.000 0.000 12.590 14.160 0.000 0.000 - 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 ! If the driver matches the clocks to the third setting above, functionality will ! be *extremely* limited (assuming the driver works at all). ! Other clock generators that have been used on ATI adapters (which can all be ! said to be clones of one of the above) might generate non-zero frequencies for ! those that are zero above, or vice-versa. ! The order of the clocks *is* very important, although the driver will reorder ! the clocks if it deems it appropriate to do so. Mach32 and Mach64 owners ! should note that this order is different than what they would use for the ! accelerated servers. ! If the driver detects a supported programmable clock generator, it will ignore ! any XF86Config clock specification and programme the generator as needed by the ! modes to be used during the X session. ! A clock probe, done with the command "X -probeonly", will help you decide which ! of the above to use for your particular adapter. If the server consistently ! reports that it has detected an unknown clock generator, please e-mail me the ! stderr output. ! Modes can be derived from the information in XFree86's doc directory. If you ! do not specify a "modes" line in the display subsection of the appropriate ! screen section of your XF86Config, the driver will generate a default mode and ! attempt to use it. The timings for the default mode are derived from the - ATI adapters README - timings of the mode (usually a text mode) in effect when the server is started. ! 5. What is the history of the driver? - The complete history of the driver is rather cloudy. The following is probably - incomplete and inaccurate. - Apparently, Per Lindqvist (pgd@compuram.bbt.se) first got an ATI driver working - with an early ATI card under X386 1.1a. This original driver may have actually - been based on an non-functional ATI driver written by Roell. Then Doug Evans - (dje@cygnus.com) ported the driver to the ATI VGA Wonder XL, trying in the pro- - cess to make the driver work with all other ATI cards. ! Rik Faith (faith@cs.unc.edu) obtained the X11R4 driver from Doug Evans in the ! summer of 1992, and ported the code to the X386 part of X11R5. This subse- ! quently became part of XFree86. ! I (Marc Aurele La France) took the driver over in the fall of 1993 after Rik ! got rid of his VGA Wonder card. ! 6. Miscellaneous notes ! In all cases, virtual resolutions must be less than 4096 pixels wide. For VGA- ! Wonder V3 adapters with 256kB of video memory, and for all 264xT adapters, the ! 256-colour server will further limit virtual resolutions to less than 2048 pix- ! els wide. These are hardware limits that cannot be circumvented. ! Dot clocks greater than 80MHz cannot be used on most adapters as a way still ! needs to be discovered to make the VGA Wonder controller do pixel multiplexing. ! Support for more than 8bpp colour depth is pending proper RAMDAC handling and ! banked framebuffer code for >8bpp. ! Video memory corruption can still occur during mode switches on V3, V4 and V5 ! adapters. Symptoms of this problem include garbled fonts on return to text ! mode, and various effects (snow, dashed lines, etc) on initial entry into a ! graphics mode. In the first case, the workaround is to use some other means of ! restoring the text font. On Linux, this can be done with the kbd or svgalib ! packages. In the second case, xrefresh will usually cleanup the image. ! Video memory banking does not work in the 16-colour and monochrome servers on ! V3, V4 and V5 adapters (with 512kB of video memory). This appears to be a ! hardware limitation. The driver's default behaviour has been changed to take ! this into consideration by limiting video memory to 256kB. ! Interlaced modes do not work in the monochrome server on 28800-x adapters when ! using a virtual resolution that is 2048 pixels or wider. This appears to be a ! hardware limitation. The driver has been changed to prune modes accordingly. - Support for virtual resolutions using more than 1MB of video memory is still - incomplete. Specifically, such support works on Mach32 adapters, and on 264xT - adapters, but not on any other Mach64 adapters. On 88800GX and 88800CX --- 415,592 ---- Mach32 and Mach64 owners should only specify up to the first 32 frequencies. ! Other clock generators that have been used on ATI adapters (which can all be ! said to be clones of one of the above) might generate non-zero frequencies for ! those that are zero above, or vice-versa. ! The order of the clocks *is* very important, although the driver will reorder ! the clocks if it deems it appropriate to do so. Mach32 and Mach64 owners ! should note that this order is different than what they would use for the ! accelerated servers. + 5.2.4 Clocks for non-ATI adapters + If no clocks are specified in the XF86Config, the driver will probe for four + clocks, the second of which will be assumed to be 28.322MHz. You can include + up to four clock frequencies in your XF86Config to specify the actual values + used by the adapter. Any more will be ignored. + 5.3 Option "nolinear" + By default, the driver will enable a linear video memory aperture for + 256-colour and higher depth modes if it is also using a Mach64 accelerator CRTC + or an integrated Mach64 graphics chip. This option disables this linear aper- + ture. Currently, this also disables support for more than 256 colours. + 5.4 MemBase address + This specification is only effective for non-PCI Mach64 adapters, and is used + to override the CPU address at which the adapter will map its video memory. + Normally, for non-PCI adapters, this address is set by a DOS install utility + provided with the adapter. The MemBase option can also be used to enable the + linear aperture in those cases where ATI's utility was not, or can not be, + used. + For PCI adapters, this address is determined at system bootup according to the + PCI Plug'n'Play specification which arbitrates the resource requirements of + most devices in the system. This means the driver can not easily change the + linear aperture address. ! 5.5 Modelines + Modes can be derived from the information in XFree86's doc directory. If you ! ATI Adapters README file ! do not specify a "modes" line in the display subsection of the appropriate ! screen section of your XF86Config, the driver will generate a default mode and ! attempt to use it. The timings for the default mode are derived from the tim- ! ings of the mode (usually a text mode) in effect when the server is started. + 6. Known problems and limitations ! There are several known problems or limitations related to the XFree86 ATI ! driver. They include: ! o A number of system lockups and blank screens have been reported when using ! PCI Mach64 adapters. The great majority of these problems have been found ! to be due to system aspects that are unrelated to this driver. As of this ! writing, these problems can be divided into three general areas: ! Improper mouse protocol specification with some recent mice. Try differ- ! ent protocol specifications or another mouse. ! A system conflict with APM. This problem is Linux-specific. There is a ! bug in kernels 2.0.31 or earlier that prevents proper APM operation. ! Upgrade to a more recent kernel or disable APM support. ! The TV port on some Mach64 adapters needs to be disabled using an ATI ! utility that might or might not be supplied with the adapter. This prob- ! lem is currently under investigation. ! o When using a Mach64's accelerator CRTC, the virtual resolution must be ! less than 8192 pixels wide. The VGA CRTC further limits the virtual reso- ! lution width to less than 4096 pixels, or to less than 2048 pixels for ! adapters based on 18800's (with 256kB of memory) and on Mach64 integrated ! controllers. These are hardware limits that cannot be circumvented. + o Virtual resolutions requiring more than 1MB of video memory (256kB in the + monochrome case) are not supported by the VGA CRTC on 88800GX and 88800CX + adapters. This is a hardware limit that cannot be circumvented. + o Due to hardware limitations, doublescanned modes are not supported by the + accelerator CRTC in 88800GX, 88800CX, 264CT and 264ET adapters. + o Monochrome interlaced modes are not supported on 18800-x and 28800-x when + using a virtual resolution that is 2048 pixels or wider. This is yet + another hardware limitation that cannot be circumvented. + o Video memory banking does not work in monochrome and 16-colour modes on + 18800 and 18800-1 adapters. This appears to be another hardware limit, + but this conclusion cannot be confirmed at this time. The driver's + default behaviour in this case is to limit video memory to 256kB. + o The default mode does not work on the more recent Mach64 adapters. This + problem is caused by the driver's attempt to use an incorrect dot clock + for the mode. This will be fixed in a future release by reading the pro- + grammable clock generator's registers to determine the actual clock used + by the mode. ! ATI Adapters README file ! o Most XFree86 servers assume that the video state on entry to the server is ! a text mode. This assumption is known to cause problems on operating sys- ! tems which invoke the server from a graphics mode. DBCS versions of OS/2, ! primarily used in Asia, are examples of such operating systems. The solu- ! tion, for now, is to somehow coerce the OS to invoke the server from a ! text mode. This driver has been changed to simply assume the mode on ! entry uses the adapter's VGA CRTC (in text or graphics modes). While this ! action alleviates the problem somewhat, it does not completely solve it, ! as the server could still be invoked from an accelerator mode. To prop- ! erly fix this problem for all XFree86 servers is a large project, and will ! probably not get done anytime soon. ! o Video memory corruption can still occur during mode switches on 18800 and ! 18800-1 adapters. Symptoms of this problem include garbled fonts on ! return to text mode, and various effects (snow, dashed lines, etc) on ini- ! tial entry into a graphics mode. In the first case, the workaround is to ! use some other means of restoring the text font. On Linux, this can be ! accomplished with the kbd or svgalib packages. In the second case, xre- ! fresh(1) will usually clean up the image. No solution to this problem is ! currently known. + o There is some controversy over what the maximum allowed clock frequency + should be on 264xT adapters. For now, clocks will, by default, be limited + to 135MHz, 170MHz, 200MHz or 230MHz, depending on the specific controller. + This limit can only be increased (up to a driver-calculated absolute maxi- + mum) through the DACSpeed specification in XF86Config. Be aware however + that doing so is untested and might damage the adapter. ! o Except as in the previous item, clocks are limited to 80MHz on most ! adapters, although many are capable of higher frequencies. This will be ! fixed in a future release. ! Support for the following will be added in a future release: ! o Mach32 accelerator's CRTC. This support is the first step towards accel- ! erated support for Mach32's, Mach8's, 8514/A's and other clones. ! o Colour depth greater than 8, where permitted by the hardware. ! o Mach64, Mach32, Mach8 and 8514/A Draw Engines. ! o Hardware cursors. ! Support, through this driver, for 3D acceleration, "TV in a window" and video ! capture, as implemented in some ATI adapters, is still in exploratory stages. ! There is currently no framework within an XFree86 server for these functions, ! although one is in the final stages of development. Also, ATI has not yet ! released a register-level specification for these, except under non-disclosure ! agreements. + 7. Reporting problems + If you are experiencing problems that are not already recorded in this *************** *** 331,375 **** - ATI adapters README - adapters, this appears to be a hardware limitation. Consequently, the driver's - default behaviour is to limit video memory to 1MB. - There is some controversy over whether or not clocks higher than 135MHz should - be allowed on 264xT adapters. For now, clocks will be limited to 135MHz by - default. This limit can only be increased (up to a driver-calculated absolute - maximum) through the DACSpeed option in XF86Config. Be aware however that - doing this is untested and might damage the adapter. ! The default mode does not work on the more recent Mach64 adapters. This will ! be fixed in a future release by reading the programmable clock generator's reg- ! isters. ! Future development plans include addressing the above problems and using accel- ! erated functionality. ! Please e-mail any bug reports, comments, etc. to Marc Aurele La France, ! tsi@ualberta.ca ! Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/ati.sgml,v 3.15.2.1 1997/06/01 12:33:36 dawes Exp $ ! $TOG: README.ati /main/16 1997/07/19 10:29:17 kaleb $ --- 593,658 ---- + ATI Adapters README file ! document, first ensure that you have the latest current release of this driver ! and XFree86. Check the server's stderr output and ! ftp://ftp.xfree86.org/pub/XFree86 if you are uncertain. ! Secondly, please check XFree86's doc directory for additional information. ! Thirdly, do not forget to read http://www.xfree86.org/FAQ. ! Fourth, a scan through the comp.windows.x.i386unix and comp.os.linux.x news- ! groups using your favorite archiving service can also prove useful in resolving ! problems. + If you are still experiencing problems, you can send me e-mail at tsi@ual- + berta.ca. Please be as specific as possible when describing the problem(s), + and include an unedited copy of the server's stderr and the XF86Config file + used. + 8. Driver history + The complete history of the driver is rather cloudy. The following is more + than likely to be incomplete and inaccurate. ! Apparently, Per Lindqvist first got a driver working with an early ATI adapter ! under X386 1.1a. This original driver might have actually been based on a non- ! functional ATI driver written by Thomas Roell (currently of Xi Graphics). + Then Doug Evans (dje@cygnus.com) added support for the ATI VGA Wonder XL, try- + ing in the process to make the driver work with all other ATI adapters avail- + able at the time. + Rik Faith (faith@cs.unc.edu) obtained the X11R4 driver from Doug Evans in the + summer of 1992 and ported the code to the X386 part of X11R5. This subse- + quently became part of XFree86. + I (Marc Aurele La France) took over development and maintenance of the driver + in the fall of 1993 after Rik got rid of his VGA Wonder card. + 9. Driver versions + Due to the introduction of loadable drivers in an upcoming XFree86 release, it + has become necessary to track driver versions separately. With this release of + the driver, I am introducing the following version numbering scheme. + Version 1 of this driver is the one I inherited from Rik Faith. This is the + version found in XFree86 2.0 and 2.1. + Version 2 is my first rewrite of this code which only ended up being a par- + tially unsuccessful attempt at generalizing the driver for all VGA Wonder, + Mach32, and early Mach64 adapters. Various releases of this version of the + driver can be found in XFree86 2.1.1, 3.1, 3.1.1 and 3.1.2. + Version 3 represents my second rewrite (although a rather lame one as rewrites *************** *** 378,393 **** --- 661,686 ---- + ATI Adapters README file + go). Into version 3, I introduced clock programming for Mach64 adapters and + merged in the old ati_test debugging tool. This is the version found in + XFree86 3.2, 3.3 and 3.3.1. + Version 4 is a rather major restructuring of version 3, which became larger + than I could comfortably handle in one source file. This version will make it + quite a bit easier to introduce new function such as acceleration, additional + colour depths, and so on. This is the version found in XFree86 3.3.2. + Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/ati.sgml,v 3.15.2.2 1998/02/01 16:04:54 robin Exp $ + $TOG: README.ati /main/17 1998/03/06 16:39:28 kaleb $ *************** *** 397,403 **** - ATI adapters README --- 690,695 ---- *************** *** 435,440 **** --- 727,733 ---- + ATI Adapters README file *************** *** 467,487 **** - CONTENTS - 1. What is the ATI VGA driver? .............................................. 1 - 2. What is the ATI VGA driver *not*? ........................................ 1 - 3. What video adapters will the driver work with? ........................... 2 - 4. What should I put in my XF86Config file? ................................. 2 - 5. What is the history of the driver? ....................................... 5 - 6. Miscellaneous notes ...................................................... 5 --- 760,773 ---- *************** *** 511,530 **** i ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/README.ati,v 3.29.2.1 1997/06/01 12:41:32 dawes Exp $ --- 797,860 ---- + CONTENTS + 1. Statement of intent ...................................................... 1 + 2. A note on acceleration ................................................... 1 + 3. Current implementation for ATI adapters .................................. 2 + 4. Current implementation of generic VGA support for non-ATI adapters ....... 3 + 5. XF86Config specifications ................................................ 4 + 5.1 ChipSet "name" ....................................................... 4 + 5.2 Clocks ............................................................... 4 + 5.3 Option "nolinear" .................................................... 7 + 5.4 MemBase address ...................................................... 7 + 5.5 Modelines ............................................................ 7 + 6. Known problems and limitations ........................................... 8 + 7. Reporting problems ....................................................... 9 + 8. Driver history .......................................................... 10 + 9. Driver versions ......................................................... 10 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + i ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/README.ati,v 3.29.2.2 1998/02/08 11:19:32 dawes Exp $ *** ./programs/Xserver/hw/xfree86/doc/README.chips@@/PUBLIC-LATEST Sun Aug 10 13:02:43 1997 --- xc/programs/Xserver/hw/xfree86/doc/README.chips Fri Mar 6 16:37:55 1998 *************** *** 346,354 **** mance. One machine known to work well with this option is the Toshiba 720CDT. Note that newer machines often have an MClk greater than 38MHz, and so this option might actually slower the ! machine down. This option is generally not recommended. 4. Modelines When constructing a modeline for use with the Chips and Technologies driver --- 346,369 ---- mance. One machine known to work well with this option is the Toshiba 720CDT. Note that newer machines often have an MClk greater than 38MHz, and so this option might actually slower the ! machine down. This option is generally not recommended and is ! superseded by the "Set_MemClk" option. + DacSpeed 80.000 + The server will limit the maximum dotclock to a value as specified + by the manufacturer. This might make certain modes impossible to + obtain with a reasonable refresh rate. Using this option the user + can override the maximum dot-clock and specify any value they pre- + fer. Use caution with this option, as driving the video processor + beyond its specifications might cause damage. + Set_MemClk 38.000 (Chips 65550/54/55 and 68554) + This option sets the internal memory clock (MCLK) registers to + 38MHz or some other value. Use caution as excess heat generated by + the video processor if its specifications are exceeded might cause + damage. However careful use of this option might boost performance. + + 4. Modelines When constructing a modeline for use with the Chips and Technologies driver *************** *** 374,379 **** --- 389,406 ---- series of chips doesn't need to use additional clock cycles to dis- play higher depths, and so the same modeline can be used at all depths, without needing to divide the clocks. Also 16/24 bpp modes + + + + + + + + + Information for Chips and Technologies Users + + + will need 2 or 3 times respectively more video ram. * Frame Acceleration *************** *** 388,406 **** 61440 bytes (640x480 panel), 96000 bytes (800x600 panel) and 157287 bytes (1024x768 panel). - - - - - - - - - - Information for Chips and Technologies Users - - - * H/W Acceleration The H/W cursor will need 1kB for the 6554x and 4kb for the 65550. On the 64300 chips the H/W cursors is stored in registers and so no --- 415,420 ---- *************** *** 437,458 **** be needed. Some machines that are known to need these options include. - Modeline "640x480@8bpp" 25.175 640 672 728 816 480 489 501 526 - Modeline "640x480@16bpp" 25.175 640 672 728 816 480 489 501 526 - Options: "use_modeline" - Tested on a Prostar 8200, (640x480, 65548, 1Mbyte) - Modeline "800x600@8bpp" 28.322 800 808 848 936 600 600 604 628 - Options: "fix_panel_size", "use_modeline" - Tested on a HP OmniBook 5000CTS (800x600 TFT, 65548, 1Mbyte) - Modeline "800x600@8bpp" 30.150 800 896 960 1056 600 600 604 628 - Options: "fix_panel_size", "use_modeline" - Test on a Zeos Meridan 850c (800x600 DSTN, 65545, 1Mbyte) --- 451,462 ---- *************** *** 459,472 **** - Information for Chips and Technologies Users The NEC Versa 4080 just needs the "fix_panel_size" option. --- 463,490 ---- + Information for Chips and Technologies Users + Modeline "640x480@8bpp" 25.175 640 672 728 816 480 489 501 526 + Modeline "640x480@16bpp" 25.175 640 672 728 816 480 489 501 526 + Options: "use_modeline" + Tested on a Prostar 8200, (640x480, 65548, 1Mbyte) + Modeline "800x600@8bpp" 28.322 800 808 848 936 600 600 604 628 + Options: "fix_panel_size", "use_modeline" + Tested on a HP OmniBook 5000CTS (800x600 TFT, 65548, 1Mbyte) + + + Modeline "800x600@8bpp" 30.150 800 896 960 1056 600 600 604 628 + Options: "fix_panel_size", "use_modeline" + Test on a Zeos Meridan 850c (800x600 DSTN, 65545, 1Mbyte) + + The NEC Versa 4080 just needs the "fix_panel_size" option. *************** *** 503,508 **** --- 521,538 ---- quency combination. For LCD modes, it is possible that your LCD panel requires different panel timings at the text console than with a graphics mode. In this case you will need the "use_modeline" + + + + + + + + + Information for Chips and Technologies Users + + + and perhaps also the "fix_panel_size" options to reprogram the LCD panel timings to sensible values. *************** *** 521,538 **** Hang as the first text is appearing on the screen on SVR4 machines. This problem has been reported under UnixWare 1.x, but not tracked - - - - - - - - - Information for Chips and Technologies Users - - - down. It doesn't occur under UnixWare 2.x and only occurs on the HiQV series of chips. It might affect some other SVR4 operating systems as well. The workaround is to turn off the use of CPU to --- 551,556 ---- *************** *** 569,574 **** --- 587,604 ---- the "TextClockFreq" option described above to select a different clock for the text console. Another possible cause of this problem is if the kernel is compiled with the "APM_DISPLAY_BLANK" option. + + + + + + + + + Information for Chips and Technologies Users + + + As mentioned before, this option should be disabled. I can't display 640x480 on my 800x600 LCD *************** *** 587,604 **** servers solution to this problem is not to do doubling vertically. Which results in the 320x240 mode only expanded to 640x360. If this is a problem, a work around is to use the "sw_cursor" option. The - - - - - - - - - Information for Chips and Technologies Users - - - server will then allow the mode to occupy the whole 640x480 LCD. After a suspend/resume my screen is messed up --- 617,622 ---- *************** *** 636,641 **** --- 654,670 ---- used by the mode will be doubled/tripled. The correct options to start the server with these modes are + + + + + + + + Information for Chips and Technologies Users + + + startx -- -bpp 16 5-6-5 RGB ('64K color', XGA) startx -- -bpp 16 -weight 555 5-5-5 RGB ('Hicolor') startx -- -bpp 24 8-8-8 RGB truecolor *************** *** 654,670 **** not addressed above, please try to alter the clock you are using slightly, say in steps of 0.05MHz and see if the problem goes away. - - - - - - - - Information for Chips and Technologies Users - - - For other screen drawing related problems, try the "noaccel" or "no_bitblt" options. A useful trick for all laptop computers is to switch between LCD/CRT (usually with something like Fn-F5), if the screen is having problems. --- 683,688 ---- *************** *** 700,705 **** --- 718,736 ---- o David Bateman + + + + + + + + + + Information for Chips and Technologies Users + + + o Xavier Ducoin Contributors (In no particular order) *************** *** 717,723 **** We also thank the many people on the net who have contributed by reporting bugs and extensively testing this server before its inclusion in XFree 3.2 ! Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/chips.sgml,v 3.12.2.6 1997/07/28 14:17:31 dawes Exp $ --- 748,754 ---- We also thank the many people on the net who have contributed by reporting bugs and extensively testing this server before its inclusion in XFree 3.2 ! Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/chips.sgml,v 3.12.2.7 1998/01/31 14:23:27 hohndel Exp $ *************** *** 727,732 **** --- 758,798 ---- + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Information for Chips and Technologies Users *************** *** 857,860 **** ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/README.chips,v 3.13.2.5 1997/07/28 14:19:35 dawes Exp $ --- 923,926 ---- ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/README.chips,v 3.13.2.7 1998/02/08 11:19:32 dawes Exp $ *** ./programs/Xserver/hw/xfree86/doc/README.cirrus@@/PUBLIC-LATEST Sat Jul 19 10:29:28 1997 --- xc/programs/Xserver/hw/xfree86/doc/README.cirrus Fri Mar 6 16:38:00 1998 *************** *** 10,16 **** Information for Cirrus Chipset Users Harm Hanemaayer (H.Hanemaayer@inter.nl.net), Randy Hendry (randy@sgi.com) ! (64xx), Corin Anderson (corina@bdc.cirrus.com) 24 May 1997 --- 10,16 ---- Information for Cirrus Chipset Users Harm Hanemaayer (H.Hanemaayer@inter.nl.net), Randy Hendry (randy@sgi.com) ! (64xx), Corin Anderson (corina@the4cs.com) 24 May 1997 *************** *** 247,258 **** For the 5429, the "mmio" option may be used to enable it, but it has not been tested. ! Finally, if you have 546X chip, it will be on the PCI bus. As such, there is ! no problem about memory mapped I/O or linear frame buffer address spaces run- ! ning into system memory. The PCI spaces are mapped way up near the 4GB point. ! Because the mmio and linear frame buffer don't conflict at all on the system, ! the "linear", Membase, and "mmio" options are ignored (memory mapped I/O and ! linear addressing are always used). --- 247,258 ---- For the 5429, the "mmio" option may be used to enable it, but it has not been tested. ! Finally, if you have 546X chip, it will be on either a PCI or AGP bus. As ! such, there is no problem about memory mapped I/O or linear frame buffer ! address spaces running into system memory. The PCI spaces are mapped way up ! near the 4GB point. Because the mmio and linear frame buffer don't conflict at ! all on the system, the "linear", Membase, and "mmio" options are ignored (mem- ! ory mapped I/O and linear addressing are always used). *************** *** 286,293 **** functions, and perhaps high dot clocks and DRAM timing, at the cost of performance (which will still be reasonable on a local bus). ! Option "fast_dram" "med_dram" "slow_dram" (5424/6/8/9, 543x, 5446) ! These options set the internal memory clock (MCLK) register to another value. The default value programmed by the BIOS is usually OK, don't mess with these options unless absolutely required. --- 286,294 ---- functions, and perhaps high dot clocks and DRAM timing, at the cost of performance (which will still be reasonable on a local bus). ! Option "fast_dram" "med_dram" ! "slow_dram" (5424/6/8/9, 543x, 5446, 546x)" These options set the ! internal memory clock (MCLK, or BCLK for the 546x) register to another value. The default value programmed by the BIOS is usually OK, don't mess with these options unless absolutely required. *************** *** 322,328 **** 0x1c (50 MHz) This is usually the BIOS default. It is forced by the - "slow_dram" option. --- 323,328 ---- *************** *** 335,340 **** --- 335,342 ---- + "slow_dram" option. + 0x1f (55 MHz) Value used by the "med_dram" option. Highest value that 542x based cards seem to be able to handle with *************** *** 354,362 **** The driver takes the MCLK into account for clock limits that are determined by DRAM bandwidth. ! If you are not having any problems (performance or stability at ! high dot clocks), it is best not to use any of the DRAM options. Option "no_bitblt" This option, when used with a 5426/28/29/3x/46/6x/754x, will have the effect of disabling the use of the BitBLT engine (which the --- 356,370 ---- The driver takes the MCLK into account for clock limits that are determined by DRAM bandwidth. ! For the 546x chips, the BCLK is the Rambus access clock. Typical ! values live in the range of 258 MHz to 300 MHz. If you have trou- ! bles, such as a black checkerboard pattern on the screen, try using ! the "med_dram" or "slow_dram" options. + In all cases, if you are not having any problems (performance or + stability at high dot clocks), it is best not to use any of the + DRAM options. + Option "no_bitblt" This option, when used with a 5426/28/29/3x/46/6x/754x, will have the effect of disabling the use of the BitBLT engine (which the *************** *** 381,393 **** of memory, or if the memory detection goes wrong. It must be speci- fied in the Device section. - Option "fifo_conservative" (5424/6/8/9/3x/46/6x/754x) - This option will set the CRT FIFO threshold to a conservative value - for high dot clocks (>= 65 MHz), reducing performance but hopefully - alleviating problems with what can be described as flashing - `streaks', `jitter' or horizontally repeated display areas on the - screen (especially when a BitBLT operation is in progress, e.g. - scrolling). --- 389,394 ---- *************** *** 396,406 **** - Information for Cirrus Chipset Users Option "fifo_aggressive" (5424/6/8/9/3x/46/6x/754x) This option will set the CRT FIFO threshold to an aggressive value; it will be the same as that used for lower dot clocks. Theoreti- --- 397,414 ---- Information for Cirrus Chipset Users + Option "fifo_conservative" (5424/6/8/9/3x/46/6x/754x) + This option will set the CRT FIFO threshold to a conservative value + for high dot clocks (>= 65 MHz), reducing performance but hopefully + alleviating problems with what can be described as flashing + `streaks', `jitter' or horizontally repeated display areas on the + screen (especially when a BitBLT operation is in progress, e.g. + scrolling). + Option "fifo_aggressive" (5424/6/8/9/3x/46/6x/754x) This option will set the CRT FIFO threshold to an aggressive value; it will be the same as that used for lower dot clocks. Theoreti- *************** *** 448,458 **** Option "favour_bitblt" (5426 only) This option is now obsolete. - Option "mmio" (5429, 7548) - This enables the use of memory-mapped I/O to talk to the BitBLT - engine on the 543x/5429, which is a bit faster. This is option has - no effect when not using the BitBLT engine (e.g. when using - "no_bitblt"). --- 456,461 ---- *************** *** 460,477 **** - - - Information for Cirrus Chipset Users Option "no_mmio" (543x/4x) This disables the use of memory-mapped I/O to talk to the BitBLT engine on any chip for which it is the default mode of operation. ! Option "sw_cursor" (542x/3x/46) This disables use of the hardware cursor provided by the chip. Try this if the cursor seems to have problems. In particular, use this when using dot clocks greater than 85 MHz on the 5434/6 since those --- 463,483 ---- Information for Cirrus Chipset Users + Option "mmio" (5429, 7548) + This enables the use of memory-mapped I/O to talk to the BitBLT + engine on the 543x/5429, which is a bit faster. This is option has + no effect when not using the BitBLT engine (e.g. when using + "no_bitblt"). + Option "no_mmio" (543x/4x) This disables the use of memory-mapped I/O to talk to the BitBLT engine on any chip for which it is the default mode of operation. ! Option "sw_cursor" (542x/3x/46/6x) This disables use of the hardware cursor provided by the chip. Try this if the cursor seems to have problems. In particular, use this when using dot clocks greater than 85 MHz on the 5434/6 since those *************** *** 494,500 **** --- 500,515 ---- Disable automatic stretching (horizontal and vertical expansion) of 640x480 on a 800x600 LCD. + Option "pci_retry" (546x) + Enables a performance feature for PCI based cards. When this fea- + ture is enabled, the driver code will attempt to transmit data on + the PCI bus as fast as possible. For the most part, this option is + safe, but may cause trouble with other PCI devices such as PCI net- + work cards, sound cards, SCSI controllers, etc. When this option + is not selected, a safer approach (polling the VGA's command queue) + is taken. + 4. Mode issues The accelerated 256-color driver uses 16K bytes of scratch space in video mem- *************** *** 506,538 **** memory bandwidth is left for drawing (the amount is displayed during start-up for 542x/3x/46 chips). For the 542x/3x chips, with default MCLK setting (0x1c) and a 32-bit memory interface, performance with a 65 MHz dot clock can be half - of that with a dot clock of 25 MHz. So if you are short on memory bandwidth - and experience blitting slowness, try using the lowest dot clock that is - acceptable; for example, on a 14" or 15" screen 800x600 with high refresh (50 - MHz dot clock) is not so bad, with a large virtual screen. - 5434-based cards with 2Mbyte of memory do much better at high dot clocks; the - DRAM bandwidth is basically double that of the 542x series. The 543x chips also - make more efficient use of the available DRAM bandwidth. The same goes for the - 544x. - 5. Linear addressing and 16bpp/24bpp/32bpp modes - Currently the framebuffer code 16-bit, 24-bit, and 32-bit pixels in the SVGA - server requires linear addressing. (This restriction may be removed in a future ! Information for Cirrus Chipset Users version, but with nearly all new cards using the PCI bus (where linear address- ing poses no problem), removing the linear addressing requirement presently has a lower priority than other features.) Option "linear" can be specified in a --- 521,553 ---- memory bandwidth is left for drawing (the amount is displayed during start-up for 542x/3x/46 chips). For the 542x/3x chips, with default MCLK setting (0x1c) and a 32-bit memory interface, performance with a 65 MHz dot clock can be half + Information for Cirrus Chipset Users + of that with a dot clock of 25 MHz. So if you are short on memory bandwidth + and experience blitting slowness, try using the lowest dot clock that is + acceptable; for example, on a 14" or 15" screen 800x600 with high refresh (50 + MHz dot clock) is not so bad, with a large virtual screen. ! 5434-based cards with 2Mbyte of memory do much better at high dot clocks; the ! DRAM bandwidth is basically double that of the 542x series. The 543x chips also ! make more efficient use of the available DRAM bandwidth. The same goes for the ! 544x. + 5. Linear addressing and 16bpp/24bpp/32bpp modes + Currently the framebuffer code 16-bit, 24-bit, and 32-bit pixels in the SVGA + server requires linear addressing. (This restriction may be removed in a future version, but with nearly all new cards using the PCI bus (where linear address- ing poses no problem), removing the linear addressing requirement presently has a lower priority than other features.) Option "linear" can be specified in a *************** *** 572,577 **** --- 587,604 ---- pin at A26, it is likely to map beyond 64Mb. To do this, take the card out. At the VESA local bus pins (this is the smaller strip of connector pins at the non-slot side of the card), consider the right side (this is the side of the + + + + + + + + + Information for Cirrus Chipset Users + + + board where all the chips are mounted). There are 45 pins here. They are num- bered 1 to 45, from the inside (i.e. the one nearest to the card end is 45). Counting from the inside, the 17th pin is probably not present, then there are *************** *** 587,604 **** With a card on the PCI bus, there is a PCI configuration register that holds the framebuffer base address, which is read automatically by the driver if a PCI card is detected. The `scanpci' program can read out the PCI configuration - - - - - - - - - Information for Cirrus Chipset Users - - - and show the base address. On the VESA local bus, most 543x cards have a default mapping address of 64Mb, --- 614,619 ---- *************** *** 627,632 **** --- 642,670 ---- each depth that you want to run, with separate Modes and virtual screen size. Example (2Mb of video memory): + + + + + + + + + + + + + + + + + + + + Information for Cirrus Chipset Users + + + Section "screen" SubSection "Display" Depth 8 *************** *** 652,670 **** EndSection - - - - - - - - - - Information for Cirrus Chipset Users - - - 6. The ``cl64xx'' Driver The cl64xx driver supports the cl-gd6440 found in many laptops. For example, --- 690,695 ---- *************** *** 693,700 **** The data book indicates that only a configuration of one megabyte of video mem- ory is supported by the chip. This size has been directly set in the driver. If one finds a need, one should be able to override the default size in ! XF86Config. Also, with 1MB of video memory, one should be able to have a vir- ! tual screen size of e.g. 1024x1024 and this is possible in CRT-only screen mode. However, whenever the LCD is in use (LCD and SimulScan), the chip uses a portion of upper video ram for its own internal acceleration purposes. Thus, the maximum video memory available for virtual resolution in LCD modes is about --- 718,737 ---- The data book indicates that only a configuration of one megabyte of video mem- ory is supported by the chip. This size has been directly set in the driver. If one finds a need, one should be able to override the default size in ! XF86Config. Also, with 1MB of video memory, one should be able to have a ! ! ! ! ! ! ! ! ! Information for Cirrus Chipset Users ! ! ! ! virtual screen size of e.g. 1024x1024 and this is possible in CRT-only screen mode. However, whenever the LCD is in use (LCD and SimulScan), the chip uses a portion of upper video ram for its own internal acceleration purposes. Thus, the maximum video memory available for virtual resolution in LCD modes is about *************** *** 720,736 **** SIMulscan mode; for LCD-only operation, use the same mode timing but with a dot clock of 16.257 MHz. Standard 56 Hz 800x600 is also supported on the CRT. - - - - - - - - Information for Cirrus Chipset Users - - - The primary contact for the cl6440 problems with ``cl64xx'' driver is Randy Hendry . --- 757,762 ---- *************** *** 759,764 **** --- 785,802 ---- Horizontal jitter at high dot clocks. This problem shows especially when drawing operations such as + + + + + + + + + Information for Cirrus Chipset Users + + + scrolling are in progress. If you're using a 542x/3x/46/6x/754x, try the "fifo_conservative" option. Failing that, you can try the "fast_dram" option, or use a lower dot clock. If that is not suf- *************** *** 785,802 **** in particular, disable caching of 0xa0000-0xaffff. Disabling hidden DRAM refresh may also help. - - - - - - - - - Information for Cirrus Chipset Users - - - Crash, hang, or trash on the screen after a graphics operation. This may be related to a bug in one of the accelerated functions, or a problem with the BitBLT engine. Try the "noaccel" option, or --- 823,828 ---- *************** *** 825,830 **** --- 851,868 ---- Chipset is not detected. Try forcing the chipset to a type that is most similar to what you + + + + + + + + + Information for Cirrus Chipset Users + + + have. Incorrect little lines (mostly white) appear occasionally *************** *** 845,869 **** PCI 5428-based cards (which are very rare, since the 5428 chip doesn't support PCI). For other screen drawing related problems, try the "noaccel" option (if "no_bitblt" doesn't help). If are having driver-related problems that are not addressed by this document, or if you have found bugs in accelerated functions, you can try contacting the ! XFree86 team (the current driver maintainer can be reached at ! ! ! ! ! ! ! ! ! Information for Cirrus Chipset Users ! ! ! ! H.Hanemaayer@inter.nl.net), or post in the Usenet newsgroup "comp.win- dows.x.i386unix". In fact, reports (success or failure) are very welcome, especially on configu- --- 883,900 ---- PCI 5428-based cards (which are very rare, since the 5428 chip doesn't support PCI). + No mouse cursor, or cursor appears twice on screen + With high dot clocks, the graphics card's hardware cursor doesn't + operate correctly. Try option "sw_cursor" or use a lower screen + refresh. + For other screen drawing related problems, try the "noaccel" option (if "no_bitblt" doesn't help). If are having driver-related problems that are not addressed by this document, or if you have found bugs in accelerated functions, you can try contacting the ! XFree86 team (the current driver maintainer can be reached at H.Hane- ! maayer@inter.nl.net), or post in the Usenet newsgroup "comp.win- dows.x.i386unix". In fact, reports (success or failure) are very welcome, especially on configu- *************** *** 885,890 **** --- 916,934 ---- CL-GD5464 with 4MB memory on PCI bus + + + + + + + + + + Information for Cirrus Chipset Users + + + CL-GD7543 on PCI bus This is a list of configurations that has received testing with one or more of *************** *** 916,934 **** Works OK at 8bpp, 16bpp, 24bpp and 32bpp. CL-GD5464 works OK at 16bpp, -weight 555. - - - - - - - - - - Information for Cirrus Chipset Users - - - CL-GD7543 on PCI bus Works for 8bpp, 16bpp on TFT display (TI TravelMate 5000). Although the previous version, 3.2, was reported to broken, on some --- 960,965 ---- *************** *** 951,959 **** (3.2A). CL-GD5430, and CL-GD5436 and CL-GD5446 with 1MB memory ! It would be nice to know whether these chips needs the same treat- ! ment at 16bpp as the CL-GD5434 with 1MB memory does. CL-GD5434 with 1MB memory on PCI bus 8bpp, 16pp and 24bpp work OK. 16bpp no longer has "static" prob- lems. MMIO operation is supported. --- 982,1002 ---- (3.2A). CL-GD5430, and CL-GD5436 and CL-GD5446 with 1MB memory ! It would be nice to know whether these chips needs the same + + + + + + + + Information for Cirrus Chipset Users + + + + treatment at 16bpp as the CL-GD5434 with 1MB memory does. + CL-GD5434 with 1MB memory on PCI bus 8bpp, 16pp and 24bpp work OK. 16bpp no longer has "static" prob- lems. MMIO operation is supported. *************** *** 983,1000 **** o Support has been added for the CL-GD5480 and CL-GD5465. - - - - - - - - - Information for Cirrus Chipset Users - - - o 32bpp mode has been fixed on some Alpine family chips. o Support for dot clocks up to 230 MHz has been added for Laguna family --- 1026,1031 ---- *************** *** 1010,1022 **** o Improved support for 754x, including support for LCD stretching/centering. ! Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/cirrus.sgml,v 3.23.2.1 1997/05/24 08:36:08 dawes Exp $ ! $TOG: README.cirrus /main/18 1997/07/19 10:29:30 kaleb $ --- 1041,1053 ---- o Improved support for 754x, including support for LCD stretching/centering. ! Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/cirrus.sgml,v 3.23.2.3 1998/02/20 23:10:31 dawes Exp $ ! $TOG: README.cirrus /main/19 1998/03/06 16:39:38 kaleb $ *************** *** 1026,1062 **** - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Information for Cirrus Chipset Users --- 1057,1062 ---- *************** *** 1139,1145 **** 4. Mode issues ............................................................. 8 ! 5. Linear addressing and 16bpp/24bpp/32bpp modes ........................... 8 6. The ``cl64xx'' Driver ................................................... 11 --- 1139,1145 ---- 4. Mode issues ............................................................. 8 ! 5. Linear addressing and 16bpp/24bpp/32bpp modes ........................... 9 6. The ``cl64xx'' Driver ................................................... 11 *************** *** 1147,1153 **** 8. Tested Configurations .................................................. 14 ! 9. Driver Changes ......................................................... 15 --- 1147,1153 ---- 8. Tested Configurations .................................................. 14 ! 9. Driver Changes ......................................................... 16 *************** *** 1187,1190 **** ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/README.cirrus,v 3.35.2.1 1997/05/24 09:12:07 dawes Exp $ --- 1187,1190 ---- ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/README.cirrus,v 3.35.2.2 1998/02/20 23:14:29 dawes Exp $ *** ./programs/Xserver/hw/xfree86/doc/README.isc@@/PUBLIC-LATEST Sat Jul 19 10:29:41 1997 --- xc/programs/Xserver/hw/xfree86/doc/README.isc Fri Mar 6 16:38:06 1998 *************** *** 11,17 **** Michael Rohleder ! 13 January 1997 --- 11,17 ---- Michael Rohleder ! 11 January 1998 *************** *** 41,50 **** 2. Things needed for compiling the sources ! gcc-2.x.x Use the highest number for x you found. Fresco will only build ! 2.6.3 and later. I'd tried gcc Version 2.5.8, 2.6.0, 2.6.2 and ! 2.6.3. I'm currently using 2.7.2. Since 2.6.3 the current source tree should be able to compile with a little bit more Optimization: --- 41,50 ---- 2. Things needed for compiling the sources ! gcc Use the highest number for x you found. Fresco will only build ! 2.6.3 and later. I'd tried gcc Version 2.5.8, 2.6.0, 2.6.2, 2.6.3 ! and 2.7.2. Current: 2.7.2.3 Since 2.6.3 the current source tree should be able to compile with a little bit more Optimization: *************** *** 71,83 **** ! binutils-2.5.2 You could use the assembler and linker the assembler is most pre- ferred,and the linker is needed at least if you want to link libFresco.a within a Program. Don't use strip and ar/ranlib, the first generates buggy binaries when stripping (at least on my machines) and the last requires the use of ranlib after creating an ! archive, this is not configured. gnu-malloc Due to better memory usage we should use GNU's malloc library on --- 71,84 ---- ! binutils You could use the assembler and linker the assembler is most pre- ferred,and the linker is needed at least if you want to link libFresco.a within a Program. Don't use strip and ar/ranlib, the first generates buggy binaries when stripping (at least on my machines) and the last requires the use of ranlib after creating an ! archive, this is not configured. Current: 2.8.1.0.15 (Used: as, ! ld, ar, strip) gnu-malloc Due to better memory usage we should use GNU's malloc library on *************** *** 89,96 **** --- 90,104 ---- Enable and set #define GnuMallocLibrary to your needs, if it isn't like the default -L/usr/local/lib -lgmalloc. + inline-math (optional) + This is the "original" inline-math package available at your + favorite Linux Mirror. + Use #define UseInlineMath YES inside host.def to enable it. Please + note the changes section what else to do, to use this package. + + 3. Changes to the System Header Files You have to change some of the standard header files supplied with your version *************** *** 117,128 **** - OPEN_MAX had to be increased to prevent Xlib Errors (max no. of clients - reached). - 3.2 /usr/include/sys/ioctl.h - surrounded by --- 125,132 ---- *************** *** 129,142 **** ! Information for ISC Users - #ifndef _IOCTL_H #define _IOCTL_H ... --- 133,149 ---- + Information for ISC Users + OPEN_MAX had to be increased to prevent Xlib Errors (max no. of clients + reached). ! 3.2 /usr/include/sys/ioctl.h + surrounded by #ifndef _IOCTL_H #define _IOCTL_H ... *************** *** 184,190 **** don't like a warning from depend. It isn't needed to compile the sources suc- cessfully. - You could use the following to produce it: --- 191,196 ---- *************** *** 193,208 **** - - - - - - Information for ISC Users #ifndef X_NO_SYS_UN struct sockaddr_un { short sun_family; /* AF_UNIX */ --- 199,210 ---- Information for ISC Users + You could use the following to produce it: + #ifndef X_NO_SYS_UN struct sockaddr_un { short sun_family; /* AF_UNIX */ *************** *** 211,217 **** --- 213,255 ---- #endif + 3.6 /usr/include/math.h + To use the Inline Math package you have to change your existing math.h. Please + note, the way I include the new Header file, is different than suggested in + inline-math's README. + + Please add the following at the bottom of math.h, before the last #endif + + #if defined(UseInlineMath) + + /* Needed on ISC __CONCAT, PI */ + #ifndef __CONCAT + /* + * The __CONCAT macro is used to concatenate parts of symbol names, e.g. + * with "#define OLD(foo) __CONCAT(old,foo)", OLD(foo) produces oldfoo. + * The __CONCAT macro is a bit tricky -- make sure you don't put spaces + * in between its arguments. __CONCAT can also concatenate double-quoted + * strings produced by the __STRING macro, but this only works with ANSI C. + */ + #if defined(__STDC__) || defined(__cplusplus) + #define __CONCAT(x,y) x ## y + #define __STRING(x) #x + #else /* !(__STDC__ || __cplusplus) */ + #define __CONCAT(x,y) x/**/y + #define __STRING(x) "x" + #endif /* !(__STDC__ || __cplusplus) */ + #endif + + #ifndef PI + #define PI M_PI + #endif + + #include "/usr/local/include/i386/__math.h" + #endif + + + 4. make World BOOTSTRAPCFLAGS="-DISC [-DISC30 | -DISC40] -DSYSV [-Di386]" *************** *** 220,225 **** --- 258,274 ---- these two defines are necessary to build the release I don't know if the build will succeed for ISC versions prior than 3.x + + + + + + + + Information for ISC Users + + + -DISC40 are only for getting the ISC version and therefore set the HasSym- Links to Yes ('cause symbolic linking were only supported from Ver- *************** *** 232,244 **** A build on ISC 4.x only needs -DISC40 defined in the BOOT- STRAPCFLAGS ( -DISC30 will be included automatically ). ! Note: if you still use Version 4.0, or you want to build binaries ! on Version 4.1 which should run on 4.0, you have to set #define ! UseChmod YES inside your host.def. (the fchmod function isn't available on 4.0, so it won't compile, and binaries from 4.1 won't run cause of the unsupported System ! call) On Versions less 4.0 this will be the default. -DSYSV [-Di386] standard defines for SystemV Release3 on x86 platform. You don't --- 281,295 ---- A build on ISC 4.x only needs -DISC40 defined in the BOOT- STRAPCFLAGS ( -DISC30 will be included automatically ). ! Note: due to some incompatibilities between ISC 4.0 and 4.1, the ! default is to build for ISC4.0, even if you build on 4.1. If you ! want to build only for 4.1 you should set #define IscCompileVer- ! sion 410 inside your host.def. (the fchmod function isn't available on 4.0, so it won't compile, and binaries from 4.1 won't run cause of the unsupported System ! call The libraries build for 4.1 couldn't be used with 4.0 Systems, ! due to some functions not available on 4.0) -DSYSV [-Di386] standard defines for SystemV Release3 on x86 platform. You don't *************** *** 257,289 **** in xf86site.def. This is necessary to get the correct setup to be defined - Information for ISC Users - for the build. - You need the mmap-2.2.3 driver installed on your system. If you don't - have the mmap-2.2.3 driver installed, you could use the driver source in - the file - xc/programs/Xserver/hw/xfree86/etc/mmapSVR3.shar ! or - /usr/X11R6/lib/X11/etc/mmapSVR3.shar - Build and install the driver as instructed. You'll need the file /usr/include/sys/mmap.h for compiling the X11R6/XFree86 source tree, with linear addressing enabled. --- 308,340 ---- in xf86site.def. This is necessary to get the correct setup to be defined + for the build. + You need the mmap-2.2.3 driver installed on your system. If you don't + have the mmap-2.2.3 driver installed, you could use the driver source in + the file + xc/programs/Xserver/hw/xfree86/etc/mmapSVR3.shar + or + /usr/X11R6/lib/X11/etc/mmapSVR3.shar + Build and install the driver as instructed. You'll need the file ! Information for ISC Users /usr/include/sys/mmap.h for compiling the X11R6/XFree86 source tree, with linear addressing enabled. *************** *** 324,354 **** Expand your .Xdefaults with - Information for ISC Users - *blinkRate: 0 - *cursorPositionVisible: false - This bug seems to be fixed since 3.1.2, and therefore the workaround - is not needed anymore. - o ELSA Winner 2000PRO/X Revision G ! if you experience a Problem with this Card you could try to use the ! older Chipset Driver instead "newmmio". - If you declare Chipset "mmio_928" --- 375,406 ---- Expand your .Xdefaults with + *blinkRate: 0 + *cursorPositionVisible: false + This bug seems to be fixed since 3.1.2, and therefore the workaround + is not needed anymore. + o ELSA Winner 2000PRO/X Revision G + if you experience a Problem with this Card you could try to use the + older Chipset Driver instead "newmmio". + If you declare ! Information for ISC Users + Chipset "mmio_928" *************** *** 386,395 **** This is an obsolete Extension. Anyway, if you want to include this Extension inside your build, you have to add: #define BuildMultibuffer YES inside ! xf86site.def --- 438,451 ---- This is an obsolete Extension. Anyway, if you want to include this Extension inside your build, you have to add: #define BuildMultibuffer YES inside ! xf86site.def Please note, this Extension should be disabled when building the ! Loader Server. + 8. Sample Definitions + This is my current host.def, if I build the sources. (So no more changes were + necessary in xf86site.def, either it isn't to bad to have a look inside it ;-) *************** *** 397,438 **** - Information for ISC Users - 8. Sample Definitions - This is my current host.def, if I build the sources. (So no more changes were - necessary in xf86site.def, either it isn't to bad to have a look inside it ;-) - #ifdef BeforeVendorCF - /* Only when building official binaries*/ - /* - #define InstallJapaneseDocs YES - #define InstallEmptyHostDef - */ - /* Try MultiBuffer Extension */ - #define BuildMultibuffer YES ! /* Build all Contrib SW */ ! #ifdef XF86Contrib ! #undef XF86Contrib ! #endif - /* gcc 2.6.3 tested Optimization Flags */ - # define DefaultGcc2i386Opt -O2 -fstrength-reduce -malign-loops=2 -malign-jumps=2 -malign-functions=2 - /* binaries which should run on ISC 4.0 or for the build on a real 4.0 System */ - # define UseChmod YES ! /* For a POSIXized build on Interactive maybe needed to use gcc2.7.2 */ ! # define UsePosix YES /* Use GNUs MallocLibrary (and the Location for the Lib) */ # define UseGnuMalloc YES # define GnuMallocLibrary -L/usr/local/lib -lgnumalloc --- 453,487 ---- ! Information for ISC Users ! #ifdef BeforeVendorCF + /* ISC 4.1Mu - build only for 4.1 + #define IscCompileVersion 410 + */ + + /* Use inline Math from linux ;-) package inline-math-2.6.tar.gz */ + /* should be available on your favorite linux ftp */ + # define UseInlineMath YES + + /* Use cbrt from liboptm.a (Interactive icc Compiler) */ + /* + */ + # define HasCbrt YES + /* Use GNUs MallocLibrary (and the Location for the Lib) */ # define UseGnuMalloc YES # define GnuMallocLibrary -L/usr/local/lib -lgnumalloc *************** *** 455,491 **** /* Install Config's for xdm, xfs, and xinit */ # define InstallXinitConfig YES # define InstallXdmConfig YES - Information for ISC Users - # define InstallFSConfig YES - #define BuildChooser YES - /* for the new XF86Setup Util */ - #define HasTk YES - #define HasTcl YES - #endif /* BeforeVendorCF */ - 9. Installation - After your make World BOOTSTRAPCFLAGS="... succeed, - make install - - to install in /usr/X11R6. Make sure you have enough space, and /usr/X11R6 exists either as a directory or a symlink to another directory maybe in another filesystem. --- 504,538 ---- /* Install Config's for xdm, xfs, and xinit */ # define InstallXinitConfig YES # define InstallXdmConfig YES + # define InstallFSConfig YES + #define BuildChooser YES + /* for the new XF86Setup Util */ + #define HasTk YES + #define HasTcl YES + #endif /* BeforeVendorCF */ + 9. Installation + After your make World BOOTSTRAPCFLAGS="... succeed, + make install + Information for ISC Users to install in /usr/X11R6. Make sure you have enough space, and /usr/X11R6 exists either as a directory or a symlink to another directory maybe in another filesystem. *************** *** 510,516 **** --- 557,571 ---- to use inside sysadm. You could also install some additional Fonts and Terminal files. + You also should increase MAXUMEM to its maximum, else programs may die with: + X Error of failed request: BadAlloc (insufficient resources for operation) + Major opcode of failed request: 53 (X_CreatePixmap) + Serial number of failed request: 37791 + Current serial number in output stream: 37822 + Widget hierarchy of resource: unknown + + 10. Using ... o Xprt: *************** *** 521,548 **** o Keyboard: You don't need any modmap-File to get your keyboard working with any - Information for ISC Users - iso-8859-1 Font. Simply enable - o LeftAlt Meta - o RightAlt ModeShift ! o RightCtl Compose - in your XF86Config - Section "Keyboard" o xpcterm: if you want to get the German 'Umlaut' inside your ISC X11R4 client xpc- --- 576,604 ---- o Keyboard: You don't need any modmap-File to get your keyboard working with any + iso-8859-1 Font. Simply enable + o LeftAlt Meta + o RightAlt ModeShift + o RightCtl Compose + in your XF86Config - Section "Keyboard" ! Information for ISC Users + o xpcterm: if you want to get the German 'Umlaut' inside your ISC X11R4 client xpc- *************** *** 586,613 **** o Warnings you may see: - Information for ISC Users - o Since 3.2A, you could see a warning from pre X11R6.3 clients. - Warning: Unable to load any usable fontset - The case are the new gzipped fonts, but the Warning isn't serious. - o If you start a server you may see the following message: _XSERVTransOpen: transport open failed for named/enigma:0 _XSERVTransMakeAllCOTSServerListeners: failed to open listener for named --- 642,669 ---- o Warnings you may see: + o Since 3.2A, you could see a warning from pre X11R6.3 clients. + Warning: Unable to load any usable fontset + The case are the new gzipped fonts, but the Warning isn't serious. + o If you start a server you may see the following message: + Information for ISC Users _XSERVTransOpen: transport open failed for named/enigma:0 _XSERVTransMakeAllCOTSServerListeners: failed to open listener for named *************** *** 624,636 **** and the X Consortium for their Public Release of X11R6, as to all who con- tribute to this excellent piece of free software. ! Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/isc.sgml,v 3.18 1997/01/25 03:22:23 dawes Exp $ ! $TOG: README.isc /main/12 1997/07/19 10:29:42 kaleb $ --- 680,692 ---- and the X Consortium for their Public Release of X11R6, as to all who con- tribute to this excellent piece of free software. ! Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/isc.sgml,v 3.18.2.2 1998/02/20 23:10:31 dawes Exp $ ! $TOG: README.isc /main/13 1998/03/06 16:39:44 kaleb $ *************** *** 661,666 **** --- 717,732 ---- + + + + + + + + + + Information for ISC Users *************** *** 741,766 **** 3. Changes to the System Header Files ...................................... 2 3.1 /usr/include/sys/limits.h ........................................... 2 ! 3.2 /usr/include/sys/ioctl.h ............................................ 2 3.3 /usr/include/errno.h ................................................ 3 3.4 /usr/include/rpc/types.h ............................................ 3 3.5 /usr/include/sys/un.h ............................................... 3 4. make World ............................................................. 4 ! 5. linear Addressing ...................................................... 4 ! 6. XKeyboard Extension ..................................................... 6 ! 7. Multibuffer Extension .................................................. 6 8. Sample Definitions ..................................................... 7 9. Installation ........................................................... 8 ! 10. Using ... .............................................................. 8 ! 11. Acknowledgements ...................................................... 10 --- 807,833 ---- 3. Changes to the System Header Files ...................................... 2 3.1 /usr/include/sys/limits.h ........................................... 2 ! 3.2 /usr/include/sys/ioctl.h ............................................ 3 3.3 /usr/include/errno.h ................................................ 3 3.4 /usr/include/rpc/types.h ............................................ 3 3.5 /usr/include/sys/un.h ............................................... 3 + 3.6 /usr/include/math.h ................................................. 4 4. make World ............................................................. 4 ! 5. linear Addressing ...................................................... 5 ! 6. XKeyboard Extension ..................................................... 7 ! 7. Multibuffer Extension .................................................. 7 8. Sample Definitions ..................................................... 7 9. Installation ........................................................... 8 ! 10. Using ... .............................................................. 9 ! 11. Acknowledgements ...................................................... 11 *************** *** 786,794 **** - i ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/README.isc,v 3.28 1997/01/27 22:13:07 dawes Exp $ --- 853,860 ---- i ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/README.isc,v 3.28.2.1 1998/02/20 23:14:30 dawes Exp $ *** /dev/null Tue Jun 30 11:46:34 1998 --- xc/programs/Xserver/hw/xfree86/doc/README.mouse Fri Mar 6 16:38:10 1998 *************** *** 0 **** --- 1,931 ---- + + + + + + + + + + Mouse Support in XFree86 + + Kazutaka Yokota + + 28 February 1998 + + + + 1. Introduction + + This document describes mouse support in XFree86 3.3.2, whose X servers have + the revised mouse driver. + + Mouse configuration has often been mysterious task for novice users. However, + once you learn several basics, it is straightforward to choose options in + XF86Setup or write the "Pointer" section in the XF86Config file by hand. + + + 2. Supported Hardware + + XFree86 X servers support three classes of mice: serial, bus and PS/2 mice. + + Serial mouse + The serial mouse has been the most popular pointing device for PCs. + There have been numerous serial mouse models from a number of manu- + factures. Despite the wide range of variations, there have been + relatively few protocols (data format) with which the serial mouse + talks to the host computer. + + The modern serial mouse conforms to the PnP COM device specifica- + tion so that the host computer can automatically detect the mouse + and load an appropriate driver. The XFree86 3.3.2 X servers sup- + port this specification and can detect popular PnP serial mouse + models. + + Bus mouse + The bus mouse connects to a dedicated interface card in an expan- + sion slot. Some video cards, notably those from ATI, and inte- + grated I/O cards may also have a bus mouse connector. Some bus + mice are known as `InPort mouse'. + + Note that some mouse manufactures have sold a package including a + serial mouse and a serial interface card. Don't confuse this type + of products with the genuine bus mouse. + + PS/2 mouse + They are sometimes called `Mouse-port mouse'. The PS/2 mouse is + becoming increasingly common and popular. + + The PS/2 mouse is an intelligent device and may have more than + three buttons and a wheel or a roller. The PS/2 mouse is usually + compatible with the original PS/2 mouse from IBM immediately after + + + Mouse Support in XFree86 + + + + + + Mouse Support in XFree86 + + + + power up. The PS/2 mouse with additional features requires a spe- + cialized initialization procedure to enable these features. With- + out proper initialization, it behaves as though it were an ordinary + two or three button mouse. + + Many mice nowadays can be used both as a serial mouse and as a PS/2 mouse. + They has a logic to distinguish which interface it is connected to. However, + the mouse which is not marketed as compatible with both serial and PS/2 mouse + interface lacks this logic and cannot be used in such a way, even if you can + find an appropriate adapter with which you can connect the PS/2 mouse to a + serial port or visa versa. + + XFree86 now supports the mouse with a wheel, a roller or a knob. Its action is + detected as the Z (third) axis motion of the mouse. As the X server or clients + normally do not use the Z axis movement of the pointing device, a new configu- + ration option, ZAxisMapping, is provided to assign the Z axis movement to + another axis or a pair of buttons (see below). + + + 3. OS Support for Mice + + 3.1 Summary of Supported Mouse Protocol Types + + Protocol Types + serial PnP BusMouse PS/2 Extended PS/2 + OS platforms protocols serial protocol protocol protocols + "Auto" "BusMouse" "PS/2" "xxxPS/2" + -------------------------------------------------------------------- + BSD/OS Ok ? ? ? ? + FreeBSD Ok Ok Ok Ok SP*1 + FreeBSD(98) Ok ? Ok NA NA + Interactive Unix Ok NA ?*1 ?*1 NA + Linux Ok Ok Ok Ok Ok + Linux/98 Ok ? Ok NA NA + LynxOS Ok NA Ok Ok NA + NetBSD Ok Ok Ok SP*1 NA + NetBSD/pc98 Ok ? Ok NA NA + OpenBSD Ok Ok Ok Ok*1 NA + OS/2 SP*2 SP*2 SP*2 SP*2 SP*2 + SCO Ok ? SP*1 SP*1 NA + Solaris 2.x Ok NA*1 ?*1 Ok NA + SVR4 Ok NA*1 SP*1 SP*1 NA + PANIX Ok ? SP*1 SP*1 NA + + Ok: support is available, NA: not available, ?: untested or unknown. + SP: support is available in a different form + + *1 Refer to the following sections for details. + *2 XFree86/OS2 will support any type of mouse that the OS supports, + whether it is serial, bus mouse, or PnP type. + + 3.2 BSD/OS + + No testing has been done with BSD/OS. + + + + + + + + + Mouse Support in XFree86 + + + + 3.3 FreeBSD + + FreeBSD supports the "SysMouse" protocol which must be specified when the + moused daemon is running in versions 2.2.1 or later. + + FreeBSD versions 2.2.5 or earlier do not support extended PS/2 mouse protocols + ("xxxPS/2"). Always specify the "PS/2" protocol for any PS/2 mouse in these + versions regardless of the brand of the mouse. + + FreeBSD versions 2.2.6 or later include the kernel-level support for these + mice. Specify the "PS/2" or "Auto" protocol and the X server will automati- + cally make use of the kernel-level support. In fact, you may always specify + "Auto" to any mouse in these versions unless the mouse is an old serial model + which doesn't support PnP. + + 3.4 FreeBSD(98) + + The PS/2 mouse is not supported. + + 3.5 Interactive Unix + + The PnP serial mouse support (the "Auto" protocol) is not supported for the + moment. + + The bus mouse and PS/2 mouse should be supported by using the appropriate + device drivers. Use /dev/mouse for the "BusMouse" protocol and /dev/kdmouse + for the "PS/2" protocol. These protocols are untested but may work. Please + send success/failure reports to . + + 3.6 Linux + + All protocol types should work. + + 3.7 Linux/98 + + The PS/2 mouse is not supported. + + 3.8 LynxOS + + The PnP serial mouse support (the "Auto" protocol) is disabled in LynxOS, + because of limited TTY device driver functionality. + + 3.9 NetBSD + + NetBSD does not support extended PS/2 mouse protocols ("xxxPS/2"). The PS/2 + mouse device driver /dev/pms emulates the bus mouse. Therefore, you should + always specify the "BusMouse" protocol for any PS/2 mouse regardless of the + brand of the mouse. + + 3.10 NetBSD/pc98 + + The PS/2 mouse is not supported. + + + + + + + + + + + Mouse Support in XFree86 + + + + 3.11 OpenBSD + + OpenBSD does not support extended PS/2 mouse protocols ("xxxPS/2"). + + The PS/2 mouse device driver /dev/pms emulates the bus mouse. Specify the + "BusMouse" protocol for any PS/2 mouse regardless of the brand of the mouse + when using this device. + + The raw PS/2 mouse device driver /dev/psm uses the standard PS/2 mouse proto- + col. Therefore, you should specify the "PS/2" protocol for any PS/2 mouse + regardless of the brand of the mouse when using this device. + + 3.12 OS/2 + + XFree86/OS2 always uses the native mouse driver of the operating system and + will support any type of pointer that the OS supports, whether it is serial, + bus mouse, or PnP type. If the mouse works under Presentation Manager, it will + also work under XFree86/OS2. + + Always specify "OSMouse" as the protocol type. + + 3.13 SCO + + The bus and PS/2 mouse are supported with the "OSMouse" protocol type. + + The "OSMouse" may also be used with the serial mouse. + + 3.14 Solaris + + Testing has been done with Solaris 2.5.1 and 2.6. Logitech and Microsoft bus + mice have not been tested, but might work with the /dev/logi and /dev/msm + devices. Standard 2 and 3 button PS/2 mice work with the "PS/2" protocol type + and the /dev/kdmouse device. The PnP serial mouse support (the "Auto" proto- + col) has been tested and does not work. + + 3.15 SVR4 + + The bus and PS/2 mouse may be supported with the "Xqueue" protocol type. + + The "Xqueue" may also be used with the serial mouse. + + The PnP serial mouse support (the "Auto" protocol) is not tested. + + 3.16 PANIX + + The PC/AT version of PANIX supports the bus and PS/2 mouse with the "Xqueue" + protocol type. The PC-98 version of PANIX supports the bus mouse with the + "Xqueue" protocol type. + + + 4. Configuring Your Mouse + + Before using the XF86Setup or xf86config programs to set up mouse configura- + tion, you must identify the interface type, the device name and the protocol + + + + + + + + + Mouse Support in XFree86 + + + + type of your mouse. Blindly trying every possible combination of mouse set- + tings will lead you nowhere. + + The first thing you need to know is the interface type of the mouse you are + going to use. It can be determined by looking at the connector of the mouse. + The serial mouse has a D-Sub female 9- or 25-pin connector. The bus mice have + either a D-Sub male 9-pin connector or a round DIN 9-pin connector. The PS/2 + mouse is equipped with a small, round DIN 6-pin connector. Some mice come with + adapters with which the connector can be converted to another. If you are to + use such an adapter, remember that the connector at the very end of the + mouse/adapter pair is what matters. + + The next thing to decide is a device node to use for the given interface. For + the bus and PS/2 mice, there is little choice; your OS most possibly offers + just one device node each for the bus mouse and PS/2 mouse. There may be more + than one serial port to which the serial mouse can be attached. + + The next step is to guess the appropriate protocol type for the mouse. The X + server may be able to select a protocol type for the given mouse automatically + in some cases. Otherwise, the user has to choose one manually. Follow the + guidelines below. + + Bus mouse + The bus and InPort mice always use "BusMouse" protocol regardless + of the brand of the mouse. + + Some OSs may allow you to specify "Auto" as the protocol type for + the bus mouse. + + PS/2 mouse + The "PS/2" protocol should always be tried first for the PS/2 mouse + regardless of the brand of the mouse. Any PS/2 mouse should work + with this protocol type, although wheels and other additional fea- + tures are unavailable in the X server. + + After verifying the mouse works with this protocol, you may choose + to specify one of "xxxPS/2" protocols so that extra features are + made available in the X server. However, support for these PS/2 + mice assumes certain behavior of the underlying OS and may not + always work as expected. Support for some PS/2 mouse models may be + disabled all together for some OS platforms for this reason. + + Some OSs may allow you to specify "Auto" as the protocol type for + the PS/2 mouse and the X server will automatically adjust itself. + + Serial mouse + The XFree86 server supports a wide range of mice, both old and new. + If your mouse is of a relatively new model, it may conform to the + PnP COM device specification and the X server may be able to detect + an appropriate protocol type for the mouse automatically. + + Specify "Auto" as the protocol type and start the X server. If the + mouse is not a PnP mouse, or the X server cannot determine a suit- + able protocol type, the server will print the following error + + + + + + + + + Mouse Support in XFree86 + + + + message and abort. + + xf86SetupMouse: Cannot determine the mouse protocol + + If the X server generates the above error message, you need to man- + ually specify a protocol type for your mouse. Choose one from the + following list: + + o GlidePoint + + o IntelliMouse + + o Logictech + + o Microsoft + + o MMHittab + + o MMSeries + + o MouseMan + + o MouseSystems + + o ThinkingMouse + + When you choose, keep in mind the following rule of thumb: + + 1. "Logitech" protocol is for old serial mouse models from Log- + itech. Modern Logitech mice use either "MouseMan" or + "Microsoft" protocol. + + 2. Most 2-button serial mice support the "Microsoft" protocol. + + 3. 3-button serial mice may work with the "Mousesystems" proto- + col. If it doesn't, it may work instead with the "Microsoft" + protocol although the third (middle) button won't function. + 3-button serial mice may also work with the "Mouseman" proto- + col under which the third button may function as expected. + + 4. 3-button serial mice may have a small switch at the bottom of + the mouse to choose between ``MS'' and ``PC'', or ``2'' and + ``3''. ``MS'' or ``2'' usually mean the "Microsoft" proto- + col. ``PC'' or ``3'' will choose the "MouseSystems" proto- + col. + + 5. If the serial mouse has a roller or a wheel, it may be com- + patible with the "IntelliMouse" protocol. + + 6. If the serial mouse has a roller or a wheel and it doesn't + work with the "IntelliMouse" protocol, you have to use it as + a regular 2- or 3-button serial mouse. + If the "Auto" protocol is specified and the mouse seems working, + but you find that not all features of the mouse is available, that + + + + + + + + + Mouse Support in XFree86 + + + + is because the X server does not have native support for that model + of mouse and is using a ``compatible'' protocol according to PnP + information. + + If you suspect this is the case with your mouse, please send report + to . + + Standardized protocols + Mouse device drivers in your OS may use the standardized protocol + regardless of the model or the class of the mouse. For example, + SVR4 systems may support "Xqueue" protocol. In FreeBSD the system + mouse device /dev/sysmouse uses the "SysMouse" protocol. Please + refer to the OS support section of this file for more information. + + + 5. XF86Config Options + + The following new options are available for the Pointer section of the XF86Con- + fig file. + + 5.1 Buttons + + This option tells the X server the number of buttons on the mouse. Currently + there is no reliable way to automatically detect the correct number. This + option is the only means for the X server to obtain it. The default value is + three. + + Note that if you intend to assign Z axis movement to button events using the + ZAxisMapping option below, you need to take account of those buttons into N + too. + + Buttons N + + 5.2 ZAxisMappping + + This option maps the Z axis (wheel) motion to a pair of buttons or to another + axis. + + ZAxisMapping X + ZAxisMapping Y + ZAxisMapping N M + + The first example will map the Z axis motion to the X axis motion. Whenever + the user moves the wheel/roller, its movement is reported as the X axis motion. + When the wheel/roller stays still, the real X axis motion is reported as is. + The last example will map negative Z axis motion to the button N and positive Z + axis motion to the button M. If this option is used and the buttons N or M + actually exists in the mouse, their actions won't be detected by the X server. + + Currently this option can not be set in the XF86Setup program. You need to + edit the XF86Config file by hand to add this option. + + + + + + + + + + + + Mouse Support in XFree86 + + + + 5.3 Resolution + + The following option will set the mouse device resolution to N counts per inch, + if possible: + + Resolution N + + Not all mice and OSs can support this option. This option can be set in the + XF86Setup program. + + + 6. Mouse Gallery + + 6.1 MS IntelliMouse (serial, PS/2) + + This mouse has been supported since XFree86 3.3. However, support in 3.3.2 is + slightly different; the wheel movement is recognized as the Z axis motion. + This behavior is not compatible with XFree86 3.3, but is more consistent with + the support for other mice with wheels or rollers. If you want to make the + wheel behave like before, you can use the new option "ZAxisMapping" as + described above. + + IntelliMouse supports the PnP COM device specification. + + To use this mouse as a serial device: + + Protocol "Auto" or "IntelliMouse" + Device "/dev/xxxx" (where xxxx is a serial port) + + To use this mouse as the PS/2 device and the OS supports PS/2 mouse initializa- + tion: + + Protocol "IMPS/2" + Device "/dev/xxxx" (where xxxx is the PS/2 mouse device) + + To use this mouse as the PS/2 device but the OS does not support PS/2 mouse + initialization (the wheel won't work in this case): + + Protocol "PS/2" + Device "/dev/xxxx" (where xxxx is the PS/2 mouse device) + + To use this mouse as the PS/2 device and the OS supports automatic PS/2 mouse + detection: + + Protocol "Auto" + Device "/dev/xxxx" (where xxxx is the PS/2 mouse device) + + 6.2 Kensington Thinking Mouse (serial, PS/2) + + This mouse has four buttons. Thinking Mouse supports the PnP COM device speci- + fication. + + To use this mouse as a serial device: + + + + + + + + + + Mouse Support in XFree86 + + + + Protocol "Auto" or "ThinkingMouse" + Device "/dev/xxxx" (where xxxx is a serial port) + + To use this mouse as the PS/2 device and the OS supports PS/2 mouse initializa- + tion: + + Protocol "ThinkingMousePS/2" + Device "/dev/xxxx" (where xxxx is the PS/2 mouse device) + + To use this mouse as the PS/2 device but the OS does not support PS/2 mouse + initialization (the third and the fourth buttons act as though they were the + first and the second buttons): + + Protocol "PS/2" + Device "/dev/xxxx" (where xxxx is the PS/2 mouse device) + + To use this mouse as the PS/2 device and the OS supports automatic PS/2 mouse + detection: + + Protocol "Auto" + Device "/dev/xxxx" (where xxxx is the PS/2 mouse device) + + 6.3 Genius NetScroll (PS/2) + + This mouse has four buttons and a roller. The roller movement is recognized as + the Z axis motion. + + To use this mouse as the PS/2 device and the OS supports PS/2 mouse initializa- + tion: + + Protocol "NetScrollPS/2" + Device "/dev/xxxx" (where xxxx is the PS/2 mouse device) + + To use this mouse as the PS/2 device but the OS does not support PS/2 mouse + initialization (the roller and the fourth button won't work): + + Protocol "PS/2" + Device "/dev/xxxx" (where xxxx is the PS/2 mouse device) + + To use this mouse as the PS/2 device and the OS supports automatic PS/2 mouse + detection: + + Protocol "Auto" + Device "/dev/xxxx" (where xxxx is the PS/2 mouse device) + + 6.4 Genius NetMouse and NetMouse Pro (serial, PS/2) + + These mice have a "magic button" which is used like a wheel or a roller. The + "magic button" action is recognized as the Z axis motion. NetMouse Pro is + identical to NetMouse except that it has the third button on the left hand + side. + + NetMouse and NetMouse Pro support the PnP COM device specification. When used + as a serial mouse, they are compatible with MS IntelliMouse. + + + + + + + + + Mouse Support in XFree86 + + + + To use these mice as a serial device: + + Protocol "Auto" or "IntelliMouse" + Device "/dev/xxxx" (where xxxx is a serial port) + + To use this mouse as the PS/2 device and the OS supports PS/2 mouse initializa- + tion: + + Protocol "NetMousePS/2" + Device "/dev/xxxx" (where xxxx is the PS/2 mouse device) + + To use this mouse as the PS/2 device but the OS does not support PS/2 mouse + initialization (the "magic button" and the third button won't work): + + Protocol "PS/2" + Device "/dev/xxxx" (where xxxx is the PS/2 mouse device) + + To use this mouse as the PS/2 device and the OS supports automatic PS/2 mouse + detection: + + Protocol "Auto" + Device "/dev/xxxx" (where xxxx is the PS/2 mouse device) + + 6.5 ALPS GlidePoint (serial, PS/2) + + The serial version of this pad device has been supported since XFree86 3.2. + `Tapping' action is interpreted as the fourth button press. (IMHO, the fourth + button of GlidePoint should always be mapped to the first button in order to + make this pad behave like the other pad products.) + + To use this pad as a serial device: + + Protocol "GlidePoint" + Device "/dev/xxxx" (where xxxx is a serial port) + + To use this mouse as the PS/2 device and the OS supports PS/2 mouse initializa- + tion: + + Protocol "GlidePointPS/2" + Device "/dev/xxxx" (where xxxx is the PS/2 mouse device) + + To use this mouse as the PS/2 device but the OS does not support PS/2 mouse + initialization: + + Protocol "PS/2" + Device "/dev/xxxx" (where xxxx is the PS/2 mouse device) + + To use this mouse as the PS/2 device and the OS supports automatic PS/2 mouse + detection: + + Protocol "Auto" + Device "/dev/xxxx" (where xxxx is the PS/2 mouse device) + + + + + + + + + + + Mouse Support in XFree86 + + + + 6.6 ASCII MieMouse (serial, PS/2) + + This mouse appears to be OEM from Genius. Although its shape is quite differ- + ent, it works like Genius NetMouse Pro. This mouse has a "knob" which is used + like a wheel or a roller. The "knob" action is recognized as the Z axis + motion. + + MieMouse supports the PnP COM device specification. When used as a serial + mouse, it is compatible with MS IntelliMouse. + + To use this mouse as a serial device: + + Protocol "Auto" or "IntelliMouse" + Device "/dev/xxxx" (where xxxx is a serial port) + + To use this mouse as the PS/2 device and the OS supports PS/2 mouse initializa- + tion: + + Protocol "NetMousePS/2" + Device "/dev/xxxx" (where xxxx is the PS/2 mouse device) + + To use this mouse as the PS/2 device but the OS does not support PS/2 mouse + initialization (the knob and the third button won't work): + + Protocol "PS/2" + Device "/dev/xxxx" (where xxxx is the PS/2 mouse device) + + To use this mouse as the PS/2 device and the OS supports automatic PS/2 mouse + detection: + + Protocol "Auto" + Device "/dev/xxxx" (where xxxx is the PS/2 mouse device) + + 6.7 Logitech MouseMan+ and FirstMouse+ (serial, PS/2) + + MouseMan+ has two buttons on top, one side button and a roller. FirstMouse+ + has two buttons and a roller. The roller movement is recognized as the Z axis + motion. The roller also acts as the third button. The side button is recog- + nized as the fourth button. + + MouseMan+ and FirstMouse+ support the PnP COM device specification. They have + MS IntelliMouse compatible mode when used as a serial mouse. + + To use these mice as a serial device: + + Protocol "Auto" or "IntelliMouse" + Device "/dev/xxxx" (where xxxx is a serial port) + + To use this mouse as the PS/2 device and the OS supports PS/2 mouse initializa- + tion: + + Protocol "MouseManPlusPS/2" + Device "/dev/xxxx" (where xxxx is the PS/2 mouse device) + + + + + + + + + + Mouse Support in XFree86 + + + + To use this mouse as the PS/2 device but the OS does not support PS/2 mouse + initialization (the wheel and the fourth button won't work): + + Protocol "PS/2" + Device "/dev/xxxx" (where xxxx is the PS/2 mouse device) + + To use this mouse as the PS/2 device and the OS supports automatic PS/2 mouse + detection: + + Protocol "Auto" + Device "/dev/xxxx" (where xxxx is the PS/2 mouse device) + + Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/mouse.sgml,v 1.1.2.8 1998/03/02 09:58:25 dawes Exp $ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Mouse Support in XFree86 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CONTENTS + + + + 1. Introduction ............................................................ 1 + + 2. Supported Hardware ...................................................... 1 + + 3. OS Support for Mice ..................................................... 2 + 3.1 Summary of Supported Mouse Protocol Types .......................... 2 + 3.2 BSD/OS ............................................................. 2 + 3.3 FreeBSD ............................................................ 3 + 3.4 FreeBSD(98) ........................................................ 3 + 3.5 Interactive Unix ................................................... 3 + 3.6 Linux .............................................................. 3 + 3.7 Linux/98 ........................................................... 3 + 3.8 LynxOS ............................................................. 3 + 3.9 NetBSD ............................................................. 3 + 3.10 NetBSD/pc98 ........................................................ 3 + 3.11 OpenBSD ............................................................ 4 + 3.12 OS/2 ............................................................... 4 + 3.13 SCO ................................................................ 4 + 3.14 Solaris ............................................................ 4 + 3.15 SVR4 ............................................................... 4 + 3.16 PANIX .............................................................. 4 + + 4. Configuring Your Mouse .................................................. 4 + + 5. XF86Config Options ...................................................... 7 + 5.1 Buttons ............................................................ 7 + 5.2 ZAxisMappping ...................................................... 7 + 5.3 Resolution ......................................................... 8 + + 6. Mouse Gallery ........................................................... 8 + 6.1 MS IntelliMouse (serial, PS/2) .................................... 8 + 6.2 Kensington Thinking Mouse (serial, PS/2) ........................... 8 + 6.3 Genius NetScroll (PS/2) ............................................ 9 + 6.4 Genius NetMouse and NetMouse Pro (serial, PS/2) .................... 9 + 6.5 ALPS GlidePoint (serial, PS/2) .................................... 10 + 6.6 ASCII MieMouse (serial, PS/2) ..................................... 11 + 6.7 Logitech MouseMan+ and FirstMouse+ (serial, PS/2) ................. 11 + + + + + + + + + + + + + + + + i + + + + $XFree86: xc/programs/Xserver/hw/xfree86/doc/README.mouse,v 1.1.2.4 1998/03/02 10:00:10 dawes Exp $ + + + + + $TOG: README.mouse /main/1 1998/03/06 16:39:48 kaleb $ *** ./programs/Xserver/hw/xfree86/doc/README.trident@@/PUBLIC-LATEST Sat Jul 19 10:29:47 1997 --- xc/programs/Xserver/hw/xfree86/doc/README.trident Fri Mar 6 16:38:15 1998 *************** *** 11,29 **** The XFree86 Project, Inc. ! 20 May 1997 1. Supported chipsets ! The Trident driver has undergone some more work for XFree86 3.3. Because of this work, all of the Trident SVGA chipsets, except the very first one, are supported by both the color and monochrome servers. 8800CS 8200LX 8900B 8900C 8900CL/D 9000 9000i 9100B 9200CXr 9320LCD ! 9400CXi 9420 9420DGi 9430DGi 9440AGi 9660XGi 9680 9682 9685 Cyber9382 ! Cyber9385 Cyber9385-1 It must be noted that the 9000i chipset is treated as a 9000 by the server. --- 11,30 ---- The XFree86 Project, Inc. ! 10th February 1998 1. Supported chipsets ! The Trident driver has undergone some more work for XFree86 3.3.2. Because of this work, all of the Trident SVGA chipsets, except the very first one, are supported by both the color and monochrome servers. 8800CS 8200LX 8900B 8900C 8900CL/D 9000 9000i 9100B 9200CXr 9320LCD ! 9400CXi 9420 9420DGi 9430DGi 9440AGi 9660XGi 9680 ProVidia9682 Pro- ! Vidia9685 Cyber9382 Cyber9385 Cyber9385-1 Cyber9388 Cyber9397 3DIm- ! age975(PCI) 3DImage985(AGP) It must be noted that the 9000i chipset is treated as a 9000 by the server. *************** *** 34,63 **** NOTES: ! o Acceleration is now supported for the 9440/96xx and Cyber938x chips. ! o 24bpp is supported for the 9440, 32bpp is supported for the 96xx and ! Cyber938x based chips. ! o The Cyber 9382/5 chips that have started to appear, have much improved ! support in XFree86 3.3 and appear to work at 800x600 on the LCD. ! o The TGUI9440 and TGUI96xx based cards are supported by the SVGA server. - o 16 bits per pixel is now supported for the 8900D, 9200CXr, 9400CXi, - 9420DGi, 9430DGi, 9440AGi, 96xx, but only the 9440AGi and 9400CXi have - been tested. - - o Linear access has been implemented for chipsets that support it. It is - enabled by default for PCI cards, and disabled by default for other cards. - Additionally Hardware cursor is implemented for the 9430, 9440, 96xx, - although only the 9440 and 9660 have been tested with the hardware cursor. - - o The following options may be specified for the Trident driver: - Option "nolinear" Turn off linear mapping --- 35,63 ---- NOTES: ! o The chipset keyword has changed in XFree86 v3.3.2 and now you no longer ! specify 'tgui96xx' as the generic keyword, but you actually specify your ! chip. i.e. Chipset 'tgui9685' will set a ProVidia9685 chip. ! o The new Cyber9397, 3DImage975(PCI) and 3DImage985(AGP) cards are intro- ! duced in XFree86 v3.3.2, but is still experimental, these chipsets are ! currently unaccelerated. ! o 24bpp is all drivers remains unaccelerated, this will change in a future ! version, although 32bpp acceleration is supported for all TGUI based ! chipset except the 9440 which doesn't have the capability. ! o 24/32bpp is not supported for the 9685, it will be fixed in a future ver- ! sion. Option "nolinear" Turn off linear mapping + Option "linear" + Force linear mapping. Use this if you have a non-PCI card and + require 16bpp support. Note: ISA cards can only access up to + 16MB of memory, so be sure you have less than this or it could + cause a system hang. *************** *** 71,82 **** - Option "linear" - Force linear mapping. Use this if you have a non-PCI card and - require 16bpp support. Note: ISA cards can only access up to - 16MB of memory, so be sure you have less than this or it could - cause a system hang. - MemBase "0x???????" This option may be used to specify the start address of the linear frame buffer. By default for VLBus/EISA cards it is at --- 71,76 ---- *************** *** 109,116 **** Turn off XAA acceleration. Option "xaa_no_color_exp" ! Disable color expansion, which is needed for some 9440 cards ! (and maybe others?). Option "no_stretch" Disable LCD stretching on Cyber 938x based chips. --- 103,109 ---- Turn off XAA acceleration. Option "xaa_no_color_exp" ! Disable color expansion. Option "no_stretch" Disable LCD stretching on Cyber 938x based chips. *************** *** 118,130 **** Option "lcd_center" Enable LCD centering on Cyber 938x based chips. Option "tgui_mclk_66' Pushes the Memory Clock from its default value to 66MHz. Increases graphics speed dramatically, but use entirely at your own risk, as it may damage the video card. If snow ! appears, disable. The original Trident chipset, 8800BR, cannot be supported as an SVGA chipset by --- 111,129 ---- Option "lcd_center" Enable LCD centering on Cyber 938x based chips. + Option "cyber_shadow" + Enable Shadow registers, might be needed for some Cyber + chipsets. (laptop machines) + Option "tgui_mclk_66' Pushes the Memory Clock from its default value to 66MHz. Increases graphics speed dramatically, but use entirely at your own risk, as it may damage the video card. If snow ! appears, disable. Only tested on the 9440. The original Trident chipset, 8800BR, cannot be supported as an SVGA chipset by + either the color or monochrome servers. The chip is supported, however, by the + ``generic'' driver for the monochrome server. *************** *** 133,146 **** Information for Trident Chipset Users - either the color or monochrome servers. The chip is supported, however, by the - ``generic'' driver for the monochrome server. - - 2. Special considerations for 512k boards There are no longer any special considerations for 512k Trident boards. The --- 132,142 ---- + Information for Trident Chipset Users 2. Special considerations for 512k boards There are no longer any special considerations for 512k Trident boards. The *************** *** 191,196 **** --- 187,196 ---- dot-clocks above 57Mhz would frequently lock up the machine. There appear to be jumpers on all of the Trident boards that determine whether the board will operate in zero-wait-state mode on the ISA bus. Disabling the zero-wait-state + mode via jumpers cured the lockups, but at the expense of performance. Whether + or not a given system will experience this problem is likely a combination of + (a) bus speed, (b) video memory speed, and (c) dot clock speed. So be prepared + for this phenomenon to occur, and have the board documentation handy. *************** *** 203,218 **** - mode via jumpers cured the lockups, but at the expense of performance. Whether - or not a given system will experience this problem is likely a combination of - (a) bus speed, (b) video memory speed, and (c) dot clock speed. So be prepared - for this phenomenon to occur, and have the board documentation handy. - NOTE: VLBus cards are also subject to the above. By specifying the Clocks in the XF86Config file, these lockups are overcome. But it may be worth checking wait states etc. on the card and in the BIOS setup. ! Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/trident.sgml,v 3.22.2.1 1997/05/21 15:02:40 dawes Exp $ --- 203,213 ---- NOTE: VLBus cards are also subject to the above. By specifying the Clocks in the XF86Config file, these lockups are overcome. But it may be worth checking wait states etc. on the card and in the BIOS setup. ! Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/trident.sgml,v 3.22.2.3 1998/02/24 13:54:23 hohndel Exp $ *************** *** 219,225 **** ! $TOG: README.trident /main/15 1997/07/19 10:29:50 kaleb $ --- 214,220 ---- ! $TOG: README.trident /main/16 1998/03/06 16:39:52 kaleb $ *************** *** 265,270 **** --- 260,270 ---- + + + + + Information for Trident Chipset Users *************** *** 395,398 **** ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/README.trident,v 3.32.2.1 1997/05/21 15:07:30 dawes Exp $ --- 395,398 ---- ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/README.trident,v 3.32.2.3 1998/02/25 12:20:27 dawes Exp $ *** ./programs/Xserver/hw/xfree86/doc/README.tseng@@/PUBLIC-LATEST Sun Aug 10 13:02:49 1997 --- xc/programs/Xserver/hw/xfree86/doc/README.tseng Mon Mar 9 12:58:40 1998 *************** *** 11,17 **** The XFree86 Project, Inc. Dirk H. Hohndel, Koen Gadeyne and others. ! 16 May 1997 --- 11,17 ---- The XFree86 Project, Inc. Dirk H. Hohndel, Koen Gadeyne and others. ! 02 Feb 1998 *************** *** 18,31 **** 1. Supported chipsets The Tseng chipsets supported by XFree86 are ET3000, ET4000, ET4000/W32 and ! ET6000. Accelerated features of the ET4000/W32p and ET6000 are supported by the ! SVGA driver. For details about the separate accelerated 8bpp (=256 color) ! ET4000/W32 and ET6000 server, refer to README.W32. ! Things that are known NOT to work with the SVGA server in this version (XFree86 ! 3.3) are some ET4000W32 ISA cards (they hang the machine... Use the W32 server ! XF86_W32 for these cards!), and acceleration on ET4000W32i cards. In the rest of this document, "8bpp" is short for "8 bits per pixel", which means a 256-color mode. Similarly, 15bpp refers to 32768 colors, 16bpp to 65536 colors , 24bpp to a "packed" 16 million color mode, and 32bpp to a "sparse" 16 --- 18,38 ---- 1. Supported chipsets The Tseng chipsets supported by XFree86 are ET3000, ET4000, ET4000/W32 and ! ET6000. Accelerated features of the ET4000/W32, W32i, W32p and ET6000 are sup- ! ported by the SVGA driver. For details about the separate accelerated 8bpp ! (=256 color) ET4000/W32 and ET6000 server, refer to README.W32. ! Note that you should NOT be using XF86_W32 unless XF86_SVGA doesn't work on ! your hardware. No further development is being done on the W32 server; all new ! efforts go into the SVGA server. + Some ET4000W32 ISA cards are known NOT to work with the SVGA server in this + version (XFree86 3.3.1): they hang the machine... Use the W32 server XF86_W32 + for these cards! + + + 2. Terminology + In the rest of this document, "8bpp" is short for "8 bits per pixel", which means a 256-color mode. Similarly, 15bpp refers to 32768 colors, 16bpp to 65536 colors , 24bpp to a "packed" 16 million color mode, and 32bpp to a "sparse" 16 *************** *** 38,44 **** weight. ! 2. ET4000 driver features The SVGA driver for ET4000 chipsets supports all color depths (8, 15, 16, 24 and 24 bpp) on most ET4000 chips starting with the ET4000W32i. The ET4000W32 --- 45,51 ---- weight. ! 3. ET4000 driver features The SVGA driver for ET4000 chipsets supports all color depths (8, 15, 16, 24 and 24 bpp) on most ET4000 chips starting with the ET4000W32i. The ET4000W32 *************** *** 46,66 **** server, some cards may only support a few of these color depths, or even only 8bpp. ! On W32p chips all color depths are supported on the supported RAMDACs (cur- ! rently ICS5341, STG170x and Chrontel CH8398). These modes are also accelerated. ! On W32i chips, only AT&T49x compatible RAMDACs will support 16 and 24 bpp ! modes, and there is no acceleration support (yet). ! W32p revision a and b chips are limited to 1 MB of video memory in linear mem- ! ory modes with acceleration (i.e. in 16/24/32 bpp modes). This is a hardware ! limitation. - Cards with a RAMDAC that is not yet supported will be limited in a similar man- - ner as the older cards, i.e. to a maximum pixel clock of 86 MHz, whilst they - actually might be able to go up to 135 MHz. As a result, 1280x1024 modes will - only be possible when using interlacing, and non-interlaced modes are limited - Information for Tseng Chipset Users --- 53,66 ---- server, some cards may only support a few of these color depths, or even only 8bpp. ! On W32i and W32p chips all color depths are supported on the supported RAMDACs ! (currently ICS5341, STG170x and Chrontel CH8398). These modes are also acceler- ! ated. ! Some W32p board implementations are limited to 1 MB of video memory in linear ! memory modes. This is a hardware limitation that cannot be solved in the Information for Tseng Chipset Users *************** *** 71,89 **** to about 1024x768 at 75 Hz refresh. ! For a non-interlaced 1280x1024x(256 colors) at say 135-MHz, you need a w32p ! (with its 16-bit RAMDAC bus) with a multiplexing RAMDAC so that the w32p sees ! only (135/2 = 67.5) MHz, not 135 MHz. This requires special code only provided ! for cards using the ICS5341 GENDAC or the STG170x. This code seems to work fine ! for most people, except, with the ICS5341, for a small band of frequencies ! around 90MHz. ! Linear memory mode (especially important for some DGA clients, and required for ! 16/24/32 bpp modes) is supported on all ET4000W32i and ET4000W32p cards, but ! not on the ET4000W32. On ET4000W32p revision a and b, linear memory is limited ! to 1 MB. For the higher color depths (16, 24 and 32 bpp), linear memory mode is REQUIRED. It is enabled by default in these modes. There is no need to specify --- 71,102 ---- + driver. Since XFree86 requires linear memory for 16/24/32 bpp modes, the use- + fulness of these cards for highcolor and truecolor applications is severely + limited (those modes mostly use a lot of video memory). + + In addition, those cards also don't support acceleration in linear mode. This + is a design choice in the driver code: if acceleration were to be supported in + linear mode, you'd only be able to use 768 kb of video memory, and the driver + code would be twice as complex. + + Cards with a RAMDAC that is not yet supported will be limited in a similar man- + ner as the older cards, i.e. to a maximum pixel clock of 86 MHz, whilst they + actually might be able to go up to 135 MHz. As a result, 1280x1024 modes will + only be possible when using interlacing, and non-interlaced modes are limited to about 1024x768 at 75 Hz refresh. ! For a non-interlaced 1280x1024x(256 colors) at say 135-MHz on a W32-type card, ! you need a w32p (with its 16-bit RAMDAC bus) with a multiplexing RAMDAC so that ! the w32p sees only (135/2 = 67.5) MHz, not 135 MHz. This requires special code ! only provided for cards using the ICS5341 GENDAC, the STG170x or the CH8398. ! This code seems to work fine for most people, except, with the ICS5341, for a ! small band of frequencies around 90MHz. ! Linear memory mode (especially important for some DGA clients, like xf86quake) ! is supported on all ET4000W32i and ET4000W32p cards, but not on the ET4000W32. ! See the section on linear memory for more information. There are some important ! issues related to linear memory. For the higher color depths (16, 24 and 32 bpp), linear memory mode is REQUIRED. It is enabled by default in these modes. There is no need to specify *************** *** 90,103 **** that in the XF86Config file. Please read the section on linear memory below: it contains some vital information on how to avoid serious problems. ! To force linear memory mode at 8bpp modes, put the following in the Device sec- ! tion of your XF86Config: Option "linear" ! Acceleration support is present, and enabled by default, for W32p chips (not ! yet for W32i, but that's being worked on). This is based on the new XFree86 ! acceleration interface (XAA). See also README.W32. If you have problems with acceleration, acceleration can be disabled by putting the following in the Device section of your XF86Config: --- 103,115 ---- that in the XF86Config file. Please read the section on linear memory below: it contains some vital information on how to avoid serious problems. ! To force linear memory mode in 8bpp modes (where "banked" mode is the default), ! put the following in the Device section of your XF86Config: Option "linear" ! Acceleration support is present, and enabled by default, for all W32 and ET6000 ! family chips. This is based on the new XFree86 acceleration interface (XAA). If you have problems with acceleration, acceleration can be disabled by putting the following in the Device section of your XF86Config: *************** *** 111,130 **** Option "xaa_no_color_exp" - 3. ET6000 driver features - In addition to the features in the ET4000 driver, the SVGA ET6000 server sup- - ports all possible color depths in the SVGA server: 8bpp, 16bpp (both at 5-5-5 - and 5-6-5 color resolutions), 24bpp and 32 bpp. - In order to be able to run at a depth of 16bpp, 24bpp, or 32bpp, and to improve - performance at 8bpp, linear addressing must be enabled. - Linear memory mode (as opposed to the default, banked memory layout) is sup- - ported. It is required and enabled by default for the 16/24/32 bpp modes. For - 8bpp, the default is banked mode. - To force linear memory at 8bpp, put the following in the SVGA section of your --- 123,132 ---- *************** *** 131,142 **** - Information for Tseng Chipset Users XF86Config: Option "linear" --- 133,153 ---- + Information for Tseng Chipset Users + 4. ET6000 driver features + In addition to the features in the ET4000 driver, the SVGA ET6000 server sup- + ports all possible color depths in the SVGA server: 8bpp, 16bpp (both at 5-5-5 + and 5-6-5 color resolutions), 24bpp and 32 bpp. + Linear memory mode (as opposed to the VGA default, banked memory layout) is + supported. It is required and enabled by default for the 16/24/32 bpp modes. + For 8bpp, the default is banked mode. + + To force linear memory at 8bpp, put the following in the SVGA section of your XF86Config: Option "linear" *************** *** 160,168 **** 110MHz) at which point the cursor does strange things when partly off the left- hand side of the screen. ! Doublescan modes currently don't work with the hardware cursor: only the top ! half of the cursor is visible. If you want to use DoubleScan modes (320x200 is ! a popular one), then do not enable the hardware cursor. On some fast systems, acceleration may cause occasional font corruption. Until this problem is fixed, font acceleration may be disabled using the following in --- 171,180 ---- 110MHz) at which point the cursor does strange things when partly off the left- hand side of the screen. ! On older ET6000 chip revisions, DoubleScan modes currently don't work with the ! hardware cursor: only the top half of the cursor is visible. If you want to use ! DoubleScan modes (320x200 is a popular one), then do not enable the hardware ! cursor. Most recent ET6000 cards and the ET6100 do not exhibit this problem. On some fast systems, acceleration may cause occasional font corruption. Until this problem is fixed, font acceleration may be disabled using the following in *************** *** 179,208 **** Ignoring it is one option (it isn't destructive). Disabling acceleration in the Device section of the XF86Config file is another option: since the accelerator - is not being used, there is ample bandwidth to avoid such problems. - 4. Clock selection problems with some ET4000 boards - XFree86 has some problems getting the clock selection right with some ET4000 - boards when the server is started from a high-resolution text mode. The clock - selection is always correct when the server is started from a standard 80x25 - text mode. - This problem is indicated when the reported clocks are different when the - server is started from the high-resolution text mode from what they are when it - Information for Tseng Chipset Users is started from the 80x25 text mode. To allow the server to work correctly from the high-resolution text mode, there are some Option flags that may be set in XF86Config. To find out which flags to set, start the server with the --- 191,220 ---- Ignoring it is one option (it isn't destructive). Disabling acceleration in the Device section of the XF86Config file is another option: since the accelerator + Information for Tseng Chipset Users + is not being used, there is ample bandwidth to avoid such problems. + 5. Clock selection problems with some ET4000 boards + XFree86 has some problems getting the clock selection right with some ET4000 + boards when the server is started from a high-resolution text mode. The clock + selection is always correct when the server is started from a standard 80x25 + text mode. + This problem is indicated when the reported clocks are different when the + server is started from the high-resolution text mode from what they are when it is started from the 80x25 text mode. To allow the server to work correctly from the high-resolution text mode, there are some Option flags that may be set in XF86Config. To find out which flags to set, start the server with the *************** *** 229,236 **** Option "hibit_high" ! 5. Basic configuration It is recommended that you generate an XF86Config file using the XF86Setup' or xf86config' program, which should produce a working high-resolution 8bpp con- figuration. You may want to include mode timings in the Monitor section that --- 241,257 ---- Option "hibit_high" ! 6. Text mode restore problems + In XFree86 1.3, an option flag ``force_bits'' was provided as an experiment to + attempt to alleviate text-restoration problems that some people experienced. + We have now made the behavior of this option the default, hence the flag has + been removed. Hopefully the past text-restoration problems are alleviated in + XFree86 2.0. + + + 7. Basic configuration + It is recommended that you generate an XF86Config file using the XF86Setup' or xf86config' program, which should produce a working high-resolution 8bpp con- figuration. You may want to include mode timings in the Monitor section that *************** *** 237,247 **** better fit your monitor (e.g 1152x864 modes). The driver options are described in detail in the next section; here the basic options are hinted at. ! If graphics redrawing goes wrong on accelerated chips (ET4000W32p and ET6000), first try the "noaccel"; option, which disables all accelerated functions. ! 6. general options in the XF86Config file The following options are of particular interest to the Tseng driver. Each of them must be specified in the svga' driver section of the XF86Config file, --- 258,279 ---- better fit your monitor (e.g 1152x864 modes). The driver options are described in detail in the next section; here the basic options are hinted at. ! ! ! ! ! ! ! ! Information for Tseng Chipset Users ! ! ! ! If graphics redrawing goes wrong on accelerated chips (ET4000W32 and ET6000), first try the "noaccel"; option, which disables all accelerated functions. ! 8. general options in the XF86Config file The following options are of particular interest to the Tseng driver. Each of them must be specified in the svga' driver section of the XF86Config file, *************** *** 254,288 **** to DRAM timing, high dot clocks, and bugs in accelerated functions, at the cost of performance (which will still be reasonable on a local or PCI bus). This option applies only to those chips where ! acceleration is supported (currently ET4000W32p and ET6000). - Information for Tseng Chipset Users - Option "fast_dram" "slow_dram" - These options set the DRAM speed of certain cards where it applies. - The "slow_dram" option is always enabled on ET4000, and ET4000W32. - If enabled, it slows down DRAM timing, which may avoid some memory- - related problems. If your card starts up with a black screen (and - possibly a system hang), this option might be needed. Not sup- - ported on ET6000. ! The "fast_dram" option will cause the driver to speed up DRAM tim- ! ings, which may also avoid screen-related problems (streaking, ! stripes, garbage, ...). It may also increase those very same ! effects. Not supported on ET6000. videoram 1024 (or another value) (all chips) This option will override the detected amount of video memory, and pretend the given amount of memory is present on the card. This is --- 286,340 ---- to DRAM timing, high dot clocks, and bugs in accelerated functions, at the cost of performance (which will still be reasonable on a local or PCI bus). This option applies only to those chips where ! acceleration is supported. + Option "fast_dram" "slow_dram" + These options set the DRAM speed of certain cards where it applies. + The "slow_dram" option is always enabled on ET4000, and ET4000W32. + If enabled, it slows down DRAM timing, which may avoid some memory- + related problems. If your card starts up with a black screen (and + possibly a system hang), this option might be needed. + The "fast_dram" option will cause the driver to speed up DRAM tim- + ings, which may also avoid screen-related problems (streaking, + stripes, garbage, ...). It may also increase those very same + effects. + All in all, these are potentially dangerous options: they could + crash your machine as soon as you start the server. Use them with + caution. + option "w32_interleave_off" "w32_interleave_on" (W32i, W32p) + Force memory interleaving off or on. W32i and W32p chips can + increase memory bandwidth when they have 2MB or more video memory. + Normally the VGA BIOS sets the W32i or W32p chip to the correct + mode. If you suspect problems with memory sizing or interleaving, + fooling around with these options may improve the situation. It may + also make things worse. These options are not normally needed: the + server will use the correct value automatically. Setting this + option the wrong way will result in a completely distorted display. + option "pci_burst_off" "pci_burst_on" (W32p) + This option disables or enables PCI bursts on the W32p chip if it's + a PCI card. Normally, a good BIOS will set the motherboard and the + VGA card to the same setting, but if both don't match, you may + experience garbage on the screen (e.g. mouse droppings). These + options allow you to match the W32p burst setting to the mother- + board setting. ! Information for Tseng Chipset Users + + videoram 1024 (or another value) (all chips) This option will override the detected amount of video memory, and pretend the given amount of memory is present on the card. This is *************** *** 322,363 **** Read the section on linear memory base address issues below! Read the section on linear memory base address issues below! (Mes- ! sage repeated on purpose) - Information for Tseng Chipset Users ! Use this option ONLY if you have trouble with the default MemBase ! used by the server, or if the server explicitly states that you ! must provide one. - Option "pci_retry" (ET4000W32p on PCI bus, ET6000) - This enables the PCI bus retry function, which is a performance - enhancing mode for PCI bus-based systems, where the VGA controller - will put the PCI bus in a hold state (sort of like wait-states) - when the server tries to start a new accelerated operation but the - accelerator is still busy with the previous operation. - This is the fastest way to drive a VGA card (no busy-waiting loops - needed), but it also stresses some hardware that is timing-depen- - dent (tape drives, sound cards, etc). See also the trouble shooting - section. - 7. linear memory base address (MemBase) issues First a WARNING: defining a bad MemBase may cause serious injury or death (to your operating system, of course). Especially defining the MemBase to be inside the range of system memory is a ticket to hell. Rule #1: first, let the server find a memory base by itself, without specifying it. Make sure you "sync" all files to disk and close all critical applications. Make sure nothing bad will happen to your filesystems if you have to jump for --- 374,418 ---- Read the section on linear memory base address issues below! Read the section on linear memory base address issues below! (Mes- ! sage repeated for a very good reason) + Use this option ONLY if you have trouble with the default MemBase + used by the server, or if the server explicitly states that you + must provide one. + Option "pci_retry" (ET4000W32p on PCI bus, ET6000) + This enables the PCI bus retry function, which is a performance + enhancing mode for local bus or PCI bus-based systems, where the + VGA controller will put the bus in a hold state (sort of like wait- + states) when the server tries to start a new accelerated operation + but the accelerator is still busy with the previous operation. + This is the fastest way to drive a VGA card (no busy-waiting loops + needed), but it also stresses some hardware that is timing- ! Information for Tseng Chipset Users + dependent (tape drives, sound cards, etc). See also the trouble + shooting section. + 9. linear memory base address (MemBase) issues + First a WARNING: defining a bad MemBase may cause serious injury or death (to your operating system, of course). Especially defining the MemBase to be inside the range of system memory is a ticket to hell. + 9.1 What you should know BEFORE trying another MemBase + Rule #1: first, let the server find a memory base by itself, without specifying it. Make sure you "sync" all files to disk and close all critical applications. Make sure nothing bad will happen to your filesystems if you have to jump for *************** *** 367,372 **** --- 422,431 ---- (VLB). The server will autodetect a linear base address that doesn't work on all systems. + The least critical cards are PCI-bus cards. The PCI BIOS normally takes care of + assigning a good MemBase, and you should never have to deal with all the mumbo- + jumbo below. + If the server gets it wrong, you may end up with a severe system crash (e.g. if it maps the video memory right on top of your system memory). If this hap- pens, RESET IMMEDIATELY. Do not try to shut down cleanly, because the X-server, *************** *** 383,388 **** --- 442,449 ---- When the server can't find a working linear memory base, it's time to experi- ment. The rest of this section deals with that. + 9.2 Choosing a MemBase + Choosing a suitable MemBase can be quite tricky. If you have no way of deter- mining the MemBase your card uses, trying to put it a few Mb above the system memory is a good first guess. E.g. if you have 16 Mb of RAM, defining MemBase *************** *** 389,395 **** --- 450,460 ---- 0x01000000 (=16M) or 0x01400000 (=20M) may work. However, this may only work on non-PCI systems, as PCI systems mostly map all + hardware above the 2GB mark. But then again, on PCI systems the server is + almost always able to detect the correct linear memory base address. The only + exception are those systems with more than one PCI VGA card. + On most VESA local bus (VLB) boards, there is an additional problem with *************** *** 397,422 **** Information for Tseng Chipset Users ! hardware above the 2GB mark. But then again, on PCI systems the server is ! almost always able to detect the correct linear memory base address. The only ! exception are those systems with more than one PCI VGA card. ! ! On most VESA local bus (VLB) boards, there is an additional problem with ! address decoding. Some motherboards only decode the first 32, 64 or 128 MB of address space (a good pointer is to check the amount of DRAM that can be installed on the board: it will at least decode as much address space as it supports DRAM). On such boards, you MUST specify a MemBase inside that range, or the actual ! address may wrap back onto system memory. That is why the general guideline of ! putting the MemBase just above the system memory is a sound one: it stands most ! chance of actually being inside the decoded address range of the board. Unless ! your motherboard's entire memory space is filled with RAM. If you don't know how much memory address space your motherboard decodes (and who does?), try using a "non-trivial" address, like 0x1FC00000, which has enough bits set to "1" to work on any motherboard, even if a few are not --- 462,488 ---- + Information for Tseng Chipset Users ! address decoding. Most motherboards only decode the first 32, 64 or 128 MB of address space (a good pointer is to check the amount of DRAM that can be installed on the board: it will at least decode as much address space as it supports DRAM). On such boards, you MUST specify a MemBase inside that range, or the actual ! address may wrap back onto system memory: if your system only decodes 128MB of ! addresses, and you set the MemBase to 128 MB, it will actually be decoded as ! being on address 0, which is probably exactly where your kernel memory is ! located. That is why the general guideline of putting the MemBase just above ! the system memory is a sound one: it stands most chance of actually being ! inside the decoded address range of the board. Unless your motherboard's entire ! memory space is filled with RAM. + 9.3 An alternative approach + If you don't know how much memory address space your motherboard decodes (and who does?), try using a "non-trivial" address, like 0x1FC00000, which has enough bits set to "1" to work on any motherboard, even if a few are not *************** *** 424,438 **** --- 490,514 ---- of your system memory if the motherboard doesn't decode all upper address bits. You will only do that once. + 9.4 When all else fails... + Some other VLB boards can only map the linear framebuffer above the 1GB mark (0x80000000 and up), so you must use a MemBase that is higher or equal to 0x80000000. + Some other VLB boards can only map the linear framebuffer BELOW the 16 MB mark. + So you may want to try booting your system with up to 12 MB of memory (some + operating systems allow you to supply a boot-time parameter that limits the + memory to a certain amount, so you don't have to open your computer to try + this), and set the MemBase to 0x00C00000 (=12M). + Unfortunately, there is no easy way to tell what system you have (these details are mostly not in the motherboard manuals). Trial and error is the only road to success here. The server code will provide a default that works on most boards... but yours won't be one of those, of course. + 9.5 Restrictions + There are some limits as to where the linear memory base may be put. On any ET4000W32, it must have a 4MB granularity (i.e. it can be put at 16M or at 20M, but not at 18M). On ET6000, it needs a 16M granularity (note: the ET6000 driver *************** *** 445,450 **** --- 521,538 ---- gent guess at it, but this is no guarantee. On ISA cards, things are much more simple: ISA only uses 24 address lines, and + + + + + + + + + Information for Tseng Chipset Users + + + hence the linear memory MUST lie within the 16 MB boundary. Together with the 4MB granularity of the linear memory base address on ET4000 cards, this means that you cannot have more than 12 MB of system memory in the machine if you *************** *** 455,482 **** WARNING: you must not have over 12 MB of system memory in this case. Or if you have it, you must disable access to all memory above the 12 MB mark. Some operating systems allow you to specify at startup how much memory it is allowed Information for Tseng Chipset Users ! to use, so you don't have to unplug some memory each time you want to use lin- ! ear memory. ! 8. Mode issues ! The accelerated driver on ET4000W32p and ET6000 uses 1K bytes of scratch space ! in video memory. Consequently, a 1024x1024 virtual resolution should not be ! used with a 1Mbyte card. The use of a higher dot clock frequencies has a negative effect on the perfor- mance of graphics operations on non-et6000 cards (the effect is much less, or even non-existing, on ET6000 cards), especially BitBlt, when little video mem- --- 543,623 ---- WARNING: you must not have over 12 MB of system memory in this case. Or if you have it, you must disable access to all memory above the 12 MB mark. Some operating systems allow you to specify at startup how much memory it is allowed + to use, so you don't have to unplug some memory each time you want to use lin- + ear memory. + 9.6 Some boards simply cannot work in linear mode + Yes, and in that case, you're out of luck. + There can be at least two reasons for this. + The first is the most common: the board manufacturer has left out the necessary + connections and hardware to be able to use linear addressing. This means that + no coding effort on this planet can help you with your problem: it is physi- + cally impossible to use linear addressing. + The second reason is that the current XFree86 Tseng linear addressing code is + incompatible with the way your board is designed. The XFree86 Tseng code + assumes a 1:1 mapping of the address lines from the bus (either ISA, VLB or + PCI) to the address lines on the Tseng VGA chip. As unlikely as it may sound, + this may NOT be the case! + Some very rare boards do not have such a 1:1 mapping (e.g. two address lines + swapped). It is possible to support this type of hardware, but at this moment, + this has not been implemented yet. + Other boards use external address decoding hardware that combines a number of + address lines on the bus to a (smaller) number of address lines to the VGA + chip. One such board for example uses three NOR gates (one 74F02 chip) to com- + bine the 6 upper address lines to three address pins on the W32i chip. Obvi- + ously, this represents a 2:1 mapping, and not a 1:1 mapping. Therefor, this + board is not "compatible" with the way XFree86 implements linear mode. + 9.7 How can I see if the linear address is wrong? + + Simple: nothing works, or your machine locks solid, or it crashes, or a zillion + of other things. + + However, sometimes it is not always as obvious. Sometimes nothing bad happens: + you just get a black screen, or a screen with rubbish on it, but nothing is + drawn on it. Sometimes you get a core dump when the first application starts. + + If acceleration is enabled in those cases, you will almost always see multiple + "WAIT_ACL: timeout" messages in the server output. That is because the acceler- + ator registers are also mapped in the linear memory, and if linear memory + doesn't work, then also the accelerator doesn't work. + + + + + + + + Information for Tseng Chipset Users ! NOTE however that a WAIT_ACL message doesn't necessarily mean the linear memory ! address is bad. There are a number of other reasons for this message as well. ! But if you never saw these messages at 8bpp banked, then there's a good chance ! you have a linear memory problem ("banked" is the opposite of "linear", and is ! the default mode when "option linear" is not in the XF86Config file). ! 10. Mode issues ! The accelerated driver on ET4000W32/W32i/W32p and ET6000 needs at least 1K ! bytes of scratch space in video memory. Consequently, if you want acceleration, ! a 1024x1024 virtual resolution should not be used with a 1Mbyte card. This also ! means that a 1024x768 mode at 24bpp on a 2.25 MB ET6000 card cannot be acceler- ! ated, since you've used up all the memory for the display. + The same thing goes for the ET6000 hardware cursor: it also requires 1kb of + free video memory. If that memory is not available, the hardware cursor cannot + be used. + The use of a higher dot clock frequencies has a negative effect on the perfor- mance of graphics operations on non-et6000 cards (the effect is much less, or even non-existing, on ET6000 cards), especially BitBlt, when little video mem- *************** *** 505,526 **** 76 Hz with a 85 MHz dot clock, an 1MB card is a poor match anyway. The ET4000W32i and ET4000W32p have a special feature that almost doubles memory ! bandwidth (+70%) using "interleaving" between the two banks. Upgrading to 2MB ! is a real bonus on these cards. - ET6000-based cards however use MDRAM (multi-bank DRAM), which is much faster - than DRAM. Some 4 MB systems, with 4 MDRAM chips will also do interleaving, - which should give virtually unlimited memory bandwidth: theoretically >1GB/sec, - comparing to the already neat 90MB/sec on a 1MB ET4000W32i/p card). Most 4MB - models have only 2 MDRAM chips (as do the 2MB models). So far for the marketing - hype: a real ET6000 card is limited to somewhere around 225 MB/sec. - 9. Acceleration issues - The XFree Acceleration Architecture makes extensive use of the unused video - memory on the VGA card. If there is not enough free video memory, some acceler- - ation features will be disabled or crippled, resulting in less performance. --- 646,658 ---- 76 Hz with a 85 MHz dot clock, an 1MB card is a poor match anyway. The ET4000W32i and ET4000W32p have a special feature that almost doubles memory ! bandwidth (+70%) using "interleaving" between the two banks. Upgrading to 2MB ! is a real bonus on these cards. This is not true for W32 cards or for ET6000 ! cards. *************** *** 533,538 **** --- 665,676 ---- + 11. Acceleration issues + + The XFree Acceleration Architecture makes extensive use of the unused video + memory on the VGA card. If there is not enough free video memory, some acceler- + ation features will be disabled or crippled, resulting in less performance. + To avoid this from happening, try to keep an absolute minimum of 16 kb of free memory, in addition to the 1kb already reserved by the accelerator. *************** *** 544,552 **** Most 1MB cards cannot display modes larger than 1024x768 with a decent refresh rate, leaving 256kb unused. ! 10. ET6000 memory size facts and fiction The ET6000 uses a special kind of video memory called MDRAM (multi-bank DRAM). It may have a non-power-of-two amount of MDRAM: 2.25 or even 4.50 MB. Espe- cially 2.25 MB MDRAM is popular, since this can support 1024x768 at 24bpp with- --- 682,714 ---- Most 1MB cards cannot display modes larger than 1024x768 with a decent refresh rate, leaving 256kb unused. + The order in which free memory is used to accelerate certain features is as + follows. ! If no video memory is unused (i.e. all of it is used for display memory), no ! acceleration can be used at all -- not even a hardware cursor on the ET6000. + If the hardware cursor is enabled (ET6000 only) and there's at least 1kb of + free video memory, 1kb is used for that. + + If there is at least 1kb of free memory remaining after this, most acceleration + features are enabled as well, reserving an extra 1kb of video memory. + + If there's still some free memory, some extra acceleration features are + enabled. These require more free video memory, depending on the virtual screen + width and the color depth (bpp). The server will print out how much memory it + used if it could. + + If there's still some free video memory, it is used as a pixmap cache. This + way, small patterns and images can be kept in the video memory so that they + don't need to be transferred into the video memory each time they're needed. + This is beneficial because transferring an image over the bus to the video mem- + ory takes a lot more time than letting the accelerator blit it from the pixmap + cache to the display memory. + + + 12. ET6000 memory size facts and fiction + The ET6000 uses a special kind of video memory called MDRAM (multi-bank DRAM). It may have a non-power-of-two amount of MDRAM: 2.25 or even 4.50 MB. Espe- cially 2.25 MB MDRAM is popular, since this can support 1024x768 at 24bpp with- *************** *** 557,565 **** First of all, All memory above the 4 MB limit is a waste of money, because the ET6000 cannot use this memory for anything at all. There are boards with 4.5 MB around, but that extra 0.5 MB is a waste. The ET6000 can only refresh 4 MB of (M)DRAM (refresh register). It can only access 64 banks of 64KB in VGA mode (bank select register). All accelerated commands use a 22-bit address (=4MB) ! inside the video memory. You get the idea... And Secondly (more importantly): you may not have 2.25 MB at all! There have been several reports about ET6000 cards that were sold with (supposedly) 2.25 --- 719,740 ---- First of all, All memory above the 4 MB limit is a waste of money, because the ET6000 cannot use this memory for anything at all. There are boards with 4.5 MB around, but that extra 0.5 MB is a waste. The ET6000 can only refresh 4 MB of + + + + + + + + + Information for Tseng Chipset Users + + + (M)DRAM (refresh register). It can only access 64 banks of 64KB in VGA mode (bank select register). All accelerated commands use a 22-bit address (=4MB) ! inside the video memory. You get the idea... There is no way for the ET6000 to ! use anything above the 4Mb limit. And Secondly (more importantly): you may not have 2.25 MB at all! There have been several reports about ET6000 cards that were sold with (supposedly) 2.25 *************** *** 570,582 **** server should detect the correct amount of memory. Do NOT define the amount of memory in the XF86Config yourself, unless you are ! absolutely sure about the amount. There is a simple way to determine the amount ! of MDRAM on your card beyond doubt. Look at the video card. There is one large chip with 204 pins on it, which is the ET6000. One socketed rectangular chip, mostly with a sticker on it,is the ! BIOS. The remaining chips are (mostly) 2 or 4 other large square chips on it ! with the following markings: MDRAM MD9xy ("xy" is a two-digit number) SJ-5-100 (this may differ, but it will have the same layout) --- 745,759 ---- server should detect the correct amount of memory. Do NOT define the amount of memory in the XF86Config yourself, unless you are ! absolutely sure about the amount. + There is a simple way to determine the amount of MDRAM on your card beyond + doubt. + Look at the video card. There is one large chip with 204 pins on it, which is the ET6000. One socketed rectangular chip, mostly with a sticker on it,is the ! BIOS. The remaining big chips are (mostly) 2 or 4 other large square chips on ! it with the following markings: MDRAM MD9xy ("xy" is a two-digit number) SJ-5-100 (this may differ, but it will have the same layout) *************** *** 584,604 **** and a nice logo next to all that with 4 diamonds and the name "MoSys" under- neath. ! The "xy" number tells you how much MEGABITS are in that one chip. The amount of RAM on the card is then: - - - - - - - - Information for Tseng Chipset Users - - - ("xy" * number_of_MDRAM_chips) / 8 Mbytes On my board, there are two MD908 chips, which means I have --- 761,770 ---- and a nice logo next to all that with 4 diamonds and the name "MoSys" under- neath. ! The "xy" number tells you how much MEGABITS there are in that one chip. The amount of RAM on the card is then: ("xy" * number_of_MDRAM_chips) / 8 Mbytes On my board, there are two MD908 chips, which means I have *************** *** 611,617 **** MD920. ! 11. ET6000 memory bandwidth hype and the impact on video modes Tseng has always had wet dreams about memory bandwidth, and their press announcements about the ET6000 memory bandwidth are no exception. --- 777,783 ---- MD920. ! 13. ET6000 memory bandwidth hype and the impact on video modes Tseng has always had wet dreams about memory bandwidth, and their press announcements about the ET6000 memory bandwidth are no exception. *************** *** 620,630 **** Gbytes/sec of bandwidth. That would surpass just about everything on the market (even SGI). And that would be true, _if_ they actually used the fastest available MDRAMs on their boards, which they don't. The stunning 1.2 GByte mark is only reached when using 4 MDRAM chips at their max clock rate of 166 MHz. But due to design limitations, the first-generation ET6000 can only drive the memories at 92 MHz ! (that will change when the ET6300 hits the streets). This means the max. theoretical bandwidth available on current ET6000 boards is "only" 360 MB/sec on boards with 2 MDRAM chips, and 720 MB/sec on boards with 4 --- 786,807 ---- Gbytes/sec of bandwidth. That would surpass just about everything on the market (even SGI). + + + + + + + + Information for Tseng Chipset Users + + + And that would be true, _if_ they actually used the fastest available MDRAMs on their boards, which they don't. The stunning 1.2 GByte mark is only reached when using 4 MDRAM chips at their max clock rate of 166 MHz. But due to design limitations, the first-generation ET6000 can only drive the memories at 92 MHz ! (that will change when the ET6100 and ET6300 hit the streets). This means the max. theoretical bandwidth available on current ET6000 boards is "only" 360 MB/sec on boards with 2 MDRAM chips, and 720 MB/sec on boards with 4 *************** *** 634,639 **** --- 811,822 ---- reduce the effective available bandwidth. The current ET6000 boards peak out at about 225 MB/sec, with 2 or 4 MDRAMs. + Whatever you may have read in press releases, the ET6000 has a 32-bit memory + bus (not 128 bits; that's only the accelerator data path within the chip, if + anything). That means that, with their 16-bit busses, 2 MDRAM chips already use + the full bus capacity. Having 4 memory chips on an ET6000 board will not give + you extra memory bandwidth. + Memory bandwidth limits the maximum resolution you can use at a given color depth. The ET6000 RAMDAC can cope with 135 MHz in any situation. But the RAM cannot. At 32bpp (sparse 16M color mode), using a 135 MHz pixel clock would *************** *** 647,672 **** available. ! 12. Linear addressing and 16bpp/24bpp/32bpp modes Currently the 16-bit (32768 or 65536 colors), 24-bit (16M colors, packed pixel), and 32-bit (16M colors, sparse) pixel support in the SVGA server ! requires linear addressing. (This restriction may be removed in a future ver- sion, but with nearly all new cards using the PCI bus (where linear addressing - - - - - - - - - Information for Tseng Chipset Users - - - poses no problem), removing the linear addressing requirement presently has a ! lower priority than other features.) Option "linear" can be specified in a depth-specific screen section to enable linear addressing; a MemBase setting (in the device section) is probably also required on non-PCI based systems, and optionally on PCI systems that have trouble finding out for themselves where --- 830,843 ---- available. ! 14. Linear addressing and 16bpp/24bpp/32bpp modes Currently the 16-bit (32768 or 65536 colors), 24-bit (16M colors, packed pixel), and 32-bit (16M colors, sparse) pixel support in the SVGA server ! requires linear addressing. This restriction may be removed in a future ver- sion, but with nearly all new cards using the PCI bus (where linear addressing poses no problem), removing the linear addressing requirement presently has a ! lower priority than other features. Option "linear" can be specified in a depth-specific screen section to enable linear addressing; a MemBase setting (in the device section) is probably also required on non-PCI based systems, and optionally on PCI systems that have trouble finding out for themselves where *************** *** 678,685 **** tion. For the most part, many of the accelerated features in the 8bpp server have ! been implemented to support 16, 24, and 32 bpp modes for the W32p and the ET6000. So although there are now up to 4 times as many bits to display, the X server shouldn't feel overly sluggish. Note also that the 24bpp and 32bpp modes are only supported on a limited set of cards, and with at least 2Mb of memory. --- 849,868 ---- tion. For the most part, many of the accelerated features in the 8bpp server have ! been implemented to support 16, 24, and 32 bpp modes for the W32 and the ET6000. So although there are now up to 4 times as many bits to display, the X + + + + + + + + + Information for Tseng Chipset Users + + + server shouldn't feel overly sluggish. Note also that the 24bpp and 32bpp modes are only supported on a limited set of cards, and with at least 2Mb of memory. *************** *** 720,746 **** EndSection Information for Tseng Chipset Users ! 13. Trouble shooting with the SVGA Tseng driver ! First of all, make sure that the default modes selected from your XF86Config ! are supported by your monitor, i.e. make sure the horizontal sync limit is cor- ! rect. It is best to start with standard 640x480x256 with a 25.175 MHz clock (by ! specifying a single horizontal sync of 31.5) to make sure the driver works on ! your configuration. The default mode used will always be the first mode listed ! in the modes line, with the highest dot clock listed for that resolution in the ! timing section. Note that some VESA standard mode timings may give problems on some monitors (try increasing the horizontal sync pulse, i.e. the difference between the mid- dle two horizontal timing values, or try multiples of 16 or 32 for all of the --- 903,953 ---- EndSection + 15. Trouble shooting with the SVGA Tseng driver + First of all, make sure that the default modes selected from your XF86Config + are supported by your monitor, i.e. make sure the horizontal sync limit is cor- + rect. It is best to start with standard 640x480x256 with a 25.175 MHz clock (by + specifying a single horizontal sync of 31.5) to make sure the driver works on + your configuration. The default mode used will always be the first mode listed + in the modes line, with the highest dot clock listed for that resolution in the + timing section. + Some general hints: + o Put Option "slow_dram" in the Device Section. + + + + + Information for Tseng Chipset Users ! o Put Option "pci_burst_off" in the Device Section. ! o Put Option "w32_interleave_off" in the Device Section. + o Take out the Hercules monochrome adapter, if you have one. Many configu- + rations of the ET4000/W32 series do not allow one in the system. + + o Get a motherboard with its local bus running at 33 MHz. Many, if not all, + ET4000/W32 boards will surely behave in a funny way on a 50-MHz bus. You + may have to use a wait state or two, but first try without any. + + o Cold-boot your machine. Do not run anything that messes with the video + hardware, including other X servers, before running XF86_SVGA. + + o In case of an ET6000 card, try specifying chipset "et6000" in the Device + Section. The card normally auto-probes from the PCI bus, but on some sys- + tems, another on-board VGA card, although disabled, may cause the ET6000 + server to want to use the other card. + Note that some VESA standard mode timings may give problems on some monitors (try increasing the horizontal sync pulse, i.e. the difference between the mid- dle two horizontal timing values, or try multiples of 16 or 32 for all of the *************** *** 775,789 **** "1024x768" 65 1024 1116 1228 1328 768 783 789 818 - Crash or hang after start-up (probably with a black screen). - Try the "noaccel" option. Check that the BIOS settings are OK; in - particular, disable caching of 0xa0000-0xaffff. Disabling hidden - DRAM refresh may also help. - Crash, hang, or trash on the screen after a graphics operation. - This may be related to a bug in one of the accelerated functions, - or a problem with the BitBLT engine. Try the "noaccel" option. - Also check the BIOS settings. --- 982,988 ---- *************** *** 792,802 **** - Information for Tseng Chipset Users `ACL: TIMEOUT' messages from the server. Same as for the above entry. However, on some systems, the problem will not go away no matter what you do. It may be related to the --- 991,1014 ---- Information for Tseng Chipset Users + Crash or hang after start-up (probably with a black screen). + Try the "noaccel" option. Check that the BIOS settings are OK; in + particular, disable caching of 0xa0000-0xaffff. Disabling hidden + DRAM refresh may also help. + + On Linux systems, if "APM" (power management) support is enabled in + the kernel, the server may start up in power-save mode or with a + black screen. Rebuild your kernel with APM support disabled. + + Crash, hang, or trash on the screen after a graphics operation. + This may be related to a bug in one of the accelerated functions, + or a problem with the BitBLT engine. Try the "noaccel" option. + Also check the BIOS settings. + `ACL: TIMEOUT' messages from the server. Same as for the above entry. However, on some systems, the problem will not go away no matter what you do. It may be related to the *************** *** 837,842 **** --- 1049,1066 ---- If that doesn't help, disabling acceleration (option "noaccel") is the only solution. + + + + + + + + + Information for Tseng Chipset Users + + + Problems with DMA hardware (floppy, tape) On some systems, the accelerated server will interfere with other hardware that uses ISA DMA. Most notably is the PC floppy con- *************** *** 851,868 **** There are two possible solutions: disable acceleration using the "noaccel" option, or disable PCI-retry (which is causing the large bus delays) by removing the "pci_retry" option. This will cause a - - - - - - - - - Information for Tseng Chipset Users - - - very small slowdown of accelerated operations. The "pci_retry" option applies not only to the PCI bus systems, but --- 1075,1080 ---- *************** *** 877,887 **** "normal" statement to the Device section in your XF86Config file. In most cases, this will solve the color problem. ! For other screen drawing related problems, try the "noaccel" option. ! As a final fallback, consider trying the separate accelerated W32 server. It is ! more mature, and has been tested more extensively as a result. See README.W32. If you are having driver-related problems that are not addressed by this docu- ment, or if you have found bugs in accelerated functions, you can try contact- ing the XFree86 team. --- 1089,1111 ---- "normal" statement to the Device section in your XF86Config file. In most cases, this will solve the color problem. ! Why does the server report my ModeLine with only half the pixel clock? ! For ET4000W32p cards at 8bpp, some modes using a clock over 75 MHz ! (e.g. a 1152x910 mode with 95 MHz pixel clock) will produce the ! following message in the Xserver output: ! (--) SVGA: Mode "1152x910" will use pixel multiplexing + And later, when the accepted modelines are reported: + + (**) SVGA: Mode "1152x910": mode clock = 47.500 + + This is normal, because with pixel multiplexing, only half the + clock is needed as two pixels are sent to the RAMDAC per clock + pulse. + + For other screen drawing related problems, try the "noaccel" option. + If you are having driver-related problems that are not addressed by this docu- ment, or if you have found bugs in accelerated functions, you can try contact- ing the XFree86 team. *************** *** 891,954 **** (mail it to report@XFree86.org). You may want to keep an eye on forthcoming beta releases at www.xfree86.org. - Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/tseng.sgml,v 3.15.2.11 1997/08/02 13:48:15 dawes Exp $ - $TOG: README.tseng /main/13 1997/08/10 13:01:25 kaleb $ Information for Tseng Chipset Users --- 1115,1237 ---- (mail it to report@XFree86.org). You may want to keep an eye on forthcoming beta releases at www.xfree86.org. + Information for Tseng Chipset Users + 16. Acknowledgments + Most of these stem from the old XF86_W32 server. That code was used extensively + for getting the SVGA server to work on all the Tseng cards, so they are still + somewhat valid. + Glenn G. Lai wrote the original XF86_W32 server. It was modified by Dirk Hohn- + del and Koen Gadeyne to support some more hardware. + Jerry J. Shekhel (jerry@msi.com) gave me (GGL) the 1-M Mirage ET4000/W32 VLB + board on which the initial development (X_W32) was done. + X11R6 and The XFree86 Project provide the base code for XF86_W32. + Hercules Computer Technology Inc. lent me (GGL) a 2-M Hercules Dynamite Pro VLB + board for the development that led to XF86_W32. They donated a Dynamite Power + PCI to The XFree86 Project, that was used by DHH to extend the server. + Tseng Labs kindly donated (KMG) an ET6000-based board (a Jazz Multimedia G- + Force 128), which spurred the development of the ET6000 code. They also pro- + vided an ET6100 evaluation board. + Heiko Eissfeldt provided an ET4000W32p_rev_b board which allowed us to get bet- + ter support for those rev_a and rev_b boards. + Numerous testers have given me feedback for X_W32 and later XF86_W32. I apolo- + gize for my failure to keep track of the people who tested X_W32, but the names + of the people involved with the XF86_W32 testing are listed below: + Linux: + bf11620@coewl.cen.uiuc.edu (Byron Thomas Faber) + dlj0@chern.math.lehigh.edu (David Johnson) + peterc@a3.ph.man.ac.uk (Peter Chang) + dmm0t@rincewind.mech.virginia.edu (David Meyer) + nrh@philabs.Philips.COM (Nikolaus R. Haus) + jdooley@dbp.caltech.edu (James Dooley) + thumper@hitchcock.eng.uiowa.edu (Timothy Paul Schlie) + klatta@pkdla5.syntex.com (Ken Latta) + robinson@cnj.digex.net (Andrew Robinson) + reggie@phys.washington.edu (Reginald S. Perry) + sjm@cs.tut.fi (M{kinen Sami J) + engel@yacc.central.de (C. Engelmann) use cengelm@gwdg.de + + + + + + + + Information for Tseng Chipset Users + postgate@cafe.net (Richard Postgate) + are1@cec.wustl.edu (Andy Ellsworth) + bill@celtech.com (Bill Foster) + FreeBSD: + ljo@ljo-slip.DIALIN.CWRU.Edu (L Jonas Olsson) + Several people have developed code for the SVGA Tseng driver (this list is + incomplete): + o Glenn G. Lai + o Dirk H. Hohndel + o Koen Gadeyne + o OEyvind Aabling + o Dejan Ilic + o Mark Vojkovich + o Harald Nordgard Hansen + o David Bateman + o Gyorgy Krajcsovits + o Kurt Olsen + Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/tseng.sgml,v 3.15.2.13 1998/02/20 23:10:32 dawes Exp $ + $TOG: README.tseng /main/15 1998/03/09 13:00:28 kaleb $ *************** *** 972,977 **** --- 1255,1261 ---- + Information for Tseng Chipset Users *************** *** 995,1029 **** - CONTENTS - 1. Supported chipsets ..................................................... 1 - 2. ET4000 driver features ................................................. 1 - 3. ET6000 driver features ................................................. 2 - 4. Clock selection problems with some ET4000 boards ....................... 3 - 5. Basic configuration .................................................... 4 - 6. general options in the XF86Config file ................................. 4 - 7. linear memory base address (MemBase) issues ............................ 6 - 8. Mode issues ............................................................ 8 - 9. Acceleration issues .................................................... 8 - 10. ET6000 memory size facts and fiction ................................... 9 - 11. ET6000 memory bandwidth hype and the impact on video modes ............ 10 - 12. Linear addressing and 16bpp/24bpp/32bpp modes ......................... 10 - 13. Trouble shooting with the SVGA Tseng driver ............................ 12 --- 1279,1299 ---- *************** *** 1051,1058 **** i ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/README.tseng,v 3.24.2.11 1997/08/02 13:53:33 dawes Exp $ --- 1321,1388 ---- + + + + + CONTENTS + + + + 1. Supported chipsets ..................................................... 1 + + 2. Terminology ............................................................ 1 + + 3. ET4000 driver features ................................................. 1 + + 4. ET6000 driver features ................................................. 3 + + 5. Clock selection problems with some ET4000 boards ....................... 4 + + 6. Text mode restore problems ............................................. 4 + + 7. Basic configuration .................................................... 4 + + 8. general options in the XF86Config file ................................. 5 + + 9. linear memory base address (MemBase) issues ............................ 7 + 9.1 What you should know BEFORE trying another MemBase .................. 7 + 9.2 Choosing a MemBase .................................................. 7 + 9.3 An alternative approach ............................................. 8 + 9.4 When all else fails... .............................................. 8 + 9.5 Restrictions ........................................................ 8 + 9.6 Some boards simply cannot work in linear mode ....................... 9 + 9.7 How can I see if the linear address is wrong? ....................... 9 + + 10. Mode issues ........................................................... 10 + + 11. Acceleration issues ................................................... 11 + + 12. ET6000 memory size facts and fiction .................................. 11 + + 13. ET6000 memory bandwidth hype and the impact on video modes ............ 12 + + 14. Linear addressing and 16bpp/24bpp/32bpp modes ......................... 13 + + 15. Trouble shooting with the SVGA Tseng driver ............................ 14 + + 16. Acknowledgments ....................................................... 18 + + + + + + + + + + + + + + i ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/README.tseng,v 3.24.2.13 1998/02/20 23:14:32 dawes Exp $ *** ./programs/Xserver/hw/xfree86/doc/VideoModes.doc@@/PUBLIC-LATEST Sat Jul 19 10:30:08 1997 --- xc/programs/Xserver/hw/xfree86/doc/VideoModes.doc Fri Mar 6 16:38:29 1998 *************** *** 1,580 **** - The Hitchhiker's Guide to X386/XFree86 Video Timing - (or, Tweaking your Monitor for Fun and Profit) - Eric S. Raymond esr@snark.thyrsus.com (from an original by Chin - Fang fangchin@leland.stanford.edu; portions derive from a how-to by - Bob Crosson crosson@cam.nist.gov) - This is version 1.0, Jan 8th 1993. - 1. Introduction - Please direct comments, criticism, and suggestions for improvement to - esr@snark.thyrsus.com. - The XFree86 server allows users to configure their video subsystem and - thus encourages best use of existing hardware. This tutorial is - intended to help you learn how to generate your own timing numbers to - make optimum use of your video card and monitor. - We'll present a method for getting something that works, and then show - you how you can experiment starting from that base to develop settings - that optimize for your taste. - If you already have a mode that almost works (in particular, if one of - predefined VESA modes gives you a stable display but one that's - displaced right or left, or too small, or too large) you can go - straight to the section on Fixing Problems. This will enlighten you - on ways to tweak the timing numbers to achieve particular effects. - XFree86 allows you to hot-key between different modes defined in - XF86Config (see XF86Config.man for details). Use this capability to - save yourself hassles! When you want to test a new mode, give it a - unique mode label and add it to the end your hot-key list. Leave a - known-good mode as the default to fall back on if the test mode - doesn't work. The Xconfig section at the end of the second Example - Calculation provides a good example of how to record your experiments - in a way that will help you quickly converge on a solution. - First check out the Monitors file in lib/X11/doc If your monitor is in - it, you can probably skip the rest of this document! You may need to - scale some of the timing numbers if the clock used to generate the - mode in the database doesn't match what your card has available, but - that's easy. - 2. How Video Displays Work ! Knowing how the display works is essential to understanding what ! numbers to put in the various fields in the file Xconfig. Those ! values are used in the lowest levels of controlling the display by the ! XFree86 server. ! The display generates a picture from a series of dots. The dots are ! arranged from left to right to form lines. The lines are arranged ! from top to bottom to form the picture. The dots emit light when they ! are struck by the electron beam inside the display. To make the beam ! strike each dot for an equal amount of time, the beam is swept across ! the display in a constant pattern. ! The pattern starts at the top left of the screen, goes across the ! screen to the right in a straight line, and stops temporarily on the ! right side of the screen. Then the beam is swept back to the left ! side of the display, but down one line. The new line is swept from ! left to right just as the first line was. This pattern is repeated ! until the bottom line on the display has been swept. Then the beam is ! moved from the bottom right corner of the display to the top left ! corner, and the pattern is started over again. - Starting the beam at the top left of the display is called the - beginning of a frame. The frame ends when the beam reaches the the - top left corner again as it comes from the bottom right corner of the - display. A frame is made up of all of the lines the beam traced from - the top of the display to the bottom. ! If the electron beam were on all of the time it was sweeping through ! the frame, all of the dots on the display would be illuminated. There ! would be no black border around the edges of the display. At the ! edges of the display the picture would become distorted because the ! beam is hard to control there. To reduce the distortion, the dots ! around the edges of the display are not illuminated by the beam even ! though the beam may be pointing at them. The viewable area of the ! display is reduced this way. ! Another important thing to understand is what becomes of the beam when ! no spot is being painted on the visible area. The time the beam would ! have been illuminating the side borders of the display is used for ! sweeping the beam back from the right edge to the left and moving the ! beam down to the next line. The time the beam would have been ! illuminating the top and bottom borders of the display is used for ! moving the beam from the bottom-right corner of the display to the ! top-left corner. - The adapter card generates the signals which cause the display to turn - on the electron beam at each dot to generate a picture. The card also - controls when the display moves the beam from the right side to the - left and down a line by generating a signal called the horizontal sync - (for synchronization) pulse. One horizontal sync pulse occurs at the - end of every line. The adapter also generates a vertical sync pulse - which signals the display to move the beam to the top-left corner of - the display. A vertical sync pulse is generated near the end of every - frame. - The display requires that there be short time periods both before and - after the horizontal and vertical sync pulses so that the position of - the electron beam can stabilize. If the beam can't stabilize, the - picture will not be steady. ! In a later section, we'll come back to these basics with definitions, ! formulas and examples to help you use them. ! 3. Basic Things to Know about your Display and Adapter ! There are some fundamental things you need to know before hacking an ! Xconfig entry. These are: ! 1. your monitor's horizontal and vertical sync frequency options - 2. your video adapter's driving clock frequency, or "dot clock" ! 3. your monitor's bandwidth ! The monitor sync frequencies: ! The horizontal sync frequency are just the number of times per second ! the monitor can write a horizontal scan line; it is the single most ! important statistic about your monitor. The vertical sync frequency ! is the number of times per second the monitor can traverse its beam ! vertically. ! Sync frequencies are usually listed on the specifications page of your ! monitor manual. The vertical sync frequency number is typically ! calibrated in Hz (cycles per second), the horizontal one in KHz ! (kilocycles per second). The usual ranges are between 50 and 80Hz - vertical, and between 31 and 135KHz horizontal. - If you have a multisync monitor, these frequencies will be given as - ranges. Some monitors, especially lower-end ones, have multiple fixed - frequencies. These can be configured too, but your options will be - severely limited by the built-in monitor characteristics. Choose the - highest frequency pair for best resolution. And be careful --- trying - to clock a fixed-frequency monitor at a higher speed than it's - designed for can damage it. - The card driving clock frequency: - Your video adapter manual's spec page will usually give you the card's - dot clock (that is, the total number of pixels per second it can write - to the screen). If you don't have this information, the X server will - get it for you. Even if your X locks up your monitor, it will emit a - line of clock and other info to standard output. If you redirect this - to a file, it should be saved even if you have to reboot to get your - console back. - If you're using SGCS X, the line will look something like the - following example, collected from a Swan local-bus S3 adapter. - XFree86 uses a slightly different multi-line format. - WGA: 86C911 (mem: 1024k clocks: 25 28 40 3 50 77 36 45 0 0 79 31 94 65 75 71) - --- ------ ----- -------------------------------------------- - | | | Possible driving frequencies in MHz - | | +-- Size of on-board frame-buffer RAM - | +-- Chip type - +-- Server type ! Note: do this with your machine unloaded (if at all possible). ! Because X is an application, its timing loops can collide with disk ! activity, rendering the numbers above inaccurate. Do it several times ! and watch for the numbers to stabilize; if they don't, start killing ! processes until they do. SVr4 users: the mousemgr process is ! particularly likely to mess you up. ! In order to avoid the clock-probe inaccuracy, you should clip out the ! clock timings and put them in your Xconfig as the value of the Clocks ! property --- this suppresses the timing loop and gives X an exact list ! of the clock values it can try. Using the data from the example ! above: ! wga ! Clocks 25 28 40 3 50 77 36 45 0 0 79 31 94 65 75 71 ! On systems with a highly variable load, this may help you avoid ! mysterious X startup failures. It's possible for X to come up, get ! its timings wrong due to system load, and then not be able to find a ! matching dot clock in its config database --- or find the wrong one! - The monitor's video bandwidth: - Finally, it's useful to know your monitor's video bandwidth, so you - know approximately what the highest dot clock you can use is. There's - a lot of give here, though --- some monitors can run as much as 30% - over their nominal bandwidth. - Knowing the bandwidth will enable you to make more intelligent choices - between possible configurations. It may affect your display's visual - quality (esp. sharpness for fine details). - Your monitor's video bandwidth should be included on the manual's spec - page. If it's not, look at the monitor's highest rated resolution. - As a rule of thumb, here's how to translate these into bandwidth - estimates (and thus into rough upper bounds for the dot clock you can - use): - 640x480 25 - 800x600 36 - 1024x768 65 - 1024x768 interlaced 45 - 1280x1024 110 - BTW, there's nothing magic about this table; these numbers are just - the lowest dot clocks per resolution in the standard XFree86 Modes - database. The bandwidth of your monitor may be higher than the - minimum needed for its top resolution, so don't be afraid to try a dot - clock a few MHz higher. - Also note that bandwidth is seldom an issue for dot clocks under 65MHz - or so. With an SVGA and most hi-res monitors, you can't get anywhere - near the limit of your monitor's video bandwidth. The following are - examples: - Brand Video Bandwidth - ---------- --------------- - NEC 4D 75Mhz - Nano 907a 50Mhz - Nano 9080i 60Mhz - Mitsubishi HL6615 110Mhz - Mitsubishi Diamond Scan 100Mhz - IDEK MF-5117 65Mhz - IOCOMM Thinksync-17 CM-7126 136Mhz - HP D1188A 100Mhz - Philips SC-17AS 110Mhz - Swan SW617 85Mhz - Even low-end monitors usually aren't terribly bandwidth-constrained - for their rated resolutions. The NEC Multisync II makes a good - example --- it can't even display 800x600 per its spec. It can only - display 800x560. For such low resolutions you don't need high dot - clocks or a lot of bandwidth; probably the best you can do is 32Mhz or - 36Mhz, both of them are still not too far from the monitor's rated - video bandwidth of 30Mhz. ! At these two driving frequencies, your screen image may not be as ! sharp as it should be, but definitely of tolerable quality. Of course ! it would be nicer if NEC Multisync II had a video bandwidth higher - than, say, 36Mhz. But this is not critical for common tasks like text - editing, as long as the difference is not so significant as to cause - severe image distortion (your eyes would tell you right away if this - were so). - What these control: ! The sync frequency ranges of your monitor, together with your video ! adapter's dot clock, determine the ultimate resolution that you can ! use. But it's up to the driver to tap the potential of your hardware. ! A superior hardware combination without an equally competent device ! driver is a waste of money. On the other hand, with a versatile ! device driver but less capable hardware, you can push the hardware's ! envelope a little. This is the design philosophy of XFree86. - 4. Interpreting the Basic Specifications ! This section explains what the specifications above mean, and some ! other things you'll need to know. First, some definitions. Next to ! each in parens is the variable name we'll use for it when doing ! calculations ! horizontal sync frequency (HSF) ! Horizontal scans per second (see above). ! vertical sync frequency (VSF) ! Vertical scans per second (see above). Mainly important as the ! upper limit on your refresh rate. - dot clock (DCF) - More formally, `driving clock frequency'; sometimes loosely - called `bandwidth'. The frequency of the crystal or VCO on your - adaptor --- the maximum dots-per-second it can emit. ! video bandwidth (VB) ! The highest frequency at which your monitor's video signal can ! change. This constrains the highest dot clock you can use and ! the overall sharpness of fine details in the video image. ! frame length (HFL, VFL) ! Horizontal frame length (HFL) is the number of dot-clock ticks ! needed for your monitor's electron gun to scan one horizontal ! line, *including the inactive left and right borders*. Vertical ! frame length (VFL) is the number of scan lines in the *entire* ! image, including the inactive top and bottom borders. ! screen refresh rate (RR) ! The number of times per second your screen is repainted. Higher ! frequencies are better, as they reduce flicker. 60Hz is good, ! VESA-standard 72Hz is better. Compute it as - RR = DCF / (HFL * VFL) - Note that the product in the denominator is *not* the same as the - monitor's visible resolution, but typically somewhat larger. We'll - get to the details of this below. - About Bandwidth: - Monitor makers like to advertise high bandwidth because it constrains - the sharpness of intensity and color changes on the screen. A high - bandwidth means smaller visible details. - Your monitor uses electronic signals to present an image to your eyes. - Such signals always come in in wave form once they are converted into - analog form from digitized form. They can be considered as - combinations of many simpler wave forms each one of which has a fixed - frequency, many of them are in the Mhz range, eg, 20Mhz, 40Mhz, or - even 70Mhz. Your monitor video bandwidth is, effectively, the - highest-frequency analog signal it can handle without distortion. ! For our purposes, bandwidth is mainly important as an approximate ! cutoff point for the highest dot clock you can use. - Sync Frequencies snd the Refresh Rate: - Each horizontal scan line on the display is just the visible portion - of a frame-length scan. At any instant there is actually only one dot - active on the screen, but with a fast enough refresh rate your eye's - persistence of vision enables you to "see" the whole image. ! Here are some pictures to help: ! _______________________ ! | | The horizontal frame length ! |->->->->->->->->->->-> | is the time in dot clocks ! | )| required for the ! |<-----<-----<-----<--- | electron beam to trace ! | | a pattern like this ! | | ! | | ! | | ! |_______________________| ! _______________________ ! | ^ | The vertical frame length ! | ^ | | is the time in dot clocks ! | | v | required for the ! | ^ | | electron beam to trace ! | | | | a pattern like this ! | ^ | | ! | | v | ! | ^ | | ! |_______|_v_____________| ! Remember that the actual raster scan is a very tight zigzag pattern; ! that is, the beam moves left <-> right and at the same time up <-> ! down. ! Now we can see how the dot clock and frame size relates to refresh ! rate. By definition, one hertz (hz) is one cycle per second. So, if ! your horizontal frame length is HFL and your vertical frame length is ! VFL, then to cover the entire screen takes (HFL * VFL) ticks. Since ! your card emits DCF ticks per second by definition, then obviously ! your monitor's electron gun(s) can sweep the screen from left to right ! and back and from bottom to top and back DCF / (HFL * VFL) times/sec. ! This is your screen's refresh rate, because it's how many times your ! screen can be updated thus REFRESHED per second! ! You need to understand this concept to design a configuration which ! trades off resolution against flicker in whatever way suits your ! needs. ! 5. Tradeoffs in Configuring your System ! Another way to look at the formula we derived above is ! DCF = RR * HFL * VFL ! That is, your dot clock is fixed. You can use those dots per second ! to buy either refresh rate, horizontal resolution, or vertical resolu- ! tion. If one of those increases, one or both of the others must ! decrease. ! Note, though, that your refresh rate cannot be greater than the ! maximum vertical sync frequency of your monitor. Thus, for any given ! monitor at a given dot clock, there is a minimum product of frame ! lengths below which you can't force it. ! In choosing your settings, remember: if you set RR too low, you will ! get mugged by screen flicker. - You probably do not want to pull your refresh rate below 60Hz. This - is the flicker rate of fluorescent lights; if you're sensitive to - those, you need to hang with 72MHz, the VESA ergonomic standard. - Flicker is very eye-fatiguing, though human eyes are adaptable and - peoples' tolerance for it varies widely. If you face your monitor at - a 90% viewing angle, are using a dark background and a good - contrasting color for foreground, and stick with low to medium - intensity, you *may* be comfortable at as little as 45Hz. ! The acid test is this: open a xterm with pure white back-ground and ! black foreground using xterm -bg white -fg black and make it so large ! as to cover the entire viewable area. Now turn your monitor's ! intensity to 3/4 of its maximum setting, and turn your face away from ! the monitor. Try peeking at your monitor sideways (bringing the more ! sensitive peripheral-vision cells into play). If you don't sense any ! flicker or if you feel the flickering is tolerable, then that refresh ! rate is fine with you. Otherwise you better configure a higher ! refresh rate, because that semi-invisible flicker is going to fatigue ! your eyes like crazy and give you headaches, even if the screen looks ! OK to normal vision. - So let's say you've picked a minimum acceptable refresh rate. In - choosing your HFL and VFL, you'll have some room for maneuver. - 6. Memory Requirements - Available frame-buffer RAM may limit the resolution you can achieve on - color or gray-scale displays. It probably isn't a factor on displays - that have only two colors, white and black with no shades of gray in - between. - For 256-color displays, a byte of video memory is required for each - visible dot to be shown. This byte contains the information that - determines what mix of red, green, and blue is generated for its dot. - To get the amount of memory required, multiply the number of visible - dots per line by the number of visible lines. For a display with a - resolution of 800x600, this would be 800 x 600 = 480,000, which is the - number of visible dots on the display. This is also, at one byte per - dot, the number of bytes of video memory that are necessary on your - adapter card. ! Thus, your memory requirement will typically be (HR * VR)/1024 Kbytes ! of VRAM, rounded up. In the example case, we'd need (936 * 702)/1024 ! = 642K. So if you have one meg, you'll have extra for virtual-screen ! panning. - However, if you only have 512K on board, then you can't use this - resolution. Even if you have a good monitor, without enough video - ram, you can't take advantage of your monitor's potential. On the - other hand, if your SVGA has one meg, but your monitor can display at - most 800x600, then high resolution is beyond your reach anyway. - Don't worry if you have more memory than required; XFree86 will make - use of it by allowing you to scroll your viewable area (see the - Xconfig file documentation on the virtual screen size parameter). - Remember also that a card with 512K bytes of memory really doesn't - have 512,000 bytes installed, it has 512 x 1024 = 524,288 bytes. ! If you're running SGCS X using an S3 card, and are willing to live ! with 16 colors (4 bits per pixel), you can set depth 4 in Xconfig and ! effectively double the resolution your card can handle. S3 cards, for ! example, normally do 1024x768x256. You can make them do 1280x1024x16 ! with depth 4. ! 7. Computing Frame Sizes ! Warning: this method was developed for multisync monitors. It will ! probably work with fixed-frequency monitors as well, but no ! guarantees! ! Start by dividing DCF by your highest available HSF to get the number ! of horizontal sweeps per second available. ! For example; suppose you have a Sigma Legend SVGA with a 65MHz dot ! clock, and your monitor has a 55KHz horizontal scan frequency. The ! quantity (DCF / HSF) is then 1181. ! Now for our first bit of black magic. You need to round this figure ! to the nearest multiple of 8. This has to do with the VGA hardware ! controller used by SVGA and S3 cards; it uses an 8-bit register, left- ! shifted 3 bits, for what's really an 11-bit quantity. Other card ! types such as ATI 8514/A may not have this requirement, but we don't ! know and the correction can't hurt. So round the usable horizontal ! scans per second figure to 1176. ! This figure (DCF / HSF rounded to a multiple of 8) is the minimum HFL ! you can use. You can get longer HFLs (and thus, possibly, more ! horizontal dots on the screen) by setting the sync pulse to produce a ! lower HSF. But you'll pay with a slower and more visible flicker ! rate. ! As a rule of thumb, 80% of the horizontal frame length is available ! for horizontal resolution, the visible part of the horizontal scan ! line (this allows, roughly, for borders and sweepback time -- that is, ! the time required for the beam to move from the right screen edge to ! the left edge of the next raster line). In this example, that's 944 ! ticks. ! Now, to get the normal 4:3 screen aspect ratio, set your vertical ! resolution to 3/4ths of the horizontal resolution you just calculated. ! For this example, that's 708 ticks. To get your actual VFL, multiply ! that by 1.05 to get 743 ticks. ! About that 4:3 --- a ratio of 4:3 for width to height of the displayed ! area approximates the Golden Section, (1 + sqrt(5))/2. Human beings ! seem to be wired to find this kind of rectangle pleasant to look at; ! accordingly, video tubes and the standard resolutions such as 800x600, ! 640x480 and 1024x768 all approximate it. Though it's psychologically ! magic, it's not technically magic; nothing prevents you from using a ! non-Golden-Section ratio if that will get the best use out of your ! screen real estate. ! So, HFL=1176 and VFL=743. Dividing 65MHz by the product of the two ! gives us a nice, healthy 74.4Hz refresh rate. Excellent! Better than ! VESA standard! And you got 944x708 to boot, more than the 800 by 600 ! you were probably expecting. Not bad at all! - You can even improve the refresh rate further, to almost 76 Hz, by - using the fact that monitors can often sync horizontally at 2khz or so - higher than rated, and by lowering VFL somewhat (that is, taking less - than 75% of 944 in the example above). But before you try this - "overdriving" maneuver, if you do, make *sure* that your monitor - electron guns can sync up to 76 Hz vertical. (the popular NEC 4D, for - instance, cannot. It goes only up to 75 Hz VSF). - So far, most of this is simple arithmetic and basic facts about raster - displays. Hardly any black magic at all! - 8. Black Magic and Sync Pulses - OK, now you've computed HFL/VFL numbers for your chosen dot clock, - found the refresh rate acceptable, and checked that you have enough - VRAM. Now for the real black magic -- you need to know when and where - to place synchronization pulses. - The sync pulses actually control the horizontal and vertical scan - frequencies of the monitor. The HSF and VSF you've pulled off the - spec sheet are nominal, approximate maximum sync frequencies. The - sync pulse in the signal from the adapter card tells the monitor how - fast to actually run. - Recall the two pictures above? Only part of the time required for - raster-scanning a frame is used for displaying viewable image (ie. - your resolution). - Horizontal Sync: ! By previous definition, it takes HFL ticks to trace the a horizontal ! scan line. Let's call the visible tick count (your horizontal screen ! resolution) HR. Then Obviously, HR < HFL by definition. For ! concreteness, let's assume both start at the same instant as shown ! below: --- 1,1262 ---- ! XFree86 Video Timings HOWTO ! Eric S. Raymond ! Version 3.0, 8 Aug 1997 ! Abstract ! How to compose a mode line for your card/monitor combination under ! XFree86. The XFree86 distribution now includes good facilities for ! configuring most standard combinations; this document is mainly use- ! ful if you are tuning a custom mode line for a high-performance moni- ! tor or very unusual hardware. It may also help you in using xvidtune ! to tweak a standard mode that is not quite right for your monitor. ! 1. Disclaimer ! You use the material herein SOLELY AT YOUR OWN RISK. It is possible to harm ! both your monitor and yourself when driving it outside the manufacturer's ! specs. Read Overdriving Your Monitor (section 11., page 18) for detailed cau- ! tions. Any damages to you or your monitor caused by overdriving it are your ! problem. ! The most up-to-date version of this HOWTO can be found at the Linux Documenta- ! tion Project web page. ! Please direct comments, criticism, and suggestions for improvement to ! esr@snark.thyrsus.com. Please do not send email pleading for a magic solution ! to your special monitor problem, as doing so will only burn up my time and ! frustrate you -- everything I know about the subject is already in here. ! 2. Introduction ! The XFree86 server allows users to configure their video subsystem and thus ! encourages best use of existing hardware. This tutorial is intended to help ! you learn how to generate your own timing numbers to make optimum use of your ! video card and monitor. ! We'll present a method for getting something that works, and then show you how ! you can experiment starting from that base to develop settings that optimize ! for your taste. ! Starting with XFree86 3.2, XFree86 provides an XF86Setup(1) program that makes ! it easy to generate a working monitor mode interactively, without messing with ! video timing number directly. So you shouldn't actually need to calculate a ! base monitor mode in most cases. Unfortunately, XF86Setup(1) has some limita- ! tions; it only knows about standard video modes up to 1280x1024. If you have a ! ! ! XFree86 Video Timings HOWTO ! ! ! ! ! ! XFree86 Video Timings HOWTO ! ! ! ! very high-performance monitor capable of 1600x1200 or more you will still have ! to compute your base monitor mode yourself. ! ! Recent versions of XFree86 provide a tool called xvidtune(1) which you will ! probably find quite useful for testing and tuning monitor modes. It begins ! with a gruesome warning about the possible consequences of mistakes with it. ! If you pay careful attention to this document and learn what is behind the ! pretty numbers in xvidtune's boxes, you will become able to use xvidtune effec- ! tively and with confidence. ! ! If you already have a mode that almost works (in particular, if one of prede- ! fined VESA modes gives you a stable display but one that's displaced right or ! left, or too small, or too large) you can go straight to the section on Fixing ! Problems with the Image (section 14., page 21). This will enlighten you on ! ways to tweak the timing numbers to achieve particular effects. ! ! If you have xvidtune(1), you'll be able to test new modes on the fly, without ! modifying your X configuration files or even rebooting your X server. Other- ! wise, XFree86 allows you to hot-key between different modes defined in Xconfig ! (see XFree86.man for details). Use this capability to save yourself hassles! ! When you want to test a new mode, give it a unique mode label and add it to the ! end of your hot-key list. Leave a known-good mode as the default to fall back ! on if the test mode doesn't work. ! ! ! 3. How Video Displays Work ! ! Knowing how the display works is essential to understanding what numbers to put ! in the various fields in the file Xconfig. Those values are used in the lowest ! levels of controlling the display by the XFree86 server. ! ! The display generates a picture from a series of dots. The dots are arranged ! from left to right to form lines. The lines are arranged from top to bottom to ! form the picture. The dots emit light when they are struck by the electron ! beam inside the display. To make the beam strike each dot for an equal amount ! of time, the beam is swept across the display in a constant pattern. ! ! The pattern starts at the top left of the screen, goes across the screen to the ! right in a straight line, and stops temporarily on the right side of the ! screen. Then the beam is swept back to the left side of the display, but down ! one line. The new line is swept from left to right just as the first line was. ! This pattern is repeated until the bottom line on the display has been swept. ! Then the beam is moved from the bottom right corner of the display to the top ! left corner, and the pattern is started over again. ! ! There is one variation of this scheme known as interlacing: here only every ! second line is swept during one half-frame and the others are filled in in dur- ! ing a second half-frame. ! ! Starting the beam at the top left of the display is called the beginning of a ! frame. The frame ends when the beam reaches the the top left corner again as ! it comes from the bottom right corner of the display. A frame is made up of ! all of the lines the beam traced from the top of the display to the bottom. ! ! ! ! ! ! ! ! ! ! XFree86 Video Timings HOWTO ! ! ! ! If the electron beam were on all of the time it was sweeping through the frame, ! all of the dots on the display would be illuminated. There would be no black ! border around the edges of the display. At the edges of the display the pic- ! ture would become distorted because the beam is hard to control there. To ! reduce the distortion, the dots around the edges of the display are not illumi- ! nated by the beam even though the beam may be pointing at them. The viewable ! area of the display is reduced this way. ! ! Another important thing to understand is what becomes of the beam when no spot ! is being painted on the visible area. The time the beam would have been illu- ! minating the side borders of the display is used for sweeping the beam back ! from the right edge to the left and moving the beam down to the next line. The ! time the beam would have been illuminating the top and bottom borders of the ! display is used for moving the beam from the bottom-right corner of the display ! to the top-left corner. ! ! The adapter card generates the signals which cause the display to turn on the ! electron beam at each dot to generate a picture. The card also controls when ! the display moves the beam from the right side to the left and down a line by ! generating a signal called the horizontal sync (for synchronization) pulse. ! One horizontal sync pulse occurs at the end of every line. The adapter also ! generates a vertical sync pulse which signals the display to move the beam to ! the top-left corner of the display. A vertical sync pulse is generated near ! the end of every frame. ! ! The display requires that there be short time periods both before and after the ! horizontal and vertical sync pulses so that the position of the electron beam ! can stabilize. If the beam can't stabilize, the picture will not be steady. ! ! In a later section, we'll come back to these basics with definitions, formulas ! and examples to help you use them. ! ! ! 4. Basic Things to Know about your Display and Adapter ! ! There are some fundamental things you need to know before hacking an Xconfig ! entry. These are: ! ! o your monitor's horizontal and vertical sync frequency options ! ! o your video adapter's driving clock frequency, or "dot clock" ! ! o your monitor's bandwidth ! ! The monitor sync frequencies: ! ! The horizontal sync frequency is just the number of times per second the moni- ! tor can write a horizontal scan line; it is the single most important statistic ! about your monitor. The vertical sync frequency is the number of times per ! second the monitor can traverse its beam vertically. ! ! Sync frequencies are usually listed on the specifications page of your monitor ! manual. The vertical sync frequency number is typically calibrated in Hz ! (cycles per second), the horizontal one in KHz (kilocycles per second). The ! ! ! ! ! ! ! ! ! XFree86 Video Timings HOWTO ! ! ! ! usual ranges are between 50 and 150Hz vertical, and between 31 and 135KHz hori- ! zontal. ! ! If you have a multisync monitor, these frequencies will be given as ranges. ! Some monitors, especially lower-end ones, have multiple fixed frequencies. ! These can be configured too, but your options will be severely limited by the ! built-in monitor characteristics. Choose the highest frequency pair for best ! resolution. And be careful --- trying to clock a fixed-frequency monitor at a ! higher speed than it's designed for can easily damage it. ! ! Earlier versions of this guide were pretty cavalier about overdriving multisync ! monitors, pushing them past their nominal highest vertical sync frequency in ! order to get better performance. We have since had more reasons pointed out to ! us for caution on this score; we'll cover those under Overdriving Your Monitor ! (section 11., page 18) below. ! ! The card driving clock frequency: ! ! Your video adapter manual's spec page will usually give you the card's dot ! clock (that is, the total number of pixels per second it can write to the ! screen). If you don't have this information, the X server will get it for you. ! Even if your X locks up your monitor, it will emit a line of clock and other ! info to standard output. If you redirect this to a file, it should be saved ! even if you have to reboot to get your console back. (Recent versions of the X ! servers all support a --probeonly option that prints out this information and ! exits without actually starting up X or changing the video mode.) ! ! Your X startup message should look something like one of the following exam- ! ples: ! ! If you're using XFree86: ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! XFree86 Video Timings HOWTO ! ! ! ! Xconfig: /usr/X11R6/lib/X11/Xconfig ! (**) stands for supplied, (--) stands for probed/default values ! (**) Mouse: type: MouseMan, device: /dev/ttyS1, baudrate: 9600 ! Warning: The directory "/usr/andrew/X11fonts" does not exist. ! Entry deleted from font path. ! (**) FontPath set to "/usr/lib/X11/fonts/misc/,/usr/lib/X11/fonts/75dpi/" ! (--) S3: card type: 386/486 localbus ! (--) S3: chipset: 924 ! --- ! Chipset -- this is the exact chip type; an early mask of the 86C911 ! ! (--) S3: chipset driver: s3_generic ! (--) S3: videoram: 1024k ! ----- ! Size of on-board frame-buffer RAM ! ! (**) S3: clocks: 25.00 28.00 40.00 3.00 50.00 77.00 36.00 45.00 ! (**) S3: clocks: 0.00 0.00 79.00 31.00 94.00 65.00 75.00 71.00 ! ------------------------------------------------------ ! Possible driving frequencies in MHz ! ! (--) S3: Maximum allowed dot-clock: 110MHz ! ------ ! Bandwidth ! (**) S3: Mode "1024x768": mode clock = 79.000, clock used = 79.000 ! (--) S3: Virtual resolution set to 1024x768 ! (--) S3: Using a banksize of 64k, line width of 1024 ! (--) S3: Pixmap cache: ! (--) S3: Using 2 128-pixel 4 64-pixel and 8 32-pixel slots ! (--) S3: Using 8 pages of 768x255 for font caching ! ! If you're using SGCS or X/Inside X: ! ! WGA: 86C911 (mem: 1024k clocks: 25 28 40 3 50 77 36 45 0 0 79 31 94 65 75 71) ! --- ------ ----- -------------------------------------------- ! | | | Possible driving frequencies in MHz ! | | +-- Size of on-board frame-buffer RAM ! | +-- Chip type ! +-- Server type ! ! Note: do this with your machine unloaded (if at all possible). Because X is an ! application, its timing loops can collide with disk activity, rendering the ! numbers above inaccurate. Do it several times and watch for the numbers to ! stabilize; if they don't, start killing processes until they do. SVr4 users: ! the mousemgr process is particularly likely to mess you up. ! ! In order to avoid the clock-probe inaccuracy, you should clip out the clock ! timings and put them in your Xconfig as the value of the Clocks property --- ! this suppresses the timing loop and gives X an exact list of the clock values ! it can try. Using the data from the example above: ! ! wga ! Clocks 25 28 40 3 50 77 36 45 0 0 79 31 94 65 75 71 + XFree86 Video Timings HOWTO ! On systems with a highly variable load, this may help you avoid mysterious X ! startup failures. It's possible for X to come up, get its timings wrong due to ! system load, and then not be able to find a matching dot clock in its config ! database --- or find the wrong one! ! 4.1 The monitor's video bandwidth: + If you're running XFree86, your server will probe your card and tell you what + your highest-available dot clock is. + Otherwise, your highest available dot clock is approximately the monitor's + video bandwidth. There's a lot of give here, though --- some monitors can run + as much as 30% over their nominal bandwidth. The risks here have to do with + exceeding the monitor's rated vertical-sync frequency; we'll discuss them in + detail below. ! Knowing the bandwidth will enable you to make more intelligent choices between ! possible configurations. It may affect your display's visual quality (espe- ! cially sharpness for fine details). + Your monitor's video bandwidth should be included on the manual's spec page. + If it's not, look at the monitor's highest rated resolution. As a rule of + thumb, here's how to translate these into bandwidth estimates (and thus into + rough upper bounds for the dot clock you can use): + 640x480 25 + 800x600 36 + 1024x768 65 + 1024x768 interlaced 45 + 1280x1024 110 + 1600x1200 185 + BTW, there's nothing magic about this table; these numbers are just the lowest + dot clocks per resolution in the standard XFree86 Modes database (except for + the last, which I interpolated). The bandwidth of your monitor may actually be + higher than the minimum needed for its top resolution, so don't be afraid to + try a dot clock a few MHz higher. ! Also note that bandwidth is seldom an issue for dot clocks under 65MHz or so. ! With an SVGA card and most hi-res monitors, you can't get anywhere near the ! limit of your monitor's video bandwidth. The following are examples: ! XFree86 Video Timings HOWTO ! Brand Video Bandwidth ! ---------- --------------- ! NEC 4D 75Mhz ! Nano 907a 50Mhz ! Nano 9080i 60Mhz ! Mitsubishi HL6615 110Mhz ! Mitsubishi Diamond Scan 100Mhz ! IDEK MF-5117 65Mhz ! IOCOMM Thinksync-17 CM-7126 136Mhz ! HP D1188A 100Mhz ! Philips SC-17AS 110Mhz ! Swan SW617 85Mhz ! Viewsonic 21PS 185Mhz ! Even low-end monitors usually aren't terribly bandwidth-constrained for their ! rated resolutions. The NEC Multisync II makes a good example --- it can't even ! display 800x600 per its spec. It can only display 800x560. For such low reso- ! lutions you don't need high dot clocks or a lot of bandwidth; probably the best ! you can do is 32Mhz or 36Mhz, both of them are still not too far from the moni- ! tor's rated video bandwidth of 30Mhz. + At these two driving frequencies, your screen image may not be as sharp as it + should be, but definitely of tolerable quality. Of course it would be nicer if + NEC Multisync II had a video bandwidth higher than, say, 36Mhz. But this is + not critical for common tasks like text editing, as long as the difference is + not so significant as to cause severe image distortion (your eyes would tell + you right away if this were so). ! 4.2 What these control: ! The sync frequency ranges of your monitor, together with your video adapter's ! dot clock, determine the ultimate resolution that you can use. But it's up to ! the driver to tap the potential of your hardware. A superior hardware combina- ! tion without an equally competent device driver is a waste of money. On the ! other hand, with a versatile device driver but less capable hardware, you can ! push the hardware's envelope a little. This is the design philosophy of ! XFree86. ! 5. Interpreting the Basic Specifications ! This section explains what the specifications above mean, and some other things ! you'll need to know. First, some definitions. Next to each in parens is the ! variable name we'll use for it when doing calculations ! horizontal sync frequency (HSF) ! Horizontal scans per second (see above). + vertical sync frequency (VSF) + Vertical scans per second (see above). Mainly important as the + upper limit on your refresh rate. ! XFree86 Video Timings HOWTO ! dot clock (DCF) ! More formally, `driving clock frequency'; The frequency of the ! crystal or VCO on your adaptor --- the maximum dots-per-second it ! can emit. + video bandwidth (VB) + The highest frequency you can feed into your monitor's video input + and still expect to see anything discernible. If your adaptor pro- + duces an alternating on/off pattern, its lowest frequency is half + the DCF, so in theory bandwidth starts making sense at DCF/2. For + tolerably crisp display of fine details in the video image, how- + ever, you don't want it much below your highest DCF, and preferably + higher. + frame length (HFL, VFL) + Horizontal frame length (HFL) is the number of dot-clock ticks + needed for your monitor's electron gun to scan one horizontal line, + including the inactive left and right borders. Vertical frame + length (VFL) is the number of scan lines in the entire image, + including the inactive top and bottom borders. ! screen refresh rate (RR) ! The number of times per second your screen is repainted (this is ! also called "frame rate"). Higher frequencies are better, as they ! reduce flicker. 60Hz is good, VESA-standard 72Hz is better. Com- ! pute it as ! RR = DCF / (HFL * VFL) + Note that the product in the denominator is not the same as the + monitor's visible resolution, but typically somewhat larger. We'll + get to the details of this below. + The rates for which interlaced modes are usually specified (like + 87Hz interlaced) are actually the half-frame rates: an entire + screen seems to have about that flicker frequency for typical dis- + plays, but every single line is refreshed only half as often. + For calculation purposes we reckon an interlaced display at its + full-frame (refresh) rate, i.e. 43.5Hz. The quality of an inter- + laced mode is better than that of a non-interlaced mode with the + same full-frame rate, but definitely worse then the non-interlaced + one corresponding to the half-frame rate. ! 5.1 About Bandwidth: ! Monitor makers like to advertise high bandwidth because it constrains the ! sharpness of intensity and color changes on the screen. A high bandwidth means ! smaller visible details. ! Your monitor uses electronic signals to present an image to your eyes. Such ! signals always come in in wave form once they are converted into analog form ! from digitized form. They can be considered as combinations of many simpler ! wave forms each one of which has a fixed frequency, many of them are in the Mhz ! ! ! ! ! ! ! ! XFree86 Video Timings HOWTO ! ! ! ! range, eg, 20Mhz, 40Mhz, or even 70Mhz. Your monitor video bandwidth is, ! effectively, the highest-frequency analog signal it can handle without distor- ! tion. ! ! For our purposes, bandwidth is mainly important as an approximate cutoff point ! for the highest dot clock you can use. ! ! 5.2 Sync Frequencies and the Refresh Rate: ! ! Each horizontal scan line on the display is just the visible portion of a ! frame-length scan. At any instant there is actually only one dot active on the ! screen, but with a fast enough refresh rate your eye's persistence of vision ! enables you to "see" the whole image. ! ! Here are some pictures to help: ! ! _______________________ ! | | The horizontal sync frequency ! |->->->->->->->->->->-> | is the number of times per ! | )| second that the monitor's ! |<-----<-----<-----<--- | electron beam can trace ! | | a pattern like this ! | | ! | | ! | | ! |_______________________| ! _______________________ ! | ^ | The vertical sync frequency ! | ^ | | is the number of times per ! | | v | second that the monitor's ! | ^ | | electron beam can trace ! | | | | a pattern like this ! | ^ | | ! | | v | ! | ^ | | ! |_______|_v_____________| ! ! Remember that the actual raster scan is a very tight zigzag pattern; that is, ! the beam moves left-right and at the same time up-down. ! ! Now we can see how the dot clock and frame size relates to refresh rate. By ! definition, one hertz (hz) is one cycle per second. So, if your horizontal ! frame length is HFL and your vertical frame length is VFL, then to cover the ! entire screen takes (HFL * VFL) ticks. Since your card emits DCF ticks per ! second by definition, then obviously your monitor's electron gun(s) can sweep ! the screen from left to right and back and from bottom to top and back DCF / ! (HFL * VFL) times/sec. This is your screen's refresh rate, because it's how ! many times your screen can be updated (thus refreshed) per second! ! ! You need to understand this concept to design a configuration which trades off ! resolution against flicker in whatever way suits your needs. ! ! For those of you who handle visuals better than text, here is one: ! ! ! ! ! ! ! ! ! ! XFree86 Video Timings HOWTO ! ! ! ! RR VB ! | min HSF max HSF | ! | | R1 R2 | | ! max VSF -+----|------------/----------/---|------+----- max VSF ! | |:::::::::::/::::::::::/:::::\ | ! | \::::::::::/::::::::::/:::::::\ | ! | |::::::::/::::::::::/:::::::::| | ! | |:::::::/::::::::::/::::::::::\ | ! | \::::::/::::::::::/::::::::::::\ | ! | \::::/::::::::::/::::::::::::::| | ! | |::/::::::::::/:::::::::::::::| | ! | \/::::::::::/:::::::::::::::::\| ! | /\:::::::::/:::::::::::::::::::| ! | / \:::::::/::::::::::::::::::::|\ ! | / |:::::/:::::::::::::::::::::| | ! | / \::::/::::::::::::::::::::::| \ ! min VSF -+----/-------\--/-----------------------|--\--- min VSF ! | / \/ | \ ! +--/----------/\------------------------+----\- DCF ! R1 R2 \ | \ ! min HSF | max HSF ! VB ! ! This is a generic monitor mode diagram. The x axis of the diagram shows the ! clock rate (DCF), the y axis represents the refresh rate (RR). The filled ! region of the diagram describes the monitor's capabilities: every point within ! this region is a possible video mode. ! ! The lines labeled `R1' and `R2' represent a fixed resolutions (such as ! 640x480); they are meant to illustrate how one resolution can be realized by ! many different combinations of dot clock and refresh rate. The R2 line would ! represent a higher resolution than R1. ! ! The top and bottom boundaries of the permitted region are simply horizontal ! lines representing the limiting values for the vertical sync frequency. The ! video bandwidth is an upper limit to the clock rate and hence is represented by ! a vertical line bounding the capability region on the right. ! ! Under Plotting Monitor Capabilities (section 15., page 22)) you'll find a pro- ! gram that will help you plot a diagram like this (but much nicer, with X graph- ! ics) for your individual monitor. That section also discusses the interesting ! part; the derivation of the boundaries resulting from the limits on the hori- ! zontal sync frequency. ! ! ! 6. Tradeoffs in Configuring your System ! ! Another way to look at the formula we derived above is ! ! DCF = RR * HFL * VFL ! ! ! That is, your dot clock is fixed. You can use those dots per second to buy ! either refresh rate, horizontal resolution, or vertical resolution. If one of ! ! ! ! ! ! ! ! ! XFree86 Video Timings HOWTO ! ! ! ! those increases, one or both of the others must decrease. ! ! Note, though, that your refresh rate cannot be greater than the maximum verti- ! cal sync frequency of your monitor. Thus, for any given monitor at a given dot ! clock, there is a minimum product of frame lengths below which you can't force ! it. ! ! In choosing your settings, remember: if you set RR too low, you will get mugged ! by screen flicker. ! ! You probably do not want to pull your refresh rate below 60Hz. This is the ! flicker rate of fluorescent lights; if you're sensitive to those, you need to ! hang with 72Hz, the VESA ergonomic standard. ! ! Flicker is very eye-fatiguing, though human eyes are adaptable and peoples' ! tolerance for it varies widely. If you face your monitor at a 90% viewing ! angle, are using a dark background and a good contrasting color for foreground, ! and stick with low to medium intensity, you *may* be comfortable at as little ! as 45Hz. ! ! The acid test is this: open a xterm with pure white back-ground and black fore- ! ground using xterm -bg white -fg black and make it so large as to cover the ! entire viewable area. Now turn your monitor's intensity to 3/4 of its maximum ! setting, and turn your face away from the monitor. Try peeking at your monitor ! sideways (bringing the more sensitive peripheral-vision cells into play). If ! you don't sense any flicker or if you feel the flickering is tolerable, then ! that refresh rate is fine with you. Otherwise you better configure a higher ! refresh rate, because that semi-invisible flicker is going to fatigue your eyes ! like crazy and give you headaches, even if the screen looks OK to normal ! vision. ! ! For interlaced modes, the amount of flicker depends on more factors such as the ! current vertical resolution and the actual screen contents. So just experi- ! ment. You won't want to go much below about 85Hz half frame rate, though. ! ! So let's say you've picked a minimum acceptable refresh rate. In choosing your ! HFL and VFL, you'll have some room for maneuver. ! ! ! 7. Memory Requirements ! ! Available frame-buffer RAM may limit the resolution you can achieve on color or ! gray-scale displays. It probably isn't a factor on displays that have only two ! colors, white and black with no shades of gray in between. ! ! For 256-color displays, a byte of video memory is required for each visible dot ! to be shown. This byte contains the information that determines what mix of ! red, green, and blue is generated for its dot. To get the amount of memory ! required, multiply the number of visible dots per line by the number of visible ! lines. For a display with a resolution of 800x600, this would be 800 x 600 = ! 480,000, which is the number of visible dots on the display. This is also, at ! one byte per dot, the number of bytes of video memory that are necessary on ! your adapter card. ! ! ! ! ! ! ! ! ! ! XFree86 Video Timings HOWTO ! ! ! ! Thus, your memory requirement will typically be (HR * VR)/1024 Kbytes of VRAM, ! rounded up. If you have more memory than strictly required, you'll have extra ! for virtual-screen panning. ! ! However, if you only have 512K on board, then you can't use this resolution. ! Even if you have a good monitor, without enough video RAM, you can't take ! advantage of your monitor's potential. On the other hand, if your SVGA has one ! meg, but your monitor can display at most 800x600, then high resolution is ! beyond your reach anyway (see Using Interlaced Modes (section 12., page 19) for ! a possible remedy). ! ! Don't worry if you have more memory than required; XFree86 will make use of it ! by allowing you to scroll your viewable area (see the Xconfig file documenta- ! tion on the virtual screen size parameter). Remember also that a card with ! 512K bytes of memory really doesn't have 512,000 bytes installed, it has 512 x ! 1024 = 524,288 bytes. ! ! If you're running SGCS X (now called X/Inside) using an S3 card, and are will- ! ing to live with 16 colors (4 bits per pixel), you can set depth 4 in Xconfig ! and effectively double the resolution your card can handle. S3 cards, for ! example, normally do 1024x768x256. You can make them do 1280x1024x16 with ! depth 4. ! ! ! 8. Computing Frame Sizes ! ! Warning: this method was developed for multisync monitors. It will probably ! work with fixed-frequency monitors as well, but no guarantees! ! ! Start by dividing DCF by your highest available HSF to get a horizontal frame ! length. ! ! For example; suppose you have a Sigma Legend SVGA with a 65MHz dot clock, and ! your monitor has a 55KHz horizontal scan frequency. The quantity (DCF / HSF) ! is then 1181 (65MHz = 65000KHz; 65000/55 = 1181). ! ! Now for our first bit of black magic. You need to round this figure to the ! nearest multiple of 8. This has to do with the VGA hardware controller used by ! SVGA and S3 cards; it uses an 8-bit register, left-shifted 3 bits, for what's ! really an 11-bit quantity. Other card types such as ATI 8514/A may not have ! this requirement, but we don't know and the correction can't hurt. So round ! the usable horizontal frame length figure down to 1176. ! ! This figure (DCF / HSF rounded to a multiple of 8) is the minimum HFL you can ! use. You can get longer HFLs (and thus, possibly, more horizontal dots on the ! screen) by setting the sync pulse to produce a lower HSF. But you'll pay with ! a slower and more visible flicker rate. ! ! As a rule of thumb, 80% of the horizontal frame length is available for hori- ! zontal resolution, the visible part of the horizontal scan line (this allows, ! roughly, for borders and sweepback time -- that is, the time required for the ! beam to move from the right screen edge to the left edge of the next raster ! line). In this example, that's 944 ticks. ! ! ! ! ! ! ! ! ! ! XFree86 Video Timings HOWTO ! ! ! ! Now, to get the normal 4:3 screen aspect ratio, set your vertical resolution to ! 3/4ths of the horizontal resolution you just calculated. For this example, ! that's 708 ticks. To get your actual VFL, multiply that by 1.05 to get 743 ! ticks. ! ! The 4:3 is not technically magic; nothing prevents you from using a non-Golden- ! Section ratio if that will get the best use out of your screen real estate. It ! does make figuring frame height and frame width from the diagonal size conve- ! nient, you just multiply the diagonal by by 0.8 to get width and 0.6 to get ! height. ! ! So, HFL=1176 and VFL=743. Dividing 65MHz by the product of the two gives us a ! nice, healthy 74.4Hz refresh rate. Excellent! Better than VESA standard! And ! you got 944x708 to boot, more than the 800 by 600 you were probably expecting. ! Not bad at all! ! ! You can even improve the refresh rate further, to almost 76 Hz, by using the ! fact that monitors can often sync horizontally at 2khz or so higher than rated, ! and by lowering VFL somewhat (that is, taking less than 75% of 944 in the exam- ! ple above). But before you try this "overdriving" maneuver, if you do, make ! sure that your monitor electron guns can sync up to 76 Hz vertical. (the popu- ! lar NEC 4D, for instance, cannot. It goes only up to 75 Hz VSF). (See Over- ! driving Your Monitor (section 11., page 18) for more general discussion of this ! issue. ) ! ! So far, most of this is simple arithmetic and basic facts about raster dis- ! plays. Hardly any black magic at all! ! ! ! 9. Black Magic and Sync Pulses ! ! OK, now you've computed HFL/VFL numbers for your chosen dot clock, found the ! refresh rate acceptable, and checked that you have enough VRAM. Now for the ! real black magic -- you need to know when and where to place synchronization ! pulses. ! ! The sync pulses actually control the horizontal and vertical scan frequencies ! of the monitor. The HSF and VSF you've pulled off the spec sheet are nominal, ! approximate maximum sync frequencies. The sync pulse in the signal from the ! adapter card tells the monitor how fast to actually run. ! ! Recall the two pictures above? Only part of the time required for raster-scan- ! ning a frame is used for displaying viewable image (ie. your resolution). ! ! 9.1 Horizontal Sync: ! ! By previous definition, it takes HFL ticks to trace the a horizontal scan line. ! Let's call the visible tick count (your horizontal screen resolution) HR. Then ! Obviously, HR < HFL by definition. For concreteness, let's assume both start ! at the same instant as shown below: ! ! ! ! ! ! ! ! ! ! ! ! ! XFree86 Video Timings HOWTO ! ! ! ! |___ __ __ __ __ __ __ __ __ __ __ __ __ ! |_ _ _ _ _ _ _ _ _ _ _ _ | ! |_______________________|_______________|_____ ! 0 ^ ^ unit: ticks ! | ^ ^ | ! HR | | HFL ! | |<----->| | ! |<->| HSP |<->| ! HGT1 HGT2 ! ! Now, we would like to place a sync pulse of length HSP as shown above, ie, ! between the end of clock ticks for display data and the end of clock ticks for ! the entire frame. Why so? because if we can achieve this, then your screen ! image won't shift to the right or to the left. It will be where it supposed to ! be on the screen, covering squarely the monitor's viewable area. ! Furthermore, we want about 30 ticks of "guard time" on either side of the sync ! pulse. This is represented by HGT1 and HGT2. In a typical configuration HGT1 ! != HGT2, but if you're building a configuration from scratch, you want to start ! your experimentation with them equal (that is, with the sync pulse centered). ! The symptom of a misplaced sync pulse is that the image is displaced on the ! screen, with one border excessively wide and the other side of the image ! wrapped around the screen edge, producing a white edge line and a band of ! "ghost image" on that side. A way-out-of-place vertical sync pulse can actu- ! ally cause the image to roll like a TV with a mis-adjusted vertical hold (in ! fact, it's the same phenomenon at work). + If you're lucky, your monitor's sync pulse widths will be documented on its + specification page. If not, here's where the real black magic starts... ! You'll have to do a little trial and error for this part. But most of the ! time, we can safely assume that a sync pulse is about 3.5 to 4.0 microsecond in ! length. + For concreteness again, let's take HSP to be 3.8 microseconds (which btw, is + not a bad value to start with when experimenting). + Now, using the 65Mhz clock timing above, we know HSP is equivalent to 247 clock + ticks (= 65 * 10**6 * 3.8 * 10^-6) [recall M=10^6, micro=10^-6] + Some makers like to quote their horizontal framing parameters as timings rather + than dot widths. You may see the following terms: ! active time (HAT) ! Corresponds to HR, but in milliseconds. HAT * DCF = HR. ! blanking time (HBT) ! Corresponds to (HFL - HR), but in milliseconds. HBT * DCF = (HFL - ! HR). ! front porch (HFP) ! This is just HGT1. ! $TOG: VideoModes.doc /main/14 1998/03/06 16:40:07 kaleb $ ! XFree86 Video Timings HOWTO ! sync time ! This is just HSP. ! back porch (HBP) ! This is just HGT2. ! 9.2 Vertical Sync: ! Going back to the picture above, how do we place the 247 clock ticks as shown ! in the picture? ! Using our example, HR is 944 and HFL is 1176. The difference between the two ! is 1176 - 944=232 < 247! Obviously we have to do some adjustment here. What ! can we do? ! The first thing is to raise 1176 to 1184, and lower 944 to 936. Now the dif- ! ference = 1184-936= 248. Hmm, closer. ! Next, instead using 3.8, we use 3.5 for calculating HSP; then, we have ! 65*3.5=227. Looks better. But 248 is not much higher than 227. It's normally ! necessary to have 30 or so clock ticks between HR and the start of SP, and the ! same for the end of SP and HFL. AND they have to be multiple of eight! Are we ! stuck? ! ! No. Let's do this, 936 % 8 = 0, (936 + 32) % 8 = 0 too. But 936 + 32 = 968, ! 968 + 227 = 1195, 1195 + 32 = 1227. Hmm.. this looks not too bad. But it's ! not a multiple of 8, so let's round it up to 1232. ! ! But now we have potential trouble, the sync pulse is no longer placed right in ! the middle between h and H any more. Happily, using our calculator we find ! 1232 - 32 = 1200 is also a multiple of 8 and (1232 - 32) - 968 = 232 corre- ! sponding using a sync pulse of 3.57 micro second long, still reasonable. ! ! In addition, 936/1232 ~ 0.76 or 76%, still not far from 80%, so it should be ! all right. ! ! Furthermore, using the current horizontal frame length, we basically ask our ! monitor to sync at 52.7khz (= 65Mhz/1232) which is within its capability. No ! problems. ! ! Using rules of thumb we mentioned before, 936*75%=702, This is our new vertical ! resolution. 702 * 1.05 = 737, our new vertical frame length. ! ! Screen refresh rate = 65Mhz/(737*1232)=71.6 Hz. This is still excellent. ! ! Figuring the vertical sync pulse layout is similar: ! ! |___ __ __ __ __ __ __ __ __ __ __ __ __ ! |_ _ _ _ _ _ _ _ _ _ _ _ | ! |_______________________|_______________|_____ ! 0 VR VFL unit: ticks ! ^ ^ ^ ! | | | ! |<->|<----->| ! ! ! ! ! ! ! ! ! XFree86 Video Timings HOWTO ! ! ! ! VGT VSP ! ! We start the sync pulse just past the end of the vertical display data ticks. ! VGT is the vertical guard time required for the sync pulse. Most monitors are ! comfortable with a VGT of 0 (no guard time) and we'll use that in this example. ! A few need two or three ticks of guard time, and it usually doesn't hurt to add ! that. ! ! Returning to the example: since by the definition of frame length, a vertical ! tick is the time for tracing a complete HORIZONTAL frame, therefore in our ! example, it is 1232/65Mhz=18.95us. ! ! Experience shows that a vertical sync pulse should be in the range of 50us and ! 300us. As an example let's use 150us, which translates into 8 vertical clock ! ticks (150us/18.95us~8). ! ! Some makers like to quote their vertical framing parameters as timings rather ! than dot widths. You may see the following terms: ! ! active time (VAT) ! Corresponds to VR, but in milliseconds. VAT * VSF = VR. ! blanking time (VBT) ! Corresponds to (VFL - VR), but in milliseconds. VBT * VSF = (VFL - ! VR). ! ! front porch (VFP) ! This is just VGT. ! ! sync time ! This is just VSP. ! ! back porch (VBP) ! This is like a second guard time after the vertical sync pulse. It ! is often zero. ! ! ! 10. Putting it All Together ! ! The Xconfig file Table of Video Modes contains lines of numbers, with each line ! being a complete specification for one mode of X-server operation. The fields ! are grouped into four sections, the name section, the clock frequency section, ! the horizontal section, and the vertical section. ! ! The name section contains one field, the name of the video mode specified by ! the rest of the line. This name is referred to on the "Modes" line of the ! Graphics Driver Setup section of the Xconfig file. The name field may be omit- ! ted if the name of a previous line is the same as the current line. ! ! The dot clock section contains only the dot clock (what we've called DCF) field ! of the video mode line. The number in this field specifies what dot clock was ! used to generate the numbers in the following sections. ! ! The horizontal section consists of four fields which specify how each ! ! ! ! ! ! ! ! ! XFree86 Video Timings HOWTO ! ! ! ! horizontal line on the display is to be generated. The first field of the sec- ! tion contains the number of dots per line which will be illuminated to form the ! picture (what we've called HR). The second field of the section indicates at ! which dot the horizontal sync pulse will begin. The third field indicates at ! which dot the horizontal sync pulse will end. The fourth field specifies the ! total horizontal frame length (HFL). ! ! The vertical section also contains four fields. The first field contains the ! number of visible lines which will appear on the display (VR). The second ! field indicates the line number at which the vertical sync pulse will begin. ! The third field specifies the line number at which the vertical sync pulse will ! end. The fourth field contains the total vertical frame length (VFL). ! ! Example: ! ! #Modename clock horizontal timing vertical timing ! ! "752x564" 40 752 784 944 1088 564 567 569 611 ! 44.5 752 792 976 1240 564 567 570 600 ! ! ! (Note: stock X11R5 doesn't support fractional dot clocks.) ! ! For Xconfig, all of the numbers just mentioned - the number of illuminated dots ! on the line, the number of dots separating the illuminated dots from the begin- ! ning of the sync pulse, the number of dots representing the duration of the ! pulse, and the number of dots after the end of the sync pulse - are added to ! produce the number of dots per line. The number of horizontal dots must be ! evenly divisible by eight. ! ! Example horizontal numbers: 800 864 1024 1088 ! ! This sample line has the number of illuminated dots (800) followed by the num- ! ber of the dot when the sync pulse starts (864), followed by the number of the ! dot when the sync pulse ends (1024), followed by the number of the last dot on ! the horizontal line (1088). ! ! Note again that all of the horizontal numbers (800, 864, 1024, and 1088) are ! divisible by eight! This is not required of the vertical numbers. ! ! The number of lines from the top of the display to the bottom form the frame. ! The basic timing signal for a frame is the line. A number of lines will con- ! tain the picture. After the last illuminated line has been displayed, a delay ! of a number of lines will occur before the vertical sync pulse is generated. ! Then the sync pulse will last for a few lines, and finally the last lines in ! the frame, the delay required after the pulse, will be generated. The numbers ! that specify this mode of operation are entered in a manner similar to the fol- ! lowing example. ! ! Example vertical numbers: 600 603 609 630 ! ! This example indicates that there are 600 visible lines on the display, that ! the vertical sync pulse starts with the 603rd line and ends with the 609th, and ! that there are 630 total lines being used. ! ! ! ! ! ! ! ! ! XFree86 Video Timings HOWTO ! ! ! ! Note that the vertical numbers don't have to be divisible by eight! ! ! Let's return to the example we've been working. According to the above, all we ! need to do from now on is to write our result into Xconfig as follows: ! ! DCF HR SH1 SH2 HFL VR SV1 SV2 VFL ! ! ! where SH1 is the start tick of the horizontal sync pulse and SH2 is its end ! tick; similarly, SV1 is the start tick of the vertical sync pulse and SV2 is ! its end tick. ! ! #name clock horizontal timing vertical timing flag ! 936x702 65 936 968 1200 1232 702 702 710 737 ! ! ! No special flag necessary; this is a non-interlaced mode. Now we are really ! done. ! ! ! 11. Overdriving Your Monitor ! ! You should absolutely not try exceeding your monitor's scan rates if it's a ! fixed-frequency type. You can smoke your hardware doing this! There are ! potentially subtler problems with overdriving a multisync monitor which you ! should be aware of. ! ! Having a pixel clock higher than the monitor's maximum bandwidth is rather ! harmless, in contrast. (Note: the theoretical limit of discernible features is ! reached when the pixel clock reaches double the monitor's bandwidth. This is a ! straightforward application of Nyquist's Theorem: consider the pixels as a spa- ! tially distributed series of samples of the drive signals and you'll see why.) ! ! It's exceeding the rated maximum sync frequencies that's problematic. Some ! modern monitors might have protection circuitry that shuts the monitor down at ! dangerous scan rates, but don't rely on it. In particular there are older mul- ! tisync monitors (like the Multisync II) which use just one horizontal trans- ! former. These monitors will not have much protection against overdriving them. ! While you necessarily have high voltage regulation circuitry (which can be ! absent in fixed frequency monitors), it will not necessarily cover every con- ! ceivable frequency range, especially in cheaper models. This not only implies ! more wear on the circuitry, it can also cause the screen phosphors to age ! faster, and cause more than the specified radiation (including X-rays) to be ! emitted from the monitor. ! ! Another importance of the bandwidth is that the monitor's input impedance is ! specified only for that range, and using higher frequencies can cause reflec- ! tions probably causing minor screen interferences, and radio disturbance. ! ! However, the basic problematic magnitude in question here is the slew rate (the ! steepness of the video signals) of the video output drivers, and that is usu- ! ally independent of the actual pixel frequency, but (if your board manufacturer ! cares about such problems) related to the maximum pixel frequency of the board. ! ! ! ! ! ! ! ! ! ! XFree86 Video Timings HOWTO ! ! ! ! So be careful out there... ! ! ! 12. Using Interlaced Modes ! ! (This section is largely due to David Kastrup ) ! ! At a fixed dot clock, an interlaced display is going to have considerably less ! noticeable flicker than a non-interlaced display, if the vertical circuitry of ! your monitor is able to support it stably. It is because of this that inter- ! laced modes were invented in the first place. ! ! Interlaced modes got their bad repute because they are inferior to their non- ! interlaced companions at the same vertical scan frequency, VSF (which is what ! is usually given in advertisements). But they are definitely superior at the ! same horizontal scan rate, and that's where the decisive limits of your moni- ! tor/graphics card usually lie. ! ! At a fixed refresh rate (or half frame rate, or VSF) the interlaced display ! will flicker more: a 90Hz interlaced display will be inferior to a 90Hz non- ! interlaced display. It will, however, need only half the video bandwidth and ! half the horizontal scan rate. If you compared it to a non-interlaced mode with ! the same dot clock and the same scan rates, it would be vastly superior: 45Hz ! non-interlaced is intolerable. With 90Hz interlaced, I have worked for years ! with my Multisync 3D (at 1024x768) and am very satisfied. I'd guess you'd need ! at least a 70Hz non-interlaced display for similar comfort. ! ! You have to watch a few points, though: use interlaced modes only at high reso- ! lutions, so that the alternately lighted lines are close together. You might ! want to play with sync pulse widths and positions to get the most stable line ! positions. If alternating lines are bright and dark, interlace will jump at ! you. I have one application that chooses such a dot pattern for a menu back- ! ground (XCept, no other application I know does that, fortunately). I switch to ! 800x600 for using XCept because it really hurts my eyes otherwise. ! For the same reason, use at least 100dpi fonts, or other fonts where horizontal ! beams are at least two lines thick (for high resolutions, nothing else will ! make sense anyhow). + And of course, never use an interlaced mode when your hardware would support a + non-interlaced one with similar refresh rate. ! If, however, you find that for some resolution you are pushing either monitor ! or graphics card to their upper limits, and getting unsatisfactory flickery or ! washed out (bandwidth exceeded) display, you might want to try tackling the ! same resolution using an interlaced mode. Of course this is useless if the VSF ! of your monitor is already close to its limits. ! Design of interlaced modes is easy: do it like a non-interlaced mode. Just two ! more considerations are necessary: you need an odd total number of vertical ! lines (the last number in your mode line), and when you specify the "interlace" ! flag, the actual vertical frame rate for your monitor doubles. Your monitor ! needs to support a 90Hz frame rate if the mode you specified looks like a 45Hz ! XFree86 Video Timings HOWTO *************** *** 578,1039 **** ! |___ __ __ __ __ __ __ __ __ __ __ __ __ ! |_ _ _ _ _ _ _ _ _ _ _ _ | ! |_______________________|_______________|_____ ! 0 ^ ^ unit: ticks ! | ^ ^ | ! HR | | HFL ! | |<----->| | ! |<->| HSP |<->| ! HGT1 HGT2 ! Now, we would like to place a sync pulse of length HSP as shown above, ! ie, between the end of clock ticks for display data and the end of ! clock ticks for the entire frame. Why so? because if we can achieve ! this, then your screen image won't shift to the right or to the left. ! It will be where it supposed to be on the screen, covering squarely ! the monitor's viewable area. - Furthermore, we want about 30 ticks of "guard time" on either side of - the sync pulse. This is represented by HGT1 and HGT2. In a typical - configuration HGT1 != HGT2, but if you're building a configuration - from scratch, you want to start your experimentation with them equal - (that is, with the sync pulse centered). ! The symptom of a misplaced sync pulse is that the image is displaced ! on the screen, with one border excessively wide and the other side of ! the image wrapped around the screen edge, producing a white edge line ! and a band of "ghost image" on that side. A way-out-of-place vertical ! sync pulse can actually cause the image to roll like a TV with a mis- ! adjusted vertical hold (in fact, it's the same phenomenon at work). ! If you're lucky, your monitor's sync pulse widths will be documented ! on its specification page. If not, here's where the real black magic ! starts... ! You'll have to do a little trial and error for this part. But most of ! the time, we can safely assume that a sync pulse is about 3.5 to 4.0 ! microsecond in length. ! For concreteness again, let's take HSP to be 3.8 microseconds (which ! btw, is not a bad value to start with when experimenting). ! Now, using the 65Mhz clock timing above, we know HSP is equivalent to ! 247 clock ticks (= 65x10**6 * 3.8 *10**(-6)) [recall M=10**6, ! micro=10**(-6)] ! Vertical Sync: ! Going back to the picture above, how do we place the 247 clock ticks ! as shown in the picture? ! Using our example, HR is 944 and HFL is 1176. The difference between ! the two is 1176-944=232 < 247! Obviously we have to do some ! adjustment here. What can we do? - The first thing is to raise 1176 to 1184, and lower 944 to 936. Now - the difference = 1184-936= 248. Hmm, closer. - Next, instead using 3.8, we use 3.5 for calculating HSP; then, we have - 65*3.5=227. Looks better. But 248 is not much higher than 227. It's - normally necessary to have 30 or so clock ticks between HR and the - start of SP, and the same for the end of SP and HFL. AND they have to - be multiple of eight! Are we stuck? - No! let's do this, 936% 8==0, (936+32)% 8==0 too. But 936+32=968, - 968+227=1195, 1195+32=1227. Hmm.. this looks not too bad. But it's - not a multiple of 8, so lets round it up to 1232. - But now we have potential trouble, the sync pulse is no longer placed - right in the middle between h and H any more. Happily, using our - calculator we find 1232-32=1200 is also a multiple of 8 and - (1232-32)-968=232 corresponding using a sync pulse of 3.57 micro - second long, still reasonable. - In addition, 936/1232 0.76 or 76%, still not far from 80%, so it - should be all right. - Furthermore, using the current horizontal frame length, we basically - ask our monitor to sync at 52.7khz(=65Mhz/1232) which is within its - capability. No problems. - Using rules of thumb we mentioned before, 936*75%=702, This is our new - vertical resolution. 702*1.05=737, our new vertical frame length. ! Screen refresh rate = 65Mhz/(737*1232)=71.6 Hz. This is still ! excellent. - Figuring the vertical sync pulse layout is similar: ! |___ __ __ __ __ __ __ __ __ __ __ __ __ ! |_ _ _ _ _ _ _ _ _ _ _ _ | ! |_______________________|_______________|_____ ! 0 VR VFL unit: ticks ! ^ ^ ^ ! | | | ! |<->|<----->| ! VGT VSP - We start the sync pulse just past the end of the vertical display data - ticks. VGT is the vertical guard time required for the sync pulse. - Most monitors are comfortable with a VGT of 0 (no guard time) and - we'll use that in this example. A few need two or three ticks of - guard time, and it usually doesn't hurt to add that. ! Returning to the example: since by the definition of frame length, a ! vertical tick is the time for tracing a complete HORIZONTAL frame, ! therefore in our example, it is 1232/65Mhz=18.95us. ! Experience shows that a vertical sync pulse should be in the range of ! 50us and 300us. As an example let's use 150us, which translates into ! 8 vertical clock ticks (150us/18.95us 8). ! 9. Putting it All Together ! The Xconfig file Table of Video Modes contains lines of numbers, with ! each line being a complete specification for one mode of X-server ! operation. The fields are grouped into four sections, the name ! section, the clock frequency section, the horizontal section, and the ! vertical section. ! The name section contains one field, the name of the video mode ! specified by the rest of the line. This name is referred to on the ! "Modes" line of the Graphics Driver Setup section of the Xconfig file. ! The name field may be omitted if the name of a previous line is the ! same as the current line. ! The dot clock section contains only the dot clock (what we've called ! DCF) field of the video mode line. The number in this field specifies ! what dot clock was used to generate the numbers in the following ! sections. ! The horizontal section consists of four fields which specify how each ! horizontal line on the display is to be generated. The first field of ! the section contains the number of dots per line which will be ! illuminated to form the picture (what we've called HR). The second ! field of the section indicates at which dot the horizontal sync pulse ! will begin. The third field indicates at which dot the horizontal ! sync pulse will end. The fourth field specifies the total horizontal ! frame length (HFL). ! The vertical section also contains four fields. The first field ! contains the number of visible lines which will appear on the display ! (VR). The second field indicates the line number at which the ! vertical sync pulse will begin. The third field specifies the line ! number at which the vertical sync pulse will end. The fourth field ! contains the total vertical frame length (VFL). ! Example: - #Modename clock horizontal timing vertical timing - "752x564" 40 752 784 944 1088 564 567 569 611 - 44.5 752 792 976 1240 564 567 570 600 - (Note: stock X11R5 doesn't support fractional dot clocks.) - For Xconfig, all of the numbers just mentioned - the number of - illuminated dots on the line, the number of dots separating the - illuminated dots from the beginning of the sync pulse, the number of - dots representing the duration of the pulse, and the number of dots - after the end of the sync pulse - are added to produce the number of - dots per line. The number of horizontal dots must be evenly divisible - by eight. ! Example: - horizontal numbers: 800 864 1024 1088 - The sample line has the number of illuminated dots (800) followed by - the number of the dot when the sync pulse starts (864), followed by - the number of the dot when the sync pulse ends (1024), followed by the - number of the last dot on the horizontal line (1088). ! Note again that all of the horizontal numbers (800, 864, 1024, and ! 1088) are divisible by eight! This is not required of the vertical ! numbers. ! The number of lines from the top of the display to the bottom form the ! frame. The basic timing signal for a frame is the line. A number of ! lines will contain the picture. After the last illuminated line has ! been displayed, a delay of a number of lines will occur before the ! vertical sync pulse is generated. Then the sync pulse will last for a ! few lines, and finally the last lines in the frame, the delay required ! after the pulse, will be generated. The numbers that specify this ! mode of operation are entered in a manner similar to the following ! example. ! Example: ! vertical numbers: 600 603 609 630 ! This example indicates that there are 600 visible lines on the ! display, that the vertical sync pulse starts with the 603rd line and ! ends with the 609th, and that there are 630 total lines being used. ! Note that the vertical numbers don't have to be divisible by eight! ! Let's return to the example we've been working. According to the ! above, all we need to do from now on is to write our result into ! Xconfig as follows: ! < name > DCF HR SH1 SH2 HFL VR SV1 SV2 VFL ! where SH1 is the start tick of the horizontal sync pulse and SH2 is ! its end tick; similarly, SV1 is the start tick of the vertical sync ! pulse and SV2 is its end tick. ! #name clock horizontal timing vertical timing flag ! 936x702 65 936 968 1200 1232 702 702 710 737 - No special flag necessary; this is a non-interlaced mode. Now we are - really done. - 10. Questions and Answers - Q. The example you gave is not a standard screen size, can I use it? - A. Why not? There is NO reason whatsoever why you have to use - 640x480, 800x600, or even 1024x768. XFree86 driver lets you config - your hardware with a lot of freedom. It usually takes two to three - minutes to come up the right one. The important thing to shoot for is - high refresh rate with reasonable viewing area. not high resolution at - the price of eye-tearing flicker! - Q. It this the *only* resolution given the 65Mhz dot clock and 55Khz - HSF? - A. Absolutely not! You are encouraged to follow the general procedure - and do some trial-and-error to come up with a setting that's really to - your liking. Experimenting with this can be lots of fun. Most - settings may just give you nasty video hash, but nothing you do can - actually damage a multi-sync monitor (unless you somehow force your - card to clock it at way above its bandwidth --- if you stick - reasonably close to the highest resolution the monitor is documented - to support this can't happen). Beware fixed-frequency monitors! This - kind of hacking around *can* damage them. ! Q. You just mentioned two standard resolutions. In Xconfig, there are ! many standard resolutions available, can you tell me whether there's ! any point in tinkering with timings? - A. Absolutely! Take, for example, the "standard" 640x480 listed in - the current Xconfig. It employs 25Mhz driving frequency, frame - lengths are 800 and 525 => refresh rate 59.5Hz. Not too bad. But - 28Mhz is a commonly available driving frequency from many SVGA boards. - If we use it to drive 640x480, following the procedure we discussed - above, you would get frame lengths like 812 and 505. Now the refresh - rate is raised to 68Hz, a quite significant improvement over the - standard one. - Q. But how about interlace/non-interlace? ! A. At a fixed dot clock, an interlaced display is going to flicker ! worse than a non-interlaced one, which is why the market has moved ! away from them. What you buy with the increased flicker is higher ! resolution with a slower dot clock. If the DCF were fast enough (say ! 90MHz or up) even interlacing wouldn't produce flicker -- but at ! present speeds, interlaced monitors are a bad idea for X. ! Q. Can you summarize what we have discussed so far? ! A. In a nutshell: ! 1. for any fixed driving frequency, raising max resolution incurs ! the penalty of lowering refresh rate and thus introducing more ! flicker. ! 2. if high resolution is desirable and your monitor supports it, ! try to get a SVGA card that provides a matching dot clock or ! DCF. The higher, the better! ! 11. Two More Example Calculations ! Here's another hypothetical: ! An adapter card has a 40 MHz clock rate. A display has a range of ! horizontal sync rates from 30 KHz to 37 KHz. The minimum number of ! dots per line is 40,000,000/37,000 = 1,081.081, or approximately 1,081 ! dots per line. - We'll use this number of dots per line in the following calculations. - So each line on our display must have at least 1081 dots. We round - this up to 1088 to make it divisible evenly by eight. Now let's - assume that the horizontal sync pulse should be 3.8 microseconds long. - We need to find out how many dots it takes to make a 3.8 microsecond - pulse. We do this by first finding out how many microseconds are in - one dot. Since there are 40,000,000 dots per second, 1/40,000,000 is - the number of seconds per dot. - 1/40,000,000 = .000000025 = .025 microseconds per dot - Thus the number of dots for a 3.8 microsecond sync pulse is - 3.8 microseconds = D dots x .025 microseconds/dot - or - D dots = (3.8 microseconds) / (.025 microseconds/dot) = 152 dots - So we have 1088 dots per line, 800 of which are the illuminated ones, - with 152 for the sync pulse. (Note that 152 is evenly divisible by - eight. If it weren't we would round it up until it was evenly - divisible.) This leaves us the task of calculating the time before - and after the sync pulse that is necessary for the display. - The rule of thumb for this is that we need about 30 ticks of guard - time. In this particular case, allocating 32 dots is convenient, - because all the other quantities are divisible by 8. This results in - the timing being 800 dots for the viewable area, 152 dots for the - pulse, and 1088 - (800 + 152) = 136 dots to divide between the two - other times. Half of 136 is 68 dots, so 68 dots are placed between - the illuminated dots and the sync pulse, and 68 dots are placed after - the sync pulse. The horizontal numbers in the Xconfig line then - become ! 800 (800+68) (800+68+152) (800+68+152+68) - or ! 800 868 1020 1088 ! Now we want to calculate the vertical numbers. To begin, we must ! remember that the vertical numbers are not in terms of dots or ! microseconds per dot, but are expressed as numbers of lines! So we ! have to calculate how much time it takes to display a single line. ! That's easy, because we know each line is 1088 dots and each dot is ! .025 microsecond. Each line is, therefore, - (1088 dots/line) x (.025 microseconds/dot) = 27.2 microseconds/line ! Since we chose 800 visible dots per line, let's choose the number of ! lines to be such that the ratio of horizontal to vertical is 4 to 3. ! Thus, 800 is 4 x 200, so the number of visible lines should be 3 x 200 ! = 600. Our target resolution is 800x600. ! We know that a vertical sync pulse should be in the range of 50 to 300 ! microseconds. If we chose 150 microseconds as a typical sync pulse, ! we find how many lines 150 microseconds is by dividing 150 by 27.2 ! microseconds per line. ! (150 microseconds/pulse) / (27.2 microseconds/line) = 5.51 lines/pulse ! By rounding up (never down) to 6 lines/pulse we now have the vertical ! sync pulse width. ! To guess at the total number of lines per frame (illuminated lines ! plus nonilluminated lines in the border) we assume (from ! "Videotiming...") that the total number of lines will be 5% more than ! the number of viewable lines. So the total number of lines is ! (600 lines) x (1.05) = 630 total lines per frame ! So now we must place the pulse in the time between the end of the ! illuminated lines and the end of the frame. Since we have 630 total ! lines, 600 illuminated lines, and 6 lines for the pulse, we have ! 630 - 600 - 6 = 24 lines left ! Some displays don't mind if the pulse begins immediately after the ! illuminated lines, but others might want a line or two between the ! last illuminated line and the beginning of the sync pulse. Taking the ! latter course just to be safe, we add three lines between the last ! illuminated line and the beginning of the pulse. The rest of the ! lines are added after the pulse ends. So the vertical timing numbers ! become ! 600 (600+3) (600+3+6) (600+3+6+21) ! or ! 600 603 609 630 ! Before we do anything else, we must check that the display can handle ! 630 lines/frame at 27.2 microseconds/line. We do this by calculating ! how many frames per second our configuration will generate, and ! comparing it to the display manual's entry for vertical sync rate. ! For 630 lines/frame at 27.2 micro- seconds/line, we have 630 x 27.2 = ! 17,136 microseconds/frame. 17,136 microseconds/frame is 0.017136 ! seconds/frame, or 1/0.017892 frames/second. ! 1 / (0.017136 seconds/frame) = 58.4 frames/second - If the manual says the vertical sync rate is 58.4 Hz, or 58.4 Hz is in - the range of the display's vertical sync rate, we are fine. If the - display cannot handle this rate, we'll have to change the number of - lines per frame by adjusting all of the timings proportionally. - Now we combine the horizontal and vertical timing numbers together - with the resolution and clock values to produce a test configuration - for Xconfig. Our line becomes - "800x600" 40 800 868 1020 1088 600 603 609 630 - Now we have a configuration of XFree86 to try. It may not work if any - of our assumptions were grossly wrong, but in most cases it should at - least give us a stable display. Now it takes a little experimentation - to produce something pleasing. - An actual calculation - My adapter card has a 40 MHz crystal on it so I started with a 40 MHz - clock rate. My display's maximum horizontal sync rate is 37 KHz, so - the minimum dots per line are 40,000,000/37,000 = 1081. My display's - vertical sync rate is the range from 50 Hz to 90 Hz. - My display's manual says that the largest horizontal sync pulse is - 3.92 microseconds. With 0.025 microseconds per dot, the pulse is ! (3.92 microseconds) / (.025 microseconds/dot) = 156.8 dots - Rounding this up to the nearest number evenly divisible by eight gives - 160 dots. - The manual also says that the time between the last illuminated dot - and the beginning of the sync pulse must be at least 0.67 - microseconds. The number of dots in 0.67 microseconds at a 40 MHz - clock rate - remember 40 MHz is .025 microseconds/dot - is ! D dots = (0.67 microseconds) / (.025 microseconds/dot) = 26.8 dots ! Since 26.8 is not evenly divisible by eight, round it up to 32 dots. ! My display's manual says the time after the sync pulse should be 3.56 ! microseconds or more. In dots, 3.56 microseconds is ! D dots = (3.56 microseconds) / (.025 microseconds/dot) = 142.4 dots - Round 142.4 up to 144, so that it's evenly divisible by eight. So now for a horizontal line we have 800 illuminated dots, 32 dots between the illuminated dots and the sync pulse, 152 dots for the sync --- 1260,1677 ---- + mode apart from the "Interlace" flag. ! As an example, here is my modeline for 1024x768 interlaced: my Multisync 3D ! will support up to 90Hz vertical and 38kHz horizontal. + ModeLine "1024x768" 45 1024 1048 1208 1248 768 768 776 807 Interlace + Both limits are pretty much exhausted with this mode. Specifying the same mode, + just without the "Interlace" flag, still is almost at the limit of the moni- + tor's horizontal capacity (and strictly speaking, a bit under the lower limit + of vertical scan rate), but produces an intolerably flickery display. + Basic design rules: if you have designed a mode at less than half of your moni- + tor's vertical capacity, make the vertical total of lines odd and add the + "Interlace" flag. The display's quality should vastly improve in most cases. ! If you have a non-interlaced mode otherwise exhausting your monitor's specs ! where the vertical scan rate lies about 30% or more under the maximum of your ! monitor, hand-designing an interlaced mode (probably with somewhat higher reso- ! lution) could deliver superior results, but I won't promise it. ! 13. Questions and Answers ! Q. The example you gave is not a standard screen size, can I use it? ! A. Why not? There is NO reason whatsoever why you have to use 640x480, ! 800x600, or even 1024x768. The XFree86 servers let you configure your hardware ! with a lot of freedom. It usually takes two to three tries to come up the ! right one. The important thing to shoot for is high refresh rate with reason- ! able viewing area. not high resolution at the price of eye-tearing flicker! ! Q. It this the only resolution given the 65Mhz dot clock and 55Khz HSF? ! A. Absolutely not! You are encouraged to follow the general procedure and do ! some trial-and-error to come up a setting that's really to your liking. Exper- ! imenting with this can be lots of fun. Most settings may just give you nasty ! video hash, but in practice a modern multi-sync monitor is usually not damaged ! easily. Be sure though, that your monitor can support the frame rates of your ! mode before using it for longer times. ! Beware fixed-frequency monitors! This kind of hacking around can damage them ! rather quickly. Be sure you use valid refresh rates for every experiment on ! them. ! Q. You just mentioned two standard resolutions. In Xconfig, there are many ! standard resolutions available, can you tell me whether there's any point in ! tinkering with timings? ! A. Absolutely! Take, for example, the "standard" 640x480 listed in the current ! Xconfig. It employs 25Mhz driving frequency, frame lengths are 800 and 525 => ! refresh rate ~ 59.5Hz. Not too bad. But 28Mhz is a commonly available driving ! frequency from many SVGA boards. If we use it to drive 640x480, following the ! procedure we discussed above, you would get frame lengths like 812 and 505. ! XFree86 Video Timings HOWTO + Now the refresh rate is raised to 68Hz, a quite significant improvement over + the standard one. ! Q. Can you summarize what we have discussed so far? + A. In a nutshell: + 1. for any fixed driving frequency, raising max resolution incurs the + penalty of lowering refresh rate and thus introducing more flicker. + 2. if high resolution is desirable and your monitor supports it, try to get + a SVGA card that provides a matching dot clock or DCF. The higher, the + better! ! 14. Fixing Problems with the Image. ! OK, so you've got your X configuration numbers. You put them in Xconfig with a ! test mode label. You fire up X, hot-key to the new mode, ... and the image ! doesn't look right. What do you do? Here's a list of common problems and how ! to fix them. ! (Fixing these minor distortions is where xvidtune(1) really shines.) ! You move the image by changing the sync pulse timing. You scale it by changing ! the frame length (you need to move the sync pulse to keep it in the same rela- ! tive position, otherwise scaling will move the image as well). Here are some ! more specific recipes: ! The horizontal and vertical positions are independent. That is, moving the ! image horizontally doesn't affect placement vertically, or vice-versa. How- ! ever, the same is not quite true of scaling. While changing the horizontal ! size does nothing to the vertical size or vice versa, the total change in both ! may be limited. In particular, if your image is too large in both dimensions ! you will probably have to go to a higher dot clock to fix it. Since this ! raises the usable resolution, it is seldom a problem! ! 14.1 The image is displaced to the left or right ! To fix this, move the horizontal sync pulse. That is, increment or decrement ! (by a multiple of 8) the middle two numbers of the horizontal timing section ! that define the leading and trailing edge of the horizontal sync pulse. ! If the image is shifted left (right border too large, you want to move the ! image to the right) decrement the numbers. If the image is shifted right (left ! border too large, you want it to move left) increment the sync pulse. ! 14.2 The image is displaced up or down ! To fix this, move the vertical sync pulse. That is, increment or decrement the ! middle two numbers of the vertical timing section that define the leading and ! trailing edge of the vertical sync pulse. + If the image is shifted up (lower border too large, you want to move the image ! XFree86 Video Timings HOWTO ! down) decrement the numbers. If the image is shifted down (top border too ! large, you want it to move up) increment the numbers. ! 14.3 The image is too large both horizontally and vertically ! Switch to a higher card clock speed. If you have multiple modes in your clock ! file, possibly a lower-speed one is being activated by mistake. ! 14.4 The image is too wide (too narrow) horizontally ! To fix this, increase (decrease) the horizontal frame length. That is, change ! the fourth number in the first timing section. To avoid moving the image, also ! move the sync pulse (second and third numbers) half as far, to keep it in the ! same relative position. ! 14.5 The image is too deep (too shallow) vertically ! To fix this, increase (decrease) the vertical frame length. That is, change ! the fourth number in the second timing section. To avoid moving the image, ! also move the sync pulse (second and third numbers) half as far, to keep it in ! the same relative position. ! Any distortion that can't be handled by combining these techniques is probably ! evidence of something more basically wrong, like a calculation mistake or a ! faster dot clock than the monitor can handle. + Finally, remember that increasing either frame length will decrease your + refresh rate, and vice-versa. ! 15. Plotting Monitor Capabilities + To plot a monitor mode diagram, you'll need the gnuplot package (a freeware + plotting language for UNIX-like operating systems) and the tool modeplot, a + shell/gnuplot script to plot the diagram from your monitor characteristics, + entered as command-line options. + Here is a copy of modeplot: ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! XFree86 Video Timings HOWTO ! ! ! ! #!/bin/sh ! # ! # modeplot -- generate X mode plot of available monitor modes ! # ! # Do `modeplot -?' to see the control options. ! # ! # ($Id: VideoModes.doc /main/14 1998/03/06 16:40:07 kaleb $) ! ! # Monitor description. Bandwidth in MHz, horizontal frequencies in kHz ! # and vertical frequencies in Hz. ! TITLE="Viewsonic 21PS" ! BANDWIDTH=185 ! MINHSF=31 ! MAXHSF=85 ! MINVSF=50 ! MAXVSF=160 ! ASPECT="4/3" ! vesa=72.5 # VESA-recommended minimum refresh rate ! ! while [ "$1" != "" ] ! do ! case $1 in ! -t) TITLE="$2"; shift;; ! -b) BANDWIDTH="$2"; shift;; ! -h) MINHSF="$2" MAXHSF="$3"; shift; shift;; ! -v) MINVSF="$2" MAXVSF="$3"; shift; shift;; ! -a) ASPECT="$2"; shift;; ! -g) GNUOPTS="$2"; shift;; ! -?) cat <" name of monitor defaults to "Viewsonic 21PS" + -b bandwidth in MHz defaults to 185 + -h min & max HSF (kHz) defaults to 31 85 + -v min & max VSF (Hz) defaults to 50 160 + -a aspect ratio defaults to 4/3 + -g "" pass options to gnuplot + The -b, -h and -v options are required, -a, -t, -g optional. You can + use -g to pass a device type to gnuplot so that (for example) modeplot's + output can be redirected to a printer. See gnuplot(1) for details. ! The modeplot tool was created by Eric S. Raymond based on ! analysis and scratch code by Martin Lottermoser + This is modeplot $Revision: /main/14 $ + EOF + exit;; + esac + shift + done + gnuplot $GNUOPTS <. ! Eric S. Raymond reworked, reorganized, and massively ! rewrote Chin Fang's original in an attempt to understand it. In the process, ! he merged in most of a different how-to by Bob Crosson . ! The material on interlaced modes is largely by David Kastrup ! Martin Lottermoser contributed the idea of ! using gnuplot to make mode diagrams and did the mathematical analysis behind ! modeplot. The distributed modeplot was redesigned and generalized by ESR from ! Martin's original gnuplot code for one case. ! Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/VidModes.sgml,v 3.11.2.2 1998/02/20 23:10:30 dawes Exp $ ! $TOG: VideoModes.doc /main/14 1998/03/06 16:40:07 kaleb $ *************** *** 1115,1241 **** - # the following line works but is right of center - "752x564" 40 752 784 944 1088 564 567 569 611 - # 44.5 752 792 976 1240 564 567 570 600 - # - # this line fixes the problem with the previous line - #"752x564" 40 752 816 976 1088 564 567 569 611 - # - # trying to increase the vertical display size, it works - #"752x614" 40 752 816 976 1088 614 617 619 661 - # - # trying to increase the horiz. display size, it works - #"784x564" 40 784 816 976 1088 564 567 569 611 - # - # the following works but is to the right of center - #"784x614" 40 784 816 976 1088 614 617 619 661 - # - # the following corrects the uncentered problem of the previous one - "784x614" 40 784 848 1008 1088 614 617 619 661 - # - # trying to increase the display size - # the following works, the display is slightly off center to the left - #"800x614" 40 800 864 1024 1088 614 617 619 661 - # - # the following corrects the problem of the previous entry - "800x614" 40 800 864 1024 1104 614 617 619 661 - # - # increase the display size, it works - "816x614" 40 816 880 1040 1120 614 617 619 661 - # - # increase the display size, it works - "800x620" 40 800 864 1024 1104 620 623 625 661 - # - # increase the display size, it works - "816x620" 40 816 880 1040 1120 620 623 625 661 - # - # increase the display size, it works - "832x630" 40 832 896 1056 1136 630 633 635 661 - # - # change the display size, it works but flickers badly - "848x618" 40 848 912 1072 1152 618 621 623 661 - 12. Fixing Problems with the Image. - OK, so you've got your X configuration numbers. You put them in - Xconfig with a test mode label. You fire up X, hot-key to the new - mode, ... and the image doesn't look right. What do you do? Here's a - list of common problems and how to fix them. - You *move* the image by changing the sync pulse timing. You *scale* - it by changing the frame length (you need to move the sync pulse to - keep it in the same relative position, otherwise scaling will move the - image as well). Here are some more specific recipes: - The horizontal and vertical positions are independent. That is, - moving the image horizontally doesn't affect placement vertically, or - vice-versa. However, the same is not quite true of scaling. While - changing the horizontal size does nothing to the vertical size or vice - versa, the total change in both may be limited. In particular, if - your image is too large in both dimensions you will probably have to - go to a higher dot clock to fix it. Since this raises the usable - resolution, it is seldom a problem! - The image is displaced to the left or right - To fix this, move the horizontal sync pulse. That is, increment or - decrement (by a multiple of 8) the middle two numbers of the - horizontal timing section that define the leading and trailing edge of - the horizontal sync pulse. - If the image is shifted left (right border too large, you want to move - the image to the right) decrement the numbers. If the image is - shifted right (left border too large, you want it to move left) - increment the sync pulse. - The image is displaced up or down - To fix this, move the vertical sync pulse. That is, increment or - decrement the middle two numbers of the vertical timing section that - define the leading and trailing edge of the vertical sync pulse. - If the image is shifted up (lower border too large, you want to move - the image down) decrement the numbers. If the image is shifted down - (top border too large, you want it to move up) increment the numbers. - The image is too wide (too narrow) horizontally - To fix this, increase (decrease) the horizontal frame length. That - is, change the fourth number in the first timing section. To avoid - moving the image, also move the sync pulse (second and third numbers) - half as far, to keep it in the same relative position. - The image is too deep (too shallow) vertically - To fix this, decrease (increase) the vertical frame length. That is, - change the fourth number in the second timing section. To avoid - moving the image, also move the sync pulse (second and third numbers) - half as far, to keep it in the same relative position. - Any distortion that can't be handled by combining these techniques is - probably evidence of something more basically wrong, like a - calculation mistake or a faster dot clock than the monitor can handle. - Finally, remember that increasing either frame length will decrease - your refresh rate, and vice-versa. - Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/VidModes.sgml,v 3.7 1995/08/13 09:45:11 dawes Exp $ - $TOG: VideoModes.doc /main/13 1997/07/19 10:30:10 kaleb $ --- 1718,1755 ---- + XFree86 Video Timings HOWTO *************** *** 1254,1257 **** ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/VideoModes.doc,v 3.14 1996/12/23 06:45:20 dawes Exp $ --- 1768,1851 ---- ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! CONTENTS ! ! ! ! 1. Disclaimer .............................................................. 1 ! ! 2. Introduction ............................................................ 1 ! ! 3. How Video Displays Work ................................................. 2 ! ! 4. Basic Things to Know about your Display and Adapter ..................... 3 ! 4.1 The monitor's video bandwidth: ..................................... 6 ! 4.2 What these control: ................................................ 7 ! ! 5. Interpreting the Basic Specifications ................................... 7 ! 5.1 About Bandwidth: ................................................... 8 ! 5.2 Sync Frequencies and the Refresh Rate: ............................. 9 ! ! 6. Tradeoffs in Configuring your System ................................... 10 ! ! 7. Memory Requirements .................................................... 11 ! ! 8. Computing Frame Sizes .................................................. 12 ! ! 9. Black Magic and Sync Pulses ............................................ 13 ! 9.1 Horizontal Sync: .................................................. 13 ! 9.2 Vertical Sync: .................................................... 15 ! ! 10. Putting it All Together ................................................ 16 ! ! 11. Overdriving Your Monitor ............................................... 18 ! ! 12. Using Interlaced Modes ................................................. 19 ! ! 13. Questions and Answers .................................................. 20 ! ! 14. Fixing Problems with the Image. ........................................ 21 ! 14.1 The image is displaced to the left or right ....................... 21 ! 14.2 The image is displaced up or down ................................. 21 ! 14.3 The image is too large both horizontally and vertically ........... 22 ! 14.4 The image is too wide (too narrow) horizontally ................... 22 ! 14.5 The image is too deep (too shallow) vertically .................... 22 ! ! 15. Plotting Monitor Capabilities .......................................... 22 ! ! 16. Credits ................................................................ 26 ! ! ! ! ! ! ! ! ! ! ! i ! ! ! ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/VideoModes.doc,v 3.14.2.2 1998/02/20 23:14:34 dawes Exp $ *** ./programs/Xserver/hw/xfree86/doc/man/XF86DGA.man@@/PUBLIC-LATEST Tue Nov 11 12:05:33 1997 --- xc/programs/Xserver/hw/xfree86/doc/man/XF86DGA.man Mon Mar 9 13:00:14 1998 *************** *** 1,12 **** .\" Copyright (c) 1996 The XFree86 Project ! .\" $XFree86: xc/programs/Xserver/hw/xfree86/doc/man/XF86DGA.man,v 3.5.2.1 1997/05/21 15:02:36 dawes Exp $ ! .\" $TOG: XF86DGA.man /main/9 1997/11/11 12:08:52 kaleb $ .\" .de ZN .ie t \fB\^\\$1\^\fR\\$2 .el \fI\^\\$1\^\fP\\$2 .. ! .TH XF86DGA 3X11 "Release 6.4 (XFree86 3.3.1)" "X Version 11" "X FUNCTIONS" .SH NAME XF86DGAQueryExtension, XF86DGAQueryVersion, XF86DGAQueryDirectVideo, XF86DGAGetVideo, XF86DGADirectVideo, XF86DGASetVidPage, XF86DGASetViewPort, XF86DGAViewPortChanged, XF86DGAGetViewPortSize, XF86DGAInstallColormap, XF86DGAForkApp \- XFree86-DGA extension interface functions .SH SYNTAX --- 1,12 ---- .\" Copyright (c) 1996 The XFree86 Project ! .\" $XFree86: xc/programs/Xserver/hw/xfree86/doc/man/XF86DGA.man,v 3.5.2.2 1998/02/26 13:59:04 dawes Exp $ ! .\" $TOG: XF86DGA.man /main/10 1998/03/09 13:02:02 kaleb $ .\" .de ZN .ie t \fB\^\\$1\^\fR\\$2 .el \fI\^\\$1\^\fP\\$2 .. ! .TH XF86DGA 3X11 "3.3.2" "XFree86" "X FUNCTIONS" .SH NAME XF86DGAQueryExtension, XF86DGAQueryVersion, XF86DGAQueryDirectVideo, XF86DGAGetVideo, XF86DGADirectVideo, XF86DGASetVidPage, XF86DGASetViewPort, XF86DGAViewPortChanged, XF86DGAGetViewPortSize, XF86DGAInstallColormap, XF86DGAForkApp \- XFree86-DGA extension interface functions .SH SYNTAX *** ./programs/Xserver/hw/xfree86/doc/man/XF86Misc.man@@/PUBLIC-LATEST Tue Nov 4 21:17:49 1997 --- xc/programs/Xserver/hw/xfree86/doc/man/XF86Misc.man Fri Mar 6 16:38:57 1998 *************** *** 1,15 **** ! .\" $TOG: XF86Misc.man /main/8 1997/11/04 21:20:44 kaleb $ .\" .\" .\" .\" Copyright (c) 1996 Joe Moss, The XFree86 Project .\" ! .\" $XFree86: xc/programs/Xserver/hw/xfree86/doc/man/XF86Misc.man,v 3.6.2.1 1997/05/21 15:02:36 dawes Exp $ .de ZN .ie t \fB\^\\$1\^\fR\\$2 .el \fI\^\\$1\^\fP\\$2 .. ! .TH XF86MISC 3X11 "Release 6.4 (XFree86 3.3.1)" "X Version 11" "X FUNCTIONS" .SH NAME XF86MiscQueryExtension, XF86MiscQueryVersion, XF86MiscGetMouseSettings, XF86MiscSetMouseSettings, XF86MiscGetKbdSettings, XF86MiscSetKbdSettings \- XFree86-Misc extension interface functions .SH SYNTAX --- 1,15 ---- ! .\" $TOG: XF86Misc.man /main/9 1998/03/06 16:40:35 kaleb $ .\" .\" .\" .\" Copyright (c) 1996 Joe Moss, The XFree86 Project .\" ! .\" $XFree86: xc/programs/Xserver/hw/xfree86/doc/man/XF86Misc.man,v 3.6.2.3 1998/02/26 13:59:04 dawes Exp $ .de ZN .ie t \fB\^\\$1\^\fR\\$2 .el \fI\^\\$1\^\fP\\$2 .. ! .TH XF86MISC 3X11 "3.3.2" "XFree86" "X FUNCTIONS" .SH NAME XF86MiscQueryExtension, XF86MiscQueryVersion, XF86MiscGetMouseSettings, XF86MiscSetMouseSettings, XF86MiscGetKbdSettings, XF86MiscSetKbdSettings \- XFree86-Misc extension interface functions .SH SYNTAX *************** *** 97,102 **** --- 97,104 ---- int type; /* mouse protocol */ int baudrate; /* 1200, 2400, 4800, or 9600 */ int samplerate; /* samples per second */ + int resolution; /* resolution, count per inch */ + int buttons; /* number of buttons */ Bool emulate3buttons; /* Button1+Button3 -> Button2 ? */ int emulate3timeout; /* in milliseconds */ Bool chordmiddle; /* Button1+Button3 == Button2 ? */ *************** *** 160,165 **** --- 162,169 ---- .IP 2) 3 The protocol can not be changed to or from Xqueue or OsMouse .IP 3) 3 + The buttons field can not be changed + .IP 4) 3 Invalid combinations of parameters are not allowed .RE .PP *************** *** 167,173 **** except the first \- the contents of the device field are simply ignored. .PP A change of the protocol causes the device to be closed and reopened. ! Changes to the baud rate, sample rate, or flags, when applicable to the selected protocol, also cause a reopen of the device. A reopen can be forced by using the MF_REOPEN flag, except in the case of the OsMouse and Xqueue protocols which ignore all attempts --- 171,178 ---- except the first \- the contents of the device field are simply ignored. .PP A change of the protocol causes the device to be closed and reopened. ! Changes to the baud rate, sample rate, resolution or flags, ! when applicable to the selected protocol, also cause a reopen of the device. A reopen can be forced by using the MF_REOPEN flag, except in the case of the OsMouse and Xqueue protocols which ignore all attempts *** ./programs/Xserver/hw/xfree86/doc/man/XF86VM.man@@/PUBLIC-LATEST Tue Nov 4 21:17:53 1997 --- xc/programs/Xserver/hw/xfree86/doc/man/XF86VM.man Fri Mar 6 16:39:02 1998 *************** *** 1,16 **** ! .\" $TOG: XF86VM.man /main/7 1997/11/04 21:20:48 kaleb $ .\" .\" .\" .\" .\" Copyright (c) 1996 Joe Moss, The XFree86 Project ! .\" $XFree86: xc/programs/Xserver/hw/xfree86/doc/man/XF86VM.man,v 3.6.2.2 1997/05/25 14:13:42 dawes Exp $ .\" .de ZN .ie t \fB\^\\$1\^\fR\\$2 .el \fI\^\\$1\^\fP\\$2 .. ! .TH XF86VIDMODE 3X11 "Release 6.4 (XFree86 3.3.1)" "X Version 11" "X FUNCTIONS" .SH NAME XF86VidModeQueryExtension, XF86VidModeQueryVersion, XF86VidModeGetModeLine, XF86VidModeGetAllModeLines, XF86VidModeDeleteModeLine, XF86VidModeModModeLine, XF86VidModeValidateModeLine, XF86VidModeSwitchMode, XF86VidModeSwitchToMode, XF86VidModeLockModeSwitch, XF86VidModeGetMonitor, XF86VidModeGetViewPort, XF86VidModeSetViewPort \- XFree86-VidMode extension interface functions .SH SYNTAX --- 1,16 ---- ! .\" $TOG: XF86VM.man /main/8 1998/03/06 16:40:40 kaleb $ .\" .\" .\" .\" .\" Copyright (c) 1996 Joe Moss, The XFree86 Project ! .\" $XFree86: xc/programs/Xserver/hw/xfree86/doc/man/XF86VM.man,v 3.6.2.3 1998/02/26 13:59:05 dawes Exp $ .\" .de ZN .ie t \fB\^\\$1\^\fR\\$2 .el \fI\^\\$1\^\fP\\$2 .. ! .TH XF86VIDMODE 3X11 "3.3.2" "XFree86" "X FUNCTIONS" .SH NAME XF86VidModeQueryExtension, XF86VidModeQueryVersion, XF86VidModeGetModeLine, XF86VidModeGetAllModeLines, XF86VidModeDeleteModeLine, XF86VidModeModModeLine, XF86VidModeValidateModeLine, XF86VidModeSwitchMode, XF86VidModeSwitchToMode, XF86VidModeLockModeSwitch, XF86VidModeGetMonitor, XF86VidModeGetViewPort, XF86VidModeSetViewPort \- XFree86-VidMode extension interface functions .SH SYNTAX *** ./programs/Xserver/hw/xfree86/doc/sgml/CPYRIGHT.sgml@@/PUBLIC-LATEST Wed Feb 11 10:15:01 1998 --- xc/programs/Xserver/hw/xfree86/doc/sgml/CPYRIGHT.sgml Fri Mar 6 16:39:12 1998 *************** *** 10,16 **** copyright:

! Copyright (C) 1994-1997 The XFree86 Project, Inc. All Rights Reserved. Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), --- 10,16 ---- copyright:

! Copyright (C) 1994-1998 The XFree86 Project, Inc. All Rights Reserved. Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), *************** *** 139,145 **** NVidia Corp

! Copyright (c) 1996 NVIDIA, Corp. All rights reserved. NOTICE TO USER: The source code is copyrighted under U.S. and international laws. NVIDIA, Corp. of Sunnyvale, California owns --- 139,145 ---- NVidia Corp

! Copyright (c) 1996-1998 NVIDIA, Corp. All rights reserved. NOTICE TO USER: The source code is copyrighted under U.S. and international laws. NVIDIA, Corp. of Sunnyvale, California owns *************** *** 153,159 **** and internal comments to the code, notices to the end user as follows: ! Copyright (c) 1996 NVIDIA, Corp. NVIDIA design patents pending in the U.S. and foreign countries. NVIDIA, CORP. MAKES NO REPRESENTATION ABOUT THE SUITABILITY OF --- 153,159 ---- and internal comments to the code, notices to the end user as follows: ! Copyright (c) 1996-1998 NVIDIA, Corp. NVIDIA design patents pending in the U.S. and foreign countries. NVIDIA, CORP. MAKES NO REPRESENTATION ABOUT THE SUITABILITY OF *************** *** 170,182 **** ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/CPYRIGHT.sgml,v 3.9.2.1 1997/06/08 15:41:26 dawes Exp $ ! $TOG: CPYRIGHT.sgml /main/8 1998/02/11 10:15:24 kaleb $ --- 170,182 ---- ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/CPYRIGHT.sgml,v 3.9.2.2 1998/01/24 11:55:06 dawes Exp $ ! $TOG: CPYRIGHT.sgml /main/9 1998/03/06 16:40:49 kaleb $ *** ./programs/Xserver/hw/xfree86/doc/sgml/DECtga.sgml@@/PUBLIC-LATEST Sat Jul 19 10:31:12 1997 --- xc/programs/Xserver/hw/xfree86/doc/sgml/DECtga.sgml Fri Mar 6 16:39:16 1998 *************** *** 3,9 **** Information for DEC 21030 Users (aka TGA) <author>The XFree86 Project, Inc. ! <date>20th May 1997 <toc> <p> --- 3,9 ---- <title>Information for DEC 21030 Users (aka TGA) <author>The XFree86 Project, Inc. ! <date>26th February 1998 <toc> <p> *************** *** 36,41 **** --- 36,43 ---- If the server does not detect the base address of the 21030, then Check /proc/pci for the 21030 and look for the "Prefetchable 32 bit memory at 0x???????" and enter this as your MemBase setting. + In XFree86 v3.3.2, if you are using Linux > v2.0.27 with the PCI + routines the server should detect the base address automatically. </descrip> <item>No acceleration features of the 21030 have been taken advantage of yet! *************** *** 47,53 **** <p> <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/DECtga.sgml,v 3.6.2.1 1997/05/21 15:02:39 dawes Exp $ </verb> </article> --- 49,55 ---- <p> <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/DECtga.sgml,v 3.6.2.3 1998/02/26 20:11:25 hohndel Exp $ </verb> </article> *** ./programs/Xserver/hw/xfree86/doc/sgml/DocIndex.sgml@@/PUBLIC-LATEST Sat Jul 19 10:31:19 1997 --- xc/programs/Xserver/hw/xfree86/doc/sgml/DocIndex.sgml Fri Mar 6 16:39:20 1998 *************** *** 5,23 **** <!-- Title information --> <title>List of XFree86 documentation <author>The XFree86 Project, Inc ! <date>22 January 1997 <sect> Available Documentation <p> <itemize> ! <item><htmlurl name="Release Notes for XFree86&tm; 3.3" url="RELNOTES.html"> ! <item><htmlurl name="README for XFree86&tm; 3.3" url="README.html"> <item><htmlurl name="Copyright" url="COPYRIGHT.html"> <item><htmlurl name="Quick Start Guide for XFree86" url="QuickStart.html"> <item><htmlurl name="The XInput extension in XFree86" url="xinput.html"> <!-- --- 5,25 ---- <!-- Title information --> <title>List of XFree86 documentation <author>The XFree86 Project, Inc ! <date>8 August 1997 <sect> Available Documentation <p> <itemize> ! <item><htmlurl name="Release Notes for XFree86&tm; 3.3.2" url="RELNOTES.html"> ! <item><htmlurl name="README for XFree86&tm; 3.3.2" url="README.html"> <item><htmlurl name="Copyright" url="COPYRIGHT.html"> <item><htmlurl name="Quick Start Guide for XFree86" url="QuickStart.html"> + <item><htmlurl name="Mouse Support in XFree86" + url="mouse.html"> <item><htmlurl name="The XInput extension in XFree86" url="xinput.html"> <!-- *************** *** 30,44 **** url="isc.html"> <item><htmlurl name="Information for Linux Users" url="Linux.html"> ! <item><htmlurl name="README for XFree86 3.3 on LynxOS" url="LynxOS.html"> <!-- <item><htmlurl name="README for XFree86 3.1 on Mach" url="Mach.html"> --> ! <item><htmlurl name="README for XFree86 3.3 on NetBSD and OpenBSD" url="NetBSD.html"> ! <item><htmlurl name="README for XFree86 3.3 on OS/2" url="OS2.html"> <item><htmlurl name="Notes on Rebuilding XFree86/OS2 from Scratch" url="OS2Notes.html"> --- 32,48 ---- url="isc.html"> <item><htmlurl name="Information for Linux Users" url="Linux.html"> ! <item><htmlurl name="README for XFree86 3.3.2 on LynxOS" url="LynxOS.html"> <!-- <item><htmlurl name="README for XFree86 3.1 on Mach" url="Mach.html"> --> ! <item><htmlurl name="README for XFree86 3.3.2 on NetBSD" url="NetBSD.html"> ! <item><htmlurl name="README for XFree86 3.3.2 on OpenBSD" ! url="NetBSD.html"> ! <item><htmlurl name="README for XFree86 3.3.2 on OS/2" url="OS2.html"> <item><htmlurl name="Notes on Rebuilding XFree86/OS2 from Scratch" url="OS2Notes.html"> *************** *** 52,63 **** url="Config.html"> <item><htmlurl name="Building XFree86" url="BUILD.html"> ! <!-- ! <item><htmlurl name="The Hitchhiker's Guide to X386/XFree86 Video Timing" url="VideoModes.html"> ! <item><htmlurl name="Readme for the XFree86 3.1.2 LinkKit" url="LinkKit.html"> - --> <item><htmlurl name="How to add an (S)VGA driver to XFree86" url="VGADriver.html"> <item><htmlurl name="Information for using/developing external clock setting programs" --- 56,65 ---- url="Config.html"> <item><htmlurl name="Building XFree86" url="BUILD.html"> ! <item><htmlurl name="XFree86 Video Timings HOWTO" url="VideoModes.html"> ! <item><htmlurl name="Readme for the XFree86 3.3.2 LinkKit" url="LinkKit.html"> <item><htmlurl name="How to add an (S)VGA driver to XFree86" url="VGADriver.html"> <item><htmlurl name="Information for using/developing external clock setting programs" *************** *** 64,69 **** --- 66,73 ---- url="clkprog.html"> <item><htmlurl name="Notes on the AGX Server" url="agx.html"> + <item><htmlurl name="Information for Alliance Promotion Chipset Users" + url="apm.html"> <item><htmlurl name="Information for ARK Logic Chipset Users" url="ark.html"> <item><htmlurl name="ATI boards README" *************** *** 80,86 **** url="Mach64.html"> <item><htmlurl name="Information for Matrox Millennium Users" url="MGA.html"> ! <item><htmlurl name="Information for NVidia NV1 / SGS-Thomson Users" url="NV1.html"> <item><htmlurl name="Information for Oak Technologies Inc. Chipset Users" url="Oak.html"> --- 84,90 ---- url="Mach64.html"> <item><htmlurl name="Information for Matrox Millennium Users" url="MGA.html"> ! <item><htmlurl name="Information for NVidia / SGS-Thomson NV1, Riva128 Users" url="NV1.html"> <item><htmlurl name="Information for Oak Technologies Inc. Chipset Users" url="Oak.html"> *************** *** 107,119 **** </itemize> <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/DocIndex.sgml,v 3.24.2.4 1997/05/24 11:35:35 dawes Exp $ ! $TOG: DocIndex.sgml /main/16 1997/07/19 10:31:21 kaleb $ </verb> </article> --- 111,123 ---- </itemize> <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/DocIndex.sgml,v 3.24.2.7 1998/02/28 11:11:41 dawes Exp $ ! $TOG: DocIndex.sgml /main/17 1998/03/06 16:40:57 kaleb $ </verb> </article> *** ./programs/Xserver/hw/xfree86/doc/sgml/FreeBSD.sgml@@/PUBLIC-LATEST Sat Jul 19 10:31:25 1997 --- xc/programs/Xserver/hw/xfree86/doc/sgml/FreeBSD.sgml Fri Mar 6 16:39:24 1998 *************** *** 3,9 **** <article> <title> README for XFree86 on FreeBSD <author>Rich Murphey, David Dawes ! <date>16 May 1997 <toc> --- 3,9 ---- <article> <title> README for XFree86 on FreeBSD <author>Rich Murphey, David Dawes ! <date>25 Feb 1998 <toc> *************** *** 54,60 **** unpack. If you can't decide what to pick and you have 52Mb of disk space, it's safe to unpack everything. ! At a minimum you need to unpack the 'required' <tt/X33*.tgz/ archives plus at least one server that matches your vga card. You'll need 13Mb for the minimum required run-time binaries only. --- 54,60 ---- unpack. If you can't decide what to pick and you have 52Mb of disk space, it's safe to unpack everything. ! At a minimum you need to unpack the 'required' <tt/X332*.tgz/ archives plus at least one server that matches your vga card. You'll need 13Mb for the minimum required run-time binaries only. *************** *** 62,74 **** <tag/Required:/ <descrip> ! <tag/X33bin.tgz/ all the executable X client applications and shared libs ! <tag/X33fnts.tgz/ the misc, 75 dpi and PEX fonts ! <tag/X33lib.tgz/ data files needed at runtime </descrip> --- 62,74 ---- <tag/Required:/ <descrip> ! <tag/X332bin.tgz/ all the executable X client applications and shared libs ! <tag/X332fnts.tgz/ the misc, 75 dpi and PEX fonts ! <tag/X332lib.tgz/ data files needed at runtime </descrip> *************** *** 75,81 **** <tag/Required unless you have already customized your configuration files: <descrip> ! <tag/X33cfg.tgz/ customizable xinit and xdm runtime configuration files </descrip> --- 75,81 ---- <tag/Required unless you have already customized your configuration files: <descrip> ! <tag/X332cfg.tgz/ customizable xinit and xdm runtime configuration files </descrip> *************** *** 82,163 **** <tag/Choose at least one server:/ <descrip> ! <tag/X338514.tgz/ 8-bit color for IBM 8514 and true compatibles. ! <tag/X33AGX.tgz/ 8 and 16-bit color for AGX and XGA boards. ! <tag/X33I128.tgz/ 8 and 16-bit color for I128 boards. ! <tag/X33Ma32.tgz/ 8 and 16-bit color for ATI Mach32 boards. ! <tag/X33Ma64.tgz/ 8, 16 and 32-bit color for ATI Mach64 boards. ! <tag/X33Ma8.tgz/ 8-bit color for ATI Mach8 boards. ! <tag/X33Mono.tgz/ 1-bit monochrome for VGA, Super-VGA, Hercules, and others. ! <tag/X33P9K.tgz/ 8, 16, and 32-bit color for Weitek P9000 boards (Diamond Viper). ! <tag/X33S3.tgz/ 8, 16 and 32-bit color for S3 boards. ! <tag/X33S3V.tgz/ 8 and 16-bit color for S3 ViRGE boards. ! <tag/X33SVGA.tgz/ >=8-bit color for Super-VGA cards. ! <tag/X33VG16.tgz/ 4-bit color for VGA and Super-VGA cards ! <tag/X33W32.tgz/ 8-bit Color for ET4000/W32, /W32i, /W32p and ET6000 cards. ! <tag/X339GAN.tgz/ 8-bit color for PC98 GA-98NB/WAP boards ! <tag/X339480.tgz/ 8-bit color for PC98 PEGC ! <tag/X339NKV.tgz/ 8-bit color for PC98 NEC-CIRRUS/EPSON NKV/NKV2 boards ! <tag/X339WBS.tgz/ 8-bit color for PC98 WAB-S boards ! <tag/X339WEP.tgz/ 8-bit color for PC98 WAB-EP boards ! <tag/X339WSN.tgz/ 8-bit color for PC98 WSN-A2F boards ! <tag/X339EGC.tgz/ 4-bit color for PC98 EGC ! <tag/X339TGU.tgz/ ! 8 and 16-bit color for PC98 Trident Cyber9320/9680 boards ! <tag/X339NS3.tgz/ 8 and 16-bit color for PC98 NEC S3 boards ! <tag/X339SPW.tgz/ 8 and 16-bit color for PC98 S3 PW/PCSKB boards ! <tag/X339LPW.tgz/ 8 and 16-bit color for PC98 S3 PW/LB boards ! <tag/X339GA9.tgz/ ! 8 and 16-bit color for PC98 S3 GA-968 boards ! <tag/X33nest.tgz/ A nested server running as a client window on another display. </descrip> --- 82,169 ---- <tag/Choose at least one server:/ <descrip> ! <tag/X3328514.tgz/ 8-bit color for IBM 8514 and true compatibles. ! <tag/X332AGX.tgz/ 8 and 16-bit color for AGX and XGA boards. ! <tag/X332I128.tgz/ 8 and 16-bit color for I128 boards. ! <tag/X332Ma32.tgz/ 8 and 16-bit color for ATI Mach32 boards. ! <tag/X332Ma64.tgz/ 8, 16 and 32-bit color for ATI Mach64 boards. ! <tag/X332Ma8.tgz/ 8-bit color for ATI Mach8 boards. ! <tag/X332Mono.tgz/ 1-bit monochrome for VGA, Super-VGA, Hercules, and others. ! <tag/X332P9K.tgz/ 8, 16, and 32-bit color for Weitek P9000 boards (Diamond Viper). ! <tag/X332S3.tgz/ 8, 16 and 32-bit color for S3 boards. ! <tag/X332S3V.tgz/ 8 and 16-bit color for S3 ViRGE boards. ! <tag/X332SVGA.tgz/ >=8-bit color for Super-VGA cards. ! <tag/X332VG16.tgz/ 4-bit color for VGA and Super-VGA cards ! <tag/X332W32.tgz/ 8-bit Color for ET4000/W32, /W32i, /W32p and ET6000 cards. ! <tag/X3329GAN.tgz/ 8-bit color for PC98 GA-98NB/WAP boards ! <tag/X3329480.tgz/ 8-bit color for PC98 PEGC ! <tag/X3329NKV.tgz/ 8-bit color for PC98 NEC-CIRRUS/EPSON NKV/NKV2 boards ! <tag/X3329WBS.tgz/ 8-bit color for PC98 WAB-S boards ! <tag/X3329WEP.tgz/ 8-bit color for PC98 WAB-EP boards ! <tag/X3329WSN.tgz/ 8-bit color for PC98 WSN-A2F boards ! <tag/X3329EGC.tgz/ 4-bit color for PC98 EGC ! <tag/X3329TGU.tgz/ ! 8 and 16-bit color for PC98 Trident Cyber9320/968x boards ! <tag/X3329MGA.tgz/ ! >=8-bit color for PC98 Millennium/Mystique cards. ! ! <tag/X3329SVG.tgz/ ! 8-bit color for PC98 Cirrus755x boards ! ! <tag/X3329NS3.tgz/ 8 and 16-bit color for PC98 NEC S3 boards ! <tag/X3329SPW.tgz/ 8 and 16-bit color for PC98 S3 PW/PCSKB boards ! <tag/X3329LPW.tgz/ 8 and 16-bit color for PC98 S3 PW/LB boards ! <tag/X3329GA9.tgz/ ! 8, 16 and 32-bit color for PC98 S3 GA-968 boards ! <tag/X332nest.tgz/ A nested server running as a client window on another display. </descrip> *************** *** 165,205 **** <descrip> ! <tag/X32doc.tgz/ READMEs ! <tag/X32ps.tgz/ READMEs in PostScript ! <tag/X32html.tgz/ READMEs in HTML ! <tag/X32man.tgz/ man pages ! <tag/X32f100.tgz/ 100dpi fonts ! <tag/X32fscl.tgz/ Speedo and Type1 fonts ! <tag/X32fnon.tgz/ Japanese, Chinese and other non-english fonts ! <tag/X32fcyr.tgz/ Cyrillic fonts ! <tag/X32fsrv.tgz/ the font server and its man page ! <tag/X32prog.tgz/ config, lib*.a and *.h files needed only for compiling <!-- ! <tag/X32lkit.tgz/ (10.8Mb) X server reconfiguration kit ! <tag/X32lk98.tgz/ (14.2Mb) X server reconfiguration kit for PC98 X servers --> --- 171,211 ---- <descrip> ! <tag/X332doc.tgz/ READMEs ! <tag/X332ps.tgz/ READMEs in PostScript ! <tag/X332html.tgz/ READMEs in HTML ! <tag/X332man.tgz/ man pages ! <tag/X332f100.tgz/ 100dpi fonts ! <tag/X332fscl.tgz/ Speedo and Type1 fonts ! <tag/X332fnon.tgz/ Japanese, Chinese and other non-english fonts ! <tag/X332fcyr.tgz/ Cyrillic fonts ! <tag/X332fsrv.tgz/ the font server and its man page ! <tag/X332prog.tgz/ config, lib*.a and *.h files needed only for compiling <!-- ! <tag/X332lkit.tgz/ (10.8Mb) X server reconfiguration kit ! <tag/X332lk98.tgz/ (14.2Mb) X server reconfiguration kit for PC98 X servers --> *************** *** 241,247 **** If you are using sh (as root usually does): <tscreen><verb> ! # for i in X33*.tgz; do # tar -x -z --unlink -f $i # done </verb></tscreen> --- 247,253 ---- If you are using sh (as root usually does): <tscreen><verb> ! # for i in X332*.tgz; do # tar -x -z --unlink -f $i # done </verb></tscreen> *************** *** 248,254 **** Else, if you are using csh: <tscreen><verb> ! % foreach i (X33*.tgz) % tar -x -z --unlink -f $i % end </verb></tscreen> --- 254,260 ---- Else, if you are using csh: <tscreen><verb> ! % foreach i (X332*.tgz) % tar -x -z --unlink -f $i % end </verb></tscreen> *************** *** 269,275 **** <tscreen><verb> # for i in bin fnts lib xicf; do ! # tar -x -z --unlink -f X33$i.tgz # done </verb></tscreen> --- 275,281 ---- <tscreen><verb> # for i in bin fnts lib xicf; do ! # tar -x -z --unlink -f X332$i.tgz # done </verb></tscreen> *************** *** 279,285 **** based card you will use the XF86_SVGA server: <tscreen><verb> ! # tar -x -z --unlink -f X33SVGA.tgz # cd /usr/X11R6/bin; rm X; ln -s XF86_SVGA X </verb></tscreen> --- 285,291 ---- based card you will use the XF86_SVGA server: <tscreen><verb> ! # tar -x -z --unlink -f X332SVGA.tgz # cd /usr/X11R6/bin; rm X; ln -s XF86_SVGA X </verb></tscreen> *************** *** 371,377 **** <item>Your monitor's sync frequencies. </itemize> ! The easiest way to find which device your mouse is plugged into is to use ``<tt/cat/'' or ``<tt/kermit/'' to look at the output of the mouse. Connect to it and just make sure that it generates output when the mouse is moved or clicked: --- 377,420 ---- <item>Your monitor's sync frequencies. </itemize> ! If you plan to fine tune the screen size or position on your monitor you'll ! need the specs for sync frequencies from your monitor's manual. ! ! When you run the `XF86Setup' utility, do NOT touch the mouse until ! you are finished with mouse set up. ! Otherwise, the VGA16 server and the mouse device driver may get ! confused and you may experience mouse and/or keyboard input problems. ! ! If you are running ``<tt/moused/'' (see the man page for <tt/moused(8)/) ! in FreeBSD versions 2.2.1 or later, ! you MUST specify <tt>SysMouse</tt> as the mouse protocol type ! and <tt>/dev/sysmouse</tt> as the mouse device name, ! regardless of the brand and model of your mouse. ! ! If you are NOT running ``<tt/moused/'', you need to know the interface ! type of your mouse, <tt>/dev</tt> entry and the protocol type to use. ! ! The interface type can be determined by looking at the connector ! of the mouse. ! The serial mouse has a D-Sub female 9- or 25-pin connector. ! The bus mouse has either a D-Sub male 9-pin connector ! or a round DIN 9-pin connector. ! The PS/2 mouse is equipped with a small, round DIN 6-pin connector. ! Some mice come with adapters with which the connector can ! be converted to another. If you are to use such an adapter, ! remember the connector at the very end of the mouse/adapter pair is ! what matters. ! ! The next thing to decide is a <tt>/dev</tt> entry for the given interface. ! For the bus and PS/2 mice, there is little choice: ! the bus mouse always use <tt>/dev/mse0</tt>, ! and the PS/2 mouse is always at <tt>/dev/psm0</tt>. ! There may be more than one serial port to which the serial ! mouse can be attached. Many people often assign the first, built-in ! serial port <tt>/dev/cuaa0</tt> to the mouse. ! ! If you are not sure which serial device your mouse is plugged into, ! the easiest way to find out the device is to use ``<tt/cat/'' or ``<tt/kermit/'' to look at the output of the mouse. Connect to it and just make sure that it generates output when the mouse is moved or clicked: *************** *** 381,387 **** </verb></tscreen> If you can't find the right mouse device then use ``<tt/dmesg|grep ! sio/'' to get a list of devices that were detected upon booting: <tscreen><verb> % dmesg|grep sio --- 424,430 ---- </verb></tscreen> If you can't find the right mouse device then use ``<tt/dmesg|grep ! sio/'' to get a list of serial devices that were detected upon booting: <tscreen><verb> % dmesg|grep sio *************** *** 397,407 **** % sh MAKEDEV tty00 </verb></tscreen> ! If you plan to fine tune the screen size or position on your monitor you'll ! need the specs for sync frequencies from your monitor's manual. ! <sect>Running X <p> 8mb of memory is a recommended minimum for running X. The server, --- 440,493 ---- % sh MAKEDEV tty00 </verb></tscreen> ! You may want to create a symbolic link <tt>/dev/mouse</tt> ! pointing to the real port to which the mouse is connected, so that you ! can easily distinguish which is your ``mouse'' port later. ! The next step is to guess the appropriate protocol type for the mouse. ! In FreeBSD 2.2.6 or later, the X server may be able to automatically ! determine the appropriate protocol type, unless your mouse is of a ! relatively old model. ! Use the ``<tt/Auto/'' protocol in these versions. + In other versions of FreeBSD or if the ``<tt/Auto/'' protocol + doesn't work in 2.2.6, you have to guess a protocol type and try. + + There is rule of thumb: + + <enum> + <item>The bus mice always use the ``<tt>BusMouse</tt>'' + protocol regardless of the brand of the mouse. + <item>The ``<tt>PS/2</tt>'' protocol should always be specified for + the PS/2 mouse regardless of the brand of the mouse. + <quote> + <bf/NOTE:/ There are quite a few PS/2 mouse protocols listed in the man page + for <tt>XF86Config</tt>. But, ``<tt>PS/2</tt>'' is the only PS/2 mouse + protocol type useful in <tt>XF86Config</tt> for FreeBSD. + The other PS/2 mouse protocol types are not supported in FreeBSD. + FreeBSD version 2.2.6 and later directly support + these protocol types in the PS/2 mouse driver <tt/psm/ and it is not + necessary to tell the X server which PS/2 mouse protocol type is to + be used; ``<tt/Auto/'' should work, otherwise use ``<tt>PS/2</tt>''. + </quote> + <item>The ``<tt>Logitech</tt>'' protocol is for old mouse models + from Logitech. + Modern Logitech mice use either the ``<tt>MouseMan</tt>'' + or ``<tt>Microsoft</tt>'' protocol. + <item>Most 2-button serial mice support the ``<tt>Microsoft</tt>'' protocol. + <item>3-button serial mice may work with the ``<tt>MouseSystems</tt>'' + protocol. If it doesn't, it may work with the ``<tt>Microsoft</tt>'' + protocol although the third (middle) button won't function. + 3-button serial mice may also work with the ``<tt>MouseMan</tt>'' + protocol under which the third button may function as expected. + <item>3-button serial mice may have a small switch to choose between ``MS'' + and ``PC'', or ``2'' and ``3''. + ``MS'' or ``2'' usually mean the ``<tt>Microsoft</tt>'' protocol. + ``PC'' or ``3'' will choose the ``<tt>MouseSystems</tt>'' protocol. + <item>If the serial mouse has a roller or a wheel, it may be compatible + with the ``<tt>IntelliMouse</tt>'' protocol. + </enum> + <sect>Running X <p> 8mb of memory is a recommended minimum for running X. The server, *************** *** 437,447 **** chapter from the system maintainers manual. If you do decide to reduce your kernel configuration file, do not ! remove the two lines below (in <tt>/sys/arch/i386/conf</tt>). They ! are both required for X support: <tscreen><verb> - options XSERVER #Xserver options UCONSOLE #X Console support </verb></tscreen> --- 523,532 ---- chapter from the system maintainers manual. If you do decide to reduce your kernel configuration file, do not ! remove the line below (in <tt>/sys/arch/i386/conf</tt>). It ! is required for X support: <tscreen><verb> options UCONSOLE #X Console support </verb></tscreen> *************** *** 453,472 **** device sc0 at isa? port "IO_KBD" tty irq 1 vector scintr </verb></tscreen> ! The number of virtual consoles can be set using the NCONS option: <tscreen><verb> ! options "NCONS=4" #4 virtual consoles </verb></tscreen> ! Otherwise, the default without a line like this is 12. You must have more VTs than gettys as described in the end of section 3, and 4 is a reasonable minimum. ! The server supports several console drivers: pccons, syscons and pcvt. The syscons driver is the default in FreeBSD 1.1.5 and higher. They are detected at runtime and no configuration of the server itself is required. The XFree86 servers include support for the MIT-SHM extension. The GENERIC kernel does not support this, so if you want to make use of this, you will need a kernel configured with SYSV shared memory --- 538,588 ---- device sc0 at isa? port "IO_KBD" tty irq 1 vector scintr </verb></tscreen> ! The number of virtual consoles can be set using the MAXCONS option: <tscreen><verb> ! options "MAXCONS=4" #4 virtual consoles </verb></tscreen> ! Otherwise, the default without a line like this is 16. You must have more VTs than gettys as described in the end of section 3, and 4 is a reasonable minimum. ! The server supports two console drivers: syscons and pcvt. The syscons driver is the default in FreeBSD 1.1.5 and higher. They are detected at runtime and no configuration of the server itself is required. + If you intend to use pcvt as the console driver, be sure to include the + following option in your kernel configuration file. + + <tscreen><verb> + options XSERVER #Xserver + </verb></tscreen> + + The number of virtual consoles in pcvt can be set using the following + option: + + <tscreen><verb> + options "PCVT_NSCREENS=10" #10 virtual consoles + </verb></tscreen> + + The bus mouse driver and the PS/2 mouse driver may not be included, or + may be included but disabled in your kernel. If you intend to use + these mice, verify the following lines in the kernel configuration file: + + + <tscreen><verb> + device mse0 at isa? port 0x23c tty irq 5 vector mseintr + device psm0 at isa? port "IO_KBD" conflicts tty irq 12 vector psmintr + </verb></tscreen> + + The <tt/mse0/ device is for the bus mouse and the <tt/psm/ device is + for the PS/2 mouse. Your bus mouse interface card may allow you to + change IRQ and the port address. Please refer to the manual of + the bus mouse and the manual page for <tt/mse(4)/ for details. + There is no provision to change IRQ and the port address of the + PS/2 mouse. + The XFree86 servers include support for the MIT-SHM extension. The GENERIC kernel does not support this, so if you want to make use of this, you will need a kernel configured with SYSV shared memory *************** *** 558,570 **** </itemize> <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/FreeBSD.sgml,v 3.25.2.1 1997/05/17 12:03:29 dawes Exp $ ! $TOG: FreeBSD.sgml /main/13 1997/07/19 10:31:27 kaleb $ </verb> </article> --- 674,686 ---- </itemize> <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/FreeBSD.sgml,v 3.25.2.3 1998/02/26 13:59:06 dawes Exp $ ! $TOG: FreeBSD.sgml /main/14 1998/03/06 16:41:01 kaleb $ </verb> </article> *** ./programs/Xserver/hw/xfree86/doc/sgml/Imakefile@@/PUBLIC-LATEST Sun Aug 10 13:03:06 1997 --- xc/programs/Xserver/hw/xfree86/doc/sgml/Imakefile Fri Mar 6 16:39:29 1998 *************** *** 1,9 **** ! XCOMM $TOG: Imakefile /main/18 1997/08/10 13:01:42 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/Imakefile,v 3.25.2.4 1997/07/27 02:41:16 dawes Exp $ #include <Server.tmpl> #include <lnxdoc.rules> --- 1,9 ---- ! XCOMM $TOG: Imakefile /main/19 1998/03/06 16:41:06 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/Imakefile,v 3.25.2.7 1998/02/25 12:20:30 dawes Exp $ #include <Server.tmpl> #include <lnxdoc.rules> *************** *** 73,83 **** --- 73,85 ---- LinuxDocReadmeTarget(SiS) LinuxDocReadmeTarget(W32) LinuxDocReadmeTarget(WstDig) + LinuxDocReadmeTarget(apm) LinuxDocReadmeTarget(ark) LinuxDocReadmeTarget(agx) LinuxDocReadmeTarget(ati) LinuxDocReadmeTarget(chips) LinuxDocReadmeTarget(cirrus) + LinuxDocReadmeTarget(mouse) LinuxDocReadmeTarget(trident) LinuxDocReadmeTarget(tseng) #if BuildAllDocs *************** *** 97,105 **** LinuxDocReadmeTarget(LinkKit) LinuxDocReadmeTarget(clkprog) LinuxDocTarget(xinput) - #if 0 LinuxDocTargetLong(VidModes.sgml,VideoModes.doc,VideoModes) - #endif LinuxDocTargetLong(VGADriv.sgml,VGADriver.Doc,VGADriver) InstallLinkKitNamedNonExec(README.LinkKit,README,$(LINKKITDIR)) --- 99,105 ---- *** ./programs/Xserver/hw/xfree86/doc/sgml/LinkKit.sgml@@/PUBLIC-LATEST Sat Jul 19 10:31:39 1997 --- xc/programs/Xserver/hw/xfree86/doc/sgml/LinkKit.sgml Fri Mar 6 16:39:33 1998 *************** *** 2,17 **** <article> ! <title>Readme for the XFree86 3.3 LinkKit <author>The XFree86 Project, Inc. ! <date>16 May 1997 ! <sect>Readme for the XFree86 3.3 LinkKit <p> <enum> <item>For systems which don't use gcc-2, you may need to install libgcc.a if the binary distribution you are using was built with gcc-2. ! <item>Make sure that you have the XFree86 3.3 libraries installed under <tt>/usr/X11R6</tt> if you will be linking Xnest with the LinkKit. The LinkKit is now self-contained for the other servers. --- 2,17 ---- <article> ! <title>Readme for the XFree86 3.3.2 LinkKit <author>The XFree86 Project, Inc. ! <date>26 February 1998 ! <sect>Readme for the XFree86 3.3.2 LinkKit <p> <enum> <item>For systems which don't use gcc-2, you may need to install libgcc.a if the binary distribution you are using was built with gcc-2. ! <item>Make sure that you have the XFree86 3.3.2 libraries installed under <tt>/usr/X11R6</tt> if you will be linking Xnest with the LinkKit. The LinkKit is now self-contained for the other servers. *************** *** 64,69 **** --- 64,73 ---- set <tt>XF98WSNAServer</tt> to <tt>YES</tt>. <item>To build the Trident Cyber9320/9680 server: set <tt>XF98TGUIServer</tt> to <tt>YES</tt>. + <item>To build the Matrox Millennium/Mystique Server: + set <tt>XF98MGAServer</tt> to <tt>YES</tt>. + <item>To build the Cirrus Logic CLGD7555 Server: + set <tt>XF98SVGAServer</tt> to <tt>YES</tt>. <item>To build the EGC server: set <tt>XF98EGCServer</tt> to <tt>YES</tt>. <item>To build the NEC S3 server: *************** *** 150,162 **** </enum> <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/LinkKit.sgml,v 3.14.2.1 1997/05/17 12:03:29 dawes Exp $ ! $TOG: LinkKit.sgml /main/9 1997/07/19 10:31:42 kaleb $ </verb> </article> --- 154,166 ---- </enum> <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/LinkKit.sgml,v 3.14.2.3 1998/02/26 20:11:26 hohndel Exp $ ! $TOG: LinkKit.sgml /main/10 1998/03/06 16:41:11 kaleb $ </verb> </article> *** ./programs/Xserver/hw/xfree86/doc/sgml/Linux.sgml@@/PUBLIC-LATEST Sat Jul 19 10:31:46 1997 --- xc/programs/Xserver/hw/xfree86/doc/sgml/Linux.sgml Fri Mar 6 16:39:37 1998 *************** *** 4,18 **** <title>Information for Linux Users <author>Orest Zborowski, Dirk Hohndel ! <date>May 13, 1997 <toc> <sect>Linux versions on which XFree86 has been tested <p> ! XFree86 has been tested with Linux version 2.0.30. It should work ! with any version since 1.0 without change. The binaries and libraries are ! based on the 5.4.7 Elf C libraries, and the 1.7.14 dynamic linker ! <tt>ld.so</tt>. You will at least need the 5.2.x Elf C libraries to ! successfully use the servers. <sect>Backwards Compatibility <p> X11R6 is considered a major update from X11R5, so the shared --- 4,21 ---- <title>Information for Linux Users <author>Orest Zborowski, Dirk Hohndel ! <date>February 26, 1997 <toc> <sect>Linux versions on which XFree86 has been tested <p> ! XFree86 has been tested with Linux version 2.0.32 and several 2.1xx kernels. ! It is known not to compile with kernel sources newer then somewhere around ! 2.1.70, due to incompatibilities in the joystick driver. Except for the ! joystick driver, it works just fine with all 2.1.x kernels tested (including ! 2.1.88). It should work with any version since 1.0 without change. The ! binaries and libraries are based on the 5.3.12 Elf C libraries, and the ! 1.7.14 dynamic linker <tt>ld.so</tt>. You will at least need the 5.2.x Elf ! C libraries to successfully use the servers. <sect>Backwards Compatibility <p> X11R6 is considered a major update from X11R5, so the shared *************** *** 141,147 **** <sect>xterm <p> ! The XFree86-3.3 binary release contains an xterm binary that has been linked statically against libtermcap. This was done to make sure that it will correctly work with all distributions, regardless whether they rely on libtermcap or libncurses. Contrary to the xterm binaries in some beta version --- 144,150 ---- <sect>xterm <p> ! The XFree86-3.3.2 binary release contains an xterm binary that has been linked statically against libtermcap. This was done to make sure that it will correctly work with all distributions, regardless whether they rely on libtermcap or libncurses. Contrary to the xterm binaries in some beta version *************** *** 190,196 **** <sect> Compiling XFree86 <p> There are no special instructions required for compiling XFree86. ! This version was compiled with gcc-2.7.2.1, the 5.4.7 Elf libraries and the 1.7.14 shared, dynamic linker ld.so. The server has been compiled with <tt>-m486</tt>, which optimizes it for the 486 processor, but --- 193,199 ---- <sect> Compiling XFree86 <p> There are no special instructions required for compiling XFree86. ! This version was compiled with gcc-2.7.2.1, the 5.3.12 Elf libraries and the 1.7.14 shared, dynamic linker ld.so. The server has been compiled with <tt>-m486</tt>, which optimizes it for the 486 processor, but *************** *** 204,219 **** <tt>site.def</tt>, extra extensions can be compiled into the server. Alternately, the link kit can be used to craft modified servers. - The distribution is very large, but it is possible to compile - XFree86 on a single 64mb partition, if the source tree is carefully trimmed - (no manpages, PEX or large clients). Simply run ``<tt>make Makefiles</tt>'' to - create - the Makefiles, then stop the make and run each piece individually. It is - not necessary to run ``<tt>make depend</tt>'' as well, which saves some - space. Having - 150mb available makes compiling XFree86 a lot easier. You will need about - 10mb of virtual memory to compile the entire server. - If an aout version of XFree86 is to be built and patches are applied which significantly change the libraries, modified jump_xxx files will be needed. Those can be generated according to --- 207,212 ---- *************** *** 230,242 **** to the <it>comp.windows.x.i386unix</it> newsgroup. <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/Linux.sgml,v 3.13.2.3 1997/05/23 12:19:40 dawes Exp $ ! $TOG: Linux.sgml /main/7 1997/07/19 10:31:48 kaleb $ </verb> </article> --- 223,235 ---- to the <it>comp.windows.x.i386unix</it> newsgroup. <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/Linux.sgml,v 3.13.2.4 1998/02/26 20:11:26 hohndel Exp $ ! $TOG: Linux.sgml /main/8 1998/03/06 16:41:15 kaleb $ </verb> </article> *** ./programs/Xserver/hw/xfree86/doc/sgml/LynxOS.sgml@@/PUBLIC-LATEST Sat Jul 19 10:31:53 1997 --- xc/programs/Xserver/hw/xfree86/doc/sgml/LynxOS.sgml Fri Mar 6 16:39:41 1998 *************** *** 2,10 **** <article> ! <title>README for XFree86 3.3 on LynxOS <author>Thomas Mueller ! <date>Last modified on: 26 May 1997 <toc> <sect>What and Where is XFree86?<p> --- 2,10 ---- <article> ! <title>README for XFree86 3.3.2 on LynxOS <author>Thomas Mueller ! <date>Last modified on: 24 February 1998 <toc> <sect>What and Where is XFree86?<p> *************** *** 23,29 **** <htmlurl name="ftp://ftp.XFree86.org/pub/XFree86/current" url="ftp://ftp.XFree86.org/pub/XFree86/current"> ! Binaries of the 3.3 release for LynxOS AT are available from: <htmlurl name="ftp://ftp.XFree86.org/pub/XFree86/current/binaries/LynxOS" url="ftp://ftp.XFree86.org/pub/XFree86/current/binaries/LynxOS"> --- 23,29 ---- <htmlurl name="ftp://ftp.XFree86.org/pub/XFree86/current" url="ftp://ftp.XFree86.org/pub/XFree86/current"> ! Binaries of the 3.3.2 release for LynxOS AT are available from: <htmlurl name="ftp://ftp.XFree86.org/pub/XFree86/current/binaries/LynxOS" url="ftp://ftp.XFree86.org/pub/XFree86/current/binaries/LynxOS"> *************** *** 31,37 **** The binaries are built on `LynxOS 2.5.0 012797-G i386'. These binaries don't run on earlier LynxOS versions because of the changes made to the networking code in LynxOS 2.5.0. This XFree86 version has never ! been tested on LynxOS versions earlier than 2.3.0. XFree86 supports LynxOS on the AT, on the microSPARC and on the PowerPC platform. X servers are currently available on --- 31,37 ---- The binaries are built on `LynxOS 2.5.0 012797-G i386'. These binaries don't run on earlier LynxOS versions because of the changes made to the networking code in LynxOS 2.5.0. This XFree86 version has never ! been tested on LynxOS versions earlier than 2.4.0. XFree86 supports LynxOS on the AT, on the microSPARC and on the PowerPC platform. X servers are currently available on *************** *** 40,49 **** on the non-AT platforms. If you need binaries for other platforms than the one on the ! XFree86 FTP server contact me (<htmlurl name="tm@systrix.de" ! url="mailto:tm@systrix.de">). ! Send email to <it>tm@systrix.de</it> (Thomas Mueller) or <it>XFree86@XFree86.org</it> if you have comments or suggestions about this file and we'll revise it. --- 40,49 ---- on the non-AT platforms. If you need binaries for other platforms than the one on the ! XFree86 FTP server contact me (<htmlurl name="tmueller@sysgo.de" ! url="mailto:tmueller@sysgo.de">). ! Send email to <it>tmueller@sysgo.de</it> (Thomas Mueller) or <it>XFree86@XFree86.org</it> if you have comments or suggestions about this file and we'll revise it. *************** *** 54,60 **** man pages, config files, and the server link kit. The full distribution takes over 95MB of disk space. ! At minimum you need to unpack the 'required' <tt/X33*.tgz/ archives plus at least one server that matches your vga card. If you will be using the new <tt/XF86Setup/ utility you will also need the VGA16 server. You'll need about 40Mb for the minimum required run-time --- 54,60 ---- man pages, config files, and the server link kit. The full distribution takes over 95MB of disk space. ! At minimum you need to unpack the 'required' <tt/X332*.tgz/ archives plus at least one server that matches your vga card. If you will be using the new <tt/XF86Setup/ utility you will also need the VGA16 server. You'll need about 40Mb for the minimum required run-time *************** *** 63,122 **** <descrip> <tag/REQUIRED:/ <descrip> ! <tag/X33bin/ Clients, run-time libs, and app-defaults files ! <tag/X33doc/ Documentation ! <tag/X33fnts/ 75dpi and misc fonts ! <tag/X33lib/ Data files required at run-time ! <tag/X33cfg/ sample config files for xinit, xdm ! <tag/X33set/ XF86Setup utility ! <tag/X33VG16/ 16 colour VGA server (XF86Setup needs this server) </descrip> Choose at least one of the following server to match your hardware: <descrip> ! <tag/X338514/ 8514/A server ! <tag/X33AGX/ AGX server ! <tag/X33I128/ I128 server ! <tag/X33Ma64/ Mach 64 server ! <tag/X33Ma32/ Mach 32 server ! <tag/X33Ma8/ Mach 8 server ! <tag/X33Mono/ Monochrome server ! <tag/X33P9K/ P9000 server ! <tag/X33S3/ S3 server ! <tag/X33S3V/ S3 ViRGE server ! <tag/X33SVGA/ SVGA server ! <tag/X33VG16/ 16 colour VGA server ! <tag/X33W32/ ET4000W32, ET6000 server </descrip> <tag/OPTIONAL:/ <descrip> ! <tag/X33f100/ 100dpi fonts ! <tag/X33fcyr/ Cyrillic fonts ! <tag/X33fnon/ Other fonts (Chinese, Japanese, Korean, Hebrew) ! <tag/X33fscl/ Scalable fonts (Speedo and Type1) ! <tag/X33fsrv/ Font server and config files ! <tag/X33prog/ X header files, config files and compile-time libs ! <tag/X33man/ Manual pages ! <tag/X33nest/ Nested X server ! <tag/X33prt/ X Print server ! <tag/X33vfb/ Virtual frame buffer X server ! <tag/X33lkit/ The server LinkKit ! <tag/X33ps/ PostScript version of the documentation ! <tag/X33html/ HTML version of the documentation </descrip> </descrip> If this is your first time, then you can safely install all of the packages. As a minimal install, you'll need doc, bin, fonts lib, ! config, and one X server. If you plan to install XF86Setup you'll have to install ! <tt/X33prog/ as well since XF86Setup checks for the existence of a certain file name pattern which is satisfied only if you install ! the library files from <tt/X33prog/. This restriction will be fixed in future XFree86 releases for LynxOS. It may be necessary to increase the process stack limit in order to --- 63,146 ---- <descrip> <tag/REQUIRED:/ <descrip> ! <tag/preinst.sh/ Pre-installation script ! <tag/postinst.sh/ Post-installation script ! <tag/extract/ XFree86 extraction utility ! <tag/X332bin/ Clients, run-time libs, and app-defaults files ! <tag/X332doc/ Documentation ! <tag/X332cfg/ sample config files for xinit, xdm ! <tag/X332fnts/ 75dpi and misc fonts ! <tag/X332lib/ Data files required at run-time ! <tag/X332set/ XF86Setup utility ! <tag/X332VG16/ 16 colour VGA server (XF86Setup needs this server) </descrip> + The following are required for an upgrade from XFree86 3.3.1: + + <descrip> + <tag/UPDATE from 3.3.1:/ + <descrip> + <tag/preinst.sh/ Pre-installation script + <tag/postinst.sh/ Post-installation script + <tag/extract/ XFree86 extraction utility + <tag/X332upd.tgz/ Changes since 3.3.1 (except the servers) + <tag/X332doc.tgz/ Documentation + <tag/X332set.tgz/ XF86Setup utility + <tag/X332VG16.tgz/ 16 colour VGA server (XF86Setup needs this server) + </descrip> + Choose at least one of the following server to match your hardware: <descrip> ! <tag/X3328514/ 8514/A server ! <tag/X332AGX/ AGX server ! <tag/X332I128/ I128 server ! <tag/X332Ma64/ Mach 64 server ! <tag/X332Ma32/ Mach 32 server ! <tag/X332Ma8/ Mach 8 server ! <tag/X332Mono/ Monochrome server ! <tag/X332P9K/ P9000 server ! <tag/X332S3/ S3 server ! <tag/X332S3V/ old S3 ViRGE server (please use SVGA server) ! <tag/X332SVGA/ SVGA server ! <tag/X332VG16/ 16 colour VGA server (XF86Setup needs this server) ! <tag/X332W32/ ET4000W32, ET6000 server </descrip> <tag/OPTIONAL:/ <descrip> ! <tag/X332f100/ 100dpi fonts ! <tag/X332fcyr/ Cyrillic fonts ! <tag/X332fnon/ Other fonts (Chinese, Japanese, Korean, Hebrew) ! <tag/X332fscl/ Scalable fonts (Speedo and Type1) ! <tag/X332fsrv/ Font server and config files ! <tag/X332prog/ X header files, config files and compile-time libs ! <tag/X332man/ Manual pages ! <tag/X332nest/ Nested X server ! <tag/X332prt/ X Print server ! <tag/X332vfb/ Virtual frame buffer X server ! <tag/X332lkit/ The X server LinkKit ! <tag/X332ps/ PostScript version of the documentation ! <tag/X332html/ HTML version of the documentation ! <tag/X332jdoc/ Documentation in Japanese ! <tag/X332jhtm/ HTML version of the documentation in Japanese </descrip> </descrip> If this is your first time, then you can safely install all of the packages. As a minimal install, you'll need doc, bin, fonts lib, ! config, and one X server. If you already have a version of XFree86 ! installed, <bf>MAKE A BACKUP OF</bf> <tt>/usr/X11R6</tt> ! <bf>BEFORE DOING ANYTHING ELSE</bf>. The standard installation ! procedure will overwrite your existing version of XFree86. ! Also, be sure to read the Release Notes <htmlurl url="RELNOTES.html" ! name="Release Notes"> before installing. If you plan to install XF86Setup you'll have to install ! <tt/X332prog/ as well since XF86Setup checks for the existence of a certain file name pattern which is satisfied only if you install ! the library files from <tt/X332prog/. This restriction will be fixed in future XFree86 releases for LynxOS. It may be necessary to increase the process stack limit in order to *************** *** 133,138 **** --- 157,167 ---- several executables are set-user-id. Otherwise the server may abort if you unpack it as an ordinary user. + For the purposes of these installation instructions, it is assumed that + you have downloaded all the files to the <tt>/usr/tmp</tt> directory. + If you've put them in another directory, that's fine -- just replace + all occurrences of ``<tt>/usr/tmp</tt>'' with the name of that directory. + <item>If you have about 80Mb free in the <tt>/usr</tt> partition create a directory <tt>/usr/X11R6</tt> and skip to no. 3. Otherwise, create a directory on another partition and sym link it into *************** *** 146,157 **** <item>Unpack everything: If you are using bash: <tscreen><verb> # cd /usr/X11R6 ! # for i in X33*.tgz; do ! # gnutar -xzpPf $i # done </verb></tscreen> --- 175,208 ---- <item>Unpack everything: + Make the installation utility executable. To do this, + make sure the `extract' file is in the same directory as all the X332*.tgz + files, and run the following from that directory: + <tscreen><verb> + chmod 755 /usr/tmp/extract + </verb></tscreen> + + The installation utility ``extract'' is used to unpack the .tgz files + that make up the XFree86 distribution. The .tgz files are gzipped + tar files. However, ``tar'' in its standard form on most OSs is not + well-suited to the task of installing XFree86. The extract utility is + a modified version of GNU tar 1.12 built with the options required to + make it suitable for installing XFree86. The source for extract is + available from the same place you got the XFree86 distribution. + + It is strongly recommended that you use the provided extract utility to + unpack the XFree86 distribution. If you choose to ignore this and use + something else, we don't want to hear from you if you run into problems. + It is also important that you do not rename the extract utility. If + renamed, it behaves just like the normal GNU tar. + + To extract the XFree86 binaries, run the following as <bf>root</bf>: If you are using bash: <tscreen><verb> # cd /usr/X11R6 ! # for i in /usr/tmp/X332*.tgz; do ! # extract $i # done </verb></tscreen> *************** *** 158,165 **** Else, if you are using csh: <tscreen><verb> % cd /usr/X11R6 ! % foreach i (X33*.tgz) ! % gnutar -xzpPf $i % end </verb></tscreen> --- 209,216 ---- Else, if you are using csh: <tscreen><verb> % cd /usr/X11R6 ! % foreach i (/usr/tmp/X332*.tgz) ! % /usr/tmp/extract $i % end </verb></tscreen> *************** *** 179,186 **** <tscreen><verb> # cd /usr/X11R6 ! # for i in bin fnts lib xicf; do ! # gnutar -xzpPf X33$i.tgz # done </verb></tscreen> --- 230,237 ---- <tscreen><verb> # cd /usr/X11R6 ! # for i in bin fnts lib cfg prog; do ! # /usr/tmp/extract /usr/tmp/X332$i.tgz # done </verb></tscreen> *************** *** 190,196 **** based card you will use the XF86_SVGA server: <tscreen><verb> ! # gnutar -xzpPf X33SVGA.tgz # cd /usr/X11R6/bin; rm -f X; ln -s XF86_SVGA X </verb></tscreen> --- 241,247 ---- based card you will use the XF86_SVGA server: <tscreen><verb> ! # /usr/tmp/extract /usr/tmp/X332SVGA.tgz # cd /usr/X11R6/bin; rm -f X; ln -s XF86_SVGA X </verb></tscreen> *************** *** 267,276 **** </verb></tscreen> </itemize> ! <tag>LynxOS AT 2.3 and 2.4</tag> <itemize> ! <item>Use the CYGNUS GNU-C Compiler to build XFree86. With LynxOS 2.3.0 ! and 2.4.0 you must execute the shell script <tt>/CYGNUS.bash</tt> to apply the necessary changes to your environment. <item>Create a shell script named <tt>/lib/cpp</tt> as follows: <tscreen><verb> --- 318,327 ---- </verb></tscreen> </itemize> ! <tag>LynxOS AT 2.4</tag> <itemize> ! <item>Use the CYGNUS GNU-C Compiler to build XFree86. With LynxOS ! 2.4.0 you must execute the shell script <tt>/CYGNUS.bash</tt> to apply the necessary changes to your environment. <item>Create a shell script named <tt>/lib/cpp</tt> as follows: <tscreen><verb> *************** *** 289,294 **** --- 340,348 ---- # chmod 755 /lib/cpp </verb></tscreen> </itemize> + <tag>LynxOS AT 2.3</tag> + This has actually not been tested, but the steps for described + for 2.4 should apply to 2.3 as well. <tag>LynxOS AT 2.2.1</tag> This has actually never been tested, be prepared that the build will fail somewhere! *************** *** 337,342 **** --- 391,399 ---- <sect1> make World<p> + Read <htmlurl url="BUILD.html" name="Building XFree86"> before + trying to rebuild XFree86 from the source distribution. + Before you start compilation you must edit <tt>xc/config/cf/lynx.cf</tt> to match your operating system version (defaults set up for 2.5.0). Change the definitions of OSMajorVersion, OSMinorVersion and OSTeenyVersion *************** *** 377,385 **** <sect>Running XFree86<p><label id="running"> <sect1>System requirements<p> ! A minimum of 8MB of memory is required to run X. If you want to run ! real-world applications you should think of upgrading to 16MB. If ! you plan to develop software under X take 32MB into consideration. <sect1>System tuning<p> <sect2>Tunable parameters<p> --- 434,441 ---- <sect>Running XFree86<p><label id="running"> <sect1>System requirements<p> ! A minimum of 16MB of memory is required to run X. If you want to run ! real-world applications you should think of upgrading to 32MB (or more). <sect1>System tuning<p> <sect2>Tunable parameters<p> *************** *** 424,429 **** --- 480,493 ---- # reboot -N </verb></tscreen> + <sect1>Mouse support in 3.3.2<p> + + XFree86 3.3.2 includes support for PnP mice (see also + <htmlurl url="mouse.html" name="Mouse Support in XFree86">). The + current LynxOS TTY device driver doesn't allow the necessary + manipulation of the RTS line and therefore the support for + PnP mice has been disabled for LynxOS. + <sect1>Bus mouse drivers<p> Starting with LynxOS AT 2.4.0 LynxOS includes a PS/2 mouse driver. *************** *** 661,672 **** <tt>lynx.cf</tt> but it has never been tested (reports are welcome). <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/LynxOS.sgml,v 3.14.2.2 1997/05/26 14:36:18 dawes Exp $ ! $TOG: LynxOS.sgml /main/11 1997/07/19 10:31:56 kaleb $ </verb> </article> --- 725,736 ---- <tt>lynx.cf</tt> but it has never been tested (reports are welcome). <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/LynxOS.sgml,v 3.14.2.5 1998/02/26 13:59:06 dawes Exp $ ! $TOG: LynxOS.sgml /main/12 1998/03/06 16:41:19 kaleb $ </verb> </article> *** ./programs/Xserver/hw/xfree86/doc/sgml/MGA.sgml@@/PUBLIC-LATEST Sun Aug 10 13:03:11 1997 --- xc/programs/Xserver/hw/xfree86/doc/sgml/MGA.sgml Fri Mar 6 16:39:46 1998 *************** *** 3,38 **** <article> <title>Information for Matrox Millennium/Mystique Users <author>The XFree86 Project Inc. ! <date>2 August 1997 <toc> <sect>Supported hardware <p> ! The current MGA driver in the SVGA server supports the Matrox Millennium (MGA2064W) with Ti3026 RAMDAC. It has been tested with 175, 220MHz, and ! 250MHz cards with 2MB, 4MB and 8MB WRAM. It supports the Matrox Mystique ! with 170 and 220 MHz RAMDACs. - There is experimental support for the Matrox - Millennium II, which for the most part works, but DO NOT USE THIS ON PRODUCTION - SYSTEMS - it is no where near tested enough for that role. We do not yet have - the card's documentation, so this is a alpha quality addition - test this support - at your own risk. - - This version of the server does not support the rev 3 Matrox Millennium I. - - NOTE: This driver is pretty new, and not everything works like you expect - it to. It shouldn't crash your machine, but you may have video artifacts - or missing lines. Please report any and all problems to - <htmlurl name="XFree86@Xfree86.org" url="mailto:XFree86@Xfree86.org"> - using the appropriate bug report sheet. - <sect>Features: <p> <itemize> - <item>Basic support for the Matrox Millennium video adapter - - <itemize> <item>uses linear frame buffer <item>it should be possible to reach resolutions up to 1920x1024 <item>it should be possible to use pixel depths of 8, 16, 24, and 32 bits --- 3,27 ---- <article> <title>Information for Matrox Millennium/Mystique Users <author>The XFree86 Project Inc. ! <date>21 February 1998 <toc> <sect>Supported hardware <p> ! The current MGA driver in the SVGA server supports ! <p> ! <itemize> ! <item>Matrox Millennium (MGA2064W) with Ti3026 RAMDAC. It has been tested with 175, 220MHz, and ! 250MHz cards with 2MB, 4MB and 8MB WRAM. ! <item>Millennium II both PCI and AGP. It has been tested with up to 16MB RAM. ! <item>Matrox Mystique ! with 170 and 220 MHz RAMDACs. Both 1064SG and 1164SG should work. ! </itemize> <sect>Features: <p> <itemize> <item>uses linear frame buffer <item>it should be possible to reach resolutions up to 1920x1024 <item>it should be possible to use pixel depths of 8, 16, 24, and 32 bits *************** *** 41,103 **** <item>supports VESA Display Power Management Signaling (DPMS) <item>supports RGB Sync-on-Green <item>supports DGA ! <item>has the following accelerations: ! <itemize> ! <item>lines ! <item>most bitblts ! <item>filled rectangles ! <item>cached pixmaps ! <item>many more... </itemize> ! The Millennium server is fairly well accelerated, and is one of the fastest ! XFree86 3.3.1 Xservers. Future work will concentrate on fixing remaining bugs. - </itemize> - <item>Basic support for the Matrox Mystique video adapter - <itemize> - <item>uses linear frame buffer - <item>it should be possible to reach resolutions up to 1280x1024 - <item>it should be possible to use pixel depths of 8, 16, 24, and 32 bits - per pixel (256 pseudo colour, "high colour", "packed true colour", - "true colour"). - <item>supports VESA Display Power Management Signaling (DPMS) - <item>has the following accelerations (may be with some bugs): - <itemize> - <item>lines - <item>most bitblts - <item>filled rectangles - <item>cached pixmaps - <item>NOTE: If acceleration do not work properly, you had rather to insert: - Option "noaccel" - line in the Device section of XF86Config file. It will be slower but will work better. - </itemize> - </itemize> - </itemize> - - <itemize>Experimental Support for the Matrox Millennium II - <item>Provided ONLY as a test and to provide early access to Mill II owners - <item>Works as if it is a Millennium I - <item>We don't have the card's tech docs yet, so no specific Mill II speedups - <item>Has plenty of bugs: - <itemize> - <item>May corrupt your text font when you exit X - <item>May not work correctly at 24 bpp - <item>Lots more where that came from... :-) - </itemize> - </itemize> - - - <sect>Future Features (in order from highest to lowest priority) - <p> - - <itemize> - <item>more hardware acceleration (more primitive operations, etc) - <item>hw cursor for Mystique board - <item>more chipsets and RAMDACs - <item>3D acceleration using Mesa - </itemize> - <sect>Technical Note: <p> --- 30,41 ---- <item>supports VESA Display Power Management Signaling (DPMS) <item>supports RGB Sync-on-Green <item>supports DGA ! <item>full accelerations: </itemize> ! This server is very well accelerated, and is one of the fastest ! XFree86 3.3.2 Xservers. Future work will concentrate on fixing remaining bugs. <sect>Technical Note: <p> *************** *** 109,121 **** <item>the MGA Storm (MGA1064SG) chipset with integrated 170 and 220 MHz RAMDAC ! <item>the MGA Storm (MGA2164W) chipset with the TI TVP 3026 RAMDAC. This is experimental ! <item>We will eventually provide support for the other Matrox chipsets (once the ! Millennium driver is at a far enough stage and more people with other cards ! join the effort), including the Impression, Atlas, Genesis etc. ! At the moment, however, only the Millennium and Mystique are supported. </itemize> <sect>Configuration: --- 47,60 ---- <item>the MGA Storm (MGA1064SG) chipset with integrated 170 and 220 MHz RAMDAC ! <item>the MGA Storm (MGA1164SG) chipset with integrated 170 and 220 MHz RAMDAC ! <item>the MGA Storm (MGA2164W) chipset with the TI TVP 3026 RAMDAC. ! <item>We are still interested to provide support for the other Matrox chipsets ! including the Impression, Atlas, Genesis etc. but at this time have not been ! able to obtain the docs for them. ! </itemize> <sect>Configuration: *************** *** 138,143 **** --- 77,86 ---- <item>the driver doesn't support some values of HTotal parameter in Modelines in the XF86Config file. If you get flickering vertical stripes on the screen, try to change this parameter +/- 8. + <item>On some Millennium II cards the driver shows severe distortions with + 24bpp in modes above about 1024x768. We hope to have automated the detection + and fix of this problem. If it still occurs, please use Option "mga_24bpp_fix" + in the Device Section to get a stable picture. </itemize> <sect>Authors *************** *** 145,150 **** --- 88,95 ---- Radoslaw Kapitan, <it>kapitan@student.uci.agh.edu.pl</it> + Mark Vojkovich, <it>mvojkovi@sdcc10.ucsd.edu</it> + and: <itemize> *************** *** 155,172 **** <item>Stephen Pitts, <it>pitts2@memphisonline.com</it> <item>Dirk Hohndel, <it>hohndel@XFree86.Org</it> <item>Leonard N. Zubkoff, <it>lnz@dandelion.com</it> - <item>Mark Vojkovich, <it>mvojkovi@sdcc10.ucsd.edu</it> <item>Harm Hanemaayer, <it>H.Hanemaayer@inter.nl.net</it> <item>Guy Desbief, <it>g.desbief@aix.pacwan.net</it> </itemize> - Visit the <url name = "Matrox Millennium XServer for XFree86 Home Page" - url="http://www.bf.rmit.edu.au/~ajv/xf86-matrox.html"> - to keep up to date with the latest news, new sources, etc. - - <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/MGA.sgml,v 3.4.2.5 1997/08/02 13:48:14 dawes Exp $ </verb> </article> --- 100,112 ---- <item>Stephen Pitts, <it>pitts2@memphisonline.com</it> <item>Dirk Hohndel, <it>hohndel@XFree86.Org</it> <item>Leonard N. Zubkoff, <it>lnz@dandelion.com</it> <item>Harm Hanemaayer, <it>H.Hanemaayer@inter.nl.net</it> <item>Guy Desbief, <it>g.desbief@aix.pacwan.net</it> + <item>Takaaki Nomura, <it>tnomura@sfc.keio.ac.jp</it> </itemize> <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/MGA.sgml,v 3.4.2.8 1998/02/26 20:11:26 hohndel Exp $ </verb> </article> *** ./programs/Xserver/hw/xfree86/doc/sgml/Mach64.sgml@@/PUBLIC-LATEST Sat Jul 19 10:32:22 1997 --- xc/programs/Xserver/hw/xfree86/doc/sgml/Mach64.sgml Fri Mar 6 16:39:50 1998 *************** *** 5,11 **** <title>Mach64 X Server Release Notes <author>Kevin E. Martin (martin@cs.unc.edu) ! <date>23 January 1997 <!-- Table of contents --> <toc> --- 5,11 ---- <title>Mach64 X Server Release Notes <author>Kevin E. Martin (martin@cs.unc.edu) ! <date>25 February 1998 <!-- Table of contents --> <toc> *************** *** 44,53 **** AT&T20C408 80MHz 16 1024x768 2Mb AT&T20C408 40MHz 32 800x600 2Mb ! 3D Rage II (Int) 170MHz 8 1600x1200 4Mb ! 3D Rage II (Int) 170MHz 16 1600x1200 4Mb ! 3D Rage II (Int) 135MHz 32 1024x768 4Mb Internal 135MHz 8 1280x1024 2Mb Internal 80MHz 16 1024x768 2Mb Internal 40MHz 32 800x600 2Mb --- 44,61 ---- AT&T20C408 80MHz 16 1024x768 2Mb AT&T20C408 40MHz 32 800x600 2Mb ! 3D Rage II 170MHz 8 1600x1200 4Mb ! 3D Rage II 170MHz 16 1600x1200 4Mb ! 3D Rage II 170MHz 32 1024x768 4Mb + 3D Rage II+DVD 200MHz 8 1600x1200 4Mb + 3D Rage II+DVD 200MHz 16 1600x1200 4Mb + 3D Rage II+DVD 200MHz 32 1024x768 4Mb + + Rage Pro 230MHz 8 1600x1200 8Mb + Rage Pro 230MHz 16 1600x1200 8Mb + Rage Pro 230MHz 32 1600x1200 8Mb + Internal 135MHz 8 1280x1024 2Mb Internal 80MHz 16 1024x768 2Mb Internal 40MHz 32 800x600 2Mb *************** *** 82,89 **** ATI WinTurbo cards. The IBM RGB514 RAMDAC is found on the ATI Graphics Pro Turbo 1600 card. The other RAMDACs are usually found on ATI Graphics Xpression, ATI Video Xpression and ATI 3d Xpression ! cards. Mach64 CT, ET, VT, GT (3D Rage) and 3D Rage II chips have an ! "Internal" RAMDAC (i.e., it is built into the Mach64 chip). As advertised, Mach64 graphics cards can use a special 24bpp mode (packed pixel mode), but this is not currently supported in the --- 90,98 ---- ATI WinTurbo cards. The IBM RGB514 RAMDAC is found on the ATI Graphics Pro Turbo 1600 card. The other RAMDACs are usually found on ATI Graphics Xpression, ATI Video Xpression and ATI 3d Xpression ! cards. Mach64 CT, ET, VT, GT (3D Rage), 3D Rage II, 3D Rage II+DVD ! and Rage Pro chips have an "Internal" RAMDAC (i.e., it is built into ! the Mach64 chip). As advertised, Mach64 graphics cards can use a special 24bpp mode (packed pixel mode), but this is not currently supported in the *************** *** 95,105 **** card or a VLB based Mach64 card, then the Mach64 X server will work with any amount of main memory. ! Accelerated doublescan modes are supported on VT, GT and 3D Rage II ! based Mach64 cards. Mach64 cards with other chips cannot handle ! accelerated double scan modes due to a hardware limitation. ! Non-accelerated doublescan modes should work with the ATI driver in ! the SVGA X server for all Mach64 cards. <sect>Optimizing the speed of the Mach64 X server<p> To maximize the speed of the Mach64 X server, I suggest that you use --- 104,114 ---- card or a VLB based Mach64 card, then the Mach64 X server will work with any amount of main memory. ! Accelerated doublescan modes are supported on VT, GT, 3D Rage II, 3D ! Rage II+DVD and Rage Pro based Mach64 cards. Mach64 cards with other ! chips cannot handle accelerated double scan modes due to a hardware ! limitation. Non-accelerated doublescan modes should work with the ATI ! driver in the SVGA X server for all Mach64 cards. <sect>Optimizing the speed of the Mach64 X server<p> To maximize the speed of the Mach64 X server, I suggest that you use *************** *** 153,159 **** programming with the "no_program_clocks" option. In this case, the Mach64 X server reads the Clocks from the BIOS. The "Clocks" lines in the XF86Config file are normally ignored by the Mach64 X server unless ! the "no_bios_clocks" option is given. <descrip> <tag>Option &dquot;sw_cursor&dquot;</tag> --- 162,171 ---- programming with the "no_program_clocks" option. In this case, the Mach64 X server reads the Clocks from the BIOS. The "Clocks" lines in the XF86Config file are normally ignored by the Mach64 X server unless ! the "no_bios_clocks" option is given. Note on newer Mach64 cards (CT, ! ET, VT, GT, 3D Rage II, 3D Rage II+DVD and Rage Pro) the "Ramdac", ! "ClockChip" and "Clocks" lines have no meaning and should not be ! included in your XF86Config file. <descrip> <tag>Option &dquot;sw_cursor&dquot;</tag> *************** *** 267,274 **** --- 279,333 ---- <item>stg1703 <item>tlc34075 </itemize> + <tag>DacSpeed &dquot;<it>MHz</it>&dquot;</tag> + This entry allows you to override the default maximum + dot clock. Use this option with extreme caution. If + you specify a <it>MHz</it> value too large for your + card, you can damage it. </descrip> + <sect>Enhancements for this release<p> + With this release, the following enhancements have been made: + <itemize> + <item>Proper identification of all current Mach64 chips + <item>Support for 16MB boards + <item>Increased max DAC speed settings for newer chips + <item>Support for RagePro cards (including AGP cards) + <item>Block write mode for RagePro based cards + <item>1600x1200, 1600x1280 and other high resolution mode support for + VT and newer chips + <item>Use of the auxiliary register aperture on chips that support + it + <item>Use of 16MB memory aperture on PCI Mach64s with integrated + controllers + </itemize> + + <sect>Cards known to work with this release<p> + The following is a list of cards that have been tested with this + release. Many other cards should work including All-In-Wonder and + All-In-Wonder Pro cards as well as motherboards with Mach64, 3D Rage + II and Rage Pro included on them. If you have a new card that does + not appear to work, see the Known Problems and Bug Reports section + below. + + <verb> + ATI Xpert@Play 8MB 3D Rage Pro (PCI, rev 92) + ATI Xpert@Work 2MB 3D Rage Pro (PCI, rev 92) + ATI Pro Turbo+PC2TV 4MB 3D Rage II+DVD (rev 154) + ATI 3D Xpression+ 4MB 3D Rage II (GT-B, SGRAM, rev 65) + ATI 3D Xpression+ 2MB 3D Rage II (GT-B, SDRAM, rev 65) + ATI 3D Xpression 2MB 3D Rage (GT-A, rev 72) + ATI Video Xpression+ 2MB Mach64 VT-A3 (rev 8) + ATI Video Xpression 2MB Mach64 VT-A4 (rev 72) + ATI Graphics Xpression 2MB Mach64 CT (rev 9) + ATI Graphics Xpression 2MB Mach64 CT-C (rev 65) + ATI Graphics Xpression 2MB Mach64 CT-D (rev 10) + ATI Graphics Xpression 2MB Mach64 GX (rev 1) with Chrontel8398 RAMDAC + ATI Graphics Pro Turbo 2MB Mach64 GX (rev 0) with 68860-B RAMDAC + ATI Graphics Pro Turbo 2MB Mach64 CX (rev 1) with AT&T20C408 RAMDAC + ATI WinTurbo 2MB Mach64 GX (rev 1) with 68860-C RAMDAC + </verb> + <sect>Known Problems and Bug Reports<p> There are several known problems with the current version of the Mach64 X server. They include: *************** *** 279,287 **** is displayed. The hardware cursor works fine in all other modes. <item>Text may not be displayed correctly in certain programs. ! <item>Some RAMDACs are incorrectly reported by the BIOS. This can be ! handled by explicitly specifying the RAMDAC in the XF86Config ! file. This should no longer be a problem. <item>ISA cards with more than 12Mb of main memory cannot use the server due to the requirement of a video memory aperture. This a major project. --- 338,347 ---- is displayed. The hardware cursor works fine in all other modes. <item>Text may not be displayed correctly in certain programs. ! <item>With high refresh rates on certain cards (VT-A3 and CT-D) noise ! can become a problem in 32bpp mode. This usually only happens ! with refresh rates of 85Hz or greater and can be fixed by using ! a lower refresh rate (e.g., 72Hz or 75Hz). <item>ISA cards with more than 12Mb of main memory cannot use the server due to the requirement of a video memory aperture. This a major project. *************** *** 298,303 **** --- 358,365 ---- other documentation available with the release). Third, make sure you do not have any Ramdac, ClockChip or Clocks lines in your XF86Config file (all of these are automatically detected by the Mach64 X server). + The "Device" section should only contain the Identifier, VendorName + and BoardName. All other options should be automatically detected. If you are still experiencing problems, please send e-mail to XFree86@XFree86.org or post to the comp.windows.x.i386unix newsgroup. *************** *** 310,322 **** <p> <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/Mach64.sgml,v 3.15 1997/01/25 03:21:59 dawes Exp $ ! $TOG: Mach64.sgml /main/9 1997/07/19 10:32:23 kaleb $ </verb> </article> --- 372,384 ---- <p> <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/Mach64.sgml,v 3.15.2.2 1998/02/26 23:32:28 dawes Exp $ ! $TOG: Mach64.sgml /main/10 1998/03/06 16:41:28 kaleb $ </verb> </article> *** ./programs/Xserver/hw/xfree86/doc/sgml/NV1.sgml@@/PUBLIC-LATEST Sat Jul 19 10:32:27 1997 --- xc/programs/Xserver/hw/xfree86/doc/sgml/NV1.sgml Fri Mar 6 16:39:54 1998 *************** *** 3,25 **** <article> <!-- Title information --> ! <title>Information for NVidia NV1 / SGS-Thomson STG2000 Users ! <author>David McKay ! <date>23 October 1996 <!-- Table of contents --> <toc> ! <sect>XFree driver for NVidia NV1 / SGS-Thomson STG2000 v1.0 <p> ! This is the first release of a driver for the above chips. This driver ! has very basic functionality, and does not use the accelerated features of ! the chip. <sect1>Notes <p> <itemize> ! <item>THE DRIVER DOES NOT SUPPORT THE VIRTUAL DESKTOP FEATURES OF XFREE86 This is because the NV1 does not have the necessary hardware to support this feature. If you want to change resolutions, you will have --- 3,25 ---- <article> <!-- Title information --> ! <title>Information for NVidia NV1 / SGS-Thomson STG2000 and Riva128 Users ! <author>David McKay, Dirk Hohndel ! <date>26 February 1998 <!-- Table of contents --> <toc> ! <sect>XFree86 driver for NVidia NV1 / SGS-Thomson STG2000 and Riva128 <p> ! This driver supports good acceleration for both the NV1/STG2000 as well as ! the Riva128. It is known to work on PCI and AGP versions of the Riva128. <sect1>Notes <p> <itemize> ! <item>On the NV1/STG2000, the driver does not support the virtual desktop ! features of xfree86. This is because the NV1 does not have the necessary hardware to support this feature. If you want to change resolutions, you will have *************** *** 30,50 **** <tt>xf86config</tt> instead. Select `Diamond Edge 3D' as your board, and select only <bf>ONE</bf> mode for each of 8bpp and 16bpp. Do not select a virtual desktop. Also, make sure you don't select ! a RAMDAC or clock chip. ! <item>The NV1 only supports a 555 RGB Weight in 16 bpp, the hardware does ! not do 565. You must put a Weight 555 in the Display section. ! <item>24/32 bpp mode is not yet supported. </itemize> - <sect1>Known Bugs - <p> - <itemize> - <item>Corruption of a single pixel in 8bpp mode when switching VCs - <item>The driver should force Weight 555 in 16 bpp mode - </itemize> - <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/NV1.sgml,v 3.2 1997/01/24 09:32:15 dawes Exp $ </verb> </article> --- 30,56 ---- <tt>xf86config</tt> instead. Select `Diamond Edge 3D' as your board, and select only <bf>ONE</bf> mode for each of 8bpp and 16bpp. Do not select a virtual desktop. Also, make sure you don't select ! a RAMDAC or clock chip. This does not apply if you own a Riva128 ! card, as the VGA16 server works just fine on that. ! <item>Both the NV1 and the Riva128 only support a 555 RGB Weight in 16 bpp, ! the hardware does ! not do 565. If you run into problems with some window managers in ! 16bpp, try putting a Weight 555 in the Display section. ! <item>24 bpp is not supported. ! <item>In some modes the hardware cursor gets out of sync with the display. ! Use Option "sw_cursor" to work around this problem. ! <item>There are modelines that confuse the Riva128 chip. This results in ! a greenish display. Slightly modifying the modeline usually fixes ! the problem. In most cases all that is needed is to reduce the ! HTotal. You can use xvidtune to do that. ! <item>The dotclock limits for this driver seem to be lower than the ! hardware specs (and drivers for other graphical user interfaces) seem ! to indicate. If you get a flickery screen with flashes, try to limit ! the modes you use to about 160MHz in 16bpp and about 100MHz in 32bpp. </itemize> <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/NV1.sgml,v 3.2.2.3 1998/02/26 20:11:27 hohndel Exp $ </verb> </article> *** ./programs/Xserver/hw/xfree86/doc/sgml/NetBSD.sgml@@/PUBLIC-LATEST Sun Aug 10 13:03:22 1997 --- xc/programs/Xserver/hw/xfree86/doc/sgml/NetBSD.sgml Fri Mar 6 16:39:58 1998 *************** *** 1,13 **** <!DOCTYPE linuxdoc PUBLIC "-//XFree86//DTD linuxdoc//EN"> <article> ! <title>README for XFree86 3.3.1 on NetBSD <author>Rich Murphey, David Dawes, Marc Wandschneider, Mark Weaver, Matthieu Herrb ! <Date>Last modified on: 26 July 1997 <toc> --- 1,13 ---- <!DOCTYPE linuxdoc PUBLIC "-//XFree86//DTD linuxdoc//EN"> <article> ! <title>README for XFree86 3.3.2 on NetBSD <author>Rich Murphey, David Dawes, Marc Wandschneider, Mark Weaver, Matthieu Herrb ! <Date>Last modified on: 21 February 1998 <toc> *************** *** 15,21 **** <sect>What and Where is XFree86? <p> ! XFree86 3.3.1 is a port of X11R6.3 that supports several versions of Intel-based Unix. It is derived from X386 1.2, which was the X server distributed with X11R5. This release consists of many new features and performance improvements as well as many bug fixes. The release --- 15,21 ---- <sect>What and Where is XFree86? <p> ! XFree86 3.3.2 is a port of X11R6.3 that supports several versions of Intel-based Unix. It is derived from X386 1.2, which was the X server distributed with X11R5. This release consists of many new features and performance improvements as well as many bug fixes. The release *************** *** 46,60 **** upgrading to a newer version of NetBSD first. If you don't upgrade, you'll have to build XFree86 from the sources. ! XFree86 3.3.1 should compile cleanly under earlier versions of NetBSD, although this has not been tested. ! XFree86 3.3.1 also builds on NetBSD/sparc. See section ! <ref id="sparc" name="Building on sparc"> for details. ! The client side of XFree86 also builds on NetBSD/alpha. ! XFree86 3.3.1 also supports NetBSD on PC98 machines. <sect>Bug Reports for This Document --- 46,61 ---- upgrading to a newer version of NetBSD first. If you don't upgrade, you'll have to build XFree86 from the sources. ! XFree86 3.3.2 should compile cleanly under earlier versions of NetBSD, although this has not been tested. ! XFree86 3.3.2 also builds on NetBSD/sparc. See section ! <ref id="sparc" name="Building on other architectures"> for details. ! The client side of XFree86 also builds on NetBSD/alpha and many other ! architecture supported by NetBSD. ! XFree86 3.3.2 also supports NetBSD on PC98 machines. <sect>Bug Reports for This Document *************** *** 69,81 **** <p> <enum> <item>See the <htmlurl url="RELNOTES.html" name="Release Notes"> for ! non-OS dependent new features in XFree86 3.3.1. </enum> <sect>Installing the Binaries <p> ! Refer to section 4 of the <htmlurl url="RELNOTES.html" name="Release Notes"> for detailed installation instructions. --- 70,82 ---- <p> <enum> <item>See the <htmlurl url="RELNOTES.html" name="Release Notes"> for ! non-OS dependent new features in XFree86 3.3.2. </enum> <sect>Installing the Binaries <p> ! Refer to section 5 of the <htmlurl url="RELNOTES.html" name="Release Notes"> for detailed installation instructions. *************** *** 159,164 **** --- 160,172 ---- The NetBSD pms mouse driver handles PS/2 style mice as Busmouse. Specify the protocol <bf/busmouse/ in the mouse section of your <tt/XF86Config/ file if you're using a PS/2 mouse. + <p> + Only standard PS/2 mice are supported by this driver. Newest PS/2 + mice that send more than three bytes at a time (especially + intellimouse, or mouseman+ with a "3D" roller) are not supported yet. + <p> + See <htmlurl url="mouse.html" name="README.mouse"> for general + instruction on mouse configuration in XFree86. <sect1>Other input devices <p> *************** *** 327,333 **** /usr/X11R6/lib/X11/kernel/ap.o - ap /usr/X11R6/lib/X11/kernel/apinstall - </verb></tscreen> ! <item> NetBSD 1.2G and later <p> The <tt>lkm.conf</tt> format changed in 1.2G. Add the following line to <tt>/etc/lkm.conf</tt>: --- 335,341 ---- /usr/X11R6/lib/X11/kernel/ap.o - ap /usr/X11R6/lib/X11/kernel/apinstall - </verb></tscreen> ! <item> NetBSD 1.2G, 1.3 and later <p> The <tt>lkm.conf</tt> format changed in 1.2G. Add the following line to <tt>/etc/lkm.conf</tt>: *************** *** 411,417 **** <sect1>Console drivers<label id="console-drivers"> <p> ! XFree86 3.3.1 has a configuration option to select the console drivers to use in <tt/xf86site.def/: <itemize> <item> if you're using pccons put: --- 419,425 ---- <sect1>Console drivers<label id="console-drivers"> <p> ! XFree86 3.3.2 has a configuration option to select the console drivers to use in <tt/xf86site.def/: <itemize> <item> if you're using pccons put: *************** *** 479,485 **** <sect1>Support for shared libs under NetBSD 1.0 and later <p> ! By default XFree86 3.3.1 builds for NetBSD with shared libraries support. If you're building on 0.9 or don't want shared libraries add the following line to <tt/xf86site.def/: --- 487,493 ---- <sect1>Support for shared libs under NetBSD 1.0 and later <p> ! By default XFree86 3.3.2 builds for NetBSD with shared libraries support. If you're building on 0.9 or don't want shared libraries add the following line to <tt/xf86site.def/: *************** *** 487,496 **** #define BuildBsdSharedLibs NO </tscreen> ! <sect1>Building on Sparc<label id="sparc"> <p> ! XFree86 3.3.1 also compiles on NetBSD/sparc. The Sun server patches from Dennis Ferguson and Matthew Green have been integrated in <tt>xc/programs/Xserver/hw/sun</tt>. Small modifications to <tt/xf86site.def/ are needed: --- 495,504 ---- #define BuildBsdSharedLibs NO </tscreen> ! <sect1>Building on other architectures<label id="sparc"> <p> ! XFree86 3.3.2 also compiles on NetBSD/sparc. The Sun server patches from Dennis Ferguson and Matthew Green have been integrated in <tt>xc/programs/Xserver/hw/sun</tt>. Small modifications to <tt/xf86site.def/ are needed: *************** *** 509,514 **** --- 517,530 ---- <em/port-sparc@NetBSD.Org/ mailing list or directly to me <em/matthieu@laas.fr/ rather than to the xfree86 mailing list. + <p> + Note that the NetBSD project has now its own source tree, based on the + XFree86 source tree, with some local modifications. You may want to + start with this tree to rebuild from sources. + The NetBSD xsrc source tree is available at: + <htmlurl url="ftp://ftp.netbsd.org/pub/NetBSD/NetBSD-current/xsrc/" + name="ftp://ftp.netbsd.org/pub/NetBSD/NetBSD-current/xsrc/"> + <sect>Building New X Clients <p> *************** *** 573,585 **** </itemize> <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/NetBSD.sgml,v 3.45.2.5 1997/07/27 02:41:16 dawes Exp $ ! $TOG: NetBSD.sgml /main/28 1997/08/10 13:01:57 kaleb $ </verb> </article> --- 589,601 ---- </itemize> <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/NetBSD.sgml,v 3.45.2.7 1998/02/26 13:59:07 dawes Exp $ ! $TOG: NetBSD.sgml /main/29 1998/03/06 16:41:36 kaleb $ </verb> </article> *** ./programs/Xserver/hw/xfree86/doc/sgml/OS2.sgml@@/PUBLIC-LATEST Sun Aug 10 13:03:28 1997 --- xc/programs/Xserver/hw/xfree86/doc/sgml/OS2.sgml Fri Mar 6 16:40:04 1998 *************** *** 1,13 **** <!DOCTYPE linuxdoc PUBLIC "-//XFree86//DTD linuxdoc//EN"> <article> ! <title>README for XFree86 3.3.1 on OS/2 <author>Holger Veit ! <Date>Last modified on: 2 August 1997 <toc> ! <sect>Introductory Note about the release 3.3.1 <p> Before looking into this file, please check for any LATEST.OS2 files that may come with the binary distribution. Please also check out the --- 1,13 ---- <!DOCTYPE linuxdoc PUBLIC "-//XFree86//DTD linuxdoc//EN"> <article> ! <title>README for XFree86 3.3.2 on OS/2 <author>Holger Veit ! <Date>Last modified on: 15 February 1998 <toc> ! <sect>Introductory Note about the release 3.3.2 <p> Before looking into this file, please check for any LATEST.OS2 files that may come with the binary distribution. Please also check out the *************** *** 19,33 **** </itemize> before you claim to have found any problems. ! This version of the code is called XFree86/OS2 3.3.1. This is a bugfix release ! for 3.3. It is a full, unrestricted version which does not expire, and for ! which the complete source code is available. In contrast to beta versions, we ! consider this code as sufficiently stable for use by an end user. Since there have been numerous bugfixes, we recommend this version, even if you had ! XFree86/OS2 3.2 before and it worked satisfyingly with your hardware. ! By the time 3.3.1 is released, the older version 3.3 will be withdrawn, and archives will be updated to this version. There may still be references ! to 3.3 still in documents; these apply to 3.3.1 as well, unless otherwise noted. Previous versions have been tested in a large number of configurations --- 19,35 ---- </itemize> before you claim to have found any problems. ! This version of the code is called XFree86/OS2 3.3.2. This is a bugfix release ! for 3.3.1 which also adds hardware support for some newer cards (including ! AGP boards. See the RELNOTES document for details. Xfree86/OS2-3.3.2 is a ! full, unrestricted version which does not expire, and for which the complete ! source code is available. In contrast to beta versions, we consider this ! code as sufficiently stable for use by an end user. Since there have been numerous bugfixes, we recommend this version, even if you had ! XFree86/OS2 3.3 before and it worked satisfyingly with your hardware. ! By the time 3.3.2 is released, the older version 3.3 will be withdrawn, and archives will be updated to this version. There may still be references ! to 3.3 still in documents; these apply to 3.3.2 as well, unless otherwise noted. Previous versions have been tested in a large number of configurations *************** *** 64,70 **** <sect>What and Where is XFree86? <p> ! XFree86 is a port of X11R6 that supports several versions of Intel-based Unix. It is derived from X386 1.2, which was the X server distributed with X11R5. This release consists of many new features and performance improvements as well as many bug fixes. The release --- 66,72 ---- <sect>What and Where is XFree86? <p> ! XFree86 is a port of X11R6.3 that supports several versions of Intel-based Unix. It is derived from X386 1.2, which was the X server distributed with X11R5. This release consists of many new features and performance improvements as well as many bug fixes. The release *************** *** 78,90 **** <!-- The sources for XFree86/OS2 are available by anonymous ftp from: ! <htmlurl name="ftp.XFree86.org:/pub/XFree86" ! url="ftp://ftp.XFree86.org/pub/XFree86"> --> Binaries for OS/2 Warp and Merlin are available from: ! <htmlurl name="ftp.XFree86.org:/pub/XFree86/beta/OS2" ! url="ftp://ftp.XFree86.org/pub/XFree86/beta/OS2"> <p> The WWW page <htmlurl name="http://borneo.gmd.de/~veit/os2/xf86os2.html" --- 80,92 ---- <!-- The sources for XFree86/OS2 are available by anonymous ftp from: ! <htmlurl name="ftp.XFree86.org:/pub/XFree86/3.3.2/source" ! url="ftp://ftp.XFree86.org/pub/XFree86/3.3.2/source"> --> Binaries for OS/2 Warp and Merlin are available from: ! <htmlurl name="ftp.XFree86.org:/pub/XFree86/3.3.2/OS2" ! url="ftp://ftp.XFree86.org/pub/XFree86/3.3.2/OS2"> <p> The WWW page <htmlurl name="http://borneo.gmd.de/~veit/os2/xf86os2.html" *************** *** 101,118 **** For Warp 3 installing fixpack level 17 is strongly recommended, newer fixpacks like 22 also work. There have been a few reports that the installation of FP26 causes XFree86 no longer to work, but I am not sure ! about a real reason. ! Warp 4 may be used with or without the recent public fixpack FP1. Please check in all cases a LATEST.OS2 file. OS/2 2.11 is not supported any longer with this release, due to lack ! of a working test environment. Consequently, OS/2 SMP is not supported either, ! because this is currently based on OS/2 2.11. Warp Server SMP is supported, ! but SMP does not give significant advantage, other than the general speedup ! because of multiple processors working. ! OS/2 versions 1.X are definitely not supported and will never be. It is possible to build XFree86/OS2 from the sources. Read about this in the document OS2.NOTES. --- 103,120 ---- For Warp 3 installing fixpack level 17 is strongly recommended, newer fixpacks like 22 also work. There have been a few reports that the installation of FP26 causes XFree86 no longer to work, but I am not sure ! about a real reason. Current fixpacks for Warp 3, like FP32, seem to work ! well also. ! Warp 4 may be used with or without the recent public fixpack FP5. Please check in all cases a LATEST.OS2 file. OS/2 2.11 is not supported any longer with this release, due to lack ! of a working test environment. Consequently, OS/2 SMP 2.11 is not supported ! either. Warp Server SMP is supported, but SMP does not give significant ! advantage, other than the general speedup because of multiple processors ! working. OS/2 versions 1.X are definitely not supported and will never be. It is possible to build XFree86/OS2 from the sources. Read about this in the document OS2.NOTES. *************** *** 153,159 **** <p> <itemize> <item>Any version of Warp 3 with at least fixpack 17, or Warp 4 is required ! <item>XFree86/OS2-3.3.1 may use a local named-pipe connection or a TCP/IP based network connection. <enum> <item>Warp comes with the Internet Access Kit (IAK), which is --- 155,161 ---- <p> <itemize> <item>Any version of Warp 3 with at least fixpack 17, or Warp 4 is required ! <item>XFree86/OS2-3.3.2 may use a local named-pipe connection or a TCP/IP based network connection. <enum> <item>Warp comes with the Internet Access Kit (IAK), which is *************** *** 161,166 **** --- 163,170 ---- version of TCP/IP (3.0). Use of this software is preferred over IAK then. <item>Warp 4 comes with TCP/IP 4.0 which should also work. + <item>There are reports that with EMX 0.9 fix 4, you can also use + the new 32 bit IBM TCP/IP 4.1 product. <item>The old IBM TCP/IP 2.0, that comes with the IBM PMX product may be used with Warp as well, although it is no longer supported by IBM. Please ensure that you have the latest CSDs installed. *************** *** 171,177 **** or NetBIOS work, and I won't to provide support for that in the future. <item>If you want to write or port applications for XFree86, you are encouraged to do so. You will need a complete installation of ! EMX/gcc 0.9C fix2 or later for doing so. Neither the second (obsolete) implementation of gcc, nor any commercial package, including Cset/2, VAC++, Borland C++/OS2, Watcom C++, Metaware C, and others, is suitable for porting, because various parts of the X DLLs rely --- 175,181 ---- or NetBIOS work, and I won't to provide support for that in the future. <item>If you want to write or port applications for XFree86, you are encouraged to do so. You will need a complete installation of ! EMX/gcc 0.9C fix4 or later for doing so. Neither the second (obsolete) implementation of gcc, nor any commercial package, including Cset/2, VAC++, Borland C++/OS2, Watcom C++, Metaware C, and others, is suitable for porting, because various parts of the X DLLs rely *************** *** 187,195 **** 40-55MB of disk space. All archives of this alpha version are packed with the <tt/info-zip/ utility, ! which is available under the name <tt/UNZ512X2.EXE/ from many OS/2 archives. ! Please obtain a native OS/2 version of this unpacker. DOS <tt/PKUNZIP/ does ! not work, because it cannot unpack long file names and extended attributes. At this moment, the distribution covers only the ``core'' distribution which somewhat reduces the usability. Refer to WWW sites and archives listed --- 191,200 ---- 40-55MB of disk space. All archives of this alpha version are packed with the <tt/info-zip/ utility, ! which is available under the name <tt/UNZ512X2.EXE/ (or a later version) ! from many OS/2 archives. Please obtain a native OS/2 version of this unpacker. ! DOS <tt/PKUNZIP/ does not work, because it cannot unpack long file names and ! extended attributes. At this moment, the distribution covers only the ``core'' distribution which somewhat reduces the usability. Refer to WWW sites and archives listed *************** *** 201,210 **** <descrip> <tag/REQUIRED:/ <descrip> ! <tag/X331base/ A special device driver and the SuperProbe program ! <tag/X331doc/ READMEs and XFree86 specific man pages. ! <tag/X331bin/ all of the executable X client applications and shared libs ! <tag/X331fnts/ the misc and 75dpi fonts <tag/emxrt/ Runtime libraries of EMX </descrip> --- 206,215 ---- <descrip> <tag/REQUIRED:/ <descrip> ! <tag/X332base/ A special device driver and the SuperProbe program ! <tag/X332doc/ READMEs and XFree86 specific man pages. ! <tag/X332bin/ all of the executable X client applications and shared libs ! <tag/X332fnts/ the misc and 75dpi fonts <tag/emxrt/ Runtime libraries of EMX </descrip> *************** *** 211,243 **** Choose at least one of the following to match your hardware: <descrip> ! <tag/X3318514/ the X server for IBM 8514/A and compatible boards ! <tag/X331AGX/ the X server for AGX boards ! <tag/X331I128/ the X server for #9 Imagination 128 boards ! <tag/X331Ma32/ the X server for ATI Mach32 graphics boards ! <tag/X331Ma64/ the X server for ATI Mach64 graphics boards ! <tag/X331Ma8/ the X server for ATI Mach8 graphics boards ! <tag/X331Mono/ the Monochrome X Server ! <tag/X331P9K/ the X server for P9000 based boards ! <tag/X331S3/ the X server for S3 based boards (excluding S3 ViRGE) ! <tag/X331S3V/ the X server for S3 ViRGE based boards ! <tag/X331SVGA/ the 8-bit pseudo-color X server for Super VGA cards ! <tag/X331VG16/ the 4-bit pseudo-color X server for VGA & SVGA cards. ! <tag/X331W32/ the X server for et4000w32 based boards </descrip> <tag/OPTIONAL:/ <descrip> ! <tag/X331man/ pre-formatted man pages for the X11 interface and clients ! <tag/X331f100/ 100dpi fonts ! <tag/X331fscl/ Speedo and Type1 fonts ! <tag/X331fnon/ Japanese, Chinese and other fonts ! <tag/X331fcyr/ Cyrillic fonts ! <tag/X331fsrv/ the font server with man pages. ! <tag/X331prog/ the X11 header files and programmer's utilities for compiling other X applications ! <tag/X331pex/ PEX fonts and libraries required for PEX applications </descrip> </descrip> --- 216,248 ---- Choose at least one of the following to match your hardware: <descrip> ! <tag/X3328514/ the X server for IBM 8514/A and compatible boards ! <tag/X332AGX/ the X server for AGX boards ! <tag/X332I128/ the X server for #9 Imagination 128 boards ! <tag/X332Ma32/ the X server for ATI Mach32 graphics boards ! <tag/X332Ma64/ the X server for ATI Mach64 graphics boards ! <tag/X332Ma8/ the X server for ATI Mach8 graphics boards ! <tag/X332Mono/ the Monochrome X Server ! <tag/X332P9K/ the X server for P9000 based boards ! <tag/X332S3/ the X server for S3 based boards (excluding S3 ViRGE) ! <tag/X332S3V/ the X server for S3 ViRGE based boards ! <tag/X332SVGA/ the 8-bit pseudo-color X server for Super VGA cards ! <tag/X332VG16/ the 4-bit pseudo-color X server for VGA & SVGA cards. ! <tag/X332W32/ the X server for et4000w32 based boards </descrip> <tag/OPTIONAL:/ <descrip> ! <tag/X332man/ pre-formatted man pages for the X11 interface and clients ! <tag/X332f100/ 100dpi fonts ! <tag/X332fscl/ Speedo and Type1 fonts ! <tag/X332fnon/ Japanese, Chinese and other fonts ! <tag/X332fcyr/ Cyrillic fonts ! <tag/X332fsrv/ the font server with man pages. ! <tag/X332prog/ the X11 header files and programmer's utilities for compiling other X applications ! <tag/X332pex/ PEX fonts and libraries required for PEX applications </descrip> </descrip> *************** *** 246,252 **** and occupies 3.0MB on the disk. You won't normally need more than the single Xserver tailored to your video card. ! If it is your first time install, get the <tt/X331base/ archive before any of the other packages. This package contains a driver and a test program, which analyzes your video hardware. If this program fails or reports an incompatible hardware, it makes no sense to obtain the other packages in --- 251,257 ---- and occupies 3.0MB on the disk. You won't normally need more than the single Xserver tailored to your video card. ! If it is your first time install, get the <tt/X332base/ archive before any of the other packages. This package contains a driver and a test program, which analyzes your video hardware. If this program fails or reports an incompatible hardware, it makes no sense to obtain the other packages in *************** *** 291,302 **** in all commands accordingly. <enum> ! <item>Obtain the package <tt/X331base/ and install it from the root directory of the Y: drive, by entering the following commands: <tscreen><verb> [C:\] Y: [Y:\] cd \ ! [Y:\] unzip \path_of_package\X331base.zip </verb></tscreen> <item>Edit your CONFIG.SYS file to contain the following line somewhere: --- 296,307 ---- in all commands accordingly. <enum> ! <item>Obtain the package <tt/X332base/ and install it from the root directory of the Y: drive, by entering the following commands: <tscreen><verb> [C:\] Y: [Y:\] cd \ ! [Y:\] unzip \path_of_package\X332base.zip </verb></tscreen> <item>Edit your CONFIG.SYS file to contain the following line somewhere: *************** *** 355,367 **** drive, and type: <tscreen><verb> drive:> cd \ ! drive:> unzip \path_of_packages\X331xxxx.zip </verb></tscreen> <item>You might encounter that some packages report duplicate files, e.g. the X server packages install corresponding README files, which are also ! in the X331doc package. This is okay, the files are the same. Let unzip replace the files. ! <item>There is no special sequence of installing packages required. </enum> <sect>Adding Variables to CONFIG.SYS <label id="envvar"> --- 360,372 ---- drive, and type: <tscreen><verb> drive:> cd \ ! drive:> unzip \path_of_packages\X332xxxx.zip </verb></tscreen> <item>You might encounter that some packages report duplicate files, e.g. the X server packages install corresponding README files, which are also ! in the X332doc package. This is okay, the files are the same. Let unzip replace the files. ! <item>No special sequence to unpack the files is required. </enum> <sect>Adding Variables to CONFIG.SYS <label id="envvar"> *************** *** 368,374 **** <p> XFree86/OS2 requires a number of settings in the CONFIG.SYS file to work ! correctly. Please add the following settings: <descrip> <tag/TERM/ --- 373,380 ---- <p> XFree86/OS2 requires a number of settings in the CONFIG.SYS file to work ! correctly. Please add the following settings, and in particular take ! care to set forward versus backward slashes correctly: <descrip> <tag/TERM/ *************** *** 490,496 **** <item>Add the following line to your <tt>\tcpip\bin\tcpstart.cmd</tt>: <tscreen><verb>ifconfig lo 127.0.0.1 up</verb></tscreen> ! <item>Uncomment the <tt/inetd/ process in the same file. <item>Set the HOSTNAME environment variable to <tt/localhost/ as described in the last section. <item>Add the following line to CONFIG.SYS: --- 496,506 ---- <item>Add the following line to your <tt>\tcpip\bin\tcpstart.cmd</tt>: <tscreen><verb>ifconfig lo 127.0.0.1 up</verb></tscreen> ! If you don't have such a tcpstart.cmd file (Warp 4 calls this file ! <tt>\MPTN\BIN\MPTSTART.CMD</tt>), create one, and add a line ! like the following to your config.sys file: ! <tt>CALL=C:\OS2\CMD.EXE /Q /C C:\tcpip\bin\tcpstart.cmd >NUL</tt>: ! (implying that your bootdrive is C:). <item>Set the HOSTNAME environment variable to <tt/localhost/ as described in the last section. <item>Add the following line to CONFIG.SYS: *************** *** 499,506 **** <tscreen><verb>[C:\] ping localhost</verb></tscreen> </enum> The <tt/checkinstall.cmd/ script coming with XFree86/OS2 gives some advice ! here as well. If you have problems to get this or other basic networking things running, seek assistance elsewhere. --- 509,522 ---- <tscreen><verb>[C:\] ping localhost</verb></tscreen> </enum> + You don't need this ``loopback'' interface if your PC is connected to a LAN + (either directly or through SLIP/PPP). + + In case of a SLIP/PPP line, you have to establish this connection BEFORE + you start XFree86. + The <tt/checkinstall.cmd/ script coming with XFree86/OS2 gives some advice ! on the configuration as well. If you have problems to get this or other basic networking things running, seek assistance elsewhere. *************** *** 510,516 **** <p> After you have added the required settings and setup a working network, run the <tt/xf86config/ program to create a standard configuration file ! in <tt>Y:\XFree86\lib\X11\XConfig</tt> from a windowed or full screen OS/2 text session: <tscreen><verb>[C:\] xf86config</verb></tscreen> --- 526,532 ---- <p> After you have added the required settings and setup a working network, run the <tt/xf86config/ program to create a standard configuration file ! in <tt>Y:\XFree86\lib\X11\XF86Config</tt> from a windowed or full screen OS/2 text session: <tscreen><verb>[C:\] xf86config</verb></tscreen> *************** *** 520,527 **** assistance in the newsgroups. It is possible, but strongly discouraged for the non-expert, to edit the ! <tt/XConfig/ file with a text editor. In a few situations, as described in ! the FAQ, this might even be mandatory. This file is not a hacker's area, such as the Win95 registry, but it has in common with it that you can easily cause damage. --- 536,543 ---- assistance in the newsgroups. It is possible, but strongly discouraged for the non-expert, to edit the ! <tt/XF86Config/ file with a text editor. In a few situations as described in ! the FAQ, however, this might even be mandatory. This file is not a hacker's area, such as the Win95 registry, but it has in common with it that you can easily cause damage. *************** *** 531,537 **** If you know the configuration process from Linux or other XFree86 platform, you will encounter a few differences: <itemize> - <item>The configuration file is named <tt/XF86Config/ in Unix environments. <item>There is no configuration for the mouse type or device. The mouse device name is fixed to OSMOUSE, and this cannot be changed. If you have a three-button-mouse, install the correct OS/2 driver --- 547,552 ---- *************** *** 541,551 **** DEVICE=D:\OS2\BOOT\MOUSE.SYS TYPE=PCLOGIC$ </verb></tscreen> for a MouseSystems compatible mouse, for instance. ! <item>The X server does not read the native OS/2 keyboard map, ! so you need a xmodmap file for a non-us keyboard. Fortunately, it ! is the same you use for Linux. Alternatively, for standard keyboards, ! you can also use the XKB extension which is offered during the ! <tt/xf86config/ dialogue, provided your language is available. <item>There is no support for the Wacom and Elographics input devices yet. </itemize> --- 556,569 ---- DEVICE=D:\OS2\BOOT\MOUSE.SYS TYPE=PCLOGIC$ </verb></tscreen> for a MouseSystems compatible mouse, for instance. ! <item>The X server does not read the native OS/2 keyboard map, but the new XKB ! server extension might already give you a correct keyboard layout, ! provided your language was selectable in the <tt/xf86config/ program. If you ! encounter incorrect settings, please send a mail to <tt/XFree86@XFree86.org/ ! describing in detail what is wrong. Even with XKB, you have the option ! to replace some key settings with a xmodmap file. See the man page ! for xmodmap for details (or use some available xmodmap file from Linux - ! they are the same). <item>There is no support for the Wacom and Elographics input devices yet. </itemize> *************** *** 559,565 **** <tscreen><verb> MemBase 0x12345678 </verb></tscreen> ! to the XConfig file. Once you've set up a XF86Config file, you can fine tune the video modes with the <tt>xvidtune</tt> utility. --- 577,583 ---- <tscreen><verb> MemBase 0x12345678 </verb></tscreen> ! to the XF86Config file. Once you've set up a XF86Config file, you can fine tune the video modes with the <tt>xvidtune</tt> utility. *************** *** 620,632 **** </itemize> <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/OS2.sgml,v 3.9.2.4 1997/08/04 02:10:42 dawes Exp $ ! $TOG: OS2.sgml /main/6 1997/08/10 13:02:03 kaleb $ </verb> </article> --- 638,650 ---- </itemize> <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/OS2.sgml,v 3.9.2.5 1998/02/22 01:28:24 robin Exp $ ! $TOG: OS2.sgml /main/7 1998/03/06 16:41:42 kaleb $ </verb> </article> *** ./programs/Xserver/hw/xfree86/doc/sgml/OS2note.sgml@@/PUBLIC-LATEST Sat Jul 19 10:32:47 1997 --- xc/programs/Xserver/hw/xfree86/doc/sgml/OS2note.sgml Fri Mar 6 16:40:09 1998 *************** *** 3,9 **** <title>Notes on Rebuilding XFree86/OS2 from Scratch <author>Holger Veit ! <date>Last modified 17 May 1997 <toc> --- 3,9 ---- <title>Notes on Rebuilding XFree86/OS2 from Scratch <author>Holger Veit ! <date>Last modified 26 Mar 1998 <toc> *************** *** 20,36 **** Please also read <htmlurl name=README.OS2 url=OS2.html> for end-user information, and set at least the environment variables described there. <p> ! At the current time, the most recent version available is XFree86-3.3. This is a full and unrestricted version which comes with complete source ! code. 3.3 is an intermediate version which was released because the last ! beta version (3.2A) was about to expire and the new 4.0 version was not ! completely finished in time. 3.3 is the last ``classical'' version which ! has separate Xservers for different video cards. If you want to join the XFree86 developer team, e.g. to add support for certain hardware, please send a request to BOD@XFree86.org. Please think about such a step carefully before, though, since much work is ! involved. Please use the XFree86-3.3 source code as a test example how to compile the system. The ability to manage that is a basic requirement for becoming a developer. --- 20,35 ---- Please also read <htmlurl name=README.OS2 url=OS2.html> for end-user information, and set at least the environment variables described there. <p> ! At the current time, the most recent version available is XFree86-3.3.2. This is a full and unrestricted version which comes with complete source ! code. 3.3.2 is not only a bugfix release, but also supports new hardware, ! some of which might not even supported by OS/2 itself. See the RELEASE NOTES ! document for details. If you want to join the XFree86 developer team, e.g. to add support for certain hardware, please send a request to BOD@XFree86.org. Please think about such a step carefully before, though, since much work is ! involved. Please use the XFree86-3.3.2 source code as a test example how to compile the system. The ability to manage that is a basic requirement for becoming a developer. *************** *** 46,52 **** via anonymous FTP. The following shopping list shows what you will need: <itemize> ! <item>gcc EMX/gcc emx 0.9C patch2 or later <item>gzip GNU zip/unzip <item>tar GNU tar <item>patch Larry Wall's patch utility (attention: incompatible tool with same name in OS/2) --- 45,51 ---- via anonymous FTP. The following shopping list shows what you will need: <itemize> ! <item>gcc EMX/gcc emx 0.9C patch4 or later <item>gzip GNU zip/unzip <item>tar GNU tar <item>patch Larry Wall's patch utility (attention: incompatible tool with same name in OS/2) *************** *** 57,63 **** <item>sed GNU sed stream editor <item>grep GNU grep <item>gawk GNU awk ! <item>make GNU make 3.71/3.72 (use the one coming with XFree86!) <item>flex GNU flex <item>bison GNU bison <item>find GNU find (attention: incompatible tool with the same name in OS/2) --- 56,62 ---- <item>sed GNU sed stream editor <item>grep GNU grep <item>gawk GNU awk ! <item>make GNU make 3.71/3.72 (use the one from X332prog.zip!) <item>flex GNU flex <item>bison GNU bison <item>find GNU find (attention: incompatible tool with the same name in OS/2) *************** *** 176,182 **** --- 175,195 ---- xmake install xmake install.man </verb> + <item>There are a few minor glitches in the installation: + <enum> + <item>The xdm and linkkit directories will fail in compile and installation. + This is no problem and has no effect on the rest of the system. + <item>The imake.exe which is installed in <tt/\XFree86\bin/ is usually defective. + The one which was built initially and installed in the root directory + of the drive where you have the source tree is okay. So simply copy + this <tt/\imake.exe/ to the <tt/\XFree86\bin/ directory + manually. Some day this might be fixed. + <item><tt/XF86Setup/ is not ported yet and won't work with the tcl/tk port + available for XFree86/OS2. My idea was to replace this by some native + installation tool, which I didn't find the time to do yet. Feel free + to spend a bit of time to play with XF86Setup if you like. </enum> + </enum> Well, you see, this was quite easy :-) *************** *** 184,196 **** <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/OS2note.sgml,v 3.4.2.2 1997/05/24 08:36:06 dawes Exp $ ! $TOG: OS2note.sgml /main/2 1997/07/19 10:32:49 kaleb $ </verb> </article> --- 197,209 ---- <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/OS2note.sgml,v 3.4.2.3 1998/02/26 20:11:29 hohndel Exp $ ! $TOG: OS2note.sgml /main/3 1998/03/06 16:41:46 kaleb $ </verb> </article> *** ./programs/Xserver/hw/xfree86/doc/sgml/Oak.sgml@@/PUBLIC-LATEST Sat Jul 19 10:32:53 1997 --- xc/programs/Xserver/hw/xfree86/doc/sgml/Oak.sgml Fri Mar 6 16:40:13 1998 *************** *** 5,11 **** <!-- Title information --> <title>Information for Oak Technologies Inc. Chipset Users <author>Jorge F. Delgado Mendoza (<it>ernar@dit.upm.es</it>) ! <date>12 March 1996 <!-- Table of contents --> <toc> --- 5,11 ---- <!-- Title information --> <title>Information for Oak Technologies Inc. Chipset Users <author>Jorge F. Delgado Mendoza (<it>ernar@dit.upm.es</it>) ! <date>27 February 1998 <!-- Table of contents --> <toc> *************** *** 16,47 **** server. The following chipsets for Oak Tech. Inc. are supported: <descrip> <tag>OTI037C</tag> ! 8-bit SVGA chipset, with up to 256Kbytes of DRAM, only ! preliminary support is included in the driver as I don't have ! a 037c to test it. <tag>OTI067</tag> ! ISA SVGA chipset, up to 512Kbytes of DRAM (usually 70/80 ns). <tag>OTI077</tag> ! Enhanced version of the 067, with support for 1Mbyte and ! up to 65 Mhz dot-clock, this chipset supports up to ! 1024x768x256 colors in Non-Interlaced mode, and up to ! 1280x1024x16 colors Interlaced. <tag>OTI087</tag> ! One of the first VLB chipsets available, it has a 16-bit ! external data path, and a 32-bit internal ! memory-controller data path, it also has register-based ! color expansion, hardware cursor, a primitive BitBlt ! engine, a 64 bit graphic latch and some other new (on its ! time) features. Maximum BIOS resolutions are 1024x768x256 ! Non-Interlaced and 1280x1024x256 interlaced. Maximum ! Dot-Clock is 80Mhz, but is usually coupled with the OTI068 ! clock generator whose highest frequency is 78Mhz. ! Supports up to 2MBytes of 70/70R ns DRAM. <tag>OTI107 and OTI111</tag> ! These are new, PCI chipsets by Oak Tech. Inc. Support is not ! included for them, as they are very rare, and I haven't had ! the chance to look at one of these boards. </descrip> All the chipsets up to the OTI087 are "Backwards compatible", --- 16,55 ---- server. The following chipsets for Oak Tech. Inc. are supported: <descrip> <tag>OTI037C</tag> ! 8-bit VGA chipset, with up to 256Kbytes of DRAM. All the ! boards I have seen are only able to do standard VGA modes. ! (ie. up to 320x200x256 and up to 640x480x16). Currently the ! probe for this chip is disabled, so use the generic VGA ! driver instead. <tag>OTI067</tag> ! ISA SVGA chipset, up to 512Kbytes of DRAM (usually 70/80 ns). <tag>OTI077</tag> ! Enhanced version of the 067, with support for 1Mbyte and ! up to 65 Mhz dot-clock. This chipset is capable of resolutions ! up to ! 1024x768x256 colors in Non-Interlaced mode, and up to ! 1280x1024x16 colors Interlaced. <tag>OTI087</tag> ! One of the first VLB chipsets available, it has a 16-bit ! external data path, and a 32-bit internal memory-controller ! data path. It features some acceleration hardware: ! register-based color expansion, hardware cursor, ! a primitive BitBlt engine, a 64 bit graphic latch and some ! other new (on its time) features. ! Maximum BIOS resolutions are 1024x768x256 ! Non-Interlaced and 1280x1024x256 interlaced. Maximum ! Dot-Clock is 80Mhz, but is usually coupled with the OTI068 ! clock generator capable of frequencies up to 78Mhz. ! This chipset supports up to 2MBytes of 70/70R ns DRAM. <tag>OTI107 and OTI111</tag> ! These are new, PCI chipsets by Oak Tech. Inc. Support is not ! included for them, as they are very rare and I haven't had ! the chance to look at one of these boards. ! We have been unable to locate either 107's or 111's (also ! called "Spitfire 64111"). If anybody has such a board and ! can donate it to XFree86, I would be more than glad to add ! support for them. </descrip> All the chipsets up to the OTI087 are "Backwards compatible", *************** *** 55,62 **** The following options are of particular interest to the Oak driver. Each of them must be specified in the 'svga' driver section of the ! <tt>XF86Config</tt> file, within the Screen subsections to which they are ! applicable (you can enable options for all depths by specifying them in the Device section). <descrip> --- 63,72 ---- The following options are of particular interest to the Oak driver. Each of them must be specified in the 'svga' driver section of the ! <tt>XF86Config</tt> file, within the Screen subsections to which they ! are ! applicable (you can enable options for all depths by specifying them in ! the Device section). <descrip> *************** *** 63,158 **** <tag> Option &dquot;linear&dquot; (OTI087) </tag> ! This option enables a linear framebuffer at 0xE00000 (14Mb) for ! cards recognized as ISA by the probe. Cards that are VLB will ! map the framebuffer at 0x4E00000. The aperture depends ! on the VideoRam parameter in the <tt>XF86Config</tt> file or on ! the probed value for the board. It will speed up performance by ! about 15% on a VLB-based boards for a DX2-66 486. ! Sometimes a motherboard will not be able to map at 0x4E00000, ! and then linear mode will not work with more than 14 Mbytes of ! main RAM. I know this because mine doesn't. <tag> Option &dquot;fifo_aggressive&dquot; (OTI087) </tag> ! This option will cause the command FIFO threshold of the ! chipset to be set at 0 instructions, which should be optimal ! for 16-bit data transfers, as empirical use of different ! thresholds, with xbench, show. Expect a 5-10% of performance ! boost on a DX2-66 486. <tag> Option &dquot;fifo_conservative&dquot; (OTI087) </tag> ! This option will set the FIFO to a safe value of 14, slowing ! the board by a 50%, use this only if you experience streaks or ! anomalies on the screen. <tag> Option &dquot;enable_bitblt&dquot; (OTI087) </tag> ! This option will enable an internal cache on the board that ! will be used as a rudimentary bitblt engine. Performance boost ! is more or less 100%, (double BlitStones on xbench). Most ! OTI087 boards seem to have this feature broken, corrupting text ! from xterms and leaving mouse droppings throughout the ! screen. As a rule of thumb, enable it, if it works badly, ! disable it ;). <tag> Option &dquot;clock_50&dquot; (OTI087) </tag> ! This one will force the internal speed to 50 Mhz. <tag> Option &dquot;clock_66&dquot; (OTI087) </tag> ! This one will force the internal speed to 66 Mhz, speeding up ! performance of the chipset. <tag> Option &dquot;no_wait&dquot; (OTI087) </tag> ! Sets the VLB interface to no wait states. On a medium VLB ! board (mine is VLB/PCI, so its not a very fast one) in VLB ! transparent mode, it manages up to 16 Mbytes/second transfer ! rate through the bus. <tag> Option &dquot;first_wait&dquot; (OTI087) </tag> ! Makes the VLB interface to add one wait state to the first ! read or write of a given burst. <tag> Option &dquot;first_wwait&dquot; (OTI087) </tag> ! Similar to the previous one, this only inserts a wait state in ! the first 'write' of a given burst. reads are not ! affected. This is the default behaviour of the server. <tag> Option &dquot;write_wait&dquot; (OTI087) </tag> ! This configures the VLB interface to add one wait state to ! each write cycle. <tag> Option &dquot;read_wait&dquot; (OTI087) </tag> ! This configures the VLB interface to add one wait state to ! each read cycle. <tag> Option &dquot;all_wait&dquot; (OTI087) </tag> ! Enables the slowest VLB transfer adding wait states in all ! cases. Hopefully, no board will need this enabled. <tag> Option &dquot;one_wait&dquot; (OTI087) </tag> ! Sets the VLB interface to at least one wait state. <tag> Option &dquot;noaccel&dquot; (OTI087) </tag> ! One accelerated routine has been lately added to the driver, ! allowing it to draw solid fills quite faster. This routine ! only works (up to date) on segmented addressing, and only if ! the virtual width is 1024. This option is automatically enabled ! by the driver. Use this option if you want to disable it. </descrip> As a rule of thumb, use the option "no_wait", and if it doesn't --- 73,170 ---- <tag> Option &dquot;linear&dquot; (OTI087) </tag> ! This option enables a linear framebuffer at 0xE00000 (14Mb) for ! cards recognized as ISA by the probe. Cards that are VLB will ! map the framebuffer at 0x4E00000. The aperture depends ! on the VideoRam parameter in the <tt>XF86Config</tt> file or on ! the probed value for the board. It will speed up performance by ! about 15% on a VLB-based boards for a DX2-66 486. ! Sometimes a motherboard will not be able to map at 0x4E00000, ! and then linear mode will not work with more than 14 Mbytes of ! main RAM. I know this because mine doesn't. <tag> Option &dquot;fifo_aggressive&dquot; (OTI087) </tag> ! This option will cause the command FIFO threshold of the ! chipset to be set at 0 instructions, which should be optimal ! for 16-bit data transfers, as empirical use of different ! thresholds, with xbench, show. Expect a 5-10% of ! performance ! boost on a DX2-66 486. <tag> Option &dquot;fifo_conservative&dquot; (OTI087) </tag> ! This option will set the FIFO to a safe value of 14, slowing ! the board by a 50%, use this only if you experience ! streaks or ! anomalies on the screen. <tag> Option &dquot;enable_bitblt&dquot; (OTI087) </tag> ! This option will enable an internal cache on the board that ! will be used as a rudimentary bitblt engine. Performance boost ! is more or less 100%, (double BlitStones on xbench). Most ! OTI087 boards seem to have this feature broken, corrupting text ! from xterms and leaving mouse droppings throughout the ! screen. As a rule of thumb, enable it, if it works badly, ! disable it. <tag> Option &dquot;clock_50&dquot; (OTI087) </tag> ! This one will force the internal speed to 50 Mhz. <tag> Option &dquot;clock_66&dquot; (OTI087) </tag> ! This one will force the internal speed to 66 Mhz, speeding up ! performance of the chipset. <tag> Option &dquot;no_wait&dquot; (OTI087) </tag> ! Sets the VLB interface to no wait states. On a medium VLB ! board (mine is VLB/PCI, so its not a very fast one) in VLB ! transparent mode, it manages up to 16 Mbytes/second transfer ! rate through the bus. <tag> Option &dquot;first_wait&dquot; (OTI087) </tag> ! Makes the VLB interface to add one wait state to the first ! read or write of a given burst. <tag> Option &dquot;first_wwait&dquot; (OTI087) </tag> ! Similar to the previous one, this only inserts a wait state in ! the first 'write' of a given burst. reads are not ! affected. This is the default behaviour of the server. <tag> Option &dquot;write_wait&dquot; (OTI087) </tag> ! This configures the VLB interface to add one wait state to ! each write cycle. <tag> Option &dquot;read_wait&dquot; (OTI087) </tag> ! This configures the VLB interface to add one wait state to ! each read cycle. <tag> Option &dquot;all_wait&dquot; (OTI087) </tag> ! Enables the slowest VLB transfer adding wait states in all ! cases. Hopefully, no board will need this enabled. <tag> Option &dquot;one_wait&dquot; (OTI087) </tag> ! Sets the VLB interface to at least one wait state. <tag> Option &dquot;noaccel&dquot; (OTI087) </tag> ! One accelerated routine has been lately added to the driver, ! allowing it to draw solid fills quite faster. This routine ! only works (up to date) on segmented addressing, and only if ! the virtual width is 1024. This option is automatically enabled ! by the driver. Use this option if you want to disable it. </descrip> As a rule of thumb, use the option "no_wait", and if it doesn't *************** *** 185,204 **** detected if VideoRam is not found. I hope (because I have not tested it very thoroughly) that linear ! addressing will work on ISA boards, VLB ones are fine (I am ! writing this stuff on mine). - - GOOD LUCK!!!! - <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/Oak.sgml,v 3.12 1997/01/25 03:22:02 dawes Exp $ ! $TOG: Oak.sgml /main/9 1997/07/19 10:32:55 kaleb $ </verb> </article> --- 197,212 ---- detected if VideoRam is not found. I hope (because I have not tested it very thoroughly) that linear ! addressing will work on all ISA boards, VLB ones work flawlessly. <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/Oak.sgml,v 3.12.2.2 1998/02/28 13:29:46 dawes Exp $ ! $TOG: Oak.sgml /main/10 1998/03/06 16:41:50 kaleb $ </verb> </article> *** ./programs/Xserver/hw/xfree86/doc/sgml/QStart.sgml@@/PUBLIC-LATEST Sat Jul 19 10:33:05 1997 --- xc/programs/Xserver/hw/xfree86/doc/sgml/QStart.sgml Fri Mar 6 16:40:21 1998 *************** *** 5,11 **** <title>Quick-Start Guide to XFree86 Setup <author>Joe Moss ! <date>26 August 1996 <abstract> Current releases of XFree86 include several tools that can help --- 5,11 ---- <title>Quick-Start Guide to XFree86 Setup <author>Joe Moss ! <date>27 February 1998 <abstract> Current releases of XFree86 include several tools that can help *************** *** 44,50 **** It will help speed up the process, if you know which protocol is used by your mouse to communicate. Some mice are capable of using two different protocols, although the method of ! switching between them varies. </descrip> <sect> What to Do - An Overview --- 44,52 ---- It will help speed up the process, if you know which protocol is used by your mouse to communicate. Some mice are capable of using two different protocols, although the method of ! switching between them varies. In some cases, with new ! Plug-n-Play mice, the protocol can be determined ! automatically. </descrip> <sect> What to Do - An Overview *************** *** 98,103 **** --- 100,113 ---- is found, it will display a message and exit. Correct the problem (e.g. install the missing files) and run it again. + XF86Setup is internationalized. If you are Japanese and set + the LANG environment variable to ja, japan, japanese, etc., + XF86Setup's screen can be Japanized. But it is necessary that + XF86Setup is built with Japanized Tcl/Tk. Other language can + be added, if you prepare its own directory under the directory + XF86Setup/texts. Please see under the directory + XF86Setup/texts/generic. + <sect1> Initial questions <p> If you have an existing XF86Config file, you will be asked if *************** *** 120,126 **** <sect1> Configuration areas <p> Once the VGA16 server is started, and once the program has ! finished loading, you will see a screen with five buttons along the top and three along the bottom. The buttons along the top correspond to the general categories of configuration settings. They can be done in any order. --- 130,136 ---- <sect1> Configuration areas <p> Once the VGA16 server is started, and once the program has ! finished loading, you will see a screen with six buttons along the top and three along the bottom. The buttons along the top correspond to the general categories of configuration settings. They can be done in any order. *************** *** 156,162 **** If that is not happening, then your mouse is not correctly configured. <p> ! Along the top is a row of buttons corresponding to the various possible protocols. There will also be several buttons and a couple of sliders for other settings, a visual representation of the mouse, --- 166,172 ---- If that is not happening, then your mouse is not correctly configured. <p> ! Along the top are some rows of buttons corresponding to the various possible protocols. There will also be several buttons and a couple of sliders for other settings, a visual representation of the mouse, *************** *** 173,179 **** either the mouse device or the protocol (or both). You can press 'n' followed by a Tab, to move to the list of mouse devices and select a different one. ! Pressing 'p' will pick the next available protocol on the list. After changing these, press 'a' to apply the changes and try again. Repeat the process until you are getting some response from your mouse. --- 183,192 ---- either the mouse device or the protocol (or both). You can press 'n' followed by a Tab, to move to the list of mouse devices and select a different one. ! Pressing 'p' will pick the next available protocol on the list ! (protocols that are not available on your OS will be ! greyed-out). If you have a PnP mouse, it may be easiest to ! just select "Auto" as the protocol. After changing these, press 'a' to apply the changes and try again. Repeat the process until you are getting some response from your mouse. *************** *** 263,268 **** --- 276,296 ---- card, though the server will usually be able to detect this. + <sect2> Modeselect + <p> + Use this one to pick which depth you prefer to use (this + determines how many colors can be displayed at a time) + and to select all of the modes you are interested in + possibly using. + <p> + Your hardware may not be able to support all + of depth and mode combinations that can be selected. + Any unsupported combinations will automatically be + rejected by the server when it tries to startup. + Note also that if you select multiple modes, you will + get a virtual screen as large as the largest of the + usable modes. + <sect2> Monitor <p> Enter the horizontal and vertical frequency ranges that your *************** *** 391,396 **** --- 419,428 ---- as to which might be most likely) and then see the troubleshooting section if it doesn't work when you run the server. + + The xf86config program has not been updated to allow you to + select the latest mouse protocols, so you may have to edit + the config file by hand after xf86config has finished. <sect1> Keyboard setup <p> *************** *** 440,446 **** If you have a card which uses one of the chipsets for which a specific server exists (Mach8, Mach32, Mach64, AGX/XGA, ! 8514/A, S3, ET4000/W32, I128, P9000) you'll want to pick the <tt/accel/ option. Otherwise you'll probably want to use the SVGA server. --- 472,478 ---- If you have a card which uses one of the chipsets for which a specific server exists (Mach8, Mach32, Mach64, AGX/XGA, ! 8514/A, S3, I128, P9000) you'll want to pick the <tt/accel/ option. Otherwise you'll probably want to use the SVGA server. *************** *** 626,638 **** <sect1> I don't appear to have xf86config or xvidtune on my system <p> ! Hmmm. Three possibilities: <enum> - <item>You have a version of XFree86 that is older than 3.1.2. - If this is the case then you probably aren't reading - this document either, because it wasn't included in - 3.1.2 and earlier releases. Please upgrade to the - latest version. <item>Your <tt/PATH/ is not set correctly. Make sure it includes the bin directory for the XFree86 binaries (usually, <tt>/usr/X11R6/bin</tt> --- 658,665 ---- <sect1> I don't appear to have xf86config or xvidtune on my system <p> ! Hmmm. A couple of possibilities: <enum> <item>Your <tt/PATH/ is not set correctly. Make sure it includes the bin directory for the XFree86 binaries (usually, <tt>/usr/X11R6/bin</tt> *************** *** 644,650 **** <!-- Lots of things still need to be added --> <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/QStart.sgml,v 3.4 1997/01/25 03:22:04 dawes Exp $ </verb> </article> --- 671,677 ---- <!-- Lots of things still need to be added --> <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/QStart.sgml,v 3.4.2.2 1998/02/28 04:47:08 dawes Exp $ </verb> </article> *** ./programs/Xserver/hw/xfree86/doc/sgml/README.sgml@@/PUBLIC-LATEST Sun Aug 10 13:03:33 1997 --- xc/programs/Xserver/hw/xfree86/doc/sgml/README.sgml Fri Mar 6 16:40:26 1998 *************** *** 3,11 **** <article> ! <title>README for XFree86&tm; 3.3.1 <author>The XFree86 Project, Inc ! <date>26 July 1997 <abstract> --- 3,11 ---- <article> ! <title>README for XFree86&tm; 3.3.2 <author>The XFree86 Project, Inc ! <date>28 January 1998 <abstract> *************** *** 12,33 **** XFree86 is a port of X11R6.3 that supports several Unix and Unix-like operating systems on Intel and other platforms. This release is a ! maintenance release, fixing bugs found in XFree86 3.3. It also includes ! the latest public patch for X11R6.3 (patch 2). The release is available as source patches against the X Consortium X11R6.3 code and the XFree86 ! 3.3 release. Binary distributions for many architectures are also ! available, including a binary upgrade for XFree86 3.3. </abstract> <toc> ! <sect>What's new in XFree86 3.3.1 <p> For a summary of new features in this release, please refer to the <htmlurl name="RELNOTES" url="RELNOTES.html"> file. - For a detailed list of changes, refer to the CHANGELOG file in the source distribution. --- 12,32 ---- XFree86 is a port of X11R6.3 that supports several Unix and Unix-like operating systems on Intel and other platforms. This release is a ! maintenance release, fixing bugs found in XFree86 3.3.1. ! The release is available as source patches against the X Consortium X11R6.3 code and the XFree86 ! 3.3.1 release. Binary distributions for many architectures are also ! available, including a binary upgrade for XFree86 3.3.1. </abstract> <toc> ! <sect>What's new in XFree86 3.3.2 <p> For a summary of new features in this release, please refer to the <htmlurl name="RELNOTES" url="RELNOTES.html"> file. For a detailed list of changes, refer to the CHANGELOG file in the source distribution. *************** *** 49,55 **** <ITEM>ISC: 4.0.3 <ITEM>AT&T: 2.1, 4.0 <ITEM>NCR: MP-RAS ! <ITEM>SunSoft: Solaris x86 2.1, 2.4, 2.5, 2.5.1 <ITEM>PANIX 5.0 for AT </itemize> --- 48,54 ---- <ITEM>ISC: 4.0.3 <ITEM>AT&T: 2.1, 4.0 <ITEM>NCR: MP-RAS ! <ITEM>SunSoft: Solaris x86 2.1, 2.4, 2.5, 2.5.1, 2.6 <ITEM>PANIX 5.0 for AT </itemize> *************** *** 69,78 **** <tag/Others:/ <itemize> ! <ITEM>NetBSD 1.0, 1.1, 1.2, 1.2.1 <ITEM>OpenBSD 2.0, 2.1 <ITEM>FreeBSD 2.0.5, 2.1, 2.1.5, 2.1.6, 2.1.7, 2.1.7.1, 2.2, ! 2.2.1, 2.2.2, 3.0-current <!-- <ITEM>BSD/386 1.1, BSD/OS 2.0 <ITEM>Mach 386 --- 68,77 ---- <tag/Others:/ <itemize> ! <ITEM>NetBSD 1.0, 1.1, 1.2, 1.2.1, 1.3 <ITEM>OpenBSD 2.0, 2.1 <ITEM>FreeBSD 2.0.5, 2.1, 2.1.5, 2.1.6, 2.1.7, 2.1.7.1, 2.2, ! 2.2.1, 2.2.2, 2.2.5, 3.0-current <!-- <ITEM>BSD/386 1.1, BSD/OS 2.0 <ITEM>Mach 386 *************** *** 90,98 **** <tag/PC98:/ <itemize> ! <ITEM>FreeBSD(98) 2.0.5, 2.1, 2.1.5, 2.2, 2.2.1 ! <ITEM>NetBSD/pc98 (based on NetBSD 1.2) <ITEM>PANIX 5.0 for 98 </itemize> </DESCRIP> --- 89,99 ---- <tag/PC98:/ <itemize> ! <ITEM>FreeBSD(98) 2.0.5, 2.1, 2.1.5, 2.1.7.1, 2.2, 2.2.1, ! 2.2.2, 2.2.5 ! <ITEM>NetBSD/pc98 (based on NetBSD 1.2, 1.2.1) <ITEM>PANIX 5.0 for 98 + <ITEM>Linux/98 </itemize> </DESCRIP> *************** *** 100,106 **** <sect> Supported video-card chip-sets <p> ! At this time, XFree86 3.3.1 supports the following chipsets: <DESCRIP> <tag/Ark Logic/ --- 101,107 ---- <sect> Supported video-card chip-sets <p> ! At this time, XFree86 3.3.2 supports the following chipsets: <DESCRIP> <tag/Ark Logic/ *************** *** 108,122 **** <tag/Alliance/ AP6422, AT24 <tag/ATI / ! 18800, 18800-1, 28800-2, 28800-4, 28800-5, 28800-6, 68800-3, ! 68800-6, 68800AX, 68800LX, 88800GX-C, 88800GX-D, 88800GX-E, ! 88800GX-F, 88800CX, 264CT, 264ET, 264VT, 264VT2, 264GT ! (this list includes the Mach8, Mach32, Mach64, 3D Rage and 3D Rage II) <tag/Avance Logic / ALG2101, ALG2228, ALG2301, ALG2302, ALG2308, ALG2401 <tag/Chips & Technologies / 65520, 65530, 65540, 65545, 65520, 65530, 65540, ! 65545, 65546, 65548, 65550, 65554, 65555, 68554 <tag/Cirrus Logic / CLGD5420, CLGD5422, CLGD5424, CLGD5426, CLGD5428, CLGD5429, CLGD5430, CLGD5434, CLGD5436, CLGD5440, CLGD5446, CLGD5462, --- 109,124 ---- <tag/Alliance/ AP6422, AT24 <tag/ATI / ! 18800, 18800-1, 28800-2, 28800-4, 28800-5, 28800-6, 68800-3, 68800-6, ! 68800AX, 68800LX, 88800GX-C, 88800GX-D, 88800GX-E, 88800GX-F, 88800CX, ! 264CT, 264ET, 264VT, 264GT, 264VT-B, 264VT3, 264GT-B, 264GT3 ! (this list includes the Mach8, Mach32, Mach64, 3D Rage, 3D Rage II and ! 3D Rage Pro) <tag/Avance Logic / ALG2101, ALG2228, ALG2301, ALG2302, ALG2308, ALG2401 <tag/Chips & Technologies / 65520, 65530, 65540, 65545, 65520, 65530, 65540, ! 65545, 65546, 65548, 65550, 65554, 65555, 68554, 64200, 64300 <tag/Cirrus Logic / CLGD5420, CLGD5422, CLGD5424, CLGD5426, CLGD5428, CLGD5429, CLGD5430, CLGD5434, CLGD5436, CLGD5440, CLGD5446, CLGD5462, *************** *** 134,148 **** <tag/IIT / AGX-014, AGX-015, AGX-016 <tag/Matrox/ ! MGA2064W (Millennium), MGA1064SG (Mystique) <tag/MX / MX68000(*), MX680010(*) <tag/NCR / 77C22(*), 77C22E(*), 77C22E+(*) <tag/Number Nine/ ! I128 (series I and II) <tag>NVidia/SGS Thomson </tag> ! NV1, STG2000 <tag/OAK / OTI067, OTI077, OTI087 <tag/RealTek/ --- 136,151 ---- <tag/IIT / AGX-014, AGX-015, AGX-016 <tag/Matrox/ ! MGA2064W (Millennium), MGA1064SG (Mystique and Mystique 220), ! MGA2164W (Millennium II PCI and AGP) <tag/MX / MX68000(*), MX680010(*) <tag/NCR / 77C22(*), 77C22E(*), 77C22E+(*) <tag/Number Nine/ ! I128 (series I and II), Revolution 3D (T2R) <tag>NVidia/SGS Thomson </tag> ! NV1, STG2000, RIVA128 <tag/OAK / OTI067, OTI077, OTI087 <tag/RealTek/ *************** *** 149,166 **** RTG3106(*) <tag/S3 / 86C911, 86C924, 86C801, 86C805, 86C805i, 86C928, 86C864, 86C964, ! 86C732, 86C764, 86C765, 86C767, 86C775, 86C868, 86C968, ! 86C325, 86C375, 86C385, 86C988, 86CM65 <tag/SiS/ 86C201, 86C202, 86C205 <tag/Tseng / ! ET3000, ET4000AX, ET4000/W32, ET4000/W32i, ET4000/W32p, ET6000 <tag/Trident / TVGA8800CS, TVGA8900B, TVGA8900C, TVGA8900CL, TVGA9000, ! TVGA9000i, TVGA9100B, TVGA9200CXR, TVGA9320(*), TVGA9400CXi, TVGA9420, TGUI9420DGi, TGUI9430DGi, TGUI9440AGi, TGUI9660XGi, ! TGUI9680, ProVidia 9682, ProVidia 9685, ProVidia 9692, Cyber 9382(*), ! Cyber 9385(*) <tag>Video 7/Headland Technologies </tag> HT216-32(*) <tag/Weitek / --- 152,170 ---- RTG3106(*) <tag/S3 / 86C911, 86C924, 86C801, 86C805, 86C805i, 86C928, 86C864, 86C964, ! 86C732, 86C764, 86C765, 86C767, 86C775, 86C785, 86C868, 86C968, ! 86C325, 86C357, 86C375, 86C375, 86C385, 86C988, 86CM65, 86C260 <tag/SiS/ 86C201, 86C202, 86C205 <tag/Tseng / ! ET3000, ET4000AX, ET4000/W32, ET4000/W32i, ET4000/W32p, ET6000, ET6100 <tag/Trident / TVGA8800CS, TVGA8900B, TVGA8900C, TVGA8900CL, TVGA9000, ! TVGA9000i, TVGA9100B, TVGA9200CXR, Cyber9320(*), TVGA9400CXi, TVGA9420, TGUI9420DGi, TGUI9430DGi, TGUI9440AGi, TGUI9660XGi, ! TGUI9680, ProVidia 9682, ProVidia 9685(*), Cyber 9382, ! Cyber 9385, Cyber 9388, 3DImage975(PCI), 3DImage985(AGP), Cyber 9397, ! Cyber 9520 <tag>Video 7/Headland Technologies </tag> HT216-32(*) <tag/Weitek / *************** *** 208,224 **** size is limited to approximately 800x600. ! <bf>Note:</bf> The Diamond SpeedStar 24 (and possibly some SpeedStar+) boards are NOT supported, even though they use the ET4000. ! The Weitek 9100 and 9130 chipsets are not supported (these are used on the Diamond Viper Pro and Viper SE boards). - The chips used on the FireGL boards are not currently supported. Most other Diamond boards will work with this release of XFree86. Diamond is actively supporting The XFree86 Project, Inc. <sect>Where to get more information <p> --- 212,243 ---- size is limited to approximately 800x600. ! <bf>Notes:</bf> The Diamond SpeedStar 24 (and possibly some SpeedStar+) boards are NOT supported, even though they use the ET4000. ! The Weitek 9100 and 9130 chipsets are not supported (these are used on the Diamond Viper Pro and Viper SE boards). Most other Diamond boards will work with this release of XFree86. Diamond is actively supporting The XFree86 Project, Inc. + 3DLabs GLINT, Permedia and Permedia 2 support could unfortunately not + be included in XFree86 3.3.2 since there are open issues regarding the + documentation and whether or not they were provided to us under NDA. + + S.u.S.E. will continue to make available binary only servers for these + cards. These servers can be freely distributed just like XFree86, + but sources cannot be made available. S.u.S.E. will continue to develop + these servers and will continue to try to donate the code back to + XFree86. For the time being S.u.S.E. will try to not only make Linux + binaries available, but binaries for other platforms as well. + + Please contact <htmlurl name="x@suse.de" url="mailto:x@suse.de"> + with further questions. You can find the + servers at <htmlurl name="http://www.suse.de/XSuSE/XSuSE_E.html" + url="http://www.suse.de/XSuSE/XSuSE_E.html"> + <sect>Where to get more information <p> *************** *** 260,271 **** <sect>Thanks <p> The XFree86 Project wants to express a special thanks to ! S.u.S.E. GmbH, Fürth, Germany, for hiring our Core Team member and ! Vice President Dirk Hohndel as an employee and allowing him to work ! more or less full time on XFree86 for the past 5 months. Without this ! significant investment from S.u.S.E. into XFree86 the 3.3 release ! would not have been possible in this form and at this time, and the ! work on our 4.0 branch wouldn't be where it is today. <sect>Credits <p> --- 279,292 ---- <sect>Thanks <p> The XFree86 Project wants to express a special thanks to ! S.u.S.E. GmbH, Fuerth, Germany, for the long and successful ! cooperation over the last few years. S.u.S.E. GmbH at one point hired our ! Core Team member and Vice President Dirk Hohndel as an employee and ! allowed him to work more or less full time on XFree86 for almost nine ! months. S.u.S.E. continues to be a significant source of input and ! help to XFree86. This manifested itself in the XSuSE series of X ! servers that have all except for the GLINT server (due to unresolved ! legal issues) been integrated into XFree86 3.3.2. <sect>Credits <p> *************** *** 363,369 **** </itemize> <tag/LynxOS support by: / <itemize> ! <item>Thomas Mueller <it><tm@systrix.de></it> </itemize> <tag>OS/2 support by: </tag> <itemize> --- 384,390 ---- </itemize> <tag/LynxOS support by: / <itemize> ! <item>Thomas Mueller <it><tmueller@sysgo.de></it> </itemize> <tag>OS/2 support by: </tag> <itemize> *************** *** 385,393 **** <item>Naoki Katsurakawa <it><katsura@prc.tsukuba.ac.jp></it>, <item>Shuichiro Urata <it><s-urata@nmit.tmg.nec.co.jp></it>, <item>Yasuyuki Kato <it><yasuyuki@acaets0.anritsu.co.jp></it>, ! <item>Michio Jinbo <it><karl@pms.nagaokaut.ac.jp></it>, <item>Tatsuya Koike <it><koiket@focus.rim.or.jp></it>, ! <item>Koichiro Suzuki <it><ksuzuki@cc.tuat.ac.jp></it>, <item>Tsuyoshi Tamaki <it><tamaki@sail.t.u-tokyo.ac.jp></it>, <item>Isao Ohishi <it><ohishi@hf.rim.or.jp></it>, <item>Kohji Ohishi <it><atena@njk.co.jp></it>, --- 406,414 ---- <item>Naoki Katsurakawa <it><katsura@prc.tsukuba.ac.jp></it>, <item>Shuichiro Urata <it><s-urata@nmit.tmg.nec.co.jp></it>, <item>Yasuyuki Kato <it><yasuyuki@acaets0.anritsu.co.jp></it>, ! <item>Michio Jinbo <it><karl@spnet.ne.jp></it>, <item>Tatsuya Koike <it><koiket@focus.rim.or.jp></it>, ! <item>Koichiro Suzuki <it><s-koichi@nims.nec.co.jp></it>, <item>Tsuyoshi Tamaki <it><tamaki@sail.t.u-tokyo.ac.jp></it>, <item>Isao Ohishi <it><ohishi@hf.rim.or.jp></it>, <item>Kohji Ohishi <it><atena@njk.co.jp></it>, *************** *** 396,402 **** <item>Jun Sakuma <it><i931361@jks.is.tsukuba.ac.jp></it>, <item>Shuichi Ueno <it><uenos@ppp.bekkoame.or.jp></it>, <item>Ishida Kazuo <it><ishidakz@obp.cl.nec.co.jp></it>, ! <item>Takaaki Nomura <it><tnomura@sfc.keio.ac.jp></it>, <item>Tadaaki Nagao <it><nagao@cs.titech.ac.jp></it>, <item>Minoru Noda <it><mnoda@cv.tottori-u.ac.jp></it>, <item>Naofumi Honda <it><honda@Kururu.math.hokudai.ac.jp></it>, --- 417,423 ---- <item>Jun Sakuma <it><i931361@jks.is.tsukuba.ac.jp></it>, <item>Shuichi Ueno <it><uenos@ppp.bekkoame.or.jp></it>, <item>Ishida Kazuo <it><ishidakz@obp.cl.nec.co.jp></it>, ! <item>Takaaki Nomura <it><amadeus@yk.rim.or.jp></it>, <item>Tadaaki Nagao <it><nagao@cs.titech.ac.jp></it>, <item>Minoru Noda <it><mnoda@cv.tottori-u.ac.jp></it>, <item>Naofumi Honda <it><honda@Kururu.math.hokudai.ac.jp></it>, *************** *** 403,410 **** <item>Akio Morita <it><amorita@bird.scphys.kyoto-u.ac.jp></it>, <item>Takashi Sakamoto <it><sakamoto@yajima.kuis.kyoto-u.ac.jp></it>, <item>Yasuhiro Ichikawa <it><cs94006@mbox.sist.ac.jp></it>, ! <item>Kazunori Ueno <it><g540012@komaba.ecc.u-tokyo.ac.jp></it>, <item>Yasushi Suzuki <it><suz@d2.bs1.fc.nec.co.jp></it>, <item>Masato Yoshida (Contributor of PW805i support) </itemize> --- 424,436 ---- <item>Akio Morita <it><amorita@bird.scphys.kyoto-u.ac.jp></it>, <item>Takashi Sakamoto <it><sakamoto@yajima.kuis.kyoto-u.ac.jp></it>, <item>Yasuhiro Ichikawa <it><cs94006@mbox.sist.ac.jp></it>, ! <item>Kazunori Ueno <it><jagarl@creator.club.or.jp></it>, <item>Yasushi Suzuki <it><suz@d2.bs1.fc.nec.co.jp></it>, + <item>Satoshi Kimura <it><KFB03633@niftyserve.or.jp></it>, + <item>Kazuhiko Uno <it><Kazuhiko.Uno@softvision.co.jp></it>, + <item>Tomiharu Takigami <it><takigami@elsd.mt.nec.co.jp></it>, + <item>Tomomi Suzuki <it><suzuki@grelot.elec.ryukoku.ac.jp></it>, + <item>Toshihiko Yagi <it><j2297222@ed.kagu.sut.ac.jp></it>, <item>Masato Yoshida (Contributor of PW805i support) </itemize> *************** *** 467,473 **** <item>Simon Cooper <it><scooper@vizlab.rutgers.edu></it>, <item>Harm Hanemaayer <it><H.Hanemaayer@inter.nl.net></it>, <item>Bill Reynolds <it><bill@goshawk.lanl.gov></it>, ! <item>Corin Anderson <it><corina@bdc.cirrus.com></it> </itemize> <tag/Western Digital accelerated code by: / <itemize> --- 493,499 ---- <item>Simon Cooper <it><scooper@vizlab.rutgers.edu></it>, <item>Harm Hanemaayer <it><H.Hanemaayer@inter.nl.net></it>, <item>Bill Reynolds <it><bill@goshawk.lanl.gov></it>, ! <item>Corin Anderson <it><corina@the4cs.com></it> </itemize> <tag/Western Digital accelerated code by: / <itemize> *************** *** 517,523 **** <item>Per Lindqvist <it><pgd@compuram.bbt.se></it> and Doug Evans <it><dje@cygnus.com></it>. <item>Ported to X11R5 by Rik Faith <it><faith@cs.unc.edu></it>. ! <item>Rewritten by Marc La France <it><Marc.La-France@ualberta.ca></it> </itemize> <tag/WD90C24 support by:/ <itemize> --- 543,549 ---- <item>Per Lindqvist <it><pgd@compuram.bbt.se></it> and Doug Evans <it><dje@cygnus.com></it>. <item>Ported to X11R5 by Rik Faith <it><faith@cs.unc.edu></it>. ! <item>Rewritten by Marc Aurele La France <it><tsi@ualberta.ca></it> </itemize> <tag/WD90C24 support by:/ <itemize> *************** *** 548,554 **** <item>Hank Dietz <it><hankd@ecn.purdue.edu></it>, <item>Simon Cooper <it><scooper@vizlab.rutgers.edu></it>, <item>Harm Hanemaayer <it><H.Hanemaayer@inter.nl.net></it>, ! <item>Corin Anderson <it><corina@bdc.cirrus.com></it> </itemize> <tag/Cirrus CL64xx driver by: / <itemize> --- 574,580 ---- <item>Hank Dietz <it><hankd@ecn.purdue.edu></it>, <item>Simon Cooper <it><scooper@vizlab.rutgers.edu></it>, <item>Harm Hanemaayer <it><H.Hanemaayer@inter.nl.net></it>, ! <item>Corin Anderson <it><corina@the4cs.com></it> </itemize> <tag/Cirrus CL64xx driver by: / <itemize> *************** *** 849,855 **** --- 875,884 ---- <item><url url="http://www.infomagic.com/" name="InfoMagic">, Flagstaff, AZ <item>Daniel Kraemer + <item><url url="http://www.eni.net/" + name="Epoch Networks, Inc.">, Irvine, CA <item>Frank & Paige McCormick + <item>Internet Labs, Inc. <item>Linux International <item>Linux Support Team, Erlangen, Germany <item><url url="http://www.lunetix.de" *************** *** 899,905 **** Source patches are available to upgrade X11R6.3 PL2 from the X Consortium (now The Open Group) ! to XFree86 3.3.1. Binaries for many OSs are also available. The distribution is available from: <itemize> --- 928,934 ---- Source patches are available to upgrade X11R6.3 PL2 from the X Consortium (now The Open Group) ! to XFree86 3.3.2. Binaries for many OSs are also available. The distribution is available from: <itemize> *************** *** 1056,1074 **** which files you need to get to build your distribution. --> ! Ensure that you are getting XFree86 3.3.1 - some of these sites may archive older releases as well. Check the <htmlurl name="RELNOTES" url="RELNOTES.html"> to find which files you need to take from the archive. <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/README.sgml,v 3.75.2.24 1997/07/26 11:49:28 dawes Exp $ ! $TOG: README.sgml /main/33 1997/08/10 13:02:09 kaleb $ </verb> </article> --- 1085,1103 ---- which files you need to get to build your distribution. --> ! Ensure that you are getting XFree86 3.3.2 - some of these sites may archive older releases as well. Check the <htmlurl name="RELNOTES" url="RELNOTES.html"> to find which files you need to take from the archive. <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/README.sgml,v 3.75.2.33 1998/02/28 15:49:46 robin Exp $ ! $TOG: README.sgml /main/34 1998/03/06 16:42:04 kaleb $ </verb> </article> *** ./programs/Xserver/hw/xfree86/doc/sgml/S3.sgml@@/PUBLIC-LATEST Sat Jul 19 10:33:22 1997 --- xc/programs/Xserver/hw/xfree86/doc/sgml/S3.sgml Fri Mar 6 16:40:37 1998 *************** *** 3,15 **** <article> <title> Information for S3 Chipset Users <author>The XFree86 Project Inc. ! <date>15 January 1996 <toc> <sect> Supported hardware <p> The current S3 Server supports the following S3 chipsets: 911, 924, ! 801/805, 928, 732 (Trio32), 764 (Trio64), 864, 868, 964 and 968. The S3 server will also recognise the 866, but it has not been tested with this chipset. If you have any problems or success with these, please report it to us. --- 3,16 ---- <article> <title> Information for S3 Chipset Users <author>The XFree86 Project Inc. ! <date>27 February 1998 <toc> <sect> Supported hardware <p> The current S3 Server supports the following S3 chipsets: 911, 924, ! 801/805, 928, 732 (Trio32), 764, 765, 775, 785 (Trio64*), ! 864, 868, 964, 968 and M65 (Aurora64V+). The S3 server will also recognise the 866, but it has not been tested with this chipset. If you have any problems or success with these, please report it to us. *************** *** 757,762 **** --- 758,799 ---- mode and probing fails! + <sect>Hints for LCD configuration (S3 Aurora64V+) + <p> + If LCD is active the CRT will always output 1024x768 (or whatever is + the _physical_ LCD size) and smaller modes are zoomed to fit on the LCD + unless you specify Option "lcd_center" in the device section. + + The pixel clock for this physical size (e.g. 1024x768) mode... + <itemize> + <item>...can explicitly set in the config file (device section) with e.g. `Set_LCDClk 70' + (resulting 70 MHz pixel clock being used for all modes when LCD is on) + <item>...is taken from the _first_ mode in the modes line iff this mode's display size + is the same as the physical LCD size + <item>...the default LCD pixel clock of BIOS initialisation setup is used. + This value is output at server startup in the line `LCD size ...' + unless you're specifying a value using `Set_LCDClk ...' + </itemize> + + If LCD is _not_ active, the normal mode lines and pixel clocks + are used for the VGA output. + + Whenever you switch output sources with Fn-F5, + the Xserver won't get informed and pixel clock and other settings are wrong. + Because of this you have to switch modes _after_ switch output sources! + Then the server will check which outputs are active and select the correct + clocks etc. + So the recommended key sequence to switch output is + + Fn-F5 Ctrl-Alt-Plus Ctrl-Alt-Minus + + and everything should be ok.. + + on the Toshiba keypad you can first hold down Ctrl-Alt, then press `Fn' additionally + before pressing Plus/Minus too to avoid to explicitly enable/disable + the numeric keypad for mode switching. + + <sect> How to avoid ``snowing'' display while performing graphics operations <p> *************** *** 833,846 **** exit </code> <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/S3.sgml,v 3.37.2.1 1997/05/27 06:22:23 dawes Exp $ ! $TOG: S3.sgml /main/15 1997/07/19 10:33:25 kaleb $ </verb> </article> --- 870,933 ---- exit </code> + <sect>New S3 SVGA driver<p> + There is a new experimental S3 driver for + non-ViRGE S3 chipsets in the XF86_SVGA server. This is definitely + an ALPHA quality driver and hasn't been well tested, and has some known + problems. + Because of this, the configuration programs will install XF86_S3 by + default rather than this one. But if you're adventurous or had some + problems with XF86_S3, you might want to give it a try. + + The driver includes generic S3 support which should work on + all non-ViRGE S3 chips (in theory, that is). It also has improved + support for chips that support S3's new style memory mapped I/O. + These chips include the 868, 968 and recent Trio64 variants (not + the plain old Trio64s). Chips that are capable of using the new + style MMIO will use it automatically. The option "NO_MMIO" can + be used to turn this off. + + Performance for chips using the new style MMIO is expected + to be better than XF86_S3, especially on a PCI bus. Performance + without MMIO, however, is expected to be roughly comparable + to XF86_S3 (faster in some areas, slower in others). + + All color depths achievable with XF86_S3 should be possible + with these drivers. Additionally, packed 24 bpp "sort of" works + for the 868 and 968. Your results may vary. + + Nearly all the options and features supported by XF86_S3 + are supported by this driver. Additionally, the standard XAA/SVGA + server options such as NO_ACCEL, SW_CURSOR, and NO_PIXMAP_CACHE are + also supported. XF86_S3 features which are NOT supported in this + driver are DPMS support and gamma correction. + + The driver supports the PCI_RETRY option when using MMIO and + a PCI card. This option can give large performance boosts for + some operations, but has a tendency to hog the bus. Because + of this, the option is not set by default. Most hardware + combinations may not have any problems using this option, but + sound card glitches during intensive graphics operations have + been reported on some. + + One shortcoming worth noting is that this driver does not yet + contain the work-around for some S3 PCI BIOSs that report + their memory usage incorrectly. This can result in conflicting + address spaces. If this is the case on your hardware you should + run XF86_S3 once and write down the address that your card is + relocated to (as printed out in the server output). Then you can + force the server to use this address with the MemBase field in the + XF86Config (see the man page on XF86Config). + + <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/S3.sgml,v 3.37.2.4 1998/02/27 02:34:38 dawes Exp $ ! $TOG: S3.sgml /main/16 1998/03/06 16:42:15 kaleb $ </verb> </article> *** ./programs/Xserver/hw/xfree86/doc/sgml/S3V.sgml@@/PUBLIC-LATEST Sat Jul 19 10:33:30 1997 --- xc/programs/Xserver/hw/xfree86/doc/sgml/S3V.sgml Fri Mar 6 16:40:42 1998 *************** *** 1,28 **** <!DOCTYPE linuxdoc PUBLIC "-//XFree86//DTD linuxdoc//EN"> <article> ! <title> Information for S3 ViRGE, ViRGE/DX, ViRGE/GX and ViRGE/VX Users <author>The XFree86 Project Inc. ! <date>1 June 1997 <toc> <sect> Supported hardware <p> ! With release 3.3 of XFree86, there are now two servers which support ! the ViRGE family of chips. The XF86_S3V server (also available in 3.2A) is a dedicated server which supports the S3 ViRGE (86C325), the ViRGE/DX (86C375), ViRGE/GX (86C385) and the ViRGE/VX (86C988) chips. New with this release, the above ViRGE chipsets are also supported in the XF86_SVGA server, which includes a new ViRGE driver making use ! of the XAA acceleration architecture. <sect> XF86_S3V server <p> ! The S3V server has many enhancements and bug fixes since 3.2A. With the ! release of 3.3 you should find that the ViRGE server is stable at all depths. ! Supported for 24bpp has been enhanced. The server now supports 1 and 32 bpp ! pixmap formats (3.2A supported 1 and 24bpp pixmaps). ! This fixes known problems with xanim and Netscape clients in 3.2A. It has been tested with ViRGE cards with 2 and 4MB DRAM, ViRGE/DX 4M, ViRGE/VX 8M (4M VRAM/4M DRAM), and with a 220MHz ViRGE/VX card with 2MB VRAM up to 1600x1200 with 8/15/16bpp. --- 1,37 ---- <!DOCTYPE linuxdoc PUBLIC "-//XFree86//DTD linuxdoc//EN"> <article> ! <title> Information for S3 ViRGE, ViRGE/DX, ViRGE/GX, ViRGE/GX2, ! ViRGE/MX and ViRGE/VX Users <author>The XFree86 Project Inc. ! <date>1 March 1998 <toc> <sect> Supported hardware <p> ! With release 3.3.2 of XFree86, there are now two servers which support ! the ViRGE family of chips. The XF86_S3V server is a dedicated server which supports the S3 ViRGE (86C325), the ViRGE/DX (86C375), ViRGE/GX (86C385) and the ViRGE/VX (86C988) chips. New with this release, the above ViRGE chipsets are also supported in the XF86_SVGA server, which includes a new ViRGE driver making use ! of the XAA acceleration architecture and also supports ! ViRGE/GX2 (86C357) and ViRGE/MX (86C260) chips now. ! <p> ! The following sections describe details of ViRGE support. Be aware that ! there are two servers described. XF86_S3V is the ViRGE specific server ! and was created first. The new acceleration architecture support is found ! in the XF86_SVGA server using the s3_virge driver. Each has strengths and ! weaknesses. <sect> XF86_S3V server <p> ! The S3V server has some minor fixes since 3.3.1. ! You should find that the ViRGE server is stable at all depths. ! The server supports 1 and 32 bpp ! pixmap formats. ! This fixes known problems with xanim and Netscape clients in ! early versions of the S3V server. It has been tested with ViRGE cards with 2 and 4MB DRAM, ViRGE/DX 4M, ViRGE/VX 8M (4M VRAM/4M DRAM), and with a 220MHz ViRGE/VX card with 2MB VRAM up to 1600x1200 with 8/15/16bpp. *************** *** 93,100 **** It uses the XAA acceleration architecture for acceleration, and allows color depths of 8, 15, 16, 24 and 32 bpp. It has been tested on several 2MB and 4MB ViRGE cards, a 4MB ViRGE/DX card and a ViRGE/VX card. Resolutions ! of up to 1600x1200 have been achieved. As this is the first release of this ! driver, not everything may work as expected. Please report any problems to <htmlurl name="XFree86@Xfree86.org" url="mailto:XFree86@Xfree86.org"> using the appropriate bug report sheet. --- 102,109 ---- It uses the XAA acceleration architecture for acceleration, and allows color depths of 8, 15, 16, 24 and 32 bpp. It has been tested on several 2MB and 4MB ViRGE cards, a 4MB ViRGE/DX card and a ViRGE/VX card. Resolutions ! of up to 1600x1200 have been achieved. This is an early release of this ! driver, and not everything may work as expected. Please report any problems to <htmlurl name="XFree86@Xfree86.org" url="mailto:XFree86@Xfree86.org"> using the appropriate bug report sheet. *************** *** 102,108 **** <p> <itemize> ! <item>Supports PCI hardware, ViRGE, ViRGE/DX, ViRGE/GX and ViRGE/VX. <item>Supports 8bpp, 15/16bpp, 24bpp and 32bpp. <item>VT switching seems to work well, no corruption reported at all color depths. --- 111,118 ---- <p> <itemize> ! <item>Supports PCI hardware, ViRGE, ViRGE/DX, ViRGE/GX, ViRGE/GX2, ViRGE/MX ! and ViRGE/VX. <item>Supports 8bpp, 15/16bpp, 24bpp and 32bpp. <item>VT switching seems to work well, no corruption reported at all color depths. *************** *** 198,206 **** --- 208,255 ---- <item>32bpp uses STREAMS as well; however, because the ViRGE does not really support 32 bpp "natively", acceleration is quite limited. <item>Both 24bpp and 32bpp do not support interlace modes. + <item>32bpp is limited to a width of < 1024 pixels. (1024x768 is not possible, + even if you have the memory.) This is a hardware limit of ViRGE chips. </itemize> + <sect1>Hints for LCD configuration (S3 ViRGE/MX) + <p> + If LCD is active the CRT will always output 1024x768 (or whatever is + the _physical_ LCD size) and smaller modes are zoomed to fit on the LCD + unless you specify Option "lcd_center" in the device section. + + The pixel clock for this physical size (e.g. 1024x768) mode... + <itemize> + <item>...can explicitly set in the config file (device section) with e.g. `Set_LCDClk 70' + (resulting 70 MHz pixel clock being used for all modes when LCD is on) + <item>...is taken from the _first_ mode in the modes line iff this mode's display size + is the same as the physical LCD size + <item>...the default LCD pixel clock of BIOS initialisation setup is used. + This value is output at server startup in the line `LCD size ...' + unless you're specifying a value using `Set_LCDClk ...' + </itemize> + + If LCD is _not_ active, the normal mode lines and pixel clocks + are used for the VGA output. + + Whenever you switch output sources with Fn-F5 or similar, + the Xserver won't get informed and pixel clock and other settings are wrong. + Because of this you have to switch modes _after_ switch output sources! + Then the server will check which outputs are active and select the correct + clocks etc. + So the recommended key sequence to switch output is + + Fn-F5 Ctrl-Alt-Plus Ctrl-Alt-Minus + + and everything should be ok.. + + on the Toshiba keypad you can first hold down Ctrl-Alt, then press `Fn' additionally + before pressing Plus/Minus too to avoid to explicitly enable/disable + the numeric keypad for mode switching. + + + <sect>Authors <p> *************** *** 211,217 **** and: <itemize> ! <item>Kevin Brosius <it>70247.1640@compuserve.com</it> <item>Berry Dijk <it>berry_dijk@tasking.nl</it> <item>Dirk Hohndel <it>hohndel@XFree86.Org</it> <item>Huver Hu <it>huver@amgraf.com</it> --- 260,266 ---- and: <itemize> ! <item>Kevin Brosius <it>Cobra@compuserve.com</it> <item>Berry Dijk <it>berry_dijk@tasking.nl</it> <item>Dirk Hohndel <it>hohndel@XFree86.Org</it> <item>Huver Hu <it>huver@amgraf.com</it> *************** *** 225,235 **** and: ! Harald Koenig <it><koenig@tat.physik.uni-tuebingen.de></it> - <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/S3V.sgml,v 3.3.2.5 1997/06/02 01:44:14 dawes Exp $ </verb> </article> --- 274,286 ---- and: ! <itemize> ! <item>Harald Koenig <it><koenig@tat.physik.uni-tuebingen.de></it> ! <item>Kevin Brosius <it>Cobra@compuserve.com</it> ! </itemize> <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/S3V.sgml,v 3.3.2.8 1998/02/27 04:53:51 dawes Exp $ </verb> </article> *** ./programs/Xserver/hw/xfree86/doc/sgml/SOLX86.sgml@@/PUBLIC-LATEST Sat Jul 19 10:33:42 1997 --- xc/programs/Xserver/hw/xfree86/doc/sgml/SOLX86.sgml Fri Mar 6 16:40:46 1998 *************** *** 5,11 **** <title>Information for Solaris for x86 Users <author>David Holland ! <date>16 May 1997 <!-- Table of contents --> <toc> --- 5,11 ---- <title>Information for Solaris for x86 Users <author>David Holland ! <date>25 Feb 1998 <!-- Table of contents --> <toc> *************** *** 16,22 **** <!--Contents -------- ! 1) What is XFree86 3.3 2) Solaris versions on which XFree86 has been tested. 3) The VT-switching sub-system in Solaris x86 4) Various notes for building XFree86 on Solaris x86 --- 16,22 ---- <!--Contents -------- ! 1) What is XFree86 3.3.2 2) Solaris versions on which XFree86 has been tested. 3) The VT-switching sub-system in Solaris x86 4) Various notes for building XFree86 on Solaris x86 *************** *** 24,32 **** --> ! <sect>What is XFree86 3.3<p> ! XFree86 3.3 is a port of X11R6.3 that supports several versions of Intel-based Unix. It is derived from X386 1.2 which was the X server distributed with X11R5. This release consists of many new features and --- 24,32 ---- --> ! <sect>What is XFree86 3.3.2<p> ! XFree86 3.3.2 is a port of X11R6.3 that supports several versions of Intel-based Unix. It is derived from X386 1.2 which was the X server distributed with X11R5. This release consists of many new features and *************** *** 49,57 **** binaries. --> ! <sect> Solaris for x86, versions on which XFree86 3.3 has been tested<p> ! XFree86 3.3 has been actively tested on: <itemize> <!-- <item>Solaris 2.1 for x86 --- 49,57 ---- binaries. --> ! <sect> Solaris for x86, versions on which XFree86 3.3.2 has been tested<p> ! XFree86 3.3.2 has been actively tested on: <itemize> <!-- <item>Solaris 2.1 for x86 *************** *** 59,64 **** --- 59,65 ---- --> <item>Solaris 2.4 for x86 FCS <item>Solaris 2.5.1 for x86 + <item>Solaris 2.6 for x86 </itemize> And is expected to run under: <itemize> *************** *** 184,190 **** --> <item>Both Gcc, and ProWorks are supported by XFree86. Gcc-2.5.8 or ! gcc-2.7.2 are suggested, Gcc-2.6.0 is known not to work. You also need to set HasGcc2 correctly in <tt>~xc/config/cf/xf86site.def</tt>. --- 185,191 ---- --> <item>Both Gcc, and ProWorks are supported by XFree86. Gcc-2.5.8 or ! gcc-2.7.2.3 are suggested, Gcc-2.6.0 is known not to work. You also need to set HasGcc2 correctly in <tt>~xc/config/cf/xf86site.def</tt>. *************** *** 206,212 **** c++filt from GNU binutils. Don't install gas or ld from GNU binutils, use the one provided by Sun. <p> ! With XFree86 3.3, you will need to setup a /opt/SUNWspro/bin directory containing symbolic links named <tt/cc/, <tt/CC/, and <tt/c++filt/ pointing respectively to the actual <tt/gcc/, <tt/g++/ and <tt/c++filt/ commands. --- 207,213 ---- c++filt from GNU binutils. Don't install gas or ld from GNU binutils, use the one provided by Sun. <p> ! With XFree86 3.3.2, you will need to setup a /opt/SUNWspro/bin directory containing symbolic links named <tt/cc/, <tt/CC/, and <tt/c++filt/ pointing respectively to the actual <tt/gcc/, <tt/g++/ and <tt/c++filt/ commands. *************** *** 242,248 **** <tt>~xc/config/cf/xf86site.def</tt>.<p> to enable the aperture driver. ! Under Solaris 2.5 and 2.5.1, there's a system driver (<tt>/dev/xsvc</tt> that provides this functionality. It will be detected automatically by the server, so you don't need to install the driver. --- 243,249 ---- <tt>~xc/config/cf/xf86site.def</tt>.<p> to enable the aperture driver. ! Under Solaris 2.5 and later, there's a system driver (<tt>/dev/xsvc</tt> that provides this functionality. It will be detected automatically by the server, so you don't need to install the driver. *************** *** 329,340 **** <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/SOLX86.sgml,v 3.12.2.4 1997/05/24 08:36:08 dawes Exp $ ! $TOG: SOLX86.sgml /main/8 1997/07/19 10:33:44 kaleb $ </verb> </article> --- 330,341 ---- <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/SOLX86.sgml,v 3.12.2.6 1998/02/28 04:47:09 dawes Exp $ ! $TOG: SOLX86.sgml /main/9 1998/03/06 16:42:24 kaleb $ </verb> </article> *** ./programs/Xserver/hw/xfree86/doc/sgml/SVR4.sgml@@/PUBLIC-LATEST Sat Jul 19 10:33:48 1997 --- xc/programs/Xserver/hw/xfree86/doc/sgml/SVR4.sgml Fri Mar 6 16:40:51 1998 *************** *** 5,11 **** <title>Information for SVR4 Users <author>The XFree86 Project, Inc ! <date>1 June 1997 <abstract> <bf>NOTE:</bf> If you intend to use any of the accelerated servers, read section --- 5,11 ---- <title>Information for SVR4 Users <author>The XFree86 Project, Inc ! <date>27 Feb 1998 <abstract> <bf>NOTE:</bf> If you intend to use any of the accelerated servers, read section *************** *** 35,41 **** and the following versions of <bf>SVR4.2</bf>: <itemize> <item>Consensys ! <item>Novell UnixWare 1.x and 2.0 </itemize> Basically, we believe that XFree86 binaries will run unmodified on any ISA, EISA, or MCA platform version version of SVR4.0 (Solaris 2.x is an --- 35,41 ---- and the following versions of <bf>SVR4.2</bf>: <itemize> <item>Consensys ! <item>Novell/SCO UnixWare 1.x and 2.0 </itemize> Basically, we believe that XFree86 binaries will run unmodified on any ISA, EISA, or MCA platform version version of SVR4.0 (Solaris 2.x is an *************** *** 273,279 **** Unix-domain sockets in such a way that making local connections via <tt>UNIXCONN</tt> does not work properly (this bug is known to exist on Consensys ! SVR4.2 and Novell UnixWare). The manifestation of this bug is that windows remain on the screen after the client program exits, until you move the mouse into the window, or otherwise cause the server to try to write to the client.<p> --- 273,279 ---- Unix-domain sockets in such a way that making local connections via <tt>UNIXCONN</tt> does not work properly (this bug is known to exist on Consensys ! SVR4.2 and Novell/SCO UnixWare). The manifestation of this bug is that windows remain on the screen after the client program exits, until you move the mouse into the window, or otherwise cause the server to try to write to the client.<p> *************** *** 435,451 **** up the server on some versions of SVR4.0. The problem seems to be related to the kernel checking for the presence of physical memory when mmaping /dev/pmem. This can cause problems when mapping memory ! mapped registers. This is known to be a problem with the MGA driver in ! the SVGA server. Some other drivers may be affected too. We currently ! have no workaround for this. <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/SVR4.sgml,v 3.13.2.1 1997/06/01 12:33:36 dawes Exp $ ! $TOG: SVR4.sgml /main/9 1997/07/19 10:33:50 kaleb $ </verb> </article> --- 435,451 ---- up the server on some versions of SVR4.0. The problem seems to be related to the kernel checking for the presence of physical memory when mmaping /dev/pmem. This can cause problems when mapping memory ! mapped registers. This was known to be a problem with the MGA driver in ! the SVGA server. Some other drivers may be affected too. The problem with ! the MGA driver is now fixed. <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/SVR4.sgml,v 3.13.2.3 1998/02/28 08:54:11 dawes Exp $ ! $TOG: SVR4.sgml /main/10 1998/03/06 16:42:28 kaleb $ </verb> </article> *** ./programs/Xserver/hw/xfree86/doc/sgml/VGADriv.sgml@@/PUBLIC-LATEST Sat Jul 19 10:33:56 1997 --- xc/programs/Xserver/hw/xfree86/doc/sgml/VGADriv.sgml Fri Mar 6 16:40:59 1998 *************** *** 845,851 **** <sect> Vendor Contact Information <p> <descrip> ! <tag/ATI Technologies (VGA-Wonder, Mach8, Mach32) 33 Commerce Valley Drive East/ Thornhill, Ontario <newline> Canada L3T 7N6 <newline> --- 845,851 ---- <sect> Vendor Contact Information <p> <descrip> ! <tag/ATI Technologies (VGA-Wonder, Mach8, Mach32, Mach64) 33 Commerce Valley Drive East/ Thornhill, Ontario <newline> Canada L3T 7N6 <newline> *************** *** 904,916 **** </descrip> <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/VGADriv.sgml,v 3.13 1997/01/25 03:22:16 dawes Exp $ ! $TOG: VGADriv.sgml /main/10 1997/07/19 10:33:58 kaleb $ </verb> </article> --- 904,916 ---- </descrip> <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/VGADriv.sgml,v 3.13.2.1 1998/02/01 16:04:54 robin Exp $ ! $TOG: VGADriv.sgml /main/11 1998/03/06 16:42:36 kaleb $ </verb> </article> *** ./programs/Xserver/hw/xfree86/doc/sgml/VidModes.sgml@@/PUBLIC-LATEST Sat Jul 19 10:34:03 1997 --- xc/programs/Xserver/hw/xfree86/doc/sgml/VidModes.sgml Fri Mar 6 16:41:04 1998 *************** *** 1,66 **** <!DOCTYPE linuxdoc PUBLIC "-//XFree86//DTD linuxdoc//EN"> <article> - <title> The Hitchhiker's Guide to X386/XFree86 Video Timing - <subtitle>(or, Tweaking your Monitor for Fun and Profit) - <author> Eric S. Raymond <em/esr@snark.thyrsus.com/ - (from an original by Chin Fang <em/fangchin@leland.stanford.edu/; - portions derive from a how-to by Bob Crosson <em/crosson@cam.nist.gov/) - <date> - This is version 1.0, Jan 8th 1993. - </date> ! <toc> ! <sect> Introduction <p> ! Please direct comments, criticism, ! and suggestions for improvement to <em/esr@snark.thyrsus.com/. The XFree86 server allows users to configure their video subsystem and thus encourages best use of existing hardware. This tutorial is intended to help you learn how to generate your own timing numbers to make optimum use of your ! video card and monitor. We'll present a method for getting something that works, and then show you how you can experiment starting from that base to develop settings that optimize ! for your taste. If you already have a mode that almost works (in particular, if one of ! predefined VESA modes gives you a stable display but one that's displaced ! right or left, or too small, or too large) you can go straight to the section ! on Fixing Problems. This will enlighten you on ways to tweak the timing ! numbers to achieve particular effects. ! XFree86 allows you to hot-key between different modes defined in XF86Config ! (see XF86Config.man for details). Use this capability to save yourself ! hassles! When you want to test a new mode, give it a unique mode ! label and add it to the <em/end/ your hot-key list. Leave a known-good mode as the default to fall back on if the test mode ! doesn't work. The Xconfig section at the end of the second Example ! Calculation provides a good example of how to record your experiments ! in a way that will help you quickly converge on a solution. ! First check out the <tt/Monitors/ file in <tt>lib/X11/doc</tt> ! If your monitor is in it, you can probably skip the rest of this document! ! You may need to scale some of the timing numbers if the clock used to ! generate the mode in the database doesn't match what your card has available, ! but that's easy. ! ! <sect> How Video Displays Work <p> Knowing how the display works is essential to understanding what numbers to put in the various fields in the file Xconfig. Those values are used in the lowest ! levels of controlling the display by the XFree86 server. The display generates a picture from a series of dots. The dots are arranged from left to right to form lines. The lines are arranged from top to bottom to form the picture. The dots emit light when they are struck by the electron beam inside the display. To make the beam strike each dot for an equal amount ! of time, the beam is swept across the display in a constant pattern. The pattern starts at the top left of the screen, goes across the screen to the right in a straight line, and stops temporarily on the right side of the --- 1,103 ---- <!DOCTYPE linuxdoc PUBLIC "-//XFree86//DTD linuxdoc//EN"> + <!-- This is the Linux Distribution HOWTO, SGML source -- > + <!-- Eric S. Raymond, esr@snark.thyrsus.com -- > + <!-- The submission address is gregh@sunsite.unc.edu -- > + <article> ! <title>XFree86 Video Timings HOWTO ! <author>Eric S. Raymond <esr@thyrsus.com> ! <date>Version 3.0, 8 Aug 1997 + <abstract> + How to compose a mode line for your card/monitor combination under XFree86. + The XFree86 distribution now includes good facilities for configuring most + standard combinations; this document is mainly useful if you are tuning a + custom mode line for a high-performance monitor or very unusual hardware. + It may also help you in using xvidtune to tweak a standard mode that is + not quite right for your monitor. + </abstract> ! <toc> ! ! <sect>Disclaimer <p> ! You use the material herein SOLELY AT YOUR OWN RISK. It is possible ! to harm both your monitor and yourself when driving it outside the ! manufacturer's specs. Read <ref id="overd" name="Overdriving Your ! Monitor"> for detailed cautions. Any damages to you or your monitor ! caused by overdriving it are your problem. + The most up-to-date version of this HOWTO can be found at the <url + url="http://sunsite.unc.edu/LDP" + name="Linux Documentation Project"> web page. + + Please direct comments, criticism, and suggestions for improvement to + <htmlurl url="mailto:esr@thyrsus.com" name="esr@snark.thyrsus.com">. Please do + <em>not</em> send email pleading for a magic solution to your + special monitor problem, as doing so will only burn up my time and + frustrate you -- everything I know about the subject is already in + here. + + <sect>Introduction<label id="intro"> + <p> + The XFree86 server allows users to configure their video subsystem and thus encourages best use of existing hardware. This tutorial is intended to help you learn how to generate your own timing numbers to make optimum use of your ! video card and monitor. We'll present a method for getting something that works, and then show you how you can experiment starting from that base to develop settings that optimize ! for your taste. + Starting with XFree86 3.2, XFree86 provides an <bf>XF86Setup</bf>(1) + program that makes it easy to generate a working monitor mode + interactively, without messing with video timing number directly. So + you shouldn't actually need to calculate a base monitor mode in most + cases. Unfortunately, <bf>XF86Setup</bf>(1) has some limitations; it + only knows about standard video modes up to 1280x1024. If you have a + very high-performance monitor capable of 1600x1200 or more you will + still have to compute your base monitor mode yourself. + + Recent versions of XFree86 provide a tool called <bf>xvidtune</bf>(1) + which you will probably find quite useful for testing and tuning + monitor modes. It begins with a gruesome warning about the possible + consequences of mistakes with it. If you pay careful attention to + this document and learn what is behind the pretty numbers in + xvidtune's boxes, you will become able to use xvidtune effectively and + with confidence. + If you already have a mode that almost works (in particular, if one of ! predefined VESA modes gives you a stable display but one that's ! displaced right or left, or too small, or too large) you can go ! straight to the section on <ref id="fixes" name="Fixing Problems with the ! Image">. This will enlighten you on ways to tweak the timing ! numbers to achieve particular effects. ! If you have <bf>xvidtune</bf>(1), you'll be able to test new modes on the fly, ! without modifying your X configuration files or even rebooting your X server. ! Otherwise, XFree86 allows you to hot-key between different modes defined in ! Xconfig (see XFree86.man for details). Use this capability to save ! yourself hassles! When you want to test a new mode, give it a unique ! mode label and add it to the <EM>end</EM> of your hot-key list. Leave a known-good mode as the default to fall back on if the test mode ! doesn't work. ! <sect>How Video Displays Work<label id="video"> <p> Knowing how the display works is essential to understanding what numbers to put in the various fields in the file Xconfig. Those values are used in the lowest ! levels of controlling the display by the XFree86 server. The display generates a picture from a series of dots. The dots are arranged from left to right to form lines. The lines are arranged from top to bottom to form the picture. The dots emit light when they are struck by the electron beam inside the display. To make the beam strike each dot for an equal amount ! of time, the beam is swept across the display in a constant pattern. The pattern starts at the top left of the screen, goes across the screen to the right in a straight line, and stops temporarily on the right side of the *************** *** 68,79 **** one line. The new line is swept from left to right just as the first line was. This pattern is repeated until the bottom line on the display has been swept. Then the beam is moved from the bottom right corner of the display to the top ! left corner, and the pattern is started over again. Starting the beam at the top left of the display is called the beginning of a frame. The frame ends when the beam reaches the the top left corner again as it comes from the bottom right corner of the display. A frame is made up of ! all of the lines the beam traced from the top of the display to the bottom. If the electron beam were on all of the time it was sweeping through the frame, all of the dots on the display would be illuminated. There would be no black --- 105,120 ---- one line. The new line is swept from left to right just as the first line was. This pattern is repeated until the bottom line on the display has been swept. Then the beam is moved from the bottom right corner of the display to the top ! left corner, and the pattern is started over again. + There is one variation of this scheme known as interlacing: here only + every second line is swept during one half-frame and the others are filled in + in during a second half-frame. + Starting the beam at the top left of the display is called the beginning of a frame. The frame ends when the beam reaches the the top left corner again as it comes from the bottom right corner of the display. A frame is made up of ! all of the lines the beam traced from the top of the display to the bottom. If the electron beam were on all of the time it was sweeping through the frame, all of the dots on the display would be illuminated. There would be no black *************** *** 81,87 **** picture would become distorted because the beam is hard to control there. To reduce the distortion, the dots around the edges of the display are not illuminated by the beam even though the beam may be pointing at them. The ! viewable area of the display is reduced this way. Another important thing to understand is what becomes of the beam when no spot is being painted on the visible area. The time the beam would have been --- 122,128 ---- picture would become distorted because the beam is hard to control there. To reduce the distortion, the dots around the edges of the display are not illuminated by the beam even though the beam may be pointing at them. The ! viewable area of the display is reduced this way. Another important thing to understand is what becomes of the beam when no spot is being painted on the visible area. The time the beam would have been *************** *** 89,95 **** from the right edge to the left and moving the beam down to the next line. The time the beam would have been illuminating the top and bottom borders of the display is used for moving the beam from the bottom-right corner of the display ! to the top-left corner. The adapter card generates the signals which cause the display to turn on the electron beam at each dot to generate a picture. The card also controls when --- 130,136 ---- from the right edge to the left and moving the beam down to the next line. The time the beam would have been illuminating the top and bottom borders of the display is used for moving the beam from the bottom-right corner of the display ! to the top-left corner. The adapter card generates the signals which cause the display to turn on the electron beam at each dot to generate a picture. The card also controls when *************** *** 98,135 **** One horizontal sync pulse occurs at the end of every line. The adapter also generates a vertical sync pulse which signals the display to move the beam to the top-left corner of the display. A vertical sync pulse is generated near ! the end of every frame. The display requires that there be short time periods both before and after the horizontal and vertical sync pulses so that the position of the electron beam ! can stabilize. If the beam can't stabilize, the picture will not be steady. In a later section, we'll come back to these basics with definitions, ! formulas and examples to help you use them. ! <sect> Basic Things to Know about your Display and Adapter <p> There are some fundamental things you need to know before hacking an Xconfig ! entry. These are: ! <enum> <item>your monitor's horizontal and vertical sync frequency options <item>your video adapter's driving clock frequency, or "dot clock" <item>your monitor's bandwidth ! </enum> ! The monitor sync frequencies: ! ! The horizontal sync frequency are just the number of times per second the monitor can write a horizontal scan line; it is the single most important statistic about your monitor. The vertical sync frequency is the number of ! times per second the monitor can traverse its beam vertically. Sync frequencies are usually listed on the specifications page of your monitor manual. The vertical sync frequency number is typically calibrated in Hz (cycles per second), the horizontal one in KHz (kilocycles per second). The ! usual ranges are between 50 and 80Hz vertical, and between 31 and 135KHz ! horizontal. If you have a multisync monitor, these frequencies will be given as ranges. Some monitors, especially lower-end ones, have multiple fixed frequencies. --- 139,176 ---- One horizontal sync pulse occurs at the end of every line. The adapter also generates a vertical sync pulse which signals the display to move the beam to the top-left corner of the display. A vertical sync pulse is generated near ! the end of every frame. The display requires that there be short time periods both before and after the horizontal and vertical sync pulses so that the position of the electron beam ! can stabilize. If the beam can't stabilize, the picture will not be steady. In a later section, we'll come back to these basics with definitions, ! formulas and examples to help you use them. ! <sect>Basic Things to Know about your Display and Adapter<label id="basic"> <p> There are some fundamental things you need to know before hacking an Xconfig ! entry. These are: ! ! <itemize> <item>your monitor's horizontal and vertical sync frequency options <item>your video adapter's driving clock frequency, or "dot clock" <item>your monitor's bandwidth ! </itemize> ! The monitor sync frequencies: ! The horizontal sync frequency is just the number of times per second the monitor can write a horizontal scan line; it is the single most important statistic about your monitor. The vertical sync frequency is the number of ! times per second the monitor can traverse its beam vertically. Sync frequencies are usually listed on the specifications page of your monitor manual. The vertical sync frequency number is typically calibrated in Hz (cycles per second), the horizontal one in KHz (kilocycles per second). The ! usual ranges are between 50 and 150Hz vertical, and between 31 and 135KHz ! horizontal. If you have a multisync monitor, these frequencies will be given as ranges. Some monitors, especially lower-end ones, have multiple fixed frequencies. *************** *** 136,157 **** These can be configured too, but your options will be severely limited by the built-in monitor characteristics. Choose the highest frequency pair for best resolution. And be careful --- trying to clock a fixed-frequency monitor at a ! higher speed than it's designed for can damage it. ! The card driving clock frequency: Your video adapter manual's spec page will usually give you the card's dot clock (that is, the total number of pixels per second it can write to the screen). If you don't have this information, the X server will get it for you. Even if your X locks up your monitor, it will emit a line of clock and other info to standard output. If you redirect this to a file, it should be ! saved even if you have to reboot to get your console back. ! If you're using SGCS X, the line will look something like the following ! example, collected from a Swan local-bus S3 adapter. XFree86 uses a slightly ! different multi-line format. <tscreen><verb> WGA: 86C911 (mem: 1024k clocks: 25 28 40 3 50 77 36 45 0 0 79 31 94 65 75 71) --- ------ ----- -------------------------------------------- | | | Possible driving frequencies in MHz --- 177,243 ---- These can be configured too, but your options will be severely limited by the built-in monitor characteristics. Choose the highest frequency pair for best resolution. And be careful --- trying to clock a fixed-frequency monitor at a ! higher speed than it's designed for can easily damage it. ! Earlier versions of this guide were pretty cavalier about overdriving ! multisync monitors, pushing them past their nominal highest vertical ! sync frequency in order to get better performance. We have since had more ! reasons pointed out to us for caution on this score; we'll cover those under ! <ref id="overd" name="Overdriving Your Monitor"> below. + The card driving clock frequency: + Your video adapter manual's spec page will usually give you the card's dot clock (that is, the total number of pixels per second it can write to the screen). If you don't have this information, the X server will get it for you. Even if your X locks up your monitor, it will emit a line of clock and other info to standard output. If you redirect this to a file, it should be ! saved even if you have to reboot to get your console back. (Recent versions ! of the X servers all support a --probeonly option that prints out this ! information and exits without actually starting up X or changing the ! video mode.) ! Your X startup message should look something like one of the following ! examples: + If you're using XFree86: + <tscreen><verb> + Xconfig: /usr/X11R6/lib/X11/Xconfig + (**) stands for supplied, (--) stands for probed/default values + (**) Mouse: type: MouseMan, device: /dev/ttyS1, baudrate: 9600 + Warning: The directory "/usr/andrew/X11fonts" does not exist. + Entry deleted from font path. + (**) FontPath set to "/usr/lib/X11/fonts/misc/,/usr/lib/X11/fonts/75dpi/" + (--) S3: card type: 386/486 localbus + (--) S3: chipset: 924 + --- + Chipset -- this is the exact chip type; an early mask of the 86C911 + + (--) S3: chipset driver: s3_generic + (--) S3: videoram: 1024k + ----- + Size of on-board frame-buffer RAM + + (**) S3: clocks: 25.00 28.00 40.00 3.00 50.00 77.00 36.00 45.00 + (**) S3: clocks: 0.00 0.00 79.00 31.00 94.00 65.00 75.00 71.00 + ------------------------------------------------------ + Possible driving frequencies in MHz + + (--) S3: Maximum allowed dot-clock: 110MHz + ------ + Bandwidth + (**) S3: Mode "1024x768": mode clock = 79.000, clock used = 79.000 + (--) S3: Virtual resolution set to 1024x768 + (--) S3: Using a banksize of 64k, line width of 1024 + (--) S3: Pixmap cache: + (--) S3: Using 2 128-pixel 4 64-pixel and 8 32-pixel slots + (--) S3: Using 8 pages of 768x255 for font caching + </verb></tscreen> + + If you're using SGCS or X/Inside X: + + <tscreen><verb> WGA: 86C911 (mem: 1024k clocks: 25 28 40 3 50 77 36 45 0 0 79 31 94 65 75 71) --- ------ ----- -------------------------------------------- | | | Possible driving frequencies in MHz *************** *** 164,201 **** an application, its timing loops can collide with disk activity, rendering the numbers above inaccurate. Do it several times and watch for the numbers to stabilize; if they don't, start killing processes until they do. SVr4 users: ! the mousemgr process is particularly likely to mess you up. In order to avoid the clock-probe inaccuracy, you should clip out the clock timings and put them in your Xconfig as the value of the Clocks property --- this suppresses the timing loop and gives X an exact list of the clock values ! it can try. Using the data from the example above: <tscreen><verb> wga Clocks 25 28 40 3 50 77 36 45 0 0 79 31 94 65 75 71 </verb></tscreen> - On systems with a highly variable load, this may help you avoid mysterious X startup failures. It's possible for X to come up, get its timings wrong due to system load, and then not be able to find a matching dot clock in its ! config database --- or find the wrong one! ! The monitor's video bandwidth: ! Finally, it's useful to know your monitor's video bandwidth, so you know ! approximately what the highest dot clock you can use is. There's a lot of ! give here, though --- some monitors can run as much as 30&percnt over their nominal ! bandwidth. ! Knowing the bandwidth will enable you to make more intelligent choices between ! possible configurations. It may affect your display's visual quality (esp. ! sharpness for fine details). Your monitor's video bandwidth should be included on the manual's spec page. If it's not, look at the monitor's highest rated resolution. As a rule of thumb, here's how to translate these into bandwidth estimates (and thus into ! rough upper bounds for the dot clock you can use): <tscreen><verb> 640x480 25 --- 250,291 ---- an application, its timing loops can collide with disk activity, rendering the numbers above inaccurate. Do it several times and watch for the numbers to stabilize; if they don't, start killing processes until they do. SVr4 users: ! the mousemgr process is particularly likely to mess you up. In order to avoid the clock-probe inaccuracy, you should clip out the clock timings and put them in your Xconfig as the value of the Clocks property --- this suppresses the timing loop and gives X an exact list of the clock values ! it can try. Using the data from the example above: <tscreen><verb> wga Clocks 25 28 40 3 50 77 36 45 0 0 79 31 94 65 75 71 </verb></tscreen> On systems with a highly variable load, this may help you avoid mysterious X startup failures. It's possible for X to come up, get its timings wrong due to system load, and then not be able to find a matching dot clock in its ! config database --- or find the wrong one! ! <sect1>The monitor's video bandwidth: ! <p> ! If you're running XFree86, your server will probe your card and tell you ! what your highest-available dot clock is. ! Otherwise, your highest available dot clock is approximately the monitor's ! video bandwidth. There's a lot of give here, though --- some monitors ! can run as much as 30% over their nominal bandwidth. The risks here have ! to do with exceeding the monitor's rated vertical-sync frequency; we'll ! discuss them in detail below. + Knowing the bandwidth will enable you to make more intelligent choices + between possible configurations. It may affect your display's visual + quality (especially sharpness for fine details). + Your monitor's video bandwidth should be included on the manual's spec page. If it's not, look at the monitor's highest rated resolution. As a rule of thumb, here's how to translate these into bandwidth estimates (and thus into ! rough upper bounds for the dot clock you can use): <tscreen><verb> 640x480 25 *************** *** 203,218 **** 1024x768 65 1024x768 interlaced 45 1280x1024 110 </verb></tscreen> ! BTW, there's nothing magic about this table; these numbers are just the lowest ! dot clocks per resolution in the standard XFree86 Modes database. The bandwidth ! of your monitor may be higher than the minimum needed for its top resolution, ! so don't be afraid to try a dot clock a few MHz higher. ! Also note that bandwidth is seldom an issue for dot clocks under 65MHz or so. ! With an SVGA and most hi-res monitors, you can't get anywhere near the limit ! of your monitor's video bandwidth. The following are examples: <tscreen><verb> Brand Video Bandwidth --- 293,312 ---- 1024x768 65 1024x768 interlaced 45 1280x1024 110 + 1600x1200 185 </verb></tscreen> ! BTW, there's nothing magic about this table; these numbers are just ! the lowest dot clocks per resolution in the standard XFree86 Modes ! database (except for the last, which I interpolated). The bandwidth ! of your monitor may actually be higher than the minimum needed for its ! top resolution, so don't be afraid to try a dot clock a few MHz ! higher. ! Also note that bandwidth is seldom an issue for dot clocks under 65MHz ! or so. With an SVGA card and most hi-res monitors, you can't get ! anywhere near the limit of your monitor's video bandwidth. The ! following are examples: <tscreen><verb> Brand Video Bandwidth *************** *** 227,240 **** HP D1188A 100Mhz Philips SC-17AS 110Mhz Swan SW617 85Mhz </verb></tscreen> - Even low-end monitors usually aren't terribly bandwidth-constrained for their rated resolutions. The NEC Multisync II makes a good example --- it can't even display 800x600 per its spec. It can only display 800x560. For such low resolutions you don't need high dot clocks or a lot of bandwidth; probably the best you can do is 32Mhz or 36Mhz, both of them are still not too far from the ! monitor's rated video bandwidth of 30Mhz. At these two driving frequencies, your screen image may not be as sharp as it should be, but definitely of tolerable quality. Of course it would be nicer if --- 321,334 ---- HP D1188A 100Mhz Philips SC-17AS 110Mhz Swan SW617 85Mhz + Viewsonic 21PS 185Mhz </verb></tscreen> Even low-end monitors usually aren't terribly bandwidth-constrained for their rated resolutions. The NEC Multisync II makes a good example --- it can't even display 800x600 per its spec. It can only display 800x560. For such low resolutions you don't need high dot clocks or a lot of bandwidth; probably the best you can do is 32Mhz or 36Mhz, both of them are still not too far from the ! monitor's rated video bandwidth of 30Mhz. At these two driving frequencies, your screen image may not be as sharp as it should be, but definitely of tolerable quality. Of course it would be nicer if *************** *** 241,249 **** NEC Multisync II had a video bandwidth higher than, say, 36Mhz. But this is not critical for common tasks like text editing, as long as the difference is not so significant as to cause severe image distortion (your eyes would tell ! you right away if this were so). ! What these control: The sync frequency ranges of your monitor, together with your video adapter's dot clock, determine the ultimate resolution that you can use. But it's up to --- 335,344 ---- NEC Multisync II had a video bandwidth higher than, say, 36Mhz. But this is not critical for common tasks like text editing, as long as the difference is not so significant as to cause severe image distortion (your eyes would tell ! you right away if this were so). ! <sect1>What these control: ! <p> The sync frequency ranges of your monitor, together with your video adapter's dot clock, determine the ultimate resolution that you can use. But it's up to *************** *** 251,307 **** combination without an equally competent device driver is a waste of money. On the other hand, with a versatile device driver but less capable hardware, you can push the hardware's envelope a little. This is the design philosophy ! of XFree86. ! <sect> Interpreting the Basic Specifications <p> This section explains what the specifications above mean, and some other things you'll need to know. First, some definitions. Next to each in parens ! is the variable name we'll use for it when doing calculations <descrip> <tag/horizontal sync frequency (HSF)/ ! Horizontal scans per second (see above). ! <tag/vertical sync frequency (VSF)/ ! Vertical scans per second (see above). Mainly important as the upper ! limit on your refresh rate. ! <tag/dot clock (DCF)/ ! More formally, `driving clock frequency'; sometimes loosely called ! `bandwidth'. The frequency of the crystal or VCO on your adaptor --- the ! maximum dots-per-second it can emit. <tag/video bandwidth (VB)/ ! The highest frequency at which your monitor's video signal can change. ! This constrains the highest dot clock you can use and the overall sharpness ! of fine details in the video image. <tag/frame length (HFL, VFL)/ ! Horizontal frame length (HFL) is the number of dot-clock ticks needed for ! your monitor's electron gun to scan one horizontal line, *including the ! inactive left and right borders*. Vertical frame length (VFL) is the number ! of scan lines in the *entire* image, including the inactive top and bottom ! borders. <tag/screen refresh rate (RR)/ ! The number of times per second your screen is repainted. Higher frequencies ! are better, as they reduce flicker. 60Hz is good, VESA-standard 72Hz is ! better. Compute it as <tscreen><verb> RR = DCF / (HFL * VFL) </verb></tscreen> ! Note that the product in the denominator is *not* the same as the monitor's ! visible resolution, but typically somewhat larger. We'll get to the details ! of this below. </descrip> ! About Bandwidth: Monitor makers like to advertise high bandwidth because it constrains the sharpness of intensity and color changes on the screen. A high bandwidth ! means smaller visible details. Your monitor uses electronic signals to present an image to your eyes. Such signals always come in in wave form once they are converted --- 346,420 ---- combination without an equally competent device driver is a waste of money. On the other hand, with a versatile device driver but less capable hardware, you can push the hardware's envelope a little. This is the design philosophy ! of XFree86. ! <sect>Interpreting the Basic Specifications<label id="specs"> <p> This section explains what the specifications above mean, and some other things you'll need to know. First, some definitions. Next to each in parens ! is the variable name we'll use for it when doing calculations <descrip> <tag/horizontal sync frequency (HSF)/ ! Horizontal scans per second (see above). ! <tag/vertical sync frequency (VSF) / ! Vertical scans per second (see above). Mainly important as the upper ! limit on your refresh rate. ! <tag/dot clock (DCF)/ ! More formally, `driving clock frequency'; The frequency of the ! crystal or VCO on your adaptor --- the maximum dots-per-second it can ! emit. <tag/video bandwidth (VB)/ ! The highest frequency you can feed into your monitor's video ! input and still expect to see anything discernible. If your adaptor ! produces an alternating on/off pattern, its lowest frequency is half ! the DCF, so in theory bandwidth starts making sense at DCF/2. For ! tolerably crisp display of fine details in the video image, however, ! you don't want it much below your highest DCF, and preferably higher. <tag/frame length (HFL, VFL)/ ! Horizontal frame length (HFL) is the number of dot-clock ticks ! needed for your monitor's electron gun to scan one horizontal line, ! <em>including the inactive left and right borders</em>. Vertical ! frame length (VFL) is the number of scan lines in the ! <em>entire</em> image, including the inactive top and bottom ! borders. <tag/screen refresh rate (RR)/ ! The number of times per second your screen is repainted (this is ! also called "frame rate"). Higher frequencies are better, as they ! reduce flicker. 60Hz is good, VESA-standard 72Hz is better. ! Compute it as <tscreen><verb> RR = DCF / (HFL * VFL) </verb></tscreen> ! ! Note that the product in the denominator is <em>not</em> the same ! as the monitor's visible resolution, but typically somewhat larger. ! We'll get to the details of this below. ! ! The rates for which interlaced modes are usually specified (like 87Hz ! interlaced) are actually the half-frame rates: an entire screen seems ! to have about that flicker frequency for typical displays, but every ! single line is refreshed only half as often. ! ! For calculation purposes we reckon an interlaced display at its ! full-frame (refresh) rate, i.e. 43.5Hz. The quality of an interlaced ! mode is better than that of a non-interlaced mode with the same ! full-frame rate, but definitely worse then the non-interlaced one ! corresponding to the half-frame rate. </descrip> ! <sect1>About Bandwidth: ! <p> Monitor makers like to advertise high bandwidth because it constrains the sharpness of intensity and color changes on the screen. A high bandwidth ! means smaller visible details. Your monitor uses electronic signals to present an image to your eyes. Such signals always come in in wave form once they are converted *************** *** 309,320 **** of many simpler wave forms each one of which has a fixed frequency, many of them are in the Mhz range, eg, 20Mhz, 40Mhz, or even 70Mhz. Your monitor video bandwidth is, effectively, the highest-frequency analog signal it can ! handle without distortion. For our purposes, bandwidth is mainly important as an approximate cutoff point ! for the highest dot clock you can use. ! Sync Frequencies snd the Refresh Rate: Each horizontal scan line on the display is just the visible portion of a frame-length scan. At any instant there is actually only one dot active on --- 422,434 ---- of many simpler wave forms each one of which has a fixed frequency, many of them are in the Mhz range, eg, 20Mhz, 40Mhz, or even 70Mhz. Your monitor video bandwidth is, effectively, the highest-frequency analog signal it can ! handle without distortion. For our purposes, bandwidth is mainly important as an approximate cutoff point ! for the highest dot clock you can use. ! <sect1>Sync Frequencies and the Refresh Rate: ! <p> Each horizontal scan line on the display is just the visible portion of a frame-length scan. At any instant there is actually only one dot active on *************** *** 321,354 **** the screen, but with a fast enough refresh rate your eye's persistence of vision enables you to "see" the whole image. ! Here are some pictures to help: ! <tscreen><verb> ! _______________________ ! | | The horizontal frame length ! |->->->->->->->->->->-> | is the time in dot clocks ! | )| required for the ! |<-----<-----<-----<--- | electron beam to trace ! | | a pattern like this ! | | ! | | ! | | ! |_______________________| ! ! _______________________ ! | ^ | The vertical frame length ! | ^ | | is the time in dot clocks ! | | v | required for the ! | ^ | | electron beam to trace ! | | | | a pattern like this ! | ^ | | ! | | v | ! | ^ | | ! |_______|_v_____________| ! </verb></tscreen> ! Remember that the actual raster scan is a very tight zigzag pattern; that is, ! the beam moves left <-> right and at the same time up <-> down. Now we can see how the dot clock and frame size relates to refresh rate. By definition, one hertz (hz) is one cycle per second. So, if your horizontal --- 435,467 ---- the screen, but with a fast enough refresh rate your eye's persistence of vision enables you to "see" the whole image. ! Here are some pictures to help: ! <code> ! _______________________ ! | | The horizontal sync frequency ! |->->->->->->->->->->-> | is the number of times per ! | )| second that the monitor's ! |<-----<-----<-----<--- | electron beam can trace ! | | a pattern like this ! | | ! | | ! | | ! |_______________________| ! _______________________ ! | ^ | The vertical sync frequency ! | ^ | | is the number of times per ! | | v | second that the monitor's ! | ^ | | electron beam can trace ! | | | | a pattern like this ! | ^ | | ! | | v | ! | ^ | | ! |_______|_v_____________| ! </code> ! Remember that the actual raster scan is a very tight zigzag pattern; that is, ! the beam moves left-right and at the same time up-down. Now we can see how the dot clock and frame size relates to refresh rate. By definition, one hertz (hz) is one cycle per second. So, if your horizontal *************** *** 357,416 **** second by definition, then obviously your monitor's electron gun(s) can sweep the screen from left to right and back and from bottom to top and back DCF / (HFL * VFL) times/sec. This is your screen's refresh rate, because it's how ! many times your screen can be updated thus REFRESHED per second! You need to understand this concept to design a configuration which trades off ! resolution against flicker in whatever way suits your needs. ! <sect> Tradeoffs in Configuring your System <p> ! Another way to look at the formula we derived above is <tscreen><verb> DCF = RR * HFL * VFL </verb></tscreen> That is, your dot clock is fixed. You can use those dots per second to buy either refresh rate, horizontal resolution, or vertical resolution. If one ! of those increases, one or both of the others must decrease. Note, though, that your refresh rate cannot be greater than the maximum vertical sync frequency of your monitor. Thus, for any given monitor at a given dot clock, there is a minimum product of frame lengths below which you ! can't force it. In choosing your settings, remember: if you set RR too low, you will get ! mugged by screen flicker. You probably do not want to pull your refresh rate below 60Hz. This is the flicker rate of fluorescent lights; if you're sensitive to those, you need ! to hang with 72MHz, the VESA ergonomic standard. Flicker is very eye-fatiguing, though human eyes are adaptable and peoples' ! tolerance for it varies widely. If you face your monitor at a 90&percnt viewing angle, are using a dark background and a good contrasting color for foreground, and stick with low to medium intensity, you *may* be comfortable ! at as little as 45Hz. The acid test is this: open a xterm with pure white back-ground and black ! foreground using xterm -bg white -fg black and make it so large as to cover the ! entire viewable area. Now turn your monitor's intensity to 3/4 of its maximum ! setting, and turn your face away from the monitor. Try peeking at your monitor ! sideways (bringing the more sensitive peripheral-vision cells into play). If ! you don't sense any flicker or if you feel the flickering is tolerable, then ! that refresh rate is fine with you. Otherwise you better configure a higher ! refresh rate, because that semi-invisible flicker is going to fatigue your eyes ! like crazy and give you headaches, even if the screen looks OK to normal ! vision. So let's say you've picked a minimum acceptable refresh rate. In choosing ! your HFL and VFL, you'll have some room for maneuver. ! <sect>Memory Requirements <p> Available frame-buffer RAM may limit the resolution you can achieve on color or gray-scale displays. It probably isn't a factor on displays that have only two ! colors, white and black with no shades of gray in between. For 256-color displays, a byte of video memory is required for each visible dot to be shown. This byte contains the information that determines what mix --- 470,586 ---- second by definition, then obviously your monitor's electron gun(s) can sweep the screen from left to right and back and from bottom to top and back DCF / (HFL * VFL) times/sec. This is your screen's refresh rate, because it's how ! many times your screen can be updated (thus <em>refreshed</em>) per second! You need to understand this concept to design a configuration which trades off ! resolution against flicker in whatever way suits your needs. ! For those of you who handle visuals better than text, here is one: ! ! <code> ! RR VB ! | min HSF max HSF | ! | | R1 R2 | | ! max VSF -+----|------------/----------/---|------+----- max VSF ! | |:::::::::::/::::::::::/:::::\ | ! | \::::::::::/::::::::::/:::::::\ | ! | |::::::::/::::::::::/:::::::::| | ! | |:::::::/::::::::::/::::::::::\ | ! | \::::::/::::::::::/::::::::::::\ | ! | \::::/::::::::::/::::::::::::::| | ! | |::/::::::::::/:::::::::::::::| | ! | \/::::::::::/:::::::::::::::::\| ! | /\:::::::::/:::::::::::::::::::| ! | / \:::::::/::::::::::::::::::::|\ ! | / |:::::/:::::::::::::::::::::| | ! | / \::::/::::::::::::::::::::::| \ ! min VSF -+----/-------\--/-----------------------|--\--- min VSF ! | / \/ | \ ! +--/----------/\------------------------+----\- DCF ! R1 R2 \ | \ ! min HSF | max HSF ! VB ! </code> ! ! This is a generic monitor mode diagram. The x axis of the diagram ! shows the clock rate (DCF), the y axis represents the refresh rate ! (RR). The filled region of the diagram describes the monitor's ! capabilities: every point within this region is a possible video ! mode. ! ! The lines labeled `R1' and `R2' represent a fixed resolutions (such as ! 640x480); they are meant to illustrate how one resolution can be realized ! by many different combinations of dot clock and refresh rate. The R2 ! line would represent a higher resolution than R1. ! ! The top and bottom boundaries of the permitted region are simply ! horizontal lines representing the limiting values for the vertical sync ! frequency. The video bandwidth is an upper limit to the clock rate and ! hence is represented by a vertical line bounding the capability region on ! the right. ! ! Under <ref id="cplot" name="Plotting Monitor Capabilities">) you'll ! find a program that will help you plot a diagram like ! this (but much nicer, with X graphics) for your individual monitor. ! That section also discusses the interesting part; the derivation of ! the boundaries resulting from the limits on the horizontal sync ! frequency. ! ! <sect>Tradeoffs in Configuring your System<label id="trade"> <p> ! Another way to look at the formula we derived above is ! <tscreen><verb> DCF = RR * HFL * VFL </verb></tscreen> That is, your dot clock is fixed. You can use those dots per second to buy either refresh rate, horizontal resolution, or vertical resolution. If one ! of those increases, one or both of the others must decrease. Note, though, that your refresh rate cannot be greater than the maximum vertical sync frequency of your monitor. Thus, for any given monitor at a given dot clock, there is a minimum product of frame lengths below which you ! can't force it. In choosing your settings, remember: if you set RR too low, you will get ! mugged by screen flicker. You probably do not want to pull your refresh rate below 60Hz. This is the flicker rate of fluorescent lights; if you're sensitive to those, you need ! to hang with 72Hz, the VESA ergonomic standard. Flicker is very eye-fatiguing, though human eyes are adaptable and peoples' ! tolerance for it varies widely. If you face your monitor at a 90% viewing angle, are using a dark background and a good contrasting color for foreground, and stick with low to medium intensity, you *may* be comfortable ! at as little as 45Hz. The acid test is this: open a xterm with pure white back-ground and black ! foreground using <TT>xterm -bg white -fg black</TT> and make it so large as ! to cover the entire viewable area. Now turn your monitor's intensity to 3/4 of ! its maximum setting, and turn your face away from the monitor. Try peeking at ! your monitor sideways (bringing the more sensitive peripheral-vision cells into ! play). If you don't sense any flicker or if you feel the flickering is ! tolerable, then that refresh rate is fine with you. Otherwise you better ! configure a higher refresh rate, because that semi-invisible flicker is going ! to fatigue your eyes like crazy and give you headaches, even if the screen ! looks OK to normal vision. + For interlaced modes, the amount of flicker depends on more factors + such as the current vertical resolution and the actual screen + contents. So just experiment. You won't want to go much below about + 85Hz half frame rate, though. + So let's say you've picked a minimum acceptable refresh rate. In choosing ! your HFL and VFL, you'll have some room for maneuver. ! <sect>Memory Requirements<label id="sizes"> <p> Available frame-buffer RAM may limit the resolution you can achieve on color or gray-scale displays. It probably isn't a factor on displays that have only two ! colors, white and black with no shades of gray in between. For 256-color displays, a byte of video memory is required for each visible dot to be shown. This byte contains the information that determines what mix *************** *** 419,459 **** visible lines. For a display with a resolution of 800x600, this would be 800 x 600 = 480,000, which is the number of visible dots on the display. This is also, at one byte per dot, the number of bytes of video memory that are ! necessary on your adapter card. Thus, your memory requirement will typically be (HR * VR)/1024 Kbytes of VRAM, ! rounded up. In the example case, we'd need (936 * 702)/1024 = 642K. So if ! you have one meg, you'll have extra for virtual-screen panning. ! However, if you only have 512K on board, then you can't use this resolution. ! Even if you have a good monitor, without enough video ram, you can't take ! advantage of your monitor's potential. On the other hand, if your SVGA has one ! meg, but your monitor can display at most 800x600, then high resolution is ! beyond your reach anyway. ! Don't worry if you have more memory than required; XFree86 will make use of it by ! allowing you to scroll your viewable area (see the Xconfig file documentation ! on the virtual screen size parameter). Remember also that a card with 512K ! bytes of memory really doesn't have 512,000 bytes installed, it has 512 x 1024 ! = 524,288 bytes. ! If you're running SGCS X using an S3 card, and are willing to live with 16 ! colors (4 bits per pixel), you can set depth 4 in Xconfig and effectively double ! the resolution your card can handle. S3 cards, for example, normally do ! 1024x768x256. You can make them do 1280x1024x16 with depth 4. ! <sect>Computing Frame Sizes <p> Warning: this method was developed for multisync monitors. It will probably ! work with fixed-frequency monitors as well, but no guarantees! ! Start by dividing DCF by your highest available HSF to get the number ! of horizontal sweeps per second available. For example; suppose you have a Sigma Legend SVGA with a 65MHz dot clock, and your monitor has a 55KHz horizontal scan frequency. The quantity (DCF / HSF) ! is then 1181. Now for our first bit of black magic. You need to round this figure to the nearest multiple of 8. This has to do with the VGA hardware controller used by --- 589,632 ---- visible lines. For a display with a resolution of 800x600, this would be 800 x 600 = 480,000, which is the number of visible dots on the display. This is also, at one byte per dot, the number of bytes of video memory that are ! necessary on your adapter card. Thus, your memory requirement will typically be (HR * VR)/1024 Kbytes of VRAM, ! rounded up. If you have more memory than strictly required, you'll have extra ! for virtual-screen panning. ! However, if you only have 512K on board, then you can't use this ! resolution. Even if you have a good monitor, without enough video ! RAM, you can't take advantage of your monitor's potential. On the ! other hand, if your SVGA has one meg, but your monitor can display at ! most 800x600, then high resolution is beyond your reach anyway (see ! <ref id="inter" name="Using Interlaced Modes"> for a possible ! remedy). ! Don't worry if you have more memory than required; XFree86 will make ! use of it by allowing you to scroll your viewable area (see the ! Xconfig file documentation on the virtual screen size parameter). ! Remember also that a card with 512K bytes of memory really doesn't ! have 512,000 bytes installed, it has 512 x 1024 = 524,288 bytes. ! If you're running SGCS X (now called X/Inside) using an S3 card, and ! are willing to live with 16 colors (4 bits per pixel), you can set ! depth 4 in Xconfig and effectively double the resolution your card can ! handle. S3 cards, for example, normally do 1024x768x256. You can ! make them do 1280x1024x16 with depth 4. ! <sect>Computing Frame Sizes<label id="frame"> <p> Warning: this method was developed for multisync monitors. It will probably ! work with fixed-frequency monitors as well, but no guarantees! ! Start by dividing DCF by your highest available HSF to get a horizontal ! frame length. For example; suppose you have a Sigma Legend SVGA with a 65MHz dot clock, and your monitor has a 55KHz horizontal scan frequency. The quantity (DCF / HSF) ! is then 1181 (65MHz = 65000KHz; 65000/55 = 1181). Now for our first bit of black magic. You need to round this figure to the nearest multiple of 8. This has to do with the VGA hardware controller used by *************** *** 460,553 **** SVGA and S3 cards; it uses an 8-bit register, left-shifted 3 bits, for what's really an 11-bit quantity. Other card types such as ATI 8514/A may not have this requirement, but we don't know and the correction can't hurt. So round ! the usable horizontal scans per second figure to 1176. This figure (DCF / HSF rounded to a multiple of 8) is the minimum HFL you can use. You can get longer HFLs (and thus, possibly, more horizontal dots on the screen) by setting the sync pulse to produce a lower HSF. But you'll pay with ! a slower and more visible flicker rate. ! As a rule of thumb, 80&percnt of the horizontal frame length is available for horizontal resolution, the visible part of the horizontal scan line (this allows, roughly, for borders and sweepback time -- that is, the time required for the beam to move from the right screen edge to the left edge of the next ! raster line). In this example, that's 944 ticks. Now, to get the normal 4:3 screen aspect ratio, set your vertical resolution to 3/4ths of the horizontal resolution you just calculated. For this example, that's 708 ticks. To get your actual VFL, multiply that by 1.05 ! to get 743 ticks. ! About that 4:3 --- a ratio of 4:3 for width to height of the displayed area ! approximates the Golden Section, (1 + sqrt(5))/2. Human beings seem to be ! wired to find this kind of rectangle pleasant to look at; accordingly, video ! tubes and the standard resolutions such as 800x600, 640x480 and 1024x768 all ! approximate it. Though it's psychologically magic, it's not technically ! magic; nothing prevents you from using a non-Golden-Section ratio if that ! will get the best use out of your screen real estate. So, HFL=1176 and VFL=743. Dividing 65MHz by the product of the two gives us a nice, healthy 74.4Hz refresh rate. Excellent! Better than VESA standard! And you got 944x708 to boot, more than the 800 by 600 you were probably ! expecting. Not bad at all! You can even improve the refresh rate further, to almost 76 Hz, by using the ! fact that monitors can often sync horizontally at 2khz or so higher than ! rated, and by lowering VFL somewhat (that is, taking less than 75&percnt of 944 in ! the example above). But before you try this "overdriving" maneuver, if you ! do, make *sure* that your monitor electron guns can sync up to 76 Hz vertical. ! (the popular NEC 4D, for instance, cannot. It goes only up to 75 Hz VSF). So far, most of this is simple arithmetic and basic facts about raster ! displays. Hardly any black magic at all! ! <sect> Black Magic and Sync Pulses <p> OK, now you've computed HFL/VFL numbers for your chosen dot clock, found the refresh rate acceptable, and checked that you have enough VRAM. Now for the real black magic -- you need to know when and where to place synchronization ! pulses. The sync pulses actually control the horizontal and vertical scan frequencies of the monitor. The HSF and VSF you've pulled off the spec sheet are nominal, approximate maximum sync frequencies. The sync pulse in the signal from the ! adapter card tells the monitor how fast to actually run. Recall the two pictures above? Only part of the time required for raster-scanning a frame is used for displaying viewable image (ie. your ! resolution). ! Horizontal Sync: By previous definition, it takes HFL ticks to trace the a horizontal scan line. Let's call the visible tick count (your horizontal screen resolution) HR. Then ! Obviously, HR < HFL by definition. For concreteness, let's assume both start ! at the same instant as shown below: ! ! <tscreen><verb> ! ! |___ __ __ __ __ __ __ __ __ __ __ __ __ ! |_ _ _ _ _ _ _ _ _ _ _ _ | ! |_______________________|_______________|_____ ! 0 ^ ^ unit: ticks ! | ^ ^ | ! HR | | HFL ! | |<----->| | ! |<->| HSP |<->| ! HGT1 HGT2 ! ! </verb></tscreen> Now, we would like to place a sync pulse of length HSP as shown above, ie, between the end of clock ticks for display data and the end of clock ticks for the entire frame. Why so? because if we can achieve this, then your screen image won't shift to the right or to the left. It will be where it supposed to ! be on the screen, covering squarely the monitor's viewable area. Furthermore, we want about 30 ticks of "guard time" on either side of the sync pulse. This is represented by HGT1 and HGT2. In a typical configuration HGT1 != HGT2, but if you're building a configuration from scratch, you want to start ! your experimentation with them equal (that is, with the sync pulse centered). The symptom of a misplaced sync pulse is that the image is displaced on the screen, with one border excessively wide and the other side of the image --- 633,725 ---- SVGA and S3 cards; it uses an 8-bit register, left-shifted 3 bits, for what's really an 11-bit quantity. Other card types such as ATI 8514/A may not have this requirement, but we don't know and the correction can't hurt. So round ! the usable horizontal frame length figure down to 1176. This figure (DCF / HSF rounded to a multiple of 8) is the minimum HFL you can use. You can get longer HFLs (and thus, possibly, more horizontal dots on the screen) by setting the sync pulse to produce a lower HSF. But you'll pay with ! a slower and more visible flicker rate. ! As a rule of thumb, 80% of the horizontal frame length is available for horizontal resolution, the visible part of the horizontal scan line (this allows, roughly, for borders and sweepback time -- that is, the time required for the beam to move from the right screen edge to the left edge of the next ! raster line). In this example, that's 944 ticks. Now, to get the normal 4:3 screen aspect ratio, set your vertical resolution to 3/4ths of the horizontal resolution you just calculated. For this example, that's 708 ticks. To get your actual VFL, multiply that by 1.05 ! to get 743 ticks. ! The 4:3 is not technically magic; nothing prevents you from using a ! non-Golden-Section ratio if that will get the best use out of your ! screen real estate. It does make figuring frame height and frame ! width from the diagonal size convenient, you just multiply the ! diagonal by by 0.8 to get width and 0.6 to get height. So, HFL=1176 and VFL=743. Dividing 65MHz by the product of the two gives us a nice, healthy 74.4Hz refresh rate. Excellent! Better than VESA standard! And you got 944x708 to boot, more than the 800 by 600 you were probably ! expecting. Not bad at all! You can even improve the refresh rate further, to almost 76 Hz, by using the ! fact that monitors can often sync horizontally at 2khz or so higher than rated, ! and by lowering VFL somewhat (that is, taking less than 75% of 944 in the ! example above). But before you try this "overdriving" maneuver, if you do, ! make <em>sure</em> that your monitor electron guns can sync up to 76 Hz ! vertical. (the popular NEC 4D, for instance, cannot. It goes only up to 75 Hz ! VSF). (See <ref id="overd" name="Overdriving Your Monitor"> for more general ! discussion of this issue. ) So far, most of this is simple arithmetic and basic facts about raster ! displays. Hardly any black magic at all! ! <sect>Black Magic and Sync Pulses<label id="magic"> <p> + OK, now you've computed HFL/VFL numbers for your chosen dot clock, found the refresh rate acceptable, and checked that you have enough VRAM. Now for the real black magic -- you need to know when and where to place synchronization ! pulses. The sync pulses actually control the horizontal and vertical scan frequencies of the monitor. The HSF and VSF you've pulled off the spec sheet are nominal, approximate maximum sync frequencies. The sync pulse in the signal from the ! adapter card tells the monitor how fast to actually run. Recall the two pictures above? Only part of the time required for raster-scanning a frame is used for displaying viewable image (ie. your ! resolution). ! <sect1>Horizontal Sync: ! <p> By previous definition, it takes HFL ticks to trace the a horizontal scan line. Let's call the visible tick count (your horizontal screen resolution) HR. Then ! Obviously, HR < HFL by definition. For concreteness, let's assume both start ! at the same instant as shown below: ! <code> ! |___ __ __ __ __ __ __ __ __ __ __ __ __ ! |_ _ _ _ _ _ _ _ _ _ _ _ | ! |_______________________|_______________|_____ ! 0 ^ ^ unit: ticks ! | ^ ^ | ! HR | | HFL ! | |<----->| | ! |<->| HSP |<->| ! HGT1 HGT2 ! </code> Now, we would like to place a sync pulse of length HSP as shown above, ie, between the end of clock ticks for display data and the end of clock ticks for the entire frame. Why so? because if we can achieve this, then your screen image won't shift to the right or to the left. It will be where it supposed to ! be on the screen, covering squarely the monitor's viewable area. Furthermore, we want about 30 ticks of "guard time" on either side of the sync pulse. This is represented by HGT1 and HGT2. In a typical configuration HGT1 != HGT2, but if you're building a configuration from scratch, you want to start ! your experimentation with them equal (that is, with the sync pulse centered). The symptom of a misplaced sync pulse is that the image is displaced on the screen, with one border excessively wide and the other side of the image *************** *** 554,657 **** wrapped around the screen edge, producing a white edge line and a band of "ghost image" on that side. A way-out-of-place vertical sync pulse can actually cause the image to roll like a TV with a mis-adjusted vertical hold ! (in fact, it's the same phenomenon at work). If you're lucky, your monitor's sync pulse widths will be documented on its ! specification page. If not, here's where the real black magic starts&hellip You'll have to do a little trial and error for this part. But most of the time, we can safely assume that a sync pulse is about 3.5 to 4.0 microsecond ! in length. For concreteness again, let's take HSP to be 3.8 microseconds (which btw, is not ! a bad value to start with when experimenting). Now, using the 65Mhz clock timing above, we know HSP is equivalent to 247 clock ! ticks (= 65x10**6 * 3.8 *10**(-6)) ! [recall M=10**6, micro=10**(-6)] ! Vertical Sync: Going back to the picture above, how do we place the 247 clock ticks as shown ! in the picture? Using our example, HR is 944 and HFL is 1176. The difference between the two ! is 1176-944=232 < 247! Obviously we have to do some adjustment here. What can ! we do? The first thing is to raise 1176 to 1184, and lower 944 to 936. Now the ! difference = 1184-936= 248. Hmm, closer. Next, instead using 3.8, we use 3.5 for calculating HSP; then, we have 65*3.5=227. Looks better. But 248 is not much higher than 227. It's normally necessary to have 30 or so clock ticks between HR and the start of SP, and the same for the end of SP and HFL. AND they have to be multiple of eight! Are we ! stuck? ! No! let's do this, 936&percnt 8==0, (936+32)&percnt 8==0 too. But 936+32=968, 968+227=1195, ! 1195+32=1227. Hmm.. this looks not too bad. But it's not a multiple of 8, so ! lets round it up to 1232. But now we have potential trouble, the sync pulse is no longer placed right in the middle between h and H any more. Happily, using our calculator we find ! 1232-32=1200 is also a multiple of 8 and (1232-32)-968=232 corresponding using ! a sync pulse of 3.57 micro second long, still reasonable. ! In addition, 936/1232~0.76 or 76&percnt, still not far from 80&percnt, so it should be all ! right. Furthermore, using the current horizontal frame length, we basically ask our ! monitor to sync at 52.7khz(=65Mhz/1232) which is within its capability. No ! problems. ! ! Using rules of thumb we mentioned before, 936*75&percnt=702, This is our new vertical ! resolution. 702*1.05=737, our new vertical frame length. ! Screen refresh rate = 65Mhz/(737*1232)=71.6 Hz. This is still excellent. - Figuring the vertical sync pulse layout is similar: - <tscreen><verb> - - |___ __ __ __ __ __ __ __ __ __ __ __ __ - |_ _ _ _ _ _ _ _ _ _ _ _ | - |_______________________|_______________|_____ - 0 VR VFL unit: ticks - ^ ^ ^ - | | | - |<->|<----->| - VGT VSP - </verb></tscreen> - We start the sync pulse just past the end of the vertical display data ticks. VGT is the vertical guard time required for the sync pulse. Most monitors are comfortable with a VGT of 0 (no guard time) and we'll use that in this example. A few need two or three ticks of guard time, and it usually doesn't ! hurt to add that. Returning to the example: since by the definition of frame length, a vertical tick is the time for tracing a complete HORIZONTAL frame, therefore in our ! example, it is 1232/65Mhz=18.95us. Experience shows that a vertical sync pulse should be in the range of 50us and 300us. As an example let's use 150us, which translates into 8 vertical clock ! ticks (150us/18.95us~8). ! <sect>Putting it All Together <p> The Xconfig file Table of Video Modes contains lines of numbers, with each line being a complete specification for one mode of X-server operation. The fields are grouped into four sections, the name section, the clock frequency section, ! the horizontal section, and the vertical section. The name section contains one field, the name of the video mode specified by the rest of the line. This name is referred to on the "Modes" line of the Graphics Driver Setup section of the Xconfig file. The name field may be ! omitted if the name of a previous line is the same as the current line. The dot clock section contains only the dot clock (what we've called DCF) field of the video mode line. The number in this field specifies what dot clock was ! used to generate the numbers in the following sections. The horizontal section consists of four fields which specify how each horizontal line on the display is to be generated. The first field of the --- 726,862 ---- wrapped around the screen edge, producing a white edge line and a band of "ghost image" on that side. A way-out-of-place vertical sync pulse can actually cause the image to roll like a TV with a mis-adjusted vertical hold ! (in fact, it's the same phenomenon at work). If you're lucky, your monitor's sync pulse widths will be documented on its ! specification page. If not, here's where the real black magic starts... You'll have to do a little trial and error for this part. But most of the time, we can safely assume that a sync pulse is about 3.5 to 4.0 microsecond ! in length. For concreteness again, let's take HSP to be 3.8 microseconds (which btw, is not ! a bad value to start with when experimenting). Now, using the 65Mhz clock timing above, we know HSP is equivalent to 247 clock ! ticks (= 65 * 10**6 * 3.8 * 10^-6) [recall M=10^6, micro=10^-6] ! Some makers like to quote their horizontal framing parameters as timings rather ! than dot widths. You may see the following terms: ! <descrip> ! <tag/active time (HAT)/ ! Corresponds to HR, but in milliseconds. HAT * DCF = HR. ! <tag/blanking time (HBT)/ ! Corresponds to (HFL - HR), but in milliseconds. HBT * DCF = (HFL - ! HR). ! <tag/front porch (HFP)/ ! This is just HGT1. ! <tag/sync time/ ! This is just HSP. ! <tag/back porch (HBP)/ ! This is just HGT2. ! </descrip> + <sect1>Vertical Sync: + <p> + Going back to the picture above, how do we place the 247 clock ticks as shown ! in the picture? Using our example, HR is 944 and HFL is 1176. The difference between the two ! is 1176 - 944=232 < 247! Obviously we have to do some adjustment here. What ! can we do? The first thing is to raise 1176 to 1184, and lower 944 to 936. Now the ! difference = 1184-936= 248. Hmm, closer. Next, instead using 3.8, we use 3.5 for calculating HSP; then, we have 65*3.5=227. Looks better. But 248 is not much higher than 227. It's normally necessary to have 30 or so clock ticks between HR and the start of SP, and the same for the end of SP and HFL. AND they have to be multiple of eight! Are we ! stuck? ! No. Let's do this, 936 % 8 = 0, (936 + 32) % 8 = 0 too. But 936 + 32 = 968, ! 968 + 227 = 1195, 1195 + 32 = 1227. Hmm.. this looks not too bad. But it's ! not a multiple of 8, so let's round it up to 1232. But now we have potential trouble, the sync pulse is no longer placed right in the middle between h and H any more. Happily, using our calculator we find ! 1232 - 32 = 1200 is also a multiple of 8 and (1232 - 32) - 968 = 232 ! corresponding using a sync pulse of 3.57 micro second long, still ! reasonable. ! In addition, 936/1232 ~ 0.76 or 76%, still not far from 80%, so it should be ! all right. Furthermore, using the current horizontal frame length, we basically ask our ! monitor to sync at 52.7khz (= 65Mhz/1232) which is within its capability. No ! problems. ! ! Using rules of thumb we mentioned before, 936*75%=702, This is our new vertical ! resolution. 702 * 1.05 = 737, our new vertical frame length. ! ! Screen refresh rate = 65Mhz/(737*1232)=71.6 Hz. This is still excellent. ! Figuring the vertical sync pulse layout is similar: ! <code> ! |___ __ __ __ __ __ __ __ __ __ __ __ __ ! |_ _ _ _ _ _ _ _ _ _ _ _ | ! |_______________________|_______________|_____ ! 0 VR VFL unit: ticks ! ^ ^ ^ ! | | | ! |<->|<----->| ! VGT VSP ! </code> We start the sync pulse just past the end of the vertical display data ticks. VGT is the vertical guard time required for the sync pulse. Most monitors are comfortable with a VGT of 0 (no guard time) and we'll use that in this example. A few need two or three ticks of guard time, and it usually doesn't ! hurt to add that. Returning to the example: since by the definition of frame length, a vertical tick is the time for tracing a complete HORIZONTAL frame, therefore in our ! example, it is 1232/65Mhz=18.95us. Experience shows that a vertical sync pulse should be in the range of 50us and 300us. As an example let's use 150us, which translates into 8 vertical clock ! ticks (150us/18.95us~8). ! Some makers like to quote their vertical framing parameters as timings rather ! than dot widths. You may see the following terms: ! ! <descrip> ! <tag/active time (VAT)/ ! Corresponds to VR, but in milliseconds. VAT * VSF = VR. ! <tag/blanking time (VBT)/ ! Corresponds to (VFL - VR), but in milliseconds. VBT * VSF = (VFL - VR). ! <tag/front porch (VFP)/ ! This is just VGT. ! <tag/sync time/ ! This is just VSP. ! <tag/back porch (VBP)/ ! This is like a second guard time after the vertical sync pulse. It ! is often zero. ! </descrip> ! ! <sect>Putting it All Together<label id="synth"> <p> The Xconfig file Table of Video Modes contains lines of numbers, with each line being a complete specification for one mode of X-server operation. The fields are grouped into four sections, the name section, the clock frequency section, ! the horizontal section, and the vertical section. The name section contains one field, the name of the video mode specified by the rest of the line. This name is referred to on the "Modes" line of the Graphics Driver Setup section of the Xconfig file. The name field may be ! omitted if the name of a previous line is the same as the current line. The dot clock section contains only the dot clock (what we've called DCF) field of the video mode line. The number in this field specifies what dot clock was ! used to generate the numbers in the following sections. The horizontal section consists of four fields which specify how each horizontal line on the display is to be generated. The first field of the *************** *** 659,673 **** the picture (what we've called HR). The second field of the section indicates at which dot the horizontal sync pulse will begin. The third field indicates at which dot the horizontal sync pulse will end. The fourth field specifies ! the total horizontal frame length (HFL). The vertical section also contains four fields. The first field contains the number of visible lines which will appear on the display (VR). The second field indicates the line number at which the vertical sync pulse will begin. The third field specifies the line number at which the vertical sync pulse will ! end. The fourth field contains the total vertical frame length (VFL). ! Example: <tscreen><verb> #Modename clock horizontal timing vertical timing --- 864,878 ---- the picture (what we've called HR). The second field of the section indicates at which dot the horizontal sync pulse will begin. The third field indicates at which dot the horizontal sync pulse will end. The fourth field specifies ! the total horizontal frame length (HFL). The vertical section also contains four fields. The first field contains the number of visible lines which will appear on the display (VR). The second field indicates the line number at which the vertical sync pulse will begin. The third field specifies the line number at which the vertical sync pulse will ! end. The fourth field contains the total vertical frame length (VFL). ! Example: <tscreen><verb> #Modename clock horizontal timing vertical timing *************** *** 674,701 **** "752x564" 40 752 784 944 1088 564 567 569 611 44.5 752 792 976 1240 564 567 570 600 </verb></tscreen> - (Note: stock X11R5 doesn't support fractional dot clocks.) - For Xconfig, all of the numbers just mentioned - the number of illuminated dots on the line, the number of dots separating the illuminated dots from the beginning of the sync pulse, the number of dots representing the duration of the pulse, and the number of dots after the end of the sync pulse - are added to produce the number of dots per line. The number of horizontal dots must be ! evenly divisible by eight. ! Example: ! horizontal numbers: 800 864 1024 1088 - The sample line has the number of illuminated dots - (800) followed by the number of the dot when the sync - pulse starts (864), followed by the number of the dot - when the sync pulse ends (1024), followed by the number - of the last dot on the horizontal line (1088). - Note again that all of the horizontal numbers (800, 864, 1024, and 1088) are ! divisible by eight! This is not required of the vertical numbers. The number of lines from the top of the display to the bottom form the frame. The basic timing signal for a frame is the line. A number of lines will --- 879,902 ---- "752x564" 40 752 784 944 1088 564 567 569 611 44.5 752 792 976 1240 564 567 570 600 </verb></tscreen> + (Note: stock X11R5 doesn't support fractional dot clocks.) For Xconfig, all of the numbers just mentioned - the number of illuminated dots on the line, the number of dots separating the illuminated dots from the beginning of the sync pulse, the number of dots representing the duration of the pulse, and the number of dots after the end of the sync pulse - are added to produce the number of dots per line. The number of horizontal dots must be ! evenly divisible by eight. ! Example horizontal numbers: 800 864 1024 1088 ! This sample line has the number of illuminated dots (800) followed by the ! number of the dot when the sync pulse starts (864), followed by the number of ! the dot when the sync pulse ends (1024), followed by the number of the last dot ! on the horizontal line (1088). Note again that all of the horizontal numbers (800, 864, 1024, and 1088) are ! divisible by eight! This is not required of the vertical numbers. The number of lines from the top of the display to the bottom form the frame. The basic timing signal for a frame is the line. A number of lines will *************** *** 704,1158 **** generated. Then the sync pulse will last for a few lines, and finally the last lines in the frame, the delay required after the pulse, will be generated. The numbers that specify this mode of operation are entered in a manner similar to ! the following example. ! Example: ! vertical numbers: 600 603 609 630 ! This example indicates that there are 600 visible lines ! on the display, that the vertical sync pulse starts ! with the 603rd line and ends with the 609th, and that ! there are 630 total lines being used. ! Note that the vertical numbers don't have to be divisible by eight! ! ! Let's return to the example we've been working. According to the above, all ! we need to do from now on is to write our result into Xconfig as follows: ! <tscreen><verb> ! < name > DCF HR SH1 SH2 HFL VR SV1 SV2 VFL </verb></tscreen> - where SH1 is the start tick of the horizontal sync pulse and SH2 is its end tick; similarly, SV1 is the start tick of the vertical sync pulse and SV2 is ! its end tick. ! <tscreen><verb> #name clock horizontal timing vertical timing flag 936x702 65 936 968 1200 1232 702 702 710 737 </verb></tscreen> - No special flag necessary; this is a non-interlaced mode. Now we are really done. ! <sect>Questions and Answers <p> ! Q. The example you gave is not a standard screen size, can I use ! it? ! A. Why not? There is NO reason whatsoever why you have to use 640x480, ! 800x600, or even 1024x768. XFree86 driver lets you config your hardware with a ! lot of freedom. It usually takes two to three minutes to come up the right ! one. The important thing to shoot for is high refresh rate with reasonable ! viewing area. not high resolution at the price of eye-tearing flicker! ! Q. It this the *only* resolution given the 65Mhz dot clock and ! 55Khz HSF? ! A. Absolutely not! You are encouraged to follow the general procedure and ! do some trial-and-error to come up with a setting that's really to your liking. ! Experimenting with this can be lots of fun. Most settings may just give you ! nasty video hash, but nothing you do can actually damage a multi-sync monitor ! (unless you somehow force your card to clock it at way above its bandwidth --- ! if you stick reasonably close to the highest resolution the monitor is ! documented to support this can't happen). ! Beware fixed-frequency monitors! This kind of hacking around *can* damage ! them. ! Q. You just mentioned two standard resolutions. In Xconfig, there are many ! standard resolutions available, can you tell me whether there's any point in ! tinkering with timings? ! A. Absolutely! Take, for example, the "standard" 640x480 listed in the ! current Xconfig. It employs 25Mhz driving frequency, frame lengths are 800 ! and 525 => refresh rate ~ 59.5Hz. Not too bad. But 28Mhz is a commonly ! available driving frequency from many SVGA boards. If we use it to drive ! 640x480, following the procedure we discussed above, you would get frame ! lengths like 812 and 505. Now the refresh rate is raised to 68Hz, a ! quite significant improvement over the standard one. ! Q. But how about interlace/non-interlace? ! ! A. At a fixed dot clock, an interlaced display is going to flicker ! worse than a non-interlaced one, which is why the market has ! moved away from them. ! What you buy with the increased flicker is higher resolution with a slower ! dot clock. If the DCF were fast enough (say 90MHz or up) even interlacing ! wouldn't produce flicker -- but at present speeds, interlaced monitors are ! a bad idea for X. ! ! Q. Can you summarize what we have discussed so far? ! ! A. In a nutshell: ! ! <enum> ! <item>for any fixed driving frequency, raising max resolution ! incurs the penalty of lowering refresh rate and thus ! introducing more flicker. ! ! <item>if high resolution is desirable and your monitor ! supports it, try to get a SVGA card that provides ! a matching dot clock or DCF. The higher, the ! better! ! </enum> ! ! <sect> Two More Example Calculations <p> - Here's another hypothetical: ! An adapter card has a 40 MHz clock rate. A display has a range of horizontal ! sync rates from 30 KHz to 37 KHz. The minimum number of dots per line is ! 40,000,000/37,000 = 1,081.081, or approximately 1,081 dots per line. ! We'll use this number of dots per line in the following calculations. So each ! line on our display must have at least 1081 dots. We round this up to 1088 to ! make it divisible evenly by eight. Now let's assume that the horizontal sync ! pulse should be 3.8 microseconds long. We need to find out how many dots it ! takes to make a 3.8 microsecond pulse. We do this by first finding out how ! many microseconds are in one dot. Since there are 40,000,000 dots per second, ! 1/40,000,000 is the number of seconds per dot. ! 1/40,000,000 = .000000025 = .025 microseconds per dot ! Thus the number of dots for a 3.8 microsecond sync pulse is ! 3.8 microseconds = D dots x .025 microseconds/dot ! or ! D dots = (3.8 microseconds) / (.025 microseconds/dot) = 152 dots ! So we have 1088 dots per line, 800 of which are the illuminated ones, with 152 ! for the sync pulse. (Note that 152 is evenly divisible by eight. If it ! weren't we would round it up until it was evenly divisible.) This leaves us ! the task of calculating the time before and after the sync pulse that is ! necessary for the display. ! The rule of thumb for this is that we need about 30 ticks of guard time. In ! this particular case, allocating 32 dots is convenient, because all the other ! quantities are divisible by 8. This results in the timing being 800 dots for ! the viewable area, 152 dots for the pulse, and 1088 - (800 + 152) = 136 dots ! to divide between the two other times. Half of 136 is 68 dots, so 68 dots are ! placed between the illuminated dots and the sync pulse, and 68 dots are placed ! after the sync pulse. The horizontal numbers in the Xconfig line then become ! 800 (800+68) (800+68+152) (800+68+152+68) ! or ! 800 868 1020 1088 ! Now we want to calculate the vertical numbers. To begin, we must remember ! that the vertical numbers are not in terms of dots or microseconds per dot, ! but are expressed as numbers of lines! So we have to calculate how much time ! it takes to display a single line. That's easy, because we know each line is ! 1088 dots and each dot is .025 microsecond. Each line is, therefore, ! (1088 dots/line) x (.025 microseconds/dot) = ! 27.2 microseconds/line ! Since we chose 800 visible dots per line, let's choose the number of lines to ! be such that the ratio of horizontal to vertical is 4 to 3. Thus, 800 is 4 x ! 200, so the number of visible lines should be 3 x 200 = 600. Our target ! resolution is 800x600. ! We know that a vertical sync pulse should be in the range of 50 to 300 ! microseconds. If we chose 150 microseconds as a typical sync pulse, we find ! how many lines 150 microseconds is by dividing 150 by 27.2 microseconds per ! line. ! (150 microseconds/pulse) / (27.2 microseconds/line) = ! 5.51 lines/pulse ! By rounding up (never down) to 6 lines/pulse we now have the vertical sync ! pulse width. ! To guess at the total number of lines per frame (illuminated lines plus ! nonilluminated lines in the border) we assume (from "Videotiming&hellip") that the ! total number of lines will be 5&percnt more than the number of viewable lines. So ! the total number of lines is ! (600 lines) x (1.05) = 630 total lines per frame ! So now we must place the pulse in the time between the end of the illuminated ! lines and the end of the frame. Since we have 630 total lines, 600 ! illuminated lines, and 6 lines for the pulse, we have ! 630 - 600 - 6 = 24 lines left ! Some displays don't mind if the pulse begins immediately after the illuminated ! lines, but others might want a line or two between the last illuminated line ! and the beginning of the sync pulse. Taking the latter course just to be ! safe, we add three lines between the last illuminated line and the beginning ! of the pulse. The rest of the lines are added after the pulse ends. So the ! vertical timing numbers become ! 600 (600+3) (600+3+6) (600+3+6+21) ! or ! 600 603 609 630 ! Before we do anything else, we must check that the display can handle 630 ! lines/frame at 27.2 microseconds/line. We do this by calculating how many ! frames per second our configuration will generate, and comparing it to the ! display manual's entry for vertical sync rate. For 630 lines/frame at 27.2 ! micro- seconds/line, we have 630 x 27.2 = 17,136 microseconds/frame. 17,136 ! microseconds/frame is 0.017136 seconds/frame, or 1/0.017892 frames/second. ! 1 / (0.017136 seconds/frame) = 58.4 frames/second ! If the manual says the vertical sync rate is 58.4 Hz, or 58.4 Hz is in the ! range of the display's vertical sync rate, we are fine. If the display cannot ! handle this rate, we'll have to change the number of lines per frame by ! adjusting all of the timings proportionally. ! Now we combine the horizontal and vertical timing numbers together with the ! resolution and clock values to produce a test configuration for Xconfig. Our ! line becomes ! "800x600" 40 800 868 1020 1088 600 603 609 630 ! Now we have a configuration of XFree86 to try. It may not work if any of our ! assumptions were grossly wrong, but in most cases it should at least give us a ! stable display. Now it takes a little experimentation to produce something ! pleasing. ! An actual calculation ! My adapter card has a 40 MHz crystal on it so I started with a 40 ! MHz clock rate. My display's maximum horizontal sync rate is 37 ! KHz, so the minimum dots per line are 40,000,000/37,000 = 1081. ! My display's vertical sync rate is the range from 50 Hz to 90 Hz. ! My display's manual says that the largest horizontal sync pulse ! is 3.92 microseconds. With 0.025 microseconds per dot, the pulse ! is ! (3.92 microseconds) / (.025 microseconds/dot) = ! 156.8 dots ! Rounding this up to the nearest number evenly divisible by eight ! gives 160 dots. ! The manual also says that the time between the last illuminated ! dot and the beginning of the sync pulse must be at least 0.67 ! microseconds. The number of dots in 0.67 microseconds at a 40 ! MHz clock rate - remember 40 MHz is .025 microseconds/dot - is ! D dots = (0.67 microseconds) / (.025 microseconds/dot) = ! 26.8 dots ! Since 26.8 is not evenly divisible by eight, round it up to 32 ! dots. ! My display's manual says the time after the sync pulse should be ! 3.56 microseconds or more. In dots, 3.56 microseconds is ! D dots = (3.56 microseconds) / (.025 microseconds/dot) = ! 142.4 dots ! Round 142.4 up to 144, so that it's evenly divisible by eight. ! So now for a horizontal line we have 800 illuminated dots, 32 ! dots between the illuminated dots and the sync pulse, 152 dots ! for the sync pulse, and 144 dots after the sync pulse. ! 800 + 32 + 160 + 144 = 1136 ! We now have a line that is 1136 dots long. This is greater than ! the 1088 we previously calculated, but remember that 1088 was the ! MINIMUM number of dots that could be on a line. So 1136 dots per ! line is okay for starters. ! The numbers to enter on the Xconfig line so far are ! "800x?" 40 800 (800+32) (800+32+160) (800+32+160+144)&hellip ! or ! "800x?" 40 800 832 992 1136&hellip ! A line of 1136 dots at .025 microsecond/dot means that a line ! represents 1136 x .025 = 28.4 microseconds. ! Since we chose 800 dots/line horizontal resolution, we choose 600 ! lines/frame as the vertical resolution. ! My display's manual says that the vertical sync pulse must be at ! least 64 microseconds long. In terms of lines, 64 microseconds ! is ! (64 microseconds/pulse) / (28.4 microseconds/line) = ! 2.25 lines/pulse ! We round 2.25 up to 3 lines for the vertical sync pulse. ! The manual says the time between the last displayed line and the ! start of the sync pulse must be at least 318 microseconds, and ! the delay after the end of the pulse must be at least 630 ! microseconds. We calculate how many lines each of these time ! periods represents as follows. ! (318 microseconds) / (28.4 microseconds/line) = ! 11.20 lines ! (630 microseconds) / (28.4 microseconds/line) = ! 22.18 lines ! We round each of the times up to become 12 lines before the sync ! pulse and 23 lines after the pulse. This makes our vertical ! timing numbers ! 600 (600+12) (600+12+3) (600+12+3+23) ! or ! 600 612 615 638 ! Checking the frame rate to see if it falls within the rate of the ! display, we see that 638 lines/frame at 28.4 microseconds/line is ! 18,119 microseconds/frame, which is 55.19 frames/second. My ! display can handle anything from 50 Hz to 90 Hz, so the timing is ! all right. ! Putting the resolution, clock, horizontal, vertical timing ! numbers together on a video mode line in Xconfig results in ! "800x600" 40 800 832 992 1136 600 612 615 638 ! This was the first video mode I tried. It turned out not to be ! very satisfactory because there was too much flicker. I tried ! other timings both above and below this setting as shown in the ! following example. I finally settled on the "784x614" mode as a ! compromise between flicker and resolution. ! You'll notice that almost all of the clock frequencies are 40 ! MHz. Through experimentation I found that higher frequencies ! were beyond my adapter card's capabilities, and that lower ! frequencies didn't provide the resolution I wanted. - Example: - Timings I have tried: - <tscreen><verb> ! # the following line works but is right of center ! "752x564" 40 752 784 944 1088 564 567 569 611 ! # 44.5 752 792 976 1240 564 567 570 600 ! # ! # this line fixes the problem with the previous line ! #"752x564" 40 752 816 976 1088 564 567 569 611 ! # ! # trying to increase the vertical display size, it works ! #"752x614" 40 752 816 976 1088 614 617 619 661 ! # ! # trying to increase the horiz. display size, it works ! #"784x564" 40 784 816 976 1088 564 567 569 611 ! # ! # the following works but is to the right of center ! #"784x614" 40 784 816 976 1088 614 617 619 661 ! # ! # the following corrects the uncentered problem of the previous one ! "784x614" 40 784 848 1008 1088 614 617 619 661 ! # ! # trying to increase the display size ! # the following works, the display is slightly off center to the left ! #"800x614" 40 800 864 1024 1088 614 617 619 661 ! # ! # the following corrects the problem of the previous entry ! "800x614" 40 800 864 1024 1104 614 617 619 661 ! # ! # increase the display size, it works ! "816x614" 40 816 880 1040 1120 614 617 619 661 ! # ! # increase the display size, it works ! "800x620" 40 800 864 1024 1104 620 623 625 661 ! # ! # increase the display size, it works ! "816x620" 40 816 880 1040 1120 620 623 625 661 ! # ! # increase the display size, it works ! "832x630" 40 832 896 1056 1136 630 633 635 661 ! # ! # change the display size, it works but flickers badly ! "848x618" 40 848 912 1072 1152 618 621 623 661 </verb></tscreen> ! <sect> Fixing Problems with the Image. ! <p> ! OK, so you've got your X configuration numbers. You put them in Xconfig with ! a test mode label. You fire up X, hot-key to the new mode, &hellip and the image ! doesn't look right. What do you do? Here's a list of common problems and how ! to fix them. ! You *move* the image by changing the sync pulse timing. You *scale* it by ! changing the frame length (you need to move the sync pulse to keep it in ! the same relative position, otherwise scaling will move the image as well). ! Here are some more specific recipes: ! The horizontal and vertical positions are independent. That is, moving the ! image horizontally doesn't affect placement vertically, or vice-versa. ! However, the same is not quite true of scaling. While changing the horizontal ! size does nothing to the vertical size or vice versa, the total change in both ! may be limited. In particular, if your image is too large in both dimensions ! you will probably have to go to a higher dot clock to fix it. Since this ! raises the usable resolution, it is seldom a problem! ! The image is displaced to the left or right ! To fix this, move the horizontal sync pulse. That is, increment or ! decrement (by a multiple of 8) the middle two numbers of the horizontal timing ! section that define the leading and trailing edge of the horizontal sync pulse. ! If the image is shifted left (right border too large, you want to move ! the image to the right) decrement the numbers. If the image is shifted right ! (left border too large, you want it to move left) increment the sync pulse. ! The image is displaced up or down ! To fix this, move the vertical sync pulse. That is, increment or ! decrement the middle two numbers of the vertical timing section that define ! the leading and trailing edge of the vertical sync pulse. ! If the image is shifted up (lower border too large, you want to move ! the image down) decrement the numbers. If the image is shifted down ! (top border too large, you want it to move up) increment the numbers. ! The image is too wide (too narrow) horizontally ! To fix this, increase (decrease) the horizontal frame length. That is, ! change the fourth number in the first timing section. To avoid moving the ! image, also move the sync pulse (second and third numbers) half as far, ! to keep it in the same relative position. ! The image is too deep (too shallow) vertically ! To fix this, decrease (increase) the vertical frame length. That is, ! change the fourth number in the second timing section. To avoid moving the ! image, also move the sync pulse (second and third numbers) half as far, ! to keep it in the same relative position. ! Any distortion that can't be handled by combining these techniques is probably ! evidence of something more basically wrong, like a calculation mistake or a ! faster dot clock than the monitor can handle. ! Finally, remember that increasing either frame length will decrease your ! refresh rate, and vice-versa. <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/VidModes.sgml,v 3.11 1997/01/25 03:22:17 dawes Exp $ ! ! ! ! ! ! $TOG: VidModes.sgml /main/8 1997/07/19 10:34:05 kaleb $ </verb> </article> --- 905,1421 ---- generated. Then the sync pulse will last for a few lines, and finally the last lines in the frame, the delay required after the pulse, will be generated. The numbers that specify this mode of operation are entered in a manner similar to ! the following example. ! Example vertical numbers: 600 603 609 630 ! This example indicates that there are 600 visible lines on the display, that ! the vertical sync pulse starts with the 603rd line and ends with the 609th, and ! that there are 630 total lines being used. ! Note that the vertical numbers don't have to be divisible by eight! ! Let's return to the example we've been working. According to the above, all ! we need to do from now on is to write our result into Xconfig as follows: <tscreen><verb> ! <name> DCF HR SH1 SH2 HFL VR SV1 SV2 VFL </verb></tscreen> where SH1 is the start tick of the horizontal sync pulse and SH2 is its end tick; similarly, SV1 is the start tick of the vertical sync pulse and SV2 is ! its end tick. <tscreen><verb> #name clock horizontal timing vertical timing flag 936x702 65 936 968 1200 1232 702 702 710 737 </verb></tscreen> No special flag necessary; this is a non-interlaced mode. Now we are really done. ! <sect>Overdriving Your Monitor<label id="overd"> <p> ! You should absolutely <EM>not</EM> try exceeding your monitor's scan ! rates if it's a fixed-frequency type. You can smoke your hardware ! doing this! There are potentially subtler problems with overdriving a ! multisync monitor which you should be aware of. ! Having a pixel clock higher than the monitor's maximum bandwidth is ! rather harmless, in contrast. (Note: the theoretical limit of ! discernible features is reached when the pixel clock reaches double ! the monitor's bandwidth. This is a straightforward application of ! Nyquist's Theorem: consider the pixels as a spatially distributed ! series of samples of the drive signals and you'll see why.) ! It's exceeding the rated maximum sync frequencies that's problematic. ! Some modern monitors might have protection circuitry that shuts the ! monitor down at dangerous scan rates, but don't rely on it. In ! particular there are older multisync monitors (like the Multisync II) ! which use just one horizontal transformer. These monitors will not ! have much protection against overdriving them. While you necessarily ! have high voltage regulation circuitry (which can be absent in fixed ! frequency monitors), it will not necessarily cover every conceivable ! frequency range, especially in cheaper models. This not only implies ! more wear on the circuitry, it can also cause the screen phosphors to ! age faster, and cause more than the specified radiation (including X-rays) ! to be emitted from the monitor. ! Another importance of the bandwidth is that the monitor's input ! impedance is specified only for that range, and using higher ! frequencies can cause reflections probably causing minor screen ! interferences, and radio disturbance. ! However, the basic problematic magnitude in question here is the slew ! rate (the steepness of the video signals) of the video output drivers, ! and that is usually independent of the actual pixel frequency, but ! (if your board manufacturer cares about such problems) related ! to the maximum pixel frequency of the board. ! So be careful out there... ! <sect>Using Interlaced Modes<label id="inter"> <p> ! (This section is largely due to David Kastrup ! <dak@pool.informatik.rwth-aachen.de>) ! At a fixed dot clock, an interlaced display is going to have ! considerably less noticeable flicker than a non-interlaced display, if ! the vertical circuitry of your monitor is able to support it stably. ! It is because of this that interlaced modes were invented in the first ! place. ! Interlaced modes got their bad repute because they are inferior to ! their non-interlaced companions at the same vertical scan frequency, ! VSF (which is what is usually given in advertisements). But they are ! definitely superior at the same horizontal scan rate, and that's where ! the decisive limits of your monitor/graphics card usually lie. + At a fixed <EM>refresh rate</EM> (or half frame rate, or VSF) the + interlaced display will flicker more: a 90Hz interlaced display will + be inferior to a 90Hz non-interlaced display. It will, however, need + only half the video bandwidth and half the horizontal scan rate. If + you compared it to a non-interlaced mode with the same dot clock and + the same scan rates, it would be vastly superior: 45Hz non-interlaced + is intolerable. With 90Hz interlaced, I have worked for years with my + Multisync 3D (at 1024x768) and am very satisfied. I'd guess you'd need + at least a 70Hz non-interlaced display for similar comfort. ! You have to watch a few points, though: use interlaced modes only at ! high resolutions, so that the alternately lighted lines are close ! together. You might want to play with sync pulse widths and positions ! to get the most stable line positions. If alternating lines are bright ! and dark, interlace will <EM>jump</EM> at you. I have one application that ! chooses such a dot pattern for a menu background (XCept, no other ! application I know does that, fortunately). I switch to 800x600 for ! using XCept because it really hurts my eyes otherwise. ! For the same reason, use at least 100dpi fonts, or other fonts where ! horizontal beams are at least two lines thick (for high resolutions, ! nothing else will make sense anyhow). ! And of course, never use an interlaced mode when your hardware would ! support a non-interlaced one with similar refresh rate. ! If, however, you find that for some resolution you are pushing either ! monitor or graphics card to their upper limits, and getting ! unsatisfactory flickery or washed out (bandwidth exceeded) display, ! you might want to try tackling the same resolution using an ! interlaced mode. Of course this is useless if the VSF ! of your monitor is already close to its limits. ! Design of interlaced modes is easy: do it like a non-interlaced ! mode. Just two more considerations are necessary: you need an odd ! total number of vertical lines (the last number in your mode line), and ! when you specify the "interlace" flag, the actual vertical frame rate ! for your monitor doubles. Your monitor needs to support a 90Hz frame ! rate if the mode you specified looks like a 45Hz mode apart from the ! "Interlace" flag. ! As an example, here is my modeline for 1024x768 interlaced: my ! Multisync 3D will support up to 90Hz vertical and 38kHz horizontal. ! <tscreen><verb> ! ModeLine "1024x768" 45 1024 1048 1208 1248 768 768 776 807 Interlace ! </verb></tscreen> ! Both limits are pretty much exhausted with this mode. Specifying the ! same mode, just without the "Interlace" flag, still is almost at the ! limit of the monitor's horizontal capacity (and strictly speaking, a ! bit under the lower limit of vertical scan rate), but produces an ! intolerably flickery display. ! Basic design rules: if you have designed a mode at less than half of ! your monitor's vertical capacity, make the vertical total of lines odd ! and add the "Interlace" flag. The display's quality should vastly ! improve in most cases. ! If you have a non-interlaced mode otherwise exhausting your monitor's ! specs where the vertical scan rate lies about 30% or more under the ! maximum of your monitor, hand-designing an interlaced mode (probably ! with somewhat higher resolution) could deliver superior results, but I ! won't promise it. ! <sect>Questions and Answers<label id="answe"> ! <p> ! Q. The example you gave is not a standard screen size, can I use it? ! A. Why not? There is NO reason whatsoever why you have to use 640x480, ! 800x600, or even 1024x768. The XFree86 servers let you configure your hardware ! with a lot of freedom. It usually takes two to three tries to come up the ! right one. The important thing to shoot for is high refresh rate with ! reasonable viewing area. not high resolution at the price of eye-tearing ! flicker! ! Q. It this the only resolution given the 65Mhz dot clock and 55Khz HSF? ! A. Absolutely not! You are encouraged to follow the general procedure and ! do some trial-and-error to come up a setting that's really to your liking. ! Experimenting with this can be lots of fun. Most settings may just give you ! nasty video hash, but in practice a modern multi-sync monitor is usually not ! damaged easily. Be sure though, that your monitor can support the frame ! rates of your mode before using it for longer times. ! Beware fixed-frequency monitors! This kind of hacking around can damage ! them rather quickly. Be sure you use valid refresh rates for <EM>every</EM> ! experiment on them. ! Q. You just mentioned two standard resolutions. In Xconfig, there are many ! standard resolutions available, can you tell me whether there's any point in ! tinkering with timings? ! A. Absolutely! Take, for example, the "standard" 640x480 listed in the ! current Xconfig. It employs 25Mhz driving frequency, frame lengths are 800 ! and 525 => refresh rate ~ 59.5Hz. Not too bad. But 28Mhz is a commonly ! available driving frequency from many SVGA boards. If we use it to drive ! 640x480, following the procedure we discussed above, you would get frame ! lengths like 812 and 505. Now the refresh rate is raised to 68Hz, a ! quite significant improvement over the standard one. ! Q. Can you summarize what we have discussed so far? ! A. In a nutshell: ! <enum> ! <item> ! for any fixed driving frequency, raising max resolution incurs the penalty ! of lowering refresh rate and thus introducing more flicker. ! <item> ! if high resolution is desirable and your monitor supports it, try to ! get a SVGA card that provides a matching dot clock or DCF. The higher, ! the better! ! </enum> ! <sect>Fixing Problems with the Image.<label id="fixes"> ! <p> + OK, so you've got your X configuration numbers. You put them in Xconfig with + a test mode label. You fire up X, hot-key to the new mode, ... and the image + doesn't look right. What do you do? Here's a list of common problems and how + to fix them. ! (Fixing these minor distortions is where <bf>xvidtune</bf>(1) really shines.) ! You <em>move</em> the image by changing the sync pulse timing. You ! <em>scale</em> it by changing the frame length (you need to move the ! sync pulse to keep it in the same relative position, otherwise scaling will ! move the image as well). Here are some more specific recipes: ! The horizontal and vertical positions are independent. That is, moving the ! image horizontally doesn't affect placement vertically, or vice-versa. ! However, the same is not quite true of scaling. While changing the horizontal ! size does nothing to the vertical size or vice versa, the total change in both ! may be limited. In particular, if your image is too large in both dimensions ! you will probably have to go to a higher dot clock to fix it. Since this ! raises the usable resolution, it is seldom a problem! ! <sect1>The image is displaced to the left or right ! <p> ! To fix this, move the horizontal sync pulse. That is, increment or decrement ! (by a multiple of 8) the middle two numbers of the horizontal timing section ! that define the leading and trailing edge of the horizontal sync pulse. ! If the image is shifted left (right border too large, you want to move ! the image to the right) decrement the numbers. If the image is shifted right ! (left border too large, you want it to move left) increment the sync pulse. ! <sect1>The image is displaced up or down ! <p> ! To fix this, move the vertical sync pulse. That is, increment or decrement the ! middle two numbers of the vertical timing section that define the leading and ! trailing edge of the vertical sync pulse. ! If the image is shifted up (lower border too large, you want to move the image ! down) decrement the numbers. If the image is shifted down (top border too ! large, you want it to move up) increment the numbers. ! <sect1>The image is too large both horizontally and vertically ! <p> ! Switch to a higher card clock speed. If you have multiple modes in your ! clock file, possibly a lower-speed one is being activated by mistake. ! <sect1>The image is too wide (too narrow) horizontally ! <p> ! To fix this, increase (decrease) the horizontal frame length. That is, change ! the fourth number in the first timing section. To avoid moving the image, also ! move the sync pulse (second and third numbers) half as far, to keep it in the ! same relative position. ! <sect1>The image is too deep (too shallow) vertically ! <p> ! To fix this, increase (decrease) the vertical frame length. That is, change ! the fourth number in the second timing section. To avoid moving the image, ! also move the sync pulse (second and third numbers) half as far, to keep it in ! the same relative position. ! Any distortion that can't be handled by combining these techniques is probably ! evidence of something more basically wrong, like a calculation mistake or a ! faster dot clock than the monitor can handle. ! Finally, remember that increasing either frame length will decrease your ! refresh rate, and vice-versa. ! <sect>Plotting Monitor Capabilities<label id="cplot"> ! <p> ! To plot a monitor mode diagram, you'll need the gnuplot package (a ! freeware plotting language for UNIX-like operating systems) and the ! tool <TT>modeplot</TT>, a shell/gnuplot script to plot the diagram from your ! monitor characteristics, entered as command-line options. ! Here is a copy of modeplot: ! <code> ! #!/bin/sh ! # ! # modeplot -- generate X mode plot of available monitor modes ! # ! # Do `modeplot -?' to see the control options. ! # ! # ($Id: VidModes.sgml /main/9 1998/03/06 16:42:42 kaleb $) ! # Monitor description. Bandwidth in MHz, horizontal frequencies in kHz ! # and vertical frequencies in Hz. ! TITLE="Viewsonic 21PS" ! BANDWIDTH=185 ! MINHSF=31 ! MAXHSF=85 ! MINVSF=50 ! MAXVSF=160 ! ASPECT="4/3" ! vesa=72.5 # VESA-recommended minimum refresh rate ! while [ "$1" != "" ] ! do ! case $1 in ! -t) TITLE="$2"; shift;; ! -b) BANDWIDTH="$2"; shift;; ! -h) MINHSF="$2" MAXHSF="$3"; shift; shift;; ! -v) MINVSF="$2" MAXVSF="$3"; shift; shift;; ! -a) ASPECT="$2"; shift;; ! -g) GNUOPTS="$2"; shift;; ! -?) cat <<EOF ! modeplot control switches: ! -t "<description>" name of monitor defaults to "Viewsonic 21PS" ! -b <nn> bandwidth in MHz defaults to 185 ! -h <min> <max> min & max HSF (kHz) defaults to 31 85 ! -v <min> <max> min & max VSF (Hz) defaults to 50 160 ! -a <aspect ratio> aspect ratio defaults to 4/3 ! -g "<options>" pass options to gnuplot ! The -b, -h and -v options are required, -a, -t, -g optional. You can ! use -g to pass a device type to gnuplot so that (for example) modeplot's ! output can be redirected to a printer. See gnuplot(1) for details. + The modeplot tool was created by Eric S. Raymond <esr@thyrsus.com> based on + analysis and scratch code by Martin Lottermoser <Martin.Lottermoser@mch.sni.de> ! This is modeplot $Revision: /main/9 $ ! EOF ! exit;; ! esac ! shift ! done ! gnuplot $GNUOPTS <<EOF ! set title "$TITLE Mode Plot" ! # Magic numbers. Unfortunately, the plot is quite sensitive to changes in ! # these, and they may fail to represent reality on some monitors. We need ! # to fix values to get even an approximation of the mode diagram. These come ! # from looking at lots of values in the ModeDB database. ! F1 = 1.30 # multiplier to convert horizontal resolution to frame width ! F2 = 1.05 # multiplier to convert vertical resolution to frame height ! # Function definitions (multiplication by 1.0 forces real-number arithmetic) ! ac = (1.0*$ASPECT)*F1/F2 ! refresh(hsync, dcf) = ac * (hsync**2)/(1.0*dcf) ! dotclock(hsync, rr) = ac * (hsync**2)/(1.0*rr) ! resolution(hv, dcf) = dcf * (10**6)/(hv * F1 * F2) ! # Put labels on the axes ! set xlabel 'DCF (MHz)' ! set ylabel 'RR (Hz)' 6 # Put it right over the Y axis ! # Generate diagram ! set grid ! set label "VB" at $BANDWIDTH+1, ($MAXVSF + $MINVSF) / 2 left ! set arrow from $BANDWIDTH, $MINVSF to $BANDWIDTH, $MAXVSF nohead ! set label "max VSF" at 1, $MAXVSF-1.5 ! set arrow from 0, $MAXVSF to $BANDWIDTH, $MAXVSF nohead ! set label "min VSF" at 1, $MINVSF-1.5 ! set arrow from 0, $MINVSF to $BANDWIDTH, $MINVSF nohead ! set label "min HSF" at dotclock($MINHSF, $MAXVSF+17), $MAXVSF + 17 right ! set label "max HSF" at dotclock($MAXHSF, $MAXVSF+17), $MAXVSF + 17 right ! set label "VESA $vesa" at 1, $vesa-1.5 ! set arrow from 0, $vesa to $BANDWIDTH, $vesa nohead # style -1 ! plot [dcf=0:1.1*$BANDWIDTH] [$MINVSF-10:$MAXVSF+20] \ ! refresh($MINHSF, dcf) notitle with lines 1, \ ! refresh($MAXHSF, dcf) notitle with lines 1, \ ! resolution(640*480, dcf) title "640x480 " with points 2, \ ! resolution(800*600, dcf) title "800x600 " with points 3, \ ! resolution(1024*768, dcf) title "1024x768 " with points 4, \ ! resolution(1280*1024, dcf) title "1280x1024" with points 5, \ ! resolution(1600*1280, dcf) title "1600x1200" with points 6 ! pause 9999 ! EOF ! </code> ! Once you know you have <TT>modeplot</TT> and the gnuplot package in ! place, you'll need the following monitor characteristics: ! <itemize> ! <item> video bandwidth (VB) ! <item> range of horizontal sync frequency (HSF) ! <item> range of vertical sync frequency (VSF) ! </itemize> ! The plot program needs to make some simplifying assumptions which are ! not necessarily correct. This is the reason why the resulting diagram is ! only a rough description. These assumptions are: ! <enum> ! <item> All resolutions have a single fixed aspect ratio AR = HR/VR. ! Standard resolutions have AR = 4/3 or AR = 5/4. The <TT>modeplot</TT> ! programs assumes 4/3 by default, but you can override this. ! <item> For the modes considered, horizontal and vertical frame lengths are ! fixed multiples of horizontal and vertical resolutions, respectively: ! <tscreen><verb> ! HFL = F1 * HR ! VFL = F2 * VR ! </verb></tscreen> ! </enum> ! As a rough guide, take F1 = 1.30 and F2 = 1.05 (see <ref id=frame> ! "Computing Frame Sizes"). ! Now take a particular sync frequency, HSF. Given the assumptions just ! presented, every value for the clock rate DCF already determines the ! refresh rate RR, i.e. for every value of HSF there is a function RR(DCF). ! This can be derived as follows. ! The refresh rate is equal to the clock rate divided by the product of the ! frame sizes: ! <tscreen><verb> ! RR = DCF / (HFL * VFL) (*) ! </verb></tscreen> ! On the other hand, the horizontal frame length is equal to the clock rate ! divided by the horizontal sync frequency: <tscreen><verb> ! HFL = DCF / HSF (**) </verb></tscreen> ! VFL can be reduced to HFL be means of the two assumptions above: ! <tscreen><verb> ! VFL = F2 * VR ! = F2 * (HR / AR) ! = (F2/F1) * HFL / AR (***) ! </verb></tscreen> ! Inserting (**) and (***) into (*) we obtain: ! <tscreen><verb> ! RR = DCF / ((F2/F1) * HFL**2 / AR) ! = (F1/F2) * AR * DCF * (HSF/DCF)**2 ! = (F1/F2) * AR * HSF**2 / DCF ! </verb></tscreen> ! For fixed HSF, F1, F2 and AR, this is a hyperbola in our diagram. Drawing ! two such curves for minimum and maximum horizontal sync frequencies we ! have obtained the two remaining boundaries of the permitted region. ! The straight lines crossing the capability region represent particular ! resolutions. This is based on (*) and the second assumption: ! <tscreen><verb> ! RR = DCF / (HFL * VFL) = DCF / (F1 * HR * F2 * VR) ! </verb></tscreen> ! By drawing such lines for all resolutions one is interested in, one ! can immediately read off the possible relations between resolution, ! clock rate and refresh rate of which the monitor is capable. Note that ! these lines do not depend on monitor properties, but they do depend on ! the second assumption. ! The <TT>modeplot</TT> tool provides you with an easy way to do this. Do ! <TT>modeplot -?</TT> to see its control options. A typical invocation ! looks like this: ! <tscreen><verb> ! modeplot -t "Swan SW617" -b 85 -v 50 90 -h 31 58 ! </verb></tscreen> ! The -b option specifies video bandwidth; -v and -h set horizontal and ! vertical sync frequency ranges. ! When reading the output of <TT>modeplot</TT>, always bear in mind that ! it gives only an approximate description. For example, it disregards ! limitations on HFL resulting from a minimum required sync pulse width, ! and it can only be accurate as far as the assumptions are. It is ! therefore no substitute for a detailed calculation (involving some ! black magic) as presented in <ref id="synth" name="Putting it All ! Together">. However, it should give you a better feeling for what ! is possible and which tradeoffs are involved. ! <sect>Credits<label id="credi"> ! <p> ! The original ancestor of this document was by Chin Fang ! <fangchin@leland.stanford.edu>. ! Eric S. Raymond <esr@snark.thyrsus.com> reworked, reorganized, and ! massively rewrote Chin Fang's original in an attempt to understand it. In ! the process, he merged in most of a different how-to by Bob Crosson ! <crosson@cam.nist.gov>. ! The material on interlaced modes is largely by David Kastrup ! <dak@pool.informatik.rwth-aachen.de> + Martin Lottermoser <Martin.Lottermoser@mch.sni.de> contributed + the idea of using gnuplot to make mode diagrams and did the + mathematical analysis behind <TT>modeplot</TT>. The distributed + <TT>modeplot</TT> was redesigned and generalized by ESR from + Martin's original gnuplot code for one case. <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/VidModes.sgml,v 3.11.2.2 1998/02/20 23:10:30 dawes Exp $ ! ! ! ! ! ! $TOG: VidModes.sgml /main/9 1998/03/06 16:42:42 kaleb $ ! $TOG: VidModes.sgml /main/9 1998/03/06 16:42:42 kaleb $ </verb> </article> *** /dev/null Tue Jun 30 11:47:22 1998 --- xc/programs/Xserver/hw/xfree86/doc/sgml/apm.sgml Fri Mar 6 16:41:10 1998 *************** *** 0 **** --- 1,77 ---- + <!DOCTYPE linuxdoc PUBLIC "-//XFree86//DTD linuxdoc//EN"> + + <article> + <title> Information for Alliance Promotion chipset users + <author> Henrik Harmsen (Henrik.Harmsen@erv.ericsson.se) + <date> 23 February 1998 + <toc> + + <sect> Support chipsets + <p> + The apm driver in the SVGA server is for Alliance Promotion + (www.alsc.com) graphics chipsets. The following chipsets are supported: + + <itemize> + <item> 6422 + + Old chipset without color expansion hardware (text accel). + + <item> AT24 + + As found in Diamond Stealth Video 2500. Quite similar to AT3D. + + <item> AT25, AT3D + + AT3D is found in Hercules Stingray 128/3D. Most other Voodoo + Rush based cards use the AT25 which is identical except it + doesn't have the 3D stuff in it. + </itemize> + + <sect> Acceleration + <p> + The apm driver uses the XAA (XFree86 Acceleration Architecture) in the + SVGA server. It has support for the following acceleration: + + <itemize> + <item> Bitblts (rectangle copy operation) + <item> Lines (solid, single pixel) + <item> Filled rectangles + <item> CPU->Screen colour expansion (text accel). Not for 6422. + <item> Hardware cursor + </itemize> + + All in 8, 16 and 32 bpp modes. No 24bpp mode is supported. + Also VESA DPMS power save mode is fully supported with "standby", + "suspend" and "off" modes (set with with the "xset dpms" command). + + <sect> Configuration + <p> + First: Please run the XF86Setup program to create a correct + configuration. + + You can turn off hardware cursor by inserting the following line in the + Device section of the XF86Config file: + + Option "sw_cursor" + + Or turn off hardware acceleration: + + Option "noaccel" + + Please don't specify the amount of video RAM you have or which chipset + you have in the config file, let the driver probe for this. Also please + don't put any "clocks" line in the device section since these chips have + a fully programmable clock that can take (almost) any modeline you throw + at it. It might fail at some specific clock values but you should just + try a slightly different clock and it should work. + + + + <verb> + $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/apm.sgml,v 1.1.2.2 1998/02/25 12:20:30 dawes Exp $ + + + + $TOG: apm.sgml /main/1 1998/03/06 16:42:48 kaleb $ + </verb> + </article> *** ./programs/Xserver/hw/xfree86/doc/sgml/ati.sgml@@/PUBLIC-LATEST Sat Jul 19 10:34:42 1997 --- xc/programs/Xserver/hw/xfree86/doc/sgml/ati.sgml Fri Mar 6 16:41:14 1998 *************** *** 3,19 **** <!-- Title information --> ! <title>ATI adapters README <author>Marc Aurele La France ! <date>23 March 1996 <abstract> ! This is the README for the XFree86 ATI VGA driver used in the XF86_Mono, ! XF86_VGA16 and XF86_SVGA servers. ! Users of ATI adapters based on the Mach8, Mach32 or Mach64 (including 3D Rage ! and 3D Rage II) accelerators should ! be using the accelerated servers (XF86_Mach8, XF86_Mach32 or XF86_Mach64). ! The unaccelerated servers (XF86_Mono, XF86_VGA16 and XF86_SVGA) should still ! work, but are a waste of capabilities. </abstract> <!-- Table of contents --> --- 3,13 ---- <!-- Title information --> ! <title>ATI Adapters README file <author>Marc Aurele La France ! <date>1998 January 28 <abstract> ! This is the README for the XFree86 ATI driver included in this release. </abstract> <!-- Table of contents --> *************** *** 21,94 **** <!-- Begin the document --> ! <sect> What is the ATI VGA driver?<p> ! The ATI VGA driver is a 256-colour, 16-colour and monochrome driver for ! XFree86. ! The driver is intended for all ATI video adapters except those that do not ! provide SuperVGA functionality (such as some early Mach8 and Mach32 adapters). ! The following approximate maximum resolutions (based on the Golden Ratio of x/y ! = (1 + sqrt(5))/2) are possible depending on the video memory available on the ! adapter (and the capabilities of your monitor): <verb> ! 256k 640x409x256 896x585x16 ! 512k 896x585x256 1280x819x16 ! 1M 1280x819x256 1824x1149x16</verb> ! Maximum monochrome resolutions are the same as those for 16-colour mode, ! because the monochrome server uses a maximum of one fourth of the available ! video memory.<p> ! <sect> What is the ATI VGA driver *not*?<p> ! This driver does not yet support more than 8 bits of pixel depth. ! Even if your manual says that your graphics adapter supports modes using more ! than 256 colours, the ATI VGA driver will not use these modes.<p> ! The ATI VGA driver is not an accelerated driver. ! If your adapter is based on the Mach8, Mach32 or Mach64 video controllers, this ! driver will not use the accelerated functions of the hardware. ! It will only use the VGA hardware (which, for Mach32's and Mach64's, is ! integrated into the accelerator). ! This can make opaque moves, for example, quite jerky.<p> ! <sect> What video adapters will the driver work with?<p> ! Most adapters harbouring the following ATI video controller chips will work ! with this driver: <verb> ! VGA Wonder series: 18800, 18800-1, 28800-2, 28800-4, 28800-5, 28800-6 ! Mach32 series: 68800-3, 68800-6, 68800AX, 68800LX ! Mach64 series: 88800GX-C, 88800GX-D, 88800GX-E, 88800GX-F, 88800CX, ! 264CT, 264ET, 264VT, 264VT2, 264GT</verb> ! The 264xT series are integrated controllers, meaning that they include an ! internal RAMDAC and clock generator. ! Some early Mach32 adapters will not work with this driver because they do not ! provide VGA functionality. ! Also, early Mach8 adapters will not work for the same reason, unless the ! adapter also has a video controller from the VGA Wonder series (or is connected ! to one through the VGA passthrough connector).<p> These adapters are available with a variety of clock generators and RAMDACs. ! See the XF86Config section below for details. ! These adapters are available with or without a mouse.<p> ! VGA Wonder V3 adapters use a 18800 video controller and generate dot clocks ! with crystals. ! VGA Wonder V4 adapters have a 18800-1 and also use crystals. ! VGA Wonder V5 adapters also use a 18800-1, but have a 18810 clock generator. ! VGA Wonder+ adapters use a 28800-2 and a 18810. ! Other than these, ATI's adapter naming convention (if it can be said that one ! exists) starts to fall apart.<p> ! The VGA Wonder series was also available through ATI's OEM channel under the ! name VGA1024. ! Thus, the ATI VGA driver also supports VGA1024, VGA1024D, VGA1024XL, ! VGA1024DXL and VGA1024VLB adapters, among others.<p> ! <sect>What should I put in my XF86Config file?<p> ! The chipset will be automatically detected. ! The chipset name for this driver is "ati". ! The driver also recognizes "vgawonder", "mach8", "mach32" and "mach64" as ! chipset names. ! In this version of the driver, all names are equivalent. ! In some future version each name will have a different meaning to be documented at that time.<p> ! The clocks line to be specified in your XF86Config depends on what the adapter ! uses to generate dot clocks.<p> ! For all adapters, one of the following clocks specifications (or an initial ! subset thereof) can be used depending on what the adapter uses to generate dot ! clocks: <verb> Crystals (VGA Wonder V3 and V4 adapters only): Clocks 50.000 56.644 0.000 44.900 44.900 50.000 0.000 36.000 --- 15,232 ---- <!-- Begin the document --> ! <sect>Statement of intent<p> ! Generally speaking, the driver is intended for all ATI video adapters, ! providing maximum video function within hardware limitations. ! The driver is also intended to optionally provide the same level of support for ! generic VGA or 8514/A adapters. ! This driver is still being actively developed, meaning that it currently does ! not yet fully meet these goals.<p> ! The driver will provide ! <itemize> ! <item>accelerated support if an ATI accelerator is detected <it>and</it> the ! user has not requested that this support be disabled; otherwise ! <item>accelerated support if a non-ATI 8514/A-capable adapter is detected ! <it>and</it> the user has requested such support; otherwise ! <item>unaccelerated SuperVGA support if an ATI VGA-capable adapter is detected; ! otherwise ! <item>generic VGA support if a non-ATI VGA-capable adapter is detected ! <it>and</it> the user has requested such support. ! </itemize> ! Thus, the support provided not only depends on what the driver detects in the ! system, but also, on what the user specifies in the XF86Config file. ! See the "XF86Config specifications" section below for details.<p> ! If none of the above conditions are met, the ATI driver will essentially ! disable itself to allow other drivers to examine the system.<p> ! <sect>A note on acceleration<p> ! The meaning of "acceleration", as used in this document, needs to be clarified. ! Two of the many components in an accelerator are the CRT controller (CRTC) and ! the Draw Engine. ! This is in addition to another CRTC that, generally, is also present in the ! system (often in the same chip) and typically provides EGA, VGA or SuperVGA ! functionality.<p> ! A CRTC is the component of a graphics controller that is responsible for ! reading video memory for output to the screen. ! A Draw Engine is an accelerator component that can be programmed to manipulate ! video memory contents, thus freeing the CPU for other tasks.<p> ! When the VGA CRTC is used, all drawing operations into video memory are the ! responsibility of the system's CPU, i.e. no Draw Engine can be used. ! On the other hand, if the accelerator's CRTC is chosen to drive the screen, ! the Draw Engine can also be used for drawing operations, although the CPU can ! still be used for this purpose if it can access the accelerator's video ! memory.<p> ! Video acceleration refers to the programming of an accelerator's Draw Engine to ! offload drawing operations from the CPU, and thus also implies the use of the ! accelerator's CRTC.<p> ! <sect>Current implementation for ATI adapters<p> ! The driver currently supports the SuperVGA capabilities of all ATI adapters ! except some early Mach8 and Mach32 adapters that do not provide the required ! functionality. ! This support works for monochrome, 16-colour and 256-colour video modes, if one ! of the following ATI graphics controller chips is present: <verb> ! VGAWonder series: 18800, 18800-1, 28800-2, 28800-4, 28800-5, 28800-6 ! Mach32 series: 68800-3, 68800-6, 68800AX, 68800LX ! Mach64 series: 88800GX-C, 88800GX-D, 88800GX-E, 88800GX-F, 88800CX, ! 264CT, 264ET, 264VT, 264GT (a.k.a. 3D Rage), 264VT-B, ! 264VT3, 264GT-B (a.k.a. 3D Rage II), 264GT3 (a.k.a. ! 3D Rage Pro)</verb> ! There is some support for the 264LT (ATI's recent entry into the laptop ! world), but it is untested.<p> ! The driver also supports 32K, 64K and 16M-colour modes on the 264xT series of ! adapters using the accelerator CRTC (but not the VGA CRTC). ! This support is as yet unaccelerated.<p> ! Adapters based on the above chips have been marketed under a rather large ! number of names over the years. Among them are: <verb> ! VGAWonder series: VGAWonder V3, VGAWonder V4, VGAWonder V5, VGAWonder+, ! VGAWonder XL, VGAWonder XL24, VGA Basic 16, VGA Edge, ! VGA Edge 16, VGA Integra, VGA Charger, VGAStereo F/X, ! VGA 640, VGA 800, VGA 1024, VGA 1024D, VGA 1024 XL, ! VGA 1024 DXL, VGA 1024 VLB ! Mach8 series: Graphics Ultra, Graphics Vantage, VGAWonder GT ! (None of the 8514/Ultra and 8514 Vantage series is ! supported at this time) ! Mach32 series: Graphics Ultra+, Graphics Ultra Pro, Graphics Wonder, ! Graphics Ultra XLR, Graphics Ultra AXO, VLB mach32-D, ! PCI mach32-D, ISA mach32 ! Mach64 series: Graphics Xpression, Graphics Pro Turbo, Win Boost, ! Win Turbo, Graphics Pro Turbo 1600, Video Xpression, ! 3D Xpression, Video Xpression+, 3D Xpression+, ! All-In-Wonder, All-In-Wonder PRO, 3D Pro Turbo, ATI-TV, ! XPERT@Play, XPERT@Work, XPERT XL</verb> ! VGAWonder, Mach8 and Mach32 ISA adapters are available with or without a ! mouse.<p> These adapters are available with a variety of clock generators and RAMDACs. ! The 264xT series of chips are integrated controllers, meaning that they include ! a programmable clock generator and a RAMDAC. ! See the "XF86Config specifications" section below for details.<p> ! This driver still does not provide support for accelerated drawing to the ! screen. ! This means that all drawing is done by the CPU, rather than by any accelerator ! present in the system. ! This can make opaque moves, for example, quite "jerky". ! Thus, given that IBM 8514/A and ATI Mach8 do not allow CPU access to their ! frame buffer, the driver will currently ignore these accelerators. ! Most Mach32 adapters provide both accelerated function and VGA functionality, ! but the driver currently only uses the VGA.<p> ! The driver *does* however support the accelerator CRTC present in all ATI ! Mach64 adapters. ! For 256-colour, and higher depth modes, this support will be used by default, ! although an XF86Config option can be specified to use the SuperVGA CRTC ! instead. ! A linear video memory aperture is also available in 256-colour and higher depth ! modes and enabled by default if a 264xT controller is detected or, on 88800 ! controllers, if the accelerator CRTC is used. ! XF86Config options are available to disable this aperture, or (on non-PCI ! adapters) enable it or move it to some other address.<p> ! <sect>Current implementation of generic VGA support for non-ATI adapters<p> ! Support for generic VGA with non-ATI adapters is also implemented, but has ! undergone only limited testing. ! The driver will intentionally disallow the use of this support with ATI ! adapters. ! This support must be explicitly requested through an XF86Config ChipSet ! specification. ! This prevents the current generic driver from being disabled.<p> ! This driver's generic VGA support is intended as an extension of that provided ! by the current generic driver. ! Specifically, within the architectural bounds defined by IBM's VGA standard, ! this driver will allow the use of any 256-colour mode, and any dot clock ! frequencies both of which allow for many more mode possibilities.<p> ! The driver will enforce the following limitations derived from IBM's original ! VGA implementation: ! <itemize> ! <item>There can only be a set of four (non-programmable) clocks to choose from. ! <item>Video memory is limited to 256kB in monochrome and 16-colour modes. ! <item>Video memory is limited to 64kB in 256-colour modes. ! <item>Interlaced modes are not available. ! </itemize> ! <sect>XF86Config specifications<p> ! Except for clocks, the driver does not require any XF86Config specifications ! of its own for default operation. ! The driver's behaviour can however be modified by the following ! specifications.<p> ! <sect1>ChipSet "name"<p> ! The default ChipSet name for this driver is "ati".<p> ! If "ativga" is specified instead, the driver will not use any ATI accelerator ! CRTC it detects, relying instead on any detected ATI VGA CRTC to provide the ! screen image.<p> ! A ChipSet name of "ibmvga" enables the driver's generic VGA support, but only ! for non-ATI adapters. ! If an ATI adapter is detected, the driver will operate as if "ativga" had been ! specified instead.<p> ! For compatibility with other XFree86 servers, both past and present, that ! support ATI adapters, the driver also recognizes "vgawonder", "mach8", "mach32" ! and "mach64" as chipset names. ! In this version of the driver, all such names are equivalent to "ati". ! In some future release, each name will have a different meaning to be documented at that time.<p> ! <sect1>Clocks<p> ! For the purpose of specifying a clock line in your XF86Config, one of four ! different situations can occur, as follows.<p> ! Those configuring the driver's generic VGA support for a non-ATI adapter, ! can skip ahead to the "Clocks for non-ATI adapters" section below. ! Those <it>not</it> trying to configure the driver for a Mach64 adapter, can ! skip ahead to the "Clocks for fixed clock generators on ATI adapters" section ! below.<p> ! The very earliest Mach64 adapters use fixed (i.e. non-programmable) clock ! generators. ! Very few of these (mostly prototypes) are known to exist, but if you have one ! of these, you can also skip ahead to the "Clocks for fixed clock generators on ! ATI adapters" section below.<p> ! The two cases that are left deal with programmable clock generators, which are ! used on the great majority of Mach64 adapters.<p> ! If you are uncertain which situation applies to your adapter, you can run a ! clock probe with the command "X -probeonly".<p> ! <sect2>Clocks for supported programmable clock generators<p> ! At bootup, video BIOS initialization programmes an initial set of frequencies. ! Two of these are reserved to allow the setting of modes that do not use a ! frequency from this initial set. ! One of these reserved slots is used by the BIOS mode set routine, the other by ! the particular driver used (e.g. MS-Windows, AutoCAD, X, etc.). ! The clock numbers reserved in this way are dependent on the particular clock ! generator used by the adapter.<p> ! The driver currently supports all programmable clock generators known to exist ! on Mach64 adapters. ! In this case, the driver will completely ignore any XF86Config clock ! specification, and programme the clock generator as needed by the modes used ! during the X session.<p> ! <sect2>Clocks for unsupported programmable clock generators<p> ! This case is unlikely to occur, but is documented for the sake of ! completeness.<p> ! In this situation, the driver will probe the adapter for clock frequencies ! unless XF86Config clocks are already specified. ! In either case, the driver will then attempt to normalize the clocks to one of ! the following specifications: <verb> + BIOS setting 1: + + Clocks 0.000 110.000 126.000 135.000 50.350 56.640 63.000 72.000 + 0.000 80.000 75.000 65.000 40.000 44.900 49.500 50.000 + 0.000 55.000 63.000 67.500 25.180 28.320 31.500 36.000 + 0.000 40.000 37.500 32.500 20.000 22.450 24.750 25.000</verb> + <verb> + BIOS setting 2: + + Clocks 0.000 110.000 126.000 135.000 25.180 28.320 31.500 36.000 + 0.000 80.000 75.000 65.000 40.000 44.900 49.500 50.000 + 0.000 55.000 63.000 67.500 12.590 14.160 15.750 18.000 + 0.000 40.000 37.500 32.500 20.000 22.450 24.750 25.000</verb> + <verb> + BIOS setting 3: + + Clocks 0.000 0.000 0.000 0.000 25.180 28.320 0.000 0.000 + 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 + 0.000 0.000 0.000 0.000 12.590 14.160 0.000 0.000 + 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000</verb> + If the driver matches the clocks to the third setting above, functionality will + be *extremely* limited (assuming the driver works at all).<p> + <sect2>Clocks for fixed clock generators on ATI adapters<p> + This section applies to all ATI adapters except all but the very earliest + Mach64's.<p> + One of the following clocks specifications (or an initial subset thereof) can + be used depending on what the adapter uses to generate dot clocks: + <verb> Crystals (VGA Wonder V3 and V4 adapters only): Clocks 50.000 56.644 0.000 44.900 44.900 50.000 0.000 36.000 *************** *** 129,170 **** 33.750 8.000 27.500 20.000 25.000 31.500 23.100 9.000 9.978 11.225 18.750 16.250 12.588 14.160 0.000 11.225</verb> Mach32 and Mach64 owners should only specify up to the first 32 frequencies.<p> - The oldest Mach64 adapters use one of the clock generators described above. - The possibilities for Mach64 adapters also include programmable clock - generators. - At bootup, video BIOS initialization programmes an initial set of frequencies. - Two of these are reserved to allow the setting of modes that do not use a - frequency from this initial set. - One of these reserved slots is used by the BIOS mode set routine, the other by - the particular driver used (MS-Windows, AutoCAD, X, etc.). - The clock numbers reserved in this way are dependent on the particular clock - generator used on the adapter.<p> - If the driver does not support the adapter's clock generator, it will try to - match the clocks to one of the following specifications. This matching will - occur whether or not the user specifies the clocks in XF86Config. - <verb> - BIOS setting 1: - - Clocks 0.000 110.000 126.000 135.000 50.350 56.640 63.000 72.000 - 0.000 80.000 75.000 65.000 40.000 44.900 49.500 50.000 - 0.000 55.000 63.000 67.500 25.180 28.320 31.500 36.000 - 0.000 40.000 37.500 32.500 20.000 22.450 24.750 25.000</verb> - <verb> - BIOS setting 2: - - Clocks 0.000 110.000 126.000 135.000 25.180 28.320 31.500 36.000 - 0.000 80.000 75.000 65.000 40.000 44.900 49.500 50.000 - 0.000 55.000 63.000 67.500 12.590 14.160 15.750 18.000 - 0.000 40.000 37.500 32.500 20.000 22.450 24.750 25.000</verb> - <verb> - BIOS setting 3: - - Clocks 0.000 0.000 0.000 0.000 25.180 28.320 0.000 0.000 - 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 - 0.000 0.000 0.000 0.000 12.590 14.160 0.000 0.000 - 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000</verb> - If the driver matches the clocks to the third setting above, functionality will - be *extremely* limited (assuming the driver works at all).<p> Other clock generators that have been used on ATI adapters (which can all be said to be clones of one of the above) might generate non-zero frequencies for those that are zero above, or vice-versa.<p> --- 267,272 ---- *************** *** 172,184 **** the clocks if it deems it appropriate to do so. Mach32 and Mach64 owners should note that this order is different than what they would use for the accelerated servers.<p> ! If the driver detects a supported programmable clock generator, it will ignore ! any XF86Config clock specification and programme the generator as needed by the ! modes to be used during the X session.<p> ! A clock probe, done with the command "X -probeonly", will help you decide which ! of the above to use for your particular adapter. ! If the server consistently reports that it has detected an unknown clock ! generator, please e-mail me the stderr output.<p> Modes can be derived from the information in XFree86's doc directory. If you do not specify a "modes" line in the display subsection of the appropriate screen section of your XF86Config, the driver will generate a --- 274,303 ---- the clocks if it deems it appropriate to do so. Mach32 and Mach64 owners should note that this order is different than what they would use for the accelerated servers.<p> ! <sect2>Clocks for non-ATI adapters<p> ! If no clocks are specified in the XF86Config, the driver will probe for four ! clocks, the second of which will be assumed to be 28.322MHz. ! You can include up to four clock frequencies in your XF86Config to specify the ! actual values used by the adapter. ! Any more will be ignored.<p> ! <sect1>Option "nolinear"<p> ! By default, the driver will enable a linear video memory aperture for ! 256-colour and higher depth modes if it is also using a Mach64 accelerator CRTC ! or an integrated Mach64 graphics chip. ! This option disables this linear aperture. ! Currently, this also disables support for more than 256 colours.<p> ! <sect1>MemBase address<p> ! This specification is only effective for non-PCI Mach64 adapters, and is used ! to override the CPU address at which the adapter will map its video memory. ! Normally, for non-PCI adapters, this address is set by a DOS install utility ! provided with the adapter. ! The MemBase option can also be used to enable the linear aperture in those ! cases where ATI's utility was not, or can not be, used.<p> ! For PCI adapters, this address is determined at system bootup according to the ! PCI Plug'n'Play specification which arbitrates the resource requirements of ! most devices in the system. ! This means the driver can not easily change the linear aperture address.<p> ! <sect1>Modelines<p> Modes can be derived from the information in XFree86's doc directory. If you do not specify a "modes" line in the display subsection of the appropriate screen section of your XF86Config, the driver will generate a *************** *** 185,262 **** default mode and attempt to use it. The timings for the default mode are derived from the timings of the mode (usually a text mode) in effect when the server is started.<p> ! <sect> What is the history of the driver?<p> ! The complete history of the driver is rather cloudy. ! The following is probably incomplete and inaccurate.<p> ! Apparently, <bf>Per Lindqvist</bf> (<it>pgd@compuram.bbt.se</it>) first got an ! ATI driver working with an early ATI card under X386 1.1a. ! This original driver may have actually been based on an non-functional ATI ! driver written by <bf>Roell</bf>. ! Then <bf>Doug Evans</bf> (<it>dje@cygnus.com</it>) ported the driver to the ATI ! VGA Wonder XL, trying in the process to make the driver work with all other ATI ! cards.<p> ! <bf>Rik Faith</bf> (<it>faith@cs.unc.edu</it>) obtained the X11R4 driver from ! Doug Evans in the summer of 1992, and ported the code to the X386 part of ! X11R5. ! This subsequently became part of XFree86.<p> ! I (<bf>Marc Aurele La France</bf>) took the driver over in the fall of 1993 ! after Rik got rid of his VGA Wonder card.<p> ! <sect> Miscellaneous notes<p> ! In all cases, virtual resolutions must be less than 4096 pixels wide. ! For VGAWonder V3 adapters with 256kB of video memory, and for all 264xT ! adapters, the 256-colour server will further limit virtual resolutions to less ! than 2048 pixels wide. ! These are hardware limits that cannot be circumvented.<p> ! Dot clocks greater than 80MHz cannot be used on most adapters as a way still ! needs to be discovered to make the VGA Wonder controller do pixel ! multiplexing.<p> ! Support for more than 8bpp colour depth is pending proper RAMDAC handling and ! banked framebuffer code for >8bpp.<p> ! Video memory corruption can still occur during mode switches on V3, V4 and V5 adapters. Symptoms of this problem include garbled fonts on return to text mode, and various effects (snow, dashed lines, etc) on initial entry into a graphics mode. In the first case, the workaround is to use some other means of restoring the text font. ! On Linux, this can be done with the kbd or svgalib packages. ! In the second case, xrefresh will usually cleanup the image.<p> ! Video memory banking does not work in the 16-colour and monochrome servers on ! V3, V4 and V5 adapters (with 512kB of video memory). ! This appears to be a hardware limitation. ! The driver's default behaviour has been changed to take this into consideration ! by limiting video memory to 256kB.<p> ! Interlaced modes do not work in the monochrome server on 28800-x adapters when ! using a virtual resolution that is 2048 pixels or wider. ! This appears to be a hardware limitation. ! The driver has been changed to prune modes accordingly.<p> ! Support for virtual resolutions using more than 1MB of video memory is still ! incomplete. ! Specifically, such support works on Mach32 adapters, and on 264xT adapters, ! but not on any other Mach64 adapters. ! On 88800GX and 88800CX adapters, this appears to be a hardware limitation. ! Consequently, the driver's default behaviour is to limit video memory to ! 1MB.<p> ! There is some controversy over whether or not clocks higher than 135MHz should ! be allowed on 264xT adapters. ! For now, clocks will be limited to 135MHz by default. This limit can only be increased (up to a driver-calculated absolute maximum) ! through the DACSpeed option in XF86Config. ! Be aware however that doing this is untested and might damage the adapter.<p> ! The default mode does not work on the more recent Mach64 adapters. ! This will be fixed in a future release by reading the programmable clock ! generator's registers.<p> ! Future development plans include addressing the above problems and using ! accelerated functionality.<p> ! Please e-mail any bug reports, comments, etc. to <bf>Marc Aurele La ! France</bf>, <it>tsi@ualberta.ca</it><p> <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/ati.sgml,v 3.15.2.1 1997/06/01 12:33:36 dawes Exp $ ! $TOG: ati.sgml /main/10 1997/07/19 10:34:45 kaleb $ </verb> </article> --- 304,464 ---- default mode and attempt to use it. The timings for the default mode are derived from the timings of the mode (usually a text mode) in effect when the server is started.<p> ! <sect>Known problems and limitations<p> ! There are several known problems or limitations related to the XFree86 ATI ! driver. ! They include:<p> ! <itemize> ! <item>A number of system lockups and blank screens have been reported when ! using PCI Mach64 adapters. ! The great majority of these problems have been found to be due to system ! aspects that are unrelated to this driver. ! As of this writing, these problems can be divided into three general areas:<p> ! Improper mouse protocol specification with some recent mice. ! Try different protocol specifications or another mouse.<p> ! A system conflict with APM. ! This problem is Linux-specific. ! There is a bug in kernels 2.0.31 or earlier that prevents proper APM operation. ! Upgrade to a more recent kernel or disable APM support.<p> ! The TV port on some Mach64 adapters needs to be disabled using an ATI utility ! that might or might not be supplied with the adapter. ! This problem is currently under investigation. ! <item>When using a Mach64's accelerator CRTC, the virtual resolution must be ! less than 8192 pixels wide. ! The VGA CRTC further limits the virtual resolution width to less than 4096 ! pixels, or to less than 2048 pixels for adapters based on 18800's (with 256kB ! of memory) and on Mach64 integrated controllers. ! These are hardware limits that cannot be circumvented. ! <item>Virtual resolutions requiring more than 1MB of video memory (256kB in the ! monochrome case) are not supported by the VGA CRTC on 88800GX and 88800CX adapters. + This is a hardware limit that cannot be circumvented. + <item>Due to hardware limitations, doublescanned modes are not supported by the + accelerator CRTC in 88800GX, 88800CX, 264CT and 264ET adapters. + <item>Monochrome interlaced modes are not supported on 18800-x and 28800-x when + using a virtual resolution that is 2048 pixels or wider. + This is yet another hardware limitation that cannot be circumvented. + <item>Video memory banking does not work in monochrome and 16-colour modes on + 18800 and 18800-1 adapters. + This appears to be another hardware limit, but this conclusion cannot be + confirmed at this time. + The driver's default behaviour in this case is to limit video memory to 256kB. + <item>The default mode does not work on the more recent Mach64 adapters. + This problem is caused by the driver's attempt to use an incorrect dot clock + for the mode. + This will be fixed in a future release by reading the programmable clock + generator's registers to determine the actual clock used by the mode. + <item>Most XFree86 servers assume that the video state on entry to the server + is a text mode. + This assumption is known to cause problems on operating systems which invoke + the server from a graphics mode. + DBCS versions of OS/2, primarily used in Asia, are examples of such operating + systems. + The solution, for now, is to somehow coerce the OS to invoke the server from a + text mode. + This driver has been changed to simply assume the mode on entry uses the + adapter's VGA CRTC (in text or graphics modes). + While this action alleviates the problem somewhat, it does not completely solve + it, as the server could still be invoked from an accelerator mode. + To properly fix this problem for all XFree86 servers is a large project, and + will probably not get done anytime soon. + <item>Video memory corruption can still occur during mode switches on 18800 and + 18800-1 adapters. Symptoms of this problem include garbled fonts on return to text mode, and various effects (snow, dashed lines, etc) on initial entry into a graphics mode. In the first case, the workaround is to use some other means of restoring the text font. ! On Linux, this can be accomplished with the kbd or svgalib packages. ! In the second case, xrefresh(1) will usually clean up the image. ! No solution to this problem is currently known. ! <item>There is some controversy over what the maximum allowed clock frequency ! should be on 264xT adapters. ! For now, clocks will, by default, be limited to 135MHz, 170MHz, 200MHz or ! 230MHz, depending on the specific controller. This limit can only be increased (up to a driver-calculated absolute maximum) ! through the DACSpeed specification in XF86Config. ! Be aware however that doing so is untested and might damage the adapter. ! <item>Except as in the previous item, clocks are limited to 80MHz on most ! adapters, although many are capable of higher frequencies. ! This will be fixed in a future release. ! </itemize> ! Support for the following will be added in a future release: ! <itemize> ! <item>Mach32 accelerator's CRTC. ! This support is the first step towards accelerated support for Mach32's, ! Mach8's, 8514/A's and other clones. ! <item>Colour depth greater than 8, where permitted by the hardware. ! <item>Mach64, Mach32, Mach8 and 8514/A Draw Engines. ! <item>Hardware cursors. ! </itemize> ! Support, through this driver, for 3D acceleration, "TV in a window" and video ! capture, as implemented in some ATI adapters, is still in exploratory stages. ! There is currently no framework within an XFree86 server for these functions, ! although one is in the final stages of development. ! Also, ATI has not yet released a register-level specification for these, except ! under non-disclosure agreements.<p> ! <sect>Reporting problems<p> ! If you are experiencing problems that are not already recorded in this ! document, first ensure that you have the latest current release of this driver ! and XFree86. ! Check the server's stderr output and <htmlurl ! name="ftp://ftp.xfree86.org/pub/XFree86" ! url="ftp://ftp.xfree86.org/pub/XFree86"> if you are uncertain.<p> ! Secondly, please check XFree86's doc directory for additional information.<p> ! Thirdly, do not forget to read <htmlurl name="http://www.xfree86.org/FAQ" ! url="http://www.xfree86.org/FAQ">.<p> ! Fourth, a scan through the comp.windows.x.i386unix and comp.os.linux.x ! newsgroups using your favorite archiving service can also prove useful in ! resolving problems.<p> ! If you are still experiencing problems, you can send me e-mail at ! <it>tsi@ualberta.ca</it>. ! Please be as specific as possible when describing the problem(s), and include ! an unedited copy of the server's stderr and the XF86Config file used.<p> ! <sect>Driver history<p> ! The complete history of the driver is rather cloudy. ! The following is more than likely to be incomplete and inaccurate.<p> ! Apparently, Per Lindqvist first got a driver working with an early ATI adapter ! under X386 1.1a. ! This original driver might have actually been based on a non-functional ATI ! driver written by Thomas Roell (currently of Xi Graphics).<p> ! Then Doug Evans (<it>dje@cygnus.com</it>) added support for the ATI VGA Wonder ! XL, trying in the process to make the driver work with all other ATI adapters ! available at the time.<p> ! Rik Faith (<it>faith@cs.unc.edu</it>) obtained the X11R4 driver from Doug Evans ! in the summer of 1992 and ported the code to the X386 part of X11R5. ! This subsequently became part of XFree86.<p> ! I (Marc Aurele La France) took over development and maintenance of the driver ! in the fall of 1993 after Rik got rid of his VGA Wonder card.<p> ! <sect>Driver versions<p> ! Due to the introduction of loadable drivers in an upcoming XFree86 release, it ! has become necessary to track driver versions separately. ! With this release of the driver, I am introducing the following version ! numbering scheme.<p> ! Version 1 of this driver is the one I inherited from Rik Faith. ! This is the version found in XFree86 2.0 and 2.1.<p> ! Version 2 is my first rewrite of this code which only ended up being a ! partially unsuccessful attempt at generalizing the driver for all VGA Wonder, ! Mach32, and early Mach64 adapters. ! Various releases of this version of the driver can be found in XFree86 2.1.1, ! 3.1, 3.1.1 and 3.1.2.<p> ! Version 3 represents my second rewrite (although a rather lame one as rewrites ! go). ! Into version 3, I introduced clock programming for Mach64 adapters and merged ! in the old ati_test debugging tool. ! This is the version found in XFree86 3.2, 3.3 and 3.3.1.<p> ! Version 4 is a rather major restructuring of version 3, which became larger ! than I could comfortably handle in one source file. ! This version will make it quite a bit easier to introduce new function such as ! acceleration, additional colour depths, and so on. ! This is the version found in XFree86 3.3.2.<p> <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/ati.sgml,v 3.15.2.2 1998/02/01 16:04:54 robin Exp $ ! $TOG: ati.sgml /main/11 1998/03/06 16:42:51 kaleb $ </verb> </article> *** ./programs/Xserver/hw/xfree86/doc/sgml/chips.sgml@@/PUBLIC-LATEST Sun Aug 10 13:03:46 1997 --- xc/programs/Xserver/hw/xfree86/doc/sgml/chips.sgml Fri Mar 6 16:41:18 1998 *************** *** 297,303 **** One machine known to work well with this option is the Toshiba 720CDT. Note that newer machines often have an MClk greater than 38MHz, and so this option might actually slower the machine down. This option ! is generally not recommended. </descrip> <sect> Modelines <p> --- 297,320 ---- One machine known to work well with this option is the Toshiba 720CDT. Note that newer machines often have an MClk greater than 38MHz, and so this option might actually slower the machine down. This option ! is generally not recommended and is superseded by the ! "<tt>Set_MemClk</tt>" option. ! <tag> ! DacSpeed 80.000 ! </tag> ! The server will limit the maximum dotclock to a value as specified ! by the manufacturer. This might make certain modes impossible ! to obtain with a reasonable refresh rate. Using this option the ! user can override the maximum dot-clock and specify any value they ! prefer. Use caution with this option, as driving the video processor ! beyond its specifications might cause damage. ! <tag> ! Set_MemClk 38.000 (Chips 65550/54/55 and 68554) ! </tag> ! This option sets the internal memory clock (MCLK) registers to 38MHz ! or some other value. Use caution as excess heat generated by ! the video processor if its specifications are exceeded might cause ! damage. However careful use of this option might boost performance. </descrip> <sect> Modelines <p> *************** *** 596,602 **** bugs and extensively testing this server before its inclusion in XFree 3.2 <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/chips.sgml,v 3.12.2.6 1997/07/28 14:17:31 dawes Exp $ </verb> </article> --- 613,619 ---- bugs and extensively testing this server before its inclusion in XFree 3.2 <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/chips.sgml,v 3.12.2.7 1998/01/31 14:23:27 hohndel Exp $ </verb> </article> *** ./programs/Xserver/hw/xfree86/doc/sgml/cirrus.sgml@@/PUBLIC-LATEST Sat Jul 19 10:34:57 1997 --- xc/programs/Xserver/hw/xfree86/doc/sgml/cirrus.sgml Fri Mar 6 16:41:23 1998 *************** *** 6,12 **** <title> Information for Cirrus Chipset Users <author> Harm Hanemaayer (<it>H.Hanemaayer@inter.nl.net</it>), Randy Hendry (<it>randy@sgi.com</it>) (64xx), ! Corin Anderson (<it>corina@bdc.cirrus.com</it>) <date> 24 May 1997 <!-- Table of contents --> --- 6,12 ---- <title> Information for Cirrus Chipset Users <author> Harm Hanemaayer (<it>H.Hanemaayer@inter.nl.net</it>), Randy Hendry (<it>randy@sgi.com</it>) (64xx), ! Corin Anderson (<it>corina@the4cs.com</it>) <date> 24 May 1997 <!-- Table of contents --> *************** *** 203,209 **** chip. For the 5429, the <tt>&dquot;mmio&dquot;</tt> option may be used to enable it, but it has not been tested. ! Finally, if you have 546X chip, it will be on the PCI bus. As such, there is no problem about memory mapped I/O or linear frame buffer address spaces running into system memory. The PCI spaces are mapped way up near the 4GB point. Because the mmio and linear frame buffer don't conflict at all on --- 203,210 ---- chip. For the 5429, the <tt>&dquot;mmio&dquot;</tt> option may be used to enable it, but it has not been tested. ! Finally, if you have 546X chip, it will be on either a PCI or AGP bus. ! As such, there is no problem about memory mapped I/O or linear frame buffer address spaces running into system memory. The PCI spaces are mapped way up near the 4GB point. Because the mmio and linear frame buffer don't conflict at all on *************** *** 229,237 **** is likely to help with problems related to bugs in acceleration functions, and perhaps high dot clocks and DRAM timing, at the cost of performance (which will still be reasonable on a local bus). ! <tag>Option &dquot;fast_dram&dquot; &dquot;med_dram&dquot; &dquot;slow_dram&dquot; (5424/6/8/9, 543x, 5446) </tag> ! These options set the internal memory clock (MCLK) register to another value. The default value programmed by the BIOS is usually OK, don't mess with these options unless absolutely required. --- 230,240 ---- is likely to help with problems related to bugs in acceleration functions, and perhaps high dot clocks and DRAM timing, at the cost of performance (which will still be reasonable on a local bus). ! <tag>Option &dquot;fast_dram&dquot; &dquot;med_dram&dquot; ! &dquot;slow_dram&dquot; (5424/6/8/9, 543x, 5446, 546x) </tag> ! These options set the internal memory clock (MCLK, or BCLK for ! the 546x) register to another value. The default value programmed by the BIOS is usually OK, don't mess with these options unless absolutely required. *************** *** 287,299 **** the 5429 and 5430 is probably 60 MHz (0x22). Current revisions of the 5434 (E and greater) support 60 MHz MCLK in graphics modes, and the driver will program this automatically. If it causes ! problems, use the "slow_dram" option. The driver takes the MCLK into account for clock limits that are determined by DRAM bandwidth. ! If you are not having any problems (performance or stability at ! high dot clocks), it is best not to use any of the DRAM options. <tag> Option &dquot;no_bitblt&dquot; </tag> --- 290,309 ---- the 5429 and 5430 is probably 60 MHz (0x22). Current revisions of the 5434 (E and greater) support 60 MHz MCLK in graphics modes, and the driver will program this automatically. If it causes ! problems, use the <tt>"slow_dram"</tt> option. The driver takes the MCLK into account for clock limits that are determined by DRAM bandwidth. ! For the 546x chips, the BCLK is the Rambus access clock. ! Typical values live in the range of 258 MHz to 300 MHz. If you ! have troubles, such as a black checkerboard pattern on the ! screen, try using the <tt>"med_dram"</tt> or ! <tt>"slow_dram"</tt> options. ! ! In all cases, if you are not having any problems (performance ! or stability at high dot clocks), it is best not to use any of ! the DRAM options. <tag> Option &dquot;no_bitblt&dquot; </tag> *************** *** 402,408 **** engine on any chip for which it is the default mode of operation. <tag> ! Option &dquot;sw_cursor&dquot; (542x/3x/46) </tag> This disables use of the hardware cursor provided by the chip. Try this if the cursor seems to have problems. In particular, use this --- 412,418 ---- engine on any chip for which it is the default mode of operation. <tag> ! Option &dquot;sw_cursor&dquot; (542x/3x/46/6x) </tag> This disables use of the hardware cursor provided by the chip. Try this if the cursor seems to have problems. In particular, use this *************** *** 430,435 **** --- 440,455 ---- </tag> Disable automatic stretching (horizontal and vertical expansion) of 640x480 on a 800x600 LCD. + <tag> + Option &dquot;pci_retry&dquot; (546x) + </tag> + Enables a performance feature for PCI based cards. When this + feature is enabled, the driver code will attempt to transmit + data on the PCI bus as fast as possible. For the most part, + this option is safe, but may cause trouble with other PCI + devices such as PCI network cards, sound cards, SCSI + controllers, etc. When this option is not selected, a safer + approach (polling the VGA's command queue) is taken. </descrip> *************** *** 747,752 **** --- 767,778 ---- card and/or motherboard design. It has been observed on some PCI 5428-based cards (which are very rare, since the 5428 chip doesn't support PCI). + <tag> + No mouse cursor, or cursor appears twice on screen + </tag> + With high dot clocks, the graphics card's hardware cursor + doesn't operate correctly. Try option <tt>"sw_cursor"</tt> or + use a lower screen refresh. </descrip> For other screen drawing related problems, try the <tt>"noaccel"</tt> option (if <tt>"no_bitblt"</tt> doesn't help). *************** *** 881,893 **** </itemize> <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/cirrus.sgml,v 3.23.2.1 1997/05/24 08:36:08 dawes Exp $ ! $TOG: cirrus.sgml /main/13 1997/07/19 10:34:59 kaleb $ </verb> </article> --- 907,919 ---- </itemize> <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/cirrus.sgml,v 3.23.2.3 1998/02/20 23:10:31 dawes Exp $ ! $TOG: cirrus.sgml /main/14 1998/03/06 16:43:01 kaleb $ </verb> </article> *** ./programs/Xserver/hw/xfree86/doc/sgml/isc.sgml@@/PUBLIC-LATEST Sat Jul 19 10:35:11 1997 --- xc/programs/Xserver/hw/xfree86/doc/sgml/isc.sgml Fri Mar 6 16:41:28 1998 *************** *** 4,10 **** <!-- made up title --> <title> Information for ISC Users <author> Michael Rohleder ! <date> 13 January 1997 <toc> <sect> X11R6/XFree86&tm; on Interactive Unix <p> --- 4,10 ---- <!-- made up title --> <title> Information for ISC Users <author> Michael Rohleder ! <date> 11 January 1998 <toc> <sect> X11R6/XFree86&tm; on Interactive Unix <p> *************** *** 31,41 **** <sect> Things needed for compiling the sources<p> <descrip> ! <tag> gcc-2.x.x </tag> Use the highest number for x you found. Fresco will only build 2.6.3 and later. ! I'd tried gcc Version 2.5.8, 2.6.0, 2.6.2 and 2.6.3. ! I'm currently using 2.7.2. <p> Since 2.6.3 the current source tree should be able to compile with a little bit more Optimization: --- 31,41 ---- <sect> Things needed for compiling the sources<p> <descrip> ! <tag> gcc </tag> Use the highest number for x you found. Fresco will only build 2.6.3 and later. ! I'd tried gcc Version 2.5.8, 2.6.0, 2.6.2, 2.6.3 and 2.7.2. ! Current: 2.7.2.3 <p> Since 2.6.3 the current source tree should be able to compile with a little bit more Optimization: *************** *** 50,56 **** <tag> libg++-2.x.x </tag> The needed g++ Libraries for use with g++ 2.x.x. As this is only necessary for Fresco, it isn't needed anymore since X11R6.1. ! <tag> binutils-2.5.2 </tag> You could use the assembler and linker the assembler is most preferred,and the linker is needed at least if you want to link libFresco.a within a Program. --- 50,56 ---- <tag> libg++-2.x.x </tag> The needed g++ Libraries for use with g++ 2.x.x. As this is only necessary for Fresco, it isn't needed anymore since X11R6.1. ! <tag> binutils </tag> You could use the assembler and linker the assembler is most preferred,and the linker is needed at least if you want to link libFresco.a within a Program. *************** *** 57,62 **** --- 57,63 ---- Don't use strip and ar/ranlib, the first generates buggy binaries when stripping (at least on my machines) and the last requires the use of ranlib after creating an archive, this is not configured. + Current: 2.8.1.0.15 (Used: as, ld, ar, strip) <tag> gnu-malloc </tag> Due to better memory usage we should use GNU's malloc library on systems where possible. *************** *** 68,73 **** --- 69,82 ---- to your needs, if it isn't like the default <tt>-L/usr/local/lib -lgmalloc</tt>. + <tag> inline-math (optional)</tag> + This is the "original" inline-math package available at your + favorite Linux Mirror. + + Use <tt>#define UseInlineMath YES</tt> + inside host.def to enable it. Please note the changes section + what else to do, to use this package. + </descrip> <sect> Changes to the System Header Files<p> *************** *** 152,158 **** --- 161,204 ---- }; #endif </verb> + <p> + <sect1><tt>/usr/include/math.h</tt><p> + To use the Inline Math package you have to change your existing + math.h. Please note, the way I include the new Header file, is + different than suggested in inline-math's README. + + Please add the following at the bottom of math.h, before the last + #endif + <verb> + #if defined(UseInlineMath) + + /* Needed on ISC __CONCAT, PI */ + #ifndef __CONCAT + /* + * The __CONCAT macro is used to concatenate parts of symbol names, e.g. + * with "#define OLD(foo) __CONCAT(old,foo)", OLD(foo) produces oldfoo. + * The __CONCAT macro is a bit tricky -- make sure you don't put spaces + * in between its arguments. __CONCAT can also concatenate double-quoted + * strings produced by the __STRING macro, but this only works with ANSI C. + */ + #if defined(__STDC__) || defined(__cplusplus) + #define __CONCAT(x,y) x ## y + #define __STRING(x) #x + #else /* !(__STDC__ || __cplusplus) */ + #define __CONCAT(x,y) x/**/y + #define __STRING(x) "x" + #endif /* !(__STDC__ || __cplusplus) */ + #endif + + #ifndef PI + #define PI M_PI + #endif + + #include "/usr/local/include/i386/__math.h" + #endif + </verb> + <sect> make World <p> <code> *************** *** 175,187 **** inside xf86site.def.<p> A build on ISC 4.x only needs -DISC40 defined in the BOOTSTRAPCFLAGS ( -DISC30 will be included automatically ).<p> ! Note: if you still use Version 4.0, or you want to build ! binaries on Version 4.1 which should run on 4.0, you have ! to set <tt> #define UseChmod YES </tt> inside your host.def.<p> (the fchmod function isn't available on 4.0, so it won't compile, ! and binaries from 4.1 won't run cause of the unsupported System call) ! On Versions less 4.0 this will be the default. <tag>-DSYSV [-Di386]</tag> standard defines for SystemV Release3 on x86 platform. --- 221,235 ---- inside xf86site.def.<p> A build on ISC 4.x only needs -DISC40 defined in the BOOTSTRAPCFLAGS ( -DISC30 will be included automatically ).<p> ! Note: due to some incompatibilities between ISC 4.0 and 4.1, the default ! is to build for ISC4.0, even if you build on 4.1. ! If you want to build only for 4.1 you should ! set <tt> #define IscCompileVersion 410 </tt> inside your host.def.<p> (the fchmod function isn't available on 4.0, so it won't compile, ! and binaries from 4.1 won't run cause of the unsupported System call ! The libraries build for 4.1 couldn't be used with 4.0 Systems, due ! to some functions not available on 4.0) <tag>-DSYSV [-Di386]</tag> standard defines for SystemV Release3 on x86 platform. *************** *** 302,307 **** --- 350,356 ---- This is an obsolete Extension. Anyway, if you want to include this Extension inside your build, you have to add: <tt>#define BuildMultibuffer YES</tt> inside xf86site.def + Please note, this Extension should be disabled when building the Loader Server. <sect> Sample Definitions <p> *************** *** 311,340 **** #ifdef BeforeVendorCF ! /* Only when building official binaries*/ ! /* ! #define InstallJapaneseDocs YES ! #define InstallEmptyHostDef */ ! /* Try MultiBuffer Extension */ ! #define BuildMultibuffer YES - /* Build all Contrib SW */ - #ifdef XF86Contrib - #undef XF86Contrib - #endif - - /* gcc 2.6.3 tested Optimization Flags */ - # define DefaultGcc2i386Opt -O2 -fstrength-reduce -malign-loops=2 -malign-jumps=2 -malign-functions=2 - - /* binaries which should run on ISC 4.0 or for the build on a real 4.0 System */ - # define UseChmod YES - - /* For a POSIXized build on Interactive maybe needed to use gcc2.7.2 */ - # define UsePosix YES - /* Use GNUs MallocLibrary (and the Location for the Lib) */ # define UseGnuMalloc YES # define GnuMallocLibrary -L/usr/local/lib -lgnumalloc --- 360,378 ---- #ifdef BeforeVendorCF ! /* ISC 4.1Mu - build only for 4.1 ! #define IscCompileVersion 410 */ + /* Use inline Math from linux ;-) package inline-math-2.6.tar.gz */ + /* should be available on your favorite linux ftp */ + # define UseInlineMath YES ! /* Use cbrt from liboptm.a (Interactive icc Compiler) */ ! /* ! */ ! # define HasCbrt YES /* Use GNUs MallocLibrary (and the Location for the Lib) */ # define UseGnuMalloc YES # define GnuMallocLibrary -L/usr/local/lib -lgnumalloc *************** *** 365,371 **** #define HasTk YES #define HasTcl YES - #endif /* BeforeVendorCF */ </verb> <sect> Installation <p> --- 403,408 ---- *************** *** 398,403 **** --- 435,450 ---- some additional Fonts and Terminal files. </code> + You also should increase MAXUMEM to its maximum, else + programs may die with: + <code> + X Error of failed request: BadAlloc (insufficient resources for operation) + Major opcode of failed request: 53 (X_CreatePixmap) + Serial number of failed request: 37791 + Current serial number in output stream: 37822 + Widget hierarchy of resource: unknown + </code> + <sect>Using … <p> <itemize> *************** *** 493,505 **** <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/isc.sgml,v 3.18 1997/01/25 03:22:23 dawes Exp $ ! $TOG: isc.sgml /main/9 1997/07/19 10:35:13 kaleb $ </verb> </article> --- 540,552 ---- <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/isc.sgml,v 3.18.2.2 1998/02/20 23:10:31 dawes Exp $ ! $TOG: isc.sgml /main/10 1998/03/06 16:43:06 kaleb $ </verb> </article> *** /dev/null Tue Jun 30 11:47:29 1998 --- xc/programs/Xserver/hw/xfree86/doc/sgml/mouse.sgml Fri Mar 6 16:41:34 1998 *************** *** 0 **** --- 1,656 ---- + <!DOCTYPE linuxdoc PUBLIC "-//XFree86//DTD linuxdoc//EN"> + + <article> + <title>Mouse Support in XFree86 + <author>Kazutaka Yokota + <date>28 February 1998 + <toc> + + <sect>Introduction <p> + + This document describes mouse support in XFree86 3.3.2, whose + X servers have the revised mouse driver. + + Mouse configuration has often been mysterious task for + novice users. + However, once you learn several basics, it is straightforward + to choose options in <tt>XF86Setup</tt> or write the <tt>"Pointer"</tt> + section in the <tt>XF86Config</tt> file by hand. + + <sect>Supported Hardware <p> + + XFree86 X servers support three classes of mice: + serial, bus and PS/2 mice. + + <descrip> + <tag>Serial mouse</tag> + The serial mouse has been the most popular pointing device for + PCs. + There have been numerous serial mouse models from a number of + manufactures. + Despite the wide range of variations, there have been relatively + few protocols (data format) with which the serial mouse talks + to the host computer. + + The modern serial mouse conforms to the PnP COM device specification + so that the host computer can automatically detect the mouse + and load an appropriate driver. + The XFree86 3.3.2 X servers support this specification and can detect + popular PnP serial mouse models. + + <tag>Bus mouse</tag> + The bus mouse connects to a dedicated interface card in an expansion + slot. + Some video cards, notably those from ATI, and integrated I/O + cards may also have a bus mouse connector. + Some bus mice are known as `InPort mouse'. + + Note that some mouse manufactures have sold a package including a serial mouse + and a serial interface card. + Don't confuse this type of products with the genuine bus mouse. + + <tag>PS/2 mouse</tag> + They are sometimes called `Mouse-port mouse'. + The PS/2 mouse is becoming increasingly common and popular. + + The PS/2 mouse is an intelligent device and may have more than + three buttons and a wheel or a roller. + The PS/2 mouse is usually compatible with the original PS/2 mouse from IBM + immediately after power up. + The PS/2 mouse with additional features requires a specialized + initialization procedure to enable these features. + Without proper initialization, it behaves as though it were an ordinary + two or three button mouse. + </descrip> + + Many mice nowadays can be used both as a serial mouse and as a PS/2 mouse. + They has a logic to distinguish which interface it is connected to. + However, the mouse which is not marketed as compatible with both + serial and PS/2 mouse interface lacks this logic and cannot be + used in such a way, even if you can find an appropriate + adapter with which you can connect the PS/2 mouse to a serial port + or visa versa. + + XFree86 now supports the mouse with a wheel, a roller or a knob. + Its action is detected as the Z (third) axis motion of the mouse. + As the X server or clients normally do not use the Z axis movement of the + pointing device, a new configuration option, <tt>ZAxisMapping</tt>, + is provided to assign the Z axis movement to another axis or a pair + of buttons (see below). + + <sect>OS Support for Mice <p> + + <sect1>Summary of Supported Mouse Protocol Types <p> + <verb> + Protocol Types + serial PnP BusMouse PS/2 Extended PS/2 + OS platforms protocols serial protocol protocol protocols + "Auto" "BusMouse" "PS/2" "xxxPS/2" + -------------------------------------------------------------------- + BSD/OS Ok ? ? ? ? + FreeBSD Ok Ok Ok Ok SP*1 + FreeBSD(98) Ok ? Ok NA NA + Interactive Unix Ok NA ?*1 ?*1 NA + Linux Ok Ok Ok Ok Ok + Linux/98 Ok ? Ok NA NA + LynxOS Ok NA Ok Ok NA + NetBSD Ok Ok Ok SP*1 NA + NetBSD/pc98 Ok ? Ok NA NA + OpenBSD Ok Ok Ok Ok*1 NA + OS/2 SP*2 SP*2 SP*2 SP*2 SP*2 + SCO Ok ? SP*1 SP*1 NA + Solaris 2.x Ok NA*1 ?*1 Ok NA + SVR4 Ok NA*1 SP*1 SP*1 NA + PANIX Ok ? SP*1 SP*1 NA + + Ok: support is available, NA: not available, ?: untested or unknown. + SP: support is available in a different form + + *1 Refer to the following sections for details. + *2 XFree86/OS2 will support any type of mouse that the OS supports, + whether it is serial, bus mouse, or PnP type. + + </verb> + + <sect1>BSD/OS <p> + No testing has been done with BSD/OS. + + <sect1>FreeBSD <p> + FreeBSD supports the <tt>"SysMouse"</tt> protocol which must be + specified when the <tt>moused</tt> daemon is running in versions 2.2.1 + or later. + + FreeBSD versions 2.2.5 or earlier do not support extended PS/2 + mouse protocols (<tt>"xxxPS/2"</tt>). + Always specify the <tt>"PS/2"</tt> protocol for any PS/2 mouse + in these versions regardless of the brand of the mouse. + + FreeBSD versions 2.2.6 or later include the kernel-level + support for these mice. + Specify the <tt>"PS/2"</tt> or <tt>"Auto"</tt> protocol and + the X server will automatically make use of the kernel-level support. + In fact, you may always specify <tt>"Auto"</tt> to any mouse in these + versions unless the mouse is an old serial model which doesn't support PnP. + + <sect1>FreeBSD(98) <p> + The PS/2 mouse is not supported. + + <sect1>Interactive Unix <p> + The PnP serial mouse support (the <tt>"Auto"</tt> protocol) is not + supported for the moment. + + The bus mouse and PS/2 mouse should be supported by using the + appropriate device drivers. + Use <tt>/dev/mouse</tt> for the <tt>"BusMouse"</tt> protocol + and <tt>/dev/kdmouse</tt> for the <tt>"PS/2"</tt> protocol. + These protocols are untested but may work. + Please send success/failure reports to + <it/<michael.rohleder@stadt-frankfurt.de>/. + + <sect1>Linux <p> + All protocol types should work. + + <sect1>Linux/98 <p> + The PS/2 mouse is not supported. + + <sect1>LynxOS <p> + The PnP serial mouse support (the <tt>"Auto"</tt> protocol) is disabled in + LynxOS, because of limited TTY device driver functionality. + + <sect1>NetBSD <p> + NetBSD does not support extended PS/2 mouse protocols (<tt>"xxxPS/2"</tt>). + The PS/2 mouse device driver <tt>/dev/pms</tt> emulates the bus mouse. + Therefore, you should always specify the <tt>"BusMouse"</tt> protocol for + any PS/2 mouse regardless of the brand of the mouse. + + <sect1>NetBSD/pc98 <p> + The PS/2 mouse is not supported. + + <sect1>OpenBSD <p> + OpenBSD does not support extended PS/2 mouse protocols (<tt>"xxxPS/2"</tt>). + + The PS/2 mouse device driver <tt>/dev/pms</tt> emulates the bus mouse. + Specify the <tt>"BusMouse"</tt> protocol for + any PS/2 mouse regardless of the brand of the mouse when using this device. + + The raw PS/2 mouse device driver <tt>/dev/psm</tt> uses the standard PS/2 + mouse protocol. + Therefore, you should specify the <tt>"PS/2"</tt> protocol for + any PS/2 mouse regardless of the brand of the mouse when using this device. + + <sect1>OS/2 <p> + XFree86/OS2 always uses the native mouse driver of the operating system + and will support any type of pointer that the OS supports, whether it is + serial, bus mouse, or PnP type. + If the mouse works under Presentation Manager, + it will also work under XFree86/OS2. + + Always specify <tt>"OSMouse"</tt> as the protocol type. + + <sect1>SCO <p> + The bus and PS/2 mouse are supported with the <tt>"OSMouse"</tt> + protocol type. + + The <tt>"OSMouse"</tt> may also be used with the serial mouse. + + <sect1>Solaris <p> + Testing has been done with Solaris 2.5.1 and 2.6. Logitech and + Microsoft bus mice + have not been tested, but might work with the <tt>/dev/logi</tt> and + <tt>/dev/msm</tt> devices. + Standard 2 and 3 button PS/2 mice work with the <tt>"PS/2"</tt> protocol + type and the <tt>/dev/kdmouse</tt> device. + The PnP serial mouse support (the <tt>"Auto"</tt> protocol) has been tested + and does not work. + + <sect1>SVR4 <p> + The bus and PS/2 mouse may be supported with the <tt>"Xqueue"</tt> + protocol type. + + The <tt>"Xqueue"</tt> may also be used with the serial mouse. + + The PnP serial mouse support (the <tt>"Auto"</tt> protocol) is not + tested. + + <sect1>PANIX <p> + The PC/AT version of PANIX supports the bus and PS/2 mouse with the + <tt>"Xqueue"</tt> protocol type. + The PC-98 version of PANIX supports the bus mouse with the + <tt>"Xqueue"</tt> protocol type. + + <sect>Configuring Your Mouse <p> + + Before using the <tt>XF86Setup</tt> or <tt>xf86config</tt> programs + to set up mouse configuration, you must identify the interface type, + the device name and the protocol type of your mouse. + Blindly trying every possible combination of mouse settings + will lead you nowhere. + + The first thing you need to know is the interface type + of the mouse you are going to use. + It can be determined by looking at the connector of the mouse. + The serial mouse has a D-Sub female 9- or 25-pin connector. + The bus mice have either a D-Sub male 9-pin connector + or a round DIN 9-pin connector. + The PS/2 mouse is equipped with a small, round DIN 6-pin connector. + Some mice come with adapters with which the connector can + be converted to another. If you are to use such an adapter, + remember that the connector at the very end of the mouse/adapter pair is + what matters. + + The next thing to decide is a device node to use for the given interface. + For the bus and PS/2 mice, there is little choice; + your OS most possibly offers just one device node each + for the bus mouse and PS/2 mouse. + There may be more than one serial port to which the serial + mouse can be attached. + + The next step is to guess the appropriate protocol type for the mouse. + The X server may be able to select a protocol type for the given mouse + automatically in some cases. + Otherwise, the user has to choose one manually. + Follow the guidelines below. + + <descrip> + <tag>Bus mouse</tag> + The bus and InPort mice always use <tt>"BusMouse"</tt> + protocol regardless of the brand of the mouse. + + Some OSs may allow you to specify <tt>"Auto"</tt> as the + protocol type for the bus mouse. + + <tag>PS/2 mouse</tag> + The <tt>"PS/2"</tt> protocol should always be tried first for the PS/2 mouse + regardless of the brand of the mouse. + Any PS/2 mouse should work with this protocol type, although + wheels and other additional features are unavailable in the + X server. + + After verifying the mouse works with this protocol, + you may choose to specify one of <tt>"xxxPS/2"</tt> protocols so that + extra features are made available in the X server. + However, support for these PS/2 mice assumes certain behavior of + the underlying OS and may not always work as expected. + Support for some PS/2 mouse models may be disabled all together + for some OS platforms for this reason. + + Some OSs may allow you to specify <tt>"Auto"</tt> as the + protocol type for the PS/2 mouse and the X server will automatically + adjust itself. + + <tag>Serial mouse</tag> + The XFree86 server supports a wide range of mice, both old and new. + If your mouse is of a relatively new model, it may conform to the + PnP COM device specification and the X server may be able to + detect an appropriate protocol type for the mouse automatically. + + Specify <tt>"Auto"</tt> as the protocol type and start the X server. + If the mouse is not a PnP mouse, or the X server cannot determine + a suitable protocol type, the server will print the following + error message and abort. + + <verb> + xf86SetupMouse: Cannot determine the mouse protocol + </verb> + + If the X server generates the above error message, you need to + manually specify a protocol type for your mouse. + Choose one from the following list: + + <itemize> + <item><tt>GlidePoint</tt> + <item><tt>IntelliMouse</tt> + <item><tt>Logictech</tt> + <item><tt>Microsoft</tt> + <item><tt>MMHittab</tt> + <item><tt>MMSeries</tt> + <item><tt>MouseMan</tt> + <item><tt>MouseSystems</tt> + <item><tt>ThinkingMouse</tt> + </itemize> + + When you choose, keep in mind the following rule of thumb: + + <enum> + <item><tt>"Logitech"</tt> protocol is for old serial mouse models + from Logitech. + Modern Logitech mice use either <tt>"MouseMan"</tt> or <tt>"Microsoft"</tt> + protocol. + <item>Most 2-button serial mice support the <tt>"Microsoft"</tt> protocol. + <item>3-button serial mice may work with the <tt>"Mousesystems"</tt> + protocol. If it doesn't, it may work instead with the + <tt>"Microsoft"</tt> protocol although the third (middle) button won't + function. + 3-button serial mice may also work with the <tt>"Mouseman"</tt> + protocol under which the third button may function as expected. + <item>3-button serial mice may have a small switch at the bottom + of the mouse to choose between ``MS'' and ``PC'', or ``2'' and ``3''. + ``MS'' or ``2'' usually mean the <tt>"Microsoft"</tt> protocol. + ``PC'' or ``3'' will choose the <tt>"MouseSystems"</tt> protocol. + <item>If the serial mouse has a roller or a wheel, it may be compatible + with the <tt>"IntelliMouse"</tt> protocol. + <item>If the serial mouse has a roller or a wheel and it doesn't work + with the <tt>"IntelliMouse"</tt> protocol, you have to use it + as a regular 2- or 3-button serial mouse. + </enum> + + If the <tt>"Auto"</tt> protocol is specified and the mouse seems working, + but you find that not all features of the mouse is available, that is + because the X server does not have native support for that model of mouse + and is using a ``compatible'' protocol according to PnP information. + + If you suspect this is the case with your mouse, please send report to + <it/<XFree86@XFree86.Org>/. + + <tag>Standardized protocols</tag> + Mouse device drivers in your OS may use the standardized protocol + regardless of the model or the class of the mouse. + For example, SVR4 systems may support <tt>"Xqueue"</tt> protocol. + In FreeBSD the system mouse device <tt>/dev/sysmouse</tt> + uses the <tt>"SysMouse"</tt> protocol. + Please refer to the OS support section of this file for more information. + + </descrip> + + <sect>XF86Config Options <p> + + The following new options are available for the <tt>Pointer</tt> section + of the <tt>XF86Config</tt> file. + + <sect1>Buttons <p> + This option tells the X server the number of buttons on the mouse. + Currently there is no reliable way to automatically detect the correct + number. + This option is the only means for the X server to obtain it. + The default value is three. + + Note that if you intend to assign Z axis movement to button events + using the <tt>ZAxisMapping</tt> option below, you need to take account + of those buttons into <tt>N</tt> too. + + <verb> + Buttons N + </verb> + + <sect1>ZAxisMappping <p> + This option maps the Z axis (wheel) motion to a pair of buttons or to + another axis. + + <verb> + ZAxisMapping X + ZAxisMapping Y + ZAxisMapping N M + </verb> + + The first example will map the Z axis motion to the X axis motion. + Whenever the user moves the wheel/roller, its movement is reported as + the X axis motion. When the wheel/roller stays still, the real X axis + motion is reported as is. The last example will map negative Z axis + motion to the button <tt>N</tt> and positive Z axis motion to + the button <tt>M</tt>. If this option is used and the buttons <tt>N</tt> + or <tt>M</tt> actually exists in the mouse, + their actions won't be detected by the X server. + + Currently this option can not be set in the <tt>XF86Setup</tt> program. + You need to edit the <tt>XF86Config</tt> file by hand to add this option. + + <sect1>Resolution <p> + The following option will set the mouse device resolution to <tt>N</tt> + counts per inch, if possible: + + <verb> + Resolution N + </verb> + + Not all mice and OSs can support this option. + This option can be set in the <tt>XF86Setup</tt> program. + + <sect>Mouse Gallery <p> + + <sect1>MS IntelliMouse (serial, PS/2) <p> + This mouse has been supported since XFree86 3.3. + However, support in 3.3.2 is slightly different; + the wheel movement is recognized as the Z axis motion. + This behavior is not compatible with XFree86 + 3.3, but is more consistent with the support for other mice with + wheels or rollers. + If you want to make the wheel behave like before, + you can use the new option <tt>"ZAxisMapping"</tt> as described above. + <p> + IntelliMouse supports the PnP COM device specification. + <p> + To use this mouse as a serial device: + <verb> + Protocol "Auto" or "IntelliMouse" + Device "/dev/xxxx" (where xxxx is a serial port) + </verb> + + To use this mouse as the PS/2 device and the OS supports PS/2 mouse + initialization: + <verb> + Protocol "IMPS/2" + Device "/dev/xxxx" (where xxxx is the PS/2 mouse device) + </verb> + + To use this mouse as the PS/2 device but the OS does not support PS/2 mouse + initialization (the wheel won't work in this case): + <verb> + Protocol "PS/2" + Device "/dev/xxxx" (where xxxx is the PS/2 mouse device) + </verb> + + To use this mouse as the PS/2 device and the OS supports automatic + PS/2 mouse detection: + <verb> + Protocol "Auto" + Device "/dev/xxxx" (where xxxx is the PS/2 mouse device) + </verb> + + <sect1>Kensington Thinking Mouse (serial, PS/2) <p> + This mouse has four buttons. + Thinking Mouse supports the PnP COM device specification. + <p> + To use this mouse as a serial device: + <verb> + Protocol "Auto" or "ThinkingMouse" + Device "/dev/xxxx" (where xxxx is a serial port) + </verb> + + To use this mouse as the PS/2 device and the OS supports PS/2 mouse + initialization: + <verb> + Protocol "ThinkingMousePS/2" + Device "/dev/xxxx" (where xxxx is the PS/2 mouse device) + </verb> + + To use this mouse as the PS/2 device but the OS does not support PS/2 mouse + initialization (the third and the fourth buttons act as though they + were the first and the second buttons): + <verb> + Protocol "PS/2" + Device "/dev/xxxx" (where xxxx is the PS/2 mouse device) + </verb> + + To use this mouse as the PS/2 device and the OS supports automatic + PS/2 mouse detection: + <verb> + Protocol "Auto" + Device "/dev/xxxx" (where xxxx is the PS/2 mouse device) + </verb> + + <sect1>Genius NetScroll (PS/2) <p> + This mouse has four buttons and a roller. The roller movement is + recognized as the Z axis motion. + <p> + To use this mouse as the PS/2 device and the OS supports PS/2 mouse + initialization: + <verb> + Protocol "NetScrollPS/2" + Device "/dev/xxxx" (where xxxx is the PS/2 mouse device) + </verb> + + To use this mouse as the PS/2 device but the OS does not support PS/2 mouse + initialization (the roller and the fourth button won't work): + <verb> + Protocol "PS/2" + Device "/dev/xxxx" (where xxxx is the PS/2 mouse device) + </verb> + + To use this mouse as the PS/2 device and the OS supports automatic + PS/2 mouse detection: + <verb> + Protocol "Auto" + Device "/dev/xxxx" (where xxxx is the PS/2 mouse device) + </verb> + + <sect1>Genius NetMouse and NetMouse Pro (serial, PS/2) <p> + These mice have a "magic button" which is used like a wheel or a + roller. The "magic button" action is recognized as the Z axis motion. + NetMouse Pro is identical to NetMouse except that it has the third + button on the left hand side. + <p> + NetMouse and NetMouse Pro support the PnP COM device specification. + When used as a serial mouse, they are compatible with MS IntelliMouse. + <p> + To use these mice as a serial device: + <verb> + Protocol "Auto" or "IntelliMouse" + Device "/dev/xxxx" (where xxxx is a serial port) + </verb> + + To use this mouse as the PS/2 device and the OS supports PS/2 mouse + initialization: + <verb> + Protocol "NetMousePS/2" + Device "/dev/xxxx" (where xxxx is the PS/2 mouse device) + </verb> + + To use this mouse as the PS/2 device but the OS does not support PS/2 mouse + initialization (the "magic button" and the third button won't work): + <verb> + Protocol "PS/2" + Device "/dev/xxxx" (where xxxx is the PS/2 mouse device) + </verb> + + To use this mouse as the PS/2 device and the OS supports automatic + PS/2 mouse detection: + <verb> + Protocol "Auto" + Device "/dev/xxxx" (where xxxx is the PS/2 mouse device) + </verb> + + <sect1>ALPS GlidePoint (serial, PS/2) <p> + The serial version of this pad device has been supported since XFree86 + 3.2. `Tapping' action is interpreted as the fourth button press. + (IMHO, the fourth button of GlidePoint should always be mapped to the first + button in order to make this pad behave like the other pad products.) + <p> + To use this pad as a serial device: + <verb> + Protocol "GlidePoint" + Device "/dev/xxxx" (where xxxx is a serial port) + </verb> + + To use this mouse as the PS/2 device and the OS supports PS/2 mouse + initialization: + <verb> + Protocol "GlidePointPS/2" + Device "/dev/xxxx" (where xxxx is the PS/2 mouse device) + </verb> + + To use this mouse as the PS/2 device but the OS does not support PS/2 mouse + initialization: + <verb> + Protocol "PS/2" + Device "/dev/xxxx" (where xxxx is the PS/2 mouse device) + </verb> + + To use this mouse as the PS/2 device and the OS supports automatic + PS/2 mouse detection: + <verb> + Protocol "Auto" + Device "/dev/xxxx" (where xxxx is the PS/2 mouse device) + </verb> + + <sect1>ASCII MieMouse (serial, PS/2) <p> + This mouse appears to be OEM from Genius. Although its shape is + quite different, it works like Genius NetMouse Pro. This mouse has a + "knob" which is used like a wheel or a roller. The "knob" action is + recognized as the Z axis motion. + <p> + MieMouse supports the PnP COM device specification. When used as a + serial mouse, it is compatible with MS IntelliMouse. + <p> + To use this mouse as a serial device: + <verb> + Protocol "Auto" or "IntelliMouse" + Device "/dev/xxxx" (where xxxx is a serial port) + </verb> + + To use this mouse as the PS/2 device and the OS supports PS/2 mouse + initialization: + <verb> + Protocol "NetMousePS/2" + Device "/dev/xxxx" (where xxxx is the PS/2 mouse device) + </verb> + + To use this mouse as the PS/2 device but the OS does not support PS/2 mouse + initialization (the knob and the third button won't work): + <verb> + Protocol "PS/2" + Device "/dev/xxxx" (where xxxx is the PS/2 mouse device) + </verb> + + To use this mouse as the PS/2 device and the OS supports automatic + PS/2 mouse detection: + <verb> + Protocol "Auto" + Device "/dev/xxxx" (where xxxx is the PS/2 mouse device) + </verb> + + <sect1>Logitech MouseMan+ and FirstMouse+ (serial, PS/2) <p> + MouseMan+ has two buttons on top, one side button and a roller. + FirstMouse+ has two buttons and a roller. The roller movement is + recognized as the Z axis motion. The roller also acts as the third + button. The side button is recognized as the fourth button. + <p> + MouseMan+ and FirstMouse+ support the PnP COM device specification. + They have MS IntelliMouse compatible mode when used as a serial mouse. + <p> + To use these mice as a serial device: + <verb> + Protocol "Auto" or "IntelliMouse" + Device "/dev/xxxx" (where xxxx is a serial port) + </verb> + + To use this mouse as the PS/2 device and the OS supports PS/2 mouse + initialization: + <verb> + Protocol "MouseManPlusPS/2" + Device "/dev/xxxx" (where xxxx is the PS/2 mouse device) + </verb> + + To use this mouse as the PS/2 device but the OS does not support PS/2 mouse + initialization (the wheel and the fourth button won't work): + <verb> + Protocol "PS/2" + Device "/dev/xxxx" (where xxxx is the PS/2 mouse device) + </verb> + + To use this mouse as the PS/2 device and the OS supports automatic + PS/2 mouse detection: + <verb> + Protocol "Auto" + Device "/dev/xxxx" (where xxxx is the PS/2 mouse device) + </verb> + + + + <verb> + $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/mouse.sgml,v 1.1.2.8 1998/03/02 09:58:25 dawes Exp $ + + + + $TOG: mouse.sgml /main/1 1998/03/06 16:43:12 kaleb $ + </verb> + </article> *** ./programs/Xserver/hw/xfree86/doc/sgml/trident.sgml@@/PUBLIC-LATEST Sat Jul 19 10:35:18 1997 --- xc/programs/Xserver/hw/xfree86/doc/sgml/trident.sgml Fri Mar 6 16:41:38 1998 *************** *** 3,13 **** <title> Information for Trident Chipset Users <author> The XFree86 Project, Inc. ! <date> 20 May 1997 <toc> <sect> Supported chipsets <p> ! The Trident driver has undergone some more work for XFree86 3.3. Because of this work, all of the Trident SVGA chipsets, except the very first one, are supported by both the color and monochrome servers. <quote><bf> --- 3,13 ---- <title> Information for Trident Chipset Users <author> The XFree86 Project, Inc. ! <date> 10th February 1998 <toc> <sect> Supported chipsets <p> ! The Trident driver has undergone some more work for XFree86 3.3.2. Because of this work, all of the Trident SVGA chipsets, except the very first one, are supported by both the color and monochrome servers. <quote><bf> *************** *** 14,20 **** 8800CS 8200LX 8900B 8900C 8900CL/D 9000 9000i 9100B 9200CXr 9320LCD 9400CXi 9420 9420DGi 9430DGi 9440AGi 9660XGi 9680 ! 9682 9685 Cyber9382 Cyber9385 Cyber9385-1 </bf></quote> It must be noted that the 9000i chipset is treated as a 9000 by the server. Additionally the 9100B is treated --- 14,21 ---- 8800CS 8200LX 8900B 8900C 8900CL/D 9000 9000i 9100B 9200CXr 9320LCD 9400CXi 9420 9420DGi 9430DGi 9440AGi 9660XGi 9680 ! ProVidia9682 ProVidia9685 Cyber9382 Cyber9385 Cyber9385-1 Cyber9388 ! Cyber9397 3DImage975(PCI) 3DImage985(AGP) </bf></quote> It must be noted that the 9000i chipset is treated as a 9000 by the server. Additionally the 9100B is treated *************** *** 26,46 **** <bf> NOTES: </bf> <itemize> ! <item>Acceleration is now supported for the 9440/96xx and Cyber938x chips. ! <item>24bpp is supported for the 9440, 32bpp is supported for the 96xx ! and Cyber938x based chips. ! <item>The Cyber 9382/5 chips that have started to appear, have much improved ! support in XFree86 3.3 and appear to work at 800x600 on the LCD. ! <item>The TGUI9440 and TGUI96xx based cards are supported by the SVGA server. ! <item>16 bits per pixel is now supported for the 8900D, 9200CXr, 9400CXi, ! 9420DGi, 9430DGi, 9440AGi, 96xx, but only the 9440AGi and 9400CXi ! have been tested. ! <item>Linear access has been implemented for chipsets that support it. ! It is enabled by default for PCI cards, and disabled by default for other ! cards. ! Additionally Hardware cursor is implemented for the 9430, 9440, 96xx, ! although only the 9440 and 9660 have been tested with the hardware cursor. ! <item>The following options may be specified for the Trident driver: <descrip> <tag>Option &dquot;nolinear&dquot;</tag> Turn off linear mapping --- 27,43 ---- <bf> NOTES: </bf> <itemize> ! <item> The chipset keyword has changed in XFree86 v3.3.2 and now you ! no longer specify 'tgui96xx' as the generic keyword, but you actually ! specify your chip. i.e. Chipset 'tgui9685' will set a ProVidia9685 chip. ! <item> The new Cyber9397, 3DImage975(PCI) and 3DImage985(AGP) cards are ! introduced in XFree86 v3.3.2, but is still experimental, these chipsets ! are currently unaccelerated. ! <item> 24bpp is all drivers remains unaccelerated, this will change in ! a future version, although 32bpp acceleration is supported for all TGUI ! based chipset except the 9440 which doesn't have the capability. ! <item> 24/32bpp is not supported for the 9685, it will be fixed in a future ! version. <descrip> <tag>Option &dquot;nolinear&dquot;</tag> Turn off linear mapping *************** *** 74,90 **** <tag>Option &dquot;noaccel&dquot;</tag> Turn off XAA acceleration. <tag>Option &dquot;xaa_no_color_exp&dquot;</tag> ! Disable color expansion, which is needed for some 9440 cards ! (and maybe others?). <tag>Option &dquot;no_stretch&dquot;</tag> Disable LCD stretching on Cyber 938x based chips. <tag>Option &dquot;lcd_center&dquot;</tag> Enable LCD centering on Cyber 938x based chips. <tag>Option &dquot;tgui_mclk_66"</tag> Pushes the Memory Clock from its default value to 66MHz. Increases graphics speed dramatically, but use entirely at your own risk, as it may damage the video card. ! If snow appears, disable. </descrip> </itemize> --- 71,89 ---- <tag>Option &dquot;noaccel&dquot;</tag> Turn off XAA acceleration. <tag>Option &dquot;xaa_no_color_exp&dquot;</tag> ! Disable color expansion. <tag>Option &dquot;no_stretch&dquot;</tag> Disable LCD stretching on Cyber 938x based chips. <tag>Option &dquot;lcd_center&dquot;</tag> Enable LCD centering on Cyber 938x based chips. + <tag>Option &dquot;cyber_shadow&dquot;</tag> + Enable Shadow registers, might be needed for some + Cyber chipsets. (laptop machines) <tag>Option &dquot;tgui_mclk_66"</tag> Pushes the Memory Clock from its default value to 66MHz. Increases graphics speed dramatically, but use entirely at your own risk, as it may damage the video card. ! If snow appears, disable. Only tested on the 9440. </descrip> </itemize> *************** *** 150,156 **** be worth checking wait states etc. on the card and in the BIOS setup. <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/trident.sgml,v 3.22.2.1 1997/05/21 15:02:40 dawes Exp $ --- 149,155 ---- be worth checking wait states etc. on the card and in the BIOS setup. <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/trident.sgml,v 3.22.2.3 1998/02/24 13:54:23 hohndel Exp $ *************** *** 157,163 **** ! $TOG: trident.sgml /main/12 1997/07/19 10:35:20 kaleb $ </verb> </article> --- 156,162 ---- ! $TOG: trident.sgml /main/13 1998/03/06 16:43:16 kaleb $ </verb> </article> *** ./programs/Xserver/hw/xfree86/doc/sgml/tseng.sgml@@/PUBLIC-LATEST Sun Aug 10 13:03:52 1997 --- xc/programs/Xserver/hw/xfree86/doc/sgml/tseng.sgml Fri Mar 6 16:41:42 1998 *************** *** 5,26 **** <title> Information for Tseng Chipset Users <author> The XFree86 Project, Inc. Dirk H. Hohndel, Koen Gadeyne and others. ! <date> 16 May 1997 <toc> <sect> Supported chipsets <p> The Tseng chipsets supported by XFree86 are ET3000, ET4000, ET4000/W32 and ! ET6000. Accelerated features of the ET4000/W32p and ET6000 are supported by ! the SVGA driver. For details about the separate accelerated 8bpp (=256 ! color) ET4000/W32 and ET6000 server, refer to <htmlurl name="README.W32" url="W32.html">. ! Things that are known NOT to work with the SVGA server in this version ! (XFree86 3.3) are some ET4000W32 ISA cards (they hang the machine... Use the ! W32 server <tt>XF86_W32</tt> for these cards!), and acceleration on ! ET4000W32i cards. In the rest of this document, "8bpp" is short for "8 bits per pixel", which means a 256-color mode. Similarly, 15bpp refers to 32768 colors, 16bpp to 65536 colors , 24bpp to a "packed" 16 million color mode, and 32bpp to a --- 5,31 ---- <title> Information for Tseng Chipset Users <author> The XFree86 Project, Inc. Dirk H. Hohndel, Koen Gadeyne and others. ! <date> 02 Feb 1998 <toc> <sect> Supported chipsets <p> The Tseng chipsets supported by XFree86 are ET3000, ET4000, ET4000/W32 and ! ET6000. Accelerated features of the ET4000/W32, W32i, W32p and ET6000 are ! supported by the SVGA driver. For details about the separate accelerated ! 8bpp (=256 color) ET4000/W32 and ET6000 server, refer to <htmlurl name="README.W32" url="W32.html">. ! Note that you should NOT be using XF86_W32 unless XF86_SVGA doesn't work on ! your hardware. No further development is being done on the W32 server; all ! new efforts go into the SVGA server. + Some ET4000W32 ISA cards are known NOT to work with the SVGA server in this + version (XFree86 3.3.1): they hang the machine... Use the W32 server + <tt>XF86_W32</tt> for these cards! + + <sect> Terminology <p> + In the rest of this document, "8bpp" is short for "8 bits per pixel", which means a 256-color mode. Similarly, 15bpp refers to 32768 colors, 16bpp to 65536 colors , 24bpp to a "packed" 16 million color mode, and 32bpp to a *************** *** 40,54 **** server, some cards may only support a few of these color depths, or even only 8bpp. ! On W32p chips all color depths are supported on the supported RAMDACs ! (currently ICS5341, STG170x and Chrontel CH8398). These modes are also ! accelerated. On W32i chips, only AT&T49x compatible RAMDACs will support 16 ! and 24 bpp modes, and there is no acceleration support (yet). - W32p revision a and b chips are limited to 1 MB of video memory in linear - memory modes with acceleration (i.e. in 16/24/32 bpp modes). This is a - hardware limitation. Cards with a RAMDAC that is not yet supported will be limited in a similar manner as the older cards, i.e. to a maximum pixel clock of 86 MHz, whilst they actually might be able to go up to 135 MHz. As a result, 1280x1024 --- 45,67 ---- server, some cards may only support a few of these color depths, or even only 8bpp. ! On W32i and W32p chips all color depths are supported on the supported ! RAMDACs (currently ICS5341, STG170x and Chrontel CH8398). These modes are ! also accelerated. + Some W32p board implementations are limited to 1 MB of video memory in + linear memory modes. This is a hardware limitation that cannot be solved in + the driver. Since XFree86 requires linear memory for 16/24/32 bpp modes, the + usefulness of these cards for highcolor and truecolor applications is + severely limited (those modes mostly use a lot of video memory). + + In addition, those cards also don't support acceleration in linear mode. + This is a design choice in the driver code: if acceleration were to be + supported in linear mode, you'd only be able to use 768 kb of video memory, + and the driver code would be twice as complex. + + Cards with a RAMDAC that is not yet supported will be limited in a similar manner as the older cards, i.e. to a maximum pixel clock of 86 MHz, whilst they actually might be able to go up to 135 MHz. As a result, 1280x1024 *************** *** 55,72 **** modes will only be possible when using interlacing, and non-interlaced modes are limited to about 1024x768 at 75 Hz refresh. ! For a non-interlaced 1280x1024x(256 colors) at say 135-MHz, you need a w32p ! (with its 16-bit RAMDAC bus) with a multiplexing RAMDAC so that the w32p ! sees only (135/2 = 67.5) MHz, not 135 MHz. This requires special code only ! provided for cards using the ICS5341 GENDAC or the STG170x. This code seems ! to work fine for most people, except, with the ICS5341, for a small band of ! frequencies around 90MHz. ! Linear memory mode (especially important for some DGA clients, and required ! for 16/24/32 bpp modes) is supported on all ET4000W32i and ET4000W32p cards, ! but not on the ET4000W32. On ET4000W32p revision a and b, linear memory is ! limited to 1 MB. For the higher color depths (16, 24 and 32 bpp), linear memory mode is REQUIRED. It is enabled by default in these modes. There is no need to --- 68,85 ---- modes will only be possible when using interlacing, and non-interlaced modes are limited to about 1024x768 at 75 Hz refresh. ! For a non-interlaced 1280x1024x(256 colors) at say 135-MHz on a W32-type ! card, you need a w32p (with its 16-bit RAMDAC bus) with a multiplexing ! RAMDAC so that the w32p sees only (135/2 = 67.5) MHz, not 135 MHz. This ! requires special code only provided for cards using the ICS5341 GENDAC, the ! STG170x or the CH8398. This code seems to work fine for most people, except, ! with the ICS5341, for a small band of frequencies around 90MHz. ! Linear memory mode (especially important for some DGA clients, like ! xf86quake) is supported on all ET4000W32i and ET4000W32p cards, but not on ! the ET4000W32. See the section on linear memory for more information. There ! are some important issues related to linear memory. For the higher color depths (16, 24 and 32 bpp), linear memory mode is REQUIRED. It is enabled by default in these modes. There is no need to *************** *** 74,90 **** linear memory below: it contains some vital information on how to avoid serious problems. ! To force linear memory mode at 8bpp modes, put the following in the Device ! section of your <tt>XF86Config</tt>: <verb> Option "linear" </verb> ! Acceleration support is present, and enabled by default, for W32p chips (not ! yet for W32i, but that's being worked on). This is based on the new XFree86 ! acceleration interface (XAA). See also ! <htmlurl name="README.W32" url="W32.html">. If you have problems with acceleration, acceleration can be disabled by putting the following in the Device section of your --- 87,102 ---- linear memory below: it contains some vital information on how to avoid serious problems. ! To force linear memory mode in 8bpp modes (where "banked" mode is the ! default), put the following in the Device section of your <tt>XF86Config</tt>: <verb> Option "linear" </verb> ! Acceleration support is present, and enabled by default, for all W32 and ! ET6000 family chips. This is based on the new XFree86 acceleration interface ! (XAA). If you have problems with acceleration, acceleration can be disabled by putting the following in the Device section of your *************** *** 107,116 **** supports all possible color depths in the SVGA server: 8bpp, 16bpp (both at 5-5-5 and 5-6-5 color resolutions), 24bpp and 32 bpp. ! In order to be able to run at a depth of 16bpp, 24bpp, or 32bpp, and to ! improve performance at 8bpp, linear addressing must be enabled. ! ! Linear memory mode (as opposed to the default, banked memory layout) is supported. It is required and enabled by default for the 16/24/32 bpp modes. For 8bpp, the default is banked mode. --- 119,125 ---- supports all possible color depths in the SVGA server: 8bpp, 16bpp (both at 5-5-5 and 5-6-5 color resolutions), 24bpp and 32 bpp. ! Linear memory mode (as opposed to the VGA default, banked memory layout) is supported. It is required and enabled by default for the 16/24/32 bpp modes. For 8bpp, the default is banked mode. *************** *** 142,150 **** approx. 110MHz) at which point the cursor does strange things when partly off the left-hand side of the screen. ! Doublescan modes currently don't work with the hardware cursor: only the top ! half of the cursor is visible. If you want to use DoubleScan modes (320x200 ! is a popular one), then do not enable the hardware cursor. On some fast systems, acceleration may cause occasional font corruption. Until --- 151,161 ---- approx. 110MHz) at which point the cursor does strange things when partly off the left-hand side of the screen. ! On older ET6000 chip revisions, DoubleScan modes currently don't work with ! the hardware cursor: only the top half of the cursor is visible. If you want ! to use DoubleScan modes (320x200 is a popular one), then do not enable the ! hardware cursor. Most recent ET6000 cards and the ET6100 do not exhibit this ! problem. On some fast systems, acceleration may cause occasional font corruption. Until *************** *** 201,206 **** --- 212,225 ---- Option "hibit_high" </verb> + <sect> Text mode restore problems <p> + In XFree86 1.3, an option flag ``force_bits'' was provided as an experiment + to attempt to alleviate text-restoration problems that some people experienced. + We have now made the behavior of this option the default, hence the flag + has been removed. Hopefully the past text-restoration problems are alleviated + in XFree86 2.0. + + <sect> Basic configuration <p> It is recommended that you generate an XF86Config file using *************** *** 211,217 **** (e.g 1152x864 modes). The driver options are described in detail in the next section; here the basic options are hinted at. ! If graphics redrawing goes wrong on accelerated chips (ET4000W32p and ET6000), first try the <tt>&dquot;noaccel&dquot</tt>; option, which disables all accelerated functions. --- 230,236 ---- (e.g 1152x864 modes). The driver options are described in detail in the next section; here the basic options are hinted at. ! If graphics redrawing goes wrong on accelerated chips (ET4000W32 and ET6000), first try the <tt>&dquot;noaccel&dquot</tt>; option, which disables all accelerated functions. *************** *** 231,237 **** dot clocks, and bugs in accelerated functions, at the cost of performance (which will still be reasonable on a local or PCI bus). This option applies only to those chips where acceleration is ! supported (currently ET4000W32p and ET6000). <tag>Option &dquot;fast_dram&dquot; &dquot;slow_dram&dquot; </tag> These options set the DRAM speed of certain cards where it applies. --- 250,256 ---- dot clocks, and bugs in accelerated functions, at the cost of performance (which will still be reasonable on a local or PCI bus). This option applies only to those chips where acceleration is ! supported. <tag>Option &dquot;fast_dram&dquot; &dquot;slow_dram&dquot; </tag> These options set the DRAM speed of certain cards where it applies. *************** *** 239,251 **** ET4000W32. If enabled, it slows down DRAM timing, which may avoid some memory-related problems. If your card starts up with a black screen (and possibly a system hang), this option might be needed. - Not supported on ET6000. The <tt>"fast_dram"</tt> option will cause the driver to speed up DRAM timings, which may also avoid screen-related problems (streaking, stripes, garbage, ...). It may also increase those very ! same effects. Not supported on ET6000. <tag> videoram 1024 (or another value) (all chips) </tag> This option will override the detected amount of video memory, and --- 258,293 ---- ET4000W32. If enabled, it slows down DRAM timing, which may avoid some memory-related problems. If your card starts up with a black screen (and possibly a system hang), this option might be needed. The <tt>"fast_dram"</tt> option will cause the driver to speed up DRAM timings, which may also avoid screen-related problems (streaking, stripes, garbage, ...). It may also increase those very ! same effects. ! ! All in all, these are potentially dangerous options: they could ! crash your machine as soon as you start the server. Use them with ! caution. <tag> + option &dquot;w32_interleave_off&dquot; &dquot;w32_interleave_on&dquot; (W32i, W32p) + </tag> + Force memory interleaving off or on. W32i and W32p chips can + increase memory bandwidth when they have 2MB or more video memory. + Normally the VGA BIOS sets the W32i or W32p chip to the correct + mode. If you suspect problems with memory sizing or interleaving, + fooling around with these options may improve the situation. It may + also make things worse. These options are not normally needed: the + server will use the correct value automatically. Setting this option + the wrong way will result in a completely distorted display. + <tag> + option &dquot;pci_burst_off&dquot; &dquot;pci_burst_on&dquot; (W32p) + </tag> + This option disables or enables PCI bursts on the W32p chip if it's + a PCI card. Normally, a good BIOS will set the motherboard and the + VGA card to the same setting, but if both don't match, you may + experience garbage on the screen (e.g. mouse droppings). These + options allow you to match the W32p burst setting to the motherboard + setting. + <tag> videoram 1024 (or another value) (all chips) </tag> This option will override the detected amount of video memory, and *************** *** 288,294 **** Read the section on linear memory base address issues below! Read the section on linear memory base address issues below! ! (Message repeated on purpose) Use this option ONLY if you have trouble with the default MemBase used by the server, or if the server explicitly states that you must --- 330,336 ---- Read the section on linear memory base address issues below! Read the section on linear memory base address issues below! ! (Message repeated for a very good reason) Use this option ONLY if you have trouble with the default MemBase used by the server, or if the server explicitly states that you must *************** *** 297,306 **** Option &dquot;pci_retry&dquot; (ET4000W32p on PCI bus, ET6000) </tag> This enables the PCI bus retry function, which is a performance ! enhancing mode for PCI bus-based systems, where the VGA controller ! will put the PCI bus in a hold state (sort of like wait-states) when ! the server tries to start a new accelerated operation but the ! accelerator is still busy with the previous operation. This is the fastest way to drive a VGA card (no busy-waiting loops needed), but it also stresses some hardware that is timing-dependent --- 339,349 ---- Option &dquot;pci_retry&dquot; (ET4000W32p on PCI bus, ET6000) </tag> This enables the PCI bus retry function, which is a performance ! enhancing mode for local bus or PCI bus-based systems, where the VGA ! controller will put the bus in a hold state (sort of like ! wait-states) when the server tries to start a new accelerated ! operation but the accelerator is still busy with the previous ! operation. This is the fastest way to drive a VGA card (no busy-waiting loops needed), but it also stresses some hardware that is timing-dependent *************** *** 314,319 **** --- 357,363 ---- (to your operating system, of course). Especially defining the MemBase to be inside the range of system memory is a ticket to hell. + <sect1>What you should know BEFORE trying another MemBase<p> Rule #1: first, let the server find a memory base by itself, without specifying it. Make sure you "sync" all files to disk and close all critical applications. Make sure nothing bad will happen to your filesystems if you *************** *** 323,328 **** --- 367,376 ---- (VLB). The server will autodetect a linear base address that doesn't work on all systems. + The least critical cards are PCI-bus cards. The PCI BIOS normally takes care + of assigning a good MemBase, and you should never have to deal with all the + mumbo-jumbo below. + If the server gets it wrong, you may end up with a severe system crash (e.g. if it maps the video memory right on top of your system memory). If this happens, RESET IMMEDIATELY. Do not try to shut down cleanly, because the *************** *** 340,345 **** --- 388,394 ---- When the server can't find a working linear memory base, it's time to experiment. The rest of this section deals with that. + <sect1>Choosing a MemBase<p> Choosing a suitable MemBase can be quite tricky. If you have no way of determining the MemBase your card uses, trying to put it a few Mb above the system memory is a good first guess. E.g. if you have 16 Mb of RAM, defining *************** *** 351,367 **** only exception are those systems with more than one PCI VGA card. On most VESA local bus (VLB) boards, there is an additional problem with ! address decoding. Some motherboards only decode the first 32, 64 or 128 MB of address space (a good pointer is to check the amount of DRAM that can be installed on the board: it will at least decode as much address space as it supports DRAM). On such boards, you MUST specify a MemBase inside that range, or the actual ! address may wrap back onto system memory. That is why the general guideline ! of putting the MemBase just above the system memory is a sound one: it ! stands most chance of actually being inside the decoded address range of the ! board. Unless your motherboard's entire memory space is filled with RAM. If you don't know how much memory address space your motherboard decodes (and who does?), try using a "non-trivial" address, like 0x1FC00000, which has enough bits set to "1" to work on any motherboard, even if a few are not --- 400,420 ---- only exception are those systems with more than one PCI VGA card. On most VESA local bus (VLB) boards, there is an additional problem with ! address decoding. Most motherboards only decode the first 32, 64 or 128 MB of address space (a good pointer is to check the amount of DRAM that can be installed on the board: it will at least decode as much address space as it supports DRAM). On such boards, you MUST specify a MemBase inside that range, or the actual ! address may wrap back onto system memory: if your system only decodes 128MB ! of addresses, and you set the MemBase to 128 MB, it will actually be decoded ! as being on address 0, which is probably exactly where your kernel memory is ! located. That is why the general guideline of putting the MemBase just above ! the system memory is a sound one: it stands most chance of actually being ! inside the decoded address range of the board. Unless your motherboard's ! entire memory space is filled with RAM. + <sect1>An alternative approach<p> If you don't know how much memory address space your motherboard decodes (and who does?), try using a "non-trivial" address, like 0x1FC00000, which has enough bits set to "1" to work on any motherboard, even if a few are not *************** *** 369,383 **** --- 422,444 ---- top of your system memory if the motherboard doesn't decode all upper address bits. You will only do that once. + <sect1>When all else fails...<p> Some other VLB boards can only map the linear framebuffer above the 1GB mark (0x80000000 and up), so you must use a MemBase that is higher or equal to 0x80000000. + Some other VLB boards can only map the linear framebuffer BELOW the 16 MB + mark. So you may want to try booting your system with up to 12 MB of memory + (some operating systems allow you to supply a boot-time parameter that + limits the memory to a certain amount, so you don't have to open your + computer to try this), and set the MemBase to 0x00C00000 (=12M). + Unfortunately, there is no easy way to tell what system you have (these details are mostly not in the motherboard manuals). Trial and error is the only road to success here. The server code will provide a default that works on most boards... but yours won't be one of those, of course. + <sect1>Restrictions<p> There are some limits as to where the linear memory base may be put. On any ET4000W32, it must have a 4MB granularity (i.e. it can be put at 16M or at 20M, but not at 18M). On ET6000, it needs a 16M granularity (note: the *************** *** 404,415 **** allowed to use, so you don't have to unplug some memory each time you want to use linear memory. <sect> Mode issues <p> ! The accelerated driver on ET4000W32p and ET6000 uses 1K bytes of scratch ! space in video memory. Consequently, a 1024x1024 virtual resolution should ! not be used with a 1Mbyte card. The use of a higher dot clock frequencies has a negative effect on the performance of graphics operations on non-et6000 cards (the effect is much less, or even non-existing, on ET6000 cards), especially BitBlt, when little --- 465,531 ---- allowed to use, so you don't have to unplug some memory each time you want to use linear memory. + <sect1>Some boards simply cannot work in linear mode<p> + Yes, and in that case, you're out of luck. + + There can be at least two reasons for this. + + The first is the most common: the board manufacturer has left out the + necessary connections and hardware to be able to use linear addressing. This + means that no coding effort on this planet can help you with your problem: + it is physically impossible to use linear addressing. + + The second reason is that the current XFree86 Tseng linear addressing code is + incompatible with the way your board is designed. The XFree86 Tseng code + assumes a 1:1 mapping of the address lines from the bus (either ISA, VLB or + PCI) to the address lines on the Tseng VGA chip. As unlikely as it may + sound, this may NOT be the case! + + Some very rare boards do not have such a 1:1 mapping (e.g. two address lines + swapped). It is possible to support this type of hardware, but at this + moment, this has not been implemented yet. + + Other boards use external address decoding hardware that combines a number + of address lines on the bus to a (smaller) number of address lines to the + VGA chip. One such board for example uses three NOR gates (one 74F02 chip) + to combine the 6 upper address lines to three address pins on the W32i chip. + Obviously, this represents a 2:1 mapping, and not a 1:1 mapping. Therefor, + this board is not "compatible" with the way XFree86 implements linear mode. + + <sect1>How can I see if the linear address is wrong?<p> + Simple: nothing works, or your machine locks solid, or it crashes, or a + zillion of other things. + + However, sometimes it is not always as obvious. Sometimes nothing bad + happens: you just get a black screen, or a screen with rubbish on it, but + nothing is drawn on it. Sometimes you get a core dump when the first + application starts. + + If acceleration is enabled in those cases, you will almost always see + multiple "WAIT_ACL: timeout" messages in the server output. That is because + the accelerator registers are also mapped in the linear memory, and if + linear memory doesn't work, then also the accelerator doesn't work. + + NOTE however that a WAIT_ACL message doesn't necessarily mean the linear + memory address is bad. There are a number of other reasons for this message + as well. But if you never saw these messages at 8bpp banked, then there's a + good chance you have a linear memory problem ("banked" is the opposite of + "linear", and is the default mode when "option linear" is not in the + XF86Config file). + <sect> Mode issues <p> ! The accelerated driver on ET4000W32/W32i/W32p and ET6000 needs at least 1K ! bytes of scratch space in video memory. Consequently, if you want ! acceleration, a 1024x1024 virtual resolution should not be used with a ! 1Mbyte card. This also means that a 1024x768 mode at 24bpp on a 2.25 MB ! ET6000 card cannot be accelerated, since you've used up all the memory for ! the display. + The same thing goes for the ET6000 hardware cursor: it also requires 1kb of + free video memory. If that memory is not available, the hardware cursor + cannot be used. + The use of a higher dot clock frequencies has a negative effect on the performance of graphics operations on non-et6000 cards (the effect is much less, or even non-existing, on ET6000 cards), especially BitBlt, when little *************** *** 439,455 **** match anyway. The ET4000W32i and ET4000W32p have a special feature that almost doubles ! memory bandwidth (+70%) using "interleaving" between the two banks. Upgrading ! to 2MB is a real bonus on these cards. - ET6000-based cards however use MDRAM (multi-bank DRAM), which is much faster - than DRAM. Some 4 MB systems, with 4 MDRAM chips will also do interleaving, - which should give virtually unlimited memory bandwidth: theoretically - >1GB/sec, comparing to the already neat 90MB/sec on a 1MB ET4000W32i/p - card). Most 4MB models have only 2 MDRAM chips (as do the 2MB models). So - far for the marketing hype: a real ET6000 card is limited to somewhere - around 225 MB/sec. - <sect> Acceleration issues <p> The XFree Acceleration Architecture makes extensive use of the unused video --- 555,564 ---- match anyway. The ET4000W32i and ET4000W32p have a special feature that almost doubles ! memory bandwidth (+70%) using "interleaving" between the two banks. ! Upgrading to 2MB is a real bonus on these cards. This is not true for W32 ! cards or for ET6000 cards. <sect> Acceleration issues <p> The XFree Acceleration Architecture makes extensive use of the unused video *************** *** 468,473 **** --- 577,608 ---- Most 1MB cards cannot display modes larger than 1024x768 with a decent refresh rate, leaving 256kb unused. + The order in which free memory is used to accelerate certain features is as + follows. + + If no video memory is unused (i.e. all of it is used for display memory), + no acceleration can be used at all -- not even a hardware cursor on the + ET6000. + + If the hardware cursor is enabled (ET6000 only) and there's at least 1kb of + free video memory, 1kb is used for that. + + If there is at least 1kb of free memory remaining after this, most + acceleration features are enabled as well, reserving an extra 1kb of video + memory. + + If there's still some free memory, some extra acceleration features are + enabled. These require more free video memory, depending on the virtual + screen width and the color depth (bpp). The server will print out how much + memory it used if it could. + + If there's still some free video memory, it is used as a pixmap cache. This + way, small patterns and images can be kept in the video memory so that they + don't need to be transferred into the video memory each time they're needed. + This is beneficial because transferring an image over the bus to the video + memory takes a lot more time than letting the accelerator blit it from the + pixmap cache to the display memory. + <sect> ET6000 memory size facts and fiction <p> The ET6000 uses a special kind of video memory called MDRAM (multi-bank *************** *** 482,488 **** 4.5 MB around, but that extra 0.5 MB is a waste. The ET6000 can only refresh 4 MB of (M)DRAM (refresh register). It can only access 64 banks of 64KB in VGA mode (bank select register). All accelerated commands use a 22-bit ! address (=4MB) inside the video memory. You get the idea... And Secondly (more importantly): you may not have 2.25 MB at all! There have been several reports about ET6000 cards that were sold with (supposedly) --- 617,624 ---- 4.5 MB around, but that extra 0.5 MB is a waste. The ET6000 can only refresh 4 MB of (M)DRAM (refresh register). It can only access 64 banks of 64KB in VGA mode (bank select register). All accelerated commands use a 22-bit ! address (=4MB) inside the video memory. You get the idea... There is no way ! for the ET6000 to use anything above the 4Mb limit. And Secondly (more importantly): you may not have 2.25 MB at all! There have been several reports about ET6000 cards that were sold with (supposedly) *************** *** 493,505 **** has been fixed now, and the server should detect the correct amount of memory. Do NOT define the amount of memory in the XF86Config yourself, unless you ! are absolutely sure about the amount. There is a simple way to determine the ! amount of MDRAM on your card beyond doubt. Look at the video card. There is one large chip with 204 pins on it, which is the ET6000. One socketed rectangular chip, mostly with a sticker on it,is ! the BIOS. The remaining chips are (mostly) 2 or 4 other large square chips ! on it with the following markings: MDRAM MD9xy ("xy" is a two-digit number) --- 629,643 ---- has been fixed now, and the server should detect the correct amount of memory. Do NOT define the amount of memory in the XF86Config yourself, unless you ! are absolutely sure about the amount. + There is a simple way to determine the amount of MDRAM on your card beyond + doubt. + Look at the video card. There is one large chip with 204 pins on it, which is the ET6000. One socketed rectangular chip, mostly with a sticker on it,is ! the BIOS. The remaining big chips are (mostly) 2 or 4 other large square ! chips on it with the following markings: MDRAM MD9xy ("xy" is a two-digit number) *************** *** 508,514 **** and a nice logo next to all that with 4 diamonds and the name "MoSys" underneath. ! The "xy" number tells you how much MEGABITS are in that one chip. The amount of RAM on the card is then: --- 646,652 ---- and a nice logo next to all that with 4 diamonds and the name "MoSys" underneath. ! The "xy" number tells you how much MEGABITS there are in that one chip. The amount of RAM on the card is then: *************** *** 536,542 **** on their boards, which they don't. The stunning 1.2 GByte mark is only reached when using 4 MDRAM chips at their max clock rate of 166 MHz. But due to design limitations, the first-generation ET6000 can only drive the ! memories at 92 MHz (that will change when the ET6300 hits the streets). This means the max. theoretical bandwidth available on current ET6000 boards is "only" 360 MB/sec on boards with 2 MDRAM chips, and 720 MB/sec on boards with 4 --- 674,681 ---- on their boards, which they don't. The stunning 1.2 GByte mark is only reached when using 4 MDRAM chips at their max clock rate of 166 MHz. But due to design limitations, the first-generation ET6000 can only drive the ! memories at 92 MHz (that will change when the ET6100 and ET6300 hit the ! streets). This means the max. theoretical bandwidth available on current ET6000 boards is "only" 360 MB/sec on boards with 2 MDRAM chips, and 720 MB/sec on boards with 4 *************** *** 546,551 **** --- 685,696 ---- will reduce the effective available bandwidth. The current ET6000 boards peak out at about 225 MB/sec, with 2 or 4 MDRAMs. + Whatever you may have read in press releases, the ET6000 has a 32-bit memory + bus (not 128 bits; that's only the accelerator data path within the chip, if + anything). That means that, with their 16-bit busses, 2 MDRAM chips already + use the full bus capacity. Having 4 memory chips on an ET6000 board will not + give you extra memory bandwidth. + Memory bandwidth limits the maximum resolution you can use at a given color depth. The ET6000 RAMDAC can cope with 135 MHz in any situation. But the RAM cannot. At 32bpp (sparse 16M color mode), using a 135 MHz pixel clock would *************** *** 562,571 **** Currently the 16-bit (32768 or 65536 colors), 24-bit (16M colors, packed pixel), and 32-bit (16M colors, sparse) pixel support in the SVGA server ! requires linear addressing. (This restriction may be removed in a future version, but with nearly all new cards using the PCI bus (where linear addressing poses no problem), removing the linear addressing requirement ! presently has a lower priority than other features.) Option "linear" can be specified in a depth-specific screen section to enable linear addressing; a MemBase setting (in the device section) is probably also required on non-PCI based systems, and optionally on PCI systems that have trouble finding out --- 707,716 ---- Currently the 16-bit (32768 or 65536 colors), 24-bit (16M colors, packed pixel), and 32-bit (16M colors, sparse) pixel support in the SVGA server ! requires linear addressing. This restriction may be removed in a future version, but with nearly all new cards using the PCI bus (where linear addressing poses no problem), removing the linear addressing requirement ! presently has a lower priority than other features. Option "linear" can be specified in a depth-specific screen section to enable linear addressing; a MemBase setting (in the device section) is probably also required on non-PCI based systems, and optionally on PCI systems that have trouble finding out *************** *** 577,583 **** working solution. For the most part, many of the accelerated features in the 8bpp server have ! been implemented to support 16, 24, and 32 bpp modes for the W32p and the ET6000. So although there are now up to 4 times as many bits to display, the X server shouldn't feel overly sluggish. Note also that the 24bpp and 32bpp modes are only supported on a limited set of cards, and with at least 2Mb of --- 722,728 ---- working solution. For the most part, many of the accelerated features in the 8bpp server have ! been implemented to support 16, 24, and 32 bpp modes for the W32 and the ET6000. So although there are now up to 4 times as many bits to display, the X server shouldn't feel overly sluggish. Note also that the 24bpp and 32bpp modes are only supported on a limited set of cards, and with at least 2Mb of *************** *** 631,636 **** --- 776,803 ---- the first mode listed in the modes line, with the highest dot clock listed for that resolution in the timing section. + Some general hints: + <itemize> + <item>Put Option "slow_dram" in the Device Section. + <item>Put Option "pci_burst_off" in the Device Section. + <item>Put Option "w32_interleave_off" in the Device Section. + <item>Take out the Hercules monochrome adapter, if you have one. Many + configurations of the ET4000/W32 series do not allow one in the + system. + <item>Get a motherboard with its local bus running at 33 MHz. Many, if not + all, ET4000/W32 boards will surely behave in a funny way on a 50-MHz + bus. You may have to use a wait state or two, but first try without + any. + <item>Cold-boot your machine. Do not run anything that messes with the + video hardware, including other X servers, before running + <tt>XF86_SVGA</tt>. + <item>In case of an ET6000 card, try specifying chipset "et6000" + in the Device Section. The card normally auto-probes from the PCI bus, + but on some systems, another on-board VGA card, although disabled, may + cause the ET6000 server to want to use the other card. + </itemize> + + Note that some VESA standard mode timings may give problems on some monitors (try increasing the horizontal sync pulse, i.e. the difference between the middle two horizontal timing values, or try multiples of 16 or 32 for *************** *** 669,674 **** --- 836,845 ---- Try the <tt>"noaccel"</tt> option. Check that the BIOS settings are OK; in particular, disable caching of 0xa0000-0xaffff. Disabling hidden DRAM refresh may also help. + + On Linux systems, if "APM" (power management) support is enabled in + the kernel, the server may start up in power-save mode or with a + black screen. Rebuild your kernel with APM support disabled. <tag> Crash, hang, or trash on the screen after a graphics operation. </tag> *************** *** 750,765 **** "normal"</tt> statement to the Device section in your <tt>XF86Config</tt> file. In most cases, this will solve the color problem. </descrip> For other screen drawing related problems, try the <tt>"noaccel"</tt> option. - As a final fallback, consider trying the separate accelerated W32 server. It - is more mature, and has been tested more extensively as a result. See - <htmlurl name="README.W32" url="W32.html">. - If you are having driver-related problems that are not addressed by this document, or if you have found bugs in accelerated functions, you can try contacting the XFree86 team. --- 921,947 ---- "normal"</tt> statement to the Device section in your <tt>XF86Config</tt> file. In most cases, this will solve the color problem. + <tag> + Why does the server report my ModeLine with only half the pixel clock? + </tag> + For ET4000W32p cards at 8bpp, some modes using a clock over 75 MHz + (e.g. a 1152x910 mode with 95 MHz pixel clock) will produce the + following message in the Xserver output: + (--) SVGA: Mode "1152x910" will use pixel multiplexing + + And later, when the accepted modelines are reported: + + (**) SVGA: Mode "1152x910": mode clock = 47.500 + + This is normal, because with pixel multiplexing, only half the clock + is needed as two pixels are sent to the RAMDAC per clock pulse. + </descrip> For other screen drawing related problems, try the <tt>"noaccel"</tt> option. If you are having driver-related problems that are not addressed by this document, or if you have found bugs in accelerated functions, you can try contacting the XFree86 team. *************** *** 770,784 **** keep an eye on forthcoming beta releases at <it>www.xfree86.org</it>. <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/tseng.sgml,v 3.15.2.11 1997/08/02 13:48:15 dawes Exp $ ! $TOG: tseng.sgml /main/8 1997/08/10 13:02:28 kaleb $ </verb> </article> --- 952,1037 ---- keep an eye on forthcoming beta releases at <it>www.xfree86.org</it>. + <sect> Acknowledgments <p> + Most of these stem from the old XF86_W32 server. That code was used + extensively for getting the SVGA server to work on all the Tseng cards, so + they are still somewhat valid. + Glenn G. Lai wrote the original XF86_W32 server. It was modified by + Dirk Hohndel and Koen Gadeyne to support some more hardware. + + Jerry J. Shekhel (<it>jerry@msi.com</it>) gave me (GGL) the 1-M Mirage + ET4000/W32 VLB board on which the initial development (X_W32) was done. + + X11R6 and The XFree86 Project provide the base code for XF86_W32. + + Hercules Computer Technology Inc. lent me (GGL) a 2-M Hercules Dynamite Pro VLB + board for the development that led to <tt>XF86_W32</tt>. They donated a + Dynamite Power PCI to The XFree86 Project, that was used by DHH to extend + the server. + + Tseng Labs kindly donated (KMG) an ET6000-based board (a Jazz Multimedia + G-Force 128), which spurred the development of the ET6000 code. They also + provided an ET6100 evaluation board. + + Heiko Eissfeldt provided an ET4000W32p_rev_b board which allowed us to get + better support for those rev_a and rev_b boards. + + Numerous testers have given me feedback for <tt>X_W32</tt> and later + <tt>XF86_W32</tt>. I + apologize for my failure to keep track of the people who tested + <tt>X_W32</tt>, but + the names of the people involved with the <tt>XF86_W32</tt> testing are + listed below: + <descrip> + <tag>Linux:</tag> + <it>bf11620@coewl.cen.uiuc.edu</it> (Byron Thomas Faber) <newline> + <it>dlj0@chern.math.lehigh.edu</it> (David Johnson) <newline> + <it>peterc@a3.ph.man.ac.uk</it> (Peter Chang) <newline> + <it>dmm0t@rincewind.mech.virginia.edu</it> (David Meyer) <newline> + <it>nrh@philabs.Philips.COM</it> (Nikolaus R. Haus) <newline> + <it>jdooley@dbp.caltech.edu</it> (James Dooley) <newline> + <it>thumper@hitchcock.eng.uiowa.edu</it> (Timothy Paul Schlie) <newline> + <it>klatta@pkdla5.syntex.com</it> (Ken Latta) <newline> + <it>robinson@cnj.digex.net</it> (Andrew Robinson) <newline> + <it>reggie@phys.washington.edu</it> (Reginald S. Perry) <newline> + <it>sjm@cs.tut.fi</it> (M{kinen Sami J) <newline> + <it>engel@yacc.central.de</it> (C. Engelmann) <bf>use</bf> + <it>cengelm@gwdg.de</it> <newline> + <it>postgate@cafe.net</it> (Richard Postgate) <newline> + <it>are1@cec.wustl.edu</it> (Andy Ellsworth) <newline> + <it>bill@celtech.com</it> (Bill Foster) + <tag> FreeBSD: </tag> + <it>ljo@ljo-slip.DIALIN.CWRU.Edu</it> (L Jonas Olsson) + </descrip> + + Several people have developed code for the SVGA Tseng driver (this list is + incomplete): + <itemize> + <item>Glenn G. Lai + <item>Dirk H. Hohndel + <item>Koen Gadeyne + <item>OEyvind Aabling + <item>Dejan Ilic + <item>Mark Vojkovich + <item>Harald Nordgard Hansen + <item>David Bateman + <item>Gyorgy Krajcsovits + <item>Kurt Olsen + </itemize> + + + + + <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/tseng.sgml,v 3.15.2.13 1998/02/20 23:10:32 dawes Exp $ ! $TOG: tseng.sgml /main/9 1998/03/06 16:43:20 kaleb $ </verb> </article> *** ./programs/Xserver/hw/xfree86/etc/install.sv3@@/PUBLIC-LATEST Sat Jul 19 10:36:46 1997 --- xc/programs/Xserver/hw/xfree86/etc/install.sv3 Fri Mar 6 16:41:51 1998 *************** *** 1,6 **** #!/bin/sh # ! # $XFree86: xc/programs/Xserver/hw/xfree86/etc/install.sv3,v 3.6 1996/12/23 06:47:10 dawes Exp $ # # Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany. # --- 1,6 ---- #!/bin/sh # ! # $XFree86: xc/programs/Xserver/hw/xfree86/etc/install.sv3,v 3.6.2.1 1998/02/26 13:59:09 dawes Exp $ # # Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany. # *************** *** 30,41 **** # Changed for XFree86 3.1 to coexist with Interactive X11 by Michael Rohleder # (michael.rohleder@stadt-frankfurt.de) ! # $TOG: install.sv3 /main/5 1997/07/19 10:36:48 kaleb $ # # XFree86 version # ! VERSION=3.1.1 # # dependencies --- 30,41 ---- # Changed for XFree86 3.1 to coexist with Interactive X11 by Michael Rohleder # (michael.rohleder@stadt-frankfurt.de) ! # $TOG: install.sv3 /main/6 1998/03/06 16:43:29 kaleb $ # # XFree86 version # ! VERSION=3.3.2 # # dependencies *** ./programs/Xserver/hw/xfree86/etc/kbd_mode.man@@/PUBLIC-LATEST Tue Nov 4 21:17:57 1997 --- xc/programs/Xserver/hw/xfree86/etc/kbd_mode.man Fri Mar 6 16:41:56 1998 *************** *** 1,5 **** .\" $XFree86: xc/programs/Xserver/hw/xfree86/etc/kbd_mode.man,v 3.2 1996/12/23 06:47:14 dawes Exp $ ! .TH KBD_MODE 1 "Release 6.4 (XFree86 3.3.1)" "X Version 11" .SH NAME kbd_mode \- recover the PC console keyboard .SH SYNOPSIS --- 1,5 ---- .\" $XFree86: xc/programs/Xserver/hw/xfree86/etc/kbd_mode.man,v 3.2 1996/12/23 06:47:14 dawes Exp $ ! .TH KBD_MODE 1 "Release 6.3 (XFree86 3.2)" "X Version 11" .SH NAME kbd_mode \- recover the PC console keyboard .SH SYNOPSIS *************** *** 33,36 **** kbd_mode -u .sp ! .\" $TOG: kbd_mode.man /main/7 1997/11/04 21:20:52 kaleb $ --- 33,36 ---- kbd_mode -u .sp ! .\" $TOG: kbd_mode.man /main/8 1998/03/06 16:43:33 kaleb $ *** ./programs/Xserver/hw/xfree86/etc/postinst.sh@@/PUBLIC-LATEST Sun Aug 10 13:03:58 1997 --- xc/programs/Xserver/hw/xfree86/etc/postinst.sh Fri Mar 6 16:41:59 1998 *************** *** 1,8 **** #!/bin/sh ! # $XFree86: xc/programs/Xserver/hw/xfree86/etc/postinst.sh,v 3.13.2.4 1997/07/26 06:30:51 dawes Exp $ # ! # postinst.sh (for XFree86 3.3.1) # # This script should be run after installing a new version of XFree86. # --- 1,8 ---- #!/bin/sh ! # $XFree86: xc/programs/Xserver/hw/xfree86/etc/postinst.sh,v 3.13.2.6 1998/02/26 20:41:52 hohndel Exp $ # ! # postinst.sh (for XFree86 3.3.2) # # This script should be run after installing a new version of XFree86. # *************** *** 37,43 **** TERMCAPFILE="$TERMCAP2" fi fi ! if [ x"$TERMCAPFILE" != x ]; then echo "" echo "You appear to have a termcap file: $TERMCAPFILE" echo "This should be edited manually to replace the xterm entries" --- 37,43 ---- TERMCAPFILE="$TERMCAP2" fi fi ! if [ x"$TERMCAPFILE" != x -a `uname` != OpenBSD ]; then echo "" echo "You appear to have a termcap file: $TERMCAPFILE" echo "This should be edited manually to replace the xterm entries" *** ./programs/Xserver/hw/xfree86/etc/preinst.sh@@/PUBLIC-LATEST Sun Aug 10 13:04:03 1997 --- xc/programs/Xserver/hw/xfree86/etc/preinst.sh Fri Mar 6 16:42:04 1998 *************** *** 1,8 **** #!/bin/sh ! # $XFree86: xc/programs/Xserver/hw/xfree86/etc/preinst.sh,v 3.8.2.4 1997/07/19 07:00:08 dawes Exp $ # ! # preinst.sh (for XFree86 3.3.1) # # This script should be run before installing a new version. # --- 1,8 ---- #!/bin/sh ! # $XFree86: xc/programs/Xserver/hw/xfree86/etc/preinst.sh,v 3.8.2.5 1998/02/26 20:41:53 hohndel Exp $ # ! # preinst.sh (for XFree86 3.3.2) # # This script should be run before installing a new version. # *************** *** 10,16 **** # when extracting the new version. This includes symbolic links to old # beta versions, shared lib symlinks, and old files. # ! # $TOG: preinst.sh /main/7 1997/08/10 13:02:38 kaleb $ # RUNDIR=/usr/X11R6 --- 10,16 ---- # when extracting the new version. This includes symbolic links to old # beta versions, shared lib symlinks, and old files. # ! # $TOG: preinst.sh /main/8 1998/03/06 16:43:42 kaleb $ # RUNDIR=/usr/X11R6 *** ./programs/Xserver/hw/xfree86/etc/scanpci.c@@/PUBLIC-LATEST Sun Aug 10 13:04:08 1997 --- xc/programs/Xserver/hw/xfree86/etc/scanpci.c Fri Mar 6 16:42:08 1998 *************** *** 1,4 **** ! /* $TOG: scanpci.c /main/27 1997/08/10 13:02:43 kaleb $ */ /* * name: scanpci.c * --- 1,4 ---- ! /* $TOG: scanpci.c /main/28 1998/03/06 16:43:46 kaleb $ */ /* * name: scanpci.c * *************** *** 9,15 **** * * supported O/S's: SVR4, UnixWare, SCO, Solaris, * FreeBSD, NetBSD, 386BSD, BSDI BSD/386, ! * Linux, Mach/386, * DOS (WATCOM 9.5 compiler) * * compiling: [g]cc scanpci.c -o scanpci --- 9,15 ---- * * supported O/S's: SVR4, UnixWare, SCO, Solaris, * FreeBSD, NetBSD, 386BSD, BSDI BSD/386, ! * Linux, Mach/386, ISC * DOS (WATCOM 9.5 compiler) * * compiling: [g]cc scanpci.c -o scanpci *************** *** 21,27 **** * */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/etc/scanpci.c,v 3.34.2.4 1997/08/02 13:48:16 dawes Exp $ */ /* * Copyright 1995 by Robin Cutshaw <robin@XFree86.Org> --- 21,27 ---- * */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/etc/scanpci.c,v 3.34.2.10 1998/02/27 17:13:22 robin Exp $ */ /* * Copyright 1995 by Robin Cutshaw <robin@XFree86.Org> *************** *** 103,110 **** #define GCCUSESGAS #endif #endif ! #if defined(SCO) #include <sys/console.h> #include <sys/param.h> #include <sys/immu.h> #include <sys/region.h> --- 103,112 ---- #define GCCUSESGAS #endif #endif ! #if defined(SCO) || defined(ISC) ! #ifndef ISC #include <sys/console.h> + #endif #include <sys/param.h> #include <sys/immu.h> #include <sys/region.h> *************** *** 136,142 **** #if defined(__GNUC__) ! #if !defined(__alpha__) #if defined(GCCUSESGAS) #define OUTB_GCC "outb %0,%1" #define OUTL_GCC "outl %0,%1" --- 138,144 ---- #if defined(__GNUC__) ! #if !defined(__alpha__) && !defined(__powerpc__) #if defined(GCCUSESGAS) #define OUTB_GCC "outb %0,%1" #define OUTL_GCC "outl %0,%1" *************** *** 158,164 **** static unsigned long inl(unsigned short port) { unsigned long ret; __asm__ __volatile__(INL_GCC : "=a" (ret) : "d" (port)); return ret; } ! #endif /* !defined(__alpha__) */ #else /* __GNUC__ */ #if defined(__STDC__) && (__STDC__ == 1) --- 160,166 ---- static unsigned long inl(unsigned short port) { unsigned long ret; __asm__ __volatile__(INL_GCC : "=a" (ret) : "d" (port)); return ret; } ! #endif /* !defined(__alpha__) && !defined(__powerpc__) */ #else /* __GNUC__ */ #if defined(__STDC__) && (__STDC__ == 1) *************** *** 260,267 **** --- 262,334 ---- Generate compiler error - scanpci unsupported on non-linux alpha platforms #endif /* linux */ #endif /* __alpha__ */ + #if defined(Lynx) && defined(__powerpc__) + /* let's mimick the Linux Alpha stuff for LynxOS so we don't have + * to change too much code + */ + #include <smem.h> + unsigned char *pciConfBase; + static __inline__ unsigned long + swapl(unsigned long val) + { + unsigned char *p = (unsigned char *)&val; + return ((p[3] << 24) | (p[2] << 16) | (p[1] << 8) | (p[0] << 0)); + } + + + #define BUS(tag) (((tag)>>16)&0xff) + #define DFN(tag) (((tag)>>8)&0xff) + + #define PCIBIOS_DEVICE_NOT_FOUND 0x86 + #define PCIBIOS_SUCCESSFUL 0x00 + + int pciconfig_read( + unsigned char bus, + unsigned char dev, + unsigned char offset, + int len, /* unused, alway 4 */ + unsigned long *val) + { + unsigned long _val; + unsigned long *ptr; + + dev >>= 3; + if (bus || dev >= 16) { + *val = 0xFFFFFFFF; + return PCIBIOS_DEVICE_NOT_FOUND; + } else { + ptr = (unsigned long *)(pciConfBase + ((1<<dev) | offset)); + _val = swapl(*ptr); + } + *val = _val; + return PCIBIOS_SUCCESSFUL; + } + + int pciconfig_write( + unsigned char bus, + unsigned char dev, + unsigned char offset, + int len, /* unused, alway 4 */ + unsigned long val) + { + unsigned long _val; + unsigned long *ptr; + + dev >>= 3; + _val = swapl(val); + if (bus || dev >= 16) { + return PCIBIOS_DEVICE_NOT_FOUND; + } else { + ptr = (unsigned long *)(pciConfBase + ((1<<dev) | offset)); + *ptr = _val; + } + return PCIBIOS_SUCCESSFUL; + } + #endif + + #if !defined(__powerpc__) struct pci_config_reg { /* start of official PCI config space header */ union { *************** *** 395,401 **** --- 462,611 ---- unsigned short _ioaddr; /* config type 1 - private I/O addr */ unsigned long _cardnum; /* config type 2 - private card number */ }; + #else + /* ppc is big endian, swapping bytes is not quite enough + * to interpret the PCI config registers... + */ + struct pci_config_reg { + /* start of official PCI config space header */ + union { + unsigned long device_vendor; + struct { + unsigned short device; + unsigned short vendor; + } dv; + } dv_id; + #define _device_vendor dv_id.device_vendor + #define _vendor dv_id.dv.vendor + #define _device dv_id.dv.device + union { + unsigned long status_command; + struct { + unsigned short status; + unsigned short command; + } sc; + } stat_cmd; + #define _status_command stat_cmd.status_command + #define _command stat_cmd.sc.command + #define _status stat_cmd.sc.status + union { + unsigned long class_revision; + struct { + unsigned char base_class; + unsigned char sub_class; + unsigned char prog_if; + unsigned char rev_id; + } cr; + } class_rev; + #define _class_revision class_rev.class_revision + #define _rev_id class_rev.cr.rev_id + #define _prog_if class_rev.cr.prog_if + #define _sub_class class_rev.cr.sub_class + #define _base_class class_rev.cr.base_class + union { + unsigned long bist_header_latency_cache; + struct { + unsigned char bist; + unsigned char header_type; + unsigned char latency_timer; + unsigned char cache_line_size; + } bhlc; + } bhlc; + #define _bist_header_latency_cache bhlc.bist_header_latency_cache + #define _cache_line_size bhlc.bhlc.cache_line_size + #define _latency_timer bhlc.bhlc.latency_timer + #define _header_type bhlc.bhlc.header_type + #define _bist bhlc.bhlc.bist + union { + struct { + unsigned long dv_base0; + unsigned long dv_base1; + unsigned long dv_base2; + unsigned long dv_base3; + unsigned long dv_base4; + unsigned long dv_base5; + } dv; + /* ?? */ + struct { + unsigned long bg_rsrvd[2]; + unsigned char secondary_latency_timer; + unsigned char subordinate_bus_number; + unsigned char secondary_bus_number; + unsigned char primary_bus_number; + + unsigned short secondary_status; + unsigned char io_limit; + unsigned char io_base; + + unsigned short mem_limit; + unsigned short mem_base; + + unsigned short prefetch_mem_limit; + unsigned short prefetch_mem_base; + } bg; + } bc; + #define _base0 bc.dv.dv_base0 + #define _base1 bc.dv.dv_base1 + #define _base2 bc.dv.dv_base2 + #define _base3 bc.dv.dv_base3 + #define _base4 bc.dv.dv_base4 + #define _base5 bc.dv.dv_base5 + #define _primary_bus_number bc.bg.primary_bus_number + #define _secondary_bus_number bc.bg.secondary_bus_number + #define _subordinate_bus_number bc.bg.subordinate_bus_number + #define _secondary_latency_timer bc.bg.secondary_latency_timer + #define _io_base bc.bg.io_base + #define _io_limit bc.bg.io_limit + #define _secondary_status bc.bg.secondary_status + #define _mem_base bc.bg.mem_base + #define _mem_limit bc.bg.mem_limit + #define _prefetch_mem_base bc.bg.prefetch_mem_base + #define _prefetch_mem_limit bc.bg.prefetch_mem_limit + unsigned long rsvd1; + unsigned long rsvd2; + unsigned long _baserom; + unsigned long rsvd3; + unsigned long rsvd4; + union { + unsigned long max_min_ipin_iline; + struct { + unsigned char max_lat; + unsigned char min_gnt; + unsigned char int_pin; + unsigned char int_line; + } mmii; + } mmii; + #define _max_min_ipin_iline mmii.max_min_ipin_iline + #define _int_line mmii.mmii.int_line + #define _int_pin mmii.mmii.int_pin + #define _min_gnt mmii.mmii.min_gnt + #define _max_lat mmii.mmii.max_lat + /* I don't know how accurate or standard this is (DHD) */ + union { + unsigned long user_config; + struct { + unsigned char user_config_3; + unsigned char user_config_2; + unsigned char user_config_1; + unsigned char user_config_0; + } uc; + } uc; + #define _user_config uc.user_config + #define _user_config_0 uc.uc.user_config_0 + #define _user_config_1 uc.uc.user_config_1 + #define _user_config_2 uc.uc.user_config_2 + #define _user_config_3 uc.uc.user_config_3 + /* end of official PCI config space header */ + unsigned long _pcibusidx; + unsigned long _pcinumbus; + unsigned long _pcibuses[16]; + unsigned short _ioaddr; /* config type 1 - private I/O addr */ + unsigned short _configtype; /* config type found */ + unsigned long _cardnum; /* config type 2 - private card number */ + }; + #endif + extern void identify_card(struct pci_config_reg *, int); extern void print_i128(struct pci_config_reg *); extern void print_mach64(struct pci_config_reg *); *************** *** 408,414 **** #define MAX_PCI_DEVICES 64 #define NF ((void (*)())NULL) #define PCI_MULTIFUNC_DEV 0x80 ! #if defined(__alpha__) #define PCI_ID_REG 0x00 #define PCI_CMD_STAT_REG 0x04 #define PCI_CLASS_REG 0x08 --- 618,624 ---- #define MAX_PCI_DEVICES 64 #define NF ((void (*)())NULL) #define PCI_MULTIFUNC_DEV 0x80 ! #if defined(__alpha__) || defined(__powerpc__) #define PCI_ID_REG 0x00 #define PCI_CMD_STAT_REG 0x04 #define PCI_CLASS_REG 0x08 *************** *** 429,434 **** --- 639,654 ---- } device[MAX_DEV_PER_VENDOR_CFG1]; } pvd[] = { { 0x0e11, "Compaq", { + { 0x3033, "QVision 1280/p", NF }, + { 0xae10, "Smart-2/P RAID Controller", NF }, + { 0xae32, "Netellignet 10/100", NF }, + { 0xae34, "Netellignet 10", NF }, + { 0xae35, "NetFlex 3", NF }, + { 0xae40, "Netellignet 10/100 Dual", NF }, + { 0xae43, "Netellignet 10/100 ProLiant", NF }, + { 0xb011, "Netellignet 10/100 Integrated", NF }, + { 0xf130, "ThunderLAN", NF }, + { 0xf150, "NetFlex 3 BNC", NF }, { 0x0000, (char *)NULL, NF } } }, { 0x1000, "NCR", { { 0x0001, "53C810", NF }, *************** *** 437,461 **** { 0x0004, "53C815", NF }, { 0x0005, "53C810AP", NF }, { 0x0006, "53C860", NF }, { 0x000F, "53C875", NF }, { 0x0000, (char *)NULL, NF } } }, { 0x1002, "ATI", { { 0x4158, "Mach32", NF }, - { 0x4758, "Mach64 GX", print_mach64 }, - { 0x4358, "Mach64 CX", print_mach64 }, { 0x4354, "Mach64 CT", print_mach64 }, { 0x4554, "Mach64 ET", print_mach64 }, ! { 0x5654, "Mach64 VT", print_mach64 }, { 0x4754, "Mach64 GT", print_mach64 }, { 0x0000, (char *)NULL, NF } } }, { 0x1004, "VLSI", { { 0x0005, "82C592-FC1", NF }, { 0x0006, "82C593-FC1", NF }, { 0x0000, (char *)NULL, NF } } }, { 0x1005, "Avance Logic", { { 0x2301, "ALG2301", NF }, { 0x0000, (char *)NULL, NF } } }, { 0x100B, "NS", { { 0xD001, "87410", NF }, { 0x0000, (char *)NULL, NF } } }, { 0x100C, "Tseng Labs", { --- 657,696 ---- { 0x0004, "53C815", NF }, { 0x0005, "53C810AP", NF }, { 0x0006, "53C860", NF }, + { 0x000B, "53C896", NF }, + { 0x000C, "53C895", NF }, + { 0x000D, "53C885", NF }, { 0x000F, "53C875", NF }, + { 0x008F, "53C875J", NF }, { 0x0000, (char *)NULL, NF } } }, { 0x1002, "ATI", { { 0x4158, "Mach32", NF }, { 0x4354, "Mach64 CT", print_mach64 }, + { 0x4358, "Mach64 CX", print_mach64 }, { 0x4554, "Mach64 ET", print_mach64 }, ! { 0x4742, "Mach64 GB", print_mach64 }, ! { 0x4744, "Mach64 GD", print_mach64 }, ! { 0x4750, "Mach64 GP", print_mach64 }, { 0x4754, "Mach64 GT", print_mach64 }, + { 0x4755, "Mach64 GT", print_mach64 }, + { 0x4758, "Mach64 GX", print_mach64 }, + { 0x4C47, "Mach64 LT", print_mach64 }, + { 0x5654, "Mach64 VT", print_mach64 }, { 0x0000, (char *)NULL, NF } } }, { 0x1004, "VLSI", { { 0x0005, "82C592-FC1", NF }, { 0x0006, "82C593-FC1", NF }, + { 0x0007, "82C594-AFC2", NF }, + { 0x0009, "82C597-AFC2", NF }, + { 0x000C, "82C541 Lynx", NF }, + { 0x000D, "82C543 Lynx ISA", NF }, + { 0x0702, "VAS96011", NF }, { 0x0000, (char *)NULL, NF } } }, { 0x1005, "Avance Logic", { { 0x2301, "ALG2301", NF }, { 0x0000, (char *)NULL, NF } } }, { 0x100B, "NS", { + { 0x0002, "87415", NF }, { 0xD001, "87410", NF }, { 0x0000, (char *)NULL, NF } } }, { 0x100C, "Tseng Labs", { *************** *** 463,469 **** { 0x3205, "ET4000w32p rev B", NF }, { 0x3206, "ET4000w32p rev D", NF }, { 0x3207, "ET4000w32p rev C", NF }, ! { 0x3208, "ET6000", NF }, { 0x0000, (char *)NULL, NF } } }, { 0x100E, "Weitek", { { 0x9001, "P9000", NF }, --- 698,705 ---- { 0x3205, "ET4000w32p rev B", NF }, { 0x3206, "ET4000w32p rev D", NF }, { 0x3207, "ET4000w32p rev C", NF }, ! { 0x3208, "ET6000/6100", NF }, ! { 0x4702, "ET6300", NF }, { 0x0000, (char *)NULL, NF } } }, { 0x100E, "Weitek", { { 0x9001, "P9000", NF }, *************** *** 472,480 **** { 0x1011, "Digital Equipment Corporation", { { 0x0001, "DC21050 PCI-PCI Bridge",print_pcibridge}, { 0x0002, "DC21040 10Mb/s Ethernet", NF }, { 0x0009, "DC21140 10/100 Mb/s Ethernet", NF }, ! { 0x0014, "DC21041 10Mb/s Ethernet Plus", NF }, { 0x000F, "DEFPA (FDDI PCI)", NF }, { 0x0000, (char *)NULL, NF } } }, { 0x1013, "Cirrus Logic", { { 0x0038, "GD 7548", NF }, --- 708,721 ---- { 0x1011, "Digital Equipment Corporation", { { 0x0001, "DC21050 PCI-PCI Bridge",print_pcibridge}, { 0x0002, "DC21040 10Mb/s Ethernet", NF }, + { 0x0004, "TGA", NF }, { 0x0009, "DC21140 10/100 Mb/s Ethernet", NF }, ! { 0x000D, "TGA2", NF }, { 0x000F, "DEFPA (FDDI PCI)", NF }, + { 0x0014, "DC21041 10Mb/s Ethernet Plus", NF }, + { 0x0019, "DC21142 10/100 Mb/s Ethernet", NF }, + { 0x0021, "DC21052", NF }, + { 0x0024, "DC21152", NF }, { 0x0000, (char *)NULL, NF } } }, { 0x1013, "Cirrus Logic", { { 0x0038, "GD 7548", NF }, *************** *** 483,501 **** --- 724,748 ---- { 0x00A8, "GD 5434-8", NF }, { 0x00AC, "GD 5436", NF }, { 0x00B8, "GD 5446", NF }, + { 0x00BC, "GD 5480", NF }, { 0x00D0, "GD 5462", NF }, { 0x00D4, "GD 5464", NF }, { 0x1100, "CL 6729", NF }, + { 0x1110, "CL 6832", NF }, { 0x1200, "GD 7542", NF }, { 0x1202, "GD 7543", NF }, { 0x1204, "GD 7541", NF }, { 0x0000, (char *)NULL, NF } } }, { 0x1014, "IBM", { + { 0x000A, "Fire Coral", NF }, + { 0x0018, "Token Ring", NF }, + { 0x001D, "82G2675", NF }, { 0x0022, "82351 pci-pci bridge", NF }, { 0x0000, (char *)NULL, NF } } }, { 0x101A, "NCR", { { 0x0000, (char *)NULL, NF } } }, { 0x101C, "WD*", { + { 0x3296, "WD 7197", NF }, { 0x0000, (char *)NULL, NF } } }, { 0x1022, "AMD", { { 0x2000, "79C970 Lance", NF }, *************** *** 510,515 **** --- 757,763 ---- { 0x9680, "TGUI 9680", NF }, { 0x9682, "TGUI 9682", NF }, #endif + { 0x9750, "TGUI 9750", NF }, { 0x0000, (char *)NULL, NF } } }, { 0x1025, "ALI", { { 0x1435, "M1435", NF }, *************** *** 528,534 **** --- 776,786 ---- { 0x00E4, "65554", NF }, { 0x0000, (char *)NULL, NF } } }, { 0x1031, "Miro", { + { 0x5601, "ZR36050", NF }, { 0x0000, (char *)NULL, NF } } }, + { 0x1033, "NEC", { + { 0x0046, "PowerVR PCX2", NF }, + { 0x0000, (char *)NULL, NF } } }, { 0x1036, "FD", { { 0x0000, "TMC-18C30 (36C70)", NF }, { 0x0000, (char *)NULL, NF } } }, *************** *** 540,584 **** { 0x0406, "85C501", NF }, { 0x0496, "85C496", NF }, { 0x0601, "85C601", NF }, { 0x0000, (char *)NULL, NF } } }, ! { 0x103c, "HP", { { 0x1030, "J2585A", NF }, { 0x0000, (char *)NULL, NF } } }, ! { 0x1042, "SMC", { ! { 0x1000, "FDC 37C665", NF }, { 0x0000, (char *)NULL, NF } } }, { 0x1044, "DPT", { { 0xA400, "SmartCache/Raid", NF }, { 0x0000, (char *)NULL, NF } } }, { 0x1045, "Opti", { ! { 0xC557, "82C557", NF }, ! { 0xC558, "82C558", NF }, { 0xC621, "82C621", NF }, { 0xC822, "82C822", NF }, { 0x0000, (char *)NULL, NF } } }, { 0x104A, "SGS Thomson", { { 0x0000, (char *)NULL, NF } } }, { 0x104B, "BusLogic", { { 0x0140, "946C 01", NF }, { 0x1040, "946C 10", NF }, { 0x0000, (char *)NULL, NF } } }, { 0x105A, "Promise", { { 0x5300, "DC5030", NF }, { 0x0000, (char *)NULL, NF } } }, { 0x105D, "Number Nine", { { 0x2309, "Imagine-128", print_i128 }, { 0x2339, "Imagine-128-II", print_i128 }, { 0x0000, (char *)NULL, NF } } }, { 0x1060, "UMC", { { 0x0101, "UM8673F", NF }, { 0x8881, "UM8881F", NF }, { 0x8886, "UM8886F", NF }, - { 0x888A, "UM8886A", NF }, { 0x8891, "UM8891A", NF }, { 0x0000, (char *)NULL, NF } } }, { 0x1061, "X", { { 0x0001, "ITT AGX016", NF }, { 0x0000, (char *)NULL, NF } } }, { 0x1074, "Nexgen", { { 0x0000, (char *)NULL, NF } } }, { 0x1077, "QLogic", { --- 792,882 ---- { 0x0406, "85C501", NF }, { 0x0496, "85C496", NF }, { 0x0601, "85C601", NF }, + { 0x5107, "5107", NF }, + { 0x5511, "85C5511", NF }, + { 0x5513, "85C5513", NF }, + { 0x5571, "5571", NF }, + { 0x5597, "5597", NF }, + { 0x7001, "7001", NF }, { 0x0000, (char *)NULL, NF } } }, ! { 0x103C, "HP", { { 0x1030, "J2585A", NF }, + { 0x1031, "J2585B", NF }, { 0x0000, (char *)NULL, NF } } }, ! { 0x1042, "SMC/PCTECH", { ! { 0x1000, "FDC 37C665/RZ1000", NF }, ! { 0x1001, "FDC /RZ1001", NF }, { 0x0000, (char *)NULL, NF } } }, { 0x1044, "DPT", { { 0xA400, "SmartCache/Raid", NF }, { 0x0000, (char *)NULL, NF } } }, { 0x1045, "Opti", { ! { 0xC178, "92C178", NF }, ! { 0xC557, "82C557 Viper-M", NF }, ! { 0xC558, "82C558 Viper-M ISA+IDE", NF }, { 0xC621, "82C621", NF }, + { 0xC700, "82C700", NF }, + { 0xC701, "82C701 FireStar Plus", NF }, + { 0xC814, "82C814 Firebridge 1", NF }, { 0xC822, "82C822", NF }, { 0x0000, (char *)NULL, NF } } }, { 0x104A, "SGS Thomson", { + { 0x0008, "STG2000", NF }, + { 0x0009, "STG1764", NF }, { 0x0000, (char *)NULL, NF } } }, { 0x104B, "BusLogic", { { 0x0140, "946C 01", NF }, { 0x1040, "946C 10", NF }, + { 0x8130, "FlashPoint", NF }, { 0x0000, (char *)NULL, NF } } }, + { 0x104C, "Texas Instruments", { + { 0x3d04, "3DLabs Permedia", NF }, + { 0x3d07, "3DLabs Permedia 2", NF }, + { 0xAC12, "PCI1130", NF }, + { 0xAC15, "PCI1131", NF }, + { 0x0000, (char *)NULL, NF } } }, + { 0x104E, "Oak", { + { 0x0107, "OTI107", NF }, + { 0x0000, (char *)NULL, NF } } }, + { 0x1050, "Windbond", { + { 0x0940, "89C940 NE2000-PCI", NF }, + { 0x0000, (char *)NULL, NF } } }, + { 0x1057, "Motorola", { + { 0x0001, "MPC105 Eagle", NF }, + { 0x0002, "MPC105 Grackle", NF }, + { 0x4801, "Raven", NF }, + { 0x0000, (char *)NULL, NF } } }, { 0x105A, "Promise", { + { 0x4D33, "IDE UltraDMA/33", NF }, { 0x5300, "DC5030", NF }, { 0x0000, (char *)NULL, NF } } }, { 0x105D, "Number Nine", { { 0x2309, "Imagine-128", print_i128 }, { 0x2339, "Imagine-128-II", print_i128 }, + { 0x493D, "Imagine-128-T2R", print_i128 }, { 0x0000, (char *)NULL, NF } } }, { 0x1060, "UMC", { { 0x0101, "UM8673F", NF }, + { 0x673A, "UM8886BF", NF }, + { 0x886A, "UM8886A", NF }, { 0x8881, "UM8881F", NF }, { 0x8886, "UM8886F", NF }, { 0x8891, "UM8891A", NF }, + { 0x9017, "UM9017F", NF }, + { 0xE886, "UM8886N", NF }, + { 0xE891, "UM8891N", NF }, { 0x0000, (char *)NULL, NF } } }, { 0x1061, "X", { { 0x0001, "ITT AGX016", NF }, { 0x0000, (char *)NULL, NF } } }, + { 0x1066, "PICOP", { + { 0x0001, "PT86C52x Vesuvius", NF }, + { 0x0000, (char *)NULL, NF } } }, + { 0x106B, "Apple", { + { 0x0001, "Bandit", NF }, + { 0x0002, "Grand Central", NF }, + { 0x000E, "Hydra", NF }, + { 0x0000, (char *)NULL, NF } } }, { 0x1074, "Nexgen", { { 0x0000, (char *)NULL, NF } } }, { 0x1077, "QLogic", { *************** *** 585,590 **** --- 883,898 ---- { 0x1020, "ISP1020", NF }, { 0x1022, "ISP1022", NF }, { 0x0000, (char *)NULL, NF } } }, + { 0x1078, "Cyrix", { + { 0x0000, "5510", NF }, + { 0x0001, "PCI Master", NF }, + { 0x0002, "5520", NF }, + { 0x0100, "5530 Kahlua Legacy", NF }, + { 0x0101, "5530 Kahlua SMI", NF }, + { 0x0102, "5530 Kahlua IDE", NF }, + { 0x0103, "5530 Kahlua Audio", NF }, + { 0x0104, "5530 Kahlua Video", NF }, + { 0x0000, (char *)NULL, NF } } }, { 0x107D, "Leadtek", { { 0x0000, "S3 805", NF }, { 0x0000, (char *)NULL, NF } } }, *************** *** 591,638 **** --- 899,1024 ---- { 0x1080, "Contaq", { { 0x0600, "82C599", NF }, { 0x0000, (char *)NULL, NF } } }, + { 0x1083, "FOREX", { + { 0x0000, (char *)NULL, NF } } }, + { 0x108D, "Olicom", { + { 0x0001, "OC-3136", NF }, + { 0x0011, "OC-2315", NF }, + { 0x0012, "OC-2325", NF }, + { 0x0013, "OC-2183", NF }, + { 0x0014, "OC-2326", NF }, + { 0x0021, "OC-6151", NF }, + { 0x0000, (char *)NULL, NF } } }, + { 0x108E, "Sun", { + { 0x1000, "EBUS", NF }, + { 0x1001, "Happy Meal", NF }, + { 0x8000, "PCI Bus Module", NF }, + { 0x0000, (char *)NULL, NF } } }, { 0x1095, "CMD", { { 0x0640, "640A", NF }, + { 0x0643, "643", NF }, + { 0x0646, "646", NF }, + { 0x0670, "670", NF }, { 0x0000, (char *)NULL, NF } } }, { 0x1098, "Vision", { { 0x0001, "QD 8500", NF }, { 0x0002, "QD 8580", NF }, { 0x0000, (char *)NULL, NF } } }, + { 0x109E, "Brooktree", { + { 0x0350, "Bt848", NF }, + { 0x0000, (char *)NULL, NF } } }, { 0x10A8, "Sierra", { + { 0x0000, "STB Horizon 64", NF }, { 0x0000, (char *)NULL, NF } } }, { 0x10AA, "ACC", { + { 0x0000, "2056", NF }, { 0x0000, (char *)NULL, NF } } }, { 0x10AD, "Winbond", { { 0x0001, "W83769F", NF }, + { 0x0105, "SL82C105", NF }, + { 0x0565, "W83C553", NF }, { 0x0000, (char *)NULL, NF } } }, + { 0x10B3, "Databook", { + { 0xB106, "DB87144", NF }, + { 0x0000, (char *)NULL, NF } } }, { 0x10B7, "3COM", { { 0x5900, "3C590 10bT", NF }, { 0x5950, "3C595 100bTX", NF }, { 0x5951, "3C595 100bT4", NF }, { 0x5952, "3C595 10b-MII", NF }, + { 0x9000, "3C900 10bTPO", NF }, + { 0x9001, "3C900 10b Combo", NF }, + { 0x9050, "3C905 100bTX", NF }, { 0x0000, (char *)NULL, NF } } }, + { 0x10B8, "SMC", { + { 0x0005, "9432 TX", NF }, + { 0x0000, (char *)NULL, NF } } }, { 0x10B9, "ALI", { { 0x1445, "M1445", NF }, { 0x1449, "M1449", NF }, { 0x1451, "M1451", NF }, + { 0x1461, "M1461", NF }, + { 0x1489, "M1489", NF }, + { 0x1511, "M1511", NF }, + { 0x1513, "M1513", NF }, + { 0x1521, "M1521", NF }, + { 0x1523, "M1523", NF }, + { 0x1531, "M1531 Aladdin IV", NF }, + { 0x1533, "M1533 Aladdin IV", NF }, { 0x5215, "M4803", NF }, + { 0x5219, "M5219", NF }, + { 0x5229, "M5229 TXpro", NF }, { 0x0000, (char *)NULL, NF } } }, + { 0x10BA, "Mitsubishi", { + { 0x0000, (char *)NULL, NF } } }, + { 0x10BD, "Surecom", { + { 0x0E34, "NE-34PCI Lan", NF }, + { 0x0000, (char *)NULL, NF } } }, + { 0x10C8, "Neomagic", { + { 0x0001, "Magicgraph NM2070", NF }, + { 0x0002, "Magicgraph 128V", NF }, + { 0x0003, "Magicgraph 128ZV", NF }, + { 0x0004, "Magicgraph NM2160", NF }, + { 0x0000, (char *)NULL, NF } } }, { 0x10CD, "Advanced System Products", { + { 0x1200, "ABP940", NF }, + { 0x1300, "ABP940U", NF }, { 0x0000, (char *)NULL, NF } } }, { 0x10DC, "CERN", { + { 0x0001, "STAR/RD24 SCI-PCI (PMC)", NF }, + { 0x0002, "STAR/RD24 SCI-PCI (PMC)", NF }, { 0x0000, (char *)NULL, NF } } }, + { 0x10DE, "NVidia", { + { 0x0008, "NV1", NF }, + { 0x0009, "DAC64", NF }, + { 0x0000, (char *)NULL, NF } } }, { 0x10E0, "IMS", { { 0x8849, "8849", NF }, { 0x0000, (char *)NULL, NF } } }, { 0x10E1, "Tekram", { + { 0x690C, "DC690C", NF }, { 0x0000, (char *)NULL, NF } } }, + { 0x10E3, "Tundra", { + { 0x0000, "CA91C042 Universe", NF }, + { 0x0000, (char *)NULL, NF } } }, { 0x10E8, "AMCC", { + { 0x8043, "Myrinet PCI (M2-PCI-32)", NF }, + { 0x807D, "S5933 PCI44", NF }, + { 0x809C, "S5933 Traquair HEPC3", NF }, { 0x0000, (char *)NULL, NF } } }, { 0x10EA, "Intergraphics", { + { 0x1680, "IGA-1680", NF }, + { 0x1682, "IGA-1682", NF }, { 0x0000, (char *)NULL, NF } } }, { 0x10EC, "Realtek", { + { 0x8029, "8029", NF }, + { 0x8129, "8129", NF }, { 0x0000, (char *)NULL, NF } } }, + { 0x10FA, "Truevision", { + { 0x000C, "Targa 1000", NF }, + { 0x0000, (char *)NULL, NF } } }, { 0x1101, "Initio Corp", { + { 0x9100, "320 P", NF }, { 0x0000, (char *)NULL, NF } } }, { 0x1106, "VIA", { { 0x0505, "VT 82C505", NF }, *************** *** 663,668 **** --- 1049,1058 ---- { 0x1159, "Mutech", { { 0x0001, "MV1000", NF }, { 0x0000, (char *)NULL, NF } } }, + { 0x1163, "Rendition", { + { 0x0001, "V1000", NF }, + { 0x2000, "V2100", NF }, + { 0x0000, (char *)NULL, NF } } }, { 0x1179, "Toshiba", { { 0x0000, (char *)NULL, NF } } }, { 0x1193, "Zeinet", { *************** *** 674,684 **** --- 1064,1083 ---- { 0x0000, (char *)NULL, NF } } }, { 0x120E, "Cyclades", { { 0x0000, (char *)NULL, NF } } }, + { 0x121A, "3Dfx Interactive", { + { 0x0001, "Voodoo Graphics", NF }, + { 0x0000, (char *)NULL, NF } } }, { 0x1236, "Sigma Designs", { { 0x6401, "REALmagic64/GX (SD 6425)", NF }, { 0x0000, (char *)NULL, NF } } }, { 0x1281, "YOKOGAWA", { { 0x0000, (char *)NULL, NF } } }, + { 0x1292, "TriTech Microelectronics", { + { 0xfc02, "Pyramid3D TR25202", NF }, + { 0x0000, (char *)NULL, NF } } }, + { 0x12D2, "NVidia/SGS-Thomson", { + { 0x0018, "Riva128", NF }, + { 0x0000, (char *)NULL, NF } } }, { 0x1C1C, "Symphony", { { 0x0001, "82C101", NF }, { 0x0000, (char *)NULL, NF } } }, *************** *** 689,703 **** { 0x0001, "GLINT 300SX", NF }, { 0x0002, "GLINT 500TX", NF }, { 0x0003, "GLINT Delta", NF }, ! { 0x0000, (char *)NULL, NF } } } , { 0x4005, "Avance", { { 0x0000, (char *)NULL, NF } } }, { 0x5333, "S3", { { 0x8811, "Trio32/64", NF }, { 0x8812, "Aurora64V+", NF }, { 0x8814, "Trio64UV+", NF }, ! { 0x8901, "Trio64V2/DX or /GX", NF }, ! { 0x8902, "PLATO/PX", NF }, { 0x8880, "868", NF }, { 0x88B0, "928", NF }, { 0x88C0, "864-0", NF }, --- 1088,1106 ---- { 0x0001, "GLINT 300SX", NF }, { 0x0002, "GLINT 500TX", NF }, { 0x0003, "GLINT Delta", NF }, ! { 0x0004, "GLINT Permedia", NF }, ! { 0x0006, "GLINT MX", NF }, ! { 0x0007, "GLINT Permedia 2", NF }, ! { 0x0000, (char *)NULL, NF } } } , { 0x4005, "Avance", { { 0x0000, (char *)NULL, NF } } }, { 0x5333, "S3", { + { 0x0551, "Plato/PX", NF }, + { 0x5631, "ViRGE", NF }, { 0x8811, "Trio32/64", NF }, { 0x8812, "Aurora64V+", NF }, { 0x8814, "Trio64UV+", NF }, ! { 0x883D, "ViRGE/VX", NF }, { 0x8880, "868", NF }, { 0x88B0, "928", NF }, { 0x88C0, "864-0", NF }, *************** *** 705,713 **** { 0x88D0, "964-0", NF }, { 0x88D1, "964-1", NF }, { 0x88F0, "968", NF }, ! { 0x5631, "ViRGE", NF }, ! { 0x883D, "ViRGE/VX", NF }, ! { 0x8A01, "ViRGE/DX or /GX", NF }, { 0x0000, (char *)NULL, NF } } }, { 0x8086, "Intel", { { 0x0482, "82375EB pci-eisa bridge", NF }, --- 1108,1120 ---- { 0x88D0, "964-0", NF }, { 0x88D1, "964-1", NF }, { 0x88F0, "968", NF }, ! { 0x8901, "Trio64V2/DX or /GX", NF }, ! { 0x8902, "PLATO/PX", NF }, ! { 0x8A01, "ViRGE/DX or /GX", NF }, ! { 0x8A10, "ViRGE/GX2", NF }, ! { 0x8C01, "ViRGE/MX", NF }, ! { 0x8C02, "ViRGE/MX+", NF }, ! { 0x8C03, "ViRGE/MX+MV", NF }, { 0x0000, (char *)NULL, NF } } }, { 0x8086, "Intel", { { 0x0482, "82375EB pci-eisa bridge", NF }, *************** *** 717,722 **** --- 1124,1130 ---- { 0x04A3, "82434LX/NX pci cache mem controller", NF }, { 0x1230, "82371 bus-master IDE controller", NF }, { 0x1223, "SAA7116", NF }, + { 0x1229, "82557 10/100MBit network controller",NF}, { 0x122D, "82437 Triton", NF }, { 0x122E, "82471 Triton", NF }, { 0x1230, "82438", NF }, *************** *** 723,728 **** --- 1131,1141 ---- { 0x1250, "82439", NF }, { 0x7000, "82371 pci-isa bridge", NF }, { 0x7010, "82371 bus-master IDE controller", NF }, + { 0x7100, "82439 TX", NF }, + { 0x7110, "82371AB PIIX4 ISA", NF }, + { 0x7111, "82371AB PIIX4 IDE", NF }, + { 0x7112, "82371AB PIIX4 USB", NF }, + { 0x7113, "82371AB PIIX4 ACPI", NF }, { 0x0000, (char *)NULL, NF } } }, { 0x9004, "Adaptec", { { 0x5078, "7850", NF }, *************** *** 745,753 **** { 0xA0A1, "2000MT", NF }, { 0xA0A9, "2000MI", NF }, { 0x0000, (char *)NULL, NF } } }, - { 0x109E, "Brooktree", { - { 0x0350, "BT-848", NF}, - { 0x0000, (char *)NULL, NF } } }, { 0x0000, (char *)NULL, { { 0x0000, (char *)NULL, NF } } } }; --- 1158,1163 ---- *************** *** 775,794 **** unsigned char tmp1, tmp2; unsigned int idx; struct pci_config_reg pcr; ! int ch, verbose; int func; ! if (argc > 2) { ! printf("Usage: %s [-v] \n", argv[0]); ! exit(1); ! } ! while((ch = getopt(argc, argv, "v")) != EOF) { switch((char)ch) { case 'v': verbose = 1; break; default : ! printf("Usage: %s [-v] \n", argv[0]); exit(1); } } --- 1185,1206 ---- unsigned char tmp1, tmp2; unsigned int idx; struct pci_config_reg pcr; ! int ch, verbose = 0, do_mode1_scan = 0, do_mode2_scan = 0; int func; ! while((ch = getopt(argc, argv, "v12")) != EOF) { switch((char)ch) { + case '1': + do_mode1_scan = 1; + break; + case '2': + do_mode2_scan = 1; + break; case 'v': verbose = 1; break; default : ! printf("Usage: %s [-v12] \n", argv[0]); exit(1); } } *************** *** 801,807 **** enable_os_io(); ! #if !defined(__alpha__) pcr._configtype = 0; outb(PCI_MODE2_ENABLE_REG, 0x00); --- 1213,1219 ---- enable_os_io(); ! #if !defined(__alpha__) && !defined(__powerpc__) pcr._configtype = 0; outb(PCI_MODE2_ENABLE_REG, 0x00); *************** *** 831,836 **** --- 1243,1249 ---- /* Try pci config 1 probe first */ + if ((pcr._configtype == 1) || do_mode1_scan) { printf("\nPCI probing configuration type 1\n"); pcr._ioaddr = 0xFFFF; *************** *** 847,853 **** pcr._cardnum += 0x1) { func = 0; do { /* loop over the different functions, if present */ ! #if !defined(__alpha__) config_cmd = PCI_EN | (pcr._pcibuses[pcr._pcibusidx]<<16) | (pcr._cardnum<<11) | (func<<8); --- 1260,1266 ---- pcr._cardnum += 0x1) { func = 0; do { /* loop over the different functions, if present */ ! #if !defined(__alpha__) && !defined(__powerpc__) config_cmd = PCI_EN | (pcr._pcibuses[pcr._pcibusidx]<<16) | (pcr._cardnum<<11) | (func<<8); *************** *** 865,871 **** pcr._pcibuses[pcr._pcibusidx], pcr._cardnum, func, pcr._vendor, pcr._device); ! #if !defined(__alpha__) outl(PCI_MODE1_ADDRESS_REG, config_cmd | 0x04); pcr._status_command = inl(PCI_MODE1_DATA_REG); outl(PCI_MODE1_ADDRESS_REG, config_cmd | 0x08); --- 1278,1284 ---- pcr._pcibuses[pcr._pcibusidx], pcr._cardnum, func, pcr._vendor, pcr._device); ! #if !defined(__alpha__) && !defined(__powerpc__) outl(PCI_MODE1_ADDRESS_REG, config_cmd | 0x04); pcr._status_command = inl(PCI_MODE1_DATA_REG); outl(PCI_MODE1_ADDRESS_REG, config_cmd | 0x08); *************** *** 945,954 **** } while( func < 8 ); } } while (++pcr._pcibusidx < pcr._pcinumbus); ! #if !defined(__alpha__) /* Now try pci config 2 probe (deprecated) */ outb(PCI_MODE2_ENABLE_REG, 0xF1); outb(PCI_MODE2_FORWARD_REG, 0x00); /* bus 0 for now */ --- 1358,1369 ---- } while( func < 8 ); } } while (++pcr._pcibusidx < pcr._pcinumbus); + } ! #if !defined(__alpha__) && !defined(__powerpc__) /* Now try pci config 2 probe (deprecated) */ + if ((pcr._configtype == 2) || do_mode2_scan) { outb(PCI_MODE2_ENABLE_REG, 0xF1); outb(PCI_MODE2_FORWARD_REG, 0x00); /* bus 0 for now */ *************** *** 1002,1007 **** --- 1417,1423 ---- } while (++pcr._pcibusidx < pcr._pcinumbus); outb(PCI_MODE2_ENABLE_REG, 0x00); + } #endif /* __alpha__ */ *************** *** 1223,1229 **** void enable_os_io() { ! #if defined(SVR4) || defined(SCO) #if defined(SI86IOPL) sysi86(SI86IOPL, 3); #else --- 1639,1645 ---- void enable_os_io() { ! #if defined(SVR4) || defined(SCO) || defined(ISC) #if defined(SI86IOPL) sysi86(SI86IOPL, 3); #else *************** *** 1315,1320 **** --- 1731,1742 ---- DosClose(hfd); } #endif + #if defined(Lynx) && defined(__powerpc__) + pciConfBase = (unsigned char *) smem_create("PCI-CONF", + (char *)0x80800000, 64*1024, SM_READ|SM_WRITE); + if (pciConfBase == (void *) -1) + exit(1); + #endif } *************** *** 1321,1327 **** void disable_os_io() { ! #if defined(SVR4) || defined(SCO) #if defined(SI86IOPL) sysi86(SI86IOPL, 0); #else --- 1743,1749 ---- void disable_os_io() { ! #if defined(SVR4) || defined(SCO) || defined(ISC) #if defined(SI86IOPL) sysi86(SI86IOPL, 0); #else *************** *** 1359,1363 **** --- 1781,1790 ---- #endif #if defined(MACH386) close(io_fd); + #endif + #if defined(Lynx) && defined(__powerpc__) + smem_create(NULL, (char *) pciConfBase, 0, SM_DETACH); + smem_remove("PCI-CONF"); + pciConfBase = NULL; #endif } *** ./programs/Xserver/hw/xfree86/mono/Imakefile@@/PUBLIC-LATEST Sat Jul 19 18:05:17 1997 --- xc/programs/Xserver/hw/xfree86/mono/Imakefile Fri Mar 6 16:42:14 1998 *************** *** 1,4 **** ! XCOMM $TOG: Imakefile /main/12 1997/07/19 18:05:19 kaleb $ --- 1,4 ---- ! XCOMM $TOG: Imakefile /main/13 1998/03/06 16:43:52 kaleb $ *************** *** 31,37 **** NormalDepLibraryTarget(mono,$(SUBDIRS) $(DONES),$(OBJS)) ! ConfigTargetNoDepend(monoConf,$(ICONFIGFILES),confmono.sh,$(MONODRIVERS)) NormalLibraryObjectRule() --- 31,37 ---- NormalDepLibraryTarget(mono,$(SUBDIRS) $(DONES),$(OBJS)) ! ConfigTargetNoDepend(monoConf,$(ICONFIGFILES),confmono.SHsuf,$(MONODRIVERS)) NormalLibraryObjectRule() *************** *** 38,43 **** ForceSubdirs($(SUBDIRS)) InstallLinkKitLibrary(mono,$(LINKKITDIR)/drivers) ! InstallLinkKitNonExecFile(confmono.sh,$(LINKKITDIR)) DependSubdirs($(SUBDIRS)) --- 38,43 ---- ForceSubdirs($(SUBDIRS)) InstallLinkKitLibrary(mono,$(LINKKITDIR)/drivers) ! InstallLinkKitNonExecFile(confmono.SHsuf,$(LINKKITDIR)) DependSubdirs($(SUBDIRS)) *** ./programs/Xserver/hw/xfree86/mono/USING@@/PUBLIC-LATEST Sat Jul 19 10:39:06 1997 --- xc/programs/Xserver/hw/xfree86/mono/USING Fri Mar 6 16:42:18 1998 *************** *** 23,27 **** and are reasonable only on primary displays. Default is 0xE0000. ! $TOG: USING /main/4 1997/07/19 10:39:08 kaleb $ ! $XFree86: xc/programs/Xserver/hw/xfree86/mono/USING,v 3.1 1996/02/04 09:09:17 dawes Exp $ --- 23,27 ---- and are reasonable only on primary displays. Default is 0xE0000. ! $TOG: USING /main/5 1998/03/06 16:43:55 kaleb $ ! $XFree86: xc/programs/Xserver/hw/xfree86/mono/USING,v 3.2 1996/12/23 06:47:42 dawes Exp $ *** ./programs/Xserver/hw/xfree86/mono/mono/mono.c@@/PUBLIC-LATEST Sat Jul 19 10:41:20 1997 --- xc/programs/Xserver/hw/xfree86/mono/mono/mono.c Fri Mar 6 16:42:21 1998 *************** *** 1,4 **** ! /* $XFree86: xc/programs/Xserver/hw/xfree86/mono/mono/mono.c,v 3.28.2.3 1997/05/11 02:56:21 dawes Exp $ */ /* * MONO: Driver family for interlaced and banked monochrome video adaptors * Pascal Haible 8/93, 3/94, 4/94 haible@IZFM.Uni-Stuttgart.DE --- 1,4 ---- ! /* $XFree86: xc/programs/Xserver/hw/xfree86/mono/mono/mono.c,v 3.28.2.5 1998/03/01 13:58:22 dawes Exp $ */ /* * MONO: Driver family for interlaced and banked monochrome video adaptors * Pascal Haible 8/93, 3/94, 4/94 haible@IZFM.Uni-Stuttgart.DE *************** *** 14,20 **** * * see mono/COPYRIGHT for copyright and disclaimers. */ ! /* $TOG: mono.c /main/17 1997/07/19 10:41:22 kaleb $ */ #include "X.h" --- 14,20 ---- * * see mono/COPYRIGHT for copyright and disclaimers. */ ! /* $TOG: mono.c /main/18 1998/03/06 16:43:59 kaleb $ */ #include "X.h" *************** *** 155,161 **** 0, /* int textClockFreq */ NULL, /* char* DCConfig */ NULL, /* char* DCOptions */ ! 0 /* int MemClk */ #ifdef XFreeXDGA ,0, /* int directMode */ NULL, /* Set Vid Page */ --- 155,162 ---- 0, /* int textClockFreq */ NULL, /* char* DCConfig */ NULL, /* char* DCOptions */ ! 0, /* int MemClk */ ! 0 /* int LCDClk */ #ifdef XFreeXDGA ,0, /* int directMode */ NULL, /* Set Vid Page */ *************** *** 521,526 **** --- 522,530 ---- PixmapPtr pspix; /* Pointer to the pixmap of the saved screen */ ScreenPtr pScreen = savepScreen; /* This is the 'old' Screen: real screen on leave, dummy on enter */ + + if (monoEnterLeaveFunc == NULL) + return; /* Set up pointer to the saved pixmap (pspix) only if not resetting and not exiting */ *** ./programs/Xserver/hw/xfree86/os-support/bsd/bsd_init.c@@/PUBLIC-LATEST Sat Jul 19 10:42:29 1997 --- xc/programs/Xserver/hw/xfree86/os-support/bsd/bsd_init.c Fri Mar 6 16:42:35 1998 *************** *** 1,4 **** ! /* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/bsd/bsd_init.c,v 3.8 1996/12/23 06:49:36 dawes Exp $ */ /* * Copyright 1992 by Rich Murphey <Rich@Rice.edu> * Copyright 1993 by David Wexelblat <dwex@goblin.org> --- 1,4 ---- ! /* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/bsd/bsd_init.c,v 3.8.2.1 1998/02/06 22:36:49 hohndel Exp $ */ /* * Copyright 1992 by Rich Murphey <Rich@Rice.edu> * Copyright 1993 by David Wexelblat <dwex@goblin.org> *************** *** 23,29 **** * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ ! /* $TOG: bsd_init.c /main/9 1997/07/19 10:42:31 kaleb $ */ #include "X.h" #include "Xmd.h" --- 23,29 ---- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ ! /* $TOG: bsd_init.c /main/10 1998/03/06 16:44:13 kaleb $ */ #include "X.h" #include "Xmd.h" *************** *** 187,193 **** /* check if we are run with euid==0 */ if (geteuid() != 0) { ! FatalError("xf86OpenConsole: Server must be suid root\n"); } if (!KeepTty) --- 187,196 ---- /* check if we are run with euid==0 */ if (geteuid() != 0) { ! FatalError("xf86OpenConsole: Server must be running with root " ! "permissions\n" ! "You should be using Xwrapper to start the server or xdm.\n" ! "We strongly advise against making the server SUID root!\n"); } if (!KeepTty) *** ./programs/Xserver/hw/xfree86/os-support/bsd/bsd_video.c@@/PUBLIC-LATEST Sat Jul 19 10:42:41 1997 --- xc/programs/Xserver/hw/xfree86/os-support/bsd/bsd_video.c Fri Mar 6 16:42:40 1998 *************** *** 1,4 **** ! /* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/bsd/bsd_video.c,v 3.14.2.1 1997/05/03 09:47:11 dawes Exp $ */ /* * Copyright 1992 by Rich Murphey <Rich@Rice.edu> * Copyright 1993 by David Wexelblat <dwex@goblin.org> --- 1,4 ---- ! /* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/bsd/bsd_video.c,v 3.14.2.2 1998/02/15 16:09:31 hohndel Exp $ */ /* * Copyright 1992 by Rich Murphey <Rich@Rice.edu> * Copyright 1993 by David Wexelblat <dwex@goblin.org> *************** *** 23,29 **** * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ ! /* $TOG: bsd_video.c /main/11 1997/07/19 10:42:44 kaleb $ */ #include "X.h" #include "input.h" --- 23,29 ---- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ ! /* $TOG: bsd_video.c /main/12 1998/03/06 16:44:18 kaleb $ */ #include "X.h" #include "input.h" *************** *** 35,41 **** #include "xf86_Config.h" #if defined(__NetBSD__) && !defined(MAP_FILE) ! #define MAP_FILE 0 #endif /***************************************************************************/ --- 35,43 ---- #include "xf86_Config.h" #if defined(__NetBSD__) && !defined(MAP_FILE) ! #define MAP_FLAGS MAP_SHARED ! #else ! #define MAP_FLAGS (MAP_FILE | MAP_SHARED) #endif /***************************************************************************/ *************** *** 42,63 **** /* Video Memory Mapping section */ /***************************************************************************/ - #ifndef __mips__ - #define _386BSD_MMAP_BUG - #endif - #ifdef _386BSD_MMAP_BUG - /* - * Bug prevents multiple mappings, so just map a fixed region between 0xA0000 - * and 0xBFFFF, and return a pointer to the requested Base. - */ - static int MemMapped = FALSE; - static pointer MappedPointer = NULL; - static int MapCount = 0; - #define MAP_BASE 0xA0000 - #define MAP_SIZE 0x20000 - #endif - static Bool devMemChecked = FALSE; static Bool useDevMem = FALSE; static int devMemFd = -1; --- 44,50 ---- *************** *** 78,84 **** * Check if /dev/mem can be mmap'd. If it can't print a warning when * "warn" is TRUE. */ ! static void checkDevMem(warn) Bool warn; { int fd; --- 65,72 ---- * Check if /dev/mem can be mmap'd. If it can't print a warning when * "warn" is TRUE. */ ! static void ! checkDevMem(warn) Bool warn; { int fd; *************** *** 89,95 **** { /* Try to map a page at the VGA address */ base = (pointer)mmap((caddr_t)0, 4096, PROT_READ|PROT_WRITE, ! MAP_FILE, fd, (off_t)0xA0000); if (base != (pointer)-1) { --- 77,83 ---- { /* Try to map a page at the VGA address */ base = (pointer)mmap((caddr_t)0, 4096, PROT_READ|PROT_WRITE, ! MAP_FLAGS, fd, (off_t)0xA0000); if (base != (pointer)-1) { *************** *** 123,129 **** { /* Try to map a page at the VGA address */ base = (pointer)mmap((caddr_t)0, 4096, PROT_READ|PROT_WRITE, ! MAP_FILE, fd, (off_t)0xA0000); if (base != (pointer)-1) { --- 111,117 ---- { /* Try to map a page at the VGA address */ base = (pointer)mmap((caddr_t)0, 4096, PROT_READ|PROT_WRITE, ! MAP_FLAGS, fd, (off_t)0xA0000); if (base != (pointer)-1) { *************** *** 160,166 **** } ! pointer xf86MapVidMem(ScreenNum, Region, Base, Size) int ScreenNum; int Region; pointer Base; --- 148,155 ---- } ! pointer ! xf86MapVidMem(ScreenNum, Region, Base, Size) int ScreenNum; int Region; pointer Base; *************** *** 179,185 **** DEV_MEM, strerror(errno)); } base = (pointer)mmap((caddr_t)0, Size, PROT_READ|PROT_WRITE, ! MAP_FILE, devMemFd, (off_t)(unsigned long) Base); if (base == (pointer)-1) { --- 168,174 ---- DEV_MEM, strerror(errno)); } base = (pointer)mmap((caddr_t)0, Size, PROT_READ|PROT_WRITE, ! MAP_FLAGS, devMemFd, (off_t)(unsigned long) Base); if (base == (pointer)-1) { *************** *** 195,229 **** } /* else, mmap /dev/vga */ - #ifdef _386BSD_MMAP_BUG - if ((unsigned long)Base < MAP_BASE || - (unsigned long)Base >= MAP_BASE + MAP_SIZE) - { - FatalError("%s: Address 0x%x outside allowable range\n", - "xf86MapVidMem", Base); - } - if ((unsigned long)Base + Size > MAP_BASE + MAP_SIZE) - { - FatalError("%s: Size 0x%x too large (Base = 0x%x)\n", - "xf86MapVidMem", Size, Base); - } - if (!MemMapped) - { - base = (pointer)mmap(0, MAP_SIZE, PROT_READ|PROT_WRITE, - MAP_FILE, xf86Info.screenFd, 0); - if (base == (pointer)-1) - { - FatalError("xf86MapVidMem: Could not mmap /dev/vga (%s)\n", - strerror(errno)); - } - MappedPointer = base; - MemMapped = TRUE; - } - MapCount++; - return((pointer)((unsigned long)MappedPointer + - ((unsigned long)Base - MAP_BASE))); - - #else #ifndef PC98 if ((unsigned long)Base < 0xA0000 || (unsigned long)Base >= 0xC0000) #else --- 184,189 ---- *************** *** 233,239 **** FatalError("%s: Address 0x%x outside allowable range\n", "xf86MapVidMem", Base); } ! base = (pointer)mmap(0, Size, PROT_READ|PROT_WRITE, MAP_FILE, xf86Info.screenFd, #ifdef __mips__ (unsigned long)Base); --- 193,199 ---- FatalError("%s: Address 0x%x outside allowable range\n", "xf86MapVidMem", Base); } ! base = (pointer)mmap(0, Size, PROT_READ|PROT_WRITE, MAP_FLAGS, xf86Info.screenFd, #ifdef __mips__ (unsigned long)Base); *************** *** 246,260 **** strerror(errno)); } #if 0 ! xf86memMaps[ScreenNum].offset = (int) Base; ! xf86memMaps[ScreenNum].memSize = Size; ! return(base); #endif - #endif } #if 0 ! void xf86GetVidMemData(ScreenNum, Base, Size) int ScreenNum; int *Base; int *Size; --- 206,220 ---- strerror(errno)); } #if 0 ! xf86memMaps[ScreenNum].offset = (int) Base; ! xf86memMaps[ScreenNum].memSize = Size; ! return(base); #endif } #if 0 ! void ! xf86GetVidMemData(ScreenNum, Base, Size) int ScreenNum; int *Base; int *Size; *************** *** 263,270 **** *Size = xf86memMaps[ScreenNum].memSize; } #endif ! ! void xf86UnMapVidMem(ScreenNum, Region, Base, Size) int ScreenNum; int Region; pointer Base; --- 223,231 ---- *Size = xf86memMaps[ScreenNum].memSize; } #endif ! ! void ! xf86UnMapVidMem(ScreenNum, Region, Base, Size) int ScreenNum; int Region; pointer Base; *************** *** 276,296 **** return; } - #ifdef _386BSD_MMAP_BUG - if (MapCount == 0 || MappedPointer == NULL) - return; - - if (--MapCount == 0) - { - munmap((caddr_t)MappedPointer, MAP_SIZE); - MemMapped = FALSE; - } - #else munmap((caddr_t)Base, Size); - #endif } ! Bool xf86LinearVidMem() { /* * Call checkDevMem even if already called by xf86MapVidMem() so that --- 237,247 ---- return; } munmap((caddr_t)Base, Size); } ! Bool ! xf86LinearVidMem() { /* * Call checkDevMem even if already called by xf86MapVidMem() so that *************** *** 370,376 **** if (ScreenEnabled[i]) return; ! i386_iopl(TRUE); ExtendedEnabled = FALSE; return; --- 321,327 ---- if (ScreenEnabled[i]) return; ! i386_iopl(FALSE); ExtendedEnabled = FALSE; return; *************** *** 432,438 **** if ((fd = open("/dev/ttyC0", O_RDWR)) >= 0) { /* Try to map a page at the pccons I/O space */ base = (pointer)mmap((caddr_t)0, 65536, PROT_READ|PROT_WRITE, ! MAP_FILE, fd, (off_t)0x0000); if (base != (pointer)-1) { IOPortBase = base; --- 383,389 ---- if ((fd = open("/dev/ttyC0", O_RDWR)) >= 0) { /* Try to map a page at the pccons I/O space */ base = (pointer)mmap((caddr_t)0, 65536, PROT_READ|PROT_WRITE, ! MAP_FLAGS, fd, (off_t)0x0000); if (base != (pointer)-1) { IOPortBase = base; *************** *** 473,479 **** /* Interrupt Handling section */ /***************************************************************************/ ! Bool xf86DisableInterrupts() { #if !defined(__mips__) --- 424,431 ---- /* Interrupt Handling section */ /***************************************************************************/ ! Bool ! xf86DisableInterrupts() { #if !defined(__mips__) *************** *** 487,493 **** return(TRUE); } ! void xf86EnableInterrupts() { #if !defined(__mips__) --- 439,446 ---- return(TRUE); } ! void ! xf86EnableInterrupts() { #if !defined(__mips__) *** ./programs/Xserver/hw/xfree86/os-support/bsdi/bsdi_init.c@@/PUBLIC-LATEST Sat Jul 19 10:42:55 1997 --- xc/programs/Xserver/hw/xfree86/os-support/bsdi/bsdi_init.c Fri Mar 6 16:42:44 1998 *************** *** 1,4 **** ! /* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/bsdi/bsdi_init.c,v 3.5 1996/12/23 06:49:50 dawes Exp $ */ /* * Copyright 1992 by Rich Murphey <Rich@Rice.edu> * Copyright 1993 by David Wexelblat <dwex@goblin.org> --- 1,4 ---- ! /* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/bsdi/bsdi_init.c,v 3.5.2.1 1998/02/06 22:36:50 hohndel Exp $ */ /* * Copyright 1992 by Rich Murphey <Rich@Rice.edu> * Copyright 1993 by David Wexelblat <dwex@goblin.org> *************** *** 23,29 **** * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ ! /* $TOG: bsdi_init.c /main/6 1997/07/19 10:42:57 kaleb $ */ #include "X.h" #include "Xmd.h" --- 23,29 ---- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ ! /* $TOG: bsdi_init.c /main/7 1998/03/06 16:44:22 kaleb $ */ #include "X.h" #include "Xmd.h" *************** *** 61,67 **** /* check if we're run with euid==0 */ if (geteuid() != 0) { ! FatalError("xf86OpenConsole: Server must be suid root\n"); } if (!KeepTty) --- 61,70 ---- /* check if we're run with euid==0 */ if (geteuid() != 0) { ! FatalError("xf86OpenConsole: Server must be running with root " ! "permissions\n" ! "You should be using Xwrapper to start the server or xdm.\n" ! "We strongly advise against making the server SUID root!\n"); } if (!KeepTty) *** ./programs/Xserver/hw/xfree86/os-support/linux/lnx_init.c@@/PUBLIC-LATEST Sat Jul 19 10:43:23 1997 --- xc/programs/Xserver/hw/xfree86/os-support/linux/lnx_init.c Fri Mar 6 16:42:48 1998 *************** *** 1,4 **** ! /* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/linux/lnx_init.c,v 3.7.2.2 1997/05/03 13:33:37 dawes Exp $ */ /* * Copyright 1992 by Orest Zborowski <obz@Kodak.com> * Copyright 1993 by David Wexelblat <dwex@goblin.org> --- 1,4 ---- ! /* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/linux/lnx_init.c,v 3.7.2.3 1998/02/06 22:36:51 hohndel Exp $ */ /* * Copyright 1992 by Orest Zborowski <obz@Kodak.com> * Copyright 1993 by David Wexelblat <dwex@goblin.org> *************** *** 23,29 **** * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ ! /* $TOG: lnx_init.c /main/8 1997/07/19 10:43:25 kaleb $ */ #include "X.h" #include "Xmd.h" --- 23,29 ---- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ ! /* $TOG: lnx_init.c /main/9 1998/03/06 16:44:26 kaleb $ */ #include "X.h" #include "Xmd.h" *************** *** 68,74 **** /* check if we're run with euid==0 */ if (geteuid() != 0) { ! FatalError("xf86OpenConsole: Server must be suid root\n"); } /* --- 68,77 ---- /* check if we're run with euid==0 */ if (geteuid() != 0) { ! FatalError("xf86OpenConsole: Server must be running with root " ! "permissions\n" ! "You should be using Xwrapper to start the server or xdm.\n" ! "We strongly advise against making the server SUID root!\n"); } /* *** ./programs/Xserver/hw/xfree86/os-support/lynxos/lynx_init.c@@/PUBLIC-LATEST Mon Sep 4 19:40:22 1995 --- xc/programs/Xserver/hw/xfree86/os-support/lynxos/lynx_init.c Fri Mar 6 16:42:52 1998 *************** *** 22,28 **** */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/lynxos/lynx_init.c,v 3.1 1995/06/24 10:29:21 dawes Exp $ */ #include "X.h" #include "Xmd.h" --- 22,28 ---- */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/lynxos/lynx_init.c,v 3.1.6.1 1998/02/06 22:36:51 hohndel Exp $ */ #include "X.h" #include "Xmd.h" *************** *** 48,54 **** /* check if we're run with euid==0 */ if (geteuid() != 0) { ! FatalError("xf86OpenConsole: Server must be suid root\n"); } /* --- 48,57 ---- /* check if we're run with euid==0 */ if (geteuid() != 0) { ! FatalError("xf86OpenConsole: Server must be running with root " ! "permissions\n" ! "You should be using Xwrapper to start the server or xdm.\n" ! "We strongly advise against making the server SUID root!\n"); } /* *** ./programs/Xserver/hw/xfree86/os-support/minix/mnx_init.c@@/PUBLIC-LATEST Sat Jul 19 10:44:47 1997 --- xc/programs/Xserver/hw/xfree86/os-support/minix/mnx_init.c Fri Mar 6 16:42:56 1998 *************** *** 1,4 **** ! /* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/minix/mnx_init.c,v 3.6 1996/12/23 06:50:18 dawes Exp $ */ /* * Copyright 1993 by Vrije Universiteit, The Netherlands * Copyright 1993 by David Wexelblat <dwex@goblin.org> --- 1,4 ---- ! /* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/minix/mnx_init.c,v 3.6.2.1 1998/02/06 22:36:52 hohndel Exp $ */ /* * Copyright 1993 by Vrije Universiteit, The Netherlands * Copyright 1993 by David Wexelblat <dwex@goblin.org> *************** *** 24,30 **** * PERFORMANCE OF THIS SOFTWARE. * */ ! /* $TOG: mnx_init.c /main/6 1997/07/19 10:44:49 kaleb $ */ #include "X.h" #include "Xmd.h" --- 24,30 ---- * PERFORMANCE OF THIS SOFTWARE. * */ ! /* $TOG: mnx_init.c /main/7 1998/03/06 16:44:34 kaleb $ */ #include "X.h" #include "Xmd.h" *************** *** 57,63 **** /* check if we're run with euid==0 */ if (setuid(0) != 0) { ! FatalError("xf86OpenConsole: Server must be suid root\n"); } setuid(real_uid); --- 57,66 ---- /* check if we're run with euid==0 */ if (setuid(0) != 0) { ! FatalError("xf86OpenConsole: Server must be running with root " ! "permissions\n" ! "You should be using Xwrapper to start the server or xdm.\n" ! "We strongly advise against making the server SUID root!\n"); } setuid(real_uid); *** ./programs/Xserver/hw/xfree86/os-support/sco/sco_init.c@@/PUBLIC-LATEST Sat Jul 19 10:46:59 1997 --- xc/programs/Xserver/hw/xfree86/os-support/sco/sco_init.c Fri Mar 6 16:43:02 1998 *************** *** 1,4 **** ! /* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/sco/sco_init.c,v 3.10 1996/12/23 06:50:48 dawes Exp $ */ /* * Copyright 1993 by David McCullough <davidm@stallion.oz.au> * Copyright 1993 by David Wexelblat <dwex@goblin.org> --- 1,4 ---- ! /* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/sco/sco_init.c,v 3.10.2.1 1998/02/06 22:36:53 hohndel Exp $ */ /* * Copyright 1993 by David McCullough <davidm@stallion.oz.au> * Copyright 1993 by David Wexelblat <dwex@goblin.org> *************** *** 23,29 **** * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ ! /* $TOG: sco_init.c /main/8 1997/07/19 10:47:01 kaleb $ */ #include "X.h" #include "Xmd.h" --- 23,29 ---- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ ! /* $TOG: sco_init.c /main/9 1998/03/06 16:44:40 kaleb $ */ #include "X.h" #include "Xmd.h" *************** *** 58,64 **** /* check if we're run with euid==0 */ if (geteuid() != 0) { ! FatalError("xf86OpenConsole: Server must be suid root\n"); } /* --- 58,67 ---- /* check if we're run with euid==0 */ if (geteuid() != 0) { ! FatalError("xf86OpenConsole: Server must be running with root " ! "permissions\n" ! "You should be using Xwrapper to start the server or xdm.\n" ! "We strongly advise against making the server SUID root!\n"); } /* *** ./programs/Xserver/hw/xfree86/os-support/shared/posix_tty.c@@/PUBLIC-LATEST Sat Jul 19 10:48:07 1997 --- xc/programs/Xserver/hw/xfree86/os-support/shared/posix_tty.c Fri Mar 6 16:43:06 1998 *************** *** 1,4 **** ! /* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/shared/posix_tty.c,v 3.8 1996/12/23 06:51:01 dawes Exp $ */ /* * Copyright 1993 by David Dawes <dawes@physics.su.oz.au> * --- 1,4 ---- ! /* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/shared/posix_tty.c,v 3.8.2.1 1998/02/07 14:27:25 dawes Exp $ */ /* * Copyright 1993 by David Dawes <dawes@physics.su.oz.au> * *************** *** 22,28 **** * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ ! /* $TOG: posix_tty.c /main/8 1997/07/19 10:48:09 kaleb $ */ #define NEED_EVENTS #include "X.h" --- 22,28 ---- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ ! /* $TOG: posix_tty.c /main/9 1998/03/06 16:44:44 kaleb $ */ #define NEED_EVENTS #include "X.h" *************** *** 163,167 **** --- 163,174 ---- xf86FatalError("Unable to set status of mouse fd (%s)\n", strerror(errno)); } + } + + int + xf86FlushInput(fd) + int fd; + { + return tcflush(fd, TCIFLUSH); } *** ./programs/Xserver/hw/xfree86/os-support/shared/sysv_tty.c@@/PUBLIC-LATEST Sat Jul 19 10:48:36 1997 --- xc/programs/Xserver/hw/xfree86/os-support/shared/sysv_tty.c Fri Mar 6 16:43:10 1998 *************** *** 1,4 **** ! /* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/shared/sysv_tty.c,v 3.8 1996/12/23 06:51:08 dawes Exp $ */ /* * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany * Copyright 1993 by David Dawes <dawes@physics.su.oz.au> --- 1,4 ---- ! /* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/shared/sysv_tty.c,v 3.8.2.1 1998/02/07 14:27:25 dawes Exp $ */ /* * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany * Copyright 1993 by David Dawes <dawes@physics.su.oz.au> *************** *** 23,29 **** * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ ! /* $TOG: sysv_tty.c /main/8 1997/07/19 10:48:38 kaleb $ */ #define NEED_EVENTS #include "X.h" --- 23,29 ---- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ ! /* $TOG: sysv_tty.c /main/9 1998/03/06 16:44:48 kaleb $ */ #define NEED_EVENTS #include "X.h" *************** *** 161,165 **** --- 161,172 ---- #ifdef TCMOUSE ioctl(mouse->mseFd, TCMOUSE, 1); #endif + } + + int + xf86FlushInput(fd) + int fd; + { + return ioctl(fd, TCFLSH, 0); } *** ./programs/Xserver/hw/xfree86/os-support/solx86/solx86_init.c@@/PUBLIC-LATEST Sat Jul 19 10:48:47 1997 --- xc/programs/Xserver/hw/xfree86/os-support/solx86/solx86_init.c Fri Mar 6 16:43:14 1998 *************** *** 1,4 **** ! /* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/solx86/solx86_init.c,v 3.4 1996/12/23 06:51:17 dawes Exp $ */ /* * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany * Copyright 1993 by David Wexelblat <dwex@goblin.org> --- 1,4 ---- ! /* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/solx86/solx86_init.c,v 3.4.2.1 1998/02/06 22:36:53 hohndel Exp $ */ /* * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany * Copyright 1993 by David Wexelblat <dwex@goblin.org> *************** *** 23,29 **** * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ ! /* $TOG: solx86_init.c /main/5 1997/07/19 10:48:49 kaleb $ */ #include <signal.h> #include <sys/time.h> --- 23,29 ---- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ ! /* $TOG: solx86_init.c /main/6 1998/03/06 16:44:52 kaleb $ */ #include <signal.h> #include <sys/time.h> *************** *** 80,86 **** /* check if we're run with euid==0 */ if (geteuid() != 0) { ! FatalError("xf86OpenConsole: Server must be suid root\n"); } /* Protect page 0 to help find NULL dereferencing */ --- 80,89 ---- /* check if we're run with euid==0 */ if (geteuid() != 0) { ! FatalError("xf86OpenConsole: Server must be running with root " ! "permissions\n" ! "You should be using Xwrapper to start the server or xdm.\n" ! "We strongly advise against making the server SUID root!\n"); } /* Protect page 0 to help find NULL dereferencing */ *** ./programs/Xserver/hw/xfree86/os-support/sysv/sysv_init.c@@/PUBLIC-LATEST Sat Jul 19 10:49:21 1997 --- xc/programs/Xserver/hw/xfree86/os-support/sysv/sysv_init.c Fri Mar 6 16:43:18 1998 *************** *** 1,4 **** ! /* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/sysv/sysv_init.c,v 3.4 1996/12/23 06:51:25 dawes Exp $ */ /* * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany * Copyright 1993 by David Wexelblat <dwex@goblin.org> --- 1,4 ---- ! /* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/sysv/sysv_init.c,v 3.4.2.1 1998/02/06 22:36:54 hohndel Exp $ */ /* * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany * Copyright 1993 by David Wexelblat <dwex@goblin.org> *************** *** 23,29 **** * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ ! /* $TOG: sysv_init.c /main/5 1997/07/19 10:49:23 kaleb $ */ #include "X.h" #include "Xmd.h" --- 23,29 ---- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ ! /* $TOG: sysv_init.c /main/6 1998/03/06 16:44:56 kaleb $ */ #include "X.h" #include "Xmd.h" *************** *** 59,65 **** /* check if we're run with euid==0 */ if (geteuid() != 0) { ! FatalError("xf86OpenConsole: Server must be suid root\n"); } #ifdef SVR4 --- 59,68 ---- /* check if we're run with euid==0 */ if (geteuid() != 0) { ! FatalError("xf86OpenConsole: Server must be running with root " ! "permissions\n" ! "You should be using Xwrapper to start the server or xdm.\n" ! "We strongly advise against making the server SUID root!\n"); } #ifdef SVR4 *** ./programs/Xserver/hw/xfree86/os-support/xf86_OSlib.h@@/PUBLIC-LATEST Sun Aug 10 13:04:34 1997 --- xc/programs/Xserver/hw/xfree86/os-support/xf86_OSlib.h Fri Mar 6 16:42:26 1998 *************** *** 1,4 **** ! /* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/xf86_OSlib.h,v 3.36.2.1 1997/07/19 04:59:30 dawes Exp $ */ /* * Copyright 1990, 1991 by Thomas Roell, Dinkelscherben, Germany * Copyright 1992 by David Dawes <dawes@XFree86.org> --- 1,4 ---- ! /* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/xf86_OSlib.h,v 3.36.2.5 1998/02/15 16:09:30 hohndel Exp $ */ /* * Copyright 1990, 1991 by Thomas Roell, Dinkelscherben, Germany * Copyright 1992 by David Dawes <dawes@XFree86.org> *************** *** 31,37 **** * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ ! /* $TOG: xf86_OSlib.h /main/24 1997/08/10 13:03:09 kaleb $ */ #ifndef _XF86_OSLIB_H #define _XF86_OSLIB_H --- 31,37 ---- * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ ! /* $TOG: xf86_OSlib.h /main/25 1998/03/06 16:44:04 kaleb $ */ #ifndef _XF86_OSLIB_H #define _XF86_OSLIB_H *************** *** 55,64 **** # ifdef SCO325 # define _SVID3 # endif - # if defined(sun) && defined(i386) && defined(SVR4) - # /* Fix for Solaris ANSI compilation */ - # define __EXTENSIONS__ - # endif # include <sys/ioctl.h> # include <signal.h> # include <termio.h> --- 55,60 ---- *************** *** 245,250 **** --- 241,249 ---- #ifdef CSRG_BASED # include <sys/ioctl.h> + # if defined(__OpenBSD__) && defined(_status) + # undef _status + # endif # include <signal.h> # include <termios.h> *************** *** 302,307 **** --- 301,310 ---- }; # endif /* PCVT_SUPPORT && SYSCONS_SUPPORT */ # endif /* PCVT_SUPPORT */ + # if defined(__FreeBSD__) + # undef MOUSE_GETINFO + # include <machine/mouse.h> + # endif /* Include these definitions in case ioctl_pc.h didn't get included */ # ifndef CONSOLE_X_MODE_ON # define CONSOLE_X_MODE_ON _IO('t',121) *** ./programs/Xserver/hw/xfree86/reconfig/reconfig.man@@/PUBLIC-LATEST Tue Nov 4 21:18:01 1997 --- xc/programs/Xserver/hw/xfree86/reconfig/reconfig.man Fri Mar 6 16:43:22 1998 *************** *** 1,5 **** .\" $XFree86: xc/programs/Xserver/hw/xfree86/reconfig/reconfig.man,v 3.6 1996/12/23 06:51:44 dawes Exp $ ! .TH reconfig 1 "Release 6.4 (XFree86 3.3.1)" "X Version 11" .SH NAME reconfig \- convert old Xconfig to new XF86Config .SH SYNOPSIS --- 1,5 ---- .\" $XFree86: xc/programs/Xserver/hw/xfree86/reconfig/reconfig.man,v 3.6 1996/12/23 06:51:44 dawes Exp $ ! .TH reconfig 1 "Version 3.2" "XFree86" .SH NAME reconfig \- convert old Xconfig to new XF86Config .SH SYNOPSIS *************** *** 19,22 **** Gertjan Akkerman. .SH BUGS Comment lines are stripped out when converting. ! .\" $TOG: reconfig.man /main/10 1997/11/04 21:20:56 kaleb $ --- 19,22 ---- Gertjan Akkerman. .SH BUGS Comment lines are stripped out when converting. ! .\" $TOG: reconfig.man /main/11 1998/03/06 16:45:00 kaleb $ *** ./programs/Xserver/hw/xfree86/vga16/drivers/ati/Imakefile@@/PUBLIC-LATEST Sat Jul 19 10:51:10 1997 --- xc/programs/Xserver/hw/xfree86/vga16/drivers/ati/Imakefile Fri Mar 6 16:43:30 1998 *************** *** 1,36 **** ! XCOMM $TOG: Imakefile /main/8 1997/07/19 10:51:12 kaleb $ - XCOMM $XFree86: xc/programs/Xserver/hw/xfree86/vga16/drivers/ati/Imakefile,v 3.7 1996/12/23 06:51:58 dawes Exp $ #include <Server.tmpl> ! SRCS = ati_driver.c ati_bank.s ! OBJS = ati_driver.o ati_bank.o #if XF86LinkKit INCLUDES = -I. -I../../../include -I../../../include/X11 -I../.. #else INCLUDES = -I. -I$(XF86COMSRC) -I$(XF86HWSRC) -I$(XF86OSSRC) -I$(XF86SRC) \ ! -I../../../vga256/vga -I$(SERVERSRC)/include -I$(XINCLUDESRC) #endif ! DEFINES = -DXF86VGA16 #if MakeHasPosixVariableSubstitutions SubdirLibraryRule($(OBJS)) #endif NormalLibraryObjectRule() ! NormalRelocatableTarget(ati_drv, $(OBJS)) ! LinkSourceFile(regati.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(ati_driver.c,$(VGADRIVERSRC)/ati) ! ObjectFromSpecialAsmSource(ati_bank,$(VGADRIVERSRC)/ati/bank,NullParameter) InstallLinkKitNonExecFile(Imakefile,$(LINKKITDIR)/drivers/vga16/ati) DependTarget() --- 1,132 ---- ! XCOMM $TOG: Imakefile /main/9 1998/03/06 16:45:08 kaleb $ + XCOMM $XFree86: xc/programs/Xserver/hw/xfree86/vga16/drivers/ati/Imakefile,v 3.7.2.2 1998/02/22 01:28:25 robin Exp $ + XCOMM + XCOMM Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + XCOMM + XCOMM Permission to use, copy, modify, distribute, and sell this software and + XCOMM its documentation for any purpose is hereby granted without fee, provided + XCOMM that the above copyright notice appear in all copies and that both that + XCOMM copyright notice and this permission notice appear in supporting + XCOMM documentation, and that the name of Marc Aurele La France not be used in + XCOMM advertising or publicity pertaining to distribution of the software + XCOMM without specific, written prior permission. Marc Aurele La France makes + XCOMM no representations about the suitability of this software for any + XCOMM purpose. It is provided "as-is" without express or implied warranty. + XCOMM + XCOMM MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS + XCOMM SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND + XCOMM FITNESS. IN NO EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY + XCOMM SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER + XCOMM RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF + XCOMM CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + XCOMM CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + XCOMM #include <Server.tmpl> ! #ifdef ATIDriverCCOptions ! CCOPTIONS = ATIDriverCCOptions ! #endif ! SRCS = ati.c atiadapter.c atiadjust.c atibank.c atibanks.s atibus.c atichip.c \ ! aticlock.c aticmap.c aticonsole.c aticrtc.c atidac.c atidsp.c \ ! atifbinit.c atigetmode.c atiident.c atiio.c atimach64.c atiprint.c \ ! atiprobe.c atireset.c atiscrinit.c atiutil.c ativalid.c ativga.c \ ! atividmem.c atiwonder.c + OBJS = ati.o atiadapter.o atiadjust.o atibank.o atibanks.o atibus.o atichip.o \ + aticlock.o aticmap.o aticonsole.o aticrtc.o atidac.o atidsp.o \ + atifbinit.o atigetmode.o atiident.o atiio.o atimach64.o atiprint.o \ + atiprobe.o atireset.o atiscrinit.o atiutil.o ativalid.o ativga.o \ + atividmem.o atiwonder.o + #if XF86LinkKit INCLUDES = -I. -I../../../include -I../../../include/X11 -I../.. #else INCLUDES = -I. -I$(XF86COMSRC) -I$(XF86HWSRC) -I$(XF86OSSRC) -I$(XF86SRC) \ ! -I$(XF86SRC)/vga256/vga -I$(SERVERSRC)/include -I$(SERVERSRC)/cfb \ ! -I$(SERVERSRC)/mfb -I$(SERVERSRC)/mi -I$(XINCLUDESRC) #endif ! #if XF86Vga2Banked ! MONODEFS = -DBANKEDMONOVGA ! #endif + DEFINES = -DPSZ=8 -DXF86VGA16 $(MONODEFS) + #if MakeHasPosixVariableSubstitutions SubdirLibraryRule($(OBJS)) #endif NormalLibraryObjectRule() + NormalAsmObjectRule() ! NormalRelocatableTarget(ati_drv,$(OBJS)) ! LinkSourceFile(ati.c,$(VGADRIVERSRC)/ati) ! LinkSourceFile(ati.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atiadapter.c,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atiadapter.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atiadjust.c,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atiadjust.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atibank.c,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atibank.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atibanks.s,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atibus.c,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atibus.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atichip.c,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atichip.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(aticlock.c,$(VGADRIVERSRC)/ati) ! LinkSourceFile(aticlock.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(aticmap.c,$(VGADRIVERSRC)/ati) ! LinkSourceFile(aticmap.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(aticonsole.c,$(VGADRIVERSRC)/ati) ! LinkSourceFile(aticonsole.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(aticrtc.c,$(VGADRIVERSRC)/ati) ! LinkSourceFile(aticrtc.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atidac.c,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atidac.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atidepth.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atidsp.c,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atidsp.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atifbinit.c,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atifbinit.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atigetmode.c,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atigetmode.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atiident.c,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atiident.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atiio.c,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atiio.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atimach64.c,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atimach64.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atimono.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atiprint.c,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atiprint.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atiprobe.c,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atiprobe.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atiproto.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atiregs.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atireset.c,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atireset.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atiscrinit.c,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atiscrinit.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atiutil.c,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atiutil.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(ativalid.c,$(VGADRIVERSRC)/ati) ! LinkSourceFile(ativalid.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(ativersion.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(ativga.c,$(VGADRIVERSRC)/ati) ! LinkSourceFile(ativga.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atividmem.c,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atividmem.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atiwonder.c,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atiwonder.h,$(VGADRIVERSRC)/ati) InstallLinkKitNonExecFile(Imakefile,$(LINKKITDIR)/drivers/vga16/ati) + #ifndef OS2Architecture DependTarget() + #endif *** ./programs/Xserver/hw/xfree86/vga16/drivers/et4000/Imakefile@@/PUBLIC-LATEST Sat Jul 19 10:51:31 1997 --- xc/programs/Xserver/hw/xfree86/vga16/drivers/et4000/Imakefile Fri Mar 6 16:43:34 1998 *************** *** 1,16 **** ! XCOMM $TOG: Imakefile /main/12 1997/07/19 10:51:33 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree86/vga16/drivers/et4000/Imakefile,v 3.7.2.1 1997/05/03 09:47:20 dawes Exp $ #include <Server.tmpl> ! SRCS = et4_driver.c et4_bank.s tseng_ramdac.c tseng_clock.c ! OBJS = et4_driver.o et4_bank.o tseng_ramdac.o tseng_clock.o #if XF86LinkKit INCLUDES = -I. -I../../../include -I../../../include/X11 -I../.. --- 1,16 ---- ! XCOMM $TOG: Imakefile /main/13 1998/03/06 16:45:12 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree86/vga16/drivers/et4000/Imakefile,v 3.7.2.2 1998/02/01 16:04:57 robin Exp $ #include <Server.tmpl> ! SRCS = et4_driver.c et4_bank.s tseng_ramdac.c tseng_clock.c tseng_dpms.c ! OBJS = et4_driver.o et4_bank.o tseng_ramdac.o tseng_clock.o tseng_dpms.o #if XF86LinkKit INCLUDES = -I. -I../../../include -I../../../include/X11 -I../.. *************** *** 31,36 **** --- 31,37 ---- LinkSourceFile(et4_driver.c,$(VGADRIVERSRC)/et4000) LinkSourceFile(tseng_ramdac.c,$(VGADRIVERSRC)/et4000) LinkSourceFile(tseng_clock.c,$(VGADRIVERSRC)/et4000) + LinkSourceFile(tseng_dpms.c,$(VGADRIVERSRC)/et4000) LinkSourceFile(tseng.h,$(VGADRIVERSRC)/et4000) ObjectFromSpecialAsmSource(et4_bank,$(VGADRIVERSRC)/et4000/bank,NullParameter) *** ./programs/Xserver/hw/xfree86/vga16/ibm/ppcIO.c@@/PUBLIC-LATEST Tue Feb 10 17:30:24 1998 --- xc/programs/Xserver/hw/xfree86/vga16/ibm/ppcIO.c Fri Mar 6 16:43:38 1998 *************** *** 42,48 **** SOFTWARE. */ ! /* $TOG: ppcIO.c /main/10 1998/02/10 17:30:42 kaleb $ */ #include "X.h" #include "resource.h" --- 42,48 ---- SOFTWARE. */ ! /* $TOG: ppcIO.c /main/11 1998/03/06 16:45:15 kaleb $ */ #include "X.h" #include "resource.h" *************** *** 271,277 **** if (!mfbAllocatePrivates(pScreen, (int*)NULL, (int*)NULL)) return ; ! miScreenInit(pScreen, pbits, virtx, virty, 75, 75, virtx, VGA_MAXPLANES, NUM_DEPTHS, vgaDepths, defvisual /* See above */, NUM_VISUALS, vgaVisuals, &ppcBSFuncRec); --- 271,277 ---- if (!mfbAllocatePrivates(pScreen, (int*)NULL, (int*)NULL)) return ; ! miScreenInit(pScreen, pbits, virtx, virty, 75, 75, width, VGA_MAXPLANES, NUM_DEPTHS, vgaDepths, defvisual /* See above */, NUM_VISUALS, vgaVisuals, &ppcBSFuncRec); *** ./programs/Xserver/hw/xfree86/vga2/drivers/ati/Imakefile@@/PUBLIC-LATEST Sat Jul 19 10:27:17 1997 --- xc/programs/Xserver/hw/xfree86/vga2/drivers/ati/Imakefile Fri Mar 6 16:43:46 1998 *************** *** 1,40 **** ! XCOMM $TOG: Imakefile /main/8 1997/07/19 10:27:19 kaleb $ - XCOMM $XFree86: xc/programs/Xserver/hw/xfree86/vga2/drivers/ati/Imakefile,v 3.7 1996/12/23 06:54:19 dawes Exp $ #include <Server.tmpl> ! SRCS = ati_driver.c ati_bank.s ! OBJS = ati_driver.o ati_bank.o #if XF86LinkKit INCLUDES = -I. -I../../../include -I../../../include/X11 -I../.. #else INCLUDES = -I. -I$(XF86COMSRC) -I$(XF86HWSRC) -I$(XF86OSSRC) -I$(XF86SRC) \ ! -I../../../vga256/vga -I$(SERVERSRC)/include -I$(XINCLUDESRC) #endif #if XF86Vga2Banked ! BANKEDDEFINES = -DBANKEDMONOVGA #endif ! DEFINES = -DMONOVGA $(BANKEDDEFINES) #if MakeHasPosixVariableSubstitutions SubdirLibraryRule($(OBJS)) #endif NormalLibraryObjectRule() ! NormalRelocatableTarget(ati_drv, $(OBJS)) ! LinkSourceFile(regati.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(ati_driver.c,$(VGADRIVERSRC)/ati) ! ObjectFromSpecialAsmSource(ati_bank,$(VGADRIVERSRC)/ati/bank,NullParameter) InstallLinkKitNonExecFile(Imakefile,$(LINKKITDIR)/drivers/vga2/ati) DependTarget() --- 1,126 ---- ! XCOMM $TOG: Imakefile /main/9 1998/03/06 16:45:23 kaleb $ + XCOMM $XFree86: xc/programs/Xserver/hw/xfree86/vga2/drivers/ati/Imakefile,v 3.7.2.2 1998/02/22 01:28:25 robin Exp $ + XCOMM + XCOMM Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + XCOMM + XCOMM Permission to use, copy, modify, distribute, and sell this software and + XCOMM its documentation for any purpose is hereby granted without fee, provided + XCOMM that the above copyright notice appear in all copies and that both that + XCOMM copyright notice and this permission notice appear in supporting + XCOMM documentation, and that the name of Marc Aurele La France not be used in + XCOMM advertising or publicity pertaining to distribution of the software + XCOMM without specific, written prior permission. Marc Aurele La France makes + XCOMM no representations about the suitability of this software for any + XCOMM purpose. It is provided "as-is" without express or implied warranty. + XCOMM + XCOMM MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS + XCOMM SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND + XCOMM FITNESS. IN NO EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY + XCOMM SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER + XCOMM RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF + XCOMM CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + XCOMM CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + XCOMM #include <Server.tmpl> ! #ifdef ATIDriverCCOptions ! CCOPTIONS = ATIDriverCCOptions ! #endif ! SRCS = ati.c atiadapter.c atiadjust.c atibank.c atibanks.s atibus.c atichip.c \ ! aticlock.c aticonsole.c aticrtc.c atidac.c atidsp.c atifbinit.c \ ! atigetmode.c atiident.c atiio.c atimach64.c atiprint.c atiprobe.c \ ! atireset.c atiutil.c ativalid.c ativga.c atividmem.c atiwonder.c + OBJS = ati.o atiadapter.o atiadjust.o atibank.o atibanks.o atibus.o atichip.o \ + aticlock.o aticonsole.o aticrtc.o atidac.o atidsp.o atifbinit.o \ + atigetmode.o atiident.o atiio.o atimach64.o atiprint.o atiprobe.o \ + atireset.o atiutil.o ativalid.o ativga.o atividmem.o atiwonder.o + #if XF86LinkKit INCLUDES = -I. -I../../../include -I../../../include/X11 -I../.. #else INCLUDES = -I. -I$(XF86COMSRC) -I$(XF86HWSRC) -I$(XF86OSSRC) -I$(XF86SRC) \ ! -I$(XF86SRC)/vga256/vga -I$(SERVERSRC)/include -I$(SERVERSRC)/cfb \ ! -I$(SERVERSRC)/mfb -I$(SERVERSRC)/mi -I$(XINCLUDESRC) #endif #if XF86Vga2Banked ! MONODEFS = -DBANKEDMONOVGA #endif ! DEFINES = -DPSZ=8 -DMONOVGA $(MONODEFS) #if MakeHasPosixVariableSubstitutions SubdirLibraryRule($(OBJS)) #endif NormalLibraryObjectRule() + NormalAsmObjectRule() ! NormalRelocatableTarget(ati_drv,$(OBJS)) ! LinkSourceFile(ati.c,$(VGADRIVERSRC)/ati) ! LinkSourceFile(ati.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atiadapter.c,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atiadapter.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atiadjust.c,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atiadjust.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atibank.c,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atibank.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atibanks.s,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atibus.c,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atibus.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atichip.c,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atichip.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(aticlock.c,$(VGADRIVERSRC)/ati) ! LinkSourceFile(aticlock.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(aticonsole.c,$(VGADRIVERSRC)/ati) ! LinkSourceFile(aticonsole.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(aticrtc.c,$(VGADRIVERSRC)/ati) ! LinkSourceFile(aticrtc.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atidac.c,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atidac.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atidepth.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atidsp.c,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atidsp.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atifbinit.c,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atifbinit.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atigetmode.c,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atigetmode.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atiident.c,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atiident.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atiio.c,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atiio.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atimach64.c,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atimach64.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atimono.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atiprint.c,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atiprint.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atiprobe.c,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atiprobe.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atiproto.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atiregs.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atireset.c,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atireset.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atiutil.c,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atiutil.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(ativalid.c,$(VGADRIVERSRC)/ati) ! LinkSourceFile(ativalid.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(ativersion.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(ativga.c,$(VGADRIVERSRC)/ati) ! LinkSourceFile(ativga.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atividmem.c,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atividmem.h,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atiwonder.c,$(VGADRIVERSRC)/ati) ! LinkSourceFile(atiwonder.h,$(VGADRIVERSRC)/ati) InstallLinkKitNonExecFile(Imakefile,$(LINKKITDIR)/drivers/vga2/ati) + #ifndef OS2Architecture DependTarget() + #endif *** ./programs/Xserver/hw/xfree86/vga2/drivers/et4000/Imakefile@@/PUBLIC-LATEST Sat Jul 19 10:27:52 1997 --- xc/programs/Xserver/hw/xfree86/vga2/drivers/et4000/Imakefile Fri Mar 6 16:43:50 1998 *************** *** 1,15 **** ! XCOMM $TOG: Imakefile /main/10 1997/07/19 10:27:54 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree86/vga2/drivers/et4000/Imakefile,v 3.7.2.1 1997/05/03 09:47:25 dawes Exp $ #include <Server.tmpl> ! SRCS = et4_driver.c et4_bank.s tseng_ramdac.c tseng_clock.c ! OBJS = et4_driver.o et4_bank.o tseng_ramdac.o tseng_clock.o #if XF86LinkKit INCLUDES = -I. -I../../../include -I../../../include/X11 -I../.. --- 1,15 ---- ! XCOMM $TOG: Imakefile /main/11 1998/03/06 16:45:27 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree86/vga2/drivers/et4000/Imakefile,v 3.7.2.2 1998/02/01 16:04:59 robin Exp $ #include <Server.tmpl> ! SRCS = et4_driver.c et4_bank.s tseng_ramdac.c tseng_clock.c tseng_dpms.c ! OBJS = et4_driver.o et4_bank.o tseng_ramdac.o tseng_clock.o tseng_dpms.o #if XF86LinkKit INCLUDES = -I. -I../../../include -I../../../include/X11 -I../.. *************** *** 30,35 **** --- 30,36 ---- LinkSourceFile(et4_driver.c,$(VGADRIVERSRC)/et4000) LinkSourceFile(tseng_ramdac.c,$(VGADRIVERSRC)/et4000) LinkSourceFile(tseng_clock.c,$(VGADRIVERSRC)/et4000) + LinkSourceFile(tseng_dpms.c,$(VGADRIVERSRC)/et4000) LinkSourceFile(tseng.h,$(VGADRIVERSRC)/et4000) ObjectFromSpecialAsmSource(et4_bank,$(VGADRIVERSRC)/et4000/bank,NullParameter) *** ./programs/Xserver/hw/xfree86/vga256/drivers/apm/Imakefile@@/PUBLIC-LATEST Sat Jul 19 10:30:44 1997 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/apm/Imakefile Fri Mar 6 16:44:12 1998 *************** *** 1,14 **** ! XCOMM $TOG: Imakefile /main/4 1997/07/19 10:30:46 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/apm/Imakefile,v 3.2 1996/12/27 07:04:44 dawes Exp $ #include <Server.tmpl> ! SRCS = apm_driver.c apm_bank.s apm_cursor.c ! OBJS = apm_driver.o apm_bank.o apm_cursor.o DEFINES = -DPSZ=8 --- 1,14 ---- ! XCOMM $TOG: Imakefile /main/5 1998/03/06 16:45:50 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/apm/Imakefile,v 3.2.2.2 1998/02/15 16:09:32 hohndel Exp $ #include <Server.tmpl> ! SRCS = apm_driver.c apm_bank.s apm_cursor.c apm_accel.c ! OBJS = apm_driver.o apm_bank.o apm_cursor.o apm_accel.o DEFINES = -DPSZ=8 *************** *** 17,23 **** #else INCLUDES = -I. -I$(XF86COMSRC) -I$(XF86HWSRC) -I$(XF86OSSRC) \ -I$(SERVERSRC)/mfb -I$(SERVERSRC)/mi \ ! -I$(SERVERSRC)/cfb -I../../vga \ -I$(FONTINCSRC) -I$(SERVERSRC)/include -I$(XINCLUDESRC) #endif --- 17,23 ---- #else INCLUDES = -I. -I$(XF86COMSRC) -I$(XF86HWSRC) -I$(XF86OSSRC) \ -I$(SERVERSRC)/mfb -I$(SERVERSRC)/mi \ ! -I$(SERVERSRC)/cfb -I../../vga -I../../../xaa \ -I$(FONTINCSRC) -I$(SERVERSRC)/include -I$(XINCLUDESRC) #endif *************** *** 30,38 **** NormalRelocatableTarget(apm_drv,$(OBJS)) InstallLinkKitNonExecFile(apm_driver.c,$(LINKKITDIR)/drivers/vga256/apm) InstallLinkKitNonExecFile(apm_bank.s,$(LINKKITDIR)/drivers/vga256/apm) InstallLinkKitNonExecFile(apm_cursor.c,$(LINKKITDIR)/drivers/vga256/apm) ! InstallLinkKitNonExecFile(apm_cursor.h,$(LINKKITDIR)/drivers/vga256/apm) InstallLinkKitNonExecFile(Imakefile,$(LINKKITDIR)/drivers/vga256/apm) DependTarget() --- 30,39 ---- NormalRelocatableTarget(apm_drv,$(OBJS)) InstallLinkKitNonExecFile(apm_driver.c,$(LINKKITDIR)/drivers/vga256/apm) + InstallLinkKitNonExecFile(apm_accel.c,$(LINKKITDIR)/drivers/vga256/apm) InstallLinkKitNonExecFile(apm_bank.s,$(LINKKITDIR)/drivers/vga256/apm) InstallLinkKitNonExecFile(apm_cursor.c,$(LINKKITDIR)/drivers/vga256/apm) ! InstallLinkKitNonExecFile(apm.h,$(LINKKITDIR)/drivers/vga256/apm) InstallLinkKitNonExecFile(Imakefile,$(LINKKITDIR)/drivers/vga256/apm) DependTarget() *** /dev/null Tue Jun 30 11:48:14 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/apm/apm.h Fri Mar 6 16:44:16 1998 *************** *** 0 **** --- 1,175 ---- + /* $TOG: apm.h /main/1 1998/03/06 16:45:54 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/apm/apm.h,v 1.1.2.2 1998/02/15 23:32:05 robin Exp $ */ + + + + #ifndef APM_H_ + #define APM_H_ + + typedef unsigned char u8; + typedef unsigned short u16; + typedef unsigned long u32; + + /* Memory mapped access to extended registers */ + #define RDXB(addr) (*(u8*)(apmRegBase+(addr))) + #define RDXW(addr) (*(u16*)(apmRegBase+(addr))) + #define RDXL(addr) (*(u32*)(apmRegBase+(addr))) + #define WRXB(addr,val) (void)(*(u8*)(apmRegBase+(addr)) = (val)) + #define WRXW(addr,val) (void)(*(u16*)(apmRegBase+(addr)) = (val)) + #define WRXL(addr,val) (void)(*(u32*)(apmRegBase+(addr)) = (val)) + + /* IO port access to extended registers */ + #define RDXB_IOP(addr) (wrinx(0x3c4, 0x1d, (addr) >> 2),inb(apm_xbase + ((addr) & 3))) + #define RDXW_IOP(addr) (wrinx(0x3c4, 0x1d, (addr) >> 2),inw(apm_xbase + ((addr) & 2))) + #define RDXL_IOP(addr) (wrinx(0x3c4, 0x1d, (addr) >> 2),inl(apm_xbase)) + #define WRXB_IOP(addr,val) (wrinx(0x3c4, 0x1d, (addr) >> 2),outb(apm_xbase + ((addr) & 3), (val))) + #define WRXW_IOP(addr,val) (wrinx(0x3c4, 0x1d, (addr) >> 2),outw(apm_xbase + ((addr) & 2), (val))) + #define WRXL_IOP(addr,val) (wrinx(0x3c4, 0x1d, (addr) >> 2),outl(apm_xbase, (val))) + + /* Dynamically accessed registers, either IO port or memory mapped. Kludge, kludge... :-) */ + #define RDXB_DYN(addr) (apmMMIO_Init ? RDXB(addr) : RDXB_IOP(addr)) + #define RDXW_DYN(addr) (apmMMIO_Init ? RDXW(addr) : RDXW_IOP(addr)) + #define RDXL_DYN(addr) (apmMMIO_Init ? RDXL(addr) : RDXL_IOP(addr)) + #define WRXB_DYN(addr,val) (apmMMIO_Init ? WRXB(addr,val) : (void) WRXB_IOP(addr,val)) + #define WRXW_DYN(addr,val) (apmMMIO_Init ? WRXW(addr,val) : (void) WRXW_IOP(addr,val)) + #define WRXL_DYN(addr,val) (apmMMIO_Init ? WRXL(addr,val) : (void) WRXL_IOP(addr,val)) + + #define STATUS() (RDXW(0x1fc)) + #define STATUS_HOSTBLTBUSY (1 << 8) + #define STATUS_ENGINEBUSY (1 << 10) + #define STATUS_FIFO (0x0f) + + #define SETFOREGROUNDCOLOR(c) WRXL(0x60,c) + #define SETBACKGROUNDCOLOR(c) WRXL(0x64,c) + + #define SETSOURCEX(x) WRXW(0x50, x) + #define SETSOURCEY(y) WRXW(0x52, y) + #define SETSOURCEXY(x,y) WRXL(0x50, (y) << 16 | (x) & 0xffff) + + #define SETDESTX(x) WRXW(0x54, x) + #define SETDESTY(y) WRXW(0x56, y) + #define SETDESTXY(x,y) WRXL(0x54, (y) << 16 | (x) & 0xffff) + + #define SETWIDTH(w) WRXW(0x58, w) + #define SETHEIGHT(h) WRXW(0x5A, h) + #define SETWIDTHHEIGHT(w,h) WRXL(0x58, (h) << 16 | (w) & 0xffff) + + #define SETBYTEMASK(mask) WRXB(0x47, mask) + + #define SETDDA_AXIALSTEP(step) WRXW(0x70, step) + #define SETDDA_DIAGONALSTEP(step) WRXW(0x72, step) + #define SETDDA_ERRORTERM(eterm) WRXW(0x74, eterm) + #define SETDDA_ADSTEP(s1,s2) WRXL(0x70, (s2) << 16 | (s1) & 0xffff) + + #define SETCLIP_CTRL(ctrl) WRXB(0x30, ctrl) + #define SETCLIP_LEFT(x) WRXW(0x38, x) + #define SETCLIP_TOP(y) WRXW(0x3A, y) + #define SETCLIP_LEFTTOP(x,y) WRXL(0x38, (y) << 16 | (x) & 0xffff) + #define SETCLIP_RIGHT(x) WRXW(0x3C, x) + #define SETCLIP_BOT(y) WRXW(0x3E, y) + #define SETCLIP_RIGHTBOT(x,y) WRXL(0x3C, (y) << 16 | (x) & 0xffff) + + /* RASTER OPERATION REGISTER */ + /* P = pattern S = source D = destination */ + #define SETROP(rop) WRXB(0x46, rop) + #define ROP_P_and_S_and_D 0x80 + #define ROP_S_xor_D 0x66 + #define ROP_S 0xCC + #define ROP_P 0xF0 + /* Then there are about 252 more operations ... */ + + + /* DRAWING ENGINE CONTROL REGISTER */ + #define SETDEC(control) WRXL(0x40, control) + #define DEC_OP_VECT_NOENDP 0x0000000D + #define DEC_OP_VECT_ENDP 0x0000000C + #define DEC_OP_HOSTBLT_SCREEN2HOST 0x00000009 + #define DEC_OP_HOSTBLT_HOST2SCREEN 0x00000008 + #define DEC_OP_STRIP 0x00000004 + #define DEC_OP_BLT_STRETCH 0x00000003 + #define DEC_OP_RECT 0x00000002 + #define DEC_OP_BLT 0x00000001 + #define DEC_OP_NOOP 0x00000000 + #define DEC_DIR_X_NEG (1 << 6) + #define DEC_DIR_X_POS (0 << 6) + #define DEC_DIR_Y_NEG (1 << 7) + #define DEC_DIR_Y_POS (0 << 7) + #define DEC_MAJORAXIS_X (0 << 8) + #define DEC_MAJORAXIS_Y (1 << 8) + #define DEC_SOURCE_LINEAR (1 << 9) + #define DEC_SOURCE_XY (0 << 9) + #define DEC_SOURCE_CONTIG (1 << 11) + #define DEC_SOURCE_RECTANGULAR (0 << 11) + #define DEC_SOURCE_MONOCHROME (1 << 12) + #define DEC_SOURCE_COLOR (0 << 12) + #define DEC_SOURCE_TRANSPARENCY (1 << 13) + #define DEC_SOURCE_NO_TRANSPARENCY (0 << 13) + #define DEC_BITDEPTH_24 (4 << 14) + #define DEC_BITDEPTH_32 (3 << 14) + #define DEC_BITDEPTH_16 (2 << 14) + #define DEC_BITDEPTH_8 (1 << 14) + #define DEC_BITDEPTH_COMPAT (0 << 14) + #define DEC_DEST_LINEAR (1 << 18) + #define DEC_DEST_XY (0 << 18) + #define DEC_DEST_RECTANGULAR (1 << 19) + #define DEC_DEST_OTHER (0 << 19) + #define DEC_DEST_TRANSPARENCY (1 << 20) + #define DEC_DEST_NO_TRANSPARENCY (0 << 20) + #define DEC_DEST_TRANSP_POLARITY (1 << 21) + #define DEC_DEST_TRANSP_POLARITYINV (0 << 21) + #define DEC_PATTERN_88_8bCOLOR (3 << 22) + #define DEC_PATTERN_88_1bMONO (2 << 22) + #define DEC_PATTERN_44_4bDITHER (1 << 22) + #define DEC_PATTERN_NONE (0 << 22) + #define DEC_WIDTH_1600 (7 << 24) + #define DEC_WIDTH_1280 (6 << 24) + #define DEC_WIDTH_1152 (5 << 24) + #define DEC_WIDTH_1024 (4 << 24) + #define DEC_WIDTH_800 (2 << 24) + #define DEC_WIDTH_640 (1 << 24) + #define DEC_WIDTH_LINEAR (0 << 24) + #define DEC_DEST_UPD_LASTPIX (3 << 27) + #define DEC_DEST_UPD_BLCORNER (2 << 27) + #define DEC_DEST_UPD_TRCORNER (1 << 27) + #define DEC_DEST_UPD_NONE (0 << 27) + #define DEC_QUICKSTART_ONDEST (3 << 29) + #define DEC_QUICKSTART_ONSOURCE (2 << 29) + #define DEC_QUICKSTART_ONDIMX (1 << 29) + #define DEC_QUICKSTART_NONE (0 << 29) + #define DEC_START (1 << 31) + #define DEC_START_NO (0 << 31) + + + #define AP6422 0 + #define AT24 1 + #define AT3D 2 + + extern volatile u8* apmRegBase; + extern vgaVideoChipRec APM; + extern vgaHWCursorRec vgaHWCursor; + extern int apmMMIO_Init; + extern u32 apm_xbase; + extern int apmChip; + + void ApmAccelInit(void); + void ApmCheckMMIO_Init(void); + + /* Variables defined in apm_cursor.c. */ + + extern int apmCursorHotX; + extern int apmCursorHotY; + extern int apmCursorWidth; + extern int apmCursorHeight; + + /* Functions defined in apm_cursor.c. */ + + Bool ApmCursorInit(char *pm, ScreenPtr pScr); + void ApmRestoreCursor(ScreenPtr pScr); + void ApmWarpCursor(ScreenPtr pScr, int x, int y); + void ApmQueryBestSize(int class, unsigned short *pwidth, unsigned short *pheight, ScreenPtr pScreen); + + + #endif *** /dev/null Tue Jun 30 11:48:15 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/apm/apm_accel.c Fri Mar 6 16:44:20 1998 *************** *** 0 **** --- 1,528 ---- + /* $TOG: apm_accel.c /main/1 1998/03/06 16:45:58 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/apm/apm_accel.c,v 1.1.2.3 1998/02/15 23:32:05 robin Exp $ */ + + + /* + Created 1997-06-08 by Henrik Harmsen (hch@cd.chalmers.se or Henrik.Harmsen@erv.ericsson.se) + + Does (for 8, 16 and 32 bpp modes): + - Filled rectangles + - Screen-screen bitblts + - Host-screen color expand bitblts (text acceleration) + - Line drawing + + See apm_driver.c for more info. + */ + + #include "vga256.h" + #include "compiler.h" + #include "xf86.h" + #include "xf86Priv.h" + #include "xf86_OSlib.h" + #include "xf86_HWlib.h" + #include "vga.h" + #include "miline.h" + #include "xf86xaa.h" + #include "apm.h" + + + /* Defines */ + #define MAXLOOP 1000000 + + + /* Exported functions */ + void ApmAccelInit(void); + + + /* Local functions */ + static void ApmSync(void); + static void ApmSync6422(void); + static void ApmSetupForFillRectSolid(int color, int rop, unsigned int planemask); + static void ApmSubsequentFillRectSolid(int x, int y, int w, int h); + static void ApmSetupForScreenToScreenCopy(int xdir, int ydir, int rop, unsigned int planemask, + int transparency_color); + static void ApmSubsequentScreenToScreenCopy(int x1, int y1, int x2, int y2, int w, int h); + static void ApmSetupForCPUToScreenColorExpand(int bg, int fg, int rop, unsigned int planemask); + static void ApmSubsequentCPUToScreenColorExpand(int x, int y, int w, int h, int skipleft); + static void ApmSetupForScreenToScreenColorExpand(int bg, int fg, int rop, + unsigned int planemask); + static void ApmSubsequentScreenToScreenColorExpand(int srcx, int srcy, int x, + int y, int w, int h); + static void ApmSubsequentBresenhamLine(int x1, int y1, int octant, int err, int e1, int e2, int length); + static void ApmSubsequentBresenhamLine6422(int x1, int y1, int octant, int err, int e1, int e2, int length); + static void ApmSetClippingRectangle(int x1, int y1, int x2, int y2); + + static void Dump(void* start, u32 len); + + + /* Statics */ + static int blitxdir, blitydir; + static u32 apmBitsPerPixel_DEC; + static u32 apmScreenWidth_DEC; + static int apmTransparency; + static int apmClip = FALSE; + + + /* Translation from X ROP's to APM ROP's. */ + static unsigned char apmROP[] = { + 0, + 0x88, + 0x44, + 0xCC, + 0x22, + 0xAA, + 0x66, + 0xEE, + 0x11, + 0x99, + 0x55, + 0xDD, + 0x33, + 0xBB, + 0x77, + 0xFF + }; + + + /* Globals */ + int apmMMIO_Init = FALSE; + volatile u8* apmRegBase = NULL; + + + /* Inline functions */ + static __inline__ void + WaitForFifo(int slots) + { + volatile int i; + + for(i = 0; i < MAXLOOP; i++) { + if ((STATUS() & STATUS_FIFO) >= slots) + break; + } + if (i == MAXLOOP) + FatalError("Hung in WaitForFifo()\n"); + } + + static __inline__ void + ApmCheckMMIO_InitFast(void) + { + if (!apmMMIO_Init) + ApmCheckMMIO_Init(); + } + + + /*********************************************************************************************/ + + void + ApmAccelInit(void) + { + xf86AccelInfoRec.Flags = BACKGROUND_OPERATIONS | PIXMAP_CACHE | + NO_PLANEMASK | COP_FRAMEBUFFER_CONCURRENCY | HARDWARE_CLIP_LINE; + + xf86AccelInfoRec.Sync = ApmSync; + + /* Accelerated filled rectangles */ + xf86GCInfoRec.PolyFillRectSolidFlags = NO_PLANEMASK; + xf86AccelInfoRec.SetupForFillRectSolid = ApmSetupForFillRectSolid; + xf86AccelInfoRec.SubsequentFillRectSolid = ApmSubsequentFillRectSolid; + + /* Accelerated CPU to screen color expansion */ + xf86AccelInfoRec.SetupForCPUToScreenColorExpand = ApmSetupForCPUToScreenColorExpand; + xf86AccelInfoRec.SubsequentCPUToScreenColorExpand = ApmSubsequentCPUToScreenColorExpand; + xf86AccelInfoRec.CPUToScreenColorExpandRange = 30*1024; + xf86AccelInfoRec.ColorExpandFlags = VIDEO_SOURCE_GRANULARITY_PIXEL | + NO_PLANEMASK | SCANLINE_PAD_DWORD | CPU_TRANSFER_PAD_QWORD + | BIT_ORDER_IN_BYTE_MSBFIRST | LEFT_EDGE_CLIPPING | + LEFT_EDGE_CLIPPING_NEGATIVE_X; + + + #if 0 + /* Since this code is not used yet, I cannot test or implement it */ + /* Accelerated screen to screen color expansion */ + xf86AccelInfoRec.SetupForScreenToScreenColorExpand = + ApmSetupForScreenToScreenColorExpand; + xf86AccelInfoRec.SubsequentScreenToScreenColorExpand = + ApmSubsequentScreenToScreenColorExpand; + #endif + + /* Accelerated screen-screen bitblts */ + xf86GCInfoRec.CopyAreaFlags = NO_PLANEMASK | NO_TRANSPARENCY; + xf86AccelInfoRec.SetupForScreenToScreenCopy = + ApmSetupForScreenToScreenCopy; + xf86AccelInfoRec.SubsequentScreenToScreenCopy = + ApmSubsequentScreenToScreenCopy; + + /* Accelerated Line drawing */ + xf86AccelInfoRec.SubsequentBresenhamLine = ApmSubsequentBresenhamLine; + xf86AccelInfoRec.SetClippingRectangle = ApmSetClippingRectangle; + xf86AccelInfoRec.ErrorTermBits = 15; + + /* Pixmap cache setup */ + xf86AccelInfoRec.PixmapCacheMemoryStart = + vga256InfoRec.virtualY * vga256InfoRec.displayWidth + * vga256InfoRec.bitsPerPixel / 8; + xf86AccelInfoRec.PixmapCacheMemoryEnd = + vga256InfoRec.videoRam * 1024 - 1024; + + if (apmChip == AP6422) + { + xf86AccelInfoRec.Sync = ApmSync6422; + xf86AccelInfoRec.SetupForCPUToScreenColorExpand = NULL; + xf86AccelInfoRec.SubsequentCPUToScreenColorExpand = NULL; + xf86AccelInfoRec.SubsequentBresenhamLine = ApmSubsequentBresenhamLine6422; + } + + } + + static void + ApmSetupForFillRectSolid(int color, int rop, unsigned int planemask) + { + ApmCheckMMIO_InitFast(); + WaitForFifo(3); + SETCLIP_CTRL(0); + SETFOREGROUNDCOLOR(color); + SETROP(apmROP[rop]); + } + + static void + ApmSubsequentFillRectSolid(int x, int y, int w, int h) + { + u32 c; + + WaitForFifo(3); + SETDESTXY(x,y); + SETWIDTHHEIGHT(w,h); + SETDEC(DEC_START | DEC_OP_RECT | apmScreenWidth_DEC | apmBitsPerPixel_DEC); + } + + static void + ApmSetupForScreenToScreenCopy(int xdir, int ydir, int rop, unsigned int planemask, + int transparency_color) + { + ApmCheckMMIO_InitFast(); + blitxdir = xdir; + blitydir = ydir; + WaitForFifo(2); + SETCLIP_CTRL(0); + SETROP(apmROP[rop]); + } + + + static void + ApmSubsequentScreenToScreenCopy(int x1, int y1, int x2, int y2, int w, int h) + { + u32 c = 0; + u32 sx, dx, sy, dy; + + WaitForFifo(4); + + if (blitxdir < 0) + { + c |= DEC_DIR_X_NEG; + sx = x1+w-1; + dx = x2+w-1; + } + else + { + c |= DEC_DIR_X_POS; + sx = x1; + dx = x2; + } + + if (blitydir < 0) + { + c |= DEC_DIR_Y_NEG; + sy = y1+h-1; + dy = y2+h-1; + } + else + { + c |= DEC_DIR_Y_POS; + sy = y1; + dy = y2; + } + + SETSOURCEXY(sx,sy); + SETDESTXY(dx,dy); + SETWIDTHHEIGHT(w,h); + + SETDEC(DEC_START | DEC_OP_BLT | c | apmScreenWidth_DEC | apmBitsPerPixel_DEC); + + } + + static void + ApmSetupForCPUToScreenColorExpand(int bg, int fg, int rop, unsigned int planemask) + { + ApmCheckMMIO_InitFast(); + WaitForFifo(3); + if (bg == -1) + { + SETFOREGROUNDCOLOR(fg); + SETBACKGROUNDCOLOR(fg+1); + apmTransparency = TRUE; + } + else + { + SETFOREGROUNDCOLOR(fg); + SETBACKGROUNDCOLOR(bg); + apmTransparency = FALSE; + } + SETROP(apmROP[rop]); + } + + static void + ApmSubsequentCPUToScreenColorExpand(int x, int y, int w, int h, int skipleft) + { + u32 c; + WaitForFifo(7); + + SETCLIP_LEFTTOP(x+skipleft, y); + SETCLIP_RIGHTBOT(x+w-1, y+h-1); + SETCLIP_CTRL(0x01); + SETSOURCEX(0); /* According to manual, it just has to be zero */ + SETDESTXY(x, y); + SETWIDTHHEIGHT((w + 31) & ~31, h); + + c = DEC_OP_HOSTBLT_HOST2SCREEN | DEC_SOURCE_LINEAR | DEC_SOURCE_CONTIG | DEC_SOURCE_MONOCHROME; + + if (apmTransparency) + c |= DEC_SOURCE_TRANSPARENCY; + + SETDEC(DEC_START | c | apmScreenWidth_DEC | apmBitsPerPixel_DEC); + } + + + static void + ApmSetupForScreenToScreenColorExpand(int bg, int fg, int rop, + unsigned int planemask) + { + /* To be written... */ + } + + static void + ApmSubsequentScreenToScreenColorExpand(int srcx, int srcy, int x, + int y, int w, int h) + { + /* To be written... */ + } + + static void + ApmSubsequentBresenhamLine(int x1, int y1, int octant, int err, int e1, int e2, int length) + { + u32 c = 0; + + WaitForFifo(5); + SETDESTXY(x1,y1); + SETWIDTH(length); + SETDDA_ERRORTERM(err); + SETDDA_ADSTEP(e1,e2); + + if (octant & XDECREASING) + c |= DEC_DIR_X_NEG; + else + c |= DEC_DIR_X_POS; + + if (octant & YDECREASING) + c |= DEC_DIR_Y_NEG; + else + c |= DEC_DIR_Y_POS; + + if (octant & YMAJOR) + c |= DEC_MAJORAXIS_Y; + else + c |= DEC_MAJORAXIS_X; + + SETDEC(DEC_START | DEC_OP_VECT_ENDP | c | apmScreenWidth_DEC | apmBitsPerPixel_DEC); + + if (apmClip) + { + WaitForFifo(1); + apmClip = FALSE; + SETCLIP_CTRL(0); + } + } + + static void + ApmSetClippingRectangle(int x1, int y1, int x2, int y2) + { + WaitForFifo(3); + SETCLIP_LEFTTOP(x1,y1); + SETCLIP_RIGHTBOT(x2,y2); + SETCLIP_CTRL(0x01); + apmClip = TRUE; + } + + /* This function is a f*cking kludge since I could not get MMIO to + work if I initialized in one of the functions in apm_driver.c (like + preferrably ApmFbInit()... */ + void + ApmCheckMMIO_Init(void) + { + if (!apmMMIO_Init) + { + apmMMIO_Init = TRUE; + wrinx(0x3C4, 0x1b, 0x24); /* Enable memory mapping */ + + apmRegBase = (u8*)vgaLinearBase + APM.ChipLinearSize - 2*1024; + + if (apmChip == AP6422) + ApmSync6422(); + else + ApmSync(); + + switch(vga256InfoRec.bitsPerPixel) + { + case 8: + apmBitsPerPixel_DEC = DEC_BITDEPTH_8; + break; + case 16: + apmBitsPerPixel_DEC = DEC_BITDEPTH_16; + break; + case 24: + apmBitsPerPixel_DEC = DEC_BITDEPTH_24; + break; + case 32: + apmBitsPerPixel_DEC = DEC_BITDEPTH_32; + break; + default: + ErrorF("Cannot set up drawing engine control for bpp = %d\n", + vga256InfoRec.bitsPerPixel); + break; + } + + if (apmChip == AP6422) + apmBitsPerPixel_DEC = DEC_BITDEPTH_COMPAT; + + switch(vga256InfoRec.displayWidth) + { + case 640: + apmScreenWidth_DEC = DEC_WIDTH_640; + break; + case 800: + apmScreenWidth_DEC = DEC_WIDTH_800; + break; + case 1024: + apmScreenWidth_DEC = DEC_WIDTH_1024; + break; + case 1152: + apmScreenWidth_DEC = DEC_WIDTH_1152; + break; + case 1280: + apmScreenWidth_DEC = DEC_WIDTH_1280; + break; + case 1600: + apmScreenWidth_DEC = DEC_WIDTH_1600; + break; + default: + ErrorF("Cannot set up drawing engine control for screen width = %d\n", vga256InfoRec.displayWidth); + break; + } + + + SETBYTEMASK(0xff); + + SETROP(ROP_S); + + xf86AccelInfoRec.CPUToScreenColorExpandBase = (pointer)((u8*)vgaLinearBase + + APM.ChipLinearSize - 32*1024); + + /*Dump(apmRegBase + 0xe8, 8);*/ + + } + } + + static void + ApmSync(void) + { + volatile u32 i, stat; + + for(i = 0; i < MAXLOOP; i++) { + stat = STATUS(); + if ((!(stat & (STATUS_HOSTBLTBUSY | STATUS_ENGINEBUSY))) && + ((stat & STATUS_FIFO) >= 8)) + break; + } + if (i == MAXLOOP) + FatalError("Hung in ApmSync()\n"); + } + + + static void + Dump(void* start, u32 len) + { + u8* i; + int c = 0; + ErrorF("Memory Dump. Start 0x%x length %d\n", (u32)start, len); + for (i = (u8*)start; i < ((u8*)start+len); i++) + { + ErrorF("%02x ", *i); + if (c++ % 25 == 24) + ErrorF("\n"); + } + ErrorF("\n"); + } + + /************** AP6422 code ***************/ + + static void + ApmSubsequentBresenhamLine6422(int x1, int y1, int octant, int err, int e1, int e2, int length) + { + u32 c = 0; + + WaitForFifo(1); + SETDESTXY(x1,y1); + WaitForFifo(4); + SETWIDTH(length); + SETDDA_ERRORTERM(err); + SETDDA_ADSTEP(e1,e2); + + if (octant & XDECREASING) + c |= DEC_DIR_X_NEG; + else + c |= DEC_DIR_X_POS; + + if (octant & YDECREASING) + c |= DEC_DIR_Y_NEG; + else + c |= DEC_DIR_Y_POS; + + if (octant & YMAJOR) + c |= DEC_MAJORAXIS_Y; + else + c |= DEC_MAJORAXIS_X; + + SETDEC(DEC_START | DEC_OP_VECT_ENDP | c | apmScreenWidth_DEC | apmBitsPerPixel_DEC); + + if (apmClip) + { + WaitForFifo(1); + apmClip = FALSE; + SETCLIP_CTRL(0); + } + } + + + static void + ApmSync6422(void) + { + volatile u32 i, stat, j; + + /* This is a kludge. Somehow we can't trust the status register. Don't + know why... We shouldn't be forced to read the status reg and get + a correct value more than once... */ + for (j = 0; j < 2; j++) + { + for(i = 0; i < MAXLOOP; i++) { + stat = STATUS(); + if ((!(stat & (STATUS_HOSTBLTBUSY | STATUS_ENGINEBUSY))) && + ((stat & STATUS_FIFO) >= 4)) + break; + } + } + if (i == MAXLOOP) + FatalError("Hung in ApmSync6422()\n"); + } + *** ./programs/Xserver/hw/xfree86/vga256/drivers/apm/apm_cursor.c@@/PUBLIC-LATEST Sat Jul 19 10:30:55 1997 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/apm/apm_cursor.c Fri Mar 6 16:44:24 1998 *************** *** 1,9 **** ! /* $TOG: apm_cursor.c /main/4 1997/07/19 10:30:57 kaleb $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/apm/apm_cursor.c,v 3.2.2.1 1997/05/31 13:34:41 dawes Exp $ */ #include "X.h" #include "Xproto.h" --- 1,9 ---- ! /* $TOG: apm_cursor.c /main/5 1998/03/06 16:46:02 kaleb $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/apm/apm_cursor.c,v 3.2.2.2 1998/01/18 10:35:30 hohndel Exp $ */ #include "X.h" #include "Xproto.h" *************** *** 20,45 **** #include "xf86_Option.h" #include "xf86_OSlib.h" #include "vga.h" ! extern Bool vgaUseLinearAddressing; - static Bool ApmRealizeCursor(); - static Bool ApmUnrealizeCursor(); - static void ApmSetCursor(); - static void ApmMoveCursor(); - static void ApmRecolorCursor(); - static miPointerSpriteFuncRec apmPointerSpriteFuncs = { ! ApmRealizeCursor, ! ApmUnrealizeCursor, ! ApmSetCursor, ! ApmMoveCursor, }; /* vga256 interface defines Init, Restore, Warp, QueryBestSize. */ - extern miPointerScreenFuncRec xf86PointerScreenFuncs; extern xf86InfoRec xf86Info; --- 20,47 ---- #include "xf86_Option.h" #include "xf86_OSlib.h" #include "vga.h" + #include "apm.h" ! static void ApmShowCursor(void); ! static void ApmHideCursor(void); ! static Bool ApmRealizeCursor(ScreenPtr pScr, CursorPtr pCurs); ! static Bool ApmUnrealizeCursor(ScreenPtr pScr, CursorPtr pCurs); ! static void ApmLoadCursorToCard(ScreenPtr pScr, CursorPtr pCurs, int x, int y); ! static void ApmLoadCursor(ScreenPtr pScr, CursorPtr pCurs, int x, int y); ! static void ApmSetCursor(ScreenPtr pScr, CursorPtr pCurs, int x, int y, Bool generateEvent); ! static void ApmMoveCursor(ScreenPtr pScr, int x, int y); ! static void ApmRecolorCursor(ScreenPtr pScr, CursorPtr pCurs, Bool displayed); static miPointerSpriteFuncRec apmPointerSpriteFuncs = { ! ApmRealizeCursor, ! ApmUnrealizeCursor, ! (void(*)())ApmSetCursor, ! ApmMoveCursor, }; /* vga256 interface defines Init, Restore, Warp, QueryBestSize. */ extern miPointerScreenFuncRec xf86PointerScreenFuncs; extern xf86InfoRec xf86Info; *************** *** 56,66 **** int apmCursorHotY; int apmCursorWidth; /* Must be set before calling ApmCursorInit. */ int apmCursorHeight; static CursorPtr apmCursorpCurs; - extern void wrxl(); - extern void wrxw(); - extern void wrxb(); /* * This is a high-level init function, called once; it passes a local --- 58,66 ---- int apmCursorHotY; int apmCursorWidth; /* Must be set before calling ApmCursorInit. */ int apmCursorHeight; + static CursorPtr apmCursorpCurs; /* * This is a high-level init function, called once; it passes a local *************** *** 68,92 **** * It is called by the SVGA server. */ ! Bool ApmCursorInit(pm, pScr) ! char *pm; ! ScreenPtr pScr; { ! if (apmCursorGeneration != serverGeneration) { ! if (!(miPointerInitialize(pScr, &apmPointerSpriteFuncs, ! &xf86PointerScreenFuncs, FALSE))) ! return FALSE; ! apmCursorHotX = 0; ! apmCursorHotY = 0; ! } ! apmCursorGeneration = serverGeneration; ! apmCursorControlMode = 0; ! apmCursorAddress = vga256InfoRec.videoRam * 1024 - 35 * 1024; ! return TRUE; } /* --- 68,93 ---- * It is called by the SVGA server. */ ! Bool ! ApmCursorInit(char *pm, ScreenPtr pScr) { ! if (apmCursorGeneration != serverGeneration) { ! if (!(miPointerInitialize(pScr, &apmPointerSpriteFuncs, ! &xf86PointerScreenFuncs, FALSE))) ! return FALSE; ! apmCursorHotX = 0; ! apmCursorHotY = 0; ! } ! apmCursorGeneration = serverGeneration; ! apmCursorControlMode = 0; ! apmCursorAddress = APM.ChipLinearSize - 34*1024; ! /* apmCursorAddress = vga256InfoRec.videoRam * 1024 - 35 * 1024; */ ! ! return TRUE; } /* *************** *** 94,102 **** * It's a local function, it's not called from outside of the module. */ ! static void ApmShowCursor() { ! /* Enable the hardware cursor. */ ! wrxb(0x140, apmCursorControlMode | 1); } /* --- 95,106 ---- * It's a local function, it's not called from outside of the module. */ ! static void ! ApmShowCursor(void) ! { ! /* Enable the hardware cursor. */ ! ApmCheckMMIO_Init(); ! WRXB_DYN(0x140, apmCursorControlMode | 1); } /* *************** *** 104,112 **** * This is also a local function, it's not called from outside. */ ! void ApmHideCursor() { ! /* Disable the hardware cursor. */ ! wrxb(0x140, apmCursorControlMode); } /* --- 108,119 ---- * This is also a local function, it's not called from outside. */ ! static void ! ApmHideCursor(void) ! { ! ApmCheckMMIO_Init(); ! /* Disable the hardware cursor. */ ! WRXB_DYN(0x140, apmCursorControlMode); } /* *************** *** 116,166 **** * can conveniently handle, and store that in system memory. */ ! static Bool ApmRealizeCursor(pScr, pCurs) ! ScreenPtr pScr; ! CursorPtr pCurs; { ! register int i, j; ! unsigned char *pServMsk; ! unsigned char *pServSrc; ! int index = pScr->myNum; ! pointer *pPriv = &pCurs->bits->devPriv[index]; ! int w, h, stride; ! unsigned char *ram, *dst, v; ! CursorBitsPtr bits = pCurs->bits; ! if (pCurs->bits->refcnt > 1) ! return TRUE; ! ram = (unsigned char *)xalloc(1024); ! *pPriv = (pointer) ram; ! if (!ram) ! return FALSE; ! memset(ram, 0xaa, 64 * 64 / 4); ! pServSrc = (unsigned char *)bits->source; ! pServMsk = (unsigned char *)bits->mask; #define MAX_CURS 64 ! h = pCurs->bits->height; ! if (h > MAX_CURS) h = MAX_CURS; ! w = pCurs->bits->width; ! if (w > MAX_CURS) w = MAX_CURS; ! stride = ((pCurs->bits->width + 31) / 32) * 4; ! for (i = 0; i < h; ++i) { ! pServSrc = pCurs->bits->source + stride * i; ! pServMsk = pCurs->bits->mask + stride * i; ! dst = ram + i * 16; ! for (j = 0; j < w; ++j) { ! v = (pServSrc[j / 8] >> (j % 8)) & 1; ! v |= ((pServMsk[j / 8] >> (j % 8)) & 1) << 1; ! v <<= (j & 3) * 2; ! dst[j / 4] ^= v; ! } ! } ! return TRUE; } /* --- 123,172 ---- * can conveniently handle, and store that in system memory. */ ! static Bool ! ApmRealizeCursor(ScreenPtr pScr, CursorPtr pCurs) { ! register int i, j; ! unsigned char *pServMsk; ! unsigned char *pServSrc; ! int index = pScr->myNum; ! pointer *pPriv = &pCurs->bits->devPriv[index]; ! int w, h, stride; ! unsigned char *ram, *dst, v; ! CursorBitsPtr bits = pCurs->bits; ! if (pCurs->bits->refcnt > 1) ! return TRUE; ! ram = (unsigned char *)xalloc(1024); ! *pPriv = (pointer) ram; ! if (!ram) ! return FALSE; ! memset(ram, 0xaa, 64 * 64 / 4); ! pServSrc = (unsigned char *)bits->source; ! pServMsk = (unsigned char *)bits->mask; #define MAX_CURS 64 ! h = pCurs->bits->height; ! if (h > MAX_CURS) h = MAX_CURS; ! w = pCurs->bits->width; ! if (w > MAX_CURS) w = MAX_CURS; ! stride = ((pCurs->bits->width + 31) / 32) * 4; ! for (i = 0; i < h; ++i) { ! pServSrc = pCurs->bits->source + stride * i; ! pServMsk = pCurs->bits->mask + stride * i; ! dst = ram + i * 16; ! for (j = 0; j < w; ++j) { ! v = (pServSrc[j / 8] >> (j % 8)) & 1; ! v |= ((pServMsk[j / 8] >> (j % 8)) & 1) << 1; ! v <<= (j & 3) * 2; ! dst[j / 4] ^= v; ! } ! } ! return TRUE; } /* *************** *** 168,185 **** * cursor image storage that we created needs to be deallocated. */ ! static Bool ApmUnrealizeCursor(pScr, pCurs) ! ScreenPtr pScr; ! CursorPtr pCurs; { ! pointer priv; ! if (pCurs->bits->refcnt <= 1 && ! (priv = pCurs->bits->devPriv[pScr->myNum])) { ! xfree(priv); ! pCurs->bits->devPriv[pScr->myNum] = 0x0; ! } ! return TRUE; } /* --- 174,190 ---- * cursor image storage that we created needs to be deallocated. */ ! static Bool ! ApmUnrealizeCursor(ScreenPtr pScr, CursorPtr pCurs) { ! pointer priv; ! if (pCurs->bits->refcnt <= 1 && ! (priv = pCurs->bits->devPriv[pScr->myNum])) { ! xfree(priv); ! pCurs->bits->devPriv[pScr->myNum] = 0x0; ! } ! return TRUE; } /* *************** *** 191,225 **** * module. */ ! extern void ApmSetWrite(); ! ! static void ApmLoadCursorToCard(pScr, pCurs, x, y) ! ScreenPtr pScr; ! CursorPtr pCurs; ! int x, y; /* Not used for APM. */ { ! unsigned char *cursor_image; ! int index = pScr->myNum; ! if (!xf86VTSema) ! return; ! cursor_image = pCurs->bits->devPriv[index]; ! if (vgaUseLinearAddressing) ! memcpy((unsigned char *)vgaLinearBase + apmCursorAddress, ! cursor_image, 1024); ! else { ! /* ! * The cursor can only be in the last 16K of video memory, ! * which fits in the last banking window. ! */ ! vgaSaveBank(); ! ApmSetWrite(apmCursorAddress >> 16); ! memcpy((unsigned char *)vgaBase + (apmCursorAddress & 0xFFFF), ! cursor_image, 1024); ! vgaRestoreBank(); ! } } /* --- 196,214 ---- * module. */ ! static void ! ApmLoadCursorToCard(ScreenPtr pScr, CursorPtr pCurs, int x, int y) { ! unsigned char *cursor_image; ! int index = pScr->myNum; ! if (!xf86VTSema) ! return; ! cursor_image = pCurs->bits->devPriv[index]; ! memcpy((unsigned char *)vgaLinearBase + apmCursorAddress, ! cursor_image, 1024); } /* *************** *** 231,265 **** * function in the Pointer record needs to do). */ ! static void ApmLoadCursor(pScr, pCurs, x, y) ! ScreenPtr pScr; ! CursorPtr pCurs; ! int x, y; { ! if (!xf86VTSema) ! return; ! if (!pCurs) ! return; ! /* Remember the cursor currently loaded into this cursor slot. */ ! apmCursorpCurs = pCurs; ! ApmHideCursor(); ! /* Program the cursor image address in video memory. */ ! /* We use the last slot (the last 256 bytes of video memory). */ ! wrxw(0x144, vga256InfoRec.videoRam - 33); ! ApmLoadCursorToCard(pScr, pCurs, x, y); ! ApmRecolorCursor(pScr, pCurs, 1); ! /* Position cursor */ ! ApmMoveCursor(pScr, x, y); ! /* Turn it on. */ ! ApmShowCursor(); } /* --- 220,252 ---- * function in the Pointer record needs to do). */ ! static void ! ApmLoadCursor(ScreenPtr pScr, CursorPtr pCurs, int x, int y) { ! if (!xf86VTSema) ! return; ! if (!pCurs) ! return; ! /* Remember the cursor currently loaded into this cursor slot. */ ! apmCursorpCurs = pCurs; ! ApmHideCursor(); ! /* Program the cursor image address in video memory. */ ! /* We use the last slot (the last 256 bytes of video memory). */ ! WRXW_DYN(0x144, (apmCursorAddress >> 10)); ! ApmLoadCursorToCard(pScr, pCurs, x, y); ! ApmRecolorCursor(pScr, pCurs, 1); ! /* Position cursor */ ! ApmMoveCursor(pScr, x, y); ! /* Turn it on. */ ! ApmShowCursor(); } /* *************** *** 266,284 **** * This function should display a new cursor at a new position. */ ! static void ApmSetCursor(pScr, pCurs, x, y, generateEvent) ! ScreenPtr pScr; ! CursorPtr pCurs; ! int x, y; ! Bool generateEvent; { ! if (!pCurs) ! return; ! apmCursorHotX = pCurs->bits->xhot; ! apmCursorHotY = pCurs->bits->yhot; ! ApmLoadCursor(pScr, pCurs, x, y); } /* --- 253,268 ---- * This function should display a new cursor at a new position. */ ! static void ! ApmSetCursor(ScreenPtr pScr, CursorPtr pCurs, int x, int y, Bool generateEvent) { ! if (!pCurs) ! return; ! apmCursorHotX = pCurs->bits->xhot; ! apmCursorHotY = pCurs->bits->yhot; ! ApmLoadCursor(pScr, pCurs, x, y); } /* *************** *** 286,299 **** * displayed earlier. It is called by the SVGA server. */ ! void ApmRestoreCursor(pScr) ! ScreenPtr pScr; { ! int x, y; ! miPointerPosition(&x, &y); ! ApmLoadCursor(pScr, apmCursorpCurs, x, y); } /* --- 270,283 ---- * displayed earlier. It is called by the SVGA server. */ ! void ! ApmRestoreCursor(ScreenPtr pScr) { ! int x, y; ! miPointerPosition(&x, &y); ! ApmLoadCursor(pScr, apmCursorpCurs, x, y); } /* *************** *** 301,343 **** * the graphic chip display the cursor at the new position. */ ! static void ApmMoveCursor(pScr, x, y) ! ScreenPtr pScr; ! int x, y; { ! int xorigin, yorigin; ! if (!xf86VTSema) ! return; ! x -= vga256InfoRec.frameX0 + apmCursorHotX; ! y -= vga256InfoRec.frameY0 + apmCursorHotY; ! /* ! * If the cursor is partly out of screen at the left or top, ! * we need set the origin. ! */ ! xorigin = 0; ! yorigin = 0; ! if (x < 0) { ! xorigin = -x; ! x = 0; ! } ! if (y < 0) { ! yorigin = -y; ! y = 0; ! } ! if (XF86SCRNINFO(pScr)->modes->Flags & V_DBLSCAN) ! y *= 2; ! /* Program the cursor origin (offset into the cursor bitmap). */ ! wrxb(0x14c, xorigin); ! wrxb(0x14d, yorigin); ! /* Program the new cursor position. */ ! wrxw(0x148, x); ! wrxw(0x14a, y); } /* --- 285,326 ---- * the graphic chip display the cursor at the new position. */ ! static void ! ApmMoveCursor(ScreenPtr pScr, int x, int y) { ! int xorigin, yorigin; ! if (!xf86VTSema) ! return; ! x -= vga256InfoRec.frameX0 + apmCursorHotX; ! y -= vga256InfoRec.frameY0 + apmCursorHotY; ! /* ! * If the cursor is partly out of screen at the left or top, ! * we need set the origin. ! */ ! xorigin = 0; ! yorigin = 0; ! if (x < 0) { ! xorigin = -x; ! x = 0; ! } ! if (y < 0) { ! yorigin = -y; ! y = 0; ! } ! if (XF86SCRNINFO(pScr)->modes->Flags & V_DBLSCAN) ! y *= 2; ! /* Program the cursor origin (offset into the cursor bitmap). */ ! WRXB_DYN(0x14c, xorigin); ! WRXB_DYN(0x14d, yorigin); ! /* Program the new cursor position. */ ! WRXW_DYN(0x148, x); ! WRXW_DYN(0x14a, y); } /* *************** *** 346,381 **** * Adapted from accel/s3/s3Cursor.c. */ ! static void ApmRecolorCursor(pScr, pCurs, displayed) ! ScreenPtr pScr; ! CursorPtr pCurs; ! Bool displayed; { ! ColormapPtr pmap; ! unsigned short packedcolfg, packedcolbg; ! xColorItem sourceColor, maskColor; ! if (!xf86VTSema) ! return; ! switch (vgaBitsPerPixel) { ! case 8: ! wrxb(0x141, 0); /* XXXX Fixed colors, debugging only. */ ! wrxb(0x142, 1); ! break; ! case 16: ! case 32: ! packedcolfg = ((pCurs->foreRed & 0xe000) >> 8) ! | ((pCurs->foreGreen & 0xe000) >> 11) ! | ((pCurs->foreBlue & 0xc000) >> 14); ! packedcolbg = ((pCurs->backRed & 0xe000) >> 8) ! | ((pCurs->backGreen & 0xe000) >> 11) ! | ((pCurs->backBlue & 0xc000) >> 14); ! ! wrxb(0x141, packedcolfg); ! wrxb(0x142, packedcolbg); ! break; ! } } /* --- 329,384 ---- * Adapted from accel/s3/s3Cursor.c. */ ! static void ! ApmRecolorCursor(ScreenPtr pScr, CursorPtr pCurs, Bool displayed) { ! ColormapPtr pmap; ! unsigned short packedcolfg, packedcolbg; ! xColorItem sourceColor, maskColor; ! if (!xf86VTSema) ! return; ! switch (vgaBitsPerPixel) { ! #if 0 ! case 8: ! WRXB_DYN(0x141, 0); /* XXXX Fixed colors, debugging only. */ ! WRXB_DYN(0x142, 1); ! break; ! #endif ! case 8: ! /* ! * Now that GetInstalledColormaps is also added to ! * vga256/vga/vgacmap.c, we can use the hw cursor at 8bpp. ! */ ! vgaGetInstalledColormaps(pScr, &pmap); ! sourceColor.red = pCurs->foreRed; ! sourceColor.green = pCurs->foreGreen; ! sourceColor.blue = pCurs->foreBlue; ! FakeAllocColor(pmap, &sourceColor); ! maskColor.red = pCurs->backRed; ! maskColor.green = pCurs->backGreen; ! maskColor.blue = pCurs->backBlue; ! FakeAllocColor(pmap, &maskColor); ! FakeFreeColor(pmap, sourceColor.pixel); ! FakeFreeColor(pmap, maskColor.pixel); ! ! WRXB_DYN(0x141, sourceColor.pixel); ! WRXB_DYN(0x142, maskColor.pixel); ! break; ! case 16: ! case 32: ! packedcolfg = ((pCurs->foreRed & 0xe000) >> 8) ! | ((pCurs->foreGreen & 0xe000) >> 11) ! | ((pCurs->foreBlue & 0xc000) >> 14); ! packedcolbg = ((pCurs->backRed & 0xe000) >> 8) ! | ((pCurs->backGreen & 0xe000) >> 11) ! | ((pCurs->backBlue & 0xc000) >> 14); ! ! WRXB_DYN(0x141, packedcolfg); ! WRXB_DYN(0x142, packedcolbg); ! break; ! } } /* *************** *** 383,394 **** * by the SVGA server. */ ! void ApmWarpCursor(pScr, x, y) ! ScreenPtr pScr; ! int x, y; { ! miPointerWarpCursor(pScr, x, y); ! xf86Info.currentScreen = pScr; } /* --- 386,396 ---- * by the SVGA server. */ ! void ! ApmWarpCursor(ScreenPtr pScr, int x, int y) { ! miPointerWarpCursor(pScr, x, y); ! xf86Info.currentScreen = pScr; } /* *************** *** 397,416 **** * It is called by the SVGA server. */ ! void ApmQueryBestSize(class, pwidth, pheight, pScreen) ! int class; ! unsigned short *pwidth; ! unsigned short *pheight; ! ScreenPtr pScreen; { ! if (*pwidth > 0) { ! if (class == CursorShape) { ! *pwidth = apmCursorWidth; ! *pheight = apmCursorHeight; ! } ! else ! (void) mfbQueryBestSize(class, pwidth, pheight, pScreen); ! } } - --- 399,414 ---- * It is called by the SVGA server. */ ! void ! ApmQueryBestSize(int class, unsigned short *pwidth, unsigned short *pheight, ScreenPtr pScreen) { ! if (*pwidth > 0) { ! if (class == CursorShape) { ! *pwidth = apmCursorWidth; ! *pheight = apmCursorHeight; ! } ! else ! (void) mfbQueryBestSize(class, pwidth, pheight, pScreen); ! } } *** ./programs/Xserver/hw/xfree86/vga256/drivers/apm/apm_driver.c@@/PUBLIC-LATEST Sat Jul 19 10:31:05 1997 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/apm/apm_driver.c Fri Mar 6 16:44:29 1998 *************** *** 1,26 **** ! /* $TOG: apm_driver.c /main/6 1997/07/19 10:31:08 kaleb $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/apm/apm_driver.c,v 3.7.2.2 1997/05/09 07:15:27 hohndel Exp $ */ /* ! * These are X and server generic header files. ! */ #include <math.h> #include "X.h" #include "input.h" #include "screenint.h" #include "dix.h" - - /* - * These are XFree86-specific header files - */ #include "compiler.h" - #include "xf86.h" #include "xf86Priv.h" #include "xf86_OSlib.h" #include "xf86_HWlib.h" #define XCONFIG_FLAGS_ONLY --- 1,69 ---- ! /* $TOG: apm_driver.c /main/7 1998/03/06 16:46:07 kaleb $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/apm/apm_driver.c,v 3.7.2.6 1998/02/15 23:32:06 robin Exp $ */ /* ! TODO (also see apm_accel.c) ! ! Add 24 bpp support ! ! New code for max dotclock? ! Hercules says: Do not let the video dot clock * bytes per pixel ! go above the available memory bandwidth which is around 200MB/s. ! Then how come the manual says it is OK to use a 144MHz vclk in 16 ! bit for 1280x1024? That is something like 290MB/s...? Hmm... ! It can't be double indexed mode either, since that doesn't exist ! for anything but 8 bit... ! */ ! ! /* ! Created by Kent Hamilton for Xfree86 from source from Alliance ! ! Modified 1997-06 by Henrik Harmsen (hch@cd.chalmers.se, ! Henrik.Harmsen@erv.ericsson.se) ! - Added support for AT3D ! - Acceleration added for 8,16,32bpp: (for AT3D and AT24) ! - Filled rectangles ! - Screen-screen bitblts ! - Host-screen color expansion bitblts for text ! - DPMS support ! - Enabled hardware cursor code (also in 8bpp) ! - Set to programmable VCLK clock ! - Set MCLK to 57.3 MHz on AT3D. ! - Various bugfixes and cleanups ! ! Modified 1997-07-06 by Henrik Harmsen ! - Fixed bug that made the HW cursor screw up on VT switches ! - Probably fixed bug that screwed up the screen when using ! screen-screen bitblts. This forced me to put an ApmSync() at ! the end of ApmSubsequentScreenToScreenCopy() which makes ! me unhappy... But: Better it works than not... ! ! Modified 1998-02-08 by Henrik Harmsen ! - Added DGA support. ! - Removed accel for AT24, didn't work anyways according to reports... ! ! Modified 1998-02-14 by Henrik Harmsen ! - Added accel support for AT24 again. Got hardware, worked fine. ! - Added accel support for AP6422. ! - Fixed clock register calculation for AP6422 and AT24. ! - DPMS support for AT24 & AP6422. ! - 2% faster text accel for AT24/AT3D :-) ! ! */ ! #include <math.h> #include "X.h" #include "input.h" #include "screenint.h" #include "dix.h" #include "compiler.h" #include "xf86.h" #include "xf86Priv.h" + #include "xf86Procs.h" #include "xf86_OSlib.h" #include "xf86_HWlib.h" #define XCONFIG_FLAGS_ONLY *************** *** 27,103 **** #include "xf86_Config.h" #include "vga.h" #include "vgaPCI.h" - #include "vga256.h" ! #include "apm_cursor.h" ! extern vgaHWCursorRec vgaHWCursor; ! /* ! * Driver data structures. ! */ typedef struct { ! /* ! * This structure defines all of the register-level information ! * that must be stored to define a video mode for this chipset. ! * The 'vgaHWRec' member must be first, and contains all of the ! * standard VGA register information, as well as saved text and ! * font data. ! */ ! vgaHWRec std; /* good old IBM VGA */ ! /* ! * Any other registers or other data that the new chipset needs ! * to be saved should be defined here. The Init/Save/Restore ! * functions will manipulate theses fields. Examples of things ! * that would go here are registers that contain bank select ! * registers, or extended clock select bits, or extensions to ! * the timing registers. Use 'unsigned char' as the type for ! * these registers. ! */ ! unsigned char SR1B; ! unsigned char SR1C; ! unsigned char CR19; ! unsigned char CR1A; ! unsigned char CR1B; ! unsigned char CR1C; ! unsigned char CR1D; ! unsigned char CR1E; ! unsigned char XR80; ! unsigned char XRC0; ! unsigned char XRC6; ! unsigned long XRE8; ! unsigned long XREC; ! unsigned long XRF0; ! unsigned long XRF4; ! unsigned long XR140; ! unsigned short XR144; ! unsigned long XR148; ! unsigned short XR14C; } vgaApmRec, *vgaApmPtr; ! /* ! * Forward definitions for the functions that make up the driver. See ! * the definitions of these functions for the real scoop. ! */ ! static Bool ApmProbe(); ! static char * ApmIdent(); ! static Bool ApmClockSelect(); ! static void ApmEnterLeave(); ! static Bool ApmInit(); ! static int ApmValidMode(); ! static void * ApmSave(); ! static void ApmRestore(); ! static void ApmAdjust(); ! static void ApmFbInit(); ! /* ! * These are the bank select functions. There are defined in stub_bank.s ! */ ! void ApmSetRead(); ! void ApmSetWrite(); ! void ApmSetReadWrite(); /* * This data structure defines the driver itself. The data structure is * initialized with the functions that make up the driver and some data --- 70,151 ---- #include "xf86_Config.h" #include "vga.h" #include "vgaPCI.h" #include "vga256.h" ! #ifdef XFreeXDGA ! #include "X.h" ! #include "Xproto.h" ! #include "scrnintstr.h" ! #include "servermd.h" ! #define _XF86DGA_SERVER_ ! #include "extensions/xf86dgastr.h" ! #endif ! #include "apm.h" ! ! /* Driver data structures. */ typedef struct { ! /* ! * This structure defines all of the register-level information ! * that must be stored to define a video mode for this chipset. ! * The 'vgaHWRec' member must be first, and contains all of the ! * standard VGA register information, as well as saved text and ! * font data. ! */ ! vgaHWRec std; /* good old IBM VGA */ ! /* ! * Any other registers or other data that the new chipset needs ! * to be saved should be defined here. The Init/Save/Restore ! * functions will manipulate theses fields. Examples of things ! * that would go here are registers that contain bank select ! * registers, or extended clock select bits, or extensions to ! * the timing registers. Use 'unsigned char' as the type for ! * these registers. ! */ ! unsigned char SR1B; ! unsigned char SR1C; ! unsigned char CR19; ! unsigned char CR1A; ! unsigned char CR1B; ! unsigned char CR1C; ! unsigned char CR1D; ! unsigned char CR1E; ! unsigned char XR80; ! unsigned char XRC0; ! unsigned long XRE8; ! unsigned long XREC; ! unsigned long XRF0; ! unsigned long XRF4; ! unsigned long XR140; ! unsigned short XR144; ! unsigned long XR148; ! unsigned short XR14C; } vgaApmRec, *vgaApmPtr; ! /* Driver functions */ ! static char* ApmIdent(int n); ! static Bool ApmProbe(void); ! static void ApmFbInit(void); ! static void ApmEnterLeave(Bool enter); ! static void ApmRestore(vgaApmPtr restore); ! static void* ApmSave(vgaApmPtr save); ! static Bool ApmInit(DisplayModePtr mode); ! static void ApmAdjust(int x, int y); ! static int ApmValidMode(DisplayModePtr mode, Bool verbose, int flag); ! #ifdef DPMSExtension ! static void ApmDisplayPowerManagementSet(int PowerManagementMode); ! #endif + /* Helper functions */ + static unsigned comp_lmn(unsigned clock); + + /* Bank select functions. These are defined in apm_bank.s */ + void ApmSetRead(); + void ApmSetWrite(); + void ApmSetReadWrite(); + /* * This data structure defines the driver itself. The data structure is * initialized with the functions that make up the driver and some data *************** *** 104,218 **** * that defines how the driver operates. */ vgaVideoChipRec APM = { ! /* ! * Function pointers ! */ ! ApmProbe, ! ApmIdent, ! ApmEnterLeave, ! ApmInit, ! ApmValidMode, ! ApmSave, ! ApmRestore, ! ApmAdjust, ! vgaHWSaveScreen, ! (void (*)())NoopDDA, ! ApmFbInit, ! ApmSetRead, ! ApmSetWrite, ! ApmSetReadWrite, ! /* ! * This is the size of the mapped memory window, usually 64k. ! */ ! 0x10000, ! /* ! * This is the size of a video memory bank for this chipset. ! */ ! 0x10000, ! /* ! * This is the number of bits by which an address is shifted ! * right to determine the bank number for that address. ! */ ! 16, ! /* ! * This is the bitmask used to determine the address within a ! * specific bank. ! */ ! 0xFFFF, ! /* ! * These are the bottom and top addresses for reads inside a ! * given bank. ! */ ! 0x00000, 0x10000, ! /* ! * And corresponding limits for writes. ! */ ! 0x00000, 0x10000, ! /* ! * Whether this chipset supports a single bank register or ! * separate read and write bank registers. ! */ ! FALSE, ! /* ! * If the chipset requires vertical timing numbers to be divided ! * by two for interlaced modes, set this to VGA_DIVIDE_VERT. ! */ ! VGA_DIVIDE_VERT, ! /* ! * This is a dummy initialization for the set of option flags ! * that this driver supports. It gets filled in properly in the ! * probe function, if the probe succeeds (assuming the driver ! * supports any such flags). ! */ ! {0,}, ! /* ! * This determines the multiple to which the virtual width of ! * the display must be rounded for the 256-color server. This ! * will normally be 8, but may be 4 or 16 for some servers. ! */ ! 8, ! /* ! * If the driver includes support for a linear-mapped frame buffer ! * for the detected configuration this should be set to TRUE in the ! * Probe or FbInit function. In most cases it should be FALSE. ! */ ! FALSE, ! /* ! * This is the physical base address of the linear-mapped frame ! * buffer (when used). Set it to 0 when not in use. ! */ ! 0, ! /* ! * This is the size of the linear-mapped frame buffer (when used). ! * Set it to 0 when not in use. ! */ ! 0, ! /* ! * This is TRUE if the driver has support for 16bpp for the detected ! * configuration. It must be set in the Probe function. ! * It most cases it should be FALSE. ! */ ! FALSE, ! /* ! * This is TRUE if the driver has support for 32bpp for the detected ! * configuration. ! */ ! FALSE, ! FALSE, ! /* ! * This is a pointer to a list of builtin driver modes. ! * This is rarely used, and in must cases, set it to NULL ! */ ! NULL, ! /* ! * This is a factor that can be used to scale the raw clocks ! * to pixel clocks. This is rarely used, and in most cases, set ! * it to 1. ! */ ! 1, /* ClockMulFactor */ ! 1 /* ClockDivFactor */ }; /* * This is a convenience macro, so that entries in the driver structure * can simply be dereferenced with 'new->xxx'. --- 152,268 ---- * that defines how the driver operates. */ vgaVideoChipRec APM = { ! /* ! * Function pointers ! */ ! ApmProbe, ! ApmIdent, ! ApmEnterLeave, ! ApmInit, ! ApmValidMode, ! (void*(*)())ApmSave, ! (void(*)())ApmRestore, ! ApmAdjust, ! vgaHWSaveScreen, ! (void (*)())NoopDDA, ! ApmFbInit, ! ApmSetRead, ! ApmSetWrite, ! ApmSetReadWrite, ! /* ! * This is the size of the mapped memory window, usually 64k. ! */ ! 0x10000, ! /* ! * This is the size of a video memory bank for this chipset. ! */ ! 0x10000, ! /* ! * This is the number of bits by which an address is shifted ! * right to determine the bank number for that address. ! */ ! 16, ! /* ! * This is the bitmask used to determine the address within a ! * specific bank. ! */ ! 0xFFFF, ! /* ! * These are the bottom and top addresses for reads inside a ! * given bank. ! */ ! 0x00000, 0x10000, ! /* ! * And corresponding limits for writes. ! */ ! 0x00000, 0x10000, ! /* ! * Whether this chipset supports a single bank register or ! * separate read and write bank registers. ! */ ! FALSE, ! /* ! * If the chipset requires vertical timing numbers to be divided ! * by two for interlaced modes, set this to VGA_DIVIDE_VERT. ! */ ! VGA_DIVIDE_VERT, ! /* ! * This is a dummy initialization for the set of option flags ! * that this driver supports. It gets filled in properly in the ! * probe function, if the probe succeeds (assuming the driver ! * supports any such flags). ! */ ! {{0,}}, ! /* ! * This determines the multiple to which the virtual width of ! * the display must be rounded for the 256-color server. This ! * will normally be 8, but may be 4 or 16 for some servers. ! */ ! 8, ! /* ! * If the driver includes support for a linear-mapped frame buffer ! * for the detected configuration this should be set to TRUE in the ! * Probe or FbInit function. In most cases it should be FALSE. ! */ ! FALSE, ! /* ! * This is the physical base address of the linear-mapped frame ! * buffer (when used). Set it to 0 when not in use. ! */ ! 0, ! /* ! * This is the size of the linear-mapped frame buffer (when used). ! * Set it to 0 when not in use. ! */ ! 0, ! /* ! * This is TRUE if the driver has support for 16bpp for the detected ! * configuration. It must be set in the Probe function. ! * It most cases it should be FALSE. ! */ ! FALSE, ! /* ! * This is TRUE if the driver has support for 32bpp for the detected ! * configuration. ! */ ! FALSE, ! FALSE, ! /* ! * This is a pointer to a list of builtin driver modes. ! * This is rarely used, and in must cases, set it to NULL ! */ ! NULL, ! /* ! * This is a factor that can be used to scale the raw clocks ! * to pixel clocks. This is rarely used, and in most cases, set ! * it to 1. ! */ ! 1, /* ClockMulFactor */ ! 1 /* ClockDivFactor */ }; + + /* * This is a convenience macro, so that entries in the driver structure * can simply be dereferenced with 'new->xxx'. *************** *** 231,361 **** #define VESA 0 #define PCI 1 ! static int apmChip, apmBus, apmRamdac; ! static int apmDacPathWidth, apmMultiplexingThreshold; ! static int apmUse8bitColorComponents; static int apmDisplayableMemory; #define AP6422 0 #define AT24 1 static SymTabRec chipsets[] = { ! { AP6422, "AP6422"}, ! { AT24, "AT24" }, ! { -1, "" }, }; - static SymTabRec ramdacs[] = { - { -1, "" }, - }; - static unsigned dflt_clocks[] = { - 25175, 28322, 36000, 40000, 42000, 44000, 44900, 48000, - 50400, 52800, 57270, 58800, 61600, 64000, 65000, 67200, - 70400, 72000, 75000, 77000, 80000, 88000, 90000, 98000, - 100000, 108000, 118000, 120000, 135000, - }; - static unsigned num_dflt_clocks = sizeof(dflt_clocks) / sizeof(unsigned); - unsigned long apm_xbase; - unsigned char - rdxb(addr) - unsigned addr; - { - wrinx(0x3c4, 0x1d, addr >> 2); - return inb(apm_xbase + (addr & 3)); - } - - unsigned short - rdxw(addr) - unsigned addr; - { - wrinx(0x3c4, 0x1d, addr >> 2); - return inw(apm_xbase + (addr & 2)); - } - - unsigned long - rdxl(addr) - unsigned addr; - { - wrinx(0x3c4, 0x1d, addr >> 2); - return inl(apm_xbase); - } - - void - wrxb(addr, val) - unsigned addr; - unsigned char val; - { - wrinx(0x3c4, 0x1d, addr >> 2); - outb(apm_xbase + (addr & 3), val); - } - - void - wrxw(addr, val) - unsigned addr; - unsigned short val; - { - wrinx(0x3c4, 0x1d, addr >> 2); - outw(apm_xbase + (addr & 2), val); - } - - void - wrxl(addr, val) - unsigned addr; - unsigned long val; - { - wrinx(0x3c4, 0x1d, addr >> 2); - outl(apm_xbase, val); - } - - #define WITHIN(v,c1,c2) (((v) > (c1)) && ((v) < (c2))) - static unsigned - comp_lmn(clock) - unsigned clock; - { - int i, n, m, l, nv, mv; - float fout = (float) clock; - float fvco, d, r; - - for (l = 3; l >= 0; --l) { - fvco = fout * pow(2.0, (double) l); - if (WITHIN(fvco, 125000.0, 250000.0)) - break; - } - r = fvco / 14318.0; - if (l < 0) { - ErrorF("cannot find postscaler value for Fout = %6.2f\n"); - return 0; - } - d = 0.0; - for (nv = 128; nv > 0; --nv) { - if (!WITHIN(fvco / nv, 300.0, 30000.0)) - continue; - mv = (int) rint(nv / r); - if (!WITHIN(mv, 0, 129)) - continue; - if (!WITHIN(14318.0 / mv, 300.0, 30000.0)) - continue; - if (fabs((float) nv / mv - r) > fabs(d - r)) - continue; - n = nv; m = mv; d = (float) nv / mv; - } - if (d == 0.0) { - ErrorF("cannot find appropriate values for Fout = %6.2f\n"); - return 0; - } /* - ErrorF("%6.2f\t%6.2f\t%d\t%d\t%d\n", fout / 1000.0, - (n * 14318.0) / (m * pow(2.0, l) * 1000.0), - n - 1, m - 1, l); - */ - return ((n - 1) << 16) | ((m - 1) << 8) | (l << 2) | (4 << 4); - } - #undef WITHIN - - /* * ApmIdent -- * * Returns the string name for supported chipset 'n'. Most drivers only --- 281,308 ---- #define VESA 0 #define PCI 1 ! static int apmBus; ! int apmChip; static int apmDisplayableMemory; + static int apmDPMS; + static int apmAccelSupported; + u32 apm_xbase; #define AP6422 0 #define AT24 1 + #define AT3D 2 static SymTabRec chipsets[] = { ! { AP6422, "AP6422"}, ! { AT24, "AT24" }, ! { AT3D, "AT3D" }, ! { -1, "" }, }; /* * ApmIdent -- * * Returns the string name for supported chipset 'n'. Most drivers only *************** *** 369,441 **** * cuts down on the number of places errors can creep in. */ static char * ! ApmIdent(n) ! int n; { ! if (chipsets[n].token < 0) ! return NULL; ! else ! return chipsets[n].name; } - /* - * ApmClockSelect -- - * - * This function selects the dot-clock with index 'no'. In most cases - * this is done my setting the correct bits in various registers (generic - * VGA uses two bits in the Miscellaneous Output Register to select from - * 4 clocks). Care must be taken to protect any other bits in these - * registers by fetching their values and masking off the other bits. - * - * This function returns FALSE if the passed index is invalid or if the - * clock can't be set for some reason. - */ - static Bool - ApmClockSelect(no) - int no; - { - static unsigned char save1; - static unsigned long save2, temp1; - unsigned char temp; - switch(no) - { - case CLK_REG_SAVE: - /* - * Here all of the registers that can be affected by - * clock setting should be saved into static variables. - */ - save1 = inb(0x3CC); - save2 = rdxl(0xec); - break; - case CLK_REG_RESTORE: - /* - * Here all the previously saved registers are restored. - */ - outb(0x3C2, save1); - wrxl(0xec, save2); - break; - default: - /* - * These are the generic two low-order bits of the clock select - */ - if (no < 2) { - temp = inb(0x3CC); - outb(0x3C2, ( temp & 0xF3) | ((no << 2) & 0x0C)); - } else { - temp1 = comp_lmn(vga256InfoRec.clock[no]); - if (!temp1) - return FALSE; - temp = inb(0x3CC); - outb(0x3C2, ( temp & 0xF3) | 0x0C); - wrxl(0xec, temp1); - } - } - return(TRUE); - } - - /* * ApmProbe -- * --- 316,331 ---- * cuts down on the number of places errors can creep in. */ static char * ! ApmIdent(int n) { ! if (chipsets[n].token < 0) ! return NULL; ! else ! return chipsets[n].name; } /* * ApmProbe -- * *************** *** 446,587 **** * */ static Bool ! ApmProbe() { - int maxclock8bpp, maxclock16bpp, maxclock32bpp; ! /* ! * Set up I/O ports to be used by this card. Only do the second ! * xf86AddIOPorts() if there are non-standard ports for this ! * chipset. ! */ ! xf86ClearIOPortList(vga256InfoRec.scrnIndex); ! xf86AddIOPorts(vga256InfoRec.scrnIndex, Num_VGA_IOPorts, VGA_IOPorts); ! xf86AddIOPorts(vga256InfoRec.scrnIndex, ! Num_Apm_ExtPorts, Apm_ExtPorts); ! /* ! * First we attempt to figure out if one of the supported chipsets ! * is present. ! */ ! if (vga256InfoRec.chipset) ! { ! /* ! * This is the easy case. The user has specified the ! * chipset in the XF86Config file. All we need to do here ! * is a string comparison against each of the supported ! * names available from the Ident() function. If this ! * driver supports more than one chipset, there would be ! * nested conditionals here (see the Trident and WD drivers ! * for examples). ! */ ! apmChip = xf86StringToToken(chipsets, vga256InfoRec.chipset); ! if (apmChip >= 0) ! ApmEnterLeave(ENTER); ! else ! return FALSE; ! } ! else ! { ! /* ! * OK. We have to actually test the hardware. The ! * EnterLeave() function (described below) unlocks access ! * to registers that may be locked, and for OSs that require ! * it, enables I/O access. So we do this before we probe, ! * even though we don't know for sure that this chipset ! * is present. ! */ ! int i; ! char idstring[] = "Pro642"; ! ApmEnterLeave(ENTER); ! for (i = 0; idstring[i]; ++i) ! if (rdinx(0x3c4, 0x11 + i) != idstring[i]) { ! ApmEnterLeave(LEAVE); ! return(FALSE); ! } ! switch (rdinx(0x3c4, 0x11 +i)) { ! case '0': ! case '2': ! apmChip = AP6422; ! break; ! case '4': ! apmChip = AT24; ! break; ! default: ! ApmEnterLeave(LEAVE); ! return(FALSE); ! } ! vga256InfoRec.chipset = ApmIdent(apmChip); ! } ! /* ! * If the user has specified the amount of memory in the XF86Config ! * file, we respect that setting. ! */ ! if (!vga256InfoRec.videoRam) ! { ! /* ! * Otherwise, do whatever chipset-specific things are ! * necessary to figure out how much memory (in kBytes) is ! * available. ! */ ! vga256InfoRec.videoRam = rdinx(0x3c4, 0x20) * 64; ! } ! if (rdxb(0xca) & 1) ! apmBus = PCI; ! else ! apmBus = VESA; ! /* ! * Again, if the user has specified the clock values in the XF86Config ! * file, we respect those choices. ! */ ! if (!vga256InfoRec.clocks) ! { ! /* ! * This utility function will probe for the clock values. ! * It is passed the number of supported clocks, and a ! * pointer to the clock-select function. ! */ ! /* vgaGetClocks(2, ApmClockSelect); */ ! int i; ! for (i = 0; i < num_dflt_clocks; ++i) ! vga256InfoRec.clock[i] = dflt_clocks[i]; ! vga256InfoRec.clocks = num_dflt_clocks; ! } - vga256InfoRec.maxClock = 135000; ! /* Use linear addressing by default. */ ! if (!OFLG_ISSET(OPTION_NOLINEAR_MODE, &vga256InfoRec.options)) { ! APM.ChipUseLinearAddressing = TRUE; ! if (vga256InfoRec.MemBase != 0) ! APM.ChipLinearBase = ! vga256InfoRec.MemBase; ! else ! if (apmBus == PCI) ! APM.ChipLinearBase = rdxb(0x193) << 24; ! else ! /* VESA local bus. */ ! /* Pray that 2048MB works. */ ! APM.ChipLinearBase = 0x80000000; ! APM.ChipLinearSize = vga256InfoRec.videoRam * 1024; ! APM.ChipHas16bpp = TRUE; ! APM.ChipHas32bpp = TRUE; ! } ! /* ! * Last we fill in the remaining data structures. We specify ! * the chipset name, using the Ident() function and an appropriate ! * index. We set a boolean for whether or not this driver supports ! * banking for the Monochrome server. And we set up a list of all ! * the option flags that this driver can make use of. ! */ ! vga256InfoRec.bankedMono = FALSE; ! OFLG_SET(OPTION_NOLINEAR_MODE, &APM.ChipOptionFlags); ! return TRUE; } /* --- 336,554 ---- * */ static Bool ! ApmProbe(void) { ! xf86ClearIOPortList(vga256InfoRec.scrnIndex); ! xf86AddIOPorts(vga256InfoRec.scrnIndex, Num_VGA_IOPorts, VGA_IOPorts); ! xf86AddIOPorts(vga256InfoRec.scrnIndex, ! Num_Apm_ExtPorts, Apm_ExtPorts); ! /* ! * First we attempt to figure out if one of the supported chipsets ! * is present. ! */ + apmDPMS = FALSE; + apmAccelSupported = FALSE; ! if (vga256InfoRec.chipset) ! { ! /* ! * This is the easy case. The user has specified the ! * chipset in the XF86Config file. All we need to do here ! * is a string comparison against each of the supported ! * names available from the Ident() function. If this ! * driver supports more than one chipset, there would be ! * nested conditionals here (see the Trident and WD drivers ! * for examples). ! */ ! apmChip = xf86StringToToken(chipsets, vga256InfoRec.chipset); ! if (apmChip >= 0) ! ApmEnterLeave(ENTER); ! else ! return FALSE; ! if (apmChip >= AP6422) ! { ! apmDPMS = TRUE; ! apmAccelSupported = TRUE; ! } ! } ! else ! { ! /* ! * OK. We have to actually test the hardware. The ! * EnterLeave() function (described below) unlocks access ! * to registers that may be locked, and for OSs that require ! * it, enables I/O access. So we do this before we probe, ! * even though we don't know for sure that this chipset ! * is present. ! */ ! int i; ! char id_ap6420[] = "Pro6420"; ! char id_ap6422[] = "Pro6422"; ! char id_at24[] = "Pro6424"; ! char id_at3d[] = "ProAT3D"; /* Yeah, the manual could have been ! correct... */ ! char idstring[] = " "; ! ApmEnterLeave(ENTER); ! for (i = 0; i < 7; i++) ! idstring[i] = rdinx(0x3c4, 0x11 + i); ! if (!memcmp(id_ap6420, idstring, 7)) ! { ! apmChip = AP6422; ! apmDPMS = TRUE; ! apmAccelSupported = TRUE; ! } ! else if (!memcmp(id_ap6422, idstring, 7)) ! { ! apmChip = AP6422; ! apmDPMS = TRUE; ! apmAccelSupported = TRUE; ! } ! else if (!memcmp(id_at24, idstring, 7)) ! { ! apmChip = AT24; ! apmDPMS = TRUE; ! apmAccelSupported = TRUE; ! } ! else if (!memcmp(id_at3d, idstring, 7)) ! { ! apmChip = AT3D; ! apmDPMS = TRUE; ! apmAccelSupported = TRUE; ! } ! else ! { ! ApmEnterLeave(LEAVE); ! return(FALSE); ! } ! vga256InfoRec.chipset = ApmIdent(apmChip); ! } ! #ifdef DPMSExtension ! if (apmDPMS) ! vga256InfoRec.DPMSSet = ApmDisplayPowerManagementSet; ! #endif ! ! ! if (RDXB_IOP(0xca) & 1) ! apmBus = PCI; ! else ! apmBus = VESA; ! ! ! switch(apmChip) ! { ! /* These values come from the Manual for AT24 and AT3D ! in the overview of various modes. I've taken the largest ! number for the different modes. Alliance wouldn't ! tell me what the maximum frequency was, so... ! */ ! case AT24: ! switch(vgaBitsPerPixel) ! { ! case 8: ! vga256InfoRec.maxClock = 160000; ! break; ! case 15: ! case 16: ! vga256InfoRec.maxClock = 144000; ! break; ! case 24: ! vga256InfoRec.maxClock = 75000; /* Hmm. */ ! break; ! case 32: ! vga256InfoRec.maxClock = 94500; ! break; ! default: ! return FALSE; ! } ! break; ! case AT3D: ! switch(vgaBitsPerPixel) ! { ! case 8: ! vga256InfoRec.maxClock = 175500; ! break; ! case 15: ! case 16: ! vga256InfoRec.maxClock = 144000; ! break; ! case 24: ! vga256InfoRec.maxClock = 75000; /* Hmm. */ ! break; ! case 32: ! vga256InfoRec.maxClock = 94500; ! break; ! default: ! return FALSE; ! } ! break; ! default: ! vga256InfoRec.maxClock = 135000; ! break; ! } ! ! ! /* ! * If the user has specified the amount of memory in the XF86Config ! * file, we respect that setting. ! */ ! if (!vga256InfoRec.videoRam) ! { ! /* ! * Otherwise, do whatever chipset-specific things are ! * necessary to figure out how much memory (in kBytes) is ! * available. ! */ ! vga256InfoRec.videoRam = rdinx(0x3c4, 0x20) * 64; ! } ! ! /* Use always use linear addressing */ ! APM.ChipUseLinearAddressing = TRUE; ! ! if (vga256InfoRec.MemBase != 0) ! APM.ChipLinearBase = vga256InfoRec.MemBase; ! else ! if (apmBus == PCI) ! APM.ChipLinearBase = RDXB_IOP(0x193) << 24; ! else ! /* VESA local bus. */ ! /* Pray that 2048MB works. */ ! APM.ChipLinearBase = 0x80000000; ! ! APM.ChipLinearSize = vga256InfoRec.videoRam * 1024; ! APM.ChipHas16bpp = TRUE; ! APM.ChipHas32bpp = TRUE; ! ! vga256InfoRec.videoRam -= 34; /* We're going to use the last 34 kilobytes ! for memory mapped registers, host->screen ! bitblts and storage for the hardware ! cursor */ ! ! /* ! * Last we fill in the remaining data structures. We specify ! * the chipset name, using the Ident() function and an appropriate ! * index. We set a boolean for whether or not this driver supports ! * banking for the Monochrome server. And we set up a list of all ! * the option flags that this driver can make use of. ! */ ! ! vga256InfoRec.bankedMono = FALSE; ! OFLG_SET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions); ! OFLG_SET(OPTION_NOACCEL, &APM.ChipOptionFlags); ! OFLG_SET(OPTION_SW_CURSOR, &APM.ChipOptionFlags); ! ! #ifdef XFreeXDGA ! vga256InfoRec.directMode = XF86DGADirectPresent; ! #endif ! ! return TRUE; } /* *************** *** 589,648 **** * enable speedups for the chips that support it */ static void ! ApmFbInit() { ! int offscreen_available; ! if (xf86Verbose && APM.ChipUseLinearAddressing) ! ErrorF("%s %s: %s: Using linear framebuffer at 0x%08X (%s)\n", ! XCONFIG_PROBED, vga256InfoRec.name, ! vga256InfoRec.chipset, APM.ChipLinearBase, ! apmBus == PCI ? "PCI bus" : "VL bus"); ! apmDisplayableMemory = vga256InfoRec.displayWidth ! * vga256InfoRec.virtualY ! * (vgaBitsPerPixel / 8); ! offscreen_available = vga256InfoRec.videoRam * 1024 - ! apmDisplayableMemory; ! if (xf86Verbose) ! ErrorF("%s %s: %s: %d bytes off-screen video memory available\n", ! XCONFIG_PROBED, vga256InfoRec.name, ! vga256InfoRec.chipset, offscreen_available); ! ! /* ! * Currently, the hardware cursor is not supported at 8bpp ! * due to a framebuffer code architecture issue. ! */ ! #ifdef HW_CURSOR ! if (!OFLG_ISSET(OPTION_SW_CURSOR, &vga256InfoRec.options) ! && vgaBitsPerPixel != 8) { ! if (offscreen_available < 1024) ! ErrorF("%s %s: %s: Not enough off-screen video memory for hardware cursor\n", ! XCONFIG_PROBED, vga256InfoRec.name, ! vga256InfoRec.chipset); ! else { ! /* ! * OK, there's at least 1024 bytes available ! * at the end of video memory to store ! * the cursor image, so we can use the hardware ! * cursor. ! */ ! apmCursorWidth = 64; ! apmCursorHeight = 64; ! vgaHWCursor.Initialized = TRUE; ! vgaHWCursor.Init = ApmCursorInit; ! vgaHWCursor.Restore = ApmRestoreCursor; ! vgaHWCursor.Warp = ApmWarpCursor; ! vgaHWCursor.QueryBestSize = ApmQueryBestSize; ! if (xf86Verbose) ! ErrorF("%s %s: %s: Using hardware cursor\n", ! XCONFIG_PROBED, vga256InfoRec.name, ! vga256InfoRec.chipset); ! } ! } ! #endif ! } --- 556,588 ---- * enable speedups for the chips that support it */ static void ! ApmFbInit(void) { ! int offscreen_available; ! if (xf86Verbose && APM.ChipUseLinearAddressing) ! ErrorF("%s %s: %s: Using linear framebuffer at 0x%08X (%s)\n", ! XCONFIG_PROBED, vga256InfoRec.name, ! vga256InfoRec.chipset, APM.ChipLinearBase, ! apmBus == PCI ? "PCI bus" : "VL bus"); ! if (apmAccelSupported && !OFLG_ISSET(OPTION_NOACCEL, &vga256InfoRec.options)) ! ApmAccelInit(); ! if (apmAccelSupported && !OFLG_ISSET(OPTION_SW_CURSOR, &vga256InfoRec.options)) ! { ! apmCursorWidth = 64; ! apmCursorHeight = 64; ! vgaHWCursor.Initialized = TRUE; ! vgaHWCursor.Init = ApmCursorInit; ! vgaHWCursor.Restore = ApmRestoreCursor; ! vgaHWCursor.Warp = ApmWarpCursor; ! vgaHWCursor.QueryBestSize = ApmQueryBestSize; ! if (xf86Verbose) ! ErrorF("%s %s: %s: Using hardware cursor\n", ! XCONFIG_PROBED, vga256InfoRec.name, ! vga256InfoRec.chipset); ! } } *************** *** 657,717 **** * registers again on exit. */ static void ! ApmEnterLeave(enter) ! Bool enter; { ! /* ! * The value of the lock register is saved at the first ! * "Enter" call, restored at a "Leave". This reduces the ! * risk of messing up the registers of another chipset. ! */ ! static int enterCalled = FALSE; ! static int savedSR10; ! unsigned char temp; ! if (enter) ! { ! xf86EnableIOPorts(vga256InfoRec.scrnIndex); ! /* ! * This is a global. The CRTC base address depends on ! * whether the VGA is functioning in color or mono mode. ! * This is just a convenient place to initialize this ! * variable. ! */ ! vgaIOBase = (inb(0x3CC) & 0x01) ? 0x3D0 : 0x3B0; ! /* ! * Here we deal with register-level access locks. This ! * is a generic VGA protection; most SVGA chipsets have ! * similar register locks for their extended registers ! * as well. ! */ ! /* Unprotect CRTC[0-7] */ ! outb(vgaIOBase + 4, 0x11); temp = inb(vgaIOBase + 5); ! outb(vgaIOBase + 5, temp & 0x7F); ! if (enterCalled == FALSE) { ! savedSR10 = rdinx(0x3C4, 0x10); ! apm_xbase = (rdinx(0x3c4, 0x1f) << 8) ! | rdinx(0x3c4, 0x1e); ! enterCalled = TRUE; ! } ! outw(0x3C4, 0x1210); ! } ! else ! { ! /* ! * Here undo what was done above. ! */ ! /* Protect CRTC[0-7] */ ! outb(vgaIOBase + 4, 0x11); temp = inb(vgaIOBase + 5); ! outb(vgaIOBase + 5, (temp & 0x7F) | 0x80); ! wrinx(0x3C4, 0x10, savedSR10); ! xf86DisableIOPorts(vga256InfoRec.scrnIndex); ! } } /* --- 597,661 ---- * registers again on exit. */ static void ! ApmEnterLeave(Bool enter) { ! /* ! * The value of the lock register is saved at the first ! * "Enter" call, restored at a "Leave". This reduces the ! * risk of messing up the registers of another chipset. ! */ ! static int enterCalled = FALSE; ! static int savedSR10; ! unsigned char temp; ! #ifdef XFreeXDGA ! if (vga256InfoRec.directMode&XF86DGADirectGraphics && !enter) ! return; ! #endif ! if (enter) ! { ! xf86EnableIOPorts(vga256InfoRec.scrnIndex); ! /* ! * This is a global. The CRTC base address depends on ! * whether the VGA is functioning in color or mono mode. ! * This is just a convenient place to initialize this ! * variable. ! */ ! vgaIOBase = (inb(0x3CC) & 0x01) ? 0x3D0 : 0x3B0; ! /* ! * Here we deal with register-level access locks. This ! * is a generic VGA protection; most SVGA chipsets have ! * similar register locks for their extended registers ! * as well. ! */ ! /* Unprotect CRTC[0-7] */ ! outb(vgaIOBase + 4, 0x11); temp = inb(vgaIOBase + 5); ! outb(vgaIOBase + 5, temp & 0x7F); ! if (enterCalled == FALSE) { ! savedSR10 = rdinx(0x3C4, 0x10); ! apm_xbase = (rdinx(0x3c4, 0x1f) << 8) ! | rdinx(0x3c4, 0x1e); ! enterCalled = TRUE; ! } ! outw(0x3C4, 0x1210); ! } ! else ! { ! /* ! * Here undo what was done above. ! */ ! /* Protect CRTC[0-7] */ ! outb(vgaIOBase + 4, 0x11); temp = inb(vgaIOBase + 5); ! outb(vgaIOBase + 5, (temp & 0x7F) | 0x80); ! wrinx(0x3C4, 0x10, savedSR10); ! ! xf86DisableIOPorts(vga256InfoRec.scrnIndex); ! } } /* *************** *** 725,776 **** * used when the server enters/changes video modes. The mode definitions * have previously been initialized by the Init() function, below. */ static void ! ApmRestore(restore) ! vgaApmPtr restore; { ! vgaProtect(TRUE); ! /* ! * Whatever code is needed to get things back to bank zero should be ! * placed here. Things should be in the same state as when the ! * Save/Init was done. ! */ ! /* Set aperture index to 0. */ ! wrxw(0xC0, 0); ! /* ! * Write the extended registers first ! */ ! wrinx(0x3C4, 0x1b, restore->SR1B); ! wrinx(0x3C4, 0x1c, restore->SR1C); ! /* Hardware cursor registers. */ ! wrxl(0x140, restore->XR140); ! wrxw(0x144, restore->XR144); ! wrxl(0x148, restore->XR148); ! wrxw(0x14C, restore->XR14C); ! wrinx(vgaIOBase + 4, 0x19, restore->CR19); ! wrinx(vgaIOBase + 4, 0x1a, restore->CR1A); ! wrinx(vgaIOBase + 4, 0x1b, restore->CR1B); ! wrinx(vgaIOBase + 4, 0x1c, restore->CR1C); ! wrinx(vgaIOBase + 4, 0x1d, restore->CR1D); ! wrinx(vgaIOBase + 4, 0x1e, restore->CR1E); ! /* RAMDAC registers. */ ! wrxl(0xec, restore->XREC); ! wrxb(0x80, restore->XR80); ! wrxb(0xc6, restore->XRC6); ! /* ! * This function handles restoring the generic VGA registers. ! */ ! vgaHWRestore((vgaHWPtr)restore); ! vgaProtect(FALSE); } /* --- 669,724 ---- * used when the server enters/changes video modes. The mode definitions * have previously been initialized by the Init() function, below. */ + static void ! ApmRestore(vgaApmPtr restore) { ! vgaProtect(TRUE); ! /* ! * Whatever code is needed to get things back to bank zero should be ! * placed here. Things should be in the same state as when the ! * Save/Init was done. ! */ ! /* Set aperture index to 0. */ ! WRXW_IOP(0xC0, 0); ! /* ! * Write the extended registers first ! */ ! wrinx(0x3C4, 0x1b, restore->SR1B); ! wrinx(0x3C4, 0x1c, restore->SR1C); ! apmMMIO_Init = FALSE; ! /* Hardware cursor registers. */ ! WRXL_IOP(0x140, restore->XR140); ! WRXW_IOP(0x144, restore->XR144); ! WRXL_IOP(0x148, restore->XR148); ! WRXW_IOP(0x14C, restore->XR14C); ! wrinx(vgaIOBase + 4, 0x19, restore->CR19); /* vgaIOBase == 3d0 */ ! wrinx(vgaIOBase + 4, 0x1a, restore->CR1A); ! wrinx(vgaIOBase + 4, 0x1b, restore->CR1B); ! wrinx(vgaIOBase + 4, 0x1c, restore->CR1C); ! wrinx(vgaIOBase + 4, 0x1d, restore->CR1D); ! wrinx(vgaIOBase + 4, 0x1e, restore->CR1E); ! /* RAMDAC registers. */ ! WRXL_IOP(0xe8, restore->XRE8); ! WRXL_IOP(0xec, restore->XREC & ~(1 << 7)); ! WRXL_IOP(0xec, restore->XREC | (1 << 7)); /* Do a PLL resync */ ! WRXB_IOP(0x80, restore->XR80); ! /* ! * This function handles restoring the generic VGA registers. ! */ ! vgaHWRestore((vgaHWPtr)restore); ! ! vgaProtect(FALSE); ! } /* *************** *** 781,825 **** * mask out bits here - just read the registers. */ static void * ! ApmSave(save) ! vgaApmPtr save; { ! /* ! * Whatever code is needed to get back to bank zero goes here. ! */ ! /* Set aperture index to 0. */ ! wrxw(0xC0, 0); ! /* ! * This function will handle creating the data structure and filling ! * in the generic VGA portion. ! */ ! save = (vgaApmPtr)vgaHWSave((vgaHWPtr)save, sizeof(vgaApmRec)); ! save->SR1B = rdinx(0x3C4, 0x1b); ! save->SR1C = rdinx(0x3C4, 0x1c); ! /* Hardware cursor registers. */ ! save->XR140 = rdxl(0x140); ! save->XR144 = rdxw(0x144); ! save->XR148 = rdxl(0x148); ! save->XR14C = rdxw(0x14C); ! save->CR19 = rdinx(vgaIOBase + 4, 0x19); ! save->CR1A = rdinx(vgaIOBase + 4, 0x1A); ! save->CR1B = rdinx(vgaIOBase + 4, 0x1B); ! save->CR1C = rdinx(vgaIOBase + 4, 0x1C); ! save->CR1D = rdinx(vgaIOBase + 4, 0x1D); ! save->CR1E = rdinx(vgaIOBase + 4, 0x1E); ! /* RAMDAC registers. */ ! save->XREC = rdxl(0xec); ! save->XR80 = rdxb(0x80); ! save->XRC6 = rdxb(0xc6); ! return ((void *) save); } /* --- 729,772 ---- * mask out bits here - just read the registers. */ static void * ! ApmSave(vgaApmPtr save) { ! /* ! * Whatever code is needed to get back to bank zero goes here. ! */ ! /* Set aperture index to 0. */ ! WRXW_IOP(0xC0, 0); ! /* ! * This function will handle creating the data structure and filling ! * in the generic VGA portion. ! */ ! save = (vgaApmPtr)vgaHWSave((vgaHWPtr)save, sizeof(vgaApmRec)); ! save->SR1B = rdinx(0x3C4, 0x1b); ! save->SR1C = rdinx(0x3C4, 0x1c); ! /* Hardware cursor registers. */ ! save->XR140 = RDXL_IOP(0x140); ! save->XR144 = RDXW_IOP(0x144); ! save->XR148 = RDXL_IOP(0x148); ! save->XR14C = RDXW_IOP(0x14C); ! save->CR19 = rdinx(vgaIOBase + 4, 0x19); ! save->CR1A = rdinx(vgaIOBase + 4, 0x1A); ! save->CR1B = rdinx(vgaIOBase + 4, 0x1B); ! save->CR1C = rdinx(vgaIOBase + 4, 0x1C); ! save->CR1D = rdinx(vgaIOBase + 4, 0x1D); ! save->CR1E = rdinx(vgaIOBase + 4, 0x1E); ! /* RAMDAC registers. */ ! save->XRE8 = RDXL_IOP(0xe8); ! save->XREC = RDXL_IOP(0xec); ! save->XR80 = RDXB_IOP(0x80); ! return ((void *) save); } /* *************** *** 836,969 **** * (see definition above) is used to simply fill in the structure. */ static Bool ! ApmInit(mode) ! DisplayModePtr mode; { ! /* ! * This will allocate the datastructure and initialize all of the ! * generic VGA registers. ! */ ! if (!vgaHWInit(mode,sizeof(vgaApmRec))) ! return(FALSE); ! /* ! * Here all of the other fields of 'new' get filled in, to ! * handle the SVGA extended registers. It is also allowable ! * to override generic registers whenever necessary. ! * ! */ ! /* ! * The APM chips have a scale factor of 8 for the ! * scanline offset. There are four extended bit in addition ! * to the 8 VGA bits. ! */ ! { ! int offset; ! offset = (vga256InfoRec.displayWidth * ! vga256InfoRec.bitsPerPixel / 8) >> 3; ! new->std.CRTC[0x13] = offset; ! /* Bit 8 resides at CR1C bits 7:4. */ ! new->CR1C = (offset & 0xf00) >> 4; ! } ! /* Set pixel depth. */ ! if (vga256InfoRec.bitsPerPixel == 8) { ! new->XR80 = 0x02; ! new->XRC6 = 0x08; ! } ! if (vga256InfoRec.bitsPerPixel == 16) { ! new->XR80 = 0x0d; ! new->XRC6 = 0x03; ! } ! if (vga256InfoRec.bitsPerPixel == 32) { ! new->XR80 = 0x0f; ! new->XRC6 = vga256InfoRec.displayWidth >= 800 ? 0x0c : 0x04; ! } ! /* ! * Enable VESA Super VGA memory organisation. ! * Also enable Linear Addressing. ! */ ! if (APM.ChipUseLinearAddressing) { ! new->SR1B = 0x24; ! new->SR1C = 0x2d; ! } ! else { ! /* Banking; Map aperture at 0xA0000. */ ! new->SR1B = 0; ! new->SR1C = 0; ! } ! /* Set banking register to zero. */ ! new->XRC0 = 0; ! /* Handle the CRTC overflow bits. */ ! { ! unsigned char val; ! /* Vertical Overflow. */ ! val = 0; ! if ((mode->CrtcVTotal - 2) & 0x400) ! val |= 0x01; ! if ((mode->CrtcVDisplay - 1) & 0x400) ! val |= 0x02; ! /* VBlankStart is equal to VSyncStart + 1. */ ! if (mode->CrtcVSyncStart & 0x400) ! val |= 0x04; ! /* VRetraceStart is equal to VSyncStart + 1. */ ! if (mode->CrtcVSyncStart & 0x400) ! val |= 0x08; ! new->CR1A = val; ! /* Horizontal Overflow. */ ! val = 0; ! if ((mode->CrtcHTotal / 8 - 5) & 0x100) ! val |= 1; ! if ((mode->CrtcHDisplay / 8 - 1) & 0x100) ! val |= 2; ! /* HBlankStart is equal to HSyncStart - 1. */ ! if ((mode->CrtcHSyncStart / 8 - 1) & 0x100) ! val |= 4; ! /* HRetraceStart is equal to HSyncStart. */ ! if ((mode->CrtcHSyncStart / 8) & 0x100) ! val |= 8; ! new->CR1B = val; ! } ! new->CR1E = 1; /* disable autoreset feature */ ! /* ! * A special case - when using an external clock-setting program, ! * this function must not change bits associated with the clock ! * selection. This condition can be checked by the condition: ! * ! * if (new->std.NoClock >= 0) ! * initialize clock-select bits. ! */ ! if (new->std.NoClock >= 0) { ! /* Program clock select. */ ! if (new->std.NoClock < 2) { ! new->std.MiscOutReg &= ~0xC; ! new->std.MiscOutReg |= (new->std.NoClock & 3) << 2; ! } else { ! new->XREC = comp_lmn(vga256InfoRec.clock[new->std.NoClock]); ! if (!new->XREC) ! return FALSE; ! new->std.MiscOutReg |= 0xc; ! } ! } ! /* Set up the RAMDAC registers. */ ! if (vgaBitsPerPixel > 8) ! /* Get rid of white border. */ ! new->std.Attribute[0x11] = 0x00; ! /* ! * Hardware cursor registers. ! * Generally the SVGA server will take care of enabling the ! * cursor after a mode switch. ! */ ! return TRUE; } /* --- 783,943 ---- * (see definition above) is used to simply fill in the structure. */ static Bool ! ApmInit(DisplayModePtr mode) { ! /* ! * This will allocate the datastructure and initialize all of the ! * generic VGA registers. ! */ ! if (!vgaHWInit(mode,sizeof(vgaApmRec))) ! return(FALSE); ! /* ! * Here all of the other fields of 'new' get filled in, to ! * handle the SVGA extended registers. It is also allowable ! * to override generic registers whenever necessary. ! * ! */ ! /* ! * The APM chips have a scale factor of 8 for the ! * scanline offset. There are four extended bit in addition ! * to the 8 VGA bits. ! */ ! { ! int offset; ! offset = (vga256InfoRec.displayWidth * ! vga256InfoRec.bitsPerPixel / 8) >> 3; ! new->std.CRTC[0x13] = offset; ! /* Bit 8 resides at CR1C bits 7:4. */ ! new->CR1C = (offset & 0xf00) >> 4; ! } ! /* Set pixel depth. */ ! switch(vga256InfoRec.bitsPerPixel) ! { ! case 8: ! new->XR80 = 0x02; ! break; ! case 16: ! new->XR80 = 0x0d; ! break; ! case 32: ! new->XR80 = 0x0f; ! break; ! default: ! FatalError("Unsupported bit depth %d\n", vga256InfoRec.bitsPerPixel); ! break; ! } ! /* ! * Enable VESA Super VGA memory organisation. ! * Also enable Linear Addressing. ! */ ! if (APM.ChipUseLinearAddressing) { ! u8 size; ! new->SR1B = 0x00; /* For some reason it doesn't work to enable memory mapped registers here, ! so that is done in apm_accel.c:CheckMMIO_Init() */ ! switch (APM.ChipLinearSize) ! { ! case 0x100000: ! size = 0x00; ! break; ! case 0x200000: ! size = 0x02; ! break; ! case 0x400000: ! size = 0x04; ! break; ! case 0x600000: ! size = 0x06; ! break; ! default: ! ErrorF("Cannot find aperture size for configured amount of video ram\n"); ! return FALSE; ! } ! new->SR1C = size | 0x29; /* 2 means simultaneous access to video ram */ ! /* new->SR1C = size | 0x09; */ ! } ! else { ! /* Banking; Map aperture at 0xA0000. */ ! new->SR1B = 0; ! new->SR1C = 0; ! } ! /* Set banking register to zero. */ ! new->XRC0 = 0; ! /* Handle the CRTC overflow bits. */ ! { ! unsigned char val; ! /* Vertical Overflow. */ ! val = 0; ! if ((mode->CrtcVTotal - 2) & 0x400) ! val |= 0x01; ! if ((mode->CrtcVDisplay - 1) & 0x400) ! val |= 0x02; ! /* VBlankStart is equal to VSyncStart + 1. */ ! if (mode->CrtcVSyncStart & 0x400) ! val |= 0x04; ! /* VRetraceStart is equal to VSyncStart + 1. */ ! if (mode->CrtcVSyncStart & 0x400) ! val |= 0x08; ! new->CR1A = val; ! /* Horizontal Overflow. */ ! val = 0; ! if ((mode->CrtcHTotal / 8 - 5) & 0x100) ! val |= 1; ! if ((mode->CrtcHDisplay / 8 - 1) & 0x100) ! val |= 2; ! /* HBlankStart is equal to HSyncStart - 1. */ ! if ((mode->CrtcHSyncStart / 8 - 1) & 0x100) ! val |= 4; ! /* HRetraceStart is equal to HSyncStart. */ ! if ((mode->CrtcHSyncStart / 8) & 0x100) ! val |= 8; ! new->CR1B = val; ! } ! new->CR1E = 1; /* disable autoreset feature */ ! /* ! * A special case - when using an external clock-setting program, ! * this function must not change bits associated with the clock ! * selection. This condition can be checked by the condition: ! * ! * if (new->std.NoClock >= 0) ! * initialize clock-select bits. ! */ ! if (new->std.NoClock >= 0) { ! /* Program clock select. */ ! new->XREC = comp_lmn(vga256InfoRec.clock[mode->Clock]); ! if (!new->XREC) ! return FALSE; ! new->std.MiscOutReg |= 0xc; ! } ! /* Set up the RAMDAC registers. */ ! if (vgaBitsPerPixel > 8) ! /* Get rid of white border. */ ! new->std.Attribute[0x11] = 0x00; ! ! if (apmChip >= AT3D) ! new->XRE8 = 0x071f01e8; /* Enable 58MHz MCLK (actually 57.3 MHz) ! This is what is used in the Windows drivers. ! The BIOS sets it to 50MHz. */ ! else ! new->XRE8 = RDXL_IOP(0xe8); /* No change */ ! ! /* ! * Hardware cursor registers. ! * Generally the SVGA server will take care of enabling the ! * cursor after a mode switch. ! */ ! ! return TRUE; } /* *************** *** 974,996 **** * virtual window. */ static void ! ApmAdjust(x, y) ! int x, y; { ! int Base = ((y * vga256InfoRec.displayWidth + x) ! * (vgaBitsPerPixel / 8)) >> 2; ! /* ! * These are the generic starting address registers. ! */ ! outw(vgaIOBase + 4, (Base & 0x00FF00) | 0x0C); ! outw(vgaIOBase + 4, ((Base & 0x00FF) << 8) | 0x0D); ! /* ! * Here the high-order bits are masked and shifted, and put into ! * the appropriate extended registers. ! */ ! modinx(vgaIOBase + 4, 0x1c, 0x0f, (Base & 0x0f0000) >> 16); } /* --- 948,970 ---- * virtual window. */ static void ! ApmAdjust(int x, int y) { ! int Base = ((y * vga256InfoRec.displayWidth + x) ! * (vgaBitsPerPixel / 8)) >> 2; ! /* ! * These are the generic starting address registers. ! */ ! outw(vgaIOBase + 4, (Base & 0x00FF00) | 0x0C); ! outw(vgaIOBase + 4, ((Base & 0x00FF) << 8) | 0x0D); ! /* ! * Here the high-order bits are masked and shifted, and put into ! * the appropriate extended registers. ! */ ! modinx(vgaIOBase + 4, 0x1c, 0x0f, (Base & 0x0f0000) >> 16); ! } /* *************** *** 998,1016 **** * */ static int ! ApmValidMode(mode, verbose, flag) ! DisplayModePtr mode; ! Bool verbose; ! int flag; { ! /* Check for CRTC timing bits overflow. */ ! if (mode->VTotal > 2047) { ! if (verbose) ! ErrorF("%s %s: %s: Vertical mode timing overflow (%d)\n", ! XCONFIG_PROBED, vga256InfoRec.name, ! vga256InfoRec.chipset, mode->VTotal); ! return MODE_BAD; ! } ! return MODE_OK; } --- 972,1150 ---- * */ static int ! ApmValidMode(DisplayModePtr mode, Bool verbose, int flag) { ! /* Check for CRTC timing bits overflow. */ ! if (mode->VTotal > 2047) { ! if (verbose) ! ErrorF("%s %s: %s: Vertical mode timing overflow (%d)\n", ! XCONFIG_PROBED, vga256InfoRec.name, ! vga256InfoRec.chipset, mode->VTotal); ! return MODE_BAD; ! } ! return MODE_OK; } + + + #ifdef DPMSExtension + /* + * DPMS Control registers + * + */ + + static void + ApmDisplayPowerManagementSet(int PowerManagementMode) + { + unsigned char dpmsreg, tmp; + + dpmsreg = 0; + if (!xf86VTSema) return; + switch (PowerManagementMode) { + case DPMSModeOn: + /* Screen: On; HSync: On, VSync: On */ + dpmsreg = 0x00; + break; + case DPMSModeStandby: + /* Screen: Off; HSync: Off, VSync: On */ + dpmsreg = 0x01; + break; + case DPMSModeSuspend: + /* Screen: Off; HSync: On, VSync: Off */ + dpmsreg = 0x02; + break; + case DPMSModeOff: + /* Screen: Off; HSync: Off, VSync: Off */ + dpmsreg = 0x03; + break; + } + tmp = RDXB_IOP(0xD0); + tmp = (tmp & 0xfc) | dpmsreg; + WRXB_IOP(0xD0, tmp); + } + #endif + + #define WITHIN(v,c1,c2) (((v) >= (c1)) && ((v) <= (c2))) + + static unsigned + comp_lmn(unsigned clock) + { + int n, m, l, f; + double fvco; + double fout; + double fmax; + double fref; + double fvco_goal; + double k, c; + FILE* fp; + + if (apmChip >= AT3D) + fmax = 400000.0; + else + fmax = 250000.0; + + fref = 14318.0; + + for (m = 1; m <= 5; m++) + { + for (l = 3; l >= 0; l--) + { + for (n = 8; n <= 127; n++) + { + fout = ((double)(n + 1) * fref)/((double)(m + 1) * (1 << l)); + fvco_goal = (double)clock * (double)(1 << l); + fvco = fout * (double)(1 << l); + if (!WITHIN(fvco, 0.995*fvco_goal, 1.005*fvco_goal)) + continue; + if (!WITHIN(fvco, 125000.0, fmax)) + continue; + if (!WITHIN(fvco / (double)(n+1), 300.0, 300000.0)) + continue; + if (!WITHIN(fref / (double)(m+1), 300.0, 300000.0)) + continue; + + /* The following formula was empirically derived by + matching a number of fvco values with acceptable + values of f. + + (fvco can be 125MHz - 400MHz on AT3D) + (fvco can be 125MHz - 250MHz on AT24/AP6422) + + The table that was measured up follows: + + AT3D + + fvco f + (125) (x-7) guess + 200 5-7 + 219 4-7 + 253 3-6 + 289 2-5 + 320 0-4 + (400) (0-x) guess + + AT24 + + fvco f + 126 7 + 200 5-7 + 211 4-7 + + AP6422 + + fvco f + 126 7 + 169 5-7 + 200 4-5 + 211 4-5 + + From this, a function "f = k * fvco + c" was derived. + + For AT3D, this table was measured with MCLK == 50MHz. + The driver has since been set to use MCLK == 57.3MHz for, + but I don't think that makes a difference here. + */ + + if (apmChip >= AT24) + { + k = 7.0 / (175.0 - 380.0); + c = -k * 380.0; + f = (int)(k * fvco/1000.0 + c + 0.5); + if (f > 7) f = 7; + if (f < 0) f = 0; + } + + if (apmChip < AT24) /* i.e AP6422 */ + { + c = (211.0*6.0-169.0*4.5)/(211.0-169.0); + k = (4.5-c)/211.0; + f = (int)(k * fvco/1000.0 + c + 0.5); + if (f > 7) f = 7; + if (f < 0) f = 0; + } + + #if 0 + fp = fopen("/tmp/f","r"); + if (!fp) + { + ErrorF("Cannot open /tmp/f\n"); + return 0; + } + fscanf(fp,"%d",&f); + fclose(fp); + ErrorF("%6.2f\t%6.2f\t%d\t%d\t%d\t%.2f\t%d\n", (double)clock, fout, + n, m, l, fvco, f); + #endif + + return (n << 16) | (m << 8) | (l << 2) | (f << 4); + } + } + } + ErrorF("%s %s: %s: Cannot find register values for clock %6.2f MHz. " + "Please use a (slightly) different clock.\n", + XCONFIG_PROBED, vga256InfoRec.name, vga256InfoRec.chipset, + (double)clock / 1000.0); + return 0; + } + + *** ./programs/Xserver/hw/xfree86/vga256/drivers/ati/Imakefile@@/PUBLIC-LATEST Sat Jul 19 10:32:07 1997 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/Imakefile Fri Mar 6 16:44:35 1998 *************** *** 1,23 **** ! XCOMM $TOG: Imakefile /main/8 1997/07/19 10:32:09 kaleb $ - XCOMM $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/Imakefile,v 3.8 1996/12/23 06:56:08 dawes Exp $ #include <Server.tmpl> ! SRCS = ati_driver.c ati_bank.s ! OBJS = ati_driver.o ati_bank.o #if XF86LinkKit INCLUDES = -I. -I../../../include -I../../../include/X11 -I../.. #else INCLUDES = -I. -I$(XF86COMSRC) -I$(XF86HWSRC) -I$(XF86OSSRC) -I$(XF86SRC) \ ! -I../../vga -I$(SERVERSRC)/include -I$(XINCLUDESRC) #endif #if MakeHasPosixVariableSubstitutions SubdirLibraryRule($(OBJS)) #endif --- 1,63 ---- ! XCOMM $TOG: Imakefile /main/9 1998/03/06 16:46:13 kaleb $ + XCOMM $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/Imakefile,v 3.8.2.2 1998/02/22 01:28:26 robin Exp $ + XCOMM + XCOMM Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + XCOMM + XCOMM Permission to use, copy, modify, distribute, and sell this software and + XCOMM its documentation for any purpose is hereby granted without fee, provided + XCOMM that the above copyright notice appear in all copies and that both that + XCOMM copyright notice and this permission notice appear in supporting + XCOMM documentation, and that the name of Marc Aurele La France not be used in + XCOMM advertising or publicity pertaining to distribution of the software + XCOMM without specific, written prior permission. Marc Aurele La France makes + XCOMM no representations about the suitability of this software for any + XCOMM purpose. It is provided "as-is" without express or implied warranty. + XCOMM + XCOMM MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS + XCOMM SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND + XCOMM FITNESS. IN NO EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY + XCOMM SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER + XCOMM RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF + XCOMM CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + XCOMM CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + XCOMM #include <Server.tmpl> ! #ifdef ATIDriverCCOptions ! CCOPTIONS = ATIDriverCCOptions ! #endif ! SRCS = ati.c atiadapter.c atiadjust.c atibank.c atibanks.s atibus.c atichip.c \ ! aticlock.c aticmap.c aticonsole.c aticrtc.c atidac.c atidsp.c \ ! atifbinit.c atigetmode.c atiident.c atiio.c atimach64.c atiprint.c \ ! atiprobe.c atireset.c atiscrinit.c atiutil.c ativalid.c ativga.c \ ! atividmem.c atiwonder.c + OBJS = ati.o atiadapter.o atiadjust.o atibank.o atibanks.o atibus.o atichip.o \ + aticlock.o aticmap.o aticonsole.o aticrtc.o atidac.o atidsp.o \ + atifbinit.o atigetmode.o atiident.o atiio.o atimach64.o atiprint.o \ + atiprobe.o atireset.o atiscrinit.o atiutil.o ativalid.o ativga.o \ + atividmem.o atiwonder.o + #if XF86LinkKit INCLUDES = -I. -I../../../include -I../../../include/X11 -I../.. #else INCLUDES = -I. -I$(XF86COMSRC) -I$(XF86HWSRC) -I$(XF86OSSRC) -I$(XF86SRC) \ ! -I$(XF86SRC)/vga256/vga -I$(SERVERSRC)/include -I$(SERVERSRC)/cfb \ ! -I$(SERVERSRC)/mfb -I$(SERVERSRC)/mi -I$(XINCLUDESRC) #endif + #if XF86Vga2Banked + MONODEFS = -DBANKEDMONOVGA + #endif + + DEFINES = -DPSZ=8 $(MONODEFS) + #if MakeHasPosixVariableSubstitutions SubdirLibraryRule($(OBJS)) #endif *************** *** 26,37 **** NormalRelocatableTarget(ati_drv,$(OBJS)) - ObjectFromSpecialAsmSource(ati_bank,bank,NullParameter) - - InstallLinkKitNonExecFile(ati_driver.c,$(LINKKITDIR)/drivers/vga256/ati) - InstallLinkKitNonExecFile(bank.s,$(LINKKITDIR)/drivers/vga256/ati) - InstallLinkKitNonExecFile(regati.h,$(LINKKITDIR)/drivers/vga256/ati) InstallLinkKitNonExecFile(Imakefile,$(LINKKITDIR)/drivers/vga256/ati) DependTarget() ! --- 66,131 ---- NormalRelocatableTarget(ati_drv,$(OBJS)) InstallLinkKitNonExecFile(Imakefile,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(ati.c,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(ati.h,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(atiadapter.c,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(atiadapter.h,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(atiadjust.c,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(atiadjust.h,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(atibank.c,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(atibank.h,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(atibanks.s,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(atibus.c,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(atibus.h,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(atichip.c,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(atichip.h,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(aticlock.c,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(aticlock.h,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(aticmap.c,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(aticmap.h,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(aticonsole.c,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(aticonsole.h,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(aticrtc.c,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(aticrtc.h,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(atidac.c,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(atidac.h,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(atidepth.h,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(atidsp.c,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(atidsp.h,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(atifbinit.c,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(atifbinit.h,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(atigetmode.c,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(atigetmode.h,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(atiident.c,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(atiident.h,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(atiio.c,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(atiio.h,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(atimach64.c,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(atimach64.h,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(atimono.h,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(atiprint.c,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(atiprint.h,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(atiprobe.c,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(atiprobe.h,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(atiproto.h,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(atiregs.h,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(atireset.c,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(atireset.h,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(atiscrinit.c,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(atiscrinit.h,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(atiutil.c,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(atiutil.h,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(ativalid.c,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(ativalid.h,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(ativersion.h,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(ativga.c,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(ativga.h,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(atividmem.c,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(atividmem.h,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(atiwonder.c,$(LINKKITDIR)/drivers/vga256/ati) + InstallLinkKitNonExecFile(atiwonder.h,$(LINKKITDIR)/drivers/vga256/ati) + #ifndef OS2Architecture DependTarget() ! #endif *** /dev/null Tue Jun 30 11:48:23 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atiadapter.c Fri Mar 6 16:44:48 1998 *************** *** 0 **** --- 1,52 ---- + /* $TOG: atiadapter.c /main/1 1998/03/06 16:46:26 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atiadapter.c,v 1.1.2.1 1998/02/01 16:41:39 robin Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + #include "atiadapter.h" + + /* + * Adapter-related definitions. + */ + CARD8 ATIAdapter = ATI_ADAPTER_NONE; + CARD8 ATIVGAAdapter = ATI_ADAPTER_NONE; + const char *ATIAdapterNames[] = + { + "Unknown", + "ATI EGA Wonder800", + "ATI EGA Wonder800+", + "IBM VGA or compatible", + "ATI VGA Basic16", + "ATI VGA Wonder V3", + "ATI VGA Wonder V4", + "ATI VGA Wonder V5", + "ATI VGA Wonder+", + "ATI VGA Wonder XL or XL24", + "ATI VGA Wonder VLB or PCI", + "IBM 8514/A or compatible", + "ATI Mach8", + "ATI Mach32", + "ATI Mach64" + }; *** /dev/null Tue Jun 30 11:48:24 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atiadapter.h Fri Mar 6 16:44:52 1998 *************** *** 0 **** --- 1,55 ---- + /* $TOG: atiadapter.h /main/1 1998/03/06 16:46:29 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atiadapter.h,v 1.1.2.1 1998/02/01 16:41:39 robin Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + #ifndef ___ATIADAPTER_H___ + #define ___ATIADAPTER_H___ 1 + + #include "Xmd.h" + + /* + * Adapter-related definitions. + */ + #define ATI_ADAPTER_NONE 0 + #define ATI_ADAPTER_EGA 1 + #define ATI_ADAPTER_EGA_PLUS 2 + #define ATI_ADAPTER_VGA 3 + #define ATI_ADAPTER_BASIC 4 + #define ATI_ADAPTER_V3 5 + #define ATI_ADAPTER_V4 6 + #define ATI_ADAPTER_V5 7 + #define ATI_ADAPTER_PLUS 8 + #define ATI_ADAPTER_XL 9 + #define ATI_ADAPTER_NONISA 10 + #define ATI_ADAPTER_8514A 11 + #define ATI_ADAPTER_MACH8 12 + #define ATI_ADAPTER_MACH32 13 + #define ATI_ADAPTER_MACH64 14 + extern CARD8 ATIAdapter; + extern CARD8 ATIVGAAdapter; + extern const char *ATIAdapterNames[]; + + #endif /* ___ATIADAPTER_H___ */ *** /dev/null Tue Jun 30 11:48:25 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atiadjust.c Fri Mar 6 16:44:56 1998 *************** *** 0 **** --- 1,198 ---- + /* $TOG: atiadjust.c /main/1 1998/03/06 16:46:33 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atiadjust.c,v 1.1.2.1 1998/02/01 16:41:40 robin Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + #include "atiadjust.h" + #include "atichip.h" + #include "aticonsole.h" + #include "aticrtc.h" + #include "atidepth.h" + #include "atiio.h" + + #ifdef XFreeXDGA + # define _XF86DGA_SERVER_ + # include "extensions/xf86dga.h" + #endif + + /* + * The display start address is expressed in units of 32-bit (VGA) or 64-bit + * (accelerator) words where all planar modes are considered as 4bpp modes. + * These functions ensure the start address does not exceed architectural + * limits. Also, to avoid colour changes while panning, these 32-bit or 64-bit + * boundaries may not fall within a pixel. + */ + + static int ATIAdjustDepth; + static unsigned long ATIAdjustMask; + static int ATIAdjustMaxX, + ATIAdjustMaxY; + + /* + * ATIAjustInit -- + * + * This function calculates values needed to speed up the setting of the + * display start address. + */ + void + ATIAdjustInit(void) + { + unsigned long MaxBase = 0; + + ATIAdjustDepth = (vga256InfoRec.bitsPerPixel + 7) >> 3; + + ATIAdjustMask = 64; + while (ATIAdjustMask % (unsigned long)ATIAdjustDepth) + ATIAdjustMask += 64; + ATIAdjustMask = + ~(((ATIAdjustMask / (unsigned long)ATIAdjustDepth) >> 3) - 1); + + switch (ATICRTC) + { + case ATI_CRTC_VGA: + if (ATIChip >= ATI_CHIP_264CT) + { + MaxBase = GetBits(CRTC_OFFSET_VGA, CRTC_OFFSET_VGA) << 2; + if (ATIUsingPlanarModes) + MaxBase <<= 1; + } + else if (!ATIChipHasVGAWonder) + MaxBase = 0xFFFFU << 3; + else if (ATIChip <= ATI_CHIP_28800_6) + MaxBase = 0x3FFFFU << 3; + else /* Mach32 & Mach64 */ + MaxBase = 0xFFFFFU << 3; + break; + + case ATI_CRTC_MACH64: + MaxBase = GetBits(CRTC_OFFSET, CRTC_OFFSET) << 3; + break; + } + + MaxBase = (MaxBase / (unsigned long)ATIAdjustDepth) | ~ATIAdjustMask; + + ATIAdjustMaxX = MaxBase % vga256InfoRec.displayWidth; + ATIAdjustMaxY = MaxBase / vga256InfoRec.displayWidth; + } + + /* + * ATIAdjust -- + * + * This function is used to initialize the SVGA Start Address - the first + * displayed location in video memory. This is used to implement the virtual + * window. + */ + void + ATIAdjust(int x, int y) + { + int Base; + + /* + * Assume the caller has already done its homework in ensuring the physical + * screen is still contained in the virtual resolution. + */ + if (y >= ATIAdjustMaxY) + { + y = ATIAdjustMaxY; + if (x > ATIAdjustMaxX) + y--; + } + + Base = ((((y * vga256InfoRec.displayWidth) + x) & ATIAdjustMask) * + ATIAdjustDepth) >> 3; + + /* Unlock registers */ + ATIEnterLeave(ENTER); + + if ((ATICRTC == ATI_CRTC_VGA) && (ATIChip < ATI_CHIP_264CT)) + { + PutReg(CRTX(vgaIOBase), 0x0CU, GetByte(Base, 1)); + PutReg(CRTX(vgaIOBase), 0x0DU, GetByte(Base, 0)); + + if (ATIChipHasVGAWonder) + { + if (ATIChip <= ATI_CHIP_18800_1) + ATIModifyExtReg(0xB0U, -1, 0x3FU, Base >> 10); + else + { + ATIModifyExtReg(0xB0U, -1, 0xBFU, Base >> 10); + ATIModifyExtReg(0xA3U, -1, 0xEFU, Base >> 13); + + /* + * I don't know if this also applies to Mach64's, but give it a + * shot... + */ + if (ATIChip >= ATI_CHIP_68800) + ATIModifyExtReg(0xADU, -1, 0xF3U, Base >> 16); + } + } + } + else + { + /* + * On integrated controllers, there is only one set of CRTC control + * bits, many of which are simultaneously accessible through both VGA + * and accelerator I/O ports. Given VGA's architectural limitations, + * setting the CRTC's offset register to more than 256k needs to be + * done through the accelerator port. + */ + if (ATIUsingPlanarModes) + { + outl(ATIIOPortCRTC_OFF_PITCH, + SetBits(vga256InfoRec.displayWidth >> 4, CRTC_PITCH) | + SetBits(Base, CRTC_OFFSET)); + } + else + { + if (ATICRTC == ATI_CRTC_VGA) + Base <<= 1; /* LSBit must be zero */ + outl(ATIIOPortCRTC_OFF_PITCH, + SetBits(vga256InfoRec.displayWidth >> 3, CRTC_PITCH) | + SetBits(Base, CRTC_OFFSET)); + } + } + + # ifdef XFreeXDGA + if (!ATIUsing1bppModes && + (vga256InfoRec.directMode & XF86DGADirectGraphics)) + switch (ATICRTC) + { + case ATI_CRTC_VGA: + /* Wait until vertical retrace is in progress */ + while (inb(GENS1(vgaIOBase)) & 0x08U); + while (!(inb(GENS1(vgaIOBase)) & 0x08U)); + break; + + case ATI_CRTC_MACH64: + /* Wait until vertical retrace is in progress */ + while (inb(ATIIOPortCRTC_INT_CNTL) & CRTC_VBLANK); + while (!(inb(ATIIOPortCRTC_INT_CNTL) & CRTC_VBLANK)); + break; + + default: + break; + } + # endif + } *** /dev/null Tue Jun 30 11:48:26 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atiadjust.h Fri Mar 6 16:44:59 1998 *************** *** 0 **** --- 1,36 ---- + /* $TOG: atiadjust.h /main/1 1998/03/06 16:46:37 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atiadjust.h,v 1.1.2.1 1998/02/01 16:41:40 robin Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + #ifndef ___ATIADJUST_H___ + #define ___ATIADJUST_H___ 1 + + #include "atiproto.h" + + extern void ATIAdjustInit FunctionPrototype((void)); + extern void ATIAdjust FunctionPrototype((int, int)); + + #endif /* ___ATIADJUST_H___ */ *** /dev/null Tue Jun 30 11:48:28 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atibanks.s Fri Mar 6 16:45:12 1998 *************** *** 0 **** --- 1,333 ---- + /* $TOG: atibanks.s /main/1 1998/03/06 16:46:49 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atibanks.s,v 1.1.2.1 1998/02/01 16:48:32 robin Exp $ */ + /* + * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany. + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Thomas Roell not be used in advertising or publicity + * pertaining to distribution of the software without specific, written prior + * permission. Thomas Roell makes no representations about the suitability of + * this software for any purpose. It is provided "as is" without express or + * implied warranty. + * + * THOMAS ROELL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT + * SHALL THOMAS ROELL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS + * ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS + * SOFTWARE. + * + * Author: Thomas Roell, roell@informatik.tu-muenchen.de + * + * These are low-level (S)VGA bank switching routines. The segment to switch + * to is passed via %eax. Only %eax and %edx may be used without saving the + * original contents. + * + * WHY ASSEMBLY LANGUAGE ??? + * + * These routines must be callable by other assembly routines. But I don't + * want to have the overhead of pushing and poping the normal stack frame. + * + * Enhancements to support most VGA Wonder cards (including Plus and XL) + * by Doug Evans, dje@sspiff.UUCP. + * ALL DISCLAIMERS APPLY TO MY ADDITIONS AS WELL. + * + * Changes to enhance support for V3, Mach32 and Mach64 adapters + * by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * ALL DISCLAIMERS APPLY TO THESE CHANGES ALSO. + * + * V3 adapters use a 18800 chip and are single-banked. Bank selection is done + * with bits 1-4 of extended register 1CE, index B2. + * + * V4 and V5 adapters have the 18800-1 chip. Plus and XL adapters have the + * 28800 chip. Page selection is done with Extended Register 1CE, Index B2. + * The format is: + * + * D7-D5 = Read page select bits 2-0 + * D4 = Reserved (18800-1) + * D4 = Page select bit 3 (28800) + * D3-D1 = Page select bits 2-0 + * D0 = Reserved (18800-1) + * D0 = Read page select bit 3 (28800) + * + * For 18800-1, 28800, 68800 and 88800 adapters, a shadow of this register is + * held in memory (ATIB2Reg) to improve speed. + * + * Also, for those adapters with more than 1M of video memory (such as some + * Mach32's), additional page select bits are defined in Extended Register 1CE, + * Index AE, as follows: + * + * D7-D4 = Reserved + * D3-D2 = Read page select bits 5-4 + * D1-D0 = Page select bits 5-4 + * + * This module also supplies banking functions for use with a Mach64's small + * dual paged apertures. These functions are used to emulate a standard VGA + * aperture. + */ + + #include "assyntax.h" + + FILE("atibanks.s") + AS_BEGIN + + SEG_TEXT + + /* + * Start with an interface routine to allow calling the banking functions + * directly from C code. + */ + + ALIGNTEXT4 + GLOBL GLNAME(ATISelectBank) + GLNAME(ATISelectBank): + PUSH_L (EAX) + MOV_L (REGOFF(8,ESP),EAX) + PUSH_L (EDX) + MOV_L (CONTENT(GLNAME(ATISelectBankFunction)),EDX) + CALL (CODEPTR(EDX)) + POP_L (EDX) + POP_L (EAX) + RET + + /* + * The functions used with all controllers in the 28800, 68800 and 88800 + * series. + */ + + ALIGNTEXT4 + GLOBL GLNAME(ATISetRead) + GLNAME(ATISetRead): + SHL_L (CONST(12),EAX) + SHR_W (CONST(12),AX) + MOV_B (CONTENT(GLNAME(ATIB2Reg)),AH) + AND_B (CONST(0x1E),AH) + ROR_B (CONST(3),AL) + OR_B (AL,AH) + MOV_B (AH,CONTENT(GLNAME(ATIB2Reg))) + MOV_W (CONTENT(GLNAME(ATIIOPortVGAWonder)),DX) + MOV_B (CONST(0xB2),AL) + OUT_W + SHR_L (CONST(6),EAX) + AND_B (CONST(0x0C),AH) + MOV_B (CONST(0xAE),AL) + OUT_B + INC_W (DX) + IN_B + AND_B (CONST(0xF3),AL) + OR_B (AL,AH) + DEC_W (DX) + MOV_B (CONST(0xAE),AL) + OUT_W + RET + + ALIGNTEXT4 + GLOBL GLNAME(ATISetWrite) + GLNAME(ATISetWrite): + SHL_L (CONST(12),EAX) + SHR_W (CONST(12),AX) + MOV_B (CONTENT(GLNAME(ATIB2Reg)),AH) + AND_B (CONST(0xE1),AH) + SHL_B (CONST(1),AL) + OR_B (AL,AH) + MOV_B (AH,CONTENT(GLNAME(ATIB2Reg))) + MOV_W (CONTENT(GLNAME(ATIIOPortVGAWonder)),DX) + MOV_B (CONST(0xB2),AL) + OUT_W + SHR_L (CONST(8),EAX) + AND_B (CONST(0x03),AH) + MOV_B (CONST(0xAE),AL) + OUT_B + INC_W (DX) + IN_B + AND_B (CONST(0xFC),AL) + OR_B (AL,AH) + DEC_W (DX) + MOV_B (CONST(0xAE),AL) + OUT_W + RET + + ALIGNTEXT4 + GLOBL GLNAME(ATISetReadWrite) + GLNAME(ATISetReadWrite): + SHL_L (CONST(12),EAX) + SHR_W (CONST(12),AX) + MOV_B (AL,AH) + SHL_B (CONST(1),AH) + ROR_B (CONST(3),AL) + OR_B (AL,AH) + MOV_B (AH,CONTENT(GLNAME(ATIB2Reg))) + MOV_W (CONTENT(GLNAME(ATIIOPortVGAWonder)),DX) + MOV_B (CONST(0xB2),AL) + OUT_W + SHR_L (CONST(8),EAX) + AND_B (CONST(0x03),AH) + MOV_B (AH,AL) + SHL_B (CONST(2),AL) + OR_B (AL,AH) + MOV_B (CONST(0xAE),AL) + OUT_B + INC_W (DX) + IN_B + AND_B (CONST(0xF0),AL) + OR_B (AL,AH) + DEC_W (DX) + MOV_B (CONST(0xAE),AL) + OUT_W + RET + + /* + * The functions used for 18800-1 chips. + */ + + ALIGNTEXT4 + GLOBL GLNAME(ATIV4V5SetRead) + GLNAME(ATIV4V5SetRead): + AND_L (CONST(0x0F),EAX) + MOV_B (CONTENT(GLNAME(ATIB2Reg)),AH) + AND_B (CONST(0x1E),AH) + ROR_B (CONST(3),AL) + OR_B (AL,AH) + MOV_B (AH,CONTENT(GLNAME(ATIB2Reg))) + MOV_W (CONTENT(GLNAME(ATIIOPortVGAWonder)),DX) + MOV_B (CONST(0xB2),AL) + OUT_W + RET + + ALIGNTEXT4 + GLOBL GLNAME(ATIV4V5SetWrite) + GLNAME(ATIV4V5SetWrite): + AND_L (CONST(0x0F),EAX) + MOV_B (CONTENT(GLNAME(ATIB2Reg)),AH) + AND_B (CONST(0xE1),AH) + SHL_B (CONST(1),AL) + OR_B (AL,AH) + MOV_B (AH,CONTENT(GLNAME(ATIB2Reg))) + MOV_W (CONTENT(GLNAME(ATIIOPortVGAWonder)),DX) + MOV_B (CONST(0xB2),AL) + OUT_W + RET + + ALIGNTEXT4 + GLOBL GLNAME(ATIV4V5SetReadWrite) + GLNAME(ATIV4V5SetReadWrite): + AND_L (CONST(0x0F),EAX) + MOV_B (AL,AH) + SHL_B (CONST(1),AH) + ROR_B (CONST(3),AL) + OR_B (AL,AH) + MOV_B (AH,CONTENT(GLNAME(ATIB2Reg))) + MOV_W (CONTENT(GLNAME(ATIIOPortVGAWonder)),DX) + MOV_B (CONST(0xB2),AL) + OUT_W + RET + + /* + * The function(s) used for 18800 chips. + */ + + ALIGNTEXT4 + GLOBL GLNAME(ATIV3SetRead) + GLOBL GLNAME(ATIV3SetWrite) + GLOBL GLNAME(ATIV3SetReadWrite) + GLNAME(ATIV3SetRead): + GLNAME(ATIV3SetWrite): + GLNAME(ATIV3SetReadWrite): + AND_L (CONST(0x0F),EAX) + SHL_B (CONST(1),AL) + MOV_B (AL,AH) + MOV_B (CONST(0xB2),AL) + MOV_W (CONTENT(GLNAME(ATIIOPortVGAWonder)),DX) + OUT_B + INC_W (DX) + IN_B + AND_B (CONST(0xE1),AL) + OR_B (AL,AH) + DEC_W (DX) + MOV_B (CONST(0xB2),AL) + OUT_W + RET + + /* + * The functions used with a Mach64's small dual paged apertures. There are + * two sets of these: one for planar pixel modes and one for packed pixel + * modes. They are both always compiled in because the video mode on server + * entry and the one(s) used by the server itself are not necessarily both + * planar or both packed. + */ + + #define ATIMach64MassagePackedBankNumber \ + AND_W (CONST(0x7F),AX) ; \ + SHL_W (CONST(1),AX) ; \ + MOV_W (AX,DX) ; \ + INC_W (AX) ; \ + SHL_L (CONST(16),EAX) ; \ + MOV_W (DX,AX) + + ALIGNTEXT4 + GLOBL GLNAME(ATIMach64SetReadPacked) + GLNAME(ATIMach64SetReadPacked): + ATIMach64MassagePackedBankNumber + MOV_W (CONTENT(GLNAME(ATIIOPortMEM_VGA_RP_SEL)),DX) + OUT_L + RET + + ALIGNTEXT4 + GLOBL GLNAME(ATIMach64SetWritePacked) + GLNAME(ATIMach64SetWritePacked): + ATIMach64MassagePackedBankNumber + MOV_W (CONTENT(GLNAME(ATIIOPortMEM_VGA_WP_SEL)),DX) + OUT_L + RET + + ALIGNTEXT4 + GLOBL GLNAME(ATIMach64SetReadWritePacked) + GLNAME(ATIMach64SetReadWritePacked): + ATIMach64MassagePackedBankNumber + MOV_W (CONTENT(GLNAME(ATIIOPortMEM_VGA_RP_SEL)),DX) + OUT_L + MOV_W (CONTENT(GLNAME(ATIIOPortMEM_VGA_WP_SEL)),DX) + OUT_L + RET + + #define ATIMach64MassagePlanarBankNumber \ + AND_W (CONST(0x1F),AX) ; \ + SHL_W (CONST(1),AX) ; \ + MOV_W (AX,DX) ; \ + INC_W (AX) ; \ + SHL_L (CONST(16),EAX) ; \ + MOV_W (DX,AX) ; \ + SHL_L (CONST(2),EAX) + + ALIGNTEXT4 + GLOBL GLNAME(ATIMach64SetReadPlanar) + GLNAME(ATIMach64SetReadPlanar): + ATIMach64MassagePlanarBankNumber + MOV_W (CONTENT(GLNAME(ATIIOPortMEM_VGA_RP_SEL)),DX) + OUT_L + RET + + ALIGNTEXT4 + GLOBL GLNAME(ATIMach64SetWritePlanar) + GLNAME(ATIMach64SetWritePlanar): + ATIMach64MassagePlanarBankNumber + MOV_W (CONTENT(GLNAME(ATIIOPortMEM_VGA_WP_SEL)),DX) + OUT_L + RET + + ALIGNTEXT4 + GLOBL GLNAME(ATIMach64SetReadWritePlanar) + GLNAME(ATIMach64SetReadWritePlanar): + ATIMach64MassagePlanarBankNumber + MOV_W (CONTENT(GLNAME(ATIIOPortMEM_VGA_RP_SEL)),DX) + OUT_L + MOV_W (CONTENT(GLNAME(ATIIOPortMEM_VGA_WP_SEL)),DX) + OUT_L + RET *** /dev/null Tue Jun 30 11:48:29 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atibank.c Fri Mar 6 16:45:04 1998 *************** *** 0 **** --- 1,33 ---- + /* $TOG: atibank.c /main/1 1998/03/06 16:46:42 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atibank.c,v 1.1.2.1 1998/02/01 16:41:41 robin Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + #include "atibank.h" + + /* + * The banking function to be called by ATISelectBank. + */ + BankFunction *ATISelectBankFunction; *** /dev/null Tue Jun 30 11:48:30 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atibank.h Fri Mar 6 16:45:08 1998 *************** *** 0 **** --- 1,74 ---- + /* $TOG: atibank.h /main/1 1998/03/06 16:46:45 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atibank.h,v 1.1.2.1 1998/02/01 16:41:41 robin Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + #ifndef ___ATIBANK_H___ + #define ___ATIBANK_H___ 1 + + #include "atiproto.h" + + /* + * This is the type of all banking functions. After all, this isn't COBOL... + */ + typedef void BankFunction FunctionPrototype((int)); + + /* + * These are the bank select functions. There are several sets of them, + * starting with generic ones. + */ + extern BankFunction ATISetRead, + ATISetWrite, + ATISetReadWrite; + /* + * These are the bank selection functions for V3 adapters. + */ + extern BankFunction ATIV3SetRead, + ATIV3SetWrite, + ATIV3SetReadWrite; + /* + * These are the bank selection functions for V4 and V5 adapters. + */ + extern BankFunction ATIV4V5SetRead, + ATIV4V5SetWrite, + ATIV4V5SetReadWrite; + /* + * These are the bank selection functions for a Mach64's small dual paged + * apertures. + */ + extern BankFunction ATIMach64SetReadPacked, + ATIMach64SetWritePacked, + ATIMach64SetReadWritePacked; + extern BankFunction ATIMach64SetReadPlanar, + ATIMach64SetWritePlanar, + ATIMach64SetReadWritePlanar; + /* + * Unfortunately, the above banking functions cannot be called directly from + * this module. + */ + extern BankFunction ATISelectBank; + extern BankFunction *ATISelectBankFunction; + + #endif /* ___ATIBANK_H___ */ *** /dev/null Tue Jun 30 11:48:32 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atibus.c Fri Mar 6 16:45:16 1998 *************** *** 0 **** --- 1,46 ---- + /* $TOG: atibus.c /main/1 1998/03/06 16:46:54 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atibus.c,v 1.1.2.1 1998/02/01 16:41:42 robin Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + #include "atibus.h" + + /* + * Definitions related to an adapter's system bus interface. + */ + + CARD8 ATIBusType = ATI_BUS_ISA; + const char *ATIBusNames[] = + { + "16-Bit ISA", + "EISA", + "16-Bit MicroChannel", + "32-Bit MicroChannel", + "386SX Local Bus", + "386DX Local Bus", + "VESA Local Bus", + "PCI", + "AGP" + }; *** /dev/null Tue Jun 30 11:48:33 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atibus.h Fri Mar 6 16:45:20 1998 *************** *** 0 **** --- 1,48 ---- + /* $TOG: atibus.h /main/1 1998/03/06 16:46:57 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atibus.h,v 1.1.2.1 1998/02/01 16:41:42 robin Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + #ifndef ___ATIBUS_H___ + #define ___ATIBUS_H___ 1 + + #include "Xmd.h" + + /* + * Definitions related to an adapter's system bus interface. + */ + #define ATI_BUS_ISA 0 + #define ATI_BUS_EISA 1 + #define ATI_BUS_MCA16 2 + #define ATI_BUS_MCA32 3 + #define ATI_BUS_SXLB 4 + #define ATI_BUS_DXLB 5 + #define ATI_BUS_VLB 6 + #define ATI_BUS_PCI 7 + #define ATI_BUS_AGP 8 + extern CARD8 ATIBusType; + extern const char *ATIBusNames[]; + + #endif /* ___ATIBUS_H___ */ *** /dev/null Tue Jun 30 11:48:34 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atichip.c Fri Mar 6 16:45:23 1998 *************** *** 0 **** --- 1,250 ---- + /* $TOG: atichip.c /main/1 1998/03/06 16:47:01 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atichip.c,v 1.1.2.1 1998/02/01 16:41:43 robin Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + #include "atichip.h" + #include "atiio.h" + + /* + * Chip-related definitions. + */ + CARD8 ATIChip = ATI_CHIP_NONE; + const char *ATIChipNames[] = + { + "Unknown", + "IBM VGA or compatible", + "ATI 18800", + "ATI 18800-1", + "ATI 28800-2", + "ATI 28800-4", + "ATI 28800-5", + "ATI 28800-6", + "IBM 8514/A", + "Chips & Technologies 82C480", + "ATI 38800-1", + "ATI 68800", + "ATI 68800-3", + "ATI 68800-6", + "ATI 68800LX", + "ATI 68800AX", + "ATI 88800GX-C", + "ATI 88800GX-D", + "ATI 88800GX-E", + "ATI 88800GX-F", + "ATI 88800GX", + "ATI 88800CX", + "ATI 264CT", + "ATI 264ET", + "ATI 264VT", + "ATI 3D Rage", + "ATI 264VT-B", + "ATI 3D Rage II", + "ATI 264VT3", + "ATI 3D Rage II+DVD", + "ATI 3D Rage LT", + "ATI 3D Rage Pro", + "ATI unknown Mach64", + }; + + CARD16 ATIChipType = 0, ATIChipClass = 0, ATIChipRevision = 0; + CARD16 ATIChipVersion = 0, ATIChipFoundry = 0; + CARD8 ATIChipHasSUBSYS_CNTL = FALSE; + CARD8 ATIChipHasVGAWonder = FALSE; + const char *ATIFoundryNames[] = + { "SGS", "NEC", "KCS", "UMC", "4", "5", "6", "UMC" }; + + /* + * ATIMach32ChipID -- + * + * Set variables whose value is dependent upon an 68800's CHIP_ID register. + */ + void + ATIMach32ChipID(void) + { + CARD16 IO_Value = inw(CHIP_ID); + ATIChipType = GetBits(IO_Value, CHIP_CODE_0 | CHIP_CODE_1); + ATIChipClass = GetBits(IO_Value, CHIP_CLASS); + ATIChipRevision = GetBits(IO_Value, CHIP_REV); + if (IO_Value == 0xFFFFU) + IO_Value = 0; + switch (GetBits(IO_Value, CHIP_CODE_0 | CHIP_CODE_1)) + { + case 0x0000U: + ATIChip = ATI_CHIP_68800_3; + break; + + case 0x02F7U: + ATIChip = ATI_CHIP_68800_6; + break; + + case 0x0177U: + ATIChip = ATI_CHIP_68800LX; + break; + + case 0x0017U: + ATIChip = ATI_CHIP_68800AX; + break; + + default: + ATIChip = ATI_CHIP_68800; + break; + } + } + + /* + * ATIMach64ChipID -- + * + * Set variables whose value is dependent upon a Mach64's CONFIG_CHIP_ID + * register. + */ + void + ATIMach64ChipID(const CARD16 ExpectedChipType) + { + CARD32 IO_Value = inl(ATIIOPort(CONFIG_CHIP_ID)); + ATIChipType = GetBits(IO_Value, 0xFFFFU); + ATIChipClass = GetBits(IO_Value, CFG_CHIP_CLASS); + ATIChipRevision = GetBits(IO_Value, CFG_CHIP_REV); + ATIChipVersion = GetBits(IO_Value, CFG_CHIP_VERSION); + ATIChipFoundry = GetBits(IO_Value, CFG_CHIP_FOUNDRY); + switch (ATIChipType) + { + case 0x00D7U: + ATIChipType = 0x4758U; + case 0x4758U: + switch (ATIChipRevision) + { + case 0x00U: + ATIChip = ATI_CHIP_88800GXC; + break; + + case 0x01U: + ATIChip = ATI_CHIP_88800GXD; + break; + + case 0x02U: + ATIChip = ATI_CHIP_88800GXE; + break; + + case 0x03U: + ATIChip = ATI_CHIP_88800GXF; + break; + + default: + ATIChip = ATI_CHIP_88800GX; + break; + } + break; + + case 0x0057U: + ATIChipType = 0x4358U; + case 0x4358U: + ATIChip = ATI_CHIP_88800CX; + break; + + case 0x0053U: + ATIChipType = 0x4354U; + case 0x4354U: + ATIChipRevision = GetBits(IO_Value, CFG_CHIP_REVISION); + ATIChip = ATI_CHIP_264CT; + break; + + case 0x0093U: + ATIChipType = 0x4554U; + case 0x4554U: + ATIChipRevision = GetBits(IO_Value, CFG_CHIP_REVISION); + ATIChip = ATI_CHIP_264ET; + break; + + case 0x02B3U: + ATIChipType = 0x5654U; + case 0x5654U: + ATIChipRevision = GetBits(IO_Value, CFG_CHIP_REVISION); + ATIChip = ATI_CHIP_264VT; + /* Some early GT's are detected as VT's */ + if (ExpectedChipType && (ATIChipType != ExpectedChipType)) + { + if (ExpectedChipType == 0x4754U) + ATIChip = ATI_CHIP_264GT; + else + ErrorF("Mach64 chip type probe discrepancy detected:\n" + " PCI=0x%04X; CHIP_ID=0x%04X.\n", + ExpectedChipType, ATIChipType); + } + else if (ATIChipVersion) + ATIChip = ATI_CHIP_264VTB; + break; + + case 0x00D3U: + ATIChipType = 0x4754U; + case 0x4754U: + ATIChipRevision = GetBits(IO_Value, CFG_CHIP_REVISION); + if (!ATIChipVersion) + ATIChip = ATI_CHIP_264GT; + else + ATIChip = ATI_CHIP_264GTB; + break; + + case 0x02B4U: + ATIChipType = 0x5655U; + case 0x5655U: + ATIChipRevision = GetBits(IO_Value, CFG_CHIP_REVISION); + ATIChip = ATI_CHIP_264VT3; + break; + + case 0x00D4U: + ATIChipType = 0x4755U; + case 0x4755U: + ATIChipRevision = GetBits(IO_Value, CFG_CHIP_REVISION); + ATIChip = ATI_CHIP_264GTDVD; + break; + + case 0x0166U: + ATIChipType = 0x4C47U; + case 0x4C47U: + ATIChipRevision = GetBits(IO_Value, CFG_CHIP_REVISION); + ATIChip = ATI_CHIP_264LT; + break; + + case 0x00C7U: + case 0x00C9U: + case 0x00CEU: + case 0x00CFU: + case 0x00D0U: + ATIChipType = 0x4750U; + case 0x4742U: + case 0x4744U: + case 0x4749U: + case 0x4750U: + case 0x4751U: + ATIChipRevision = GetBits(IO_Value, CFG_CHIP_REVISION); + ATIChip = ATI_CHIP_264GT3; + break; + + default: + ATIChip = ATI_CHIP_Mach64; + break; + } + } *** /dev/null Tue Jun 30 11:48:35 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atichip.h Fri Mar 6 16:45:28 1998 *************** *** 0 **** --- 1,93 ---- + /* $TOG: atichip.h /main/1 1998/03/06 16:47:05 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atichip.h,v 1.1.2.1 1998/02/01 16:41:44 robin Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + #ifndef ___ATICHIP_H___ + #define ___ATICHIP_H___ 1 + + #include "atiproto.h" + #include "Xmd.h" + + /* + * Chip-related definitions. + */ + #define ATI_CHIP_NONE 0 + #define ATI_CHIP_VGA 1 /* Generic VGA */ + #define ATI_CHIP_18800 2 + #define ATI_CHIP_18800_1 3 + #define ATI_CHIP_28800_2 4 + #define ATI_CHIP_28800_4 5 + #define ATI_CHIP_28800_5 6 + #define ATI_CHIP_28800_6 7 + #define ATI_CHIP_8514A 8 /* 8514/A */ + #define ATI_CHIP_CT480 9 /* 8514/A clone */ + #define ATI_CHIP_38800_1 10 /* Mach8 */ + #define ATI_CHIP_68800 11 /* Mach32 */ + #define ATI_CHIP_68800_3 12 /* Mach32 */ + #define ATI_CHIP_68800_6 13 /* Mach32 */ + #define ATI_CHIP_68800LX 14 /* Mach32 */ + #define ATI_CHIP_68800AX 15 /* Mach32 */ + #define ATI_CHIP_88800GXC 16 /* Mach64 */ + #define ATI_CHIP_88800GXD 17 /* Mach64 */ + #define ATI_CHIP_88800GXE 18 /* Mach64 */ + #define ATI_CHIP_88800GXF 19 /* Mach64 */ + #define ATI_CHIP_88800GX 20 /* Mach64 */ + #define ATI_CHIP_88800CX 21 /* Mach64 */ + #define ATI_CHIP_264CT 22 /* Mach64 */ + #define ATI_CHIP_264ET 23 /* Mach64 */ + #define ATI_CHIP_264VT 24 /* Mach64 */ + #define ATI_CHIP_264GT 25 /* Mach64 */ + #define ATI_CHIP_264VTB 26 /* Mach64 */ + #define ATI_CHIP_264GTB 27 /* Mach64 */ + #define ATI_CHIP_264VT3 28 /* Mach64 */ + #define ATI_CHIP_264GTDVD 29 /* Mach64 */ + #define ATI_CHIP_264LT 30 /* Mach64 */ + #define ATI_CHIP_264GT3 31 /* Mach64 */ + #define ATI_CHIP_Mach64 32 /* Mach64 */ + extern CARD8 ATIChip; + extern const char *ATIChipNames[]; + + /* + * Foundry codes for 264xT's. + */ + #define ATI_FOUNDRY_SGS 0 /* SGS-Thompson */ + #define ATI_FOUNDRY_NEC 1 /* NEC */ + #define ATI_FOUNDRY_KSC 2 /* KSC (?) */ + #define ATI_FOUNDRY_UMC 3 /* United Microelectronics Corporation */ + #define ATI_FOUNDRY_4 4 + #define ATI_FOUNDRY_5 5 + #define ATI_FOUNDRY_6 6 + #define ATI_FOUNDRY_UMCA 7 /* UMC alternate */ + extern CARD16 ATIChipType, ATIChipClass, ATIChipRevision; + extern CARD16 ATIChipVersion, ATIChipFoundry; + extern CARD8 ATIChipHasSUBSYS_CNTL; + extern CARD8 ATIChipHasVGAWonder; + extern const char *ATIFoundryNames[]; + + extern void ATIMach32ChipID FunctionPrototype((void)); + extern void ATIMach64ChipID FunctionPrototype((const CARD16)); + + #endif /* ___ATICHIP_H___ */ *** /dev/null Tue Jun 30 11:48:36 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/aticlock.c Fri Mar 6 16:45:32 1998 *************** *** 0 **** --- 1,1285 ---- + /* $TOG: aticlock.c /main/1 1998/03/06 16:47:10 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/aticlock.c,v 1.1.2.1 1998/02/01 16:41:44 robin Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + /* + * Adapters prior to V5 use 4 crystals. Adapters V5 and later use a clock + * generator chip. V3 and V4 adapters differ when it comes to choosing clock + * frequencies. + * + * VGA Wonder V3/V4 Adapter Clock Frequencies + * R E G I S T E R S + * 1CE(*) 3C2 3C2 Frequency + * B2h/BEh + * Bit 6/4 Bit 3 Bit 2 (MHz) + * ------- ------- ------- ------- + * 0 0 0 50.000 + * 0 0 1 56.644 + * 0 1 0 Spare 1 + * 0 1 1 44.900 + * 1 0 0 44.900 + * 1 0 1 50.000 + * 1 1 0 Spare 2 + * 1 1 1 36.000 + * + * (*): V3 uses index B2h, bit 6; V4 uses index BEh, bit 4 + * + * V5, PLUS, XL and XL24 usually have an ATI 18810 clock generator chip, but + * some have an ATI 18811-0, and it's quite conceivable that some exist with + * ATI 18811-1's or ATI 18811-2's. Mach32 adapters are known to use any one of + * these clock generators. Mach32 adapters also use a different dot clock + * ordering. ATI says there is no reliable way for the driver to determine + * which clock generator is on the adapter, but this driver will do its best to + * do so anyway. + * + * VGA Wonder V5/PLUS/XL/XL24 Clock Frequencies + * R E G I S T E R S + * 1CE 1CE 3C2 3C2 Frequency + * B9h BEh (MHz) 18811-0 18811-1 + * Bit 1 Bit 4 Bit 3 Bit 2 18810 18812-0 18811-2 + * ------- ------- ------- ------- ------- ------- ------- + * 0 0 0 0 30.240 30.240 135.000 + * 0 0 0 1 32.000 32.000 32.000 + * 0 0 1 0 37.500 110.000 110.000 + * 0 0 1 1 39.000 80.000 80.000 + * 0 1 0 0 42.954 42.954 100.000 + * 0 1 0 1 48.771 48.771 126.000 + * 0 1 1 0 (*1) 92.400 92.400 + * 0 1 1 1 36.000 36.000 36.000 + * 1 0 0 0 40.000 39.910 39.910 + * 1 0 0 1 56.644 44.900 44.900 + * 1 0 1 0 75.000 75.000 75.000 + * 1 0 1 1 65.000 65.000 65.000 + * 1 1 0 0 50.350 50.350 50.350 + * 1 1 0 1 56.640 56.640 56.640 + * 1 1 1 0 (*2) (*3) (*3) + * 1 1 1 1 44.900 44.900 44.900 + * + * (*1) External 0 (supposedly 16.657 Mhz) + * (*2) External 1 (supposedly 28.322 MHz) + * (*3) This setting doesn't seem to generate anything + * + * Mach32 Clock Frequencies + * R E G I S T E R S + * 1CE 1CE 3C2 3C2 Frequency + * B9h BEh (MHz) 18811-0 18811-1 + * Bit 1 Bit 4 Bit 3 Bit 2 18810 18812-0 18811-2 + * ------- ------- ------- ------- ------- ------- ------- + * 0 0 0 0 42.954 42.954 100.000 + * 0 0 0 1 48.771 48.771 126.000 + * 0 0 1 0 (*1) 92.400 92.400 + * 0 0 1 1 36.000 36.000 36.000 + * 0 1 0 0 30.240 30.240 135.000 + * 0 1 0 1 32.000 32.000 32.000 + * 0 1 1 0 37.500 110.000 110.000 + * 0 1 1 1 39.000 80.000 80.000 + * 1 0 0 0 50.350 50.350 50.350 + * 1 0 0 1 56.640 56.640 56.640 + * 1 0 1 0 (*2) (*3) (*3) + * 1 0 1 1 44.900 44.900 44.900 + * 1 1 0 0 40.000 39.910 39.910 + * 1 1 0 1 56.644 44.900 44.900 + * 1 1 1 0 75.000 75.000 75.000 + * 1 1 1 1 65.000 65.000 65.000 + * + * (*1) External 0 (supposedly 16.657 Mhz) + * (*2) External 1 (supposedly 28.322 MHz) + * (*3) This setting doesn't seem to generate anything + * + * Note that, to reduce confusion, this driver masks out the different clock + * ordering. + * + * For all adapters, these frequencies can be divided by 1 or 2. For all + * adapters, except Mach32's and Mach64's, frequencies can also be divided by 3 + * or 4. + * + * Register 1CE, index B8h + * Bit 7 Bit 6 + * ------- ------- + * 0 0 Divide by 1 + * 0 1 Divide by 2 + * 1 0 Divide by 3 + * 1 1 Divide by 4 + * + * With respect to clocks, Mach64's are entirely different animals. + * + * The oldest Mach64's use one of the non-programmable clock generators + * described above. In this case, the driver will handle clocks in much the + * same way as it would for a Mach32. + * + * All other Mach64 adapters use a programmable clock generator. BIOS + * initialization programmes an initial set of frequencies. Two of these are + * reserved to allow for the setting of modes that do not use a frequency from + * this initial set. One of these reserved slots is used by the BIOS mode set + * routine, the other by the particular accelerated driver used (MS-Windows, + * AutoCAD, etc.). The slots reserved in this way are dependent on the + * particular clock generator used by the adapter. + * + * If the driver does not support the adapter's clock generator, it will try to + * match the (probed or specified) clocks to one of the following sets. + * + * Mach64 Clock Frequencies for unsupported programmable clock generators + * R E G I S T E R S + * 1CE 1CE 3C2 3C2 Frequency + * B9h BEh (MHz) + * Bit 1 Bit 4 Bit 3 Bit 2 Set 1 Set 2 Set 3 + * ------- ------- ------- ------- ------- ------- ------- + * 0 0 0 0 50.350 25.180 25.180 + * 0 0 0 1 56.640 28.320 28.320 + * 0 0 1 0 63.000 31.500 0.000 + * 0 0 1 1 72.000 36.000 0.000 + * 0 1 0 0 0.000 0.000 0.000 + * 0 1 0 1 110.000 110.000 0.000 + * 0 1 1 0 126.000 126.000 0.000 + * 0 1 1 1 135.000 135.000 0.000 + * 1 0 0 0 40.000 40.000 0.000 + * 1 0 0 1 44.900 44.900 0.000 + * 1 0 1 0 49.500 49.500 0.000 + * 1 0 1 1 50.000 50.000 0.000 + * 1 1 0 0 0.000 0.000 0.000 + * 1 1 0 1 80.000 80.000 0.000 + * 1 1 1 0 75.000 75.000 0.000 + * 1 1 1 1 65.000 65.000 0.000 + * + * The driver will never select a setting of 0.000 MHz. The above comments on + * clock ordering and clock divider apply here also. + * + * For all supported programmable clock generators, the driver will ignore any + * XF86Config clock line and programme, as needed, the clock number reserved by + * the BIOS for accelerated drivers. The driver's mode initialization routine + * finds integers N, M and D such that + * + * N + * R * ------- MHz + * M * D + * + * best approximates the mode's clock frequency, where R is the crystal- + * generated reference frequency (usually 14.318 MHz). D is a power of 2 + * except for those integrated controllers that also offer odd dividers. + * Different clock generators have different restrictions on the value N, M and + * D can assume. The driver contains an internal table to record these + * restrictions (among other things). The resulting values of N, M and D are + * then encoded in a generator-specific way and used to programme the clock. + * The Mach64's clock divider is not used in this case. + */ + + #include "ati.h" + #include "atiadapter.h" + #include "atichip.h" + #include "aticlock.h" + #include "atidac.h" + #include "atidsp.h" + #include "atiio.h" + #include "xf86_Config.h" + #include "xf86_HWlib.h" + #include "xf86Priv.h" + + /* + * Definitions related to non-programmable clock generators. + */ + CARD8 ATIClock = ATI_CLOCK_NONE; + const char *ATIClockNames[] = + { + "unknown", + "IBM VGA compatible", + "crystals", + "ATI 18810 or similar", + "ATI 18811-0 or similar", + "ATI 18811-1 or similar", + "Programmable (BIOS setting 1)", + "Programmable (BIOS setting 2)", + "Programmable (BIOS setting 3)" + }; + + /* + * Definitions related to programmable clock generators. + */ + CARD8 ATIProgrammableClock = ATI_CLOCK_FIXED; + static CARD16 ATIPostDividers[] = {1, 2, 4, 8, 16, 32, 64, 128}, + ATI264xTPostDividers[] = {1, 2, 4, 8, 3, 0, 6, 12}; + ClockRec ATIClockDescriptors[] = + { + { + 0, 0, 0, 1, 1, + 1, 1, 0, + 0, NULL, + "Non-programmable" + }, + { + 257, 512, 257, 1, 1, + 46, 46, 0, + 4, ATIPostDividers, + "ATI 18818 or ICS 2595 or similar" + }, + { + 2, 129, 2, 1, 1, + 8, 14, 2, + 8, ATIPostDividers, + "SGS-Thompson 1703 or similar" + }, + { + 8, 263, 8, 8, 9, + 4, 12, 2, + 4, ATIPostDividers, + "Chrontel 8398 or similar" + }, + { + 2, 255, 0, 1, 1, + 45, 45, 0, + 4, ATI264xTPostDividers, + "Internal" + }, + { + 2, 257, 2, 1, 1, + 2, 32, 2, + 4, ATIPostDividers, + "AT&T 20C408 or similar" + }, + { + 65, 128, 65, 1, 1, + 2, 31, 0, + 4, ATIPostDividers, + "IBM RGB 514 or similar" + } + }; + int ATIClockNumberToProgramme = -1; + int ATIReferenceNumerator = 157500, + ATIReferenceDenominator = 11; + ClockPtr ATIClockDescriptor = ATIClockDescriptors; + CARD16 ATIBIOSClocks[16] = + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + + /* + * XF86Config clocks line that start with the following will either be rejected + * for ATI boards, or accepted for non-ATI boards. + */ + static const int + ATIVGAClocks[] = + { + 25175, 28322, + -1 + }; + + /* + * The driver will attempt to match fixed clocks to one of the following + * specifications. + */ + static const int + ATICrystalFrequencies[] = + { + 50000, 56644, 0, 44900, 44900, 50000, 0, 36000, + -1 + }, + ATI18810Frequencies[] = + { + 30240, 32000, 37500, 39000, 42954, 48771, 0, 36000, + 40000, 56644, 75000, 65000, 50350, 56640, 0, 44900 + }, + ATI188110Frequencies[] = + { + 30240, 32000, 110000, 80000, 42954, 48771, 92400, 36000, + 39910, 44900, 75000, 65000, 50350, 56640, 0, 44900 + }, + ATI188111Frequencies[] = + { + 135000, 32000, 110000, 80000, 100000, 126000, 92400, 36000, + 39910, 44900, 75000, 65000, 50350, 56640, 0, 44900 + }, + ATIMach64AFrequencies[] = + { + 0, 110000, 126000, 135000, 50350, 56640, 63000, 72000, + 0, 80000, 75000, 65000, 40000, 44900, 49500, 50000 + }, + ATIMach64BFrequencies[] = + { + 0, 110000, 126000, 135000, 25180, 28320, 31500, 36000, + 0, 80000, 75000, 65000, 40000, 44900, 49500, 50000 + }, + ATIMach64CFrequencies[] = + { + 0, 0, 0, 0, 25180, 28320, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 + }, + *ClockLine[] = + { + NULL, + ATIVGAClocks, + ATICrystalFrequencies, + ATI18810Frequencies, + ATI188110Frequencies, + ATI188111Frequencies, + ATIMach64AFrequencies, + ATIMach64BFrequencies, + ATIMach64CFrequencies, + NULL + }; + + /* + * The driver will reject XF86Config clocks lines that start with, or are an + * initial subset of, one of the following. + */ + static const int + ATIPre_2_1_1_Clocks_A[] = /* Based on 18810 */ + { + 18000, 22450, 25175, 28320, 36000, 44900, 50350, 56640, + 30240, 32000, 37500, 39000, 40000, 56644, 75000, 65000, + -1 + }, + ATIPre_2_1_1_Clocks_B[] = /* Based on 18811-0 */ + { + 18000, 22450, 25175, 28320, 36000, 44900, 50350, 56640, + 30240, 32000, 110000, 80000, 39910, 44900, 75000, 65000, + -1 + }, + ATIPre_2_1_1_Clocks_C[] = /* Based on 18811-1 (or -2) */ + { + 18000, 22450, 25175, 28320, 36000, 44900, 50350, 56640, + 135000, 32000, 110000, 80000, 39910, 44900, 75000, 65000, + -1 + }, + ATIPre_2_1_1_Clocks_D[] = /* Based on programmable setting 1 */ + { + 36000, 25000, 20000, 22450, 72000, 50000, 40000, 44900, + 0, 110000, 126000, 135000, 0, 80000, 75000, 65000, + -1 + }, + ATIPre_2_1_1_Clocks_E[] = /* Based on programmable setting 2 */ + { + 18000, 25000, 20000, 22450, 36000, 50000, 40000, 44900, + 0, 110000, 126000, 135000, 0, 80000, 75000, 65000, + -1 + }, + *InvalidClockLine[] = + { + NULL, + ATIVGAClocks, + ATIPre_2_1_1_Clocks_A, + ATIPre_2_1_1_Clocks_B, + ATIPre_2_1_1_Clocks_C, + ATIPre_2_1_1_Clocks_D, + ATIPre_2_1_1_Clocks_E, + NULL + }; + + /* + * Clock maps. + */ + static const CARD8 Clock_Maps[][16] = + { + /* Null map */ + { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15}, + /* VGA Wonder map <-> Mach{8,32,64} */ + { 4, 5, 6, 7, 0, 1, 2, 3, 12, 13, 14, 15, 8, 9, 10, 11}, + /* VGA Wonder map <-> Accelerator */ + { 0, 1, 2, 3, 8, 9, 10, 11, 4, 5, 6, 7, 12, 13, 14, 15}, + /* VGA -> Accelerator map */ + { 8, 9, 10, 11, 0, 1, 2, 3, 12, 13, 14, 15, 4, 5, 6, 7}, + /* Accelerator -> VGA map */ + { 4, 5, 6, 7, 12, 13, 14, 15, 0, 1, 2, 3, 8, 9, 10, 11} + }; + #define ATIVGAWonderClockMap Clock_Maps[0] + #define ATIVGAWonderClockUnMap ATIVGAWonderClockMap + #define ATIMachVGAClockMap Clock_Maps[1] + #define ATIMachVGAClockUnMap ATIMachVGAClockMap + #define ATIVGAProgrammableClockMap Clock_Maps[2] + #define ATIVGAProgrammableClockUnMap ATIVGAProgrammableClockMap + #define ATIAcceleratorClockMap Clock_Maps[3] + #define ATIAcceleratorClockUnMap Clock_Maps[4] + #define ATIProgrammableClockMap Clock_Maps[0] + #define ATIProgrammableClockUnMap ATIProgrammableClockMap + const CARD8 *ATIClockMap = ATIVGAWonderClockMap; + const CARD8 *ATIClockUnMap = ATIVGAWonderClockUnMap; + + /* + * ATIClockSelect -- + * + * This function selects the dot-clock with index 'Index'. This is done by + * setting bits in various registers (generic VGA uses two bits in the + * miscellaneous output register to select from 4 clocks). Care is taken to + * protect any other bits in these registers by fetching their values and + * masking off the other bits. + */ + static Bool + ATIClockSelect(int Index) + { + CARD8 misc; + + switch(Index) + { + case CLK_REG_SAVE: + if ((ATICurrentHWPtr->crtc == ATI_CRTC_VGA) && ATIChipHasVGAWonder) + ATIModifyExtReg(0xB5U, ATICurrentHWPtr->b5, 0x7FU, 0x00U); + break; + + case CLK_REG_RESTORE: + break; + + default: + /* Remap clock number */ + Index = ATICurrentHWPtr->ClockMap[Index & 0x0FU] | + (Index & ~0x0FU); + + switch (ATICurrentHWPtr->crtc) + { + case ATI_CRTC_VGA: + /* Set the generic two low-order bits */ + misc = (inb(R_GENMO) & 0xF3U) | ((Index << 2) & 0x0CU); + + if (ATIChipHasVGAWonder) + { + /* + * On adapters with crystals, switching to one of the + * spare assignments doesn't do anything (i.e. the + * previous setting remains in effect). So, disable + * their selection. + */ + if (((Index & 0x03U) == 0x02U) && + ((ATIChip <= ATI_CHIP_18800) || + (ATIAdapter == ATI_ADAPTER_V4))) + return FALSE; + + /* Start sequencer reset */ + PutReg(SEQX, 0x00, 0x00); + + /* Set the high order bits */ + if (ATIChip <= ATI_CHIP_18800) + ATIModifyExtReg(0xB2U, -1, 0xBFU, Index << 4); + else + { + ATIModifyExtReg(0xBEU, -1, 0xEFU, Index << 2); + if (ATIAdapter != ATI_ADAPTER_V4) + { + Index >>= 1; + ATIModifyExtReg(0xB9U, -1, 0xFDU, Index >> 1); + } + } + + /* Set clock divider bits */ + ATIModifyExtReg(0xB8U, -1, 0x00U, + (Index << 3) & 0xC0U); + } + /* + * Reject clocks that cannot be selected. + */ + else + { + if (Index & 0xFCU) + return FALSE; + + /* Start sequencer reset */ + PutReg(SEQX, 0x00, 0x00); + } + + /* Must set miscellaneous output register last */ + outb(GENMO, misc); + + PutReg(SEQX, 0x00U, 0x03U); /* End sequencer reset */ + break; + + case ATI_CRTC_MACH64: + outl(ATIIOPortCLOCK_CNTL, CLOCK_STROBE | + SetBits(Index, CLOCK_SELECT | CLOCK_DIVIDER)); + break; + + default: + return FALSE; + } + break; + } + + return TRUE; + } + + /* + * ATIMatchClockLine -- + * + * This function tries to match the XF86Config clocks to one of an array of + * clock lines. It returns a clock line number (or 0). + */ + static const int + ATIMatchClockLine(const int **Clock_Line, + const unsigned short int Number_Of_Clocks, + const int Calibration_Clock_Number, const int Clock_Map) + { + int Clock_Chip = 0, Clock_Chip_Index = 0; + int Number_Of_Matching_Clocks = 0; + int Minimum_Gap = CLOCK_TOLERANCE + 1; + + /* For ATI boards, reject generic VGA clocks */ + if ((ATIAdapter != ATI_ADAPTER_VGA) && (Clock_Line == ClockLine)) + Clock_Chip_Index++; + /* If checking for XF86Config clock order, skip crystals */ + if (Clock_Map) + Clock_Chip_Index++; + + for (; Clock_Line[++Clock_Chip_Index]; ) + { + int Maximum_Gap = 0, Clock_Count = 0, Clock_Index = 0; + + for (; Clock_Index < Number_Of_Clocks; Clock_Index++) + { + int Gap, XF86Config_Clock, Specification_Clock; + + Specification_Clock = Clock_Line[Clock_Chip_Index] + [Clock_Maps[Clock_Map][Clock_Index]]; + if (Specification_Clock < 0) + break; + if (!Specification_Clock || + (Specification_Clock > vga256InfoRec.maxClock)) + continue; + + XF86Config_Clock = vga256InfoRec.clock[Clock_Index]; + if (!XF86Config_Clock || + (XF86Config_Clock > vga256InfoRec.maxClock)) + continue; + + Gap = abs(XF86Config_Clock - Specification_Clock); + if (Gap >= Minimum_Gap) + goto skip_this_clock_generator; + if (!Gap) + { + if (Clock_Index == Calibration_Clock_Number) + continue; + } + else if (Gap > Maximum_Gap) + Maximum_Gap = Gap; + Clock_Count++; + } + + if (Clock_Count <= Number_Of_Matching_Clocks) + continue; + Number_Of_Matching_Clocks = Clock_Count; + Clock_Chip = Clock_Chip_Index; + if (!(Minimum_Gap = Maximum_Gap)) + break; + skip_this_clock_generator: + /* For non-ATI adapters, only normalize standard VGA clocks */ + if (ATIAdapter == ATI_ADAPTER_VGA) + break; + } + + return Clock_Chip; + } + + /* + * ATIClockProbe -- + * + * This function is called by ATIProbe and handles the XF86Config clocks line + * (or lack thereof). + */ + void + ATIClockProbe(void) + { + unsigned short int Number_Of_Undivided_Clocks; + unsigned short int Number_Of_Dividers, Number_Of_Clocks; + int Calibration_Clock_Number, Calibration_Clock_Value; + int Clock_Index, Specification_Clock, Clock_Map = 0; + pointer saved_vgaBase = NULL; + CARD16 VSyncRegister = GENS1(vgaIOBase); + CARD8 VSyncBit = 0x08U; + + /* + * Decide what to do about the XF86Config clocks for programmable clock + * generators. + */ + if (ATIProgrammableClock != ATI_CLOCK_FIXED) + { + /* Check for those that are not (yet) handled */ + if (ATIProgrammableClock >= NumberOf(ATIClockDescriptors)) + ErrorF("Unknown programmable clock generator type (0x%02X)" + " detected.\n", ATIProgrammableClock); + else if (ATIClockDescriptor->MaxN <= 0) + ErrorF("Unsupported programmable clock generator detected: %s.", + ATIClockDescriptor->ClockName); + else + { + /* + * Recognize supported clock generators. This involves telling the + * rest of the server about it and (re-)initializing the XF86Config + * clocks line. + */ + OFLG_SET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions); + + /* Set internal clock ordering */ + if (ATICRTC == ATI_CRTC_VGA) + { + ATIClockMap = ATIVGAProgrammableClockMap; + ATIClockUnMap = ATIVGAProgrammableClockUnMap; + } + else + { + ATIClockMap = ATIProgrammableClockMap; + ATIClockUnMap = ATIProgrammableClockUnMap; + } + + if (xf86Verbose) + { + ErrorF("%s programmable clock generator detected.\n", + ATIClockDescriptor->ClockName); + ErrorF("Reference clock %.6g/%d (%.3f) MHz.\n", + ((double)ATIReferenceNumerator) / 1000.0, + ATIReferenceDenominator, + ((double)ATIReferenceNumerator) / + ((double)ATIReferenceDenominator * 1000.0)); + } + + /* Clobber XF86Config clock line */ + if (OFLG_ISSET(XCONFIG_CLOCKS, &vga256InfoRec.xconfigFlag)) + { + OFLG_CLR(XCONFIG_CLOCKS, &vga256InfoRec.xconfigFlag); + ErrorF("XF86Config clocks specification ignored.\n"); + } + if (ATIProgrammableClock == ATI_CLOCK_CH8398) + { /* The first two are fixed */ + vga256InfoRec.clocks = 2; + vga256InfoRec.clock[0] = 25175; + vga256InfoRec.clock[1] = 28322; + } + else + { + vga256InfoRec.clocks = 0; + + if (ATIProgrammableClock == ATI_CLOCK_INTERNAL) + /* + * The integrated PLL generates clocks as if the reference + * frequency were doubled. + */ + ATIReferenceNumerator <<= 1; + } + + return; /* to ATIProbe */ + } + } + + /* + * Determine the number of clock values the adapter should be able to + * generate and the dot clock to use for probe calibration. + */ + probe_clocks: + if (ATIAdapter == ATI_ADAPTER_VGA) + { + Number_Of_Dividers = 1; + Number_Of_Undivided_Clocks = 4; + Calibration_Clock_Number = 1; + Calibration_Clock_Value = 28322; + } + else + { + Number_Of_Dividers = 4; + if ((ATIChip <= ATI_CHIP_18800) || (ATIAdapter == ATI_ADAPTER_V4)) + { + Number_Of_Undivided_Clocks = 8; + /* Actually, any undivided clock will do */ + Calibration_Clock_Number = 1; + Calibration_Clock_Value = 56644; + } + else + { + Number_Of_Undivided_Clocks = 16; + Calibration_Clock_Number = 10 /* or 11 */; + Calibration_Clock_Value = 75000 /* or 65000 */; + if (ATIChip >= ATI_CHIP_68800) + { + Number_Of_Dividers = 2; + if (ATIChip >= ATI_CHIP_264CT) + { + Number_Of_Dividers = 1; + Number_Of_Undivided_Clocks = 4; + Calibration_Clock_Number = 1; + Calibration_Clock_Value = 28322; + } + + /* + * When selecting clocks, all ATI accelerators use a different + * clock ordering. + */ + if (ATICRTC == ATI_CRTC_VGA) + { + ATIClockMap = ATIMachVGAClockMap; + ATIClockUnMap = ATIMachVGAClockUnMap; + } + else + { + ATIClockMap = ATIAcceleratorClockMap; + ATIClockUnMap = ATIAcceleratorClockUnMap; + } + } + } + } + Number_Of_Clocks = Number_Of_Undivided_Clocks * Number_Of_Dividers; + + /* + * Respect any XF86Config clocks line. Well, that's the theory, anyway. + * In practice, however, the regular use of probed values is widespread, at + * times causing otherwise inexplicable results. So, attempt to normalize + * the clocks to known (specification) values. + */ + if ((!vga256InfoRec.clocks) || xf86ProbeOnly || + (OFLG_ISSET(OPTION_PROBE_CLKS, &vga256InfoRec.options))) + { + if (ATIProgrammableClock != ATI_CLOCK_FIXED) + { + /* + * For unsupported programmable clock generators, pick the highest + * frequency set by BIOS initialization for clock calibration. + */ + Calibration_Clock_Number = Calibration_Clock_Value = 0; + for (Clock_Index = 0; + Clock_Index < Number_Of_Undivided_Clocks; + Clock_Index++) + if (Calibration_Clock_Value < ATIBIOSClocks[Clock_Index]) + { + Calibration_Clock_Number = Clock_Index; + Calibration_Clock_Value = ATIBIOSClocks[Clock_Index]; + } + Calibration_Clock_Number = ATIClockUnMap[Calibration_Clock_Number]; + Calibration_Clock_Value *= 10; + } + + if (ATIVGAAdapter != ATI_ADAPTER_NONE) + { + /* + * The current video state needs to be saved before the clock + * probe, and restored after. On some older adapters, the + * sequencer resets that occur during the clock probe cause memory + * corruption. + */ + saved_vgaBase = vgaBase; + vgaBase = xf86MapVidMem(vga256InfoRec.scrnIndex, VGA_REGION, + (pointer)vga256InfoRec.VGAbase, ATI.ChipMapSize); + ATICurrentHWPtr = ATISave(NULL); + } + + switch (ATICurrentHWPtr->crtc) + { + case ATI_CRTC_VGA: + /* Already set */ + break; + + case ATI_CRTC_MACH64: + VSyncRegister = ATIIOPortCRTC_INT_CNTL + 0; + VSyncBit = GetByte(CRTC_VBLANK, 0); + break; + + default: + break; + } + + /* Probe the adapter for clock values */ + xf86GetClocks(Number_Of_Clocks, ATIClockSelect, (void (*)())NoopDDA, + (SaveScreenProcPtr)NoopDDA, VSyncRegister, VSyncBit, + Calibration_Clock_Number, Calibration_Clock_Value, &vga256InfoRec); + + if (ATIVGAAdapter != ATI_ADAPTER_NONE) + { + /* Restore video state */ + ATIRestore(ATICurrentHWPtr); + xfree(ATICurrentHWPtr); + xf86UnMapVidMem(vga256InfoRec.scrnIndex, VGA_REGION, vgaBase, + ATI.ChipMapSize); + vgaBase = saved_vgaBase; + } + + /* Tell user clocks were probed, instead of supplied */ + OFLG_CLR(XCONFIG_CLOCKS, &vga256InfoRec.xconfigFlag); + + /* Attempt to match probed clocks to a known specification */ + ATIClock = ATIMatchClockLine(ClockLine, Number_Of_Undivided_Clocks, + Calibration_Clock_Number, 0); + + if ((ATIChip <= ATI_CHIP_18800) || (ATIAdapter == ATI_ADAPTER_V4)) + { + /* V3 and V4 adapters don't have clock chips */ + if (ATIClock > ATI_CLOCK_CRYSTALS) + ATIClock = ATI_CLOCK_NONE; + } + else + { + /* All others don't have crystals */ + if (ATIClock == ATI_CLOCK_CRYSTALS) + ATIClock = ATI_CLOCK_NONE; + } + } + else + { + /* + * Allow for an initial subset of specification clocks. Can't allow + * for any more than that though... + */ + if (Number_Of_Clocks > vga256InfoRec.clocks) + { + Number_Of_Clocks = vga256InfoRec.clocks; + if (Number_Of_Undivided_Clocks > Number_Of_Clocks) + Number_Of_Undivided_Clocks = Number_Of_Clocks; + } + else + vga256InfoRec.clocks = Number_Of_Clocks; + + /* Attempt to match clocks to a known specification */ + ATIClock = + ATIMatchClockLine(ClockLine, Number_Of_Undivided_Clocks, -1, 0); + + if (ATIAdapter != ATI_ADAPTER_VGA) + { + if (ATIClock == ATI_CLOCK_NONE) + { + /* + * Reject certain clock lines that are obviously wrong. This + * includes the standard VGA clocks, and clock lines that could + * have been used with the pre-2.1.1 driver. + */ + if (ATIMatchClockLine(InvalidClockLine, Number_Of_Clocks, -1, 0)) + vga256InfoRec.clocks = 0; + else if ((ATIChip > ATI_CHIP_18800) && + (ATIAdapter != ATI_ADAPTER_V4)) + /* + * Check for clocks that are specified in the wrong order. + * This is meant to catch those who are trying to use the clock + * order intended for the accelerated servers. + */ + while((++Clock_Map, Clock_Map %= NumberOf(Clock_Maps))) + if ((ATIClock = ATIMatchClockLine(ClockLine, + Number_Of_Undivided_Clocks, -1, Clock_Map))) + { + ErrorF("XF86Config clocks ordering incorrect. Clocks" + " will be reordered.\n See README.ati for more" + " information.\n"); + break; + } + } + else + /* Ensure crystals are not matched to clock chips, and vice versa */ + if ((ATIChip <= ATI_CHIP_18800) || (ATIAdapter == ATI_ADAPTER_V4)) + { + if (ATIClock > ATI_CLOCK_CRYSTALS) + vga256InfoRec.clocks = 0; + } + else + { + if (ATIClock == ATI_CLOCK_CRYSTALS) + vga256InfoRec.clocks = 0; + } + + if (!vga256InfoRec.clocks) + { + ErrorF("Invalid or obsolete XF86Config clocks line rejected.\n" + " Clocks will be probed. See README.ati for more" + " information.\n"); + goto probe_clocks; + } + } + } + + if (ATIProgrammableClock != ATI_CLOCK_FIXED) + ATIProgrammableClock = ATI_CLOCK_FIXED; + else if (ATIClock == ATI_CLOCK_NONE) + ErrorF("Unknown clock generator detected.\n"); + else if (xf86Verbose) + if (ATIClock == ATI_CLOCK_CRYSTALS) + ErrorF("This adapter uses crystals to generate clock" + " frequencies.\n"); + else if (ATIClock != ATI_CLOCK_VGA) + ErrorF("%s clock chip detected.\n", ATIClockNames[ATIClock]); + + if (ATIClock == ATI_CLOCK_NONE) + return; /* Don't touch the clocks */ + + /* Replace the undivided clocks with specification values */ + for (Clock_Index = 0; + Clock_Index < Number_Of_Undivided_Clocks; + Clock_Index++) + { + /* + * Don't replace clocks that are probed, documented, or set by the user + * to zero. One exception is that we need to override the user's value + * for the spare settings on a crystal-based adapter. Another + * exception is when the user specifies the clock ordering intended for + * the accelerated servers. + */ + Specification_Clock = ClockLine[ATIClock][Clock_Index]; + if (Specification_Clock < 0) + break; + if (!Clock_Map) + { + if (!vga256InfoRec.clock[Clock_Index]) + continue; + if ((!Specification_Clock) && (ATIClock != ATI_CLOCK_CRYSTALS)) + continue; + } + vga256InfoRec.clock[Clock_Index] = Specification_Clock; + } + + /* Adjust the divided clocks */ + for (Clock_Index = Number_Of_Undivided_Clocks; + Clock_Index < Number_Of_Clocks; + Clock_Index++) + vga256InfoRec.clock[Clock_Index] = ATIDivide( + vga256InfoRec.clock[Clock_Index % Number_Of_Undivided_Clocks], + (Clock_Index / Number_Of_Undivided_Clocks) + 1, 0, 0); + } + + /* + * ATIClockSave -- + * + * This function saves that part of an ATIHWRec that relates to clocks. + */ + void + ATIClockSave(ATIHWPtr save) + { + if (!xf86ProbeFailed && (ATIProgrammableClock != ATI_CLOCK_FIXED)) + { + if (save->crtc == ATI_CRTC_VGA) + { + save->ClockMap = ATIVGAProgrammableClockMap; + save->ClockUnMap = ATIVGAProgrammableClockUnMap; + } + else + { + save->ClockMap = ATIProgrammableClockMap; + save->ClockUnMap = ATIProgrammableClockUnMap; + } + } + else + { + if (save->crtc != ATI_CRTC_VGA) + { + save->ClockMap = ATIAcceleratorClockMap; + save->ClockUnMap = ATIAcceleratorClockUnMap; + } + else if (ATIChip < ATI_CHIP_68800) + { + save->ClockMap = ATIVGAWonderClockMap; + save->ClockUnMap = ATIVGAWonderClockUnMap; + } + else + { + save->ClockMap = ATIMachVGAClockMap; + save->ClockUnMap = ATIMachVGAClockUnMap; + } + } + } + + /* + * ATIClockInit -- + * + * This function is called by ATIInit to generate, if necessary, the data + * needed for clock programming, and set the clock select bits in various + * register values. + */ + Bool + ATIClockInit(DisplayModePtr mode) + { + int N, M, D; + int ClockSelect, N1, TargetClock, MinimumGap; + int Frequency, Multiple; /* Used as temporaries */ + + /* Set default values */ + ATINewHWPtr->FeedbackDivider = ATINewHWPtr->ReferenceDivider = + ATINewHWPtr->PostDivider = 0; + + if ((ATIProgrammableClock == ATI_CLOCK_FIXED) || + ((ATIProgrammableClock == ATI_CLOCK_CH8398) && (mode->Clock < 2))) + { + /* Use a fixed clock */ + ClockSelect = mode->Clock; + } + else + { + /* Generate clock programme word, using units of kHz */ + if (mode == ATI.ChipBuiltinModes) + TargetClock = mode->SynthClock; + else + TargetClock = vga256InfoRec.clock[mode->Clock]; + + MinimumGap = ((unsigned int)(-1)) >> 1; + + /* Loop through reference dividers */ + for (M = ATIClockDescriptor->MinM; M <= ATIClockDescriptor->MaxM; M++) + /* Loop through post-dividers */ + for (D = 0; D < ATIClockDescriptor->NumD; D++) + { + if (!ATIClockDescriptor->PostDividers[D]) + continue; + + /* + * Calculate closest feedback divider and apply its + * restrictions. + */ + Multiple = M * ATIReferenceDenominator * + ATIClockDescriptor->PostDividers[D]; + N = ATIDivide(TargetClock * Multiple, ATIReferenceNumerator, 0, + 0); + if (N < ATIClockDescriptor->MinN) + N = ATIClockDescriptor->MinN; + else if (N > ATIClockDescriptor->MaxN) + N = ATIClockDescriptor->MaxN; + N -= ATIClockDescriptor->NAdjust; + N1 = (N / ATIClockDescriptor->N1) * ATIClockDescriptor->N2; + if (N > N1) + N = ATIDivide(N1 + 1, ATIClockDescriptor->N1, 0, 1); + N += ATIClockDescriptor->NAdjust; + N1 += ATIClockDescriptor->NAdjust; + + for (; ; N = N1) + { + /* Pick the closest setting */ + Frequency = abs(ATIDivide(N * ATIReferenceNumerator, + Multiple, 0, 0) - TargetClock); + if ((Frequency < MinimumGap) || + ((Frequency == MinimumGap) && + (ATINewHWPtr->FeedbackDivider < N))) + { + /* Save settings */ + ATINewHWPtr->FeedbackDivider = N; + ATINewHWPtr->ReferenceDivider = M; + ATINewHWPtr->PostDivider = D; + MinimumGap = Frequency; + } + + if (N <= N1) + break; + } + } + + Multiple = ATINewHWPtr->ReferenceDivider * ATIReferenceDenominator * + ATIClockDescriptor->PostDividers[ATINewHWPtr->PostDivider]; + Frequency = ATINewHWPtr->FeedbackDivider * ATIReferenceNumerator; + Frequency = ATIDivide(Frequency, Multiple, 0, 0); + if (abs(Frequency - TargetClock) > CLOCK_TOLERANCE) + { + ErrorF("Unable to programme clock %.3fMHz for mode %s.\n", + (double)TargetClock / 1000.0, mode->name); + return FALSE; + } + vga256InfoRec.clock[mode->Clock] = mode->SynthClock = Frequency; + ClockSelect = ATIClockNumberToProgramme; + + if (xf86Verbose > 1) + { + ErrorF("\nProgramming clock %d to %.3fMHz for mode %s.\n", + mode->Clock, (double)Frequency / 1000.0, mode->name); + ErrorF(" N=%d, M=%d, D=%d, L=%d.\n", + ATINewHWPtr->FeedbackDivider, ATINewHWPtr->ReferenceDivider, + ATINewHWPtr->PostDivider, ClockSelect); + } + + if ((ATIChip >= ATI_CHIP_264VTB) && (ATIIODecoding == BLOCK_IO)) + ATIDSPInit(); /* Setup DSP registers */ + + } + + /* Set clock select bits, after remapping them */ + ATINewHWPtr->std.NoClock = ClockSelect; /* Save pre-map clock number */ + ClockSelect = ATINewHWPtr->ClockMap[ClockSelect & 0x0FU] | + (ClockSelect & ~0x0FU); + + switch (ATICRTC) + { + case ATI_CRTC_VGA: + /* Set generic VGA clock select bits */ + ATINewHWPtr->std.MiscOutReg = + (ATINewHWPtr->std.MiscOutReg & 0xF3U) | + ((ClockSelect << 2) & 0x0CU); + + if (ATIChipHasVGAWonder) + { + /* Set ATI clock select bits */ + if (ATIChip <= ATI_CHIP_18800) + ATINewHWPtr->b2 = (ATINewHWPtr->b2 & 0xBFU) | + ((ClockSelect << 4) & 0x40U); + else + { + ATINewHWPtr->be = (ATINewHWPtr->be & 0xEFU) | + ((ClockSelect << 2) & 0x10U); + if (ATIAdapter != ATI_ADAPTER_V4) + { + ClockSelect >>= 1; + ATINewHWPtr->b9 = (ATINewHWPtr->b9 & 0xFDU) | + ((ClockSelect >> 1) & 0x02U); + } + } + + /* Set clock divider bits */ + ATINewHWPtr->b8 = (ATINewHWPtr->b8 & 0x3FU) | + ((ClockSelect << 3) & 0xC0U); + } + break; + + case ATI_CRTC_MACH64: + ATINewHWPtr->clock_cntl = CLOCK_STROBE | + SetBits(ClockSelect, CLOCK_SELECT | CLOCK_DIVIDER); + break; + + default: + break; + } + + return TRUE; + } + + /* + * ATIClockRestore -- + * + * This function is called by ATIRestore to programme a clock for the mode + * being set. + */ + void + ATIClockRestore(ATIHWPtr restore) + { + CARD8 saved_clock_cntl0, saved_crtc_gen_cntl3; + CARD8 tmp, tmp2, tmp3; + unsigned int Programme; + int N = restore->FeedbackDivider - ATIClockDescriptor->NAdjust; + int M = restore->ReferenceDivider - ATIClockDescriptor->MAdjust; + int D = restore->PostDivider; + + /* Temporarily switch to accelerator mode */ + saved_crtc_gen_cntl3 = inb(ATIIOPortCRTC_GEN_CNTL + 3); + outb(ATIIOPortCRTC_GEN_CNTL + 3, saved_crtc_gen_cntl3 | + GetByte(CRTC_EXT_DISP_EN, 3)); + + ATISetDACIOPorts(ATI_CRTC_MACH64); + + switch (ATIProgrammableClock) + { + case ATI_CLOCK_ICS2595: + saved_clock_cntl0 = inb(ATIIOPortCLOCK_CNTL); + + Programme = (SetBits(restore->std.NoClock, ICS2595_CLOCK) | + SetBits(N, ICS2595_FB_DIV) | SetBits(D, ICS2595_POST_DIV)) ^ + ICS2595_TOGGLE; + + ATIDelay(50000); /* 50 milliseconds */ + + (void) xf86DisableInterrupts(); + + /* Send all 20 bits of programme word */ + while (Programme >= CLOCK_BIT) + { + tmp = (Programme & CLOCK_BIT) | CLOCK_STROBE; + outb(ATIIOPortCLOCK_CNTL, tmp); + ATIDelay(26); /* 26 microseconds */ + outb(ATIIOPortCLOCK_CNTL, tmp | CLOCK_PULSE); + ATIDelay(26); /* 26 microseconds */ + Programme >>= 1; + } + + xf86EnableInterrupts(); + + /* Restore register */ + outb(ATIIOPortCLOCK_CNTL, saved_clock_cntl0 | CLOCK_STROBE); + break; + + case ATI_CLOCK_STG1703: + (void) ATIGetMach64DACCmdReg(); + (void) inb(ATIIOPortDAC_MASK); + outb(ATIIOPortDAC_MASK, (restore->std.NoClock << 1) + 0x20U); + outb(ATIIOPortDAC_MASK, 0); + outb(ATIIOPortDAC_MASK, SetBits(N, 0xFFU)); + outb(ATIIOPortDAC_MASK, SetBits(M, 0x1FU) | SetBits(D, 0xE0U)); + break; + + case ATI_CLOCK_CH8398: + tmp = inb(ATIIOPortDAC_CNTL); + outb(ATIIOPortDAC_CNTL, tmp | (DAC_EXT_SEL_RS2 | DAC_EXT_SEL_RS3)); + outb(ATIIOPortDAC_WRITE, restore->std.NoClock); + outb(ATIIOPortDAC_DATA, SetBits(N, 0xFFU)); + outb(ATIIOPortDAC_DATA, SetBits(M, 0x3FU) | SetBits(D, 0xC0U)); + outb(ATIIOPortDAC_CNTL, (tmp & ~DAC_EXT_SEL_RS2) | DAC_EXT_SEL_RS3); + break; + + case ATI_CLOCK_INTERNAL: + /* Reset VCLK generator */ + tmp3 = ATIGetMach64PLLReg(PLL_VCLK_CNTL) | PLL_VCLK_RESET; + ATIPutMach64PLLReg(PLL_VCLK_CNTL, tmp3); + + /* Set post-divider */ + tmp2 = restore->std.NoClock << 1; + tmp = ATIGetMach64PLLReg(PLL_VCLK_POST_DIV); + tmp &= ~(0x03U << tmp2); + tmp |= SetBits(D, 0x03U) << tmp2; + ATIPutMach64PLLReg(PLL_VCLK_POST_DIV, tmp); + + /* Set extended post-divider */ + tmp = ATIGetMach64PLLReg(PLL_XCLK_CNTL); + tmp &= ~(SetBits(1, PLL_VCLK0_XDIV) << restore->std.NoClock); + tmp |= SetBits(D >> 2, PLL_VCLK0_XDIV) << restore->std.NoClock; + ATIPutMach64PLLReg(PLL_XCLK_CNTL, tmp); + + /* Set feedback divider */ + tmp = PLL_VCLK0_FB_DIV + restore->std.NoClock; + ATIPutMach64PLLReg(tmp, SetBits(N, 0xFFU)); + + /* End VCLK generator reset */ + tmp3 &= ~PLL_VCLK_RESET; + ATIPutMach64PLLReg(PLL_VCLK_CNTL, tmp3); + + /* Reset write bit */ + ATIAccessMach64PLLReg(0, FALSE); + break; + + case ATI_CLOCK_ATT20C408: + (void) ATIGetMach64DACCmdReg(); + tmp = inb(ATIIOPortDAC_MASK); + (void) ATIGetMach64DACCmdReg(); + outb(ATIIOPortDAC_MASK, tmp | 1); + outb(ATIIOPortDAC_WRITE, 1); + outb(ATIIOPortDAC_MASK, tmp | 9); + ATIDelay(400); /* 400 microseconds */ + tmp2 = (restore->std.NoClock << 2) + 0x40U; + outb(ATIIOPortDAC_WRITE, tmp2); + outb(ATIIOPortDAC_MASK, SetBits(N, 0xFFU)); + outb(ATIIOPortDAC_WRITE, ++tmp2); + outb(ATIIOPortDAC_MASK, SetBits(M, 0x3FU) | SetBits(D, 0xC0U)); + outb(ATIIOPortDAC_WRITE, ++tmp2); + outb(ATIIOPortDAC_MASK, 0x77U); + ATIDelay(400); /* 400 microseconds */ + outb(ATIIOPortDAC_WRITE, 1); + outb(ATIIOPortDAC_MASK, tmp); + break; + + case ATI_CLOCK_IBMRGB514: + tmp = inb(ATIIOPortDAC_CNTL); + outb(ATIIOPortDAC_CNTL, (tmp & ~DAC_EXT_SEL_RS3) | DAC_EXT_SEL_RS2); + tmp = (restore->std.NoClock << 1) + 0x20U; + outb(ATIIOPortDAC_WRITE, tmp); + outb(ATIIOPortDAC_DATA, 0); + outb(ATIIOPortDAC_MASK, + (SetBits(N, 0x3FU) | SetBits(D, 0xC0U)) ^ 0xC0U); + outb(ATIIOPortDAC_WRITE, tmp + 1); + outb(ATIIOPortDAC_DATA, 0); + outb(ATIIOPortDAC_MASK, SetBits(M, 0x3FU)); + break; + + default: + break; + } + + (void) inb(ATIIOPortDAC_WRITE); /* Clear DAC counter */ + + /* Restore register */ + outl(ATIIOPortCRTC_GEN_CNTL + 3, saved_crtc_gen_cntl3); + } *** /dev/null Tue Jun 30 11:48:38 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/aticlock.h Fri Mar 6 16:45:37 1998 *************** *** 0 **** --- 1,88 ---- + /* $TOG: aticlock.h /main/1 1998/03/06 16:47:14 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/aticlock.h,v 1.1.2.1 1998/02/01 16:41:45 robin Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + #ifndef ___ATICLOCK_H___ + #define ___ATICLOCK_H___ 1 + + #include "aticrtc.h" + + /* + * Definitions related to non-programmable clock generators. + */ + #define ATI_CLOCK_NONE 0 /* Must be zero */ + #define ATI_CLOCK_VGA 1 /* Must be one */ + #define ATI_CLOCK_CRYSTALS 2 /* Must be two */ + #define ATI_CLOCK_18810 3 + #define ATI_CLOCK_18811_0 4 + #define ATI_CLOCK_18811_1 5 + #define ATI_CLOCK_MACH64A 6 + #define ATI_CLOCK_MACH64B 7 + #define ATI_CLOCK_MACH64C 8 + extern CARD8 ATIClock; + extern const char *ATIClockNames[]; + + /* + * Definitions related to programmable clock generators. + */ + #define ATI_CLOCK_FIXED 0 /* Further described above */ + #define ATI_CLOCK_ICS2595 1 + #define ATI_CLOCK_STG1703 2 + #define ATI_CLOCK_CH8398 3 + #define ATI_CLOCK_INTERNAL 4 + #define ATI_CLOCK_ATT20C408 5 + #define ATI_CLOCK_IBMRGB514 6 + #define ATI_CLOCK_MAX 7 /* Must be last */ + extern CARD8 ATIProgrammableClock; + typedef struct + { + CARD16 MinN, MaxN; /* Feedback divider and ... */ + CARD16 NAdjust; /* ... its adjustment and ... */ + CARD16 N1, N2; /* ... its restrictions */ + CARD16 MinM, MaxM; /* Reference divider and ... */ + CARD16 MAdjust; /* ... its adjustment */ + CARD16 NumD, *PostDividers; /* Post-dividers */ + const char *ClockName; + } ClockRec, *ClockPtr; + extern ClockRec ATIClockDescriptors[]; + extern int ATIClockNumberToProgramme; + extern int ATIReferenceNumerator, + ATIReferenceDenominator; + extern ClockPtr ATIClockDescriptor; + extern CARD16 ATIBIOSClocks[16]; + + /* + * Clock maps. + */ + extern const CARD8 *ATIClockMap; + extern const CARD8 *ATIClockUnMap; + + extern void ATIClockProbe FunctionPrototype((void)); + extern void ATIClockSave FunctionPrototype((ATIHWPtr)); + extern Bool ATIClockInit FunctionPrototype((DisplayModePtr)); + extern void ATIClockRestore FunctionPrototype((ATIHWPtr)); + + #endif /* ___ATICLOCK_H___ */ *** /dev/null Tue Jun 30 11:48:39 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/aticmap.c Fri Mar 6 16:45:41 1998 *************** *** 0 **** --- 1,148 ---- + /* $TOG: aticmap.c /main/1 1998/03/06 16:47:18 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/aticmap.c,v 1.1.2.1 1998/02/01 16:41:45 robin Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + #include "aticmap.h" + #include "aticrtc.h" + #include "atiio.h" + #include "cfb.h" + #include "xf86Priv.h" + + #ifdef XFreeXDGA + # define _XF86DGA_SERVER_ + # include "extensions/xf86dga.h" + # define ATIVTSema \ + ( \ + xf86VTSema || \ + (vga256InfoRec.directMode & XF86DGAHasColormap) || \ + ((vga256InfoRec.directMode & \ + (XF86DGADirectGraphics | XF86DGADirectColormap)) == \ + XF86DGADirectGraphics) \ + ) + #else + # define ATIVTSema (xf86VTSema) + #endif + + /* + * ATIStoreColours -- + * + * All of the VGA layer's colourmap handling is used except for this function. + * ... And I *know* there's lazy spellings in here, so don't razz me about it, + * OK? + */ + void + ATIStoreColours(ColormapPtr ColourMap, int NumberOfColours, xColorItem *Colour) + { + #ifndef XF86VGA16 + xColorItem DirectColour[256]; + #endif + int Index, OverScanLUTSlot, NewOverScanLUTSlot; + int LUTDistance, OverScanLUTDistance; + unsigned char *LUTEntry; + + /* This is only done for installed colourmaps */ + if (vgaCheckColorMap(ColourMap)) + return; + + #ifndef XF86VGA16 + /* Translate colours for TrueColor and DirectColor visuals */ + if ((ColourMap->pVisual->class | DynamicClass) == DirectColor) + { + NumberOfColours = cfbExpandDirectColors(ColourMap, NumberOfColours, + Colour, DirectColour); + Colour = DirectColour; + } + #endif + + /* Update the DAC's LUT and our copy of it */ + for (Index = 0; Index < NumberOfColours; Index++) + { + LUTEntry = &ATINewHWPtr->std.DAC[Colour[Index].pixel * 3]; + LUTEntry[0] = Colour[Index].red >> (16 - xf86weight.red); + LUTEntry[1] = Colour[Index].green >> (16 - xf86weight.green); + LUTEntry[2] = Colour[Index].blue >> (16 - xf86weight.blue); + + if (ATIVTSema) + { + outb(ATIIOPortDAC_WRITE, Colour[Index].pixel); + DACDelay; + outb(ATIIOPortDAC_DATA, LUTEntry[0]); + DACDelay; + outb(ATIIOPortDAC_DATA, LUTEntry[1]); + DACDelay; + outb(ATIIOPortDAC_DATA, LUTEntry[2]); + DACDelay; + } + } + + if (ATICRTC != ATI_CRTC_VGA) + return; + + /* Check if the overscan LUT slot has been redefined */ + OverScanLUTSlot = ATINewHWPtr->std.Attribute[OVERSCAN]; + LUTEntry = &ATINewHWPtr->std.DAC[OverScanLUTSlot * 3]; + if (!LUTEntry[0] && !LUTEntry[1] && !LUTEntry[2]) + return; + + NewOverScanLUTSlot = OverScanLUTSlot; + OverScanLUTDistance = + (LUTEntry[0] * LUTEntry[0]) + + (LUTEntry[1] * LUTEntry[1]) + + (LUTEntry[2] * LUTEntry[2]); + + /* Find the entry closest to black */ + for (Index = 256; (--Index >= 0) && OverScanLUTDistance; ) + { + if (Index == OverScanLUTSlot) + continue; + + LUTEntry = &ATINewHWPtr->std.DAC[Index * 3]; + LUTDistance = + (LUTEntry[0] * LUTEntry[0]) + + (LUTEntry[1] * LUTEntry[1]) + + (LUTEntry[2] * LUTEntry[2]); + if (LUTDistance >= OverScanLUTDistance) + continue; + + NewOverScanLUTSlot = Index; + OverScanLUTDistance = LUTDistance; + } + + /* Check for change */ + if (NewOverScanLUTSlot == OverScanLUTSlot) + return; + + ATINewHWPtr->std.Attribute[OVERSCAN] = NewOverScanLUTSlot; + + /* "On screen"? */ + if (!ATIVTSema) + return; + + /* Tell VGA CRTC where the new overscan entry is */ + (void) inb(GENS1(vgaIOBase)); + outb(ATTRX, OVERSCAN | 0x20U); + outb(ATTRX, NewOverScanLUTSlot); + } *** /dev/null Tue Jun 30 11:48:40 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/aticmap.h Sat Mar 7 15:02:56 1998 *************** *** 0 **** --- 1,39 ---- + /* $TOG: aticmap.h /main/2 1998/03/07 15:04:38 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/aticmap.h,v 1.1.2.1 1998/02/01 16:41:46 robin Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + #ifndef ___ATICMAP_H___ + #define ___ATICMAP_H___ 1 + + #include "atiproto.h" + #include "Xproto.h" + #include "screenint.h" + #include "colormap.h" + + extern void ATIStoreColours + FunctionPrototype((ColormapPtr, int, xColorItem *)); + + #endif /* ___ATICMAP_H___ */ *** /dev/null Tue Jun 30 11:48:41 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/aticonsole.c Fri Mar 6 16:45:49 1998 *************** *** 0 **** --- 1,318 ---- + /* $TOG: aticonsole.c /main/1 1998/03/06 16:47:27 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/aticonsole.c,v 1.1.2.1 1998/02/01 16:41:46 robin Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + #include "atiadapter.h" + #include "atichip.h" + #include "aticonsole.h" + #include "atidepth.h" + #include "atiio.h" + #include "xf86_OSproc.h" + + #ifdef XFreeXDGA + # define _XF86DGA_SERVER_ + # include "extensions/xf86dga.h" + #endif + + /* + * ATIEnterLeave -- + * + * This function is called when the virtual terminal on which the server is + * running is entered or left, as well as when the server starts up and is shut + * down. Its function is to obtain and relinquish I/O permissions for the SVGA + * device. This includes unlocking access to any registers that may be + * protected on the chipset, and locking those registers again on exit. + */ + void + ATIEnterLeave(const Bool enter) + { + static CARD8 saved_a6, saved_ab, + saved_b1, saved_b4, saved_b5, saved_b6, saved_b8, saved_b9, saved_be; + static CARD16 saved_clock_sel, saved_misc_options, saved_mem_bndry, + saved_mem_cfg; + static CARD32 saved_bus_cntl, saved_config_cntl, saved_crtc_gen_cntl, + saved_mem_info, saved_gen_test_cntl, saved_dac_cntl, + saved_crtc_int_cntl; + + static Bool entered = LEAVE; + CARD32 tmp; + + # ifdef XFreeXDGA + if ((enter == LEAVE) && !ATIUsing1bppModes && + (vga256InfoRec.directMode & XF86DGADirectGraphics)) + return; + # endif + + if (enter == entered) + return; + entered = enter; + + if (enter == ENTER) + { + xf86EnableIOPorts(vga256InfoRec.scrnIndex); + + if (ATIChipHasSUBSYS_CNTL) + { + /* Save register values to be modified */ + saved_clock_sel = inw(CLOCK_SEL); + if (ATIChip >= ATI_CHIP_68800) + { + saved_misc_options = inw(MISC_OPTIONS); + saved_mem_bndry = inw(MEM_BNDRY); + saved_mem_cfg = inw(MEM_CFG); + } + + tmp = inw(SUBSYS_STAT) & _8PLANE; + + /* Reset the 8514/A and disable all interrupts */ + outw(SUBSYS_CNTL, tmp | (GPCTRL_RESET | CHPTEST_NORMAL)); + outw(SUBSYS_CNTL, tmp | (GPCTRL_ENAB | CHPTEST_NORMAL | RVBLNKFLG | + RPICKFLAG | RINVALIDIO | RGPIDLE)); + + /* Ensure VGA is enabled */ + outw(CLOCK_SEL, saved_clock_sel & ~DISABPASSTHRU); + if (ATIChip >= ATI_CHIP_68800) + { + outw(MISC_OPTIONS, saved_misc_options & + ~(DISABLE_VGA | DISABLE_DAC)); + + /* Disable any video memory boundary */ + outw(MEM_BNDRY, saved_mem_bndry & + ~(MEM_PAGE_BNDRY | MEM_BNDRY_ENA)); + + /* Disable direct video memory aperture */ + outw(MEM_CFG, saved_mem_cfg & + ~(MEM_APERT_SEL | MEM_APERT_PAGE | MEM_APERT_LOC)); + } + + /* Wait for all activity to die down */ + ProbeWaitIdleEmpty(); + } + else if (ATIChip >= ATI_CHIP_88800GXC) + { + /* Save register values to be modified */ + saved_config_cntl = inl(ATIIOPortCONFIG_CNTL); + saved_dac_cntl = inl(ATIIOPortDAC_CNTL); + + /* Reset everything */ + saved_bus_cntl = (inl(ATIIOPortBUS_CNTL) & ~BUS_HOST_ERR_INT_EN) | + BUS_HOST_ERR_INT; + if (ATIChip < ATI_CHIP_264VTB) + saved_bus_cntl = (saved_bus_cntl & ~BUS_FIFO_ERR_INT_EN) | + BUS_FIFO_ERR_INT; + outl(ATIIOPortBUS_CNTL, (saved_bus_cntl & ~BUS_ROM_DIS) | + SetBits(15, BUS_FIFO_WS)); + saved_crtc_int_cntl = inl(ATIIOPortCRTC_INT_CNTL); + outl(ATIIOPortCRTC_INT_CNTL, + (saved_crtc_int_cntl & ~CRTC_INT_ENS) | CRTC_INT_ACKS); + saved_gen_test_cntl = inl(ATIIOPortGEN_TEST_CNTL) & + (GEN_OVR_OUTPUT_EN | GEN_OVR_POLARITY | GEN_CUR_EN | + GEN_BLOCK_WR_EN); + tmp = saved_gen_test_cntl & ~GEN_CUR_EN; + outl(ATIIOPortGEN_TEST_CNTL, tmp | GEN_GUI_EN); + outl(ATIIOPortGEN_TEST_CNTL, tmp); + outl(ATIIOPortGEN_TEST_CNTL, tmp | GEN_GUI_EN); + saved_crtc_gen_cntl = inl(ATIIOPortCRTC_GEN_CNTL) & + ~(CRTC_EN | CRTC_LOCK_REGS); + tmp = saved_crtc_gen_cntl & ~CRTC_EXT_DISP_EN; + outl(ATIIOPortCRTC_GEN_CNTL, tmp | CRTC_EN); + outl(ATIIOPortCRTC_GEN_CNTL, tmp); + outl(ATIIOPortCRTC_GEN_CNTL, tmp | CRTC_EN); + + /* Ensure VGA aperture is enabled */ + outl(ATIIOPortDAC_CNTL, saved_dac_cntl | DAC_VGA_ADR_EN); + outl(ATIIOPortCONFIG_CNTL, saved_config_cntl & ~CFG_VGA_DIS); + if (ATIChip < ATI_CHIP_264CT) + { + saved_mem_info = inl(ATIIOPortMEM_INFO); + outl(ATIIOPortMEM_INFO, saved_mem_info & + ~(CTL_MEM_BNDRY | CTL_MEM_BNDRY_EN)); + } + } + + if (ATIVGAAdapter != ATI_ADAPTER_NONE) + { + if (ATIChipHasVGAWonder) + { + /* + * Ensure all registers are read/write and disable all non-VGA + * emulations. + */ + saved_b1 = ATIGetExtReg(0xB1U); + ATIModifyExtReg(0xB1U, saved_b1, 0xFCU, 0x00U); + saved_b4 = ATIGetExtReg(0xB4U); + ATIModifyExtReg(0xB4U, saved_b4, 0x00U, 0x00U); + saved_b5 = ATIGetExtReg(0xB5U); + ATIModifyExtReg(0xB5U, saved_b5, 0xBFU, 0x00U); + saved_b6 = ATIGetExtReg(0xB6U); + ATIModifyExtReg(0xB6U, saved_b6, 0xDDU, 0x00U); + saved_b8 = ATIGetExtReg(0xB8U); + ATIModifyExtReg(0xB8U, saved_b8, 0xC0U, 0x00U); + saved_b9 = ATIGetExtReg(0xB9U); + ATIModifyExtReg(0xB9U, saved_b9, 0x7FU, 0x00U); + if (ATIChip > ATI_CHIP_18800) + { + saved_be = ATIGetExtReg(0xBEU); + ATIModifyExtReg(0xBEU, saved_be, 0xFAU, 0x01U); + if (ATIChip >= ATI_CHIP_28800_2) + { + saved_a6 = ATIGetExtReg(0xA6U); + ATIModifyExtReg(0xA6U, saved_a6, 0x7FU, 0x00U); + saved_ab = ATIGetExtReg(0xABU); + ATIModifyExtReg(0xABU, saved_ab, 0xE7U, 0x00U); + } + } + } + + ATISetVGAIOBase(inb(R_GENMO)); + + /* + * There's a bizarre interaction here. If bit 0x80 of CRTC[17] is + * on, then CRTC[3] is read-only. If bit 0x80 of CRTC[3] is off, + * then CRTC[17] is write-only (or a read attempt actually returns + * bits from C/EGA's light pen position). This means that if both + * conditions are met, CRTC[17]'s value on server entry cannot be + * retrieved. + */ + + tmp = GetReg(CRTX(vgaIOBase), 0x03U); + if ((tmp & 0x80U) || + ((outb(CRTD(vgaIOBase), tmp | 0x80U), + tmp = inb(CRTD(vgaIOBase))) & 0x80U)) + { + /* CRTC[16-17] should be readable */ + tmp = GetReg(CRTX(vgaIOBase), 0x11U); + if (tmp & 0x80U) /* Unprotect CRTC[0-7] */ + outb(CRTD(vgaIOBase), tmp & 0x7FU); + } + else + { + /* + * Could not make CRTC[17] readable, so unprotect CRTC[0-7] + * replacing VSyncEnd with zero. This zero will be replaced + * after acquiring the needed access. + */ + unsigned int VSyncEnd, VBlankStart, VBlankEnd; + CARD8 crt07, crt09; + + PutReg(CRTX(vgaIOBase), 0x11U, 0x20U); + /* Make CRTC[16-17] readable */ + PutReg(CRTX(vgaIOBase), 0x03U, tmp | 0x80U); + /* Make vertical synch pulse as wide as possible */ + crt07 = GetReg(CRTX(vgaIOBase), 0x07U); + crt09 = GetReg(CRTX(vgaIOBase), 0x09U); + VBlankStart = (((crt09 & 0x20U) << 4) | + ((crt07 & 0x08U) << 5) | + GetReg(CRTX(vgaIOBase), 0x15U)) + 1; + VBlankEnd = (VBlankStart & 0x300U) | + GetReg(CRTX(vgaIOBase), 0x16U); + if (VBlankEnd <= VBlankStart) + VBlankEnd += 0x0100U; + VSyncEnd = (((crt07 & 0x80U) << 2) | ((crt07 & 0x04U) << 6) | + GetReg(CRTX(vgaIOBase), 0x10U)) + 0x0FU; + if (VSyncEnd >= VBlankEnd) + VSyncEnd = VBlankEnd - 1; + PutReg(CRTX(vgaIOBase), 0x11U, (VSyncEnd & 0x0FU) | 0x20U); + } + } + } + else + { + if (ATIVGAAdapter != ATI_ADAPTER_NONE) + { + ATISetVGAIOBase(inb(R_GENMO)); + + /* Protect CRTC[0-7] */ + tmp = GetReg(CRTX(vgaIOBase), 0x11U); + outb(CRTD(vgaIOBase), tmp | 0x80U); + + if (ATIChipHasVGAWonder) + { + /* + * Restore emulation and protection bits in ATI extended VGA + * registers. + */ + ATIModifyExtReg(0xB1U, -1, 0xFCU, saved_b1); + ATIModifyExtReg(0xB4U, -1, 0x00U, saved_b4); + ATIModifyExtReg(0xB5U, -1, 0xBFU, saved_b5); + ATIModifyExtReg(0xB6U, -1, 0xDDU, saved_b6); + ATIModifyExtReg(0xB8U, -1, 0xC0U, saved_b8 & 0x03U); + ATIModifyExtReg(0xB9U, -1, 0x7FU, saved_b9); + if (ATIChip > ATI_CHIP_18800) + { + ATIModifyExtReg(0xBEU, -1, 0xFAU, saved_be); + if (ATIChip >= ATI_CHIP_28800_2) + { + ATIModifyExtReg(0xA6U, -1, 0x7FU, saved_a6); + ATIModifyExtReg(0xABU, -1, 0xE7U, saved_ab); + } + } + } + } + + if (ATIChipHasSUBSYS_CNTL) + { + tmp = inw(SUBSYS_STAT) & _8PLANE; + + /* Reset the 8514/A and disable all interrupts */ + outw(SUBSYS_CNTL, tmp | (GPCTRL_RESET | CHPTEST_NORMAL)); + outw(SUBSYS_CNTL, tmp | (GPCTRL_ENAB | CHPTEST_NORMAL | RVBLNKFLG | + RPICKFLAG | RINVALIDIO | RGPIDLE)); + + /* Restore modified accelerator registers */ + outw(CLOCK_SEL, saved_clock_sel); + if (ATIChip >= ATI_CHIP_68800) + { + outw(MISC_OPTIONS, saved_misc_options); + outw(MEM_BNDRY, saved_mem_bndry); + outw(MEM_CFG, saved_mem_cfg); + } + + /* Wait for all activity to die down */ + ProbeWaitIdleEmpty(); + } + else if (ATIChip >= ATI_CHIP_88800GXC) + { + /* Reset everything */ + outl(ATIIOPortBUS_CNTL, saved_bus_cntl); + outl(ATIIOPortCRTC_INT_CNTL, saved_crtc_int_cntl); + outl(ATIIOPortGEN_TEST_CNTL, saved_gen_test_cntl | GEN_GUI_EN); + outl(ATIIOPortGEN_TEST_CNTL, saved_gen_test_cntl); + outl(ATIIOPortGEN_TEST_CNTL, saved_gen_test_cntl | GEN_GUI_EN); + outl(ATIIOPortCRTC_GEN_CNTL, saved_crtc_gen_cntl | CRTC_EN); + outl(ATIIOPortCRTC_GEN_CNTL, saved_crtc_gen_cntl); + outl(ATIIOPortCRTC_GEN_CNTL, saved_crtc_gen_cntl | CRTC_EN); + + /* Restore registers */ + outl(ATIIOPortCONFIG_CNTL, saved_config_cntl); + outl(ATIIOPortDAC_CNTL, saved_dac_cntl); + if (ATIChip < ATI_CHIP_264CT) + outl(ATIIOPortMEM_INFO, saved_mem_info); + } + + xf86DisableIOPorts(vga256InfoRec.scrnIndex); + } + } *** /dev/null Tue Jun 30 11:48:42 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/aticonsole.h Fri Mar 6 16:45:53 1998 *************** *** 0 **** --- 1,36 ---- + /* $TOG: aticonsole.h /main/1 1998/03/06 16:47:31 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/aticonsole.h,v 1.1.2.1 1998/02/01 16:41:47 robin Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + #ifndef ___ATICONSOLE_H___ + #define ___ATICONSOLE_H___ 1 + + #include "atiproto.h" + #include "misc.h" + + extern void ATIEnterLeave FunctionPrototype((const Bool)); + + #endif /* ___ATICONSOLE_H___ */ *** /dev/null Tue Jun 30 11:48:43 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/aticrtc.c Sat Mar 7 16:59:49 1998 *************** *** 0 **** --- 1,702 ---- + /* $TOG: aticrtc.c /main/2 1998/03/07 17:01:31 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/aticrtc.c,v 1.1.2.1 1998/02/01 16:41:48 robin Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + #include "ati.h" + #include "atiadapter.h" + #include "atiadjust.h" + #include "atichip.h" + #include "aticlock.h" + #include "aticonsole.h" + #include "atidac.h" + #include "atidepth.h" + #include "atidsp.h" + #include "atiio.h" + #include "atimach64.h" + #include "atiprint.h" + #include "ativga.h" + #include "atividmem.h" + #include "atiwonder.h" + #include "xf86Procs.h" + + /* The CRTC to use for server generated video modes */ + CARD8 ATICRTC = ATI_CRTC_VGA; + + /* The current video mode */ + ATIHWPtr ATICurrentHWPtr; + + /* + * ATICopyVGAMemory -- + * + * This function is called by ATISwap to copy to/from one or all banks of a VGA + * plane. + */ + static void + ATICopyVGAMemory(void **saveptr, void **from, void **to) + { + unsigned int Bank; + + for (Bank = 0; Bank < ATICurrentBanks; Bank++) + { + ATISelectBank(Bank); + (void) memmove(*to, *from, ATI.ChipSegmentSize); + *saveptr = (char *)(*saveptr) + ATI.ChipSegmentSize; + } + } + + /* + * ATISwap -- + * + * This function saves/restores video memory contents during sequencer resets. + * This is used to remember the mode on server entry and during mode switches. + */ + static void + ATISwap(ATIHWPtr mode, Bool ToFB) + { + void *save, **from, **to; + CARD8 seq2, seq4, gra1, gra3, gra4, gra5, gra6, gra8; + unsigned int Plane = 0, PlaneMask = 1; + + /* + * This is only done for non-accelerator modes. If the video state on + * server entry was an accelerator mode, the application that relinquished + * the console had better do the Right Thing (tm) anyway by saving and + * restoring its own video memory. + */ + if (mode->crtc != ATI_CRTC_VGA) + return; + + /* + * There's also no need to do this if the VGA aperture isn't accessible + * through the adapter being driven. + */ + if ( /* (mode->crtc == ATI_CRTC_VGA) && */ + (mode != ATINewHWPtr) && (ATIVGAAdapter == ATI_ADAPTER_NONE)) + return; + + if (ToFB) + { + if (!mode->frame_buffer) + return; + + from = &save; + to = &vgaBase; + } + else + { + /* Allocate the memory */ + if (!mode->frame_buffer) + { + mode->frame_buffer = + (pointer)xalloc(ATI.ChipSegmentSize * ATICurrentPlanes * + ATICurrentBanks); + if (!mode->frame_buffer) + { + ErrorF("Warning: Temporary frame buffer could not be" + " allocated.\n"); + return; + } + } + + from = &vgaBase; + to = &save; + } + + /* Save register values to be changed */ + seq2 = GetReg(SEQX, 0x02U); + seq4 = GetReg(SEQX, 0x04U); + gra1 = GetReg(GRAX, 0x01U); + gra3 = GetReg(GRAX, 0x03U); + gra5 = GetReg(GRAX, 0x05U); + gra6 = GetReg(GRAX, 0x06U); + gra8 = GetReg(GRAX, 0x08U); + + save = mode->frame_buffer; + + /* Temporarily normalize the current mode */ + if (gra1 != 0x00U) + PutReg(GRAX, 0x01U, 0x00U); + if (gra3 != 0x00U) + PutReg(GRAX, 0x03U, 0x00U); + if (gra6 != 0x05U) + PutReg(GRAX, 0x06U, 0x05U); + if (gra8 != 0xFFU) + PutReg(GRAX, 0x08U, 0xFFU); + + if (seq4 & 0x08U) + { + /* Setup packed mode memory */ + if (seq2 != 0x0FU) + PutReg(SEQX, 0x02U, 0x0FU); + if (seq4 != 0x0AU) + PutReg(SEQX, 0x04U, 0x0AU); + if (ATIChip < ATI_CHIP_264CT) + { + if (gra5 != 0x00U) + PutReg(GRAX, 0x05U, 0x00U); + } + else + { + if (gra5 != 0x40U) + PutReg(GRAX, 0x05U, 0x40U); + } + + ATICopyVGAMemory(&save, from, to); + + if (seq2 != 0x0FU) + PutReg(SEQX, 0x02U, seq2); + if (seq4 != 0x0AU) + PutReg(SEQX, 0x04U, seq4); + if (ATIChip < ATI_CHIP_264CT) + { + if (gra5 != 0x00U) + PutReg(GRAX, 0x05U, gra5); + } + else + { + if (gra5 != 0x40U) + PutReg(GRAX, 0x05U, gra5); + } + } + else + { + gra4 = GetReg(GRAX, 0x04U); + + /* Setup planar mode memory */ + if (seq4 != 0x06U) + PutReg(SEQX, 0x04U, 0x06U); + if (gra5 != 0x00U) + PutReg(GRAX, 0x05U, 0x00U); + + for (; Plane < ATICurrentPlanes; Plane++) + { + PutReg(SEQX, 0x02U, PlaneMask); + PutReg(GRAX, 0x04U, Plane); + ATICopyVGAMemory(&save, from, to); + PlaneMask <<= 1; + } + + PutReg(SEQX, 0x02U, seq2); + if (seq4 != 0x06U) + PutReg(SEQX, 0x04U, seq4); + PutReg(GRAX, 0x04U, gra4); + if (gra5 != 0x00U) + PutReg(GRAX, 0x05U, gra5); + } + + /* Restore registers */ + if (gra1 != 0x00U) + PutReg(GRAX, 0x01U, gra1); + if (gra3 != 0x00U) + PutReg(GRAX, 0x03U, gra3); + if (gra6 != 0x05U) + PutReg(GRAX, 0x06U, gra6); + if (gra8 != 0xFFU) + PutReg(GRAX, 0x08U, gra8); + + ATISelectBank(0); /* Reset to bank 0 */ + + /* + * If restoring video memory for a server video mode, free the frame buffer + * save area. + */ + if (ToFB && (mode != (ATIHWPtr)vgaOrigVideoState)) + { + xfree(mode->frame_buffer); + mode->frame_buffer = NULL; + } + } + + /* + * ATISave -- + * + * This function saves the video state. It reads all of the SVGA registers + * into the ATIHWRec data structure. There is in general no need to mask out + * bits here - just read the registers. + */ + void * + ATISave(void *data) + { + ATIHWPtr save = data; + + /* If need be, allocate the data structure */ + if (!save) + save = (ATIHWPtr)Xcalloc(SizeOf(ATIHWRec)); + + /* Unlock registers */ + ATIEnterLeave(ENTER); + + /* Figure out what CRTC got us into this mess */ + save->crtc = ATI_CRTC_VGA; + #if 0 /* Not yet */ + if (ATIChipHasSUBSYS_CNTL) + { + } + else + #endif + if (ATIChip >= ATI_CHIP_88800GXC) + { + save->crtc_gen_cntl = inl(ATIIOPortCRTC_GEN_CNTL); + if (save->crtc_gen_cntl & CRTC_EXT_DISP_EN) + save->crtc = ATI_CRTC_MACH64; + } + + ATISelectBank(0); /* Get back to bank 0 */ + save->bank_function = ATISelectBankFunction; + save->banks = ATICurrentBanks; + save->planes = ATICurrentPlanes; + + /* Save clock data */ + ATIClockSave(save); + + switch (save->crtc) + { + case ATI_CRTC_VGA: + if (ATIVGAAdapter != ATI_ADAPTER_NONE) + { + /* Save VGA Wonder registers */ + if (ATIChipHasVGAWonder) + ATIVGAWonderSave(save); + + /* Save VGA registers */ + ATIVGASave(save); + } + + if (ATIChip >= ATI_CHIP_88800GXC) + { + save->crtc_off_pitch = inl(ATIIOPortCRTC_OFF_PITCH); + save->config_cntl = inl(ATIIOPortCONFIG_CNTL); + save->mem_vga_wp_sel = inl(ATIIOPortMEM_VGA_WP_SEL); + save->mem_vga_rp_sel = inl(ATIIOPortMEM_VGA_RP_SEL); + save->dac_cntl = inl(ATIIOPortDAC_CNTL); + if (ATIChip >= ATI_CHIP_264VTB) + save->bus_cntl = inl(ATIIOPortBUS_CNTL); + } + break; + + case ATI_CRTC_MACH64: + /* Save VGA registers */ + ATIVGASave(save); + + /* Save Mach64 data */ + ATIMach64Save(save); + break; + + default: + break; + } + + if ((ATIChip >= ATI_CHIP_264VTB) && (ATIIODecoding == BLOCK_IO)) + ATIDSPSave(save); + + /* Save RAMDAC state */ + ATIDACSave(save); + + /* + * The server has already saved video memory when switching out of its + * virtual console, so don't do it again. + */ + if (save != ATINewHWPtr) + { + ATICurrentHWPtr = save; /* Keep track of current mode */ + save->mode = NULL; /* No corresponding mode line */ + save->FeedbackDivider = 0; /* Don't programme clock */ + + ATISwap(save, FALSE); /* Save video memory */ + } + + (void) inb(GENS1(vgaIOBase)); /* Reset flip-flop */ + outb(ATTRX, 0x20U); /* Turn on PAS */ + + SetTimeSinceLastInputEvent(); + + return save; + } + + /* + * ATIInit -- + * + * This function fills in the ATIHWRec with all of the register values needed + * to enable a video mode. It's important that this be done without modifying + * the current video state. + */ + Bool + ATIInit(DisplayModePtr mode) + { + /* Unlock registers */ + ATIEnterLeave(ENTER); + + if (ATINewHWPtr == NULL) + { + /* Initialize ATIAdjust */ + ATIAdjustInit(); + + /* + * Check limits related to the virtual width. A better place for this + * would be in ATIValidMode were it not for the fact that the virtual + * width isn't necessarily known then. + */ + switch (ATICRTC) + { + case ATI_CRTC_VGA: + if (vga256InfoRec.displayWidth >= 4096) + { + ErrorF("Virtual resolution is too wide.\n"); + return FALSE; + } + + if (ATIUsing1bppModes) + { + /* + * Prune interlaced modes if the virtual width is too + * large. + */ + if ((ATIChip <= ATI_CHIP_28800_6) && + (vga256InfoRec.displayWidth >= 2048)) + { + DisplayModePtr Next, Deleted = NULL; + DisplayModePtr Original = mode; + + for (; mode; mode = Next) + { + Next = mode->next; + if (Next == vga256InfoRec.modes) + Next = NULL; + if (!(mode->Flags & V_INTERLACE)) + continue; + if (!Deleted) + { + Deleted = mode; + ErrorF("Interlaced modes are not supported at" + " this virtual width.\n See README.ati" + " for more information.\n"); + } + xf86DeleteMode(&vga256InfoRec, mode); + } + + /* Reset to first remaining mode */ + if (!(mode = vga256InfoRec.modes)) + { + ErrorF("Oops! No modes left!\n"); + return FALSE; + } + + /* The physical screen dimensions might have changed */ + if (mode != Original) + xf86InitViewport(&vga256InfoRec); + } + } + else if (!ATIUsingPlanarModes) + /* Packed modes have lower limits in some cases */ + if ((vga256InfoRec.displayWidth >= 2048) && + ((ATIChip >= ATI_CHIP_264CT) || + ((ATIChip <= ATI_CHIP_18800) && (ATIvideoRam == 256)))) + { + ErrorF("Virtual resolution is too wide.\n"); + return FALSE; + } + break; + + case ATI_CRTC_MACH64: + if (vga256InfoRec.displayWidth <= + (int)(GetBits(CRTC_PITCH, CRTC_PITCH) << 3)) + break; + ErrorF("Virtual resolution is too wide.\n"); + return FALSE; + + default: + break; + } + + /* + * Allocate and clear the data structure. Then, initialize it with the + * data that is to remain constant for all modes used by the server. + */ + vgaNewVideoState = (void *)Xcalloc(SizeOf(ATIHWRec)); + + /* Set the CRTC that will be used to generate the modes */ + ATINewHWPtr->crtc = ATICRTC; + + /* Set clock maps */ + ATINewHWPtr->ClockMap = ATIClockMap; + ATINewHWPtr->ClockUnMap = ATIClockUnMap; + + /* Setup for ATISwap */ + ATINewHWPtr->bank_function = ATI.ChipSetReadWrite; + ATINewHWPtr->banks = ATIMaximumBanks; + if (ATIUsingPlanarModes) + ATINewHWPtr->planes = 4; + else + ATINewHWPtr->planes = 1; + + switch (ATICRTC) + { + case ATI_CRTC_VGA: + /* Fill in VGA Wonder data */ + if (ATIChipHasVGAWonder) + ATIVGAWonderInit(NULL); + + /* Fill in VGA data */ + ATIVGAInit(NULL); + + if (ATIChip >= ATI_CHIP_264CT) + { + ATINewHWPtr->config_cntl = inl(ATIIOPortCONFIG_CNTL); + ATINewHWPtr->mem_vga_wp_sel = + /* SetBits(0, MEM_VGA_WPS0) + */ + SetBits(ATINewHWPtr->planes, MEM_VGA_WPS1); + ATINewHWPtr->mem_vga_rp_sel = + /* SetBits(0, MEM_VGA_RPS0) + */ + SetBits(ATINewHWPtr->planes, MEM_VGA_RPS1); + ATINewHWPtr->dac_cntl = inl(ATIIOPortDAC_CNTL); + if (vga256InfoRec.depth > 8) + ATINewHWPtr->dac_cntl |= DAC_8BIT_EN; + else + ATINewHWPtr->dac_cntl &= ~DAC_8BIT_EN; + if (ATIUsingSmallApertures) + ATINewHWPtr->config_cntl |= CFG_MEM_VGA_AP_EN; + else + ATINewHWPtr->config_cntl &= ~CFG_MEM_VGA_AP_EN; + if (ATIChip >= ATI_CHIP_264VTB) + ATINewHWPtr->bus_cntl = (inl(ATIIOPortBUS_CNTL) & + ~(BUS_HOST_ERR_INT_EN | BUS_ROM_DIS)) | + (BUS_HOST_ERR_INT | BUS_APER_REG_DIS); + } + break; + + case ATI_CRTC_MACH64: + /* Fill in VGA Wonder data */ + if (ATIChipHasVGAWonder) + ATIVGAWonderInit(NULL); + + /* Fill in mode-independent VGA data */ + ATIVGAInit(NULL); + + /* Fill in Mach64 accelerator data */ + ATIMach64Init(NULL); + break; + + default: + break; + } + + /* Set RAMDAC data */ + ATIDACInit(NULL); + } + + ATINewHWPtr->mode = mode; /* Link with mode line */ + + switch (ATINewHWPtr->crtc) + { + case ATI_CRTC_VGA: + /* Fill in VGA data */ + ATIVGAInit(mode); + + /* Fill in VGA Wonder data */ + if (ATIChipHasVGAWonder) + ATIVGAWonderInit(mode); + + if (ATIChip >= ATI_CHIP_88800GXC) + { + ATINewHWPtr->crtc_gen_cntl = inl(ATIIOPortCRTC_GEN_CNTL) & + ~(CRTC_DBL_SCAN_EN | CRTC_INTERLACE_EN | + CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_CSYNC_EN | + CRTC_PIX_BY_2_EN | CRTC_DISPLAY_DIS | + CRTC_VGA_XOVERSCAN | CRTC_VGA_128KAP_PAGING | + CRTC_VFC_SYNC_TRISTATE | + CRTC_LOCK_REGS | /* Already off, but ... */ + CRTC_SYNC_TRISTATE | CRTC_EXT_DISP_EN | + CRTC_DISP_REQ_EN | CRTC_VGA_LINEAR | CRTC_VGA_TEXT_132 | + CRTC_CUR_B_TEST); + #if 0 /* This isn't needed, but is kept for reference */ + if (mode->Flags & V_DBLSCAN) + ATINewHWPtr->crtc_gen_cntl |= CRTC_DBL_SCAN_EN; + #endif + if (mode->Flags & V_INTERLACE) + ATINewHWPtr->crtc_gen_cntl |= CRTC_INTERLACE_EN; + if ((mode->Flags & (V_CSYNC | V_PCSYNC)) || + (OFLG_ISSET(OPTION_CSYNC, &vga256InfoRec.options))) + ATINewHWPtr->crtc_gen_cntl |= CRTC_CSYNC_EN; + if (ATIUsingPlanarModes) + { + ATINewHWPtr->crtc_gen_cntl |= CRTC_EN | CRTC_CNT_EN; + ATINewHWPtr->crtc_off_pitch = + SetBits(vga256InfoRec.displayWidth >> 4, CRTC_PITCH); + } + else + { + ATINewHWPtr->crtc_gen_cntl |= + CRTC_EN | CRTC_VGA_LINEAR | CRTC_CNT_EN; + ATINewHWPtr->crtc_off_pitch = + SetBits(vga256InfoRec.displayWidth >> 3, CRTC_PITCH); + } + } + break; + + case ATI_CRTC_MACH64: + /* Fill in Mach64 accelerator data */ + ATIMach64Init(mode); + break; + + default: + break; + } + + /* Fill in RAMDAC data */ + ATIDACInit(mode); + + /* Setup clock programming and selection */ + return ATIClockInit(mode); + } + + /* + * ATIRestore -- + * + * This function sets a video mode. It basically writes out all of the + * registers that have previously been saved in the ATIHWRec data structure. + * + * Note that "Restore" is slightly incorrect. This function is also used when + * the server enters/changes video modes. The mode definitions have previously + * been initialized by the ATIInit() function. + */ + void + ATIRestore(void *data) + { + ATIHWPtr restore = data; + + /* Unlock registers */ + ATIEnterLeave(ENTER); + + ATISelectBank(0); /* Get back to bank 0 */ + + /* + * If switching from one server-generated mode to another, preserve video + * memory contents across sequencer resets. This is only necessary for + * 18800 and 18800-1 adapters. + */ + if ((ATIChip <= ATI_CHIP_18800_1) && + (ATICurrentHWPtr != (ATIHWPtr)vgaOrigVideoState) && + (restore != (ATIHWPtr)vgaOrigVideoState)) + ATISwap(restore, FALSE); + ATICurrentHWPtr = restore; + + /* Reset ATISwap setup to that needed by the mode to be restored */ + ATISelectBankFunction = restore->bank_function; + ATICurrentBanks = restore->banks; + ATICurrentPlanes = restore->planes; + + switch (restore->crtc) + { + case ATI_CRTC_VGA: + if (ATIVGAAdapter != ATI_ADAPTER_NONE) + { + ATISetVGAIOBase(restore->std.MiscOutReg); + + if (ATIChip >= ATI_CHIP_88800GXC) + outl(ATIIOPortCRTC_GEN_CNTL, + restore->crtc_gen_cntl & ~CRTC_EN); + + /* Start sequencer reset */ + PutReg(SEQX, 0x00U, 0x00U); + } + + /* Set the pixel clock */ + if ((restore->FeedbackDivider > 0) && + (ATIProgrammableClock != ATI_CLOCK_FIXED)) + ATIClockRestore(restore); + + if (ATIVGAAdapter != ATI_ADAPTER_NONE) + { + /* Restore VGA Wonder registers */ + if (ATIChipHasVGAWonder) + ATIVGAWonderRestore(restore); + + /* Load VGA device */ + ATIVGARestore(restore); + } + + if (ATIChip >= ATI_CHIP_88800GXC) + { + outl(ATIIOPortCRTC_GEN_CNTL, restore->crtc_gen_cntl); + outl(ATIIOPortMEM_VGA_WP_SEL, restore->mem_vga_wp_sel); + outl(ATIIOPortMEM_VGA_RP_SEL, restore->mem_vga_rp_sel); + if (ATIChip >= ATI_CHIP_264CT) + { + outl(ATIIOPortCRTC_OFF_PITCH, restore->crtc_off_pitch); + outl(ATIIOPortDAC_CNTL, restore->dac_cntl); + outl(ATIIOPortCONFIG_CNTL, restore->config_cntl); + outl(ATIIOPortBUS_CNTL, restore->bus_cntl); + } + } + + if (ATIVGAAdapter != ATI_ADAPTER_NONE) + { + /* Give LUT access to CRTC */ + (void) inb(GENS1(vgaIOBase)); + outb(ATTRX, 0x20U); + } + break; + + case ATI_CRTC_MACH64: + /* Load Mach64 CRTC registers */ + ATIMach64Restore(restore); + + if (ATIUsingSmallApertures) + { + /* Oddly enough, these need to be set also, maybe others */ + PutReg(SEQX, 0x02U, restore->std.Sequencer[2]); + PutReg(SEQX, 0x04U, restore->std.Sequencer[4]); + PutReg(GRAX, 0x06U, restore->std.Graphics[6]); + if (ATIChipHasVGAWonder) + ATIModifyExtReg(0xB6, -1, 0x00U, restore->b6); + } + break; + + default: + break; + } + + /* + * Set DSP registers. Note that sequencer resets clear the DSP_CONFIG + * register. + */ + if ((ATIChip >= ATI_CHIP_264VTB) && (ATIIODecoding == BLOCK_IO)) + ATIDSPRestore(restore); + + /* Load RAMDAC */ + ATIDACRestore(restore); + + ATISwap(restore, TRUE); /* Restore video memory */ + + SetTimeSinceLastInputEvent(); + + if ((xf86Verbose > 2) && (restore->mode)) + { + ErrorF("\n After setting mode \"%s\":\n\n", restore->mode->name); + ATIPrintMode(restore->mode); + ATIPrintRegisters(); + } + } *** /dev/null Tue Jun 30 11:48:45 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/aticrtc.h Fri Mar 6 16:46:01 1998 *************** *** 0 **** --- 1,93 ---- + /* $TOG: aticrtc.h /main/1 1998/03/06 16:47:39 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/aticrtc.h,v 1.1.2.1 1998/02/01 16:41:48 robin Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + #ifndef ___ATICRTC_H___ + #define ___ATICRTC_H___ 1 + + #include "atibank.h" + #include "vga.h" + + /* + * CRTC related definitions. + */ + #define ATI_CRTC_VGA 0 /* Use VGA CRTC */ + #define ATI_CRTC_8514 1 /* Use 8514/Mach8/Mach32 accelerator CRTC */ + #define ATI_CRTC_MACH64 2 /* Use Mach64 accelerator CRTC */ + extern CARD8 ATICRTC; + + /* + * Driver data structure. + */ + typedef struct + { + /* Generic VGA registers */ + vgaHWRec std; + + /* Other generic DAC registers */ + CARD8 dac_read, dac_write, dac_mask; + + /* VGA Wonder registers */ + CARD8 a3, a6, a7, ab, ac, ad, ae, + b0, b1, b2, b3, b5, b6, b8, b9, ba, bd, be, bf; + + /* Mach64 registers */ + CARD32 crtc_h_total_disp, crtc_h_sync_strt_wid, + crtc_v_total_disp, crtc_v_sync_strt_wid, + crtc_off_pitch, crtc_gen_cntl, dsp_config, dsp_on_off, + ovr_clr, ovr_wid_left_right, ovr_wid_top_bottom, + clock_cntl, bus_cntl, mem_vga_wp_sel, mem_vga_rp_sel, + dac_cntl, config_cntl; + + /* + * Various things needed by ATISwap: the function to be called by + * ATISelectBank, a pointer to a frame buffer save area and the number + * of banks and planes to contend with. + */ + BankFunction * bank_function; + void * frame_buffer; + unsigned int banks, planes; + + CARD8 crtc; /* VGA, 8514 or Mach64 CRTC */ + DisplayModePtr mode; /* The corresponding mode line */ + const CARD8 *ClockMap; /* Clock map pointers */ + const CARD8 *ClockUnMap; + + /* Parameters for programming clock frequencies */ + int FeedbackDivider, ReferenceDivider, PostDivider; + } ATIHWRec, *ATIHWPtr; + + /* The server's video mode */ + #define ATINewHWPtr ((ATIHWPtr)vgaNewVideoState) + + /* The current video mode */ + extern ATIHWPtr ATICurrentHWPtr; + + extern void * ATISave FunctionPrototype((void *)); + extern Bool ATIInit FunctionPrototype((DisplayModePtr)); + extern void ATIRestore FunctionPrototype((void *)); + + #endif /* ___ATICRTC_H___ */ *** /dev/null Tue Jun 30 11:48:46 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atidac.c Fri Mar 6 16:46:05 1998 *************** *** 0 **** --- 1,243 ---- + /* $TOG: atidac.c /main/1 1998/03/06 16:47:43 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atidac.c,v 1.1.2.1 1998/02/01 16:41:49 robin Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + #include "atidac.h" + #include "atidepth.h" + #include "atiio.h" + #include "atimono.h" + + /* + * RAMDAC-related definitions. + */ + CARD16 ATIDac = ATI_DAC_GENERIC; + const DACRec ATIDACDescriptors[] = + { /* Keep this table in ascending DACType order */ + {ATI_DAC_ATI68830, "ATI 68830 or similar"}, + {ATI_DAC_SC11483, "Sierra 11483 or similar"}, + {ATI_DAC_ATI68875, "ATI 68875 or similar"}, + {ATI_DAC_TVP3026_A, "TI ViewPoint3026 or similar"}, + {ATI_DAC_GENERIC, "Brooktree 476 or similar"}, + {ATI_DAC_BT481, "Brooktree 481 or similar"}, + {ATI_DAC_ATT20C491, "AT&T 20C491 or similar"}, + {ATI_DAC_SC15026, "Sierra 15026 or similar"}, + {ATI_DAC_MU9C1880, "Music 9C1880 or similar"}, + {ATI_DAC_IMSG174, "Inmos G174 or similar"}, + {ATI_DAC_ATI68860_B, "ATI 68860 (Revision B) or similar"}, + {ATI_DAC_ATI68860_C, "ATI 68860 (Revision C) or similar"}, + {ATI_DAC_TVP3026_B, "TI ViewPoint3026 or similar"}, + {ATI_DAC_STG1700, "SGS-Thompson 1700 or similar"}, + {ATI_DAC_ATT20C498, "AT&T 20C498 or similar"}, + {ATI_DAC_STG1702, "SGS-Thompson 1702 or similar"}, + {ATI_DAC_SC15021, "Sierra 15021 or similar"}, + {ATI_DAC_ATT21C498, "AT&T 21C498 or similar"}, + {ATI_DAC_STG1703, "SGS-Thompson 1703 or similar"}, + {ATI_DAC_CH8398, "Chrontel 8398 or similar"}, + {ATI_DAC_ATT20C408, "AT&T 20C408 or similar"}, + {ATI_DAC_INTERNAL, "Internal"}, + {ATI_DAC_IBMRGB514, "IBM RGB 514 or similar"}, + {ATI_DAC_UNKNOWN, "Unknown"} /* Must be last */ + }; + + /* + * ATISetDACIOPorts -- + * + * This function sets up DAC access I/O port numbers. + */ + void + ATISetDACIOPorts(CARD8 crtc) + { + switch (crtc) + { + case ATI_CRTC_VGA: + ATIIOPortDAC_DATA = VGA_DAC_DATA; + ATIIOPortDAC_MASK = VGA_DAC_MASK; + ATIIOPortDAC_READ = VGA_DAC_READ; + ATIIOPortDAC_WRITE = VGA_DAC_WRITE; + break; + + case ATI_CRTC_8514: + ATIIOPortDAC_DATA = DAC_DATA; + ATIIOPortDAC_MASK = DAC_MASK; + ATIIOPortDAC_READ = DAC_R_INDEX; + ATIIOPortDAC_WRITE = DAC_W_INDEX; + break; + + case ATI_CRTC_MACH64: + ATIIOPortDAC_DATA = ATIIOPortDAC_REGS + 1; + ATIIOPortDAC_MASK = ATIIOPortDAC_REGS + 2; + ATIIOPortDAC_READ = ATIIOPortDAC_REGS + 3; + ATIIOPortDAC_WRITE = ATIIOPortDAC_REGS + 0; + break; + + default: + break; + } + } + + /* + * ATIGetMach64DACCmdReg -- + * + * Setup to access a RAMDAC's command register. + */ + CARD8 + ATIGetMach64DACCmdReg(void) + { + (void) inb(ATIIOPortDAC_WRITE); /* Reset to PEL mode */ + (void) inb(ATIIOPortDAC_MASK); /* Get command register */ + (void) inb(ATIIOPortDAC_MASK); + (void) inb(ATIIOPortDAC_MASK); + return inb(ATIIOPortDAC_MASK); + } + + /* + * ATIDACSave -- + * + * This function is called by ATISave to save the current RAMDAC state into an + * ATIHWRec structure occurrence. + */ + void + ATIDACSave(ATIHWPtr save) + { + int Index; + + ATISetDACIOPorts(save->crtc); + + save->dac_read = inb(ATIIOPortDAC_READ); + save->dac_write = inb(ATIIOPortDAC_WRITE); + save->dac_mask = inb(ATIIOPortDAC_MASK); + + /* Save DAC's colour lookup table */ + outb(ATIIOPortDAC_MASK, 0xFFU); + outb(ATIIOPortDAC_READ, 0x00U); + for (Index = 0; Index < NumberOf(save->std.DAC); Index++) + { + save->std.DAC[Index] = inb(ATIIOPortDAC_DATA); + DACDelay; + } + } + + /* + * ATIDACInit -- + * + * This function is called by ATIInit to initialize RAMDAC data in an ATIHWRec + * structure occurrence. + */ + void + ATIDACInit(DisplayModePtr mode) + { + int Index, Index2; + + if (!mode) + { + ATINewHWPtr->dac_read = ATINewHWPtr->dac_write = 0x00U; + ATINewHWPtr->dac_mask = 0xFFU; + + /* + * Set colour lookup table. The first entry has already been zeroed + * out. + */ + if (vga256InfoRec.depth > 8) + for (Index = 1; + Index < (NumberOf(ATINewHWPtr->std.DAC) / 3); + Index++) + { + Index2 = Index * 3; + ATINewHWPtr->std.DAC[Index2 + 0] = + ATINewHWPtr->std.DAC[Index2 + 1] = + ATINewHWPtr->std.DAC[Index2 + 2] = Index; + } + else + { + /* + * Initialize hardware colour map so that use of uninitialized + * software colour map entries can easily be seen. + */ + ATINewHWPtr->std.DAC[3] = + ATINewHWPtr->std.DAC[4] = + ATINewHWPtr->std.DAC[5] = 0xFFU; + for (Index = 2; + Index < NumberOf(ATINewHWPtr->std.DAC) / 3; + Index++) + { + Index2 = Index * 3; + ATINewHWPtr->std.DAC[Index2 + 0] = 0xFFU; + ATINewHWPtr->std.DAC[Index2 + 1] = 0x00U; + ATINewHWPtr->std.DAC[Index2 + 2] = 0xFFU; + } + if (ATIUsing1bppModes) + { + ATINewHWPtr->std.DAC[(MONO_BLACK * 3) + 0] = + vga256InfoRec.blackColour.red; + ATINewHWPtr->std.DAC[(MONO_BLACK * 3) + 1] = + vga256InfoRec.blackColour.green; + ATINewHWPtr->std.DAC[(MONO_BLACK * 3) + 2] = + vga256InfoRec.blackColour.blue; + ATINewHWPtr->std.DAC[(MONO_WHITE * 3) + 0] = + vga256InfoRec.whiteColour.red; + ATINewHWPtr->std.DAC[(MONO_WHITE * 3) + 1] = + vga256InfoRec.whiteColour.green; + ATINewHWPtr->std.DAC[(MONO_WHITE * 3) + 2] = + vga256InfoRec.whiteColour.blue; + } + + if (ATICRTC == ATI_CRTC_VGA) + { + /* Initialize overscan to black */ + Index = ATINewHWPtr->std.Attribute[17] * 3; + ATINewHWPtr->std.DAC[Index + 0] = + ATINewHWPtr->std.DAC[Index + 1] = + ATINewHWPtr->std.DAC[Index + 2] = 0x00U; + } + } + } + } + + /* + * ATIDACRestore -- + * + * This function is called by ATIRestore to load RAMDAC data from an ATIHWRec + * structure occurrence. + */ + void + ATIDACRestore(ATIHWPtr restore) + { + int Index; + + ATISetDACIOPorts(restore->crtc); + + /* Load colour lookup table */ + outb(ATIIOPortDAC_MASK, 0xFFU); + outb(ATIIOPortDAC_WRITE, 0x00U); + for (Index = 0; Index < NumberOf(restore->std.DAC); Index++) + { + outb(ATIIOPortDAC_DATA, restore->std.DAC[Index]); + DACDelay; + } + + outb(ATIIOPortDAC_READ, restore->dac_read); + outb(ATIIOPortDAC_WRITE, restore->dac_write); + } *** /dev/null Tue Jun 30 11:48:47 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atidac.h Fri Mar 6 16:46:09 1998 *************** *** 0 **** --- 1,81 ---- + /* $TOG: atidac.h /main/1 1998/03/06 16:47:47 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atidac.h,v 1.1.2.1 1998/02/01 16:41:49 robin Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + #ifndef ___ATIDAC_H___ + #define ___ATIDAC_H___ 1 + + #include "aticrtc.h" + + /* + * RAMDAC-related definitions. + */ + #define ATI_DAC_MAX_TYPE GetBits(DACTYPE, DACTYPE) + #define ATI_DAC_MAX_SUBTYPE GetBits(BIOS_INIT_DAC_SUBTYPE, \ + BIOS_INIT_DAC_SUBTYPE) + #define ATI_DAC(_Type, _Subtype) (((_Type) << 4) | (_Subtype)) + #define ATI_DAC_ATI68830 ATI_DAC(0x0U, 0x0U) + #define ATI_DAC_SC11483 ATI_DAC(0x1U, 0x0U) + #define ATI_DAC_ATI68875 ATI_DAC(0x2U, 0x0U) + #define ATI_DAC_TVP3026_A ATI_DAC(0x2U, 0x7U) + #define ATI_DAC_GENERIC ATI_DAC(0x3U, 0x0U) + #define ATI_DAC_BT481 ATI_DAC(0x4U, 0x0U) + #define ATI_DAC_ATT20C491 ATI_DAC(0x4U, 0x1U) + #define ATI_DAC_SC15026 ATI_DAC(0x4U, 0x2U) + #define ATI_DAC_MU9C1880 ATI_DAC(0x4U, 0x3U) + #define ATI_DAC_IMSG174 ATI_DAC(0x4U, 0x4U) + #define ATI_DAC_ATI68860_B ATI_DAC(0x5U, 0x0U) + #define ATI_DAC_ATI68860_C ATI_DAC(0x5U, 0x1U) + #define ATI_DAC_TVP3026_B ATI_DAC(0x5U, 0x7U) + #define ATI_DAC_STG1700 ATI_DAC(0x6U, 0x0U) + #define ATI_DAC_ATT20C498 ATI_DAC(0x6U, 0x1U) + #define ATI_DAC_STG1702 ATI_DAC(0x7U, 0x0U) + #define ATI_DAC_SC15021 ATI_DAC(0x7U, 0x1U) + #define ATI_DAC_ATT21C498 ATI_DAC(0x7U, 0x2U) + #define ATI_DAC_STG1703 ATI_DAC(0x7U, 0x3U) + #define ATI_DAC_CH8398 ATI_DAC(0x7U, 0x4U) + #define ATI_DAC_ATT20C408 ATI_DAC(0x7U, 0x5U) + #define ATI_DAC_INTERNAL ATI_DAC(0x8U, 0x0U) + #define ATI_DAC_IBMRGB514 ATI_DAC(0x9U, 0x0U) + #define ATI_DAC_UNKNOWN ATI_DAC((ATI_DAC_MAX_TYPE << 2) + 3, \ + ATI_DAC_MAX_SUBTYPE) + extern CARD16 ATIDac; + typedef struct + { + const int DACType; + const char *DACName; + } DACRec; + extern const DACRec ATIDACDescriptors[]; + + extern CARD8 ATIGetMach64DACCmdReg FunctionPrototype((void)); + + extern void ATISetDACIOPorts FunctionPrototype((CARD8)); + + extern void ATIDACSave FunctionPrototype((ATIHWPtr)); + extern void ATIDACInit FunctionPrototype((DisplayModePtr)); + extern void ATIDACRestore FunctionPrototype((ATIHWPtr)); + + #endif /* ___ATIDAC_H___ */ *** /dev/null Tue Jun 30 11:48:48 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atidepth.h Fri Mar 6 16:46:13 1998 *************** *** 0 **** --- 1,38 ---- + /* $TOG: atidepth.h /main/1 1998/03/06 16:47:51 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atidepth.h,v 1.1.2.1 1998/02/01 16:41:50 robin Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + #ifndef ___ATIDEPTH_H___ + #define ___ATIDEPTH_H___ 1 + + #include "vga.h" + + /* As a temporary measure, I need these in a prominent location */ + #define ATIUsing1bppModes (vga256InfoRec.depth == 1) + #define ATIUsing4bppModes (vga256InfoRec.depth == 4) + #define ATIUsingPlanarModes (vga256InfoRec.depth <= 4) + + #endif /* ___ATIDEPTH_H___ */ *** /dev/null Tue Jun 30 11:48:49 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atidsp.c Fri Mar 6 16:46:17 1998 *************** *** 0 **** --- 1,254 ---- + /* $TOG: atidsp.c /main/1 1998/03/06 16:47:55 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atidsp.c,v 1.1.2.1 1998/02/01 16:41:50 robin Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + #include "atichip.h" + #include "aticlock.h" + #include "atidepth.h" + #include "atidsp.h" + #include "atiio.h" + #include "atividmem.h" + + /* Various memory-related things needed to set DSP registers */ + static int ATIXCLKFeedbackDivider, + ATIXCLKReferenceDivider, + ATIXCLKPostDivider; + + static CARD16 ATIXCLKMaxRASDelay, + ATIXCLKPageFaultDelay, + ATIDisplayLoopLatency, + ATIDisplayFIFODepth; + + /* + * ATIDSPProbe -- + * + * This function initializes global variables used to set DSP registers on a + * VT-B or later. It is called by ATIProbe. + */ + Bool + ATIDSPProbe(void) + { + CARD32 IO_Value; + int trp; + + /* Set DSP register port numbers */ + ATIIOPortDSP_CONFIG = ATIIOPort(DSP_CONFIG); + ATIIOPortDSP_ON_OFF = ATIIOPort(DSP_ON_OFF); + + /* + * VT-B's and later have additional post-dividers that are not powers of + * two. + */ + ATIClockDescriptor->NumD = 8; + + /* Retrieve XCLK settings */ + IO_Value = ATIGetMach64PLLReg(PLL_XCLK_CNTL); + ATIXCLKPostDivider = GetBits(IO_Value, PLL_XCLK_SRC_SEL); + ATIXCLKReferenceDivider = ATIClockDescriptor->MinM; + switch (ATIXCLKPostDivider) + { + case 0: case 1: case 2: case 3: + break; + + case 4: + ATIXCLKReferenceDivider *= 3; + ATIXCLKPostDivider = 0; + break; + + default: + ErrorF("Unsupported XCLK source: %d", ATIXCLKPostDivider); + return FALSE; + } + + ATIXCLKPostDivider -= GetBits(IO_Value, PLL_MFB_TIMES_4_2B); + ATIXCLKFeedbackDivider = ATIGetMach64PLLReg(PLL_MCLK_FB_DIV); + + /* Compute maximum RAS delay and friends */ + IO_Value = inl(ATIIOPortMEM_INFO); + trp = GetBits(IO_Value, CTL_MEM_TRP); + ATIXCLKPageFaultDelay = GetBits(IO_Value, CTL_MEM_TRCD) + + GetBits(IO_Value, CTL_MEM_TCRD) + trp + 2; + ATIXCLKMaxRASDelay = GetBits(IO_Value, CTL_MEM_TRAS) + trp + 2; + ATIDisplayFIFODepth = 32; + + if (ATIChip < ATI_CHIP_264GT3) + { + ATIXCLKPageFaultDelay += 2; + ATIXCLKMaxRASDelay += 3; + ATIDisplayFIFODepth = 24; + } + + switch (ATIMemoryType) + { + case MEM_264_DRAM: + if (ATIvideoRam <= 1024) + ATIDisplayLoopLatency = 10; + else + { + ATIDisplayLoopLatency = 8; + ATIXCLKPageFaultDelay += 2; + } + break; + + case MEM_264_EDO: + case MEM_264_PSEUDO_EDO: + if (ATIvideoRam <= 1024) + ATIDisplayLoopLatency = 9; + else + { + ATIDisplayLoopLatency = 8; + ATIXCLKPageFaultDelay++; + } + break; + + case MEM_264_SDRAM: + if (ATIvideoRam <= 1024) + ATIDisplayLoopLatency = 11; + else + { + ATIDisplayLoopLatency = 10; + ATIXCLKPageFaultDelay++; + } + break; + + case MEM_264_SGRAM: + ATIDisplayLoopLatency = 8; + ATIXCLKPageFaultDelay += 3; + break; + + default: /* Set maximums */ + ATIDisplayLoopLatency = 11; + ATIXCLKPageFaultDelay += 3; + break; + } + + if (ATIXCLKMaxRASDelay <= ATIXCLKPageFaultDelay) + ATIXCLKMaxRASDelay = ATIXCLKPageFaultDelay + 1; + + return TRUE; + } + + /* + * ATIDSPSave -- + * + * This function is called by ATISave() to remember DSP register values on VT-B + * and later controllers. + */ + void + ATIDSPSave(ATIHWPtr save) + { + save->dsp_on_off = inl(ATIIOPortDSP_ON_OFF); + save->dsp_config = inl(ATIIOPortDSP_CONFIG); + } + + + /* + * ATIDSPInit -- + * + * This function sets up DSP register values for a VTB or later. Note that + * this would be slightly different if VCLK 0 or 1 were used for the mode + * instead. In that case, this function would set VGA_DSP_CONFIG and + * VGA_DSP_ON_OFF, would have to zero out DSP_CONFIG and DSP_ON_OFF, and would + * have to consider that VGA_DSP_CONFIG is partitioned slightly differently + * than DSP_CONFIG. + */ + void + ATIDSPInit(void) + { + int Multiplier, Divider; + int dsp_precision, dsp_on, dsp_off, dsp_xclks; + int tmp, vshift, xshift; + + # define Maximum_DSP_PRECISION ((int)GetBits(DSP_PRECISION, DSP_PRECISION)) + + /* Compute a memory-to-screen bandwidth ratio */ + Multiplier = ATINewHWPtr->ReferenceDivider * ATIXCLKFeedbackDivider * + ATIClockDescriptor->PostDividers[ATINewHWPtr->PostDivider]; + Divider = ATINewHWPtr->FeedbackDivider * ATIXCLKReferenceDivider; + if (!ATIUsingPlanarModes) + Divider *= vga256InfoRec.bitsPerPixel / 4; + /* Start by assuming a display FIFO width of 32 bits */ + vshift = (5 - 2) - ATIXCLKPostDivider; + if (ATINewHWPtr->crtc != ATI_CRTC_VGA) + vshift++; /* Nope, it's 64 bits wide */ + + /* Determine dsp_precision first */ + tmp = ATIDivide(Multiplier * ATIDisplayFIFODepth, Divider, vshift, 1); + for (dsp_precision = -5; tmp; dsp_precision++) + tmp >>= 1; + if (dsp_precision < 0) + dsp_precision = 0; + else if (dsp_precision > Maximum_DSP_PRECISION) + dsp_precision = Maximum_DSP_PRECISION; + + xshift = 6 - dsp_precision; + vshift += xshift; + + /* Move on to dsp_off */ + dsp_off = ATIDivide(Multiplier * (ATIDisplayFIFODepth - 1), Divider, + vshift, 1); + + /* Next is dsp_on */ + if ((ATINewHWPtr->crtc == ATI_CRTC_VGA) && (dsp_precision < 3)) + { + /* + * TODO: I don't yet know why something like this appears necessary. + * But I don't have time to explore this right now. + */ + dsp_on = ATIDivide(Multiplier * 5, Divider, vshift + 2, -1); + } + else + { + dsp_on = ATIDivide(Multiplier, Divider, vshift, -1); + tmp = ATIDivide(ATIXCLKMaxRASDelay, 1, xshift, 1); + if (dsp_on < tmp) + dsp_on = tmp; + dsp_on += tmp + ATIDivide(ATIXCLKPageFaultDelay, 1, xshift, 1); + } + + /* Last but not least: dsp_xclks */ + dsp_xclks = ATIDivide(Multiplier, Divider, vshift + 5, 1); + + /* Build DSP register contents */ + ATINewHWPtr->dsp_on_off = SetBits(dsp_on, DSP_ON) | + SetBits(dsp_off, DSP_OFF); + ATINewHWPtr->dsp_config = SetBits(dsp_precision, DSP_PRECISION) | + SetBits(dsp_xclks, DSP_XCLKS_PER_QW) | + SetBits(ATIDisplayLoopLatency, DSP_LOOP_LATENCY); + } + + /* + * ATIDSPRestore -- + * + * This function is called by ATIRestore to set DSP registers on VT-B and later + * controllers. + */ + void + ATIDSPRestore(ATIHWPtr restore) + { + outl(ATIIOPortDSP_ON_OFF, restore->dsp_on_off); + outl(ATIIOPortDSP_CONFIG, restore->dsp_config); + } *** /dev/null Tue Jun 30 11:48:51 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atidsp.h Fri Mar 6 16:46:21 1998 *************** *** 0 **** --- 1,38 ---- + /* $TOG: atidsp.h /main/1 1998/03/06 16:47:59 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atidsp.h,v 1.1.2.1 1998/02/01 16:41:51 robin Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + #ifndef ___ATIDSP_H___ + #define ___ATIDSP_H___ 1 + + #include "aticrtc.h" + + extern Bool ATIDSPProbe FunctionPrototype((void)); + extern void ATIDSPSave FunctionPrototype((ATIHWPtr)); + extern void ATIDSPInit FunctionPrototype((void)); + extern void ATIDSPRestore FunctionPrototype((ATIHWPtr)); + + #endif /* ___ATIDSP_H___ */ *** /dev/null Tue Jun 30 11:48:52 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atifbinit.c Fri Mar 6 16:46:25 1998 *************** *** 0 **** --- 1,38 ---- + /* $TOG: atifbinit.c /main/1 1998/03/06 16:48:03 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atifbinit.c,v 1.1.2.1 1998/02/01 16:41:52 robin Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + #include "atifbinit.h" + + /* + * ATIFbInit -- + * + * This is only a dummy placeholder, for now. + */ + void + ATIFbInit(void) + { + } *** /dev/null Tue Jun 30 11:48:53 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atifbinit.h Fri Mar 6 16:46:29 1998 *************** *** 0 **** --- 1,35 ---- + /* $TOG: atifbinit.h /main/1 1998/03/06 16:48:07 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atifbinit.h,v 1.1.2.1 1998/02/01 16:41:52 robin Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + #ifndef ___ATIFBINIT_H___ + #define ___ATIFBINIT_H___ 1 + + #include "atiproto.h" + + extern void ATIFbInit FunctionPrototype((void)); + + #endif /* ___ATIFBINIT_H___ */ *** /dev/null Tue Jun 30 11:48:54 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atigetmode.c Fri Mar 6 16:46:33 1998 *************** *** 0 **** --- 1,280 ---- + /* $TOG: atigetmode.c /main/1 1998/03/06 16:48:11 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atigetmode.c,v 1.1.2.1 1998/02/01 16:41:53 robin Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + #include "atiadapter.h" + #include "atichip.h" + #include "aticlock.h" + #include "aticonsole.h" + #include "atigetmode.h" + #include "atiio.h" + + /* + * ATIGetMode -- + * + * This function will read the current SVGA register settings and produce a + * filled-in DisplayModeRec containing the current mode. + */ + void + ATIGetMode(DisplayModePtr mode) + { + int ShiftCount = 0; + CARD8 misc; + CARD8 crt00, crt01, crt03, crt04, crt05, crt06, crt07, crt09, + crt10, crt11, crt12, crt17; + CARD8 a6 = 0, a7 = 0, ac = 0, + b0 = 0, b1 = 0, b2 = 0, b5 = 0, b8 = 0, b9 = 0, bd = 0, be = 0; + CARD8 crtc_gen_cntl0 = 0; + + /* + * Unlock registers. + */ + ATIEnterLeave(ENTER); + + /* Initialize */ + mode->Clock = 0; + + /* + * First, get the needed register values. + */ + misc = inb(R_GENMO); + ATISetVGAIOBase(misc); + + crt00 = GetReg(CRTX(vgaIOBase), 0x00U); + crt01 = GetReg(CRTX(vgaIOBase), 0x01U); + crt03 = GetReg(CRTX(vgaIOBase), 0x03U); + crt04 = GetReg(CRTX(vgaIOBase), 0x04U); + crt05 = GetReg(CRTX(vgaIOBase), 0x05U); + crt06 = GetReg(CRTX(vgaIOBase), 0x06U); + crt07 = GetReg(CRTX(vgaIOBase), 0x07U); + crt09 = GetReg(CRTX(vgaIOBase), 0x09U); + crt10 = GetReg(CRTX(vgaIOBase), 0x10U); + crt11 = GetReg(CRTX(vgaIOBase), 0x11U); + crt12 = GetReg(CRTX(vgaIOBase), 0x12U); + crt17 = GetReg(CRTX(vgaIOBase), 0x17U); + + if (ATIChip >= ATI_CHIP_264CT) + crtc_gen_cntl0 = inb(ATIIOPortCRTC_GEN_CNTL); + + if (ATIChipHasVGAWonder) + { + b0 = ATIGetExtReg(0xB0U); + b1 = ATIGetExtReg(0xB1U); + b5 = ATIGetExtReg(0xB5U); + b8 = ATIGetExtReg(0xB8U); + b9 = ATIGetExtReg(0xB9U); + bd = ATIGetExtReg(0xBDU); + if (ATIChip <= ATI_CHIP_18800) + b2 = ATIGetExtReg(0xB2U); + else + { + be = ATIGetExtReg(0xBEU); + if (ATIChip >= ATI_CHIP_28800_2) + { + a6 = ATIGetExtReg(0xA6U); + a7 = ATIGetExtReg(0xA7U); + ac = ATIGetExtReg(0xACU); + } + } + + /* Set clock number */ + mode->Clock = (b8 & 0xC0U) >> 3; /* Clock divider */ + if (ATIChip <= ATI_CHIP_18800) + mode->Clock |= (b2 & 0x40U) >> 4; + else + { + if (ATIAdapter != ATI_ADAPTER_V4) + { + mode->Clock |= (b9 & 0x02U) << 1; + mode->Clock <<= 1; + } + mode->Clock |= (be & 0x10U) >> 2; + } + } + mode->Clock |= (misc & 0x0CU) >> 2; /* VGA clock select */ + mode->Clock = ATIClockUnMap[mode->Clock & 0x0FU] | (mode->Clock & ~0x0FU); + if (ATIProgrammableClock == ATI_CLOCK_FIXED) + mode->SynthClock = vga256InfoRec.clock[mode->Clock]; + else + /* + * TODO: Read clock generator registers. But this'll do for now. + */ + mode->SynthClock = ATIDivide(ATIBIOSClocks[mode->Clock & 0x0FU] * 10, + (mode->Clock >> 4) + 1, 0, 0); + + /* + * Set horizontal display end. + */ + mode->CrtcHDisplay = crt01; + mode->HDisplay = (crt01 + 1) << 3; + + /* + * Set horizontal synch pulse start. + */ + mode->CrtcHSyncStart = crt04; + mode->HSyncStart = crt04 << 3; + + /* + * Set horizontal synch pulse end. + */ + crt05 = (crt04 & 0xE0U) | (crt05 & 0x1FU); + if (crt05 <= crt04) + crt05 += 0x20U; + mode->CrtcHSyncEnd = crt05; + mode->HSyncEnd = crt05 << 3; + + /* + * Set horizontal total. + */ + mode->CrtcHTotal = crt00; + mode->HTotal = (crt00 + 5) << 3; + + /* + * Set horizontal display enable skew. + */ + mode->HSkew = (crt03 & 0x60U) >> 2; + if (ATIChipHasVGAWonder) + { + /* Assume ATI extended VGA registers override standard VGA */ + if (b5 & 0x01U) + mode->HSkew = 1; + if (b0 & 0x01U) + mode->HSkew = 1 << 3; + if (a6 & 0x01U) + mode->HSkew = 2 << 3; + if (a7 & 0x40U) + mode->HSkew = 4 << 3; + if (ac & 0x10U) + mode->HSkew = 5 << 3; + if (ac & 0x20U) + mode->HSkew = 6 << 3; + } + mode->CrtcHSkew = mode->HSkew; + + mode->CrtcHAdjusted = TRUE; + + /* + * Set vertical display end. + */ + mode->CrtcVDisplay = ((crt07 & 0x40U) << 3) | ((crt07 & 0x02U) << 7) | + crt12; + mode->VDisplay = mode->CrtcVDisplay + 1; + + /* + * Set vertical synch pulse start. + */ + mode->CrtcVSyncStart = mode->VSyncStart = ((crt07 & 0x80U) << 2) | + ((crt07 & 0x04U) << 6) | crt10; + + /* + * Set vertical synch pulse end. + */ + mode->VSyncEnd = (mode->VSyncStart & 0x3F0U) | (crt11 & 0x0FU); + if (mode->VSyncEnd <= mode->VSyncStart) + mode->VSyncEnd += 0x10U; + mode->CrtcVSyncEnd = mode->VSyncEnd; + + /* + * Set vertical total. + */ + mode->CrtcVTotal = ((crt07 & 0x20U) << 4) | ((crt07 & 0x01U) << 8) | crt06; + mode->VTotal = mode->CrtcVTotal + 2; + + mode->CrtcVAdjusted = TRUE; + + /* + * Set flags. + */ + if (misc & 0x40U) + mode->Flags = V_NHSYNC; + else + mode->Flags = V_PHSYNC; + if (misc & 0x80U) + mode->Flags |= V_NVSYNC; + else + mode->Flags |= V_PVSYNC; + /* + * Triple-, quad-, etc scans not yet supported. + */ + if (crt09 & 0x9FU) + mode->Flags |= V_DBLSCAN; + if (mode->HSkew) + mode->Flags |= V_HSKEW; + if (ATIChipHasVGAWonder) + { + if (ATIChip <= ATI_CHIP_18800) + { + if (b2 & 0x01U) + mode->Flags |= V_INTERLACE; + } + else + { + if (be & 0x02U) + mode->Flags |= V_INTERLACE; + } + if (b1 & 0x08U) + mode->Flags |= V_DBLSCAN; + if ((bd & 0x09U) == 0x09U) + mode->Flags |= V_NCSYNC; + else if (bd & 0x08U) + mode->Flags |= V_PCSYNC; + } + if (ATIChip >= ATI_CHIP_264CT) + { + if (crtc_gen_cntl0 & CRTC_DBL_SCAN_EN) + mode->Flags |= V_DBLSCAN; + if (crtc_gen_cntl0 & CRTC_INTERLACE_EN) + mode->Flags |= V_INTERLACE; + if (crtc_gen_cntl0 & CRTC_CSYNC_EN) + mode->Flags |= V_PCSYNC; + } + + /* + * Adjust vertical timings. + */ + if ((ATIChip < ATI_CHIP_264CT) && (mode->Flags & V_INTERLACE)) + ShiftCount++; + if (mode->Flags & V_DBLSCAN) + ShiftCount--; + if (b1 & 0x40U) + ShiftCount--; + if (crt17 & 0x04U) + ShiftCount++; + if (ShiftCount > 0) + { + mode->VDisplay <<= ShiftCount; + mode->VSyncStart <<= ShiftCount; + mode->VSyncEnd <<= ShiftCount; + mode->VTotal <<= ShiftCount; + } + else if (ShiftCount < 0) + { + mode->VDisplay >>= -ShiftCount; + mode->VSyncStart >>= -ShiftCount; + mode->VSyncEnd >>= -ShiftCount; + mode->VTotal >>= -ShiftCount; + } + } *** /dev/null Tue Jun 30 11:48:55 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atigetmode.h Fri Mar 6 16:46:37 1998 *************** *** 0 **** --- 1,36 ---- + /* $TOG: atigetmode.h /main/1 1998/03/06 16:48:15 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atigetmode.h,v 1.1.2.1 1998/02/01 16:41:53 robin Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + #ifndef ___ATIGETMODE_H___ + #define ___ATIGETMODE_H___ 1 + + #include "atiproto.h" + #include "xf86.h" + + extern void ATIGetMode FunctionPrototype((DisplayModePtr)); + + #endif /* ___ATIGETMODE_H___ */ *** /dev/null Tue Jun 30 11:48:57 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atiident.c Fri Mar 6 16:46:41 1998 *************** *** 0 **** --- 1,102 ---- + /* $TOG: atiident.c /main/1 1998/03/06 16:48:19 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atiident.c,v 1.1.2.1 1998/02/01 16:41:54 robin Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + #include "atiident.h" + #include "atiutil.h" + #include "vga.h" + #include "xf86_OSproc.h" + #include "xf86Priv.h" + + #define XCONFIG_FLAGS_ONLY + #include "xf86_Config.h" + + CARD8 ATIChipSet = ATI_CHIPSET_ATI; + + char *ATIChipSetNames[] = + { + "ati", /* "Full-blown" ATI support */ + "ativga", /* Don't use ATI accelerator */ + "ibmvga", /* Generic VGA */ + #if 0 + "ibm8514", /* IBM 8514/A */ + #endif + }; + + /* + * ATIIdent -- + * + * Returns a string name for this driver or NULL. + */ + char * + ATIIdent(int n) + { + #if 1 + /* For now, don't advertise non-default chipset names */ + if (n != ATI_CHIPSET_ATI) + #else + if ((n < 0) || (n >= NumberOf(ATIChipSetNames))) + #endif + return NULL; + else + return ATIChipSetNames[n]; + } + + /* + * ATIIdentProbe -- + * + * This function determines if the user specified a chipset name acceptable to + * this driver, and, if so, sets ATIChipSet accordingly. + */ + Bool + ATIIdentProbe(void) + { + int Index; + static const char *LegacyNames[] = + {"vgawonder", "mach8", "mach32", "mach64"}; + + /* Let ATIProbe continue if no chipset is specified */ + if (!vga256InfoRec.chipset) + return TRUE; + + for (; ATIChipSet < NumberOf(ATIChipSetNames); ATIChipSet++) + if (!StrCaseCmp(vga256InfoRec.chipset, ATIChipSetNames[ATIChipSet])) + return TRUE; + + /* Reset to default */ + ATIChipSet = ATI_CHIPSET_ATI; + + /* Check for some other chipset names that need changing */ + for (Index = 0; StrCaseCmp(vga256InfoRec.chipset, LegacyNames[Index]); ) + if (++Index >= NumberOf(LegacyNames)) + return FALSE; + + if (xf86Verbose) + ErrorF("XF86Config ChipSet specification changed from \"%s\" to" + " \"%s\".\n", LegacyNames[Index], ATIChipSetNames[ATIChipSet]); + OFLG_CLR(XCONFIG_CHIPSET, &vga256InfoRec.xconfigFlag); + return TRUE; + } *** /dev/null Tue Jun 30 11:48:58 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atiident.h Fri Mar 6 16:46:45 1998 *************** *** 0 **** --- 1,44 ---- + /* $TOG: atiident.h /main/1 1998/03/06 16:48:23 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atiident.h,v 1.1.2.1 1998/02/01 16:41:55 robin Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + #ifndef ___ATIIDENT_H___ + #define ___ATIIDENT_H___ 1 + + #include "atiproto.h" + #include "misc.h" + + #define ATI_CHIPSET_ATI 0 + #define ATI_CHIPSET_ATIVGA 1 + #define ATI_CHIPSET_IBMVGA 2 + #define ATI_CHIPSET_IBM8514 3 /* ? */ + extern CARD8 ATIChipSet; + extern char * ATIChipSetNames[]; + + extern char * ATIIdent FunctionPrototype((int)); + extern Bool ATIIdentProbe FunctionPrototype((void)); + + #endif /* ___ATIIDENT_H___ */ *** /dev/null Tue Jun 30 11:48:59 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atiio.c Fri Mar 6 16:46:49 1998 *************** *** 0 **** --- 1,133 ---- + /* $TOG: atiio.c /main/1 1998/03/06 16:48:26 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atiio.c,v 1.1.2.1 1998/02/01 16:41:56 robin Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + #include "atichip.h" + #include "atiio.h" + #include "vga.h" + + /* The following are port numbers that are determined by ATIProbe */ + CARD16 ATIIOPortVGAWonder = 0x01CEU; + + CARD16 ATIIOPortCRTC_H_TOTAL_DISP, ATIIOPortCRTC_H_SYNC_STRT_WID, + ATIIOPortCRTC_V_TOTAL_DISP, ATIIOPortCRTC_V_SYNC_STRT_WID, + ATIIOPortCRTC_OFF_PITCH, ATIIOPortCRTC_INT_CNTL, ATIIOPortCRTC_GEN_CNTL, + ATIIOPortDSP_CONFIG, ATIIOPortDSP_ON_OFF, ATIIOPortOVR_CLR, + ATIIOPortOVR_WID_LEFT_RIGHT, ATIIOPortOVR_WID_TOP_BOTTOM, + ATIIOPortCLOCK_CNTL, ATIIOPortBUS_CNTL, ATIIOPortMEM_INFO, + ATIIOPortMEM_VGA_WP_SEL, ATIIOPortMEM_VGA_RP_SEL, + ATIIOPortDAC_REGS, ATIIOPortDAC_CNTL, + ATIIOPortGEN_TEST_CNTL, ATIIOPortCONFIG_CNTL; + + /* These port numbers are to be determined by ATISave & ATIRestore */ + CARD16 ATIIOPortDAC_MASK, ATIIOPortDAC_DATA, + ATIIOPortDAC_READ, ATIIOPortDAC_WRITE; + + /* I/O decoding definitions */ + CARD16 ATIIOBase; + CARD8 ATIIODecoding; + + CARD8 ATIB2Reg = 0; /* The B2 mirror */ + CARD8 ATIVGAOffset = 0x80U; /* Low index for ATIIOPortVGAWonder */ + + /* + * ATISetVGAIOBase -- + * + * This sets vgaIOBase according to the value of the passed value of the + * miscellaneous output register. + */ + void + ATISetVGAIOBase(const CARD8 misc) + { + vgaIOBase = (misc & 0x01U) ? ColourIOBase : MonochromeIOBase; + } + + /* + * ATIModifyExtReg -- + * + * This function is called to modify certain bits in an ATI extended VGA + * register while preserving its other bits. The function will not write the + * register if it turns out its value would not change. This helps prevent + * server hangs on older adapters. + */ + void + ATIModifyExtReg(const CARD8 Index, int Current_Value, + const CARD8 Current_Mask, CARD8 New_Value) + { + /* Possibly retrieve the current value */ + if (Current_Value < 0) + Current_Value = ATIGetExtReg(Index); + + /* Compute new value */ + New_Value &= (CARD8)(~Current_Mask); + New_Value |= Current_Value & Current_Mask; + + /* Check if value will be changed */ + if (Current_Value == New_Value) + return; + + /* + * The following is taken from ATI's VGA Wonder programmer's reference + * manual which says that this is needed to "ensure the proper state of the + * 8/16 bit ROM toggle". I suspect a timing glitch appeared in the 18800 + * after its die was cast. 18800-1 and later chips do not exhibit this + * problem. + */ + if ((ATIChip <= ATI_CHIP_18800) && (Index == 0xB2U) && + ((New_Value ^ 0x40U) & Current_Value & 0x40U)) + { + CARD8 misc = inb(R_GENMO); + CARD8 bb = ATIGetExtReg(0xBBU); + + outb(GENMO, (misc & 0xF3U) | 0x04U | ((bb & 0x10U) >> 1)); + Current_Value &= (CARD8)(~0x40U); + ATIPutExtReg(0xB2U, Current_Value); + ATIDelay(5); + outb(GENMO, misc); + ATIDelay(5); + if (Current_Value != New_Value) + ATIPutExtReg(0xB2U, New_Value); + } + else + ATIPutExtReg(Index, New_Value); + } + + /* + * ATIAccessMach64PLLReg -- + * + * This function sets up the addressing required to access, for read or write, + * a 264xT's PLL registers. + */ + void + ATIAccessMach64PLLReg(const CARD8 Index, const Bool Write) + { + CARD8 clock_cntl1 = inb(ATIIOPortCLOCK_CNTL + 1) & + ~GetByte(PLL_WR_EN | PLL_ADDR, 1); + + /* Set PLL register to be read or written */ + outb(ATIIOPortCLOCK_CNTL + 1, clock_cntl1 | + GetByte(SetBits(Index, PLL_ADDR) | SetBits(Write, PLL_WR_EN), 1)); + } *** /dev/null Tue Jun 30 11:49:00 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atiio.h Fri Mar 6 16:46:53 1998 *************** *** 0 **** --- 1,127 ---- + /* $TOG: atiio.h /main/1 1998/03/06 16:48:30 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atiio.h,v 1.1.2.1 1998/02/01 16:41:56 robin Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + #ifndef ___ATIIO_H___ + #define ___ATIIO_H___ 1 + + #include "atiregs.h" + #include "compiler.h" + #include "misc.h" + + /* The following are port numbers that are determined by ATIProbe */ + extern CARD16 ATIIOPortVGAWonder; + + extern CARD16 ATIIOPortCRTC_H_TOTAL_DISP, ATIIOPortCRTC_H_SYNC_STRT_WID, + ATIIOPortCRTC_V_TOTAL_DISP, ATIIOPortCRTC_V_SYNC_STRT_WID, + ATIIOPortCRTC_OFF_PITCH,ATIIOPortCRTC_INT_CNTL, + ATIIOPortCRTC_GEN_CNTL, ATIIOPortDSP_CONFIG, ATIIOPortDSP_ON_OFF, + ATIIOPortOVR_CLR, + ATIIOPortOVR_WID_LEFT_RIGHT, ATIIOPortOVR_WID_TOP_BOTTOM, + ATIIOPortCLOCK_CNTL, ATIIOPortBUS_CNTL, ATIIOPortMEM_INFO, + ATIIOPortMEM_VGA_WP_SEL, ATIIOPortMEM_VGA_RP_SEL, + ATIIOPortDAC_REGS, ATIIOPortDAC_CNTL, + ATIIOPortGEN_TEST_CNTL, ATIIOPortCONFIG_CNTL; + + /* These port numbers are determined by ATISave & ATIRestore */ + extern CARD16 ATIIOPortDAC_MASK, ATIIOPortDAC_DATA, + ATIIOPortDAC_READ, ATIIOPortDAC_WRITE; + + /* I/O decoding definitions */ + #define SPARSE_IO 0 + #define BLOCK_IO 1 + extern CARD16 ATIIOBase; + extern CARD8 ATIIODecoding; + #define ATIIOPort(_PortTag) \ + (((ATIIODecoding == SPARSE_IO) ? \ + (((_PortTag) & SPARSE_IO_SELECT) | ((_PortTag) & IO_BYTE_SELECT)) : \ + (((_PortTag) & BLOCK_IO_SELECT) | ((_PortTag) & IO_BYTE_SELECT))) | \ + ATIIOBase) + + extern CARD8 ATIB2Reg; /* The B2 mirror */ + extern CARD8 ATIVGAOffset; /* Low index for ATIIOPortVGAWonder */ + + extern void ATISetVGAIOBase FunctionPrototype((const CARD8)); + extern void ATIModifyExtReg FunctionPrototype((const CARD8, int, const CARD8, + CARD8)); + + /* Odds and ends to ease reading and writting of registers */ + #define GetReg(_Register, _Index) \ + ( \ + outb(_Register, _Index), \ + inb(_Register + 1) \ + ) + #define PutReg(_Register, _Index, _Value) \ + outw(_Register, ((_Value) << 8) | (_Index)) + #define ATIGetExtReg(_Index) \ + GetReg(ATIIOPortVGAWonder, _Index) + #define ATIPutExtReg(_Index, _Value) \ + PutReg(ATIIOPortVGAWonder, _Index, _Value) + + extern void ATIAccessMach64PLLReg FunctionPrototype((const CARD8, const Bool)); + + #define ATIGetMach64PLLReg(_Index) \ + ( \ + ATIAccessMach64PLLReg(_Index, FALSE), \ + inb(ATIIOPortCLOCK_CNTL + 2) \ + ) + #define ATIPutMach64PLLReg(_Index, _Value) \ + ( \ + ATIAccessMach64PLLReg(_Index, TRUE), \ + outb(ATIIOPortCLOCK_CNTL + 2, _Value) \ + ) + + /* Wait until "n" queue entries are free */ + #define ibm8514WaitQueue(_n) \ + { \ + while (inw(GP_STAT) & (0x0100U >> (_n))); \ + } + #define ATIWaitQueue(_n) \ + { \ + while (inw(EXT_FIFO_STATUS) & (0x10000U >> (_n))); \ + } + + /* Wait until GP is idle and queue is empty */ + #define WaitIdleEmpty() \ + { \ + while (inw(GP_STAT) & (GPBUSY | 1)); \ + } + #define ProbeWaitIdleEmpty() \ + { \ + int i; \ + for (i = 0; i < 100000; i++) \ + if (!(inw(GP_STAT) & (GPBUSY | 1))) \ + break; \ + } + + /* Wait until GP has data available */ + #define WaitDataReady() \ + { \ + while (!(inw(GP_STAT) & DATARDY)); \ + } + + + #endif /* ___ATIIO_H___ */ *** /dev/null Tue Jun 30 11:49:02 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atimach64.c Fri Mar 6 16:46:56 1998 *************** *** 0 **** --- 1,304 ---- + /* $TOG: atimach64.c /main/1 1998/03/06 16:48:35 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atimach64.c,v 1.1.2.1 1998/02/01 16:41:57 robin Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + #include "ati.h" + #include "atibus.h" + #include "atichip.h" + #include "aticlock.h" + #include "atiio.h" + #include "atimach64.h" + #include "atividmem.h" + + /* + * ATIMach64Save -- + * + * This function is called to save a video mode that uses a Mach64 + * accelerator's CRTC. + */ + void + ATIMach64Save(ATIHWPtr save) + { + save->crtc_h_total_disp = inl(ATIIOPortCRTC_H_TOTAL_DISP); + save->crtc_h_sync_strt_wid = inl(ATIIOPortCRTC_H_SYNC_STRT_WID); + save->crtc_v_total_disp = inl(ATIIOPortCRTC_V_TOTAL_DISP); + save->crtc_v_sync_strt_wid = inl(ATIIOPortCRTC_V_SYNC_STRT_WID); + + save->crtc_off_pitch = inl(ATIIOPortCRTC_OFF_PITCH); + + save->ovr_clr = inl(ATIIOPortOVR_CLR); + save->ovr_wid_left_right = inl(ATIIOPortOVR_WID_LEFT_RIGHT); + save->ovr_wid_top_bottom = inl(ATIIOPortOVR_WID_TOP_BOTTOM); + + save->clock_cntl = inl(ATIIOPortCLOCK_CNTL); + + save->bus_cntl = inl(ATIIOPortBUS_CNTL); + + save->mem_vga_wp_sel = inl(ATIIOPortMEM_VGA_WP_SEL); + save->mem_vga_rp_sel = inl(ATIIOPortMEM_VGA_RP_SEL); + + save->dac_cntl = inl(ATIIOPortDAC_CNTL); + + save->config_cntl = inl(ATIIOPortCONFIG_CNTL); + } + + /* + * ATIMach64Init -- + * + * This function fills in the Mach64 portion of an ATIHWRec. + */ + void + ATIMach64Init(DisplayModePtr mode) + { + if (!mode) /* Fill in common data */ + { + ATINewHWPtr->crtc_off_pitch = + SetBits(vga256InfoRec.displayWidth >> 3, CRTC_PITCH); + + ATINewHWPtr->bus_cntl = (inl(ATIIOPortBUS_CNTL) & + ~BUS_HOST_ERR_INT_EN) | BUS_HOST_ERR_INT; + if (ATIChip < ATI_CHIP_264VTB) + ATINewHWPtr->bus_cntl = (ATINewHWPtr->bus_cntl & + ~(BUS_FIFO_ERR_INT_EN | BUS_ROM_DIS)) | + (SetBits(15, BUS_FIFO_WS) | BUS_FIFO_ERR_INT); + else + ATINewHWPtr->bus_cntl |= BUS_APER_REG_DIS; + + ATINewHWPtr->dac_cntl = inl(ATIIOPortDAC_CNTL); + if (vga256InfoRec.depth > 8) + ATINewHWPtr->dac_cntl |= DAC_8BIT_EN; + else + ATINewHWPtr->dac_cntl &= ~DAC_8BIT_EN; + + ATINewHWPtr->config_cntl = inl(ATIIOPortCONFIG_CNTL); + if (ATIUsingSmallApertures) + ATINewHWPtr->config_cntl |= CFG_MEM_VGA_AP_EN; + else + ATINewHWPtr->config_cntl &= ~CFG_MEM_VGA_AP_EN; + if (ATI.ChipUseLinearAddressing && (ATIBusType != ATI_BUS_PCI)) + { + /* Replace linear aperture size and address */ + ATINewHWPtr->config_cntl &= ~(CFG_MEM_AP_LOC | CFG_MEM_AP_SIZE); + ATINewHWPtr->config_cntl |= + SetBits(ATI.ChipLinearBase >> 22, CFG_MEM_AP_LOC); + if ((ATIChip < ATI_CHIP_264CT) && (ATIvideoRam < 4096)) + ATINewHWPtr->config_cntl |= SetBits(1, CFG_MEM_AP_SIZE); + else + ATINewHWPtr->config_cntl |= SetBits(2, CFG_MEM_AP_SIZE); + } + } + else + { + /* Adjust mode timings and fill in mode-specific data */ + if (!mode->CrtcHAdjusted) + { + mode->CrtcHAdjusted = TRUE; + mode->CrtcHDisplay >>= 3; + mode->CrtcHSyncStart >>= 3; + mode->CrtcHSyncEnd >>= 3; + mode->CrtcHTotal >>= 3; + mode->CrtcHDisplay--; + mode->CrtcHSyncStart--; + mode->CrtcHSyncEnd--; + mode->CrtcHTotal--; + /* Make adjustments if sync width is out-of-bounds */ + if ((mode->CrtcHSyncEnd - mode->CrtcHSyncStart) > + (int)GetBits(CRTC_H_SYNC_WID, CRTC_H_SYNC_WID)) + mode->CrtcHSyncEnd = mode->CrtcHSyncStart + + GetBits(CRTC_H_SYNC_WID, CRTC_H_SYNC_WID); + else if (mode->CrtcHSyncStart == mode->CrtcHSyncEnd) + if (mode->CrtcHDisplay < mode->CrtcHSyncStart) + mode->CrtcHSyncStart--; + else if (mode->CrtcHSyncEnd < mode->CrtcHTotal) + mode->CrtcHSyncEnd++; + } + + /* + * Ignore any vertical adjustments that have already been made. + * Doing so fixes a minor bug in doublescanned modes. + */ + mode->CrtcVDisplay = mode->VDisplay; + mode->CrtcVSyncStart = mode->VSyncStart; + mode->CrtcVSyncEnd = mode->VSyncEnd; + mode->CrtcVTotal = mode->VTotal; + + if ((mode->Flags & V_DBLSCAN) && (ATIChip >= ATI_CHIP_264CT)) + { + mode->CrtcVDisplay <<= 1; + mode->CrtcVSyncStart <<= 1; + mode->CrtcVSyncEnd <<= 1; + mode->CrtcVTotal <<= 1; + } + mode->CrtcVDisplay--; + mode->CrtcVSyncStart--; + mode->CrtcVSyncEnd--; + mode->CrtcVTotal--; + /* Make sure sync pulse is not too wide */ + if ((mode->CrtcVSyncEnd - mode->CrtcVSyncStart) > + (int)GetBits(CRTC_V_SYNC_WID, CRTC_V_SYNC_WID)) + mode->CrtcVSyncEnd = mode->CrtcVSyncStart + + GetBits(CRTC_V_SYNC_WID, CRTC_V_SYNC_WID); + mode->CrtcVAdjusted = TRUE; + + /* + * Might as well default to the same as VGA with respect to sync + * polarities. + */ + if ((!(mode->Flags & (V_PHSYNC | V_NHSYNC))) || + (!(mode->Flags & (V_PVSYNC | V_NVSYNC)))) + { + mode->Flags &= ~(V_PHSYNC | V_NHSYNC | V_PVSYNC | V_NVSYNC); + + if (mode->CrtcVDisplay < (400 - 1)) + mode->Flags |= V_PHSYNC | V_NVSYNC; + else if (mode->CrtcVDisplay < (480 - 1)) + mode->Flags |= V_NHSYNC | V_PVSYNC; + else if (mode->CrtcVDisplay < (768 - 1)) + mode->Flags |= V_NHSYNC | V_NVSYNC; + else + mode->Flags |= V_PHSYNC | V_PVSYNC; + } + + /* Build register contents */ + ATINewHWPtr->crtc_h_total_disp = + SetBits(mode->CrtcHTotal, CRTC_H_TOTAL) | + SetBits(mode->CrtcHDisplay, CRTC_H_DISP); + ATINewHWPtr->crtc_h_sync_strt_wid = + SetBits(mode->CrtcHSyncStart, CRTC_H_SYNC_STRT) | + SetBits(mode->CrtcHSkew, CRTC_H_SYNC_DLY) | /* ? */ + SetBits(GetBits(mode->CrtcHSyncStart, 0x0100U), + CRTC_H_SYNC_STRT_HI) | + SetBits(mode->CrtcHSyncEnd - mode->CrtcHSyncStart, + CRTC_H_SYNC_WID); + if (mode->Flags & V_NHSYNC) + ATINewHWPtr->crtc_h_sync_strt_wid |= CRTC_H_SYNC_POL; + + ATINewHWPtr->crtc_v_total_disp = + SetBits(mode->CrtcVTotal, CRTC_V_TOTAL) | + SetBits(mode->CrtcVDisplay, CRTC_V_DISP); + ATINewHWPtr->crtc_v_sync_strt_wid = + SetBits(mode->CrtcVSyncStart, CRTC_V_SYNC_STRT) | + SetBits(mode->CrtcVSyncEnd - mode->CrtcVSyncStart, + CRTC_V_SYNC_WID); + if (mode->Flags & V_NVSYNC) + ATINewHWPtr->crtc_v_sync_strt_wid |= CRTC_V_SYNC_POL; + + ATINewHWPtr->crtc_gen_cntl = inl(ATIIOPortCRTC_GEN_CNTL) & + ~(CRTC_DBL_SCAN_EN | CRTC_INTERLACE_EN | + CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_CSYNC_EN | + CRTC_PIX_BY_2_EN | CRTC_DISPLAY_DIS | CRTC_VGA_XOVERSCAN | + CRTC_PIX_WIDTH | CRTC_BYTE_PIX_ORDER | CRTC_FIFO_LWM | + CRTC_VGA_128KAP_PAGING | CRTC_VFC_SYNC_TRISTATE | + CRTC_LOCK_REGS | /* Already off, but ... */ + CRTC_SYNC_TRISTATE | CRTC_DISP_REQ_EN | + CRTC_VGA_TEXT_132 | CRTC_CUR_B_TEST); + ATINewHWPtr->crtc_gen_cntl |= CRTC_EXT_DISP_EN | CRTC_EN | + CRTC_VGA_LINEAR | CRTC_CNT_EN; + switch (vga256InfoRec.depth) + { + case 1: + ATINewHWPtr->crtc_gen_cntl |= CRTC_PIX_WIDTH_1BPP; + break; + case 4: + ATINewHWPtr->crtc_gen_cntl |= CRTC_PIX_WIDTH_4BPP; + break; + case 8: + ATINewHWPtr->crtc_gen_cntl |= CRTC_PIX_WIDTH_8BPP; + break; + case 15: + ATINewHWPtr->crtc_gen_cntl |= CRTC_PIX_WIDTH_15BPP; + break; + case 16: + ATINewHWPtr->crtc_gen_cntl |= CRTC_PIX_WIDTH_16BPP; + break; + case 24: + if (vga256InfoRec.bitsPerPixel == 24) + ATINewHWPtr->crtc_gen_cntl |= CRTC_PIX_WIDTH_24BPP; + else if (vga256InfoRec.bitsPerPixel == 32) + ATINewHWPtr->crtc_gen_cntl |= CRTC_PIX_WIDTH_32BPP; + break; + case 32: + ATINewHWPtr->crtc_gen_cntl |= CRTC_PIX_WIDTH_32BPP; + break; + default: + break; + } + if (mode->Flags & V_DBLSCAN) + ATINewHWPtr->crtc_gen_cntl |= CRTC_DBL_SCAN_EN; + if (mode->Flags & V_INTERLACE) + ATINewHWPtr->crtc_gen_cntl |= CRTC_INTERLACE_EN; + if ((mode->Flags & (V_CSYNC | V_PCSYNC)) || + (OFLG_ISSET(OPTION_CSYNC, &vga256InfoRec.options))) + ATINewHWPtr->crtc_gen_cntl |= CRTC_CSYNC_EN; + /* For now, set display FIFO low water mark as high as possible */ + if (ATIChip < ATI_CHIP_264VTB) + ATINewHWPtr->crtc_gen_cntl |= CRTC_FIFO_LWM; + } + } + + /* + * ATIMach64Restore -- + * + * This function is called to load a Mach64 accelerator's CRTC. + */ + void + ATIMach64Restore(ATIHWPtr restore) + { + /* First, turn off the display */ + outl(ATIIOPortCRTC_GEN_CNTL, restore->crtc_gen_cntl & ~CRTC_EN); + + if ((restore->FeedbackDivider > 0) && + (ATIProgrammableClock != ATI_CLOCK_NONE)) + ATIClockRestore(restore); /* Programme clock */ + + /* Load Mach64 CRTC registers */ + outl(ATIIOPortCRTC_H_TOTAL_DISP, restore->crtc_h_total_disp); + outl(ATIIOPortCRTC_H_SYNC_STRT_WID, restore->crtc_h_sync_strt_wid); + outl(ATIIOPortCRTC_V_TOTAL_DISP, restore->crtc_v_total_disp); + outl(ATIIOPortCRTC_V_SYNC_STRT_WID, restore->crtc_v_sync_strt_wid); + outl(ATIIOPortCRTC_OFF_PITCH, restore->crtc_off_pitch); + + /* Set pixel clock */ + outl(ATIIOPortCLOCK_CNTL, restore->clock_cntl); + + /* Load overscan registers */ + outl(ATIIOPortOVR_CLR, restore->ovr_clr); + outl(ATIIOPortOVR_WID_LEFT_RIGHT, restore->ovr_wid_left_right); + outl(ATIIOPortOVR_WID_TOP_BOTTOM, restore->ovr_wid_top_bottom); + + /* Finalize CRTC setup and turn on the screen */ + outl(ATIIOPortCRTC_GEN_CNTL, restore->crtc_gen_cntl); + + /* Aperture setup */ + outl(ATIIOPortBUS_CNTL, restore->bus_cntl); + + outl(ATIIOPortMEM_VGA_WP_SEL, restore->mem_vga_wp_sel); + outl(ATIIOPortMEM_VGA_RP_SEL, restore->mem_vga_rp_sel); + + outl(ATIIOPortDAC_CNTL, restore->dac_cntl); + + outl(ATIIOPortCONFIG_CNTL, restore->config_cntl); + } *** /dev/null Tue Jun 30 11:49:03 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atimach64.h Fri Mar 6 16:47:01 1998 *************** *** 0 **** --- 1,38 ---- + /* $TOG: atimach64.h /main/1 1998/03/06 16:48:39 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atimach64.h,v 1.1.2.1 1998/02/01 16:41:57 robin Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + #ifndef ___ATIMACH64_H___ + #define ___ATIMACH64_H___ 1 + + #include "aticrtc.h" + #include "xf86.h" + + extern void ATIMach64Save FunctionPrototype((ATIHWPtr)); + extern void ATIMach64Init FunctionPrototype((DisplayModePtr)); + extern void ATIMach64Restore FunctionPrototype((ATIHWPtr)); + + #endif /* ___ATIMACH64_H___ */ *** /dev/null Tue Jun 30 11:49:04 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atimono.h Fri Mar 6 16:47:05 1998 *************** *** 0 **** --- 1,43 ---- + /* $TOG: atimono.h /main/1 1998/03/06 16:48:43 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atimono.h,v 1.1.2.1 1998/02/01 16:41:58 robin Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + #ifndef ___ATIMONO_H___ + #define ___ATIMONO_H___ 1 + + #ifndef MONO_BLACK + # define MONO_BLACK 0x00U + #endif + + #ifndef MONO_WHITE + # define MONO_WHITE 0x3FU + #endif + + #ifndef MONO_OVERSCAN + # define MONO_OVERSCAN 0x01U + #endif + + #endif /* ___ATIMONO_H___ */ *** /dev/null Tue Jun 30 11:49:05 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atiprint.c Fri Mar 6 16:47:09 1998 *************** *** 0 **** --- 1,315 ---- + /* $TOG: atiprint.c /main/1 1998/03/06 16:48:47 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atiprint.c,v 1.1.2.2 1998/02/27 03:07:51 dawes Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + #include "atiadapter.h" + #include "atichip.h" + #include "atidac.h" + #include "atidepth.h" + #include "atiio.h" + #include "atiprint.h" + #include "atividmem.h" + #include "xf86Priv.h" + + /* + * Define a table to map mode flag values to XF86Config tokens. + */ + typedef struct + { + int flag; + char * token; + } TokenTabRec, *TokenTabPtr; + + static TokenTabRec TokenTab[] = + { + {V_PHSYNC, "+hsync"}, + {V_NHSYNC, "-hsync"}, + {V_PVSYNC, "+vsync"}, + {V_NVSYNC, "-vsync"}, + {V_PCSYNC, "+csync"}, + {V_NCSYNC, "-csync"}, + {V_INTERLACE, "interlace"}, + {V_DBLSCAN, "doublescan"}, + {V_CSYNC, "composite"}, + {0, NULL} + }; + + /* + * ATIPrintBIOS -- + * + * Display part of the video BIOS when the server is invoked with -verbose. + */ + void + ATIPrintBIOS(const CARD8 * BIOS, + const unsigned int Start, const unsigned int End) + { + unsigned int Index = Start & ~(16U - 1U); + + ErrorF("\n BIOS data at 0x%08X:", Start + vga256InfoRec.BIOSbase); + + for (; Index < End; Index++) + { + if (!(Index & (4U - 1U))) + { + if (!(Index & (16U - 1U))) + ErrorF("\n 0x%08X:", Index + vga256InfoRec.BIOSbase); + ErrorF(" "); + } + if (Index < Start) + ErrorF(" "); + else + ErrorF("%02X", BIOS[Index]); + } + + ErrorF("\n"); + } + + /* + * ATIPrintIndexedRegisters -- + * + * Display a set of indexed byte-size registers when the server is invoked with + * -verbose. + */ + static void + ATIPrintIndexedRegisters(const CARD16 Port, + const CARD8 Start_Index, const CARD8 End_Index, + const char * Name, const CARD16 GenS1) + { + int Index; + + ErrorF("\n\n %s register values:", Name); + for (Index = Start_Index; Index < End_Index; Index++) + { + if(!(Index & (4U - 1U))) + { + if (!(Index & (16U - 1U))) + ErrorF("\n 0x%02X:", Index); + ErrorF(" "); + } + if (Port == ATTRX) + (void) inb(GenS1); /* Reset flip-flop */ + ErrorF("%02X", GetReg(Port, Index)); + } + + if (Port == ATTRX) + { + (void) inb(GenS1); /* Reset flip-flop */ + outb(ATTRX, 0x20U); /* Turn on PAS bit */ + } + } + + /* + * ATIPrintRegisters -- + * + * Display various registers when the server is invoked with -verbose. + */ + void + ATIPrintRegisters(void) + { + int Index, Step, Limit; + CARD8 misc = inb(R_GENMO); + CARD8 dac_read, dac_mask; + CARD8 crtc = ATI_CRTC_VGA; + CARD32 IO_Value; + + ErrorF("\n Miscellaneous output register value: 0x%02X.", misc); + + if (misc & 0x01U) + { + ATIPrintIndexedRegisters(CRTX(ColourIOBase), 0, 64, + "Colour CRT controller", 0); + ATIPrintIndexedRegisters(ATTRX, 0, 32, "Attribute controller", + GENS1(ColourIOBase)); + } + else + { + ATIPrintIndexedRegisters(CRTX(MonochromeIOBase), 0, 64, + "Monochrome CRT controller", 0); + ATIPrintIndexedRegisters(ATTRX, 0, 32, "Attribute controller", + GENS1(MonochromeIOBase)); + } + + ATIPrintIndexedRegisters(GRAX, 0, 16, "Graphics controller", 0); + ATIPrintIndexedRegisters(SEQX, 0, 8, "Sequencer", 0); + + if (ATIChipHasVGAWonder) + ATIPrintIndexedRegisters(ATIIOPortVGAWonder, + xf86ProbeOnly ? 0x80U : ATIVGAOffset, 0xC0U, + "ATI Extended VGA", 0); + + if (ATIChipHasSUBSYS_CNTL) + { + ErrorF("\n\n 8514/A registers:"); + for (Index = 0x02E8U; Index <= 0x0FEE8; Index += 0x0400U) + { + if (!((Index - 0x02E8U) & 0x0C00U)) + ErrorF("\n 0x%04X:", Index); + ErrorF(" %04X", inw(Index)); + } + + if (ATIAdapter >= ATI_ADAPTER_MACH8) + { + ErrorF("\n\n Mach8/Mach32 registers:"); + for (Index = 0x2EEU; Index <= 0x0FEEE; Index += 0x0400U) + { + if (!((Index - 0x02EEU) & 0x0C00U)) + ErrorF("\n 0x%04X:", Index); + ErrorF(" %04X", inw(Index)); + } + } + } + else if (ATIChip >= ATI_CHIP_88800GXC) + { + ErrorF("\n\n Mach64 %s registers:", + (ATIIODecoding == SPARSE_IO) ? "sparse" : "block"); + Limit = ATIIOPort(IOPortTag(0x1FU, 0x3FU)); + Step = ATIIOPort(IOPortTag(0x01U, 0x01U)) - ATIIOBase; + for (Index = ATIIOBase; Index <= Limit; Index += Step) + { + if (!(((Index - ATIIOBase) / Step) & 0x03U)) + ErrorF("\n 0x%04X:", Index); + if (Index == ATIIOPortDAC_REGS) + ErrorF(" %02X%02X%02X%02X", + inb(ATIIOPortDAC_REGS + 3), inb(ATIIOPortDAC_REGS + 2), + inb(ATIIOPortDAC_REGS + 1), inb(ATIIOPortDAC_REGS)); + else + { + IO_Value = inl(Index); + + if ((Index == ATIIOPortCRTC_GEN_CNTL) & + (IO_Value & CRTC_EXT_DISP_EN)) + crtc = ATI_CRTC_MACH64; + + ErrorF(" %08X", IO_Value); + } + } + + if (ATIChip >= ATI_CHIP_264CT) + { + ErrorF("\n\n Mach64 PLL registers:"); + if (ATIChip == ATI_CHIP_264LT) + Limit = 32; + else + Limit = 16; + for (Index = 0; Index < Limit; Index++) + { + if (!(Index & 3)) + { + if (!(Index & 15)) + ErrorF("\n 0x%02X:", Index); + ErrorF(" "); + } + ErrorF("%02X", ATIGetMach64PLLReg(Index)); + } + } + } + + ATISetDACIOPorts(crtc); + + ErrorF("\n\n" + " DAC read index: 0x%02X\n" + " DAC write index: 0x%02X\n" + " DAC mask: 0x%02X\n\n" + " DAC colour lookup table:", + dac_read = inb(ATIIOPortDAC_READ), + inb(ATIIOPortDAC_WRITE), + dac_mask = inb(ATIIOPortDAC_MASK)); + + outb(ATIIOPortDAC_MASK, 0xFFU); + outb(ATIIOPortDAC_READ, 0x00U); + + for (Index = 0; Index < 256; Index++) + { + if (!(Index & 3)) + ErrorF("\n 0x%02X:", Index); + ErrorF(" %02X", inb(ATIIOPortDAC_DATA)); + DACDelay; + ErrorF(" %02X", inb(ATIIOPortDAC_DATA)); + DACDelay; + ErrorF(" %02X", inb(ATIIOPortDAC_DATA)); + DACDelay; + } + + outb(ATIIOPortDAC_MASK, dac_mask); + outb(ATIIOPortDAC_READ, dac_read); + + ErrorF("\n\n"); + } + + /* + * ATIPrintMode -- + * + * This function prints out a mode's timing information on stderr. + */ + void + ATIPrintMode(DisplayModePtr mode) + { + TokenTabPtr TokenEntry; + int mode_flags = mode->Flags; + + ErrorF(" Dot clock: %7.3fMHz\n" + " Horizontal timings: %4d %4d %4d %4d\n" + " Vertical timings: %4d %4d %4d %4d\n", + (double)vga256InfoRec.clock[mode->Clock] / 1000.0, + mode->HDisplay, mode->HSyncStart, mode->HSyncEnd, mode->HTotal, + mode->VDisplay, mode->VSyncStart, mode->VSyncEnd, mode->VTotal); + + if (mode_flags & V_HSKEW) + { + mode_flags &= ~V_HSKEW; + ErrorF(" Horizontal skew: %4d\n", mode->HSkew); + } + + ErrorF(" Flags: "); + + for (TokenEntry = TokenTab; TokenEntry->flag; TokenEntry++) + if (mode_flags & TokenEntry->flag) + { + ErrorF(" %s", TokenEntry->token); + mode_flags &= ~TokenEntry->flag; + if (!mode_flags) + break; + } + + ErrorF("\n"); + } + + /* + * ATIPrintMemoryType -- + * + * This function is called by ATIProbe to print, on stderr, the amount and type + * of video memory used by the adapter. + */ + void + ATIPrintMemoryType(const char *MemoryTypeName) + { + ErrorF("%d kB of %s detected", ATIvideoRam, MemoryTypeName); + if (ATIUsing1bppModes) + ErrorF(" (using %d kB)", vga256InfoRec.videoRam / 4); + else if (ATIvideoRam > vga256InfoRec.videoRam) + ErrorF(" (using %d kB)", vga256InfoRec.videoRam); + ErrorF(".\n"); + } *** /dev/null Tue Jun 30 11:49:07 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atiprint.h Fri Mar 6 16:47:13 1998 *************** *** 0 **** --- 1,41 ---- + /* $TOG: atiprint.h /main/1 1998/03/06 16:48:51 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atiprint.h,v 1.1.2.1 1998/02/01 16:41:59 robin Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + #ifndef ___ATIPRINT_H___ + #define ___ATIPRINT_H___ 1 + + #include "atiproto.h" + #include "xf86.h" + + extern void ATIPrintBIOS FunctionPrototype((const CARD8 *, + const unsigned int, + const unsigned int)); + extern void ATIPrintRegisters FunctionPrototype((void)); + extern void ATIPrintMode FunctionPrototype((DisplayModePtr)); + extern void ATIPrintMemoryType FunctionPrototype((const char *)); + + #endif /* ___ATIPRINT_H___ */ *** /dev/null Tue Jun 30 11:49:08 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atiprobe.c Fri Mar 6 16:47:17 1998 *************** *** 0 **** --- 1,1691 ---- + /* $TOG: atiprobe.c /main/1 1998/03/06 16:48:55 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atiprobe.c,v 1.1.2.2 1998/02/27 03:07:51 dawes Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + #include "ati.h" + #include "atiadapter.h" + #include "atibus.h" + #include "atichip.h" + #include "aticlock.h" + #include "aticonsole.h" + #include "atidac.h" + #include "atidepth.h" + #include "atidsp.h" + #include "atigetmode.h" + #include "atiident.h" + #include "atiio.h" + #include "atiprint.h" + #include "atiprobe.h" + #ifndef MONOVGA + #include "atiscrinit.h" + #endif + #include "ativersion.h" + #include "atividmem.h" + #include "vgaPCI.h" + #include "xf86Procs.h" + + #define XCONFIG_FLAGS_ONLY + #include "xf86_Config.h" + + #ifdef XFreeXDGA + # define _XF86DGA_SERVER_ + # include "extensions/xf86dga.h" + #endif + + /* + * This structure is used by ATIProbe in an attempt to define a default video + * mode when the user has not specified any modes in XF86Config. + */ + static DisplayModeRec DefaultMode; + + /* + * Macros for port definitions. + */ + #define IOByte(_Port) (_Port) + #define IOWord(_Port) (_Port), (_Port)+1 + #define IOLong(_Port) (_Port), (_Port)+1, (_Port)+2, (_Port)+3 + + typedef CARD16 Colour; /* The correct spelling should be OK :-) */ + + /* + * Bit patterns which are extremely unlikely to show up when reading from + * nonexistant memory (which normally shows up as either all bits set or all + * bits clear). + */ + static const Colour Test_Pixel[] = {0x5AA5U, 0x55AAU, 0xA55AU, 0xCA53U}; + + static const struct + { + int videoRamSize; + int Miscellaneous_Options_Setting; + struct + { + short int x, y; + } + Coordinates[NumberOf(Test_Pixel) + 1]; + } + Test_Case[] = + { + /* + * Given the engine settings used, only a 4M card will have enough memory + * to back up the 1025th line of the display. Since the pixel coordinates + * are zero-based, line 1024 will be the first one which is only backed on + * 4M cards. + * + * <Mark_Weaver@brown.edu>: + * In case memory is being wrapped, (0,0) and (0,1024) to make sure they + * can each hold a unique value. + */ + {4096, MEM_SIZE_4M, {{0,0}, {0,1024}, {-1,-1}}}, + + /* + * This card has 2M or less. On a 1M card, the first 2M of the card's + * memory will have even doublewords backed by physical memory and odd + * doublewords unbacked. + * + * Pixels 0 and 1 of a row will be in the zeroth doubleword, while pixels 2 + * and 3 will be in the first. Check both pixels 2 and 3 in case this is a + * pseudo-1M card (one chip pulled to turn a 2M card into a 1M card). + * + * <Mark_Weaver@brown.edu>: + * I don't have a 1M card, so I'm taking a stab in the dark. Maybe memory + * wraps every 512 lines, or maybe odd doublewords are aliases of their + * even doubleword counterparts. I try everything here. + */ + {2048, MEM_SIZE_2M, {{0,0}, {0,512}, {2,0}, {3,0}, {-1,-1}}}, + + /* + * This is a either a 1M card or a 512k card. Test pixel 1, since it is an + * odd word in an even doubleword. + * + * <Mark_Weaver@brown.edu>: + * This is the same idea as the test above. + */ + {1024, MEM_SIZE_1M, {{0,0}, {0,256}, {1,0}, {-1,-1}}}, + + /* + * Assume it is a 512k card by default, since that is the minimum + * configuration. + */ + {512, MEM_SIZE_512K, {{-1,-1}}} + }; + + /* + * ATIMach32ReadPixel -- + * + * Return the colour of the specified screen location. Called from + * ATIMach32videoRam function below. + */ + static Colour + ATIMach32ReadPixel(const short int X, const short int Y) + { + Colour Pixel_Colour; + + /* Wait for idle engine */ + ProbeWaitIdleEmpty(); + + /* Set up engine for pixel read */ + ATIWaitQueue(7); + outw(RD_MASK, (CARD16)(~0)); + outw(DP_CONFIG, FG_COLOR_SRC_BLIT | DATA_WIDTH | DRAW | DATA_ORDER); + outw(CUR_X, X); + outw(CUR_Y, Y); + outw(DEST_X_START, X); + outw(DEST_X_END, X + 1); + outw(DEST_Y_END, Y + 1); + + /* Wait for data to become ready */ + ATIWaitQueue(16); + WaitDataReady(); + + /* Read pixel colour */ + Pixel_Colour = inw(PIX_TRANS); + ProbeWaitIdleEmpty(); + return Pixel_Colour; + } + + /* + * ATIMach32WritePixel -- + * + * Set the colour of the specified screen location. Called from + * ATIMach32videoRam function below. + */ + static void + ATIMach32WritePixel(const short int X, const short int Y, + const Colour Pixel_Colour) + { + /* Set up engine for pixel write */ + ATIWaitQueue(9); + outw(WRT_MASK, (CARD16)(~0)); + outw(DP_CONFIG, FG_COLOR_SRC_FG | DRAW | READ_WRITE); + outw(ALU_FG_FN, MIX_FN_PAINT); + outw(FRGD_COLOR, Pixel_Colour); + outw(CUR_X, X); + outw(CUR_Y, Y); + outw(DEST_X_START, X); + outw(DEST_X_END, X + 1); + outw(DEST_Y_END, Y + 1); + } + + /* + * ATIMach32videoRam -- + * + * Determine the amount of video memory installed on an 68800-6 based adapter. + * This is done because these chips exhibit a bug that causes their + * MISC_OPTIONS register to report 1M rather than the true amount of memory. + * + * This function is adapted from a similar function in mach32mem.c written by + * Robert Wolff, David Dawes and Mark Weaver. + */ + static int + ATIMach32videoRam(void) + { + CARD16 saved_clock_sel, saved_mem_bndry, saved_misc_options, + saved_ext_ge_config; + Colour saved_Pixel[NumberOf(Test_Pixel)]; + unsigned int Case_Number, Pixel_Number; + CARD16 corrected_misc_options; + Bool AllPixelsOK; + + /* Save register values to be modified */ + saved_clock_sel = inw(CLOCK_SEL); + saved_mem_bndry = inw(MEM_BNDRY); + saved_misc_options = inw(MISC_OPTIONS); + corrected_misc_options = saved_misc_options & ~MEM_SIZE_ALIAS; + saved_ext_ge_config = inw(R_EXT_GE_CONFIG); + + /* Wait for enough FIFO entries */ + ATIWaitQueue(7); + + /* Enable accelerator */ + outw(CLOCK_SEL, saved_clock_sel | DISABPASSTHRU); + + /* Make accelerator and VGA share video memory */ + outw(MEM_BNDRY, saved_mem_bndry & ~(MEM_PAGE_BNDRY | MEM_BNDRY_ENA)); + + /* Prevent video memory wrap */ + outw(MISC_OPTIONS, corrected_misc_options | MEM_SIZE_4M); + + /* + * Set up the drawing engine for a pitch of 1024 at 16 bits per pixel. No + * need to mess with the CRT because the results of this test are not + * intended to be seen. + */ + outw(EXT_GE_CONFIG, PIX_WIDTH_16BPP | ORDER_16BPP_565 | MONITOR_8514 | + ALIAS_ENA); + outw(GE_PITCH, 1024 >> 3); + outw(GE_OFFSET_HI, 0); + outw(GE_OFFSET_LO, 0); + + for (Case_Number = 0; + Case_Number < (NumberOf(Test_Case) - 1); + Case_Number++) + { + /* Reduce redundancy as per Mark_Weaver@brown.edu */ + # define TestPixel Test_Case[Case_Number].Coordinates[Pixel_Number] + # define ForEachTestPixel \ + for (Pixel_Number = 0; TestPixel.x >= 0; Pixel_Number++) + + /* Save pixel colours that will be clobbered */ + ForEachTestPixel + saved_Pixel[Pixel_Number] = + ATIMach32ReadPixel(TestPixel.x, TestPixel.y); + + /* Write test patterns */ + ForEachTestPixel + ATIMach32WritePixel(TestPixel.x, TestPixel.y, + Test_Pixel[Pixel_Number]); + + /* Test for lost pixels */ + AllPixelsOK = TRUE; + ForEachTestPixel + if (ATIMach32ReadPixel(TestPixel.x, TestPixel.y) != + Test_Pixel[Pixel_Number]) + { + AllPixelsOK = FALSE; + break; + } + + /* Restore clobbered pixels */ + ForEachTestPixel + ATIMach32WritePixel(TestPixel.x, TestPixel.y, + saved_Pixel[Pixel_Number]); + + /* End test on success */ + if (AllPixelsOK) + break; + + /* Completeness */ + # undef ForEachTestPixel + # undef TestPixel + } + + /* Restore what was changed and correct MISC_OPTIONS register */ + ATIWaitQueue(4); + outw(EXT_GE_CONFIG, saved_ext_ge_config); + corrected_misc_options |= + Test_Case[Case_Number].Miscellaneous_Options_Setting; + outw(MISC_OPTIONS, corrected_misc_options); + outw(MEM_BNDRY, saved_mem_bndry); + outw(CLOCK_SEL, saved_clock_sel); + + /* Wait for activity to die down */ + ProbeWaitIdleEmpty(); + + /* Tell ATIProbe the REAL story */ + return Test_Case[Case_Number].videoRamSize; + } + + /* + * ATIMach64Probe -- + * + * This function looks for a Mach64 at a particular I/O base address. This + * sets ATIAdapter if a Mach64 is found. + */ + static void + ATIMach64Probe(const CARD16 IO_Base, const CARD8 IO_Decoding, + const CARD16 ExpectedChipType) + { + CARD32 IO_Value, saved_bus_cntl, saved_gen_test_cntl; + CARD16 IO_Port; + + if ((ATIAdapter != ATI_ADAPTER_NONE) || (IO_Base == 0)) + return; + + ATIIOBase = IO_Base; + ATIIODecoding = IO_Decoding; + + /* + * Make sure any Mach64 is not in some weird state. Note that command + * FIFO errors cannot be reset here because VTB's and later use the same + * bits for something else, and, at this point, it isn't yet known whether + * or not such a controller will be detected. Something based on the + * expected chip type could be done, I suppose, but it would be kludgy at + * best, and imprecise at worst. + */ + ATIIOPortBUS_CNTL = ATIIOPort(BUS_CNTL); + saved_bus_cntl = inl(ATIIOPortBUS_CNTL); + outl(ATIIOPortBUS_CNTL, (saved_bus_cntl & ~BUS_HOST_ERR_INT_EN) | + BUS_HOST_ERR_INT); + + ATIIOPortGEN_TEST_CNTL = ATIIOPort(GEN_TEST_CNTL); + saved_gen_test_cntl = inl(ATIIOPortGEN_TEST_CNTL); + IO_Value = saved_gen_test_cntl & + (GEN_OVR_OUTPUT_EN | GEN_OVR_POLARITY | GEN_CUR_EN | GEN_BLOCK_WR_EN); + outl(ATIIOPortGEN_TEST_CNTL, IO_Value | GEN_GUI_EN); + outl(ATIIOPortGEN_TEST_CNTL, IO_Value); + outl(ATIIOPortGEN_TEST_CNTL, IO_Value | GEN_GUI_EN); + + /* See if a Mach64 answers */ + IO_Port = ATIIOPort(SCRATCH_REG0); + IO_Value = inl(IO_Port); + + /* Test odd bits */ + outl(IO_Port, 0x55555555UL); + if (inl(IO_Port) == 0x55555555UL) + { + /* Test even bits */ + outl(IO_Port, 0xAAAAAAAAUL); + if (inl(IO_Port) == 0xAAAAAAAAUL) + { + /* + * *Something* has a R/W 32-bit register at this I/O address. Try + * to make sure it's a Mach64. The following assumes that ATI + * won't be producing any more adapters that don't register + * themselves in the PCI configuration space. + */ + ATIMach64ChipID(ExpectedChipType); + if ((ATIChip != ATI_CHIP_Mach64) || (IO_Decoding == BLOCK_IO)) + ATIAdapter = ATI_ADAPTER_MACH64; + else + ATIChip = ATI_CHIP_NONE; + } + } + + /* Restore registers that might have been clobbered */ + outl(IO_Port, IO_Value); + if (ATIAdapter != ATI_ADAPTER_MACH64) + { + outl(ATIIOPortGEN_TEST_CNTL, saved_gen_test_cntl); + outl(ATIIOPortBUS_CNTL, saved_bus_cntl); + } + } + + /* + * ATIProbe -- + * + * This is the function that makes a yes/no decision about whether or not a + * chipset supported by this driver is present or not. The server will call + * each driver's probe function in sequence, until one returns TRUE or they all + * fail. + */ + Bool + ATIProbe(void) + { + static const CARD8 ATISignature[] = " 761295520"; + # define Signature_Size 10 + # define Prefix_Size 1024 /* 1kB */ + # define BIOS_SIZE 0x008000 /* 32kB */ + # define BIOS_Signature 0x30U + # define No_Signature (Prefix_Size + 1 - Signature_Size) + CARD8 BIOS[BIOS_SIZE]; + # define BIOSByte(_n) (*((CARD8 *)(BIOS + (_n)))) + # define BIOSWord(_n) (*((CARD16 *)(BIOS + (_n)))) + CARD32 IO_Value = 0, IO_Value2; + unsigned int Signature = No_Signature; + int saved_BIOSbase = vga256InfoRec.BIOSbase; + int MachvideoRam = 0; + int VGAvideoRam = 0; + unsigned int WindowSize; + CARD8 ATIMachChip = ATI_CHIP_NONE; + CARD16 ClockDac; + static const int videoRamSizes[] = + {0, 256, 512, 1024, 2*1024, 4*1024, 6*1024, 8*1024, 12*1024, 16*1024, 0}; + int ROMTable = 0, ClockTable = 0, FrequencyTable = 0, Index; + const DACRec *DAC; + pciConfigPtr PCIDevice; + + /* Get out if this isn't the driver the user wants */ + if (!ATIIdentProbe()) + return FALSE; + + /* Enable the I/O ports needed for probing */ + xf86EnableIOPorts(vga256InfoRec.scrnIndex); + + /* + * It is quite possible for a system to preclude the existence of a mix of + * sparse I/O and block I/O devices. Scan PCI configuration space, if + * available, for any registered I/O ranges which would in most cases + * preclude the existence of an 8514/A compatible device. The following + * check is a bit of an overkill, but will do for now. + */ + if (vgaPCIInfo && vgaPCIInfo->AllCards) + { + Index = 0; + while ((PCIDevice = vgaPCIInfo->AllCards[Index++])) + { + CARD32 * BasePointer = &PCIDevice->_base0; + + /* Check all six base addresses */ + for (; BasePointer <= &PCIDevice->_base5; BasePointer++) + { + /* + * Skip 8514/A probe if this device has registered an I/O + * range. + */ + if (*BasePointer & 1U) + goto Skip8514Probe; + + /* Allow for 64-bit memory addresses */ + if (*BasePointer & 4U) + BasePointer++; + } + } + } + + /* + * Save register value to be modified, just in case there is no 8514/A + * compatible accelerator. Note that, in more ways than one, + * SUBSYS_STAT == SUBSYS_CNTL. + */ + IO_Value = inw(SUBSYS_STAT); + IO_Value2 = IO_Value & _8PLANE; + + /* + * Determine if an 8514/A-compatible accelerator is present, making sure + * it's not in some weird state. + */ + outw(SUBSYS_CNTL, IO_Value2 | (GPCTRL_RESET | CHPTEST_NORMAL)); + outw(SUBSYS_CNTL, IO_Value2 | (GPCTRL_ENAB | CHPTEST_NORMAL | RVBLNKFLG | + RPICKFLAG | RINVALIDIO | RGPIDLE)); + + IO_Value2 = inw(ERR_TERM); + outw(ERR_TERM, 0x5A5AU); + ProbeWaitIdleEmpty(); + if (inw(ERR_TERM) == 0x5A5AU) + { + outw(ERR_TERM, 0x2525U); + ProbeWaitIdleEmpty(); + if (inw(ERR_TERM) == 0x2525U) + ATIAdapter = ATI_ADAPTER_8514A; + } + outw(ERR_TERM, IO_Value2); + + if (ATIAdapter == ATI_ADAPTER_8514A) + { + /* Some kind of 8514/A detected */ + ATIChipHasSUBSYS_CNTL = TRUE; + + /* Don't leave any Mach8 or Mach32 in 8514/A mode */ + IO_Value2 = inw(CLOCK_SEL); + outw(CLOCK_SEL, IO_Value2); + ProbeWaitIdleEmpty(); + + IO_Value2 = inw(ROM_ADDR_1); + outw(ROM_ADDR_1, 0x5555U); + ProbeWaitIdleEmpty(); + if (inw(ROM_ADDR_1) == 0x5555U) + { + outw(ROM_ADDR_1, 0x2A2AU); + ProbeWaitIdleEmpty(); + if (inw(ROM_ADDR_1) == 0x2A2AU) + ATIAdapter = ATI_ADAPTER_MACH8; + } + outw(ROM_ADDR_1, IO_Value2); + } + + if (ATIAdapter == ATI_ADAPTER_MACH8) + { + /* ATI Mach8 or Mach32 accelerator detected */ + outw(DESTX_DIASTP, 0xAAAAU); + ProbeWaitIdleEmpty(); + if (inw(READ_SRC_X) == 0x02AAU) + ATIAdapter = ATI_ADAPTER_MACH32; + + outw(DESTX_DIASTP, 0x5555U); + ProbeWaitIdleEmpty(); + if (inw(READ_SRC_X) == 0x0555U) + { + if (ATIAdapter != ATI_ADAPTER_MACH32) + ATIAdapter = ATI_ADAPTER_8514A; + } + else + { + if (ATIAdapter != ATI_ADAPTER_MACH8) + ATIAdapter = ATI_ADAPTER_8514A; + } + } + else + { + /* Restore register clobbered by 8514/A reset attempt */ + outw(SUBSYS_CNTL, IO_Value); + } + + Skip8514Probe: + if (ATIAdapter == ATI_ADAPTER_NONE) + { + /* + * Determine if a Mach64 is present. First, check the user's IObase. + */ + if (vga256InfoRec.IObase & BLOCK_IO_SELECT) + ATIMach64Probe(vga256InfoRec.IObase & SPARSE_IO_BASE, SPARSE_IO, 0); + else if (vga256InfoRec.IObase & SPARSE_IO_SELECT) + ATIMach64Probe(vga256InfoRec.IObase & BLOCK_IO_BASE, BLOCK_IO, 0); + + /* Check the "standard" sparse I/O bases */ + ATIMach64Probe(0x02ECU, SPARSE_IO, 0); + ATIMach64Probe(0x01C8U, SPARSE_IO, 0); + ATIMach64Probe(0x01CCU, SPARSE_IO, 0); + + /* Lastly, check PCI configuration space */ + if (vgaPCIInfo && vgaPCIInfo->AllCards) + { + Index = 0; + while ((ATIAdapter == ATI_ADAPTER_NONE) && + (PCIDevice = vgaPCIInfo->AllCards[Index++])) + { + if (PCIDevice->_vendor != PCI_VENDOR_ATI) + continue; + if (PCIDevice->_device == PCI_CHIP_MACH32) + continue; + ATIMach64Probe(PCIDevice->_base1 & BLOCK_IO_BASE, BLOCK_IO, + PCIDevice->_device); + } + } + } + + /* Extract various information from any detected accelerator */ + switch (ATIAdapter) + { + case ATI_ADAPTER_8514A: + MachvideoRam = videoRamSizes[GetBits(IO_Value, _8PLANE) + 2]; + ATIMachChip = ATI_CHIP_8514A; + IO_Value = inb(EXT_CONFIG_3); + outb(EXT_CONFIG_3, IO_Value & 0x0FU); + if (!(inb(EXT_CONFIG_3) & 0xF0U)) + { + outb(EXT_CONFIG_3, IO_Value | 0xF0U); + if ((inb(EXT_CONFIG_3) & 0xF0U) == 0xF0U) + ATIMachChip = ATI_CHIP_CT480; + } + outb(EXT_CONFIG_3, IO_Value); + break; + + case ATI_ADAPTER_MACH8: + ATIMachChip = ATI_CHIP_38800_1; + IO_Value = inw(CONFIG_STATUS_1); + if (IO_Value & MC_BUS) + ATIBusType = ATI_BUS_MCA16; + MachvideoRam = + videoRamSizes[GetBits(IO_Value, MEM_INSTALLED) + 2]; + break; + + case ATI_ADAPTER_MACH32: + IO_Value = inw(CONFIG_STATUS_1); + if (!(IO_Value & (_8514_ONLY | CHIP_DIS))) + { + ATIVGAAdapter = ATI_ADAPTER_MACH32; + ATIChipHasVGAWonder = TRUE; + } + ATIBusType = GetBits(IO_Value, BUS_TYPE); + ATIDac = ATI_DAC(GetBits(IO_Value, DACTYPE), 0); + + ATIMach32ChipID(); + + ATIMemoryType = GetBits(IO_Value, MEM_TYPE); + MachvideoRam = + videoRamSizes[GetBits(inw(MISC_OPTIONS), MEM_SIZE_ALIAS) + 2]; + + /* + * The 68800-6 doesn't necessarily report the correct video memory + * size. + */ + if ((ATIChip == ATI_CHIP_68800_6) && (MachvideoRam == 1024)) + MachvideoRam = ATIMach32videoRam(); + + vga256InfoRec.BIOSbase = 0x000C0000U + + (GetBits(inw(ROM_ADDR_1), BIOS_BASE_SEGMENT) << 11); + break; + + case ATI_ADAPTER_MACH64: + /* Set general use I/O port numbers */ + ATIIOPortCRTC_H_TOTAL_DISP = ATIIOPort(CRTC_H_TOTAL_DISP); + ATIIOPortCRTC_H_SYNC_STRT_WID = ATIIOPort(CRTC_H_SYNC_STRT_WID); + ATIIOPortCRTC_V_TOTAL_DISP = ATIIOPort(CRTC_V_TOTAL_DISP); + ATIIOPortCRTC_V_SYNC_STRT_WID = ATIIOPort(CRTC_V_SYNC_STRT_WID); + ATIIOPortCRTC_OFF_PITCH = ATIIOPort(CRTC_OFF_PITCH); + ATIIOPortCRTC_INT_CNTL = ATIIOPort(CRTC_INT_CNTL); + ATIIOPortCRTC_GEN_CNTL = ATIIOPort(CRTC_GEN_CNTL); + ATIIOPortOVR_CLR = ATIIOPort(OVR_CLR); + ATIIOPortOVR_WID_LEFT_RIGHT = ATIIOPort(OVR_WID_LEFT_RIGHT); + ATIIOPortOVR_WID_TOP_BOTTOM = ATIIOPort(OVR_WID_TOP_BOTTOM); + ATIIOPortCLOCK_CNTL = ATIIOPort(CLOCK_CNTL); + ATIIOPortMEM_INFO = ATIIOPort(MEM_INFO); + ATIIOPortDAC_REGS = ATIIOPort(DAC_REGS); + ATIIOPortDAC_CNTL = ATIIOPort(DAC_CNTL); + ATIIOPortCONFIG_CNTL = ATIIOPort(CONFIG_CNTL); + + IO_Value = inl(ATIIOPortMEM_INFO); + if (ATIChip >= ATI_CHIP_264VTB) + { + IO_Value = GetBits(IO_Value, CTL_MEM_SIZEB); + if (IO_Value < 8) + MachvideoRam = (IO_Value + 1) * 512; + else if (IO_Value < 12) + MachvideoRam = (IO_Value - 3) * 1024; + else + MachvideoRam = (IO_Value - 7) * 2048; + } + else + MachvideoRam = + videoRamSizes[GetBits(IO_Value, CTL_MEM_SIZE) + 2]; + + IO_Value = inl(ATIIOPort(SCRATCH_REG1)); + IO_Value2 = inl(ATIIOPort(CONFIG_STATUS64_0)); + ATIDac = GetBits(inl(ATIIOPortDAC_CNTL), DAC_TYPE); + + if (ATIChip < ATI_CHIP_264CT) + { + ATIBusType = GetBits(IO_Value2, CFG_BUS_TYPE); + IO_Value2 &= (CFG_VGA_EN | CFG_CHIP_EN); + if (ATIChip == ATI_CHIP_88800CX) + IO_Value2 |= CFG_VGA_EN; + if (IO_Value2 == (CFG_VGA_EN | CFG_CHIP_EN)) + { + ATIVGAAdapter = ATI_ADAPTER_MACH64; + ATIChipHasVGAWonder = TRUE; + + /* + * Apparently, 0x1CE cannot be used for ATI's extended VGA + * registers when using block I/O decoding. Instead, these + * registers are tacked on to VGA's Graphics register bank. + */ + if (ATIIODecoding == BLOCK_IO) + ATIIOPortVGAWonder = GRAX; + } + + /* Factor in what the BIOS says the DAC is */ + ATIDac = ATI_DAC(ATIDac, + GetBits(IO_Value, BIOS_INIT_DAC_SUBTYPE)); + + ATIMemoryType = GetBits(IO_Value2, CFG_MEM_TYPE); + } + else + { + /* + * On VT's and above, it's possible BIOS initialization + * disabled VGA functionality through this adapter. It could + * be re-enabled, but this would mean disabling whatever else + * is providing the system's VGA. So, for now, respect the + * BIOS setting. This situation might well be dealt with + * differently if or when it shows up during testing or normal + * use. + */ + if ((ATIChip < ATI_CHIP_264VT) || (IO_Value2 & CFG_VGA_EN_T)) + ATIVGAAdapter = ATI_ADAPTER_MACH64; + + if ((ATIChipType == 0x4742U) || (ATIChipType == 0x4744U)) + ATIBusType = ATI_BUS_AGP; + else + ATIBusType = ATI_BUS_PCI; + ATIMemoryType = GetBits(IO_Value2, CFG_MEM_TYPE_T); + } + + /* + * RAMDAC types 0 & 1 for Mach64's are not the same as for + * Mach32's. + */ + if (ATIDac < ATI_DAC_ATI68875) + ATIDac += ATI_DAC_INTERNAL; + + vga256InfoRec.BIOSbase = 0x000C0000U + + (GetBits(IO_Value, BIOS_BASE_SEGMENT) << 11); + break; + + default: + break; + } + + /* Get video BIOS, *all* of it */ + Index = xf86ReadBIOS(vga256InfoRec.BIOSbase, 0, BIOS, SizeOf(BIOS)); + + /* Fill in what cannot be gotten with zeroes */ + if (Index < 0) + Index = 0; + for (; Index < BIOS_SIZE; Index++) + BIOS[Index] = 0; + + /* + * Attempt to find the ATI signature in the first 1024 bytes of the video + * BIOS. + */ + for (Signature = 0; Signature < No_Signature; Signature++) + for (Index = 0; BIOS[Signature + Index] == ATISignature[Index]; ) + if (++Index >= Signature_Size) + goto signature_found; + signature_found:; + + /* + * If no VGA capability has yet been detected, determine if VGA Wonder + * functionality is possible. + */ + if ((ATIAdapter <= ATI_ADAPTER_MACH8) && + (Signature == BIOS_Signature) && + (BIOS[0x40U] == '3')) + { + switch (BIOS[0x41U]) + { + case '1': + /* This is a Mach8 or VGA Wonder adapter of some kind */ + if ((BIOS[0x43U] >= '1') && (BIOS[0x43U] <= '6')) + ATIChip = BIOS[0x43U] - ('1' - ATI_CHIP_18800); + + switch (BIOS[0x43U]) + { + case '1': /* ATI_CHIP_18800 */ + ATIVGAOffset = 0xB0U; + ATIVGAAdapter = ATI_ADAPTER_V3; + + /* Reset a few things for V3 adapters */ + ATI.ChipSetRead = ATIV3SetRead; + ATI.ChipSetWrite = ATIV3SetWrite; + ATI.ChipSetReadWrite = ATIV3SetReadWrite; + ATI.ChipUse2Banks = FALSE; + break; + + case '2': /* ATI_CHIP_18800_1 */ + ATIVGAOffset = 0xB0U; + if (BIOS[0x42U] & 0x10U) + ATIVGAAdapter = ATI_ADAPTER_V5; + else + ATIVGAAdapter = ATI_ADAPTER_V4; + + /* Reset a few things for V4 and V5 adapters */ + ATI.ChipSetRead = ATIV4V5SetRead; + ATI.ChipSetWrite = ATIV4V5SetWrite; + ATI.ChipSetReadWrite = ATIV4V5SetReadWrite; + break; + + case '3': /* ATI_CHIP_28800_2 */ + case '4': /* ATI_CHIP_28800_4 */ + case '5': /* ATI_CHIP_28800_5 */ + case '6': /* ATI_CHIP_28800_6 */ + ATIVGAOffset = 0xA0U; + ATIVGAAdapter = ATI_ADAPTER_PLUS; + if (BIOS[0x44U] & 0x80U) + { + ATIVGAAdapter = ATI_ADAPTER_XL; + ATIDac = ATI_DAC_SC11483; + } + break; + + case 'a': /* A Mach32 with a */ + case 'b': /* frontal lobotomy */ + case 'c': + ATIVGAAdapter = ATI_ADAPTER_NONISA; + ATIMach32ChipID(); + ProbeWaitIdleEmpty(); + if (inw(SUBSYS_STAT) != 0xFFFFU) + ATIChipHasSUBSYS_CNTL = TRUE; + break; + + case ' ': /* A crippled Mach64 */ + ATIVGAAdapter = ATI_ADAPTER_NONISA; + ATIMach64ChipID(0); + break; + + default: + break; + } + + if (ATIVGAAdapter != ATI_ADAPTER_NONE) + ATIChipHasVGAWonder = TRUE; + break; + #if 0 + case '2': + ATIVGAOffset = 0xB0U; /* Presumably */ + ATIVGAAdapter = ATI_ADAPTER_EGA_PLUS; + break; + + case '3': + ATIVGAOffset = 0xB0U; /* Presumably */ + ATIVGAAdapter = ATI_ADAPTER_BASIC; + break; + #endif + case '?': /* A crippled Mach64 */ + ATIVGAAdapter = ATI_ADAPTER_NONISA; + ATIMach64ChipID(0); + break; + + default: + break; + } + + if (ATIAdapter == ATI_ADAPTER_NONE) + ATIAdapter = ATIVGAAdapter; + } + + /* + * At this point, some adapters should probably be shared with other + * drivers :-). + */ + if (Signature != BIOS_Signature) + { + if ((ATIVGAAdapter == ATI_ADAPTER_NONE) && + (ATIChipSet == ATI_CHIPSET_IBMVGA)) + { + /* + * VGA has one more attribute register than EGA. See if it can be + * read and written. + */ + ATISetVGAIOBase(inb(R_GENMO)); + (void) inb(GENS1(vgaIOBase)); + IO_Value = GetReg(ATTRX, 0x14U | 0x20U); + outb(ATTRX, IO_Value ^ 0x0FU); + IO_Value2 = GetReg(ATTRX, 0x14U | 0x20U); + outb(ATTRX, IO_Value); + if (IO_Value2 == (IO_Value ^ 0x0FU)) + { + /* VGA device detected */ + ATIChip = ATI_CHIP_VGA; + ATIVGAAdapter = ATI_ADAPTER_VGA; + if (ATIAdapter == ATI_ADAPTER_NONE) + ATIAdapter = ATIVGAAdapter; + + /* Disable banking */ + ATI.ChipSetRead = ATI.ChipSetWrite = ATI.ChipSetReadWrite = + (BankFunction *)NoopDDA; + } + } + if ((ATIAdapter == ATI_ADAPTER_NONE) || + (ATIVGAAdapter == ATI_ADAPTER_NONE)) + { + if (vga256InfoRec.chipset) + ErrorF("XF86Config chipset specified as \"%s\",\n but no" + " applicable adapter found.\n", vga256InfoRec.chipset); + xf86DisableIOPorts(vga256InfoRec.scrnIndex); + vga256InfoRec.BIOSbase = saved_BIOSbase; + return FALSE; + } + } + + /* + * For Mach64 adapters, pick up, from the BIOS, the type of programmable + * clock generator (if any), and various information about it. + */ + if (ATIChip >= ATI_CHIP_88800GXC) + { + ROMTable = BIOSWord(0x48U); + if ((ROMTable + 0x12U) > BIOS_SIZE) + ROMTable = 0; + if (ROMTable > 0) + { + ClockTable = BIOSWord(ROMTable + 0x10U); + if ((ClockTable + 0x0CU) > BIOS_SIZE) + ClockTable = 0; + } + if (ClockTable > 0) + { + FrequencyTable = BIOSWord(ClockTable - 0x02U); + if ((FrequencyTable + 0x20U) > BIOS_SIZE) + FrequencyTable = 0; + if (FrequencyTable > 0) + for (Index = 0; Index < 16; Index++) + ATIBIOSClocks[Index] = (&BIOSWord(FrequencyTable))[Index]; + ATIProgrammableClock = BIOSByte(ClockTable); + ATIClockNumberToProgramme = BIOSByte(ClockTable + 0x06U); + if (ATIProgrammableClock < ATI_CLOCK_MAX) + ATIClockDescriptor += ATIProgrammableClock; + if ((BIOSWord(ClockTable + 0x08U) / 10) != 143) + { + ATIReferenceNumerator = BIOSWord(ClockTable + 0x08U) * 10; + ATIReferenceDenominator = 1; + } + } + + ClockDac = ATIDac; + switch (ATIProgrammableClock) + { + case ATI_CLOCK_ICS2595: + /* + * Pick up reference divider (43 or 46) appropriate to the chip + * revision level. + */ + if (ClockTable > 0) + ATIClockDescriptor->MinM = ATIClockDescriptor->MaxM = + BIOSWord(ClockTable + 0x0AU); + break; + + case ATI_CLOCK_STG1703: + /* This one's also a RAMDAC */ + ClockDac = ATI_DAC_STG1703; + break; + + case ATI_CLOCK_CH8398: + /* This one's also a RAMDAC */ + ClockDac = ATI_DAC_CH8398; + break; + + case ATI_CLOCK_INTERNAL: + /* + * The reference divider has already been programmed by BIOS + * initialization. Because, there is only one reference + * divider for all generated frequencies (including MCLK), it + * cannot be changed without reprogramming all clocks every + * time one of them needs a different reference divider. + * + * Besides, it's not a good idea to change the reference + * divider. BIOS initialization sets it to a value that + * effectively prevents generating frequencies beyond the + * graphics controller's tolerance. + */ + ATIClockDescriptor->MinM = ATIClockDescriptor->MaxM = + ATIGetMach64PLLReg(PLL_REF_DIV); + + /* The DAC is also integrated */ + if ((ATIDac & ~0x0FU) != ATI_DAC_INTERNAL) + ClockDac = ATI_DAC_INTERNAL; + + break; + + case ATI_CLOCK_ATT20C408: + /* This one's also a RAMDAC */ + ClockDac = ATI_DAC_ATT20C408; + break; + + case ATI_CLOCK_IBMRGB514: + /* This one's also a RAMDAC */ + ClockDac = ATI_DAC_IBMRGB514; + ATIClockNumberToProgramme = 7; + break; + + default: + break; + } + + /* + * We now have up to two indications of what RAMDAC the adapter uses. + * They should be the same. The following test and corresponding + * action are under construction. + */ + if (ATIDac != ClockDac) + { + ErrorF("Mach64 RAMDAC probe discrepancy detected:\n" + " ATIDac=0x%02X; ClockDac=0x%02X.\n", ATIDac, ClockDac); + + if (ATIDac == ATI_DAC_IBMRGB514) + { + ATIProgrammableClock = ATI_CLOCK_IBMRGB514; + ATIClockDescriptor = ATIClockDescriptors + ATI_CLOCK_IBMRGB514; + ATIClockNumberToProgramme = 7; + } + else + ATIDac = ClockDac; /* For now */ + } + + /* + * For adapters with supported programmable clock generators, set an + * initial estimate for maxClock. This value might be reduced later + * due to RAMDAC considerations. + */ + if (ATIClockDescriptor->MaxN > 0) + { + int Numerator = ATIClockDescriptor->MaxN * ATIReferenceNumerator; + int Denominator = ATIClockDescriptor->MinM * + ATIReferenceDenominator * ATIClockDescriptor->PostDividers[0]; + + /* + * An integrated PLL behaves as though the reference frequency were + * doubled. + */ + if (ATIProgrammableClock == ATI_CLOCK_INTERNAL) + Numerator <<= 1; + + vga256InfoRec.maxClock = (Numerator / (Denominator * 1000)) * 1000; + } + + /* + * Use the XF86Config's ChipSet specification to decide which CRTC to + * use for the video modes generated by the server. + */ + if (!ATIUsingPlanarModes && (ATIChipSet == ATI_CHIPSET_ATI)) + { + ATICRTC = ATI_CRTC_MACH64; + + /* Support higher depths on integrated controllers */ + if (ATIChip >= ATI_CHIP_264CT) + { + if ((xf86weight.red == 5) && (xf86weight.blue == 5) && + (xf86weight.green >= 5) && (xf86weight.green <= 6)) + ATI.ChipHas16bpp = TRUE; + ATI.ChipHas24bpp = + ATI.ChipHas32bpp = TRUE; + } + } + + /* + * Decide which aperture(s) to enable to allow CPU access to video + * memory. + */ + if ((ATICRTC == ATI_CRTC_MACH64) || (ATIChip >= ATI_CHIP_264CT)) + { + /* Possibly set up for a linear aperture */ + OFLG_SET(OPTION_NOLINEAR_MODE, &ATI.ChipOptionFlags); + + if (!ATIUsingPlanarModes && + !OFLG_ISSET(OPTION_NOLINEAR_MODE, &vga256InfoRec.options) && + xf86LinearVidMem()) + { + /* Get the adapter's linear aperture configuration */ + IO_Value = inl(ATIIOPortCONFIG_CNTL); + ATI.ChipLinearBase = GetBits(IO_Value, CFG_MEM_AP_LOC) << 22; + if ((IO_Value & CFG_MEM_AP_SIZE) != CFG_MEM_AP_SIZE) + ATI.ChipLinearSize = + GetBits(IO_Value, CFG_MEM_AP_SIZE) << 22; + + /* Except for PCI, allow user override */ + if (ATIBusType != ATI_BUS_PCI) + { + if (ATIChip >= ATI_CHIP_88800GXE) + IO_Value2 = vga256InfoRec.MemBase & + ~((unsigned long)((1 << 24) - 1)); + else if (MachvideoRam >= 4096) + IO_Value2 = vga256InfoRec.MemBase & + ~((unsigned long)((1 << 23) - 1)); + else + IO_Value2 = vga256InfoRec.MemBase & + ~((unsigned long)((1 << 22) - 1)); + if (IO_Value2 && + (IO_Value2 <= + (GetBits(CFG_MEM_AP_LOC, CFG_MEM_AP_LOC) << 22))) + ATI.ChipLinearBase = IO_Value2; + if ((ATIChip < ATI_CHIP_264CT) && (MachvideoRam < 4096)) + ATI.ChipLinearSize = 4 * 1024 * 1024; + else + ATI.ChipLinearSize = 8 * 1024 * 1024; + } + + if (ATI.ChipLinearBase && ATI.ChipLinearSize) + ATI.ChipUseLinearAddressing = TRUE; + } + + if (ATIVGAAdapter == ATI_ADAPTER_NONE) + { + /* Reset banking functions */ + ATI.ChipSetRead = ATI.ChipSetWrite = + ATI.ChipSetReadWrite = (BankFunction *)NoopDDA; + } + else + { + /* + * Enable the small dual paged apertures, even if the linear + * aperture is available. + */ + ATIUsingSmallApertures = TRUE; + + /* Reset banking functions */ + if (ATIUsingPlanarModes) + { + ATI.ChipSetRead = ATIMach64SetReadPlanar; + ATI.ChipSetWrite = ATIMach64SetWritePlanar; + ATI.ChipSetReadWrite = ATIMach64SetReadWritePlanar; + } + else + { + ATI.ChipSetRead = ATIMach64SetReadPacked; + ATI.ChipSetWrite = ATIMach64SetWritePacked; + ATI.ChipSetReadWrite = ATIMach64SetReadWritePacked; + } + + /* Set banking port numbers */ + ATIIOPortMEM_VGA_RP_SEL = ATIIOPort(MEM_VGA_RP_SEL); + ATIIOPortMEM_VGA_WP_SEL = ATIIOPort(MEM_VGA_WP_SEL); + } + } + } + + if ((ATIChipHasVGAWonder) && (ATIChip <= ATI_CHIP_88800GXD)) + { + /* + * Set up extended VGA register addressing. Note that, for Mach64's, + * only the GX-C & GX-D controllers allow the setting of this address. + */ + if ((ATIChip < ATI_CHIP_88800GXC) && + (Signature == BIOS_Signature) && + (BIOSWord(0x10U)) && + (!(BIOSWord(0x10U) & ~(SPARSE_IO_BASE | IO_BYTE_SELECT)))) + { + /* Pick up extended register index I/O port number */ + ATIIOPortVGAWonder = BIOSWord(0x10U); + } + PutReg(GRAX, 0x50U, GetByte(ATIIOPortVGAWonder, 0)); + PutReg(GRAX, 0x51U, GetByte(ATIIOPortVGAWonder, 1) | ATIVGAOffset); + } + + xf86DisableIOPorts(vga256InfoRec.scrnIndex); + ATIEnterLeave(ENTER); /* Unlock registers */ + + /* Sometimes, the BIOS lies about the chip */ + if ((ATIChip >= ATI_CHIP_28800_4) && (ATIChip <= ATI_CHIP_28800_6)) + { + IO_Value = GetBits(ATIGetExtReg(0xAAU), 0x0FU) + + (ATI_CHIP_28800_4 - 4); + if ((IO_Value <= ATI_CHIP_28800_6) && (IO_Value > ATIChip)) + ATIChip = IO_Value; + } + + if ((xf86Verbose) || + (ATIChip == ATI_CHIP_NONE) || (ATIChip == ATI_CHIP_Mach64) || + ((ATIVGAAdapter == ATI_ADAPTER_NONE) && (ATICRTC == ATI_CRTC_VGA))) + { + ErrorF("Using XFree86 ATI driver version " ATI_VERSION_NAME ".\n"); + ErrorF("%s graphics controller detected.\n", ATIChipNames[ATIChip]); + if ((ATIChip >= ATI_CHIP_68800) && (ATIChip != ATI_CHIP_68800_3)) + { + ErrorF("Chip type %04X", ATIChipType); + if (!(ATIChipType & ~(CHIP_CODE_0 | CHIP_CODE_1))) + ErrorF(" (%c%c)", GetBits(ATIChipType, CHIP_CODE_1) + 0x41U, + GetBits(ATIChipType, CHIP_CODE_0) + 0x41U); + else if ((ATIChipType & 0x4040U) == 0x4040U) + ErrorF(" \"%c%c\"", GetByte(ATIChipType, 1), + GetByte(ATIChipType, 0)); + if ((ATIChip >= ATI_CHIP_264CT) && (ATIChip != ATI_CHIP_Mach64)) + ErrorF(", version %d, foundry %s", ATIChipVersion, + ATIFoundryNames[ATIChipFoundry]); + ErrorF(", class %d, revision 0x%02X.\n", ATIChipClass, + ATIChipRevision); + } + if (ATIAdapter >= ATI_ADAPTER_MACH8) + { + ErrorF("%s interface detected", ATIBusNames[ATIBusType]); + if (ATIAdapter == ATI_ADAPTER_MACH64) + ErrorF("; %s I/O base is 0x%04X", + (ATIIODecoding == SPARSE_IO) ? "Sparse" : "Block", + ATIIOBase); + ErrorF(".\n"); + } + if (ATIMachChip != ATI_CHIP_NONE) + ErrorF("%s graphics accelerator detected, with %d kB of" + " coprocessor memory.\n", ATIChipNames[ATIMachChip], + MachvideoRam); + if ((ATIVGAAdapter == ATI_ADAPTER_NONE) && + (Signature == BIOS_Signature)) + ErrorF("Unknown chip descriptor in BIOS: 0x%02X%02X%02X%02X.\n", + BIOS[0x40U], BIOS[0x41U], BIOS[0x42U], BIOS[0x43U]); + ErrorF("%s video adapter detected.\n", ATIAdapterNames[ATIAdapter]); + } + + if ((ATIDac & ~0x0FU) == ATI_DAC_INTERNAL) + { + if (xf86Verbose) + ErrorF("Internal RAMDAC (subtype %d) detected.\n", ATIDac & 0x0FU); + } + else for (DAC = ATIDACDescriptors; ; DAC++) + { + if (ATIDac == DAC->DACType) + { + if (xf86Verbose) + ErrorF("%s RAMDAC detected.\n", DAC->DACName); + break; + } + if (ATIDac < DAC->DACType) + { + ErrorF("Unknown RAMDAC type (0x%02X) detected.\n", ATIDac); + break; + } + } + + switch (ATIAdapter) + { + case ATI_ADAPTER_8514A: + case ATI_ADAPTER_MACH8: + /* From now on, ignore any 8514/A or Mach8 accelerator */ + ATIAdapter = ATIVGAAdapter; + /* Accelerator and VGA cannot share memory */ + MachvideoRam = 0; + break; + + case ATI_ADAPTER_MACH32: + case ATI_ADAPTER_MACH64: + if ((ATIVGAAdapter == ATI_ADAPTER_NONE) && + (!ATI.ChipUseLinearAddressing || (ATICRTC == ATI_CRTC_VGA))) + { + ErrorF("VGA aperture is not available through this" + " adapter.\n"); + ATIEnterLeave(LEAVE); + vga256InfoRec.BIOSbase = saved_BIOSbase; + return FALSE; + } + if (saved_BIOSbase != vga256InfoRec.BIOSbase) + { + ErrorF("BIOS Base Address changed to 0x%08X.\n", + vga256InfoRec.BIOSbase); + OFLG_CLR(XCONFIG_BIOSBASE, &vga256InfoRec.xconfigFlag); + } + break; + + default: + break; + } + + if (ATIChip == ATI_CHIP_NONE) + ErrorF("Support for this video adapter is highly experimental!\n"); + + if (ATIAdapter == ATI_ADAPTER_VGA) + { + if (ATIUsingPlanarModes) + VGAvideoRam = 256; + else + VGAvideoRam = 64; + + /* + * The XF86Config videoRam must be limited because generic VGA doesn't + * implement video memory banking. + */ + if (VGAvideoRam < vga256InfoRec.videoRam) + { + ErrorF("XF86Config videoRam specification reduced to %d kB,\n" + " because generic VGA does not support banking.\n", + VGAvideoRam); + vga256InfoRec.videoRam = VGAvideoRam; + OFLG_CLR(XCONFIG_VIDEORAM, &vga256InfoRec.xconfigFlag); + } + } + else + { + /* Normalize any XF86Config videoRam value */ + if (ATIChip < ATI_CHIP_264VTB) + { + for (Index = 0; videoRamSizes[++Index]; ) + if (vga256InfoRec.videoRam < videoRamSizes[Index]) + break; + vga256InfoRec.videoRam = videoRamSizes[Index - 1]; + } + else + { + if (vga256InfoRec.videoRam <= 4096) + vga256InfoRec.videoRam &= ~(512 - 1); + else if (vga256InfoRec.videoRam <= 8192) + vga256InfoRec.videoRam &= ~(1024 - 1); + else if (vga256InfoRec.videoRam <= 16384) + vga256InfoRec.videoRam &= ~(2048 - 1); + else + vga256InfoRec.videoRam = 16 * 1024; + } + } + + /* + * The default videoRam value is what the accelerator (if any) thinks it + * has. Also, allow the user to override the accelerator's value. + */ + ATIvideoRam = MachvideoRam; + if (!vga256InfoRec.videoRam) + { + /* Normalization might have zeroed XF86Config videoRam value */ + OFLG_CLR(XCONFIG_VIDEORAM, &vga256InfoRec.xconfigFlag); + vga256InfoRec.videoRam = MachvideoRam; + } + else + MachvideoRam = vga256InfoRec.videoRam; + + if (ATIChipHasVGAWonder) + { + /* Find out how much video memory the VGA Wonder side thinks it has */ + if (ATIChip <= ATI_CHIP_18800_1) + { + IO_Value = ATIGetExtReg(0xBBU); + if (IO_Value & 0x20U) + VGAvideoRam = 512; + else + VGAvideoRam = 256; + if (MachvideoRam > 512) + MachvideoRam = 512; + } + else + { + IO_Value = ATIGetExtReg(0xB0U); + if (IO_Value & 0x08U) + VGAvideoRam = 1024; + else if (IO_Value & 0x10U) + VGAvideoRam = 512; + else + VGAvideoRam = 256; + if (MachvideoRam > 1024) + MachvideoRam = 1024; + } + } + + /* + * If there's no supported accelerator, default videoRam to what the VGA + * side believes. + */ + if (!vga256InfoRec.videoRam) + ATIvideoRam = vga256InfoRec.videoRam = VGAvideoRam; + else if ((ATIChip < ATI_CHIP_68800) || (ATIChip > ATI_CHIP_68800AX)) + /* + * After BIOS initialization, the accelerator (if any) and the VGA won't + * necessarily agree on the amount of video memory, depending on whether or + * where the memory boundary is configured. Any discrepancy will be + * resolved by ATIInit. + * + * However, it's possible that there is more video memory than VGA Wonder + * can architecturally handle. + */ + if ((MachvideoRam < vga256InfoRec.videoRam) && (ATICRTC == ATI_CRTC_VGA)) + if (OFLG_ISSET(OPTION_FB_DEBUG, &vga256InfoRec.options)) + ErrorF("Virtual resolutions requiring more than %d kB\n of video" + " memory might not function correctly.\n", + ATIUsing1bppModes ? (MachvideoRam / 4) : MachvideoRam); + else + { + /* + * Temporary code to disable virtual resolutions that are too + * large. + */ + if (OFLG_ISSET(XCONFIG_VIDEORAM, &vga256InfoRec.xconfigFlag)) + { + ErrorF("XF86Config videoRam specification reduced to %d kB due" + " to hardware limitations.\n See README.ati for more" + " information.\n", MachvideoRam); + OFLG_CLR(XCONFIG_VIDEORAM, &vga256InfoRec.xconfigFlag); + } + vga256InfoRec.videoRam = MachvideoRam; + } + + /* VT-B's and later have DSP registers */ + if ((ATIChip >= ATI_CHIP_264VTB) && (ATIIODecoding == BLOCK_IO) && + !ATIDSPProbe()) + { + ATIEnterLeave(LEAVE); + vga256InfoRec.BIOSbase = saved_BIOSbase; + return FALSE; + } + + /* Set up for video memory banking */ + vga256InfoRec.bankedMono = TRUE; + if (ATIUsingPlanarModes) + { + if (vga256InfoRec.videoRam <= 256) + vga256InfoRec.bankedMono = FALSE; + else if (ATIChip <= ATI_CHIP_18800_1) + if (OFLG_ISSET(OPTION_FB_DEBUG, &vga256InfoRec.options)) + ErrorF("Virtual resolutions requiring more than %s kB\n of" + " video memory might not function properly.\n See" + " README.ati for more information.\n", + ATIUsing1bppModes ? "64" : "256"); + else + { + /* Temporary code to disable banking in planar modes */ + if (OFLG_ISSET(XCONFIG_VIDEORAM, &vga256InfoRec.xconfigFlag)) + { + ErrorF("XF86Config videoRam specification reduced to 256" + " kB due to hardware limitations.\n See README.ati" + " for more information.\n"); + OFLG_CLR(XCONFIG_VIDEORAM, &vga256InfoRec.xconfigFlag); + } + vga256InfoRec.videoRam = 256; + vga256InfoRec.bankedMono = FALSE; + } + + /* Planar modes also need a larger virtual X rounding */ + ATI.ChipRounding = 32; + } + else if ((ATIChip >= ATI_CHIP_264CT) || (ATICRTC == ATI_CRTC_MACH64) || + ((ATIChip <= ATI_CHIP_18800) && (ATIvideoRam == 256))) + { + ATI.ChipRounding = 8; /* Reduce virtual X rounding requirements */ + # ifdef __TSI__ + /* A temporary kludge */ + if (!ATI.ChipUseLinearAddressing && + (vga256InfoRec.bitsPerPixel == 24)) + ATI.ChipRounding = 4096; + # endif /* __TSI__ */ + } + + if (ATI.ChipUseLinearAddressing) + { + MachvideoRam = (ATI.ChipLinearSize >> 10) - 2; /* 4? */ + if (vga256InfoRec.videoRam > MachvideoRam) + { + if (ATIChip < ATI_CHIP_264VTB) + { + /* + * Don't allow virtual resolution to overlay register + * aperture(s). + */ + vga256InfoRec.videoRam = MachvideoRam; + ErrorF("Virtual resolutions will be limited to %dkB to account" + " for\n accelerator register aperture.\n", MachvideoRam); + } + else + { + /* + * On VTB's and later, ATIInit disables the primary register + * aperture. This is done so the driver can get at the frame + * buffer memory behind it. For MMIO purposes, the auxillary + * register aperture will be used instead. Also, ignore the + * CONFIG_CNTL register's indication of linear aperture size, + * as it is insufficient for adapters with more than 8MB of + * video memory. + */ + if (vga256InfoRec.videoRam > (8 * 1024)) + ATI.ChipLinearSize = 16 * 1024 * 1024; + } + } + + ErrorF("Using %dMB linear aperture at 0x%08X.\n", + ATI.ChipLinearSize >> 20, ATI.ChipLinearBase); + + /* Only mmap what is needed */ + ATI.ChipLinearSize = vga256InfoRec.videoRam * 1024; + } + + if (ATIAdapter >= ATI_ADAPTER_MACH32) + { + if (ATIChip >= ATI_CHIP_264CT) + { + if (xf86Verbose || (ATIMemoryType == MEM_264_NONE) || + (ATIMemoryType >= MEM_264_TYPE_6)) + ATIPrintMemoryType(ATIMemoryTypeNames_264xT[ATIMemoryType]); + } + else if (ATIChip == ATI_CHIP_88800CX) + { + if (xf86Verbose || (ATIMemoryType == MEM_CX_TYPE_2) || + (ATIMemoryType >= MEM_CX_TYPE_4)) + ATIPrintMemoryType(ATIMemoryTypeNames_88800CX[ATIMemoryType]); + } + else if (ATIChip >= ATI_CHIP_68800) + { + if (xf86Verbose || (ATIMemoryType == MEM_MACH_TYPE_7)) + ATIPrintMemoryType(ATIMemoryTypeNames_Mach[ATIMemoryType]); + } + } + else if (ATIAdapter >= ATI_ADAPTER_V3) + if (xf86Verbose) + ATIPrintMemoryType((ATIGetExtReg(0xB7U) & 0x04U) ? "DRAM" : "VRAM"); + + /* Initialize for ATISwap */ + IO_Value = GetReg(SEQX, 0x04U) & 0x08U; + ATICurrentPlanes = 1; + if (!IO_Value) /* Adjust for planar modes */ + ATICurrentPlanes = 4; + WindowSize = ATI.ChipSegmentSize * ATICurrentPlanes; + ATICurrentBanks = ATIMaximumBanks = + ATIDivide(vga256InfoRec.videoRam, WindowSize, 10, 1); + + if (!ATIUsingSmallApertures) + { + ATISelectBankFunction = ATI.ChipSetReadWrite; + if (ATIVGAAdapter == ATI_ADAPTER_NONE) + ATICurrentBanks = 1; + } + else if (!(inb(ATIIOPortCONFIG_CNTL) & CFG_MEM_VGA_AP_EN)) + { + ATICurrentBanks = 1; + ATISelectBankFunction = (BankFunction *)NoopDDA; + } + else if (IO_Value) + ATISelectBankFunction = ATIMach64SetReadWritePacked; + else + ATISelectBankFunction = ATIMach64SetReadWritePlanar; + + /* + * Set the maximum allowable dot-clock frequency (in kHz). This is + * dependent on what the RAMDAC can handle (in non-pixmux mode, for now). + * For an internal DAC, assume it can handle whatever frequency the + * internal PLL can produce (with the reference divider set by BIOS + * initialization), but default maxClock to a lower chip-specific default. + */ + if ((ATIDac & ~0x0FU) == ATI_DAC_INTERNAL) + { + if (vga256InfoRec.dacSpeeds[0] < vga256InfoRec.maxClock) + { + int DefaultmaxClock = 135000; + + if ((ATIChip >= ATI_CHIP_264VTB) && (ATIChip != ATI_CHIP_Mach64)) + { + if (ATIChip >= ATI_CHIP_264GT3) + DefaultmaxClock = 230000; + else if (ATIChip >= ATI_CHIP_264VT3) + DefaultmaxClock = 200000; + else + DefaultmaxClock = 170000; + } + if (vga256InfoRec.dacSpeeds[0] > DefaultmaxClock) + vga256InfoRec.maxClock = vga256InfoRec.dacSpeeds[0]; + else if (DefaultmaxClock < vga256InfoRec.maxClock) + vga256InfoRec.maxClock = DefaultmaxClock; + } + } + else switch (ATIDac) + { + case ATI_DAC_STG1700: + case ATI_DAC_STG1702: + case ATI_DAC_STG1703: + vga256InfoRec.maxClock = 110000; + break; + + default: + vga256InfoRec.maxClock = 80000; + break; + } + + /* Determine available dot clock frequencies */ + ATIClockProbe(); + + /* + * If user did not specify any modes, attempt to create a default mode. + * Its timings will be taken from the mode in effect on driver entry. + */ + if ((vga256InfoRec.modes == NULL) && (ATIVGAAdapter != ATI_ADAPTER_NONE)) + { + const char *Message = NULL; + int MaxScreen; + + # ifndef BANKEDMONOVGA + if (ATIUsing1bppModes) + MaxScreen = (ATI.ChipSegmentSize << 3); + else + # endif + if (ATIUsingPlanarModes) + MaxScreen = vga256InfoRec.videoRam << 11; + else + MaxScreen = (vga256InfoRec.videoRam << 13) / + vga256InfoRec.bitsPerPixel; + + /* Get current timings */ + ATIGetMode(&DefaultMode); + + /* Check if generated mode can be used */ + if (!DefaultMode.SynthClock) + Message = "required dot clock cannot be determined"; + else if ((DefaultMode.SynthClock / 1000) > + (((vga256InfoRec.maxClock / 1000) * ATI.ChipClockDivFactor) / + ATI.ChipClockMulFactor)) + Message = "required dot clock greater than maxClock"; + else if ((DefaultMode.HDisplay * DefaultMode.VDisplay) > MaxScreen) + Message = "insufficient video memory"; + + if (Message) + ErrorF("Default %dx%d mode not used: %s.\n", DefaultMode.HDisplay, + DefaultMode.VDisplay, Message); + else + { + DefaultMode.prev = DefaultMode.next = ATI.ChipBuiltinModes = + &DefaultMode; + DefaultMode.name = "Default mode"; + ErrorF("The following default video mode will be used:\n"); + ATIPrintMode(&DefaultMode); + } + } + + /* Set chipset name */ + vga256InfoRec.chipset = ATIChipSetNames[ATIChipSet]; + + #ifndef MONOVGA + /* Call ATIScreenInit() to finalize screen initialization */ + vgaSetScreenInitHook(ATIScreenInit); + #endif + + /* Indicate supported options ... */ + if (ATIAdapter > ATI_ADAPTER_VGA) + { + OFLG_SET(OPTION_CSYNC, &ATI.ChipOptionFlags); + if (ATIChip >= ATI_CHIP_88800GXC) + OFLG_SET(OPTION_NOLINEAR_MODE, &ATI.ChipOptionFlags); + } + OFLG_SET(OPTION_PROBE_CLKS, &ATI.ChipOptionFlags); + OFLG_SET(OPTION_FB_DEBUG, &ATI.ChipOptionFlags); /* For testing */ + + /* ... and unsupported ones */ + if (vga256InfoRec.clockprog) + { + ErrorF("XF86Config ClockProg specification ignored.\n"); + vga256InfoRec.clockprog = NULL; + } + + /* + * Our caller doesn't necessarily get back to us. So, remove its + * privileges until it does. + */ + ATIEnterLeave(LEAVE); + + if (xf86Verbose > 1) + { + /* Spill the beans... */ + if (Signature == No_Signature) + ErrorF("\nNo BIOS signature found.\n"); + else if (Signature != BIOS_Signature) + ErrorF("\nBIOS signature found at offset 0x%04X.\n", Signature); + + if (ATIChipHasVGAWonder) + ErrorF("\nThe ATI extended VGA registers are being accessed at I/O" + " port 0x%04X.\n", ATIIOPortVGAWonder); + + if ((ATIChip < ATI_CHIP_88800GXC) && (Signature == BIOS_Signature)) + { + ErrorF("\n Signature code: \"%c%c\"", + BIOS[0x40U], BIOS[0x41U]); + ErrorF("\n BIOS version: %d.%d\n", + BIOS[0x4CU], BIOS[0x4DU]); + + ErrorF("\n Byte at offset 0x42 = 0x%02X\n", + BIOS[0x42U]); + ErrorF(" 8 and 16 bit ROM supported: %s\n", + BIOS[0x42U] & 0x01U ? "Yes" : "No"); + ErrorF(" Mouse chip present: %s\n", + BIOS[0x42U] & 0x02U ? "Yes" : "No"); + ErrorF(" Inport compatible mouse port: %s\n", + BIOS[0x42U] & 0x04U ? "Yes" : "No"); + ErrorF(" Micro Channel supported: %s\n", + BIOS[0x42U] & 0x08U ? "Yes" : "No"); + ErrorF(" Clock chip present: %s\n", + BIOS[0x42U] & 0x10U ? "Yes" : "No"); + ErrorF(" Uses C000:0000 to D000:FFFF: %s\n", + BIOS[0x42U] & 0x80U ? "Yes" : "No"); + + ErrorF("\n Byte at offset 0x44 = 0x%02X\n", + BIOS[0x44U]); + ErrorF(" Supports 70Hz non-interlaced: %s\n", + BIOS[0x44U] & 0x01U ? "No" : "Yes"); + ErrorF(" Supports Korean characters: %s\n", + BIOS[0x44U] & 0x02U ? "Yes" : "No"); + ErrorF(" Uses 45Mhz memory clock: %s\n", + BIOS[0x44U] & 0x04U ? "Yes" : "No"); + ErrorF(" Supports zero wait states: %s\n", + BIOS[0x44U] & 0x08U ? "Yes" : "No"); + ErrorF(" Uses paged ROMs: %s\n", + BIOS[0x44U] & 0x10U ? "Yes" : "No"); + ErrorF(" 8514/A hardware on adapter: %s\n", + BIOS[0x44U] & 0x40U ? "No" : "Yes"); + ErrorF(" 32K colour DAC on adapter: %s\n", + BIOS[0x44U] & 0x80U ? "Yes" : "No"); + } + + ATIPrintBIOS(BIOS, 0, Prefix_Size); + + if (ROMTable > 0) + ATIPrintBIOS(BIOS, ROMTable, ROMTable + 0x16U); + if (ClockTable > 0) + ATIPrintBIOS(BIOS, ClockTable - 0x06U, ClockTable + 0x1EU); + + if (xf86Verbose > 2) + { + ErrorF("\n On server entry:\n"); + + xf86EnableIOPorts(vga256InfoRec.scrnIndex); + ATIPrintRegisters(); + xf86DisableIOPorts(vga256InfoRec.scrnIndex); + } + } + + # ifdef XFreeXDGA + if (!ATIUsing1bppModes) + vga256InfoRec.directMode = XF86DGADirectPresent; + # endif + + return TRUE; + } *** /dev/null Tue Jun 30 11:49:09 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atiprobe.h Fri Mar 6 16:47:23 1998 *************** *** 0 **** --- 1,36 ---- + /* $TOG: atiprobe.h /main/1 1998/03/06 16:49:00 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atiprobe.h,v 1.1.2.1 1998/02/01 16:42:00 robin Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + #ifndef ___ATIPROBE_H___ + #define ___ATIPROBE_H___ 1 + + #include "atiproto.h" + #include "misc.h" + + extern Bool ATIProbe FunctionPrototype((void)); + + #endif /* ___ATIPROBE_H___ */ *** /dev/null Tue Jun 30 11:49:10 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atiproto.h Fri Mar 6 16:47:26 1998 *************** *** 0 **** --- 1,45 ---- + /* $TOG: atiproto.h /main/1 1998/03/06 16:49:04 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atiproto.h,v 1.1.2.1 1998/02/01 16:42:01 robin Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + #ifndef ___ATIPROTO_H___ + #define ___ATIPROTO_H___ 1 + + #include "Xfuncproto.h" + + /* + * This isn't quite ready for Xfuncproto.h yet. + */ + + #ifndef FunctionPrototype + # if NeedFunctionPrototypes + # define FunctionPrototype(FunctionArgumentTypes) FunctionArgumentTypes + # else + # define FunctionPrototype(FunctionArgumentTypes) () + # endif + #endif + + #endif /* ___ATIPROTO_H___ */ *** /dev/null Tue Jun 30 11:49:12 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atiregs.h Fri Mar 6 16:47:30 1998 *************** *** 0 **** --- 1,1133 ---- + /* $TOG: atiregs.h /main/1 1998/03/06 16:49:09 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atiregs.h,v 1.1.2.1 1998/02/01 16:42:01 robin Exp $ */ + /* + * Copyright 1994 through 1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + * + * Acknowledgements: + * Jake Richter, Panacea Inc., Londonderry, New Hampshire, U.S.A. + * Kevin E. Martin, martin@cs.unc.edu + * Tiago Gons, tiago@comosjn.hobby.nl + * Rickard E. Faith, faith@cs.unc.edu + * Scott Laird, lair@kimbark.uchicago.edu + * + * The intent here is to list all I/O ports for VGA (and its predecessors), + * ATI VGA Wonder, 8514/A, ATI Mach8, ATI Mach32 and ATI Mach64 video adapters, + * not just the ones in use by the VGA Wonder driver. + */ + + #ifndef ___ATIREGS_H___ + #define ___ATIREGS_H___ 1 + + #include "atiutil.h" + + /* I/O decoding definitions */ + #define SPARSE_IO_BASE 0x03fcu + #define SPARSE_IO_SELECT 0xfc00u + + #define BLOCK_IO_BASE 0xff00u + #define BLOCK_IO_SELECT 0x00fcu + + #define IO_BYTE_SELECT 0x0003u + + #define IOPortTag(_SparseIOSelect, _BlockIOSelect) \ + (SetBits(_SparseIOSelect, SPARSE_IO_SELECT) | \ + SetBits(_BlockIOSelect, BLOCK_IO_SELECT)) + #define SparseIOTag(_IOSelect) IOPortTag(_IOSelect, (unsigned)(-1)) + #define BlockIOTag(_IOSelect) IOPortTag((unsigned)(-1), _IOSelect) + + /* MDA/CGA/EGA/VGA I/O ports */ + #define GENVS 0x0102u /* Write (and Read on uC only) */ + + #define R_GENLPS 0x03b9u /* Read */ + + #define GENHP 0x03bfu + + #define ATTRX 0x03c0u + #define ATTRD 0x03c1u + #define GENS0 0x03c2u /* Read */ + #define GENMO 0x03c2u /* Write */ + #define GENENB 0x03c3u /* Read */ + #define SEQX 0x03c4u + #define SEQD 0x03c5u + #define VGA_DAC_MASK 0x03c6u + #define VGA_DAC_READ 0x03c7u + #define VGA_DAC_WRITE 0x03c8u + #define VGA_DAC_DATA 0x03c9u + #define R_GENFC 0x03cau /* Read */ + /* ? 0x03cbu */ + #define R_GENMO 0x03ccu /* Read */ + /* ? 0x03cdu */ + #define GRAX 0x03ceu + #define GRAD 0x03cfu + + #define GENB 0x03d9u + + #define GENLPS 0x03dcu /* Write */ + #define KCX 0x03ddu + #define KCD 0x03deu + + #define GENENA 0x46e8u /* Write */ + + /* I/O port base numbers */ + #define MonochromeIOBase 0x03b0u + #define ColourIOBase 0x03d0u + + /* Other EGA/CGA/VGA I/O ports */ + /* ?(_IOBase) (_IOBase + 0x00u) */ + /* ?(_IOBase) (_IOBase + 0x01u) */ + /* ?(_IOBase) (_IOBase + 0x02u) */ + /* ?(_IOBase) (_IOBase + 0x03u) */ + #define CRTX(_IOBase) (_IOBase + 0x04u) + #define CRTD(_IOBase) (_IOBase + 0x05u) + /* ?(_IOBase) (_IOBase + 0x06u) */ + /* ?(_IOBase) (_IOBase + 0x07u) */ + #define GENMC(_IOBase) (_IOBase + 0x08u) + /* ?(_IOBase) (_IOBase + 0x09u) */ + #define GENS1(_IOBase) (_IOBase + 0x0au) /* Read */ + #define GENFC(_IOBase) (_IOBase + 0x0au) /* Write */ + #define GENLPC(_IOBase) (_IOBase + 0x0bu) + /* ?(_IOBase) (_IOBase + 0x0cu) */ + /* ?(_IOBase) (_IOBase + 0x0du) */ + /* ?(_IOBase) (_IOBase + 0x0eu) */ + /* ?(_IOBase) (_IOBase + 0x0fu) */ + + /* 8514/A VESA approved register definitions */ + #define DISP_STAT 0x02e8u /* Read */ + #define SENSE 0x0001u /* Presumably belong here */ + #define VBLANK 0x0002u + #define HORTOG 0x0004u + #define H_TOTAL 0x02e8u /* Write */ + #define DAC_MASK 0x02eau + #define DAC_R_INDEX 0x02ebu + #define DAC_W_INDEX 0x02ecu + #define DAC_DATA 0x02edu + #define H_DISP 0x06e8u /* Write */ + #define H_SYNC_STRT 0x0ae8u /* Write */ + #define H_SYNC_WID 0x0ee8u /* Write */ + #define HSYNCPOL_POS 0x0000u + #define HSYNCPOL_NEG 0x0020u + #define H_POLARITY_POS HSYNCPOL_POS /* Sigh */ + #define H_POLARITY_NEG HSYNCPOL_NEG /* Sigh */ + #define V_TOTAL 0x12e8u /* Write */ + #define V_DISP 0x16e8u /* Write */ + #define V_SYNC_STRT 0x1ae8u /* Write */ + #define V_SYNC_WID 0x1ee8u /* Write */ + #define VSYNCPOL_POS 0x0000u + #define VSYNCPOL_NEG 0x0020u + #define V_POLARITY_POS VSYNCPOL_POS /* Sigh */ + #define V_POLARITY_NEG VSYNCPOL_NEG /* Sigh */ + #define DISP_CNTL 0x22e8u /* Write */ + #define ODDBNKENAB 0x0001u + #define MEMCFG_2 0x0000u + #define MEMCFG_4 0x0002u + #define MEMCFG_6 0x0004u + #define MEMCFG_8 0x0006u + #define DBLSCAN 0x0008u + #define INTERLACE 0x0010u + #define DISPEN_NC 0x0000u + #define DISPEN_ENAB 0x0020u + #define DISPEN_DISAB 0x0040u + #define R_H_TOTAL 0x26e8u /* Read */ + /* ? 0x2ae8u */ + /* ? 0x2ee8u */ + /* ? 0x32e8u */ + /* ? 0x36e8u */ + /* ? 0x3ae8u */ + /* ? 0x3ee8u */ + #define SUBSYS_STAT 0x42e8u /* Read */ + #define VBLNKFLG 0x0001u + #define PICKFLAG 0x0002u + #define INVALIDIO 0x0004u + #define GPIDLE 0x0008u + #define MONITORID_MASK 0x0070u + /* MONITORID_? 0x0000u */ + #define MONITORID_8507 0x0010u + #define MONITORID_8514 0x0020u + /* MONITORID_? 0x0030u */ + /* MONITORID_? 0x0040u */ + #define MONITORID_8503 0x0050u + #define MONITORID_8512 0x0060u + #define MONITORID_8513 0x0060u + #define MONITORID_NONE 0x0070u + #define _8PLANE 0x0080u + #define SUBSYS_CNTL 0x42e8u /* Write */ + #define RVBLNKFLG 0x0001u + #define RPICKFLAG 0x0002u + #define RINVALIDIO 0x0004u + #define RGPIDLE 0x0008u + #define IVBLNKFLG 0x0100u + #define IPICKFLAG 0x0200u + #define IINVALIDIO 0x0400u + #define IGPIDLE 0x0800u + #define CHPTEST_NC 0x0000u + #define CHPTEST_NORMAL 0x1000u + #define CHPTEST_ENAB 0x2000u + #define GPCTRL_NC 0x0000u + #define GPCTRL_ENAB 0x4000u + #define GPCTRL_RESET 0x8000u + #define ROM_PAGE_SEL 0x46e8u /* Write */ + #define ADVFUNC_CNTL 0x4ae8u /* Write */ + #define DISABPASSTHRU 0x0001u + #define CLOKSEL 0x0004u + /* ? 0x4ee8u */ + #define EXT_CONFIG_0 0x52e8u /* C & T 82C480 */ + #define EXT_CONFIG_1 0x56e8u /* C & T 82C480 */ + #define EXT_CONFIG_2 0x5ae8u /* C & T 82C480 */ + #define EXT_CONFIG_3 0x5ee8u /* C & T 82C480 */ + /* ? 0x62e8u */ + /* ? 0x66e8u */ + /* ? 0x6ae8u */ + /* ? 0x6ee8u */ + /* ? 0x72e8u */ + /* ? 0x76e8u */ + /* ? 0x7ae8u */ + /* ? 0x7ee8u */ + #define CUR_Y 0x82e8u + #define CUR_X 0x86e8u + #define DESTY_AXSTP 0x8ae8u /* Write */ + #define DESTX_DIASTP 0x8ee8u /* Write */ + #define ERR_TERM 0x92e8u + #define MAJ_AXIS_PCNT 0x96e8u /* Write */ + #define GP_STAT 0x9ae8u /* Read */ + #define GE_STAT 0x9ae8u /* Alias */ + #define DATARDY 0x0100u + #define DATA_READY DATARDY /* Alias */ + #define GPBUSY 0x0200u + #define CMD 0x9ae8u /* Write */ + #define WRTDATA 0x0001u + #define PLANAR 0x0002u + #define LASTPIX 0x0004u + #define LINETYPE 0x0008u + #define DRAW 0x0010u + #define INC_X 0x0020u + #define YMAJAXIS 0x0040u + #define INC_Y 0x0080u + #define PCDATA 0x0100u + #define _16BIT 0x0200u + #define CMD_NOP 0x0000u + #define CMD_OP_MSK 0xf000u + #define BYTSEQ 0x1000u + #define CMD_LINE 0x2000u + #define CMD_RECT 0x4000u + #define CMD_RECTV1 0x6000u + #define CMD_RECTV2 0x8000u + #define CMD_LINEAF 0xa000u + #define CMD_BITBLT 0xc000u + #define SHORT_STROKE 0x9ee8u /* Write */ + #define SSVDRAW 0x0010u + #define VECDIR_000 0x0000u + #define VECDIR_045 0x0020u + #define VECDIR_090 0x0040u + #define VECDIR_135 0x0060u + #define VECDIR_180 0x0080u + #define VECDIR_225 0x00a0u + #define VECDIR_270 0x00c0u + #define VECDIR_315 0x00e0u + #define BKGD_COLOR 0xa2e8u /* Write */ + #define FRGD_COLOR 0xa6e8u /* Write */ + #define WRT_MASK 0xaae8u /* Write */ + #define RD_MASK 0xaee8u /* Write */ + #define COLOR_CMP 0xb2e8u /* Write */ + #define BKGD_MIX 0xb6e8u /* Write */ + /* 0x001fu See MIX_* definitions below */ + #define BSS_BKGDCOL 0x0000u + #define BSS_FRGDCOL 0x0020u + #define BSS_PCDATA 0x0040u + #define BSS_BITBLT 0x0060u + #define FRGD_MIX 0xbae8u /* Write */ + /* 0x001fu See MIX_* definitions below */ + #define FSS_BKGDCOL 0x0000u + #define FSS_FRGDCOL 0x0020u + #define FSS_PCDATA 0x0040u + #define FSS_BITBLT 0x0060u + #define MULTIFUNC_CNTL 0xbee8u /* Write */ + #define MIN_AXIS_PCNT 0x0000u + #define SCISSORS_T 0x1000u + #define SCISSORS_L 0x2000u + #define SCISSORS_B 0x3000u + #define SCISSORS_R 0x4000u + #define MEM_CNTL 0x5000u + #define HORCFG_4 0x0000u + #define HORCFG_5 0x0001u + #define HORCFG_8 0x0002u + #define HORCFG_10 0x0003u + #define VRTCFG_2 0x0000u + #define VRTCFG_4 0x0004u + #define VRTCFG_6 0x0008u + #define VRTCFG_8 0x000cu + #define BUFSWP 0x0010u + #define PATTERN_L 0x8000u + #define PATTERN_H 0x9000u + #define PIX_CNTL 0xa000u + #define PLANEMODE 0x0004u + #define COLCMPOP_F 0x0000u + #define COLCMPOP_T 0x0008u + #define COLCMPOP_GE 0x0010u + #define COLCMPOP_LT 0x0018u + #define COLCMPOP_NE 0x0020u + #define COLCMPOP_EQ 0x0028u + #define COLCMPOP_LE 0x0030u + #define COLCMPOP_GT 0x0038u + #define MIXSEL_FRGDMIX 0x0000u + #define MIXSEL_PATT 0x0040u + #define MIXSEL_EXPPC 0x0080u + #define MIXSEL_EXPBLT 0x00c0u + /* ? 0xc2e8u */ + /* ? 0xc6e8u */ + /* ? 0xcae8u */ + /* ? 0xcee8u */ + /* ? 0xd2e8u */ + /* ? 0xd6e8u */ + /* ? 0xdae8u */ + /* ? 0xdee8u */ + #define PIX_TRANS 0xe2e8u + /* ? 0xe6e8u */ + /* ? 0xeae8u */ + /* ? 0xeee8u */ + /* ? 0xf2e8u */ + /* ? 0xf6e8u */ + /* ? 0xfae8u */ + /* ? 0xfee8u */ + + /* ATI Mach8 & Mach32 register definitions */ + #define OVERSCAN_COLOR_8 0x02eeu /* Write */ /* Mach32 */ + #define OVERSCAN_BLUE_24 0x02efu /* Write */ /* Mach32 */ + #define OVERSCAN_GREEN_24 0x06eeu /* Write */ /* Mach32 */ + #define OVERSCAN_RED_24 0x06efu /* Write */ /* Mach32 */ + #define CURSOR_OFFSET_LO 0x0aeeu /* Write */ /* Mach32 */ + #define CURSOR_OFFSET_HI 0x0eeeu /* Write */ /* Mach32 */ + #define CONFIG_STATUS_1 0x12eeu /* Read */ + #define CLK_MODE 0x0001u /* Mach8 */ + #define BUS_16 0x0002u /* Mach8 */ + #define MC_BUS 0x0004u /* Mach8 */ + #define EEPROM_ENA 0x0008u /* Mach8 */ + #define DRAM_ENA 0x0010u /* Mach8 */ + #define MEM_INSTALLED 0x0060u /* Mach8 */ + #define ROM_ENA 0x0080u /* Mach8 */ + #define ROM_PAGE_ENA 0x0100u /* Mach8 */ + #define ROM_LOCATION 0xfe00u /* Mach8 */ + #define _8514_ONLY 0x0001u /* Mach32 */ + #define BUS_TYPE 0x000eu /* Mach32 */ + #define ISA_16_BIT 0x0000u /* Mach32 */ + #define EISA 0x0002u /* Mach32 */ + #define MICRO_C_16_BIT 0x0004u /* Mach32 */ + #define MICRO_C_8_BIT 0x0006u /* Mach32 */ + #define LOCAL_386SX 0x0008u /* Mach32 */ + #define LOCAL_386DX 0x000au /* Mach32 */ + #define LOCAL_486 0x000cu /* Mach32 */ + #define PCI 0x000eu /* Mach32 */ + #define MEM_TYPE 0x0070u /* Mach32 */ + #define CHIP_DIS 0x0080u /* Mach32 */ + #define TST_VCTR_ENA 0x0100u /* Mach32 */ + #define DACTYPE 0x0e00u /* Mach32 */ + #define MC_ADR_DECODE 0x1000u /* Mach32 */ + #define CARD_ID 0xe000u /* Mach32 */ + #define HORZ_CURSOR_POSN 0x12eeu /* Write */ /* Mach32 */ + #define CONFIG_STATUS_2 0x16eeu /* Read */ + #define SHARE_CLOCK 0x0001u /* Mach8 */ + #define HIRES_BOOT 0x0002u /* Mach8 */ + #define EPROM_16_ENA 0x0004u /* Mach8 */ + #define WRITE_PER_BIT 0x0008u /* Mach8 */ + #define FLASH_ENA 0x0010u /* Mach8 */ + #define SLOW_SEQ_EN 0x0001u /* Mach32 */ + #define MEM_ADDR_DIS 0x0002u /* Mach32 */ + #define ISA_16_ENA 0x0004u /* Mach32 */ + #define KOR_TXT_MODE_ENA 0x0008u /* Mach32 */ + #define LOCAL_BUS_SUPPORT 0x0030u /* Mach32 */ + #define LOCAL_BUS_CONFIG_2 0x0040u /* Mach32 */ + #define LOCAL_BUS_RD_DLY_ENA 0x0080u /* Mach32 */ + #define LOCAL_DAC_EN 0x0100u /* Mach32 */ + #define LOCAL_RDY_EN 0x0200u /* Mach32 */ + #define EEPROM_ADR_SEL 0x0400u /* Mach32 */ + #define GE_STRAP_SEL 0x0800u /* Mach32 */ + #define VESA_RDY 0x1000u /* Mach32 */ + #define Z4GB 0x2000u /* Mach32 */ + #define LOC2_MDRAM 0x4000u /* Mach32 */ + #define VERT_CURSOR_POSN 0x16eeu /* Write */ /* Mach32 */ + #define FIFO_TEST_DATA 0x1aeeu /* Read */ /* Mach32 */ + #define CURSOR_COLOR_0 0x1aeeu /* Write */ /* Mach32 */ + #define CURSOR_COLOR_1 0x1aefu /* Write */ /* Mach32 */ + #define HORZ_CURSOR_OFFSET 0x1eeeu /* Write */ /* Mach32 */ + #define VERT_CURSOR_OFFSET 0x1eefu /* Write */ /* Mach32 */ + #define PCI_CNTL 0x22eeu /* Mach32-PCI */ + #define CRT_PITCH 0x26eeu /* Write */ + #define CRT_OFFSET_LO 0x2aeeu /* Write */ + #define CRT_OFFSET_HI 0x2eeeu /* Write */ + #define LOCAL_CNTL 0x32eeu /* Mach32 */ + #define FIFO_OPT 0x36eeu /* Write */ /* Mach8 */ + #define MISC_OPTIONS 0x36eeu /* Mach32 */ + #define W_STATE_ENA 0x0000u /* Mach32 */ + #define HOST_8_ENA 0x0001u /* Mach32 */ + #define MEM_SIZE_ALIAS 0x000cu /* Mach32 */ + #define MEM_SIZE_512K 0x0000u /* Mach32 */ + #define MEM_SIZE_1M 0x0004u /* Mach32 */ + #define MEM_SIZE_2M 0x0008u /* Mach32 */ + #define MEM_SIZE_4M 0x000cu /* Mach32 */ + #define DISABLE_VGA 0x0010u /* Mach32 */ + #define _16_BIT_IO 0x0020u /* Mach32 */ + #define DISABLE_DAC 0x0040u /* Mach32 */ + #define DLY_LATCH_ENA 0x0080u /* Mach32 */ + #define TEST_MODE 0x0100u /* Mach32 */ + #define BLK_WR_ENA 0x0400u /* Mach32 */ + #define _64_DRAW_ENA 0x0800u /* Mach32 */ + #define FIFO_TEST_TAG 0x3aeeu /* Read */ /* Mach32 */ + #define EXT_CURSOR_COLOR_0 0x3aeeu /* Write */ /* Mach32 */ + #define EXT_CURSOR_COLOR_1 0x3eeeu /* Write */ /* Mach32 */ + #define MEM_BNDRY 0x42eeu /* Mach32 */ + #define MEM_PAGE_BNDRY 0x000fu /* Mach32 */ + #define MEM_BNDRY_ENA 0x0010u /* Mach32 */ + #define SHADOW_CTL 0x46eeu /* Write */ + #define CLOCK_SEL 0x4aeeu + /* DISABPASSTHRU 0x0001u See ADVFUNC_CNTL */ + #define VFIFO_DEPTH_1 0x0100u /* Mach32 */ + #define VFIFO_DEPTH_2 0x0200u /* Mach32 */ + #define VFIFO_DEPTH_3 0x0300u /* Mach32 */ + #define VFIFO_DEPTH_4 0x0400u /* Mach32 */ + #define VFIFO_DEPTH_5 0x0500u /* Mach32 */ + #define VFIFO_DEPTH_6 0x0600u /* Mach32 */ + #define VFIFO_DEPTH_7 0x0700u /* Mach32 */ + #define VFIFO_DEPTH_8 0x0800u /* Mach32 */ + #define VFIFO_DEPTH_9 0x0900u /* Mach32 */ + #define VFIFO_DEPTH_A 0x0a00u /* Mach32 */ + #define VFIFO_DEPTH_B 0x0b00u /* Mach32 */ + #define VFIFO_DEPTH_C 0x0c00u /* Mach32 */ + #define VFIFO_DEPTH_D 0x0d00u /* Mach32 */ + #define VFIFO_DEPTH_E 0x0e00u /* Mach32 */ + #define VFIFO_DEPTH_F 0x0f00u /* Mach32 */ + #define COMPOSITE_SYNC 0x1000u + /* ? 0x4eeeu */ + #define ROM_ADDR_1 0x52eeu + #define BIOS_BASE_SEGMENT 0x007fu /* Mach32 */ + /* ? 0xff80u */ /* Mach32 */ + #define ROM_ADDR_2 0x56eeu /* Sick ... */ + #define SHADOW_SET 0x5aeeu /* Write */ + #define MEM_CFG 0x5eeeu /* Mach32 */ + #define MEM_APERT_SEL 0x0003u /* Mach32 */ + #define MEM_APERT_PAGE 0x000cu /* Mach32 */ + #define MEM_APERT_LOC 0xfff0u /* Mach32 */ + #define EXT_GE_STATUS 0x62eeu /* Read */ /* Mach32 */ + #define HORZ_OVERSCAN 0x62eeu /* Write */ /* Mach32 */ + #define VERT_OVERSCAN 0x66eeu /* Write */ /* Mach32 */ + #define MAX_WAITSTATES 0x6aeeu + #define GE_OFFSET_LO 0x6eeeu /* Write */ + #define BOUNDS_LEFT 0x72eeu /* Read */ + #define GE_OFFSET_HI 0x72eeu /* Write */ + #define BOUNDS_TOP 0x76eeu /* Read */ + #define GE_PITCH 0x76eeu /* Write */ + #define BOUNDS_RIGHT 0x7aeeu /* Read */ + #define EXT_GE_CONFIG 0x7aeeu /* Write */ /* Mach32 */ + #define MONITOR_ALIAS 0x0007u /* Mach32 */ + /* MONITOR_? 0x0000u */ /* Mach32 */ + #define MONITOR_8507 0x0001u /* Mach32 */ + #define MONITOR_8514 0x0002u /* Mach32 */ + /* MONITOR_? 0x0003u */ /* Mach32 */ + /* MONITOR_? 0x0004u */ /* Mach32 */ + #define MONITOR_8503 0x0005u /* Mach32 */ + #define MONITOR_8512 0x0006u /* Mach32 */ + #define MONITOR_8513 0x0006u /* Mach32 */ + #define MONITOR_NONE 0x0007u /* Mach32 */ + #define ALIAS_ENA 0x0008u /* Mach32 */ + #define PIXEL_WIDTH_4 0x0000u /* Mach32 */ + #define PIXEL_WIDTH_8 0x0010u /* Mach32 */ + #define PIXEL_WIDTH_16 0x0020u /* Mach32 */ + #define PIXEL_WIDTH_24 0x0030u /* Mach32 */ + #define RGB16_555 0x0000u /* Mach32 */ + #define RGB16_565 0x0040u /* Mach32 */ + #define RGB16_655 0x0080u /* Mach32 */ + #define RGB16_664 0x00c0u /* Mach32 */ + #define MULTIPLEX_PIXELS 0x0100u /* Mach32 */ + #define RGB24 0x0000u /* Mach32 */ + #define RGBx24 0x0200u /* Mach32 */ + #define BGR24 0x0400u /* Mach32 */ + #define xBGR24 0x0600u /* Mach32 */ + #define DAC_8_BIT_EN 0x4000u /* Mach32 */ + #define PIX_WIDTH_16BPP PIXEL_WIDTH_16 /* Mach32 */ + #define ORDER_16BPP_565 RGB16_565 /* Mach32 */ + #define BOUNDS_BOTTOM 0x7eeeu /* Read */ + #define MISC_CNTL 0x7eeeu /* Write */ /* Mach32 */ + #define PATT_DATA_INDEX 0x82eeu + /* ? 0x86eeu */ + /* ? 0x8aeeu */ + #define R_EXT_GE_CONFIG 0x8eeeu /* Read */ /* Mach32 */ + #define PATT_DATA 0x8eeeu /* Write */ + #define R_MISC_CNTL 0x92eeu /* Read */ /* Mach32 */ + #define BRES_COUNT 0x96eeu + #define EXT_FIFO_STATUS 0x9aeeu /* Read */ + #define LINEDRAW_INDEX 0x9aeeu /* Write */ + /* ? 0x9eeeu */ + #define LINEDRAW_OPT 0xa2eeu + #define BOUNDS_RESET 0x0100u + #define CLIP_MODE_0 0x0000u /* Clip exception disabled */ + #define CLIP_MODE_1 0x0200u /* Line segments */ + #define CLIP_MODE_2 0x0400u /* Polygon boundary lines */ + #define CLIP_MODE_3 0x0600u /* Patterned lines */ + #define DEST_X_START 0xa6eeu /* Write */ + #define DEST_X_END 0xaaeeu /* Write */ + #define DEST_Y_END 0xaeeeu /* Write */ + #define R_H_TOTAL_DISP 0xb2eeu /* Read */ /* Mach32 */ + #define SRC_X_START 0xb2eeu /* Write */ + #define R_H_SYNC_STRT 0xb6eeu /* Read */ /* Mach32 */ + #define ALU_BG_FN 0xb6eeu /* Write */ + #define R_H_SYNC_WID 0xbaeeu /* Read */ /* Mach32 */ + #define ALU_FG_FN 0xbaeeu /* Write */ + #define SRC_X_END 0xbeeeu /* Write */ + #define R_V_TOTAL 0xc2eeu /* Read */ + #define SRC_Y_DIR 0xc2eeu /* Write */ + #define R_V_DISP 0xc6eeu /* Read */ /* Mach32 */ + #define EXT_SHORT_STROKE 0xc6eeu /* Write */ + #define R_V_SYNC_STRT 0xcaeeu /* Read */ /* Mach32 */ + #define SCAN_X 0xcaeeu /* Write */ + #define VERT_LINE_CNTR 0xceeeu /* Read */ /* Mach32 */ + #define DP_CONFIG 0xceeeu /* Write */ + #define READ_WRITE 0x0001u + #define DATA_WIDTH 0x0200u + #define DATA_ORDER 0x1000u + #define FG_COLOR_SRC_FG 0x2000u + #define FG_COLOR_SRC_BLIT 0x6000u + #define R_V_SYNC_WID 0xd2eeu /* Read */ + #define PATT_LENGTH 0xd2eeu /* Write */ + #define PATT_INDEX 0xd6eeu /* Write */ + #define READ_SRC_X 0xdaeeu /* Read */ /* Mach32 */ + #define EXT_SCISSOR_L 0xdaeeu /* Write */ + #define READ_SRC_Y 0xdeeeu /* Read */ /* Mach32 */ + #define EXT_SCISSOR_T 0xdeeeu /* Write */ + #define EXT_SCISSOR_R 0xe2eeu /* Write */ + #define EXT_SCISSOR_B 0xe6eeu /* Write */ + /* ? 0xeaeeu */ + #define DEST_COMP_FN 0xeeeeu /* Write */ + #define DEST_COLOR_CMP_MASK 0xf2eeu /* Write */ /* Mach32 */ + /* ? 0xf6eeu */ + #define CHIP_ID 0xfaeeu /* Read */ /* Mach32 */ + #define CHIP_CODE_0 0x001fu /* Mach32 */ + #define CHIP_CODE_1 0x03e0u /* Mach32 */ + #define CHIP_CLASS 0x0c00u /* Mach32 */ + #define CHIP_REV 0xf000u /* Mach32 */ + #define LINEDRAW 0xfeeeu /* Write */ + + /* ATI Mach64 register definitions */ + #define CRTC_H_TOTAL_DISP IOPortTag(0x00u, 0x00u) + #define CRTC_H_TOTAL 0x000001fful + /* ? 0x0000fe00ul */ + #define CRTC_H_DISP 0x01ff0000ul + /* ? 0xfe000000ul */ + #define CRTC_H_SYNC_STRT_WID IOPortTag(0x01u, 0x01u) + #define CRTC_H_SYNC_STRT 0x000000fful + #define CRTC_H_SYNC_DLY 0x00000700ul + /* ? 0x00000800ul */ + #define CRTC_H_SYNC_STRT_HI 0x00001000ul + /* ? 0x0000e000ul */ + #define CRTC_H_SYNC_WID 0x001f0000ul + #define CRTC_H_SYNC_POL 0x00200000ul + /* ? 0xffc00000ul */ + #define CRTC_V_TOTAL_DISP IOPortTag(0x02u, 0x02u) + #define CRTC_V_TOTAL 0x000007fful + /* ? 0x0000f800ul */ + #define CRTC_V_DISP 0x07ff0000ul + /* ? 0xf8000000ul */ + #define CRTC_V_SYNC_STRT_WID IOPortTag(0x03u, 0x03u) + #define CRTC_V_SYNC_STRT 0x000007fful + /* ? 0x0000f800ul */ + #define CRTC_V_SYNC_WID 0x001f0000ul + #define CRTC_V_SYNC_POL 0x00200000ul + /* ? 0xffc00000ul */ + #define CRTC_VLINE_CRNT_VLINE IOPortTag(0x04u, 0x04u) + #define CRTC_OFF_PITCH IOPortTag(0x05u, 0x05u) + #define CRTC_OFFSET 0x000ffffful + #define CRTC_OFFSET_VGA 0x0003fffful + /* ? 0x00300000ul */ + #define CRTC_PITCH 0xffc00000ul + #define CRTC_INT_CNTL IOPortTag(0x06u, 0x06u) + #define CRTC_VBLANK 0x00000001ul + #define CRTC_VBLANK_INT_EN 0x00000002ul + #define CRTC_VBLANK_INT 0x00000004ul + #define CRTC_VLINE_INT_EN 0x00000008ul + #define CRTC_VLINE_INT 0x00000010ul + #define CRTC_VLINE_SYNC 0x00000020ul + #define CRTC_FRAME 0x00000040ul + /* ? 0x0000ff80ul */ + #define CRTC_SNAPSHOT_INT_EN 0x00000080ul /* GT3 */ + #define CRTC_SNAPSHOT_INT 0x00000100ul /* GT3 */ + #define CRTC_I2C_INT_EN 0x00000200ul /* GT3 */ + #define CRTC_I2C_INT 0x00000400ul /* GT3 */ + #define CRTC_CAPBUF0_INT_EN 0x00010000ul /* VT/GT */ + #define CRTC_CAPBUF0_INT 0x00020000ul /* VT/GT */ + #define CRTC_CAPBUF1_INT_EN 0x00040000ul /* VT/GT */ + #define CRTC_CAPBUF1_INT 0x00080000ul /* VT/GT */ + #define CRTC_OVERLAY_EOF_INT_EN 0x00100000ul /* VT/GT */ + #define CRTC_OVERLAY_EOF_INT 0x00200000ul /* VT/GT */ + #define CRTC_ONESHOT_CAP_INT_EN 0x00400000ul /* VT/GT */ + #define CRTC_ONESHOT_CAP_INT 0x00800000ul /* VT/GT */ + #define CRTC_BUSMASTER_EOL_INT_EN 0x01000000ul /* VTB/GTB/LT */ + #define CRTC_BUSMASTER_EOL_INT 0x02000000ul /* VTB/GTB/LT */ + #define CRTC_GP_INT_EN 0x04000000ul /* VTB/GTB/LT */ + #define CRTC_GP_INT 0x08000000ul /* VTB/GTB/LT */ + /* ? 0xf0000000ul */ + #define CRTC_VBLANK_BIT2 0x80000000ul /* GT3 */ + #define CRTC_INT_ENS /* *** UPDATE ME *** */ \ + ( \ + CRTC_VBLANK_INT_EN | \ + CRTC_VLINE_INT_EN | \ + CRTC_SNAPSHOT_INT_EN | \ + CRTC_I2C_INT_EN | \ + CRTC_CAPBUF0_INT_EN | \ + CRTC_CAPBUF1_INT_EN | \ + CRTC_OVERLAY_EOF_INT_EN | \ + CRTC_ONESHOT_CAP_INT_EN | \ + CRTC_BUSMASTER_EOL_INT_EN | \ + CRTC_GP_INT_EN | \ + 0 \ + ) + #define CRTC_INT_ACKS /* *** UPDATE ME *** */ \ + ( \ + CRTC_VBLANK_INT | \ + CRTC_VLINE_INT | \ + CRTC_SNAPSHOT_INT | \ + CRTC_I2C_INT | \ + CRTC_CAPBUF0_INT | \ + CRTC_CAPBUF1_INT | \ + CRTC_OVERLAY_EOF_INT | \ + CRTC_ONESHOT_CAP_INT | \ + CRTC_BUSMASTER_EOL_INT | \ + CRTC_GP_INT | \ + 0 \ + ) + #define CRTC_GEN_CNTL IOPortTag(0x07u, 0x07u) + #define CRTC_DBL_SCAN_EN 0x00000001ul + #define CRTC_INTERLACE_EN 0x00000002ul + #define CRTC_HSYNC_DIS 0x00000004ul + #define CRTC_VSYNC_DIS 0x00000008ul + #define CRTC_CSYNC_EN 0x00000010ul + #define CRTC_PIX_BY_2_EN 0x00000020ul + #define CRTC_DISPLAY_DIS 0x00000040ul + #define CRTC_VGA_XOVERSCAN 0x00000080ul + #define CRTC_PIX_WIDTH 0x00000700ul + #define CRTC_PIX_WIDTH_1BPP 0x00000000ul + #define CRTC_PIX_WIDTH_4BPP 0x00000100ul + #define CRTC_PIX_WIDTH_8BPP 0x00000200ul + #define CRTC_PIX_WIDTH_15BPP 0x00000300ul + #define CRTC_PIX_WIDTH_16BPP 0x00000400ul + #define CRTC_PIX_WIDTH_24BPP 0x00000500ul + #define CRTC_PIX_WIDTH_32BPP 0x00000600ul + /* ? 0x00000700ul */ + #define CRTC_BYTE_PIX_ORDER 0x00000800ul + /* ? 0x00003000ul */ + #define CRTC_FIFO_OVERFILL 0x0000c000ul /* VT/GT */ + #define CRTC_FIFO_LWM 0x000f0000ul + #define CRTC_VGA_128KAP_PAGING 0x00100000ul /* VT/GT */ + #define CRTC_DISPREQ_ONLY 0x00200000ul /* VT/GT */ + #define CRTC_VFC_SYNC_TRISTATE 0x00200000ul /* VTB/GTB/LT */ + #define CRTC_LOCK_REGS 0x00400000ul /* VT/GT */ + #define CRTC_SYNC_TRISTATE 0x00800000ul /* VT/GT */ + #define CRTC_EXT_DISP_EN 0x01000000ul + #define CRTC_EN 0x02000000ul + #define CRTC_DISP_REQ_EN 0x04000000ul + #define CRTC_VGA_LINEAR 0x08000000ul + #define CRTC_VSYNC_FALL_EDGE 0x10000000ul + #define CRTC_VGA_TEXT_132 0x20000000ul + #define CRTC_CNT_EN 0x40000000ul + #define CRTC_CUR_B_TEST 0x80000000ul + #define DSP_CONFIG BlockIOTag(0x08u) /* VTB/GTB/LT */ + #define DSP_XCLKS_PER_QW 0x00003ffful + /* ? 0x00004000ul */ + #define DSP_FLUSH_WB 0x00008000ul + #define DSP_LOOP_LATENCY 0x000f0000ul + #define DSP_PRECISION 0x00700000ul + /* ? 0xff800000ul */ + #define DSP_ON_OFF BlockIOTag(0x09u) /* VTB/GTB/LT */ + #define DSP_OFF 0x000007fful + /* ? 0x0000f800ul */ + #define DSP_ON 0x07ff0000ul + /* ? 0xf8000000ul */ + #define TIMER_CONFIG BlockIOTag(0x0au) /* VTB/GTB/LT */ + #define MEM_BUF_CNTL BlockIOTag(0x0bu) /* VTB/GTB/LT */ + #define SHARED_CNTL BlockIOTag(0x0cu) /* VTB/GTB/LT */ + #define SHARED_MEM_CONFIG BlockIOTag(0x0du) /* VTB/GTB/LT */ + #define MEM_ADDR_CONFIG BlockIOTag(0x0du) /* GT3 */ + #define SHARED_CNTL_CTD BlockIOTag(0x0eu) /* CTD */ + /* ? 0x00fffffful */ + #define CTD_FIFO5 0x01000000ul + /* ? 0xfe000000ul */ + #define CRT_TRAP BlockIOTag(0x0eu) /* VTB/GTB/LT */ + #define DSTN_CONTROL BlockIOTag(0x0fu) /* LT */ + #define I2C_CNTL_0 BlockIOTag(0x0fu) /* GT3 */ + #define OVR_CLR IOPortTag(0x08u, 0x10u) + #define OVR_CLR_8 0x000000fful + #define OVR_CLR_B 0x0000ff00ul + #define OVR_CLR_G 0x00ff0000ul + #define OVR_CLR_R 0xff000000ul + #define OVR_WID_LEFT_RIGHT IOPortTag(0x09u, 0x11u) + #define OVR_WID_LEFT 0x0000003ful /* 0x0f on ! LT */ + /* ? 0x0000ffc0ul */ + #define OVR_WID_RIGHT 0x003f0000ul /* 0x0f0000 on ! LT */ + /* ? 0xffc00000ul */ + #define OVR_WID_TOP_BOTTOM IOPortTag(0x0au, 0x12u) + #define OVR_WID_TOP 0x000001fful /* 0x00ff on ! LT */ + /* ? 0x0000fe00ul */ + #define OVR_WID_BOTTOM 0x01ff0000ul /* 0x00ff0000 on ! LT */ + /* ? 0xfe000000ul */ + #define VGA_DSP_CONFIG BlockIOTag(0x13u) /* VTB/GTB/LT */ + #define VGA_DSP_XCLKS_PER_QW DSP_XCLKS_PER_QW + /* ? 0x000fc000ul */ + #define VGA_DSP_PREC_PCLKBY2 0x00700000ul + /* ? 0x00800000ul */ + #define VGA_DSP_PREC_PCLK 0x07000000ul + /* ? 0xf8000000ul */ + #define VGA_DSP_ON_OFF BlockIOTag(0x14u) /* VTB/GTB/LT */ + #define VGA_DSP_OFF DSP_OFF + /* ? 0x0000f800ul */ + #define VGA_DSP_ON DSP_ON + /* ? 0xf8000000ul */ + /* ? BlockIOTag(0x15u) */ + /* ? BlockIOTag(0x16u) */ + #define EXT_CRTC_GEN_CNTL BlockIOTag(0x17u) /* VT-A4 */ + #define CUR_CLR0 IOPortTag(0x0bu, 0x18u) + #define CUR_CLR1 IOPortTag(0x0cu, 0x19u) + #define CUR_OFFSET IOPortTag(0x0du, 0x1au) + #define CUR_HORZ_VERT_POSN IOPortTag(0x0eu, 0x1bu) + #define CUR_HORZ_VERT_OFF IOPortTag(0x0fu, 0x1cu) + #define CONFIG_PANEL BlockIOTag(0x1du) /* LT */ + #define GP_IO IOPortTag(0x1eu, 0x1eu) /* VT/GT */ + #define GP_IO_CNTL BlockIOTag(0x1fu) /* VT/GT */ + #define HW_DEBUG GP_IO_CNTL /* VTB/GTB/LT */ + #define SCRATCH_REG0 IOPortTag(0x10u, 0x20u) + #define SCRATCH_REG1 IOPortTag(0x11u, 0x21u) + /* BIOS_BASE_SEGMENT 0x0000007ful */ /* As above */ + /* ? 0x00000f80ul */ + #define BIOS_INIT_DAC_SUBTYPE 0x0000f000ul + /* ? 0xffff0000ul */ + #define SCRATCH_REG2 BlockIOTag(0x22u) /* LT */ + /* ? BlockIOTag(0x23u) */ + #define CLOCK_CNTL IOPortTag(0x12u, 0x24u) + #define CLOCK_BIT 0x00000004ul /* For ICS2595 */ + #define CLOCK_PULSE 0x00000008ul /* For ICS2595 */ + #define CLOCK_SELECT 0x0000000ful + #define CLOCK_DIVIDER 0x00000030ul + #define CLOCK_STROBE 0x00000040ul + #define CLOCK_DATA 0x00000080ul + /* ? 0x00000100ul */ + #define PLL_WR_EN 0x00000200ul /* For internal PLL */ + #define PLL_ADDR 0x00007c00ul /* For internal PLL */ + /* ? 0x00008000ul */ + #define PLL_DATA 0x00ff0000ul /* For internal PLL */ + /* ? 0xff000000ul */ + #define CONFIG_STAT64_1 BlockIOTag(0x25u) /* GT3 */ + #define CONFIG_STAT64_2 BlockIOTag(0x26u) /* GT3 */ + /* ? BlockIOTag(0x27u) */ + #define BUS_CNTL IOPortTag(0x13u, 0x28u) + #define BUS_WS 0x0000000ful + #define BUS_DBL_RESYNC 0x00000001ul /* VTB/GTB/LT */ + #define BUS_MSTR_RESET 0x00000002ul /* VTB/GTB/LT */ + #define BUS_FLUSH_BUF 0x00000004ul /* VTB/GTB/LT */ + #define BUS_STOP_REQ_DIS 0x00000008ul /* VTB/GTB/LT */ + #define BUS_ROM_WS 0x000000f0ul + #define BUS_APER_REG_DIS 0x00000010ul /* VTB/GTB/LT */ + #define BUS_EXTRA_PIPE_DIS 0x00000020ul /* VTB/GTB/LT */ + #define BUS_MASTER_DIS 0x00000040ul /* VTB/GTB/LT */ + #define BUS_ROM_WRT_EN 0x00000080ul /* GT3 */ + #define BUS_ROM_PAGE 0x00000f00ul + #define BUS_ROM_DIS 0x00001000ul + #define BUS_IO_16_EN 0x00002000ul /* GX */ + #define BUS_PCI_READ_RETRY_EN 0x00002000ul /* VTB/GTB/LT */ + #define BUS_DAC_SNOOP_EN 0x00004000ul + #define BUS_PCI_RETRY_EN 0x00008000ul /* VT/GT */ + #define BUS_PCI_WRT_RETRY_EN 0x00008000ul /* VTB/GTB/LT */ + #define BUS_FIFO_WS 0x000f0000ul + #define BUS_RETRY_WS 0x000f0000ul /* VTB/GTB/LT */ + #define BUS_FIFO_ERR_INT_EN 0x00100000ul + #define BUS_MSTR_RD_MULT 0x00100000ul /* VTB/GTB/LT */ + #define BUS_FIFO_ERR_INT 0x00200000ul + #define BUS_MSTR_RD_LINE 0x00200000ul /* VTB/GTB/LT */ + #define BUS_HOST_ERR_INT_EN 0x00400000ul + #define BUS_SUSPEND 0x00400000ul /* GT3 */ + #define BUS_HOST_ERR_INT 0x00800000ul + #define BUS_LAT16X 0x00800000ul /* GT3 */ + #define BUS_PCI_DAC_WS 0x07000000ul + #define BUS_RD_DISCARD_EN 0x01000000ul /* VTB/GTB/LT */ + #define BUS_RD_ABORT_EN 0x02000000ul /* VTB/GTB/LT */ + #define BUS_MSTR_WS 0x04000000ul /* VTB/GTB/LT */ + #define BUS_PCI_DAC_DLY 0x08000000ul + #define BUS_EXT_REG_EN 0x08000000ul /* VT/GT */ + #define BUS_PCI_MEMW_WS 0x10000000ul + #define BUS_MSTR_DISCONNECT_EN 0x10000000ul /* VTB/GTB/LT */ + #define BUS_PCI_BURST_DEC 0x20000000ul /* GX/CX */ + #define BUS_BURST 0x20000000ul /* 264xT */ + #define BUS_WRT_BURST 0x20000000ul /* VTB/GTB/LT */ + #define BUS_RDY_READ_DLY 0xc0000000ul + #define BUS_READ_BURST 0x40000000ul /* VTB/GTB/LT */ + #define BUS_RDY_READ_DLY_B 0x80000000ul /* VTB/GTB/LT */ + /* ? BlockIOTag(0x29u) */ + #define HFB_PITCH_ADDR BlockIOTag(0x2au) /* LT */ + #define EXT_MEM_CNTL BlockIOTag(0x2bu) /* VTB/GTB/LT */ + #define MEM_INFO IOPortTag(0x14u, 0x2cu) /* Renamed MEM_CNTL */ + #define CTL_MEM_SIZE 0x00000007ul + /* ? 0x00000008ul */ + #define CTL_MEM_REFRESH 0x00000078ul /* VT/GT */ + #define CTL_MEM_SIZEB 0x0000000ful /* VTB/GTB/LT */ + #define CTL_MEM_RD_LATCH_EN 0x00000010ul + #define CTL_MEM_RD_LATCH_DLY 0x00000020ul + #define CTL_MEM_LATENCY 0x00000030ul /* VTB/GTB/LT */ + #define CTL_MEM_SD_LATCH_EN 0x00000040ul + #define CTL_MEM_SD_LATCH_DLY 0x00000080ul + #define CTL_MEM_LATCH 0x000000c0ul /* VTB/GTB/LT */ + #define CTL_MEM_FULL_PLS 0x00000100ul + #define CTL_MEM_CYC_LNTH_AUX 0x00000180ul /* VT/GT */ + #define CTL_MEM_TRP 0x00000300ul /* VTB/GTB/LT */ + #define CTL_MEM_CYC_LNTH 0x00000600ul + #define CTL_MEM_REFRESH_RATE 0x00001800ul /* 264xT */ + #define CTL_MEM_TRCD 0x00000c00ul /* VTB/GTB/LT */ + #define CTL_MEM_WR_RDY_SEL 0x00000800ul /* GX/CX */ + #define CTL_MEM_EXT_RMW_CYC_EN 0x00001000ul /* GX/CX */ + #define CTL_MEM_TCRD 0x00001000ul /* VTB/GTB/LT */ + #define CTL_MEM_DLL_RESET 0x00002000ul /* VT/GT */ + #define CTL_MEM_TR2W 0x00002000ul /* GT3 */ + #define CTL_MEM_ACTV_PRE 0x0000c000ul /* VT/GT */ + #define CTL_MEM_CAS_PHASE 0x00004000ul /* GT3 */ + #define CTL_MEM_OE_PULLBACK 0x00008000ul /* GT3 */ + #define CTL_MEM_BNDRY 0x00030000ul + #define CTL_MEM_BNDRY_0K 0x00000000ul + #define CTL_MEM_BNDRY_256K 0x00010000ul + #define CTL_MEM_BNDRY_512K 0x00020000ul + #define CTL_MEM_BNDRY_1024K 0x00030000ul + #define CTL_MEM_DLL_GAIN_CNTL 0x00030000ul /* VT/GT */ + #define CTL_MEM_BNDRY_EN 0x00040000ul + #define CTL_MEM_SDRAM_RESET 0x00040000ul /* VT/GT */ + #define CTL_MEM_TRAS 0x00070000ul /* VTB/GTB/LT */ + #define CTL_MEM_TILE_SELECT 0x00180000ul /* VT/GT */ + #define CTL_MEM_REFRESH_DIS 0x00080000ul /* VTB/GTB/LT */ + #define CTL_MEM_LOW_LATENCY_MODE 0x00200000ul /* VT/GT */ + #define CTL_MEM_CDE_PULLBACK 0x00400000ul /* VT/GT */ + #define CTL_MEM_REFRESH_RATE_B 0x00700000ul /* VTB/GTB/LT */ + /* ? 0x00800000ul */ + #define CTL_MEM_PIX_WIDTH 0x07000000ul + #define CTL_MEM_LOWER_APER_ENDIAN 0x03000000ul /* VTB/GTB/LT */ + #define CTL_MEM_OE_SELECT 0x18000000ul /* VT/GT */ + #define CTL_MEM_UPPER_APER_ENDIAN 0c0c000000ul /* VTB/GTB/LT */ + /* ? 0xe0000000ul */ + #define CTL_MEM_PAGE_SIZE 0x30000000ul /* VTB/GTB/LT */ + #define MEM_VGA_WP_SEL IOPortTag(0x15u, 0x2du) + #define MEM_VGA_WPS0 0x0000fffful + #define MEM_VGA_WPS1 0xffff0000ul + #define MEM_VGA_RP_SEL IOPortTag(0x16u, 0x2eu) + #define MEM_VGA_RPS0 0x0000fffful + #define MEM_VGA_RPS1 0xffff0000ul + #define LT_GIO BlockIOTag(0x2fu) /* LT */ + #define I2C_CNTL_1 BlockIOTag(0x2fu) /* GT3 */ + #define DAC_REGS IOPortTag(0x17u, 0x30u) /* 4 separate bytes */ + #define DAC_CNTL IOPortTag(0x18u, 0x31u) + #define DAC_EXT_SEL 0x00000003ul + #define DAC_EXT_SEL_RS2 0x000000001ul + #define DAC_EXT_SEL_RS3 0x000000002ul + #define DAC_RANGE_CTL 0x00000003ul /* VTB/GTB/LT */ + #define DAC_BLANKING 0x00000004ul /* 264xT */ + #define DAC_CMP_DIS 0x00000008ul /* 264xT */ + /* ? 0x00000070ul */ + #define DAC_CMP_OUTPUT 0x00000080ul /* 264xT */ + #define DAC_8BIT_EN 0x00000100ul + #define DAC_PIX_DLY 0x00000600ul + #define DAC_DIRECT 0x00000400ul /* VTB/GTB/LT */ + #define DAC_BLANK_ADJ 0x00001800ul + #define DAC_PAL_CLK_SEL 0x00000800ul /* VTB/GTB/LT */ + #define DAC_VGA_ADR_EN 0x00002000ul + #define DAC_FEA_CON_EN 0x00004000ul /* 264xT */ + #define DAC_PDMN 0x00008000ul /* 264xT */ + #define DAC_TYPE 0x00070000ul + /* ? 0x00f80000ul */ + #define DAC_MON_ID_STATE0 0x01000000ul /* GX-E+/CX */ + #define DAC_GIO_STATE_1 0x01000000ul /* 264xT */ + #define DAC_MON_ID_STATE1 0x02000000ul /* GX-E+/CX */ + #define DAC_GIO_STATE_0 0x02000000ul /* 264xT */ + #define DAC_MON_ID_STATE2 0x04000000ul /* GX-E+/CX */ + #define DAC_GIO_STATE_4 0x04000000ul /* 264xT */ + #define DAC_MON_ID_DIR0 0x08000000ul /* GX-E+/CX */ + #define DAC_GIO_DIR_1 0x08000000ul /* 264xT */ + #define DAC_MON_ID_DIR1 0x10000000ul /* GX-E+/CX */ + #define DAC_GIO_DIR_0 0x10000000ul /* 264xT */ + #define DAC_MON_ID_DIR2 0x20000000ul /* GX-E+/CX */ + #define DAC_GIO_DIR_4 0x20000000ul /* 264xT */ + #define DAC_MAN_CMP_STATE 0x40000000ul /* GX-E+ */ + #define DAC_RW_WS 0x80000000ul /* VT/GT */ + #define HORZ_STRETCHING BlockIOTag(0x32u) /* LT */ + #define EXT_DAC_REGS BlockIOTag(0x32u) /* GT3 */ + #define VERT_STRETCHING BlockIOTag(0x33u) /* LT */ + #define GEN_TEST_CNTL IOPortTag(0x19u, 0x34u) + #define GEN_EE_DATA_OUT 0x00000001ul /* GX/CX */ + #define GEN_GIO2_DATA_OUT 0x00000001ul /* 264xT */ + #define GEN_EE_CLOCK 0x00000002ul /* GX/CX */ + /* ? 0x00000002ul */ /* 264xT */ + #define GEN_EE_CHIP_SEL 0x00000004ul /* GX/CX */ + #define GEN_GIO3_DATA_OUT 0x00000004ul /* 264xT */ + #define GEN_EE_DATA_IN 0x00000008ul /* GX/CX */ + #define GEN_GIO2_DATA_IN 0x00000008ul /* 264xT */ + #define GEN_EE_EN 0x00000010ul /* GX/CX */ + #define GEN_GIO2_ENABLE 0x00000010ul /* 264xT */ + #define GEN_OVR_OUTPUT_EN 0x00000020ul /* GX/CX */ + #define GEN_GIO2_WRITE 0x00000020ul /* 264xT */ + #define GEN_OVR_POLARITY 0x00000040ul /* GX/CX */ + /* ? 0x00000040ul */ /* 264xT */ + #define GEN_CUR_EN 0x00000080ul + #define GEN_GUI_EN 0x00000100ul /* GX/CX */ + #define GEN_GUI_RESETB 0x00000100ul /* 264xT */ + #define GEN_BLOCK_WR_EN 0x00000200ul /* GX */ + /* ? 0x00000200ul */ /* CX/264xT */ + #define GEN_SOFT_RESET 0x00000200ul /* VTB/GTB/LT */ + /* ? 0x00000c00ul */ + #define GEN_TEST_VECT_MODE 0x00003000ul /* VT/GT */ + /* ? 0x0000c000ul */ + #define GEN_TEST_FIFO_EN 0x00010000ul /* GX/CX */ + #define GEN_TEST_GUI_REGS_EN 0x00020000ul /* GX/CX */ + #define GEN_TEST_VECT_EN 0x00040000ul /* GX/CX */ + #define GEN_TEST_CRC_STR 0x00080000ul /* GX-C/-D */ + /* ? 0x00080000ul */ /* GX-E+/CX */ + #define GEN_TEST_MODE_T 0x000f0000ul /* 264xT */ + #define GEN_TEST_MODE 0x00700000ul /* GX/CX */ + #define GEN_TEST_CNT_EN 0x00100000ul /* 264xT */ + #define GEN_TEST_CRC_EN 0x00200000ul /* 264xT */ + /* ? 0x00400000ul */ /* 264xT */ + /* ? 0x00800000ul */ + #define GEN_TEST_MEM_WR 0x01000000ul /* GX-C/-D */ + #define GEN_TEST_MEM_STROBE 0x02000000ul /* GX-C/-D */ + #define GEN_TEST_DST_SS_EN 0x04000000ul /* GX/CX */ + #define GEN_TEST_DST_SS_STROBE 0x08000000ul /* GX/CX */ + #define GEN_TEST_SRC_SS_EN 0x10000000ul /* GX/CX */ + #define GEN_TEST_SRC_SS_STROBE 0x20000000ul /* GX/CX */ + #define GEN_TEST_CNT_VALUE 0x3f000000ul /* 264xT */ + #define GEN_TEST_CC_EN 0x40000000ul /* GX/CX */ + #define GEN_TEST_CC_STROBE 0x80000000ul /* GX/CX */ + /* ? 0xc0000000ul */ /* 264xT */ + #define GEN_DEBUG_MODE 0xff000000ul /* VTB/GTB/LT */ + #define LCD_GEN_CTRL BlockIOTag(0x35u) /* LT */ + #define CUSTOM_MACRO_CNTL BlockIOTag(0x35u) /* GT3 */ + #define POWER_MANAGEMENT BlockIOTag(0x36u) /* LT */ + #define CONFIG_CNTL IOPortTag(0x1au, 0x37u) + #define CFG_MEM_AP_SIZE 0x00000003ul + #define CFG_MEM_VGA_AP_EN 0x00000004ul + /* ? 0x00000008ul */ + #define CFG_MEM_AP_LOC 0x00003ff0ul + /* ? 0x0000c000ul */ + #define CFG_CARD_ID 0x00070000ul + #define CFG_VGA_DIS 0x00080000ul + /* ? 0x00f00000ul */ + #define CFG_CDE_WINDOW 0x3f000000ul /* VT/GT */ + /* ? 0xc0000000ul */ + #define CONFIG_CHIP_ID IOPortTag(0x1bu, 0x38u) /* Read */ + #define CFG_CHIP_TYPE0 0x000000fful + #define CFG_CHIP_TYPE1 0x0000ff00ul + #define CFG_CHIP_TYPE 0x0000fffful + #define CFG_CHIP_CLASS 0x00ff0000ul + #define CFG_CHIP_REV 0xff000000ul + #define CFG_CHIP_VERSION 0x07000000ul /* 264xT */ + #define CFG_CHIP_FOUNDRY 0x38000000ul /* 264xT */ + #define CFG_CHIP_REVISION 0xc0000000ul /* 264xT */ + #define CONFIG_STATUS64_0 IOPortTag(0x1cu, 0x39u) /* Read (R/W (264xT)) */ + #define CFG_BUS_TYPE 0x00000007ul /* GX/CX */ + #define CFG_MEM_TYPE_T 0x00000007ul /* 264xT */ + #define CFG_MEM_TYPE 0x00000038ul /* GX/CX */ + #define CFG_DUAL_CAS_EN_T 0x00000008ul /* 264xT */ + #define CFG_ROM_128K_EN 0x00000008ul /* VTB/GTB/LT */ + #define CFG_RAM_REMAP 0x00000008ul /* GT3 */ + #define CFG_VGA_EN_T 0x00000010ul /* VT/GT */ + #define CFG_CLOCK_EN 0x00000020ul /* 264xT */ + #define CFG_DUAL_CAS_EN 0x00000040ul /* GX/CX */ + #define CFG_VMC_SENSE 0x00000040ul /* VT/GT */ + #define CFG_SHARED_MEM_EN 0x00000040ul /* VTB/GTB/LT */ + #define CFG_LOCAL_BUS_OPTION 0x00000180ul /* GX/CX */ + #define CFG_VFC_SENSE 0x00000080ul /* VT/GT */ + #define CFG_INIT_DAC_TYPE 0x00000e00ul /* GX/CX */ + #define CFG_INIT_CARD_ID 0x00007000ul /* GX-C/-D */ + #define CFG_BLK_WR_SIZE 0x00001000ul /* GX-E+ */ + #define CFG_INT_QSF_EN 0x00002000ul /* GX-E+ */ + /* ? 0x00004000ul */ /* GX-E+ */ + /* ? 0x00007000ul */ /* CX */ + #define CFG_TRI_BUF_DIS 0x00008000ul /* GX/CX */ + #define CFG_BOARD_ID 0x0000ff00ul /* VT/GT */ + #define CFG_EXT_RAM_ADDR 0x003f0000ul /* GX/CX */ + #define CFG_PANEL_ID 0x001f0000ul /* LT */ + #define CFG_ROM_DIS 0x00400000ul /* GX/CX */ + #define CFG_PCI33EN 0x00400000ul /* GT3 */ + #define CFG_VGA_EN 0x00800000ul /* GX/CX */ + #define CFG_FULLAGP 0x00800000ul /* GT3 */ + #define CFG_LOCAL_BUS_CFG 0x01000000ul /* GX/CX */ + #define CFG_CHIP_EN 0x02000000ul /* GX/CX */ + #define CFG_LOCAL_READ_DLY_DIS 0x04000000ul /* GX/CX */ + #define CFG_ROM_OPTION 0x08000000ul /* GX/CX */ + #define CFG_BUS_OPTION 0x10000000ul /* GX/CX */ + #define CFG_LOCAL_DAC_WR_EN 0x20000000ul /* GX/CX */ + #define CFG_VLB_RDY_DIS 0x40000000ul /* GX/CX */ + #define CFG_AP_4GBYTE_DIS 0x80000000ul /* GX/CX */ + #define CONFIG_STATUS64_1 IOPortTag(0x1du, 0x3au) /* Read */ + #define CFG_PCI_DAC_CFG 0x00000001ul /* GX/CX */ + /* ? 0x0000001eul */ /* GX/CX */ + #define CFG_1C8_IO_SEL 0x00000020ul /* GX/CX */ + /* ? 0xffffffc0ul */ /* GX/CX */ + #define CRC_SIG 0xfffffffful /* 264xT */ + #define MPP_CONFIG BlockIOTag(0x3bu) /* VTB/GTB/LT */ + #define MPP_STROBE_CONFIG BlockIOTag(0x3cu) /* VTB/GTB/LT */ + #define MPP_ADDR BlockIOTag(0x3du) /* VTB/GTB/LT */ + #define MPP_DATA BlockIOTag(0x3eu) /* VTB/GTB/LT */ + #define TVO_CNTL BlockIOTag(0x3fu) /* VTB/GTB/LT */ + /* GP_IO IOPortTag(0x1eu, 0x1eu) */ /* See above */ + /* CRTC_H_TOTAL_DISP IOPortTag(0x1fu, 0x00u) */ /* Duplicate */ + + /* Definitions for an ICS2595's programme word */ + #define ICS2595_CLOCK 0x000001f0ul + #define ICS2595_FB_DIV 0x0001fe00ul /* Feedback divider */ + #define ICS2595_POST_DIV 0x000c0000ul /* Post-divider */ + #define ICS2595_STOP 0x00300000ul /* Stop bits */ + #define ICS2595_TOGGLE (ICS2595_POST_DIV | ICS2595_STOP) + + /* Definitions for internal PLL registers on a 264xT */ + #define PLL_MPLL_CNTL 0x00u + #define MPLL_PC_GAIN 0x07u + #define MPLL_VC_GAIN 0x18u + #define MPLL_D_CYC 0x60u + #define MPLL_RANGE 0x80u + #define VPLL_CNTL 0x01u + #define VPLL_PC_GAIN 0x07u + #define VPLL_VC_GAIN 0x18u + #define VPLL_D_CYC 0x60u + #define VPLL_RANGE 0x80u + #define PLL_REF_DIV 0x02u + #define PLL_GEN_CNTL 0x03u + #define PLL_OVERRIDE 0x01u + #define PLL_MCLK_RESET 0x02u + #define PLL_OSC_EN 0x04u + #define PLL_EXT_CLK_EN 0x08u + #define PLL_MCLK_POST_DIV 0x30u + #define PLL_MCLK_SRC_SEL 0x40u + #define PLL_EXT_CLK_CNTL 0x80u /* CT/ET */ + #define PLL_DLL_PWDN 0x80u /* VTB/GTB/LT */ + #define PLL_MCLK_FB_DIV 0x04u + #define PLL_VCLK_CNTL 0x05u + #define PLL_VCLK_SRC_SEL 0x03u + #define PLL_VCLK_RESET 0x04u + #define PLL_VCLK_INVERT 0x08u + #define PLL_ECP_DIV 0x30u /* VT/GT */ + #define PLL_ERATE_GT_XRATE 0x40u /* VT/GT */ + #define PLL_SCALER_LOCK_EN 0x80u /* VT/GT */ + #define PLL_VCLK_POST_DIV 0x06u + #define PLL_VCLK0_POST_DIV 0x03u + #define PLL_VCLK1_POST_DIV 0x0cu + #define PLL_VCLK2_POST_DIV 0x30u + #define PLL_VCLK3_POST_DIV 0xc0u + #define PLL_VCLK0_FB_DIV 0x07u + #define PLL_VCLK1_FB_DIV 0x08u + #define PLL_VCLK2_FB_DIV 0x09u + #define PLL_VCLK3_FB_DIV 0x0au + #define PLL_XCLK_CNTL 0x0bu /* VT/GT */ + #define PLL_XCLK_MCLK_RATIO 0x03u + #define PLL_XCLK_SRC_SEL 0x07u /* VTB/GTB/LT */ + #define PLL_MFB_TIMES_4_2B 0x08u + #define PLL_VCLK0_XDIV 0x10u + #define PLL_VCLK1_XDIV 0x20u + #define PLL_VCLK2_XDIV 0x40u + #define PLL_VCLK3_XDIV 0x80u + #define PLL_FCP_CNTL 0x0cu /* VT/GT */ + #define PLL_FCP_POST_DIV 0x0fu + #define PLL_FCP_SRC_SEL 0x70u + #define PLL_DCLK_BY2_EN 0x80u + #define PLL_DLL_CNTL 0x0cu /* VTB/GTB/LT */ + #define PLL_DLL_REF_SRC 0x03u + #define PLL_DLL_FB_SRC 0x0cu + #define PLL_DLL_GAIN 0x30u + #define PLL_DLL_RESET 0x40u + #define PLL_DLL_HCLK_OUT_EN 0x80u + #define PLL_VFC_CNTL 0x0du /* VT/GT */ + #define PLL_DCLK_INVB 0x01u + #define PLL_DCLKBY2_EN 0x02u + #define PLL_VFC_2PHASE 0x04u + #define PLL_VFC_DELAY 0x18u + #define PLL_VFC_DCLKBY2_SHIFT 0x20u + /* ? 0xc0u */ + #define PLL_TEST_CNTL 0x0eu + #define PLL_TST_SRC_SEL 0x1fu + #define PLL_TST_DIVIDERS 0x20u + #define PLL_TST_MASK_READ 0x40u + #define PLL_TST_ANALOG_MON_EN 0x80u + #define PLL_TEST_COUNT 0x0fu + /* The following are 32-bit wide! */ + #define PLL_LVDSPLL_CNTL0 0x10u /* LT */ + #define PLL_FPDI_NS_TIMING 0x0000000ful + #define PLL_CURR_LEVEL 0x0000fff0ul + #define PLL_LVDS_TEST_MODE 0xffff0000ul + #define PLL_LVDSPLL_CNTL1 0x11u /* LT */ + #define PLL_LPPL_RANGE 0x0000000ful + #define PLL_LPLL_DUTY 0x00000ff0ul + #define PLL_LPLL_VC_GAIN 0x000ff000ul + #define PLL_LPLL_CP_GAIN 0xfff00000ul + /* Back to 8-bit values */ + #define PLL_AGP1_CNTL 0x12u /* GT3 */ + #define PLL_AGP2_CNTL 0x13u /* GT3 */ + #define PLL_DLL2_CNTL 0x14u /* GT3 */ + #define PLL_SCLK_FB_DIV 0x15u /* GT3 */ + #define PLL_SPLL_CNTL1 0x16u /* GT3 */ + #define PLL_SPLL_CNTL2 0x17u /* GT3 */ + #define PLL_APLL_STRAPS 0x18u /* GT3 */ + #define PLL_EXT_VPLL_CNTL 0x19u /* GT3 */ + #define PLL_EXT_VPLL_REF_DIV 0x1au /* GT3 */ + #define PLL_EXT_VPLL_FB_DIV 0x1bu /* GT3 */ + #define PLL_EXT_VPLL_MSB 0x1cu /* GT3 */ + #define PLL_HTOTAL_CNTL 0x1du /* GT3 */ + #define PLL_BYTE_CLK_CNTL 0x1eu /* GT3 */ + + /* Miscellaneous */ + + /* Current X, Y & Dest X, Y mask */ + #define COORD_MASK 0x07ffu + + /* The Mixes */ + #define MIX_MASK 0x001fu + + #define MIX_NOT_DST 0x0000u + #define MIX_0 0x0001u + #define MIX_1 0x0002u + #define MIX_DST 0x0003u + #define MIX_NOT_SRC 0x0004u + #define MIX_XOR 0x0005u + #define MIX_XNOR 0x0006u + #define MIX_SRC 0x0007u + #define MIX_NAND 0x0008u + #define MIX_NOT_SRC_OR_DST 0x0009u + #define MIX_SRC_OR_NOT_DST 0x000au + #define MIX_OR 0x000bu + #define MIX_AND 0x000cu + #define MIX_SRC_AND_NOT_DST 0x000du + #define MIX_NOT_SRC_AND_DST 0x000eu + #define MIX_NOR 0x000fu + + #define MIX_MIN 0x0010u + #define MIX_DST_MINUS_SRC 0x0011u + #define MIX_SRC_MINUS_DST 0x0012u + #define MIX_PLUS 0x0013u + #define MIX_MAX 0x0014u + #define MIX_HALF__DST_MINUS_SRC 0x0015u + #define MIX_HALF__SRC_MINUS_DST 0x0016u + #define MIX_AVERAGE 0x0017u + #define MIX_DST_MINUS_SRC_SAT 0x0018u + #define MIX_SRC_MINUS_DST_SAT 0x001au + #define MIX_HALF__DST_MINUS_SRC_SAT 0x001cu + #define MIX_HALF__SRC_MINUS_DST_SAT 0x001eu + #define MIX_AVERAGE_SAT 0x001fu + #define MIX_FN_PAINT MIX_SRC + + #endif /* ___ATIREGS_H___ */ *** /dev/null Tue Jun 30 11:49:13 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atireset.c Fri Mar 6 16:47:36 1998 *************** *** 0 **** --- 1,51 ---- + /* $TOG: atireset.c /main/1 1998/03/06 16:49:14 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atireset.c,v 1.1.2.1 1998/02/01 16:42:02 robin Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + #include "atiio.h" + #include "atireset.h" + #include "vga.h" + + /* + * ATISaveScreen -- + * + * This is called "SaveScreen" for historical reasons. It actually only + * performs a VGA sequencer reset. + */ + void + ATISaveScreen(const Bool start) + { + static Bool started = SS_FINISH; + + if (start == started) + return; + started = start; + + if (start == SS_START) + PutReg(SEQX, 0x00U, 0x02U); /* Start sequencer reset */ + else + PutReg(SEQX, 0x00U, 0x03U); /* End sequencer reset */ + } *** /dev/null Tue Jun 30 11:49:14 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atireset.h Fri Mar 6 16:47:40 1998 *************** *** 0 **** --- 1,36 ---- + /* $TOG: atireset.h /main/1 1998/03/06 16:49:18 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atireset.h,v 1.1.2.1 1998/02/01 16:42:02 robin Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + #ifndef ___ATIRESET_H___ + #define ___ATIRESET_H___ 1 + + #include "atiproto.h" + #include "misc.h" + + extern void ATISaveScreen FunctionPrototype((const Bool)); + + #endif /* ___ATIRESET_H___ */ *** /dev/null Tue Jun 30 11:49:16 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atiscrinit.c Fri Mar 6 16:47:44 1998 *************** *** 0 **** --- 1,47 ---- + /* $TOG: atiscrinit.c /main/1 1998/03/06 16:49:22 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atiscrinit.c,v 1.1.2.1 1998/02/01 16:42:03 robin Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + #include "aticmap.h" + #include "atiscrinit.h" + #include "vga.h" + + /* + * ATIScreenInit -- + * + * For now, this function is only used to replace a screen's StoreColors + * function. + */ + Bool + ATIScreenInit(ScreenPtr pScreen, pointer FrameBuffer, + int XVirtual, int YVirtual, int XResolution, int YResolution, + int XWidth) + { + if ((vga256InfoRec.depth > 1) && (vga256InfoRec.depth <= 8)) + pScreen->StoreColors = ATIStoreColours; + + return TRUE; + } *** /dev/null Tue Jun 30 11:49:17 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atiscrinit.h Fri Mar 6 16:47:48 1998 *************** *** 0 **** --- 1,37 ---- + /* $TOG: atiscrinit.h /main/1 1998/03/06 16:49:26 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atiscrinit.h,v 1.1.2.1 1998/02/01 16:42:04 robin Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + #ifndef ___ATISCRINIT_H___ + #define ___ATISCRINIT_H___ 1 + + #include "atiproto.h" + #include "screenint.h" + + extern Bool ATIScreenInit + FunctionPrototype((ScreenPtr, pointer, int, int, int, int, int)); + + #endif /* ___ATISCRINIT_H___ */ *** /dev/null Tue Jun 30 11:49:19 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atiutil.c Fri Mar 6 16:47:52 1998 *************** *** 0 **** --- 1,67 ---- + /* $TOG: atiutil.c /main/1 1998/03/06 16:49:29 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atiutil.c,v 1.1.2.1 1998/02/01 16:42:04 robin Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + #include "atiutil.h" + + /* + * ATIDivide -- + * + * Using integer arithmetic and avoiding overflows, this function finds the + * rounded integer that best approximates + * + * Numerator Shift + * ----------- * 2 + * Denominator + * + * using the specified rounding (floor, nearest or ceiling). + */ + int + ATIDivide(int Numerator, int Denominator, int Shift, const int RoundingKind) + { + int Multiplier, Divider; + int Rounding = 0; /* Default to floor */ + + /* Deal with right shifts */ + if (Shift < 0) + { + Divider = (Numerator - 1) ^ Numerator; + Multiplier = 1 << (-Shift); + if (Divider > Multiplier) + Divider = Multiplier; + Numerator /= Divider; + Denominator *= Multiplier / Divider; + Shift = 0; + } + + if (!RoundingKind) /* Nearest */ + Rounding = Denominator >> 1; + else if (RoundingKind > 0) /* Ceiling */ + Rounding = Denominator - 1; + + return ((Numerator / Denominator) << Shift) + + ((((Numerator % Denominator) << Shift) + Rounding) / Denominator); + } *** /dev/null Tue Jun 30 11:49:20 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atiutil.h Fri Mar 6 16:47:56 1998 *************** *** 0 **** --- 1,64 ---- + /* $TOG: atiutil.h /main/1 1998/03/06 16:49:33 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atiutil.h,v 1.1.2.1 1998/02/01 16:42:05 robin Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + #ifndef ___ATIUTIL_H___ + #define ___ATIUTIL_H___ 1 + + #include "atiproto.h" + + /* + * Prevent the C standard's insistence on unsigned long sizeof's from causing + * counter-intuitive results. + */ + #define SizeOf(_object) ((int)sizeof(_object)) + #define NumberOf(_what) (SizeOf(_what) / SizeOf(_what[0])) + + #define __ONE_MICROSECOND__ 100 /* This'll need calibration */ + + #define ATIDelay(_microseconds) \ + { \ + unsigned int _i, _j; \ + for (_i = 0; _i < _microseconds; _i++) \ + for (_j = 0; _j < __ONE_MICROSECOND__; _j++) \ + /* Nothing */; \ + } + + /* + * Macros to get/set a contiguous bit field. '_Mask' should not be + * self-modifying. + */ + #define _UnitOf(___Value) ((((___Value) ^ ((___Value) - 1)) + 1) >> 1) + #define GetBits(__Value, _Mask) (((__Value) & (_Mask)) / _UnitOf(_Mask)) + #define SetBits(__Value, _Mask) (((__Value) * _UnitOf(_Mask)) & (_Mask)) + + #define _ByteMask(__Byte) ((CARD8)(-1) << (8 * (__Byte))) + #define GetByte(_Value, _Byte) GetBits(_Value, _ByteMask(_Byte)) + #define SetByte(_Value, _Byte) SetBits(_Value, _ByteMask(_Byte)) + + extern int ATIDivide FunctionPrototype((int, int, int, const int)); + + #endif /* ___ATIUTIL_H___ */ *** /dev/null Tue Jun 30 11:49:21 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/ativalid.c Fri Mar 6 16:47:59 1998 *************** *** 0 **** --- 1,149 ---- + /* $TOG: ativalid.c /main/1 1998/03/06 16:49:37 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/ativalid.c,v 1.1.2.1 1998/02/01 16:42:05 robin Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + #include "atiadapter.h" + #include "atichip.h" + #include "aticrtc.h" + #include "atiregs.h" + #include "ativalid.h" + + /* + * NOTE: The numbers in here should eventually be related to the appropriate + * bit-field #define's. + */ + + /* + * ATIValidMode -- + * + * This checks for hardware-related limits on mode timings. This assumes + * xf86CheckMode has already done some basic consistency checks. + */ + int + ATIValidMode(DisplayModePtr mode, const Bool verbose, const int Flag) + { + int Limit; + int VDisplay = mode->VDisplay; + int VTotal = mode->VTotal; + + if (mode->Flags & V_DBLSCAN) + { + VDisplay <<= 1; + VTotal <<= 1; + } + + switch (ATICRTC) + { + case ATI_CRTC_VGA: + if ((mode->HDisplay >= 2056) || (mode->HTotal >= 2088)) + { + if (verbose) + ErrorF("Mode \"%s\" is too wide. Deleted.\n", mode->name); + return MODE_HSYNC; + } + + if ((mode->Flags & V_INTERLACE) && (ATIChip < ATI_CHIP_264CT)) + { + VDisplay >>= 1; + VTotal >>= 1; + } + + if ((VDisplay > 2048) || (VTotal > 2050)) + { + if (verbose) + ErrorF("Mode \"%s\" is too high. Deleted.\n", mode->name); + return MODE_VSYNC; + } + + if (ATIAdapter != ATI_ADAPTER_VGA) + break; + + if (mode->Flags & V_INTERLACE) + { + if (verbose) + ErrorF("Interlaced modes not supported by generic VGA." + " Mode \"%s\" deleted.\n", mode->name); + return MODE_VSYNC; + } + + if ((VDisplay > 1024) || (VTotal > 1025)) + { + if (verbose) + ErrorF("Mode \"%s\" is too high for generic VGA." + " Deleted.\n", mode->name); + return MODE_VSYNC; + } + break; + + case ATI_CRTC_MACH64: + Limit = (GetBits(CRTC_H_TOTAL, CRTC_H_TOTAL) + 1) << 3; + if (ATIChip < ATI_CHIP_264VT) + Limit >>= 1; /* CRTC_H_TOTAL is 1 bit narrower */ + if (mode->HTotal > Limit) + { + if (verbose) + ErrorF("Mode \"%s\" is too wide. Deleted.\n", mode->name); + return MODE_HSYNC; + } + + if ((mode->HTotal >> 3) == (mode->HDisplay >> 3)) + { + if (verbose) + ErrorF("Horizontal sync pulse too narrow. Mode \"%s\"" + " deleted.\n", mode->name); + return MODE_HSYNC; + } + + if (VTotal > ((int)GetBits(CRTC_V_TOTAL, CRTC_V_TOTAL) + 1)) + { + if (verbose) + ErrorF("Mode \"%s\" is too high. Deleted.\n", mode->name); + return MODE_VSYNC; + } + + /* + * ATI finally fixed accelerated doublescanning in the 264VT and + * later. On 88800's, the bit is documented to exist, but only + * doubles the vertical timings. On the 264CT & 264ET, the bit is + * ignored. + */ + if ((ATIChip < ATI_CHIP_264VT) && (mode->Flags & V_DBLSCAN)) + { + if (verbose) + ErrorF("The %s does not support accelerated doublescanned" + " modes.\n Mode \"%s\" deleted.\n", + ATIChipNames[ATIChip], mode->name); + return MODE_VSYNC; + } + + break; + + default: + break; + } + + return MODE_OK; + } *** /dev/null Tue Jun 30 11:49:22 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/ativalid.h Fri Mar 6 16:48:04 1998 *************** *** 0 **** --- 1,37 ---- + /* $TOG: ativalid.h /main/1 1998/03/06 16:49:41 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/ativalid.h,v 1.1.2.1 1998/02/01 16:42:06 robin Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + #ifndef ___ATIVALID_H___ + #define ___ATIVALID_H___ 1 + + #include "atiproto.h" + #include "xf86.h" + + extern int ATIValidMode FunctionPrototype((DisplayModePtr, const Bool, + const int)); + + #endif /* ___ATIVALID_H___ */ *** /dev/null Tue Jun 30 11:49:23 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/ativersion.h Fri Mar 6 16:48:07 1998 *************** *** 0 **** --- 1,38 ---- + /* $TOG: ativersion.h /main/1 1998/03/06 16:49:45 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/ativersion.h,v 1.1.2.2 1998/02/27 03:07:52 dawes Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + #ifndef ___ATIVERSION_H___ + #define ___ATIVERSION_H___ 1 + + #define ATI_VERSION_NAME "4.3" + + #define ATI_VERSION_MAJOR 4 + #define ATI_VERSION_MINOR 3 + + #define ATI_VERSION_CURRENT ((ATI_VERSION_MAJOR << 16) | ATI_VERSION_MINOR) + + #endif /* ___ATIVERSION_H___ */ *** /dev/null Tue Jun 30 11:49:25 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/ativga.c Fri Mar 6 16:48:11 1998 *************** *** 0 **** --- 1,310 ---- + /* $TOG: ativga.c /main/1 1998/03/06 16:49:49 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/ativga.c,v 1.1.2.1 1998/02/01 16:42:07 robin Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + #include "atiadapter.h" + #include "atichip.h" + #include "atidepth.h" + #include "atiio.h" + #include "atimono.h" + #include "ativga.h" + #include "atividmem.h" + + /* + * ATIVGASave -- + * + * This function is called to save the VGA portion of the current video state. + */ + void + ATIVGASave(ATIHWPtr save) + { + int Index; + + /* Save miscellaneous output register */ + save->std.MiscOutReg = inb(R_GENMO); + ATISetVGAIOBase(save->std.MiscOutReg); + + /* Save sequencer registers */ + for (Index = 0; Index < NumberOf(save->std.Sequencer); Index++) + save->std.Sequencer[Index] = GetReg(SEQX, Index); + + /* Save CRTC registers */ + for (Index = 0; Index < NumberOf(save->std.CRTC); Index++) + save->std.CRTC[Index] = GetReg(CRTX(vgaIOBase), Index); + + /* Save attribute controller registers */ + for (Index = 0; Index < NumberOf(save->std.Attribute); Index++) + { + (void) inb(GENS1(vgaIOBase)); /* Reset flip-flop */ + save->std.Attribute[Index] = GetReg(ATTRX, Index); + } + + /* Save graphics controller registers */ + for (Index = 0; Index < NumberOf(save->std.Graphics); Index++) + save->std.Graphics[Index] = GetReg(GRAX, Index); + } + + /* + * ATIVGAInit -- + * + * This function fills in the VGA portion of an ATIHWRec. + */ + void + ATIVGAInit(DisplayModePtr mode) + { + int Index, VDisplay; + + if (!mode) + { + /* + * An ATIHWRec structure has been allocated and cleared. Fill in the + * VGA data common to all modes generated by the server. + */ + + /* Initialize sequencer register values */ + ATINewHWPtr->std.Sequencer[0] = 0x03U; + if (ATIUsing1bppModes) + ATINewHWPtr->std.Sequencer[2] = 0x01U << BIT_PLANE; + else + ATINewHWPtr->std.Sequencer[2] = 0x0FU; + if (ATIUsingPlanarModes) + ATINewHWPtr->std.Sequencer[4] = 0x06U; + else if (ATIAdapter == ATI_ADAPTER_VGA) + ATINewHWPtr->std.Sequencer[4] = 0x0EU; + else + ATINewHWPtr->std.Sequencer[4] = 0x0AU; + + /* Initialize CRTC register values */ + if (!ATIUsingPlanarModes && + ((ATIChip >= ATI_CHIP_264CT) || + ((ATIChip <= ATI_CHIP_18800) && (ATIvideoRam == 256)))) + ATINewHWPtr->std.CRTC[19] = vga256InfoRec.displayWidth >> 3; + else + ATINewHWPtr->std.CRTC[19] = vga256InfoRec.displayWidth >> 4; + ATINewHWPtr->std.CRTC[24] = 0xFFU; + + /* Initialize attribute controller register values */ + if (ATIUsing1bppModes) + { + for (Index = 0; Index < 16; Index++) + if (Index & (0x01U << BIT_PLANE)) + ATINewHWPtr->std.Attribute[Index] = MONO_WHITE; + else + ATINewHWPtr->std.Attribute[Index] = MONO_BLACK; + ATINewHWPtr->std.Attribute[16] = 0x01U; + ATINewHWPtr->std.Attribute[17] = MONO_OVERSCAN; + } + else + { + for (Index = 1; Index < 16; Index++) + ATINewHWPtr->std.Attribute[Index] = Index; + if (ATIUsingPlanarModes) + ATINewHWPtr->std.Attribute[16] = 0x81U; + else + { + if (ATIAdapter == ATI_ADAPTER_VGA) + ATINewHWPtr->std.Attribute[16] = 0x41U; + else + ATINewHWPtr->std.Attribute[16] = 0x01U; + ATINewHWPtr->std.Attribute[17] = 0xFFU; + } + } + ATINewHWPtr->std.Attribute[18] = 0x0FU; + + /* Initialize graphics controller register values */ + if (ATIUsing1bppModes) + ATINewHWPtr->std.Graphics[4] = BIT_PLANE; + else if (ATIUsingPlanarModes) + ATINewHWPtr->std.Graphics[5] = 0x02U; + else if (ATIChip >= ATI_CHIP_264CT) + ATINewHWPtr->std.Graphics[5] = 0x40U; + if (ATIUsingSmallApertures && (ATIChip >= ATI_CHIP_264VTB)) + ATINewHWPtr->std.Graphics[6] = 0x01U; /* 128kB aperture */ + else + ATINewHWPtr->std.Graphics[6] = 0x05U; /* 64kB aperture */ + ATINewHWPtr->std.Graphics[7] = 0x0FU; + ATINewHWPtr->std.Graphics[8] = 0xFFU; + } + else + { + /* Adjust mode timings as needed, then fill in VGA data */ + if (!mode->CrtcHAdjusted) + { + mode->CrtcHAdjusted = TRUE; + mode->CrtcHDisplay = (mode->CrtcHDisplay >> 3) - 1; + mode->CrtcHSyncStart >>= 3; + mode->CrtcHSyncEnd >>= 3; + mode->CrtcHTotal = (mode->CrtcHTotal >> 3) - 5; + } + if (!ATIUsingPlanarModes && (ATIAdapter == ATI_ADAPTER_VGA)) + ATINewHWPtr->std.CRTC[23] = 0xC3U; + else + ATINewHWPtr->std.CRTC[23] = 0xE3U; + + /* + * It is necessary to redo all vertical adjustments that have been + * made. Doing so fixes a minor bug in doublescanned modes. + */ + mode->CrtcVDisplay = mode->VDisplay; + mode->CrtcVSyncStart = mode->VSyncStart; + mode->CrtcVSyncEnd = mode->VSyncEnd; + mode->CrtcVTotal = mode->VTotal; + + /* Adjust double scanned modes */ + if (mode->Flags & V_DBLSCAN) + { + mode->CrtcVDisplay <<= 1; + mode->CrtcVSyncStart <<= 1; + mode->CrtcVSyncEnd <<= 1; + mode->CrtcVTotal <<= 1; + } + + /* + * The following two adjustments to the vertical timings don't apply to + * generic VGA, because ATIValidMode has already weeded out the + * affected modes. + */ + if ((mode->Flags & V_INTERLACE) && (ATIChip < ATI_CHIP_264CT)) + { + mode->CrtcVDisplay >>= 1; + mode->CrtcVSyncStart >>= 1; + mode->CrtcVSyncEnd >>= 1; + mode->CrtcVTotal >>= 1; + } + if (mode->CrtcVTotal > 1024) + { + /* Use vertical doubling bit */ + ATINewHWPtr->std.CRTC[23] |= 0x04U; + mode->CrtcVDisplay >>= 1; + mode->CrtcVSyncStart >>= 1; + mode->CrtcVSyncEnd >>= 1; + mode->CrtcVTotal >>= 1; + } + + mode->CrtcVDisplay--; + mode->CrtcVTotal -= 2; + mode->CrtcVAdjusted = TRUE; + + /* Setup miscellanous output register value */ + ATINewHWPtr->std.MiscOutReg = 0x23U; + if ((mode->Flags & (V_PHSYNC | V_NHSYNC)) && + (mode->Flags & (V_PVSYNC | V_NVSYNC))) + { + if (mode->Flags & V_NHSYNC) + ATINewHWPtr->std.MiscOutReg |= 0x40U; + if (mode->Flags & V_NVSYNC) + ATINewHWPtr->std.MiscOutReg |= 0x80U; + } + else + { + VDisplay = mode->VDisplay; + if (mode->Flags & V_DBLSCAN) + VDisplay *= 2; + + if (VDisplay < 400) + ATINewHWPtr->std.MiscOutReg |= 0x80U; /* +hsync -vsync */ + else if (VDisplay < 480) + ATINewHWPtr->std.MiscOutReg |= 0x40U; /* -hsync +vsync */ + else if (VDisplay < 768) + ATINewHWPtr->std.MiscOutReg |= 0xC0U; /* -hsync -vsync */ + } + + /* Setup sequencer register values */ + if (mode->Flags & V_CLKDIV2) + ATINewHWPtr->std.Sequencer[1] = 0x09U; + else + ATINewHWPtr->std.Sequencer[1] = 0x01U; + + /* Setup CRTC register values */ + ATINewHWPtr->std.CRTC[0] = mode->CrtcHTotal; + ATINewHWPtr->std.CRTC[1] = mode->CrtcHDisplay; + ATINewHWPtr->std.CRTC[2] = mode->CrtcHSyncStart - 1; + ATINewHWPtr->std.CRTC[3] = (mode->CrtcHSyncEnd & 0x1FU) | 0x80U; + Index = ((mode->CrtcHSkew << 2) + 0x10U) & ~0x1FU; + if (Index < 0x0080) + ATINewHWPtr->std.CRTC[3] |= Index; + ATINewHWPtr->std.CRTC[4] = mode->CrtcHSyncStart; + ATINewHWPtr->std.CRTC[5] = ((mode->CrtcHSyncEnd & 0x20U) << 2) | + ((mode->CrtcHSyncEnd & 0x1FU) ); + ATINewHWPtr->std.CRTC[6] = mode->CrtcVTotal & 0xFFU; + ATINewHWPtr->std.CRTC[7] = ((mode->CrtcVTotal & 0x0100U) >> 8) | + ((mode->CrtcVDisplay & 0x0100U) >> 7) | + ((mode->CrtcVSyncStart & 0x0100U) >> 6) | + ((mode->CrtcVSyncStart & 0x0100U) >> 5) | + 0x10U | + ((mode->CrtcVTotal & 0x0200U) >> 4) | + ((mode->CrtcVDisplay & 0x0200U) >> 3) | + ((mode->CrtcVSyncStart & 0x0200U) >> 2); + ATINewHWPtr->std.CRTC[9] = ((mode->CrtcVSyncStart & 0x0200U) >> 4) | + 0x40U; + /* + * For doublescanned modes, setting bits 0-4 to 1 (which amounts to + * oring in 1) appears to produce more consistent results than simply + * setting bit 7. + */ + if (mode->Flags & V_DBLSCAN) + ATINewHWPtr->std.CRTC[9] |= 0x01U; + ATINewHWPtr->std.CRTC[16] = mode->CrtcVSyncStart & 0xFFU; + ATINewHWPtr->std.CRTC[17] = (mode->CrtcVSyncEnd & 0x0FU) | 0x20U; + ATINewHWPtr->std.CRTC[18] = mode->CrtcVDisplay & 0xFFU; + ATINewHWPtr->std.CRTC[21] = (mode->CrtcVSyncStart & 0xFFU); + ATINewHWPtr->std.CRTC[22] = (mode->CrtcVSyncEnd + 1) & 0xFFU; + } + } + + /* + * ATIVGARestore -- + * + * This function is called to load the VGA portion of a video mode. + */ + void + ATIVGARestore(ATIHWPtr restore) + { + int Index; + + /* Load miscellaneous output register */ + outb(GENMO, restore->std.MiscOutReg); + + /* Load sequencer in reverse index order; this also ends its reset */ + for (Index = NumberOf(restore->std.Sequencer); --Index >= 0; ) + PutReg(SEQX, Index, restore->std.Sequencer[Index]); + + /* Load CRTC */ + for (Index = 0; Index < NumberOf(restore->std.CRTC); Index++) + PutReg(CRTX(vgaIOBase), Index, restore->std.CRTC[Index]); + + /* Load attribute controller */ + (void) inb(GENS1(vgaIOBase)); /* Reset flip-flop */ + for (Index = 0; Index < NumberOf(restore->std.Attribute); Index++) + { + outb(ATTRX, Index); + outb(ATTRX, restore->std.Attribute[Index]); + } + + /* Load graphics controller */ + for (Index = 0; Index < NumberOf(restore->std.Graphics); Index++) + PutReg(GRAX, Index, restore->std.Graphics[Index]); + } *** /dev/null Tue Jun 30 11:49:26 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/ativga.h Fri Mar 6 16:48:15 1998 *************** *** 0 **** --- 1,38 ---- + /* $TOG: ativga.h /main/1 1998/03/06 16:49:53 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/ativga.h,v 1.1.2.1 1998/02/01 16:42:07 robin Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + #ifndef ___ATIVGA_H___ + #define ___ATIVGA_H___ 1 + + #include "aticrtc.h" + #include "xf86.h" + + extern void ATIVGASave FunctionPrototype((ATIHWPtr)); + extern void ATIVGAInit FunctionPrototype((DisplayModePtr)); + extern void ATIVGARestore FunctionPrototype((ATIHWPtr)); + + #endif /* ___ATIVGA_H___ */ *** /dev/null Tue Jun 30 11:49:27 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atividmem.c Fri Mar 6 16:48:19 1998 *************** *** 0 **** --- 1,84 ---- + /* $TOG: atividmem.c /main/1 1998/03/06 16:49:57 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atividmem.c,v 1.1.2.1 1998/02/01 16:42:08 robin Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + #include "atividmem.h" + #include "misc.h" + + /* + * The number of banks and planes the driver needs to deal with when saving or + * setting a video mode. + */ + unsigned int ATICurrentBanks, ATIMaximumBanks, ATICurrentPlanes; + + /* + * The amount of video memory that is on the adapter, as opposed to the amount + * to be made available to the server. + */ + int ATIvideoRam; + + CARD8 ATIUsingSmallApertures = FALSE; + + CARD8 ATIMemoryType = 0; + + /* Memory types for 68800's and 88800GX's */ + const char *ATIMemoryTypeNames_Mach[] = + { + "DRAM (256Kx4)", + "VRAM (256Kx4, x8, x16)", + "VRAM (256Kx16 with short shift register)", + "DRAM (256Kx16)", + "Graphics DRAM (256Kx16)", + "Enhanced VRAM (256Kx4, x8, x16)", + "Enhanced VRAM (256Kx16 with short shift register)", + "Unknown video memory type" + }; + + /* Memory types for 88800CX's */ + const char *ATIMemoryTypeNames_88800CX[] = + { + "DRAM (256Kx4, x8, x16)", + "EDO DRAM (256Kx4, x8, x16)", + "Unknown video memory type", + "DRAM (256Kx16 with assymetric RAS/CAS)", + "Unknown video memory type", + "Unknown video memory type", + "Unknown video memory type", + "Unknown video memory type" + }; + + /* Memory types for 264xT's */ + const char *ATIMemoryTypeNames_264xT[] = + { + "Disabled video memory", + "DRAM", + "EDO DRAM", + "Pseudo-EDO DRAM", + "SDRAM", + "SGRAM", + "Unknown video memory type", + "Unknown video memory type" + }; *** /dev/null Tue Jun 30 11:49:28 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atividmem.h Fri Mar 6 16:48:23 1998 *************** *** 0 **** --- 1,82 ---- + /* $TOG: atividmem.h /main/1 1998/03/06 16:50:01 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atividmem.h,v 1.1.2.1 1998/02/01 16:42:09 robin Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + #ifndef ___ATIVIDMEM_H___ + #define ___ATIVIDMEM_H___ 1 + + #include "Xmd.h" + + /* + * The number of banks and planes the driver needs to deal with when saving or + * setting a video mode. + */ + extern unsigned int ATICurrentBanks, ATIMaximumBanks, ATICurrentPlanes; + + /* + * The amount of video memory that is on the adapter, as opposed to the amount + * to be made available to the server. + */ + extern int ATIvideoRam; + + extern CARD8 ATIUsingSmallApertures; + + extern CARD8 ATIMemoryType; + + /* Memory types for 68800's and 88800GX's */ + #define MEM_MACH_DRAMx4 0 + #define MEM_MACH_VRAM 1 + #define MEM_MACH_VRAMssr 2 + #define MEM_MACH_DRAMx16 3 + #define MEM_MACH_GDRAM 4 + #define MEM_MACH_EVRAM 5 + #define MEM_MACH_EVRAMssr 6 + #define MEM_MACH_TYPE_7 7 + extern const char *ATIMemoryTypeNames_Mach[]; + + /* Memory types for 88800CX's */ + #define MEM_CX_DRAM 0 + #define MEM_CX_EDO 1 + #define MEM_CX_TYPE_2 2 + #define MEM_CX_DRAM_A 3 + #define MEM_CX_TYPE_4 4 + #define MEM_CX_TYPE_5 5 + #define MEM_CX_TYPE_6 6 + #define MEM_CX_TYPE_7 7 + extern const char *ATIMemoryTypeNames_88800CX[]; + + /* Memory types for 264xT's */ + #define MEM_264_NONE 0 + #define MEM_264_DRAM 1 + #define MEM_264_EDO 2 + #define MEM_264_PSEUDO_EDO 3 + #define MEM_264_SDRAM 4 + #define MEM_264_SGRAM 5 + #define MEM_264_TYPE_6 6 + #define MEM_264_TYPE_7 7 + extern const char *ATIMemoryTypeNames_264xT[]; + + #endif /* ___ATIVIDMEM_H___ */ *** /dev/null Tue Jun 30 11:49:29 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atiwonder.c Fri Mar 6 16:48:27 1998 *************** *** 0 **** --- 1,272 ---- + /* $TOG: atiwonder.c /main/1 1998/03/06 16:50:05 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atiwonder.c,v 1.1.2.1 1998/02/01 16:42:09 robin Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + /* The ATI x8800 chips use special registers for their extended VGA features. + * These registers are accessible through an index I/O port and a data I/O + * port. BIOS initialization stores the index port number in the Graphics + * register bank (0x03CE), indices 0x50 and 0x51. Unfortunately, for all but + * the 18800-x series of adapters, these registers are write-only (a.k.a. black + * holes). On all but Mach64's, the index port number can be found in the + * short integer at offset 0x10 in the BIOS. For Mach64's, this driver will + * use 0x01CE or 0x03CE as the index port number, depending on the I/O port + * decoding used. The data port number is one more than the index port number + * (i.e. 0x01CF). These ports differ slightly in their I/O behaviour from the + * normal VGA ones: + * + * write: outw(0x01CE, (data << 8) | index); + * read: outb(0x01CE, index); data = inb(0x01CF); + * + * Two consecutive byte-writes to the data port will not work. Furthermore an + * index written to 0x01CE is usable only once. Note also that the setting of + * ATI extended registers (especially those with clock selection bits) should + * be bracketed by a sequencer reset. + * + * The number of these extended VGA registers varies by chipset. The 18800 + * series have 16, the 28800 series have 32, while Mach32's and Mach64's have + * 64. The last 16 on each have almost identical definitions. Thus, the BIOS + * (and this driver) sets up an indexing scheme whereby the last 16 extended + * VGA registers are accessed at indices 0xB0 through 0xBF on all chipsets. + */ + + #include "atichip.h" + #include "atidepth.h" + #include "atiio.h" + #include "atividmem.h" + #include "atiwonder.h" + + /* + * ATIVGAWonderSave -- + * + * This function is called to save the VGA Wonder portion of the current video + * state. + */ + void + ATIVGAWonderSave(ATIHWPtr save) + { + save->b0 = ATIGetExtReg(0xB0U); + save->b1 = ATIGetExtReg(0xB1U); + save->b2 = ATIGetExtReg(0xB2U); + save->b3 = ATIGetExtReg(0xB3U); + save->b5 = ATIGetExtReg(0xB5U); + save->b6 = ATIGetExtReg(0xB6U); + save->b8 = ATIGetExtReg(0xB8U); + save->b9 = ATIGetExtReg(0xB9U); + save->ba = ATIGetExtReg(0xBAU); + save->bd = ATIGetExtReg(0xBDU); + if (ATIChip > ATI_CHIP_18800) + { + save->be = ATIGetExtReg(0xBEU); + if (ATIChip >= ATI_CHIP_28800_2) + { + save->bf = ATIGetExtReg(0xBFU); + save->a3 = ATIGetExtReg(0xA3U); + save->a6 = ATIGetExtReg(0xA6U); + save->a7 = ATIGetExtReg(0xA7U); + save->ab = ATIGetExtReg(0xABU); + save->ac = ATIGetExtReg(0xACU); + save->ad = ATIGetExtReg(0xADU); + save->ae = ATIGetExtReg(0xAEU); + } + } + } + + /* + * ATIVGAWonderInit -- + * + * This function fills in the VGA Wonder portion of an ATIHWRec structure + * occurrentce. + */ + void + ATIVGAWonderInit(DisplayModePtr mode) + { + if (!mode) + { + /* + * Fill in VGA Wonder data that is common to all video modes generated + * by the server. + */ + ATINewHWPtr->b3 = ATIGetExtReg(0xB3U) & 0x20U; + if (ATIUsingPlanarModes) + ATINewHWPtr->b6 = 0x40U; + else + ATINewHWPtr->b6 = 0x04U; + if (ATIChip <= ATI_CHIP_18800) + ATINewHWPtr->ba = 0x08U; + else if (ATIChip >= ATI_CHIP_28800_2) + { + if (ATIvideoRam > 256) + ATINewHWPtr->b6 |= 0x01U; + ATINewHWPtr->bf = ATIGetExtReg(0xBFU) & 0x5FU; + ATINewHWPtr->a3 = ATIGetExtReg(0xA3U) & 0x67U; + ATINewHWPtr->ab = ATIGetExtReg(0xABU) & 0xE7U; + ATINewHWPtr->ae = ATIGetExtReg(0xAEU) & 0xF0U; + } + } + else + { + /* Set up default horizontal display enable skew */ + if ((ATIChip >= ATI_CHIP_28800_2) && (ATIChip <= ATI_CHIP_28800_6) && + !(mode->Flags & V_HSKEW)) + { + /* + * Modes using the higher clock frequencies need a non-zero Display + * Enable Skew. The following number has been empirically + * determined to be somewhere between 4.2 and 4.7 MHz. + */ + # define Display_Enable_Skew_Threshold 4500 + + /* Set a reasonable default Display Enable Skew */ + mode->HSkew = mode->CrtcHSkew = + ATIDivide(vga256InfoRec.clock[mode->Clock], + Display_Enable_Skew_Threshold, 0, 0); + } + mode->Flags |= V_HSKEW; + + /* + * Fill in mode-specific VGA Wonder data. + */ + ATINewHWPtr->b0 = 0x00U; + if (!ATIUsingPlanarModes) + ATINewHWPtr->b0 = 0x20U; + if (ATIChip >= ATI_CHIP_28800_2) + { + if (ATIvideoRam > 512) + ATINewHWPtr->b0 |= 0x08U; + else if (ATIvideoRam > 256) + ATINewHWPtr->b0 |= 0x10U; + } + else if (ATIUsingPlanarModes) + { + if (ATIvideoRam > 256) + ATINewHWPtr->b0 |= 0x08U; + } + else + { + if (ATIvideoRam > 256) + ATINewHWPtr->b0 |= 0x18U; + else + ATINewHWPtr->b0 |= 0x06U; + } + ATINewHWPtr->b1 = ATIGetExtReg(0xB1U) & 0x04U; + ATINewHWPtr->b5 = 0x00U; + ATINewHWPtr->b8 = ATIGetExtReg(0xB8U) & 0xC0U; + ATINewHWPtr->b9 = ATIGetExtReg(0xB9U) & 0x7FU; + ATINewHWPtr->bd = ATIGetExtReg(0xBDU) & 0x02U; + if (ATIChip <= ATI_CHIP_18800) + ATINewHWPtr->b2 = ATIGetExtReg(0xB2U) & 0xC0U; + else + { + ATINewHWPtr->b2 = 0x00U; + ATINewHWPtr->be = (ATIGetExtReg(0xBEU) & 0x30U) | 0x09U; + if (ATIChip >= ATI_CHIP_28800_2) + { + ATINewHWPtr->a6 = (ATIGetExtReg(0xA6U) & 0x38U) | 0x04U; + ATINewHWPtr->a7 = ATIGetExtReg(0xA7U) & 0xBEU; + ATINewHWPtr->ac = ATIGetExtReg(0xACU) & 0x8EU; + } + } + if (mode->Flags & V_INTERLACE) /* Enable interlacing */ + if (ATIChip <= ATI_CHIP_18800) + ATINewHWPtr->b2 |= 0x01U; + else + ATINewHWPtr->be |= 0x02U; + #if 0 /* This is no longer needed but is left in for reference */ + if (mode->Flags & V_DBLSCAN) + ATINewHWPtr->b1 |= 0x08U; /* Enable double scanning */ + #endif + if ((OFLG_ISSET(OPTION_CSYNC, &vga256InfoRec.options)) || + (mode->Flags & (V_CSYNC | V_PCSYNC))) + ATINewHWPtr->bd |= 0x08U; /* Enable composite synch */ + if (mode->Flags & V_NCSYNC) + ATINewHWPtr->bd |= 0x09U; /* Invert csync polarity */ + if (mode->CrtcHSkew > 0) + if (mode->CrtcHSkew <= 3) + ATINewHWPtr->b5 |= 0x01U; + else if (ATIChip >= ATI_CHIP_28800_2) + switch ((mode->CrtcHSkew + 4) >> 3) + { + case 1: /* Use ATI override */ + ATINewHWPtr->std.CRTC[3] &= ~0x60U; + ATINewHWPtr->b0 |= 0x01U; + break; + case 2: /* Use ATI override */ + ATINewHWPtr->std.CRTC[3] &= ~0x60U; + ATINewHWPtr->a6 |= 0x01U; + break; + case 3: + ATINewHWPtr->std.CRTC[3] |= 0x60U; + break; + case 4: + ATINewHWPtr->a7 |= 0x40U; + break; + case 5: + ATINewHWPtr->ac |= 0x10U; + break; + case 6: + ATINewHWPtr->ac |= 0x20U; + break; + default: + break; + } + } + } + + /* + * ATIVGAWonderRestore -- + * + * This function loads the VGA Wonder portion of a video mode. + */ + void + ATIVGAWonderRestore(ATIHWPtr restore) + { + if (ATIChip <= ATI_CHIP_18800) + ATIModifyExtReg(0xB2U, -1, 0x00U, restore->b2); + else + { + ATIModifyExtReg(0xBEU, -1, 0x00U, restore->be); + if (ATIChip >= ATI_CHIP_28800_2) + { + ATIModifyExtReg(0xBFU, -1, 0x00U, restore->bf); + ATIModifyExtReg(0xA3U, -1, 0x00U, restore->a3); + ATIModifyExtReg(0xA6U, -1, 0x00U, restore->a6); + ATIModifyExtReg(0xA7U, -1, 0x00U, restore->a7); + ATIModifyExtReg(0xABU, -1, 0x00U, restore->ab); + ATIModifyExtReg(0xACU, -1, 0x00U, restore->ac); + ATIModifyExtReg(0xADU, -1, 0x00U, restore->ad); + ATIModifyExtReg(0xAEU, -1, 0x00U, restore->ae); + } + } + ATIModifyExtReg(0xB0U, -1, 0x00U, restore->b0); + ATIModifyExtReg(0xB1U, -1, 0x00U, restore->b1); + ATIModifyExtReg(0xB3U, -1, 0x00U, restore->b3); + ATIModifyExtReg(0xB5U, -1, 0x00U, restore->b5); + ATIModifyExtReg(0xB6U, -1, 0x00U, restore->b6); + ATIModifyExtReg(0xB8U, -1, 0x00U, restore->b8); + ATIModifyExtReg(0xB9U, -1, 0x00U, restore->b9); + ATIModifyExtReg(0xBAU, -1, 0x00U, restore->ba); + ATIModifyExtReg(0xBDU, -1, 0x00U, restore->bd); + } *** /dev/null Tue Jun 30 11:49:31 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atiwonder.h Fri Mar 6 16:48:32 1998 *************** *** 0 **** --- 1,38 ---- + /* $TOG: atiwonder.h /main/1 1998/03/06 16:50:10 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/atiwonder.h,v 1.1.2.1 1998/02/01 16:42:10 robin Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + #ifndef ___ATIWONDER_H___ + #define ___ATIWONDER_H___ 1 + + #include "aticrtc.h" + #include "xf86.h" + + extern void ATIVGAWonderSave FunctionPrototype((ATIHWPtr)); + extern void ATIVGAWonderInit FunctionPrototype((DisplayModePtr)); + extern void ATIVGAWonderRestore FunctionPrototype((ATIHWPtr)); + + #endif /* ___ATIWONDER_H___ */ *** /dev/null Tue Jun 30 11:49:32 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/ati.c Fri Mar 6 16:44:40 1998 *************** *** 0 **** --- 1,128 ---- + /* $TOG: ati.c /main/1 1998/03/06 16:46:18 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/ati.c,v 1.1.2.1 1998/02/01 16:41:36 robin Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + /*************************************************************************/ + + /* + * Author: Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * This is the ATI driver for XFree86. + * + * John Donne once said "No man is an island", and I am most certainly not an + * exception. Contributions, intentional or not, to this and previous versions + * of this driver by the following are hereby acknowledged: + * + * Thomas Roell, roell@informatik.tu-muenchen.de + * Per Lindqvist, pgd@compuram.bbt.se + * Doug Evans, dje@cygnus.com + * Rik Faith, faith@cs.unc.edu + * Arthur Tateishi, ruhtra@turing.toronto.edu + * Alain Hebert, aal@broue.rot.qc.ca + * Ton van Rosmalen, ton@stack.urc.tue.nl + * David Chambers, davidc@netcom.com + * William Shubert, wms@ssd.intel.com + * ATI Technologies Incorporated + * Robert Wolff + * David Dawes, dawes@xfree86.org + * Mark Weaver, Mark_Weaver@brown.edu + * Hans Nasten, nasten@everyware.se + * Kevin Martin, martin@cs.unc.edu + * Frederic Rienthaler, root@mojo.synapse.com + * Marc Bolduc, bolduc@cim.mcgill.ca + * Reuben Sumner, rasumner@undergrad.math.uwaterloo.ca + * Benjamin T. Yang, risk@uclink.berkeley.edu + * James Fast Kane, jfk2@engr.uark.edu + * Randall Hopper, rhh@ct.picker.com + * + * ... and, many, many others from around the world. + * + * In addition, this work would not have been possible without the active + * support, both moral and otherwise, of the staff and management of Computing + * and Network Services at the University of Alberta, in Edmonton, Alberta, + * Canada. + * + * The driver is intended to support the ATI VGA Wonder series of adapters and + * its OEM counterpart, the VGA1024 series. It will also work with Mach32's + * and Mach64's but will not use their accelerated features. This includes + * Mach64's based on the 264xT series of integrated controllers. + */ + + /*************************************************************************/ + + #include "ati.h" + #include "atiadjust.h" + #include "aticonsole.h" + #include "aticrtc.h" + #include "atifbinit.h" + #include "atigetmode.h" + #include "atiident.h" + #include "atiprobe.h" + #include "atireset.h" + #include "ativalid.h" + + /* + * This data structure defines the driver itself. The data structure is + * initialized with the functions that make up the driver and some data that + * defines how the driver operates. Some elements of this structure will be + * modified by ATIProbe. + */ + vgaVideoChipRec ATI = + { + ATIProbe, /* Probe */ + ATIIdent, /* Ident */ + ATIEnterLeave, /* EnterLeave */ + ATIInit, /* Init */ + ATIValidMode, /* ValidMode */ + ATISave, /* Save */ + ATIRestore, /* Restore */ + ATIAdjust, /* Adjust */ + ATISaveScreen, /* SaveScreen */ + ATIGetMode, /* GetMode */ + ATIFbInit, /* FbInit */ + ATISetRead, /* SetRead */ + ATISetWrite, /* SetWrite */ + ATISetReadWrite, /* SetReadWrite */ + 0x10000U, /* Mapped memory window size (64k) */ + 0x10000U, /* Video memory bank size (64k) */ + 16, /* Shift factor to get bank number */ + 0xFFFFU, /* Bit mask for address within a bank */ + 0x00000U, 0x10000U, /* Boundaries for reads within a bank */ + 0x00000U, 0x10000U, /* Boundaries for writes within a bank */ + TRUE, /* Read & write banks can be different */ + -1, /* Not used in this driver */ + {{0,}}, /* Options are set by ATIProbe */ + 16, /* Virtual X rounding */ + FALSE, /* No linear frame buffer */ + 0, /* Linear frame buffer base address */ + 0, /* Linear frame buffer size */ + FALSE, /* No support for 16 bits per pixel (yet) */ + FALSE, /* No support for 24 bits per pixel (yet) */ + FALSE, /* No support for 32 bits per pixel (yet) */ + NULL, /* List of builtin modes */ + 1, /* ChipClockMulFactor */ + 1 /* ChipClockDivFactor */ + }; *** /dev/null Tue Jun 30 11:49:33 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/ati.h Fri Mar 6 16:44:44 1998 *************** *** 0 **** --- 1,35 ---- + /* $TOG: ati.h /main/1 1998/03/06 16:46:22 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/ati/ati.h,v 1.1.2.1 1998/02/01 16:41:37 robin Exp $ */ + /* + * Copyright 1997,1998 by Marc Aurele La France (TSI @ UQV), tsi@ualberta.ca + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + #ifndef ___ATI_H___ + #define ___ATI_H___ 1 + + #include "vga.h" + + extern vgaVideoChipRec ATI; + + #endif /* ___ATI_H___ */ *** ./programs/Xserver/hw/xfree86/vga256/drivers/chips/ct_driver.c@@/PUBLIC-LATEST Sun Aug 10 13:04:40 1997 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/chips/ct_driver.c Fri Mar 6 16:48:36 1998 *************** *** 1,4 **** ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/chips/ct_driver.c,v 3.35.2.7 1997/07/19 04:59:32 dawes Exp $ */ /* * Copyright 1993 by Jon Block <block@frc.com> * Modified by Mike Hollick <hollick@graphics.cis.upenn.edu> --- 1,4 ---- ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/chips/ct_driver.c,v 3.35.2.8 1998/01/31 14:23:29 hohndel Exp $ */ /* * Copyright 1993 by Jon Block <block@frc.com> * Modified by Mike Hollick <hollick@graphics.cis.upenn.edu> *************** *** 35,41 **** * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. */ ! /* $TOG: ct_driver.c /main/20 1997/08/10 13:03:15 kaleb $ */ /* * This driver is still worked on, however we believe it to be fairly --- 35,41 ---- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. */ ! /* $TOG: ct_driver.c /main/21 1998/03/06 16:50:14 kaleb $ */ /* * This driver is still worked on, however we believe it to be fairly *************** *** 108,114 **** /* Chip type */ Bool ctisHiQV32 = FALSE; /*New architecture used in 65550 and 65554 */ Bool ctisWINGINE = FALSE; /* WINGINE support */ - Bool ctForceVClk1 = FALSE; /* Use VClk1 as prog clock on HiQV chips */ /* syncronous reset */ Bool ctSyncResetIgn = FALSE; --- 108,113 ---- *************** *** 166,173 **** --- 165,188 ---- unsigned char fr03; int Clock; } ctClockReg, *ctClockPtr; + + typedef struct { + unsigned int Max; + unsigned int ProbedClk; + unsigned int Clk; + unsigned char M; + unsigned char N; + unsigned char P; + unsigned char PSN; + unsigned char xrCC; + unsigned char xrCD; + unsigned char xrCE; + } ctMemClockReg, *ctMemClockPtr; + Bool ctForceVClk1 = FALSE; /* Use VClk1 as prog clock on HiQV chips */ int ctCurrentClock; + ctMemClockReg ctMemClkReg; + ctMemClockPtr ctMemClk = &ctMemClkReg; static unsigned char ctClockType; static unsigned char ctConsole_clk[3]; *************** *** 182,187 **** --- 197,203 ---- #define GET_STYLE 0xF0 #define LCD_TEXT_CLK_FREQ 25000 /* lcd textclock if TYPE_PROGRAMMABLE */ #define CRT_TEXT_CLK_FREQ 28000 /* crt textclock if TYPE_PROGRAMMABLE */ + #define Fref 14318180 /* The refrence clock in Hertz */ static void ctClockSave(); static void ctClockLoad(); *************** *** 772,779 **** #endif } - #define Fref 14318180 - /* * This is Ken Raeburn's <raeburn@raeburn.org> clock * calculation code just modified a little bit to fit in here. --- 788,793 ---- *************** *** 1186,1192 **** } if (CHIPSchipset != 99) { outb(0x3D6, 0x04); ! temp = inb(0x03D7); ErrorF("%s %s: CHIPS: chip revision: %i\n", XCONFIG_PROBED, vga256InfoRec.name, temp & 0xFF); } --- 1200,1206 ---- } if (CHIPSchipset != 99) { outb(0x3D6, 0x04); ! temp = inb(0x3D7); ErrorF("%s %s: CHIPS: chip revision: %i\n", XCONFIG_PROBED, vga256InfoRec.name, temp & 0xFF); } *************** *** 1225,1231 **** ctLinearSupport = FALSE; ctHDepth = FALSE; /* Much of the acceleration code wasn't written in a way that ! * is usuable without linear addressing. This is a fault of the * code, the chips actually do support acceleration without * linear addressing */ ctAccelSupport = FALSE; --- 1239,1245 ---- ctLinearSupport = FALSE; ctHDepth = FALSE; /* Much of the acceleration code wasn't written in a way that ! * is usable without linear addressing. This is a fault of the * code, the chips actually do support acceleration without * linear addressing */ ctAccelSupport = FALSE; *************** *** 1546,1560 **** XCONFIG_GIVEN, vga256InfoRec.name); } /* maximal clock */ ! outb(0x3D0, 0x0A); ! if (inb(0x3D1) & 2) { /*5V Vcc */ ! vga256InfoRec.maxClock = 110000; ! } else { /*3.3V Vcc */ vga256InfoRec.maxClock = 80000; ! } /* Set the flags for Colour transparency. This is dependent * on the revision on the chip. Until exactly which chips --- 1560,1679 ---- XCONFIG_GIVEN, vga256InfoRec.name); } + /* Set the maximum memory clock. */ + switch (CHIPSchipset) { + case CT_550: + outb(0x3D6, 0x04); + if ((inb(0x3D7) & 0xF) < 6) + ctMemClk->Max = 38000; /* Revision A chips */ + else + ctMemClk->Max = 50000; /* Revision B chips */ + break; + case CT_554: + case CT_555: + case CT_8554: + ctMemClk->Max = 55000; + break; + } + + /* Probe the memory clock currently in use */ + outb(0x3D6,0xCC); + ctMemClk->xrCC = inb(0x3D7); + ctMemClk->M = (ctMemClk->xrCC & 0x7F) + 2; + outb(0x3D6,0xCD); + ctMemClk->xrCD = inb(0x3D7); + ctMemClk->N = (ctMemClk->xrCD & 0x7F) + 2; + outb(0x3D6,0xCE); + ctMemClk->xrCE = inb(0x3D7); + ctMemClk->PSN = (ctMemClk->xrCE & 0x1) ? 1 : 4; + ctMemClk->P = ((ctMemClk->xrCE & 0x70) >> 4); + /* Be careful with the calculation of ProbeClk as it can overflow */ + ctMemClk->ProbedClk = 4 * Fref / ctMemClk->N; + ctMemClk->ProbedClk = ctMemClk->ProbedClk * ctMemClk->M / + (ctMemClk->PSN * (1 << ctMemClk->P)); + ctMemClk->ProbedClk = ctMemClk->ProbedClk / 1000; + ctMemClk->Clk = ctMemClk->ProbedClk; + + if (OFLG_ISSET(OPTION_FAST_DRAM, &vga256InfoRec.options)) { + ctMemClk->M = 0x45; + ctMemClk->N = 0x1A; + ctMemClk->PSN = 1; + ctMemClk->P = 2; + ctMemClk->xrCC = 0x43; + ctMemClk->xrCD = 0x18; + ctMemClk->xrCE = 0xA1; + ctMemClk->Clk = 37998; + ErrorF("%s %s: CHIPS: using memory clock of %d KHz\n", + XCONFIG_GIVEN, vga256InfoRec.name, ctMemClk->Clk); + } else if (vga256InfoRec.MemClk > 0) { + if (vga256InfoRec.MemClk <= ctMemClk->Max) { + ErrorF("%s %s: CHIPS: using memory clock of %d KHz\n", + XCONFIG_GIVEN, vga256InfoRec.name, vga256InfoRec.MemClk); + + /* Only alter the memory clock if the desired memory clock differs + * by 50kHz from the one currently being used. + */ + if (abs(vga256InfoRec.MemClk - ctMemClk->ProbedClk) > 50) { + unsigned char vclk[3]; + + ctMemClk->Clk = vga256InfoRec.MemClk; + ctCalcClock(ctMemClk->Clk, vclk); + ctMemClk->M = vclk[1] + 2; + ctMemClk->N = vclk[2] + 2; + ctMemClk->P = (vclk[0] & 0x70) >> 4; + ctMemClk->PSN = (vclk[0] & 0x1) ? 1 : 4; + ctMemClk->xrCC = vclk[1]; + ctMemClk->xrCD = vclk[2]; + ctMemClk->xrCE = 0x80 || vclk[0]; + } + } else + ErrorF("%s %s: CHIPS: memory clock of %d KHz exceeds limit of %d KHz\n", + XCONFIG_GIVEN, vga256InfoRec.name, vga256InfoRec.MemClk, + ctMemClk->Max); + } else + ErrorF("%s %s: CHIPS: probed memory clock of %d KHz\n", + XCONFIG_PROBED, vga256InfoRec.name, ctMemClk->ProbedClk); + /* maximal clock */ ! switch (CHIPSchipset) { ! case CT_8554: ! case CT_555: ! vga256InfoRec.maxClock = 110000; ! break; ! case CT_554: ! vga256InfoRec.maxClock = 95000; ! case CT_550: ! outb(0x3D6, 0x04); ! if ((inb(0x3D7) & 0xF) < 6) { ! outb(0x3D0, 0x0A); ! if (inb(0x3D1) & 2) { /*5V Vcc */ ! vga256InfoRec.maxClock = 100000; ! } else { /*3.3V Vcc */ vga256InfoRec.maxClock = 80000; ! } ! } else ! vga256InfoRec.maxClock = 95000; /* Revision B */ ! break; ! } ! ! /* Check if maxClock is limited by the MemClk. Only 70% to allow for */ ! /* RAS/CAS. Extra byte per memory clock needed if framebuffer used */ ! if (ctFrameBufferSize) ! vga256InfoRec.maxClock = min(vga256InfoRec.maxClock, ! ctMemClk->Clk * 4 * 0.7 / (vgaBytesPerPixel + 1)); ! else ! vga256InfoRec.maxClock = min(vga256InfoRec.maxClock, ! ctMemClk->Clk * 4 * 0.7 / vgaBytesPerPixel); ! ! if (vga256InfoRec.dacSpeeds[0] > 0) { ! /* Maximum clock is overridden by a user supplied value */ ! ErrorF("%s %s: CHIPS: user max dot-clock of %d kHz overrides %d kHz limit\n", ! XCONFIG_GIVEN, vga256InfoRec.name, vga256InfoRec.dacSpeeds[0], ! vga256InfoRec.maxClock); ! vga256InfoRec.maxClock = vga256InfoRec.dacSpeeds[0]; ! } /* Set the flags for Colour transparency. This is dependent * on the revision on the chip. Until exactly which chips *************** *** 1817,1822 **** --- 1936,1949 ---- vga256InfoRec.maxClock = 85000; break; } + + if (vga256InfoRec.dacSpeeds[0] > 0) { + /* Maximum clock is overridden by a user supplied value */ + ErrorF("%s %s: CHIPS: user max dot-clock of %d kHz overrides %d kHz limit\n", + XCONFIG_GIVEN, vga256InfoRec.name, vga256InfoRec.dacSpeeds[0], + vga256InfoRec.maxClock); + vga256InfoRec.maxClock = vga256InfoRec.dacSpeeds[0]; + } vga256InfoRec.chipset = CHIPSIdent(CHIPSchipset); vga256InfoRec.bankedMono = FALSE; *************** *** 2274,2279 **** --- 2401,2414 ---- vga256InfoRec.maxClock = 56000; } } + + if (vga256InfoRec.dacSpeeds[0] > 0) { + /* Maximum clock is overridden by a user supplied value */ + ErrorF("%s %s: CHIPS: user max dot-clock of %d kHz overrides %d kHz limit\n", + XCONFIG_GIVEN, vga256InfoRec.name, vga256InfoRec.dacSpeeds[0], + vga256InfoRec.maxClock); + vga256InfoRec.maxClock = vga256InfoRec.dacSpeeds[0]; + } vga256InfoRec.chipset = CHIPSIdent(CHIPSchipset); vga256InfoRec.bankedMono = FALSE; *************** *** 3564,3576 **** new->Port_3D6[0x81] |= 0x2; new->Port_3D6[0x80] |= 0x10; /* Enable cursor output on P0 and P1 */ ! if (OFLG_ISSET(OPTION_FAST_DRAM, &vga256InfoRec.options)) { /* set mem clk */ ! /* Graphics Modes seem to need a Higher MClk, than at Console ! * Force a higher Mclk for now */ ! new->Port_3D6[0xCC] = 0x43; ! new->Port_3D6[0xCD] = 0x18; ! new->Port_3D6[0xCE] = 0xA1; } /* linear specific */ --- 3699,3709 ---- new->Port_3D6[0x81] |= 0x2; new->Port_3D6[0x80] |= 0x10; /* Enable cursor output on P0 and P1 */ ! if (abs(vga256InfoRec.MemClk - ctMemClk->ProbedClk) > 50) { /* set mem clk */ ! new->Port_3D6[0xCC] = ctMemClk->xrCC; ! new->Port_3D6[0xCD] = ctMemClk->xrCD; ! new->Port_3D6[0xCE] = ctMemClk->xrCE; } /* linear specific */ *************** *** 3705,3720 **** if (IS_STN(ctPanelType)) { new->Port_3D0[0x11] &= ~0x03; /* FRC clear */ new->Port_3D0[0x11] &= ~0x8C; /* Dither clear */ if (ctTMED) { ! new->Port_3D0[0x73] |= 0x80; /* Enable TMED */ ! new->Port_3D0[0x73] &= 0xC8; /* TMED 33 Shades of RB and 65 G*/ ! if (vgaBitsPerPixel == 8) ! new->Port_3D0[0x73] |= 0x10;/* TMED 65 Shades of RGB */ ! else if (vgaBitsPerPixel == 24) ! new->Port_3D0[0x73] |= 0x30;/* TMED 256 Shades of RGB */ ! } else { ! new->Port_3D0[0x11] |= 0x01; /* 16 frame FRC */ ! new->Port_3D0[0x11] |= 0x84; /* Dither */ } if (ctPanelType == DD) /* Shift Clock Mask. Use to get */ new->Port_3D0[0x12] |= 0x4; /* rid of line in DSTN screens */ --- 3838,3849 ---- if (IS_STN(ctPanelType)) { new->Port_3D0[0x11] &= ~0x03; /* FRC clear */ new->Port_3D0[0x11] &= ~0x8C; /* Dither clear */ + new->Port_3D0[0x11] |= 0x01; /* 16 frame FRC */ + new->Port_3D0[0x11] |= 0x84; /* Dither */ if (ctTMED) { ! new->Port_3D0[0x73] &= 0x4F; /* Clear TMED */ ! new->Port_3D0[0x73] |= 0x80; /* Enable TMED */ ! new->Port_3D0[0x73] |= 0x30; /* TMED 256 Shades of RGB */ } if (ctPanelType == DD) /* Shift Clock Mask. Use to get */ new->Port_3D0[0x12] |= 0x4; /* rid of line in DSTN screens */ *************** *** 4015,4021 **** XCONFIG_PROBED, vga256InfoRec.name); break; - #if 0 case 24: /* There are no corresponding structures to vga256LowlevFuncs * for 16/24bpp. Hence we have to hook to the cfb functions in --- 4144,4149 ---- *************** *** 4052,4058 **** ErrorF("%s %s: CHIPS: Too little space for accelerated tile.\n", XCONFIG_PROBED, vga256InfoRec.name); break; - #endif } --- 4180,4185 ---- *** ./programs/Xserver/hw/xfree86/vga256/drivers/cirrus/cir_blitLG.c@@/PUBLIC-LATEST Sat Jul 19 10:36:09 1997 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/cirrus/cir_blitLG.c Fri Mar 6 16:48:46 1998 *************** *** 1,8 **** ! /* $TOG: cir_blitLG.c /main/6 1997/07/19 10:36:11 kaleb $ */ /* * cir_blitLG.c * ! * Copyright 1996 by Corin Anderson, Bellevue, Washington * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that --- 1,8 ---- ! /* $TOG: cir_blitLG.c /main/7 1998/03/06 16:50:24 kaleb $ */ /* * cir_blitLG.c * ! * Copyright 1996 by Corin Anderson, Tukwila, Washington * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that *************** *** 22,32 **** * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. * ! * Author: Corin Anderson, <corina@bdc.cirrus.com> * */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/cirrus/cir_blitLG.c,v 3.3 1996/12/27 07:05:21 dawes Exp $ */ #include "vga256.h" #include "cfbrrop.h" --- 22,32 ---- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. * ! * Author: Corin Anderson, <corina@the4cs.com> * */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/cirrus/cir_blitLG.c,v 3.3.2.1 1998/02/15 16:09:33 hohndel Exp $ */ #include "vga256.h" #include "cfbrrop.h" *** ./programs/Xserver/hw/xfree86/vga256/drivers/cirrus/cir_blitLG.h@@/PUBLIC-LATEST Sat Jul 19 10:36:18 1997 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/cirrus/cir_blitLG.h Fri Mar 6 16:48:51 1998 *************** *** 1,10 **** #ifndef __CIR_BLITLG_H #define __CIR_BLITLG_H ! /* $TOG: cir_blitLG.h /main/4 1997/07/19 10:36:20 kaleb $ */ /* * ! * Copyright 1996 by Corin Anderson, Bellevue, Washington, USA * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that --- 1,10 ---- #ifndef __CIR_BLITLG_H #define __CIR_BLITLG_H ! /* $TOG: cir_blitLG.h /main/5 1998/03/06 16:50:28 kaleb $ */ /* * ! * Copyright 1996 by Corin Anderson, Tukwila, Washington, USA * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that *************** *** 24,35 **** * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. * ! * Author: Corin Anderson, <corina@bdc.cirrus.com> * * cir_blitLG.h */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/cirrus/cir_blitLG.h,v 3.7 1997/01/19 12:50:55 dawes Exp $ */ /* This header file defines the necessary structures, contstants, and --- 24,35 ---- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. * ! * Author: Corin Anderson, <corina@the4cs.com> * * cir_blitLG.h */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/cirrus/cir_blitLG.h,v 3.7.2.1 1998/02/15 16:09:33 hohndel Exp $ */ /* This header file defines the necessary structures, contstants, and *** ./programs/Xserver/hw/xfree86/vga256/drivers/cirrus/cir_cursor.c@@/PUBLIC-LATEST Sat Jul 19 10:36:59 1997 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/cirrus/cir_cursor.c Fri Mar 6 16:48:55 1998 *************** *** 1,4 **** ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/cirrus/cir_cursor.c,v 3.20.2.4 1997/05/31 13:34:43 dawes Exp $ */ /* * * Copyright 1993-94 by Simon P. Cooper, New Brunswick, New Jersey, USA. --- 1,4 ---- ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/cirrus/cir_cursor.c,v 3.20.2.5 1998/02/21 06:07:07 robin Exp $ */ /* * * Copyright 1993-94 by Simon P. Cooper, New Brunswick, New Jersey, USA. *************** *** 23,29 **** * * Author: Simon P. Cooper, <scooper@vizlab.rutgers.edu> */ ! /* $TOG: cir_cursor.c /main/15 1997/07/19 10:37:01 kaleb $ */ /* #define CIRRUS_DEBUG_CURSOR --- 23,29 ---- * * Author: Simon P. Cooper, <scooper@vizlab.rutgers.edu> */ ! /* $TOG: cir_cursor.c /main/16 1998/03/06 16:50:33 kaleb $ */ /* #define CIRRUS_DEBUG_CURSOR *************** *** 35,40 **** --- 35,43 ---- #include "Xproto.h" #include "misc.h" #include "input.h" + #ifdef PC98_SVGA + #include "compiler.h" + #endif #include "cursorstr.h" #include "regionstr.h" #include "scrnintstr.h" *** ./programs/Xserver/hw/xfree86/vga256/drivers/cirrus/cir_driver.c@@/PUBLIC-LATEST Tue Nov 11 15:46:27 1997 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/cirrus/cir_driver.c Fri Mar 6 16:49:00 1998 *************** *** 1,4 **** ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/cirrus/cir_driver.c,v 3.80.2.11 1997/08/02 13:48:18 dawes Exp $ */ /* * cir_driver.c,v 1.10 1994/09/14 13:59:50 scooper Exp * --- 1,4 ---- ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/cirrus/cir_driver.c,v 3.80.2.14 1998/02/21 06:07:08 robin Exp $ */ /* * cir_driver.c,v 1.10 1994/09/14 13:59:50 scooper Exp * *************** *** 28,37 **** * Modifications: Simon P. Cooper, <scooper@vizlab.rutgers.edu> * Modifications: Wolfgang Jung, <wong@cs.tu-berlin.de> * Modifications: Harm Hanemaayer, <hhanemaa@cs.ruu.nl> ! * Modifications: Corin Anderson, <corina@bdc.cirrus.com> * */ ! /* $TOG: cir_driver.c /main/31 1997/11/11 15:46:29 msr $ */ /* * Modifications to this file for the Cirrus 62x5 chips and color LCD --- 28,37 ---- * Modifications: Simon P. Cooper, <scooper@vizlab.rutgers.edu> * Modifications: Wolfgang Jung, <wong@cs.tu-berlin.de> * Modifications: Harm Hanemaayer, <hhanemaa@cs.ruu.nl> ! * Modifications: Corin Anderson, <corina@the4cs.com> * */ ! /* $TOG: cir_driver.c /main/32 1998/03/06 16:50:38 kaleb $ */ /* * Modifications to this file for the Cirrus 62x5 chips and color LCD *************** *** 155,160 **** --- 155,161 ---- Bool cirrusFavourBLT = FALSE; Bool cirrusAvoidImageBLT = FALSE; Bool cirrus128KDevices = FALSE; + Bool cirrusUsingHWCursor = FALSE; int cirrusDRAMBandwidth; int cirrusDRAMBandwidthLimit; int cirrusReprogrammedMCLK = 0; *************** *** 209,215 **** (x) == CLGD5436) || \ (x) == CLGD5446 || (x) == CLGD5480 || \ ((x) == CLGD5462 || (x) == CLGD5464) || \ ! (x) == CLGD5465) #define HasLargeHWCursor(x) ((x) == CLGD5462 || (x) == CLGD5464 || \ (x) == CLGD5465) --- 210,216 ---- (x) == CLGD5436) || \ (x) == CLGD5446 || (x) == CLGD5480 || \ ((x) == CLGD5462 || (x) == CLGD5464) || \ ! (x) == CLGD5465 || (x) == CLGD7555) #define HasLargeHWCursor(x) ((x) == CLGD5462 || (x) == CLGD5464 || \ (x) == CLGD5465) *************** *** 1091,1133 **** default: /* The Laguna family (546x) doesn't respond to CR27 writes like all of its cousins. So instead, query the PCI bus to ! see if there's a Laguna chip there. */ ! if (vgaPCIInfo && vgaPCIInfo->Vendor == PCI_VENDOR_CIRRUS) { ! switch (vgaPCIInfo->ChipType) { ! case PCI_CHIP_GD5462: ! cirrusChip = CLGD5462; ! break; ! case PCI_CHIP_GD5464: ! cirrusChip = CLGD5464; ! break; ! case PCI_CHIP_GD5465: ! cirrusChip = CLGD5465; ! break; ! case PCI_CHIP_GD7548: ! cirrusChip = CLGD7548; ! break; ! } ! if (HAVE546X() && vgaBitsPerPixel < 8) { ! /* The mono and 16 color support isn't working ! yet for the Laguna driver. As a work around, ! punt these modes off to the generic driver. ! We wouldn't do anything fancier, anyway. And ! besides, if you have a Laguna card, what are ! you doing in mono or 16 color mode?!? ! --corey 5/20/97 */ ! return FALSE; ! } ! /* If we've found the chip on the PCI bus, jump out of the ! chip-switch statement */ ! if (cirrusChip > 0) ! break; } case CLGD5434_OLD_ID: ErrorF("Unknown Cirrus chipset: type 0x%02x, rev %d\n", id, rev); --- 1092,1151 ---- default: /* The Laguna family (546x) doesn't respond to CR27 writes like all of its cousins. So instead, query the PCI bus to ! see if there's a Laguna chip there. Note that there may ! be more than one video device hanging out on the PCI bus. ! For instance, there might have been a PCI video chip on the ! motherboard *and* the Laguna card. */ ! if (vgaPCIInfo && vgaPCIInfo->AllCards) { ! int card = 0; ! pciConfigPtr pcr; ! while (NULL != (pcr = vgaPCIInfo->AllCards[card++])) { ! if (pcr->_vendor == PCI_VENDOR_CIRRUS) { ! /* Yep, it's a Cirrus chip. What one? */ ! switch (pcr->_device) { ! case PCI_CHIP_GD5462: ! cirrusChip = CLGD5462; ! break; ! case PCI_CHIP_GD5464: ! cirrusChip = CLGD5464; ! break; ! case PCI_CHIP_GD5465: ! cirrusChip = CLGD5465; ! break; ! ! case PCI_CHIP_GD7548: ! cirrusChip = CLGD7548; ! break; ! ! default: ! ErrorF("%s %s: Unknown Cirrus chip: PCI ID 0x%02X\n", ! XCONFIG_PROBED, vga256InfoRec.name, pcr->_device); ! break; ! } ! if (HAVE546X() && vgaBitsPerPixel < 8) { ! /* The mono and 16 color support isn't working ! yet for the Laguna driver. As a work around, ! punt these modes off to the generic driver. ! We wouldn't do anything fancier, anyway. And ! besides, if you have a Laguna card, what are ! you doing in mono or 16 color mode?!? ! --corey 5/20/97 */ ! return FALSE; ! } ! /* If we've found a recognizable Cirrus chip on the PCI ! bus, jump out of the PCI scanning loop. */ ! if (cirrusChip > 0) ! break; ! } ! } } + break; case CLGD5434_OLD_ID: ErrorF("Unknown Cirrus chipset: type 0x%02x, rev %d\n", id, rev); *************** *** 1187,1197 **** --- 1205,1219 ---- * BitBLT engine on a local bus. The 754x use a different register. */ if (HAVE75XX()) { + #ifdef PC98_SVGA + cirrusBusType = CIRRUS_BUS_PCI; + #else outb(0x3c4, 0x22); if (inb(0x3c5) & 0x1) cirrusBusType = CIRRUS_BUS_PCI; else cirrusBusType = CIRRUS_BUS_VLB; + #endif } else { outb(0x3c4, 0x17); *************** *** 1251,1256 **** --- 1273,1279 ---- XCONFIG_PROBED, vga256InfoRec.name, vga256InfoRec.chipset); break; case 0x40: + lcd_is_on = TRUE; ErrorF("%s %s: %s: CRT display only\n", XCONFIG_PROBED, vga256InfoRec.name, vga256InfoRec.chipset); break; *************** *** 1781,1790 **** OFLG_SET(OPTION_16CLKS, &CIRRUS.ChipOptionFlags); ErrorF("CIRRUS: Warning: Out of spec clocks can be enabled\n"); #endif ! /* option noaccel doesn't presently work with the Laguna chips. ! Hey -- I never needed it! --corey 8/1/97 */ ! if (!HAVE546X()) ! OFLG_SET(OPTION_NOACCEL, &CIRRUS.ChipOptionFlags); OFLG_SET(OPTION_PROBE_CLKS, &CIRRUS.ChipOptionFlags); OFLG_SET(OPTION_LINEAR, &CIRRUS.ChipOptionFlags); OFLG_SET(OPTION_NOLINEAR_MODE, &CIRRUS.ChipOptionFlags); --- 1804,1812 ---- OFLG_SET(OPTION_16CLKS, &CIRRUS.ChipOptionFlags); ErrorF("CIRRUS: Warning: Out of spec clocks can be enabled\n"); #endif ! if (HAVE546X()) ! OFLG_SET(OPTION_PCI_RETRY, &CIRRUS.ChipOptionFlags); ! OFLG_SET(OPTION_NOACCEL, &CIRRUS.ChipOptionFlags); OFLG_SET(OPTION_PROBE_CLKS, &CIRRUS.ChipOptionFlags); OFLG_SET(OPTION_LINEAR, &CIRRUS.ChipOptionFlags); OFLG_SET(OPTION_NOLINEAR_MODE, &CIRRUS.ChipOptionFlags); *************** *** 1835,1841 **** * cursor, the virtual desktop won't work. */ ! if (Has_HWCursor(cirrusChip) && !HAVE546X()) { OFLG_SET(OPTION_SW_CURSOR, &CIRRUS.ChipOptionFlags); } --- 1857,1863 ---- * cursor, the virtual desktop won't work. */ ! if (Has_HWCursor(cirrusChip)) { OFLG_SET(OPTION_SW_CURSOR, &CIRRUS.ChipOptionFlags); } *************** *** 2086,2150 **** CIRRUS.ChipLinearBase = 0x04000000; /* 64MB */ } if (cirrusBusType == CIRRUS_BUS_PCI) { cirrusUseLinear = FALSE; - if (vgaPCIInfo && vgaPCIInfo->Vendor == PCI_VENDOR_CIRRUS) { - /* The later Cirrus PCI chips don't set the lower - order bit of the PCI base registers as expected by - XFree86. This was done (by Cirrus) by design. It's - okay, though, because we know how the registers - should be decoded in these cases. */ - if ((vgaPCIInfo->ChipType == PCI_CHIP_GD5462) || - (vgaPCIInfo->ChipType == PCI_CHIP_GD5464) || - (vgaPCIInfo->ChipType == PCI_CHIP_GD5464BD) || - (vgaPCIInfo->ChipType == PCI_CHIP_GD5465) || - (vgaPCIInfo->ChipType == PCI_CHIP_GD7548)) { ! if (vgaPCIInfo->ChipType == PCI_CHIP_GD5465) { ! /* Swapped in the '65, by design. */ ! vgaPCIInfo->IOBase = vgaPCIInfo->ThisCard->_base1; ! vgaPCIInfo->MemBase = vgaPCIInfo->ThisCard->_base0; } else { ! vgaPCIInfo->IOBase = vgaPCIInfo->ThisCard->_base0; ! vgaPCIInfo->MemBase = vgaPCIInfo->ThisCard->_base1; } ! ErrorF("%s %s: PCI: ", XCONFIG_PROBED, ! vga256InfoRec.name); ! if (vgaPCIInfo->MemBase) ! ErrorF("Memory @ 0x%08x", vgaPCIInfo->MemBase); ! if (vgaPCIInfo->IOBase) ! ErrorF(", I/O @ 0x%08x", vgaPCIInfo->IOBase); ! ErrorF("\n"); ! } ! ! /* ! * Known devices: ! * 0x00A0 5430, 5440 ! * 0x00A8 5434 ! * 0x00AC 5436 ! * 0x00B8 5446 ! * 0x00BC 5480 ! * 0x00D0 5462 ! * 0x00D4 5464 ! * 0x00D5 5464BD ! * 0x00D6 5465 ! */ ! if (vgaPCIInfo->MemBase != 0) { ! CIRRUS.ChipLinearBase = ! vgaPCIInfo->MemBase & 0xFF000000; ! cirrusUseLinear = TRUE; ! } ! else ! ErrorF("%s %s: %s: Can't find valid PCI " ! "Base Address\n", XCONFIG_PROBED, ! vga256InfoRec.name, vga256InfoRec.chipset); ! } else ! ErrorF("%s %s: %s: Can't find PCI device in " ! "configuration space\n", XCONFIG_PROBED, ! vga256InfoRec.name, vga256InfoRec.chipset); ! if (!cirrusUseLinear) ! goto nolinear; } } else { --- 2108,2199 ---- CIRRUS.ChipLinearBase = 0x04000000; /* 64MB */ } if (cirrusBusType == CIRRUS_BUS_PCI) { + /* Be careful to not make any silly assumptions. Like + assuming that we're the only video card on the PCI bus. + It's quite possible that there's another video device on + the PCI bus, and that the scanpci code found it. Thus, + we must search through the entire list of PCI video + cards, setting up only the one that we care about. */ + + int card = 0; + pciConfigPtr pcr = NULL; cirrusUseLinear = FALSE; ! while (NULL != (pcr = vgaPCIInfo->AllCards[card++])) { ! if (pcr->_vendor == PCI_VENDOR_CIRRUS) { ! /* Found a Cirrus video card. ! !!! We should really do something to be sure ! that the card we just found is really the same ! card as the one we probed earlier. */ ! ! /* The later Cirrus PCI chips don't set the lower ! order bit of the PCI base registers as expected by ! XFree86. This was done (by Cirrus) by design. It's ! okay, though, because we know how the registers ! should be decoded in these cases. */ ! if ((vgaPCIInfo->ChipType == PCI_CHIP_GD5462) || ! (vgaPCIInfo->ChipType == PCI_CHIP_GD5464) || ! (vgaPCIInfo->ChipType == PCI_CHIP_GD5464BD) || ! (vgaPCIInfo->ChipType == PCI_CHIP_GD5465) || ! (vgaPCIInfo->ChipType == PCI_CHIP_GD7548)) { ! ! if ((vgaPCIInfo->ChipType == PCI_CHIP_GD5465) || ! (vgaPCIInfo->ChipType == PCI_CHIP_GD7548)) { ! /* Swapped in the '65, by design. */ ! vgaPCIInfo->IOBase = vgaPCIInfo->ThisCard->_base1; ! vgaPCIInfo->MemBase = vgaPCIInfo->ThisCard->_base0; ! } else { ! vgaPCIInfo->IOBase = vgaPCIInfo->ThisCard->_base0; ! vgaPCIInfo->MemBase = vgaPCIInfo->ThisCard->_base1; ! } ! ! ErrorF("%s %s: PCI: ", ! XCONFIG_PROBED, vga256InfoRec.name); ! if (vgaPCIInfo->MemBase) ! ErrorF("Memory @ 0x%08x", vgaPCIInfo->MemBase); ! if (vgaPCIInfo->IOBase) { ! if (vgaPCIInfo->MemBase) ! ErrorF(", "); ! ErrorF("I/O @ 0x%08x", vgaPCIInfo->IOBase); ! } ! ErrorF("\n"); ! } ! ! /* ! * Known devices: ! * 0x00A0 5430, 5440 ! * 0x00A8 5434 ! * 0x00AC 5436 ! * 0x00B8 5446 ! * 0x00BC 5480 ! * 0x00D0 5462 ! * 0x00D4 5464 ! * 0x00D5 5464BD ! * 0x00D6 5465 ! */ ! if (vgaPCIInfo->MemBase != 0) { ! CIRRUS.ChipLinearBase = ! vgaPCIInfo->MemBase & 0xFF000000; ! cirrusUseLinear = TRUE; } else { ! ErrorF("%s %s: %s: Can't find valid PCI " ! "Base Address\n", XCONFIG_PROBED, ! vga256InfoRec.name, vga256InfoRec.chipset); } ! /* We've found the chip that we had detected ! in cirrusProbe(). Exit the PCI card scanning ! loop. */ ! break; } ! } ! if (pcr == NULL) { ! ErrorF("%s %s: %s: Can't find PCI device in " ! "configuration space\n", XCONFIG_PROBED, ! vga256InfoRec.name, vga256InfoRec.chipset); ! } ! if (!cirrusUseLinear) ! goto nolinear; } } else { *************** *** 2190,2196 **** if (Has_HWCursor(cirrusChip) && !OFLG_ISSET(OPTION_SW_CURSOR, &vga256InfoRec.options) && (vgaBitsPerPixel != 24 || cirrusChip == CLGD5436 || ! cirrusChip == CLGD5446 || cirrusChip == CLGD5480)) { #if 1 if (HasLargeHWCursor(cirrusChip)) --- 2239,2246 ---- if (Has_HWCursor(cirrusChip) && !OFLG_ISSET(OPTION_SW_CURSOR, &vga256InfoRec.options) && (vgaBitsPerPixel != 24 || cirrusChip == CLGD5436 || ! cirrusChip == CLGD5446 || cirrusChip == CLGD5480 || ! HAVE546X())) { #if 1 if (HasLargeHWCursor(cirrusChip)) *************** *** 2215,2220 **** --- 2265,2272 ---- vgaHWCursor.Warp = cirrusWarpCursor; vgaHWCursor.QueryBestSize = cirrusQueryBestSize; + cirrusUsingHWCursor = FALSE; + if (xf86Verbose) { ErrorF( "%s %s: %s: Using hardware cursor\n", *************** *** 2230,2237 **** } if ((!OFLG_ISSET(OPTION_NOACCEL, &vga256InfoRec.options) ! && !(cirrusChip == CLGD5420 && cirrusChipRevision == 1)) || ! HAVE546X()) { if (xf86Verbose) { ErrorF ("%s %s: %s: Using accelerator functions\n", --- 2282,2288 ---- } if ((!OFLG_ISSET(OPTION_NOACCEL, &vga256InfoRec.options) ! && !(cirrusChip == CLGD5420 && cirrusChipRevision == 1))) { if (xf86Verbose) { ErrorF ("%s %s: %s: Using accelerator functions\n", *************** *** 2337,2343 **** || HAVE546X()) { cirrusUseMMIO = TRUE; ! if (cirrusBusType == CIRRUS_BUS_PCI && HAVE546X()) { /* The MMIO address lives in a PCI base address register */ /* !!! what's scr_index? */ --- 2388,2394 ---- || HAVE546X()) { cirrusUseMMIO = TRUE; ! if (cirrusBusType == CIRRUS_BUS_PCI && (HAVE546X() || HAVE75XX())) { /* The MMIO address lives in a PCI base address register */ /* !!! what's scr_index? */ *************** *** 2563,2572 **** if (!cirrusMMIOBase) cirrusMMIOBase = xf86MapVidMem(0, EXTENDED_REGION, (pointer)vgaPCIInfo->IOBase, 0x4000); ! ErrorF("%s %s: %s: Using memory-mapped I/O at address 0x%08X\n" ! "\tmapped to 0x%08X\n", ! XCONFIG_GIVEN, vga256InfoRec.name, vga256InfoRec.chipset, ! (unsigned char *)vgaPCIInfo->IOBase, cirrusMMIOBase); } else { /* We shouldn't get here. This case is where we (1) have a 546X, but (2) don't have a PCI card. We won't handle --- 2614,2679 ---- if (!cirrusMMIOBase) cirrusMMIOBase = xf86MapVidMem(0, EXTENDED_REGION, (pointer)vgaPCIInfo->IOBase, 0x4000); ! ! ErrorF("%s %s: %s: Using memory-mapped I/O at address 0x%08X\n", ! XCONFIG_PROBED, vga256InfoRec.name, vga256InfoRec.chipset, ! (unsigned char *)vgaPCIInfo->IOBase); ! ! ! /* Should the Rambus memory clock be adjusted? */ ! /* By default, don't do anything to the BCLK register. However, ! if the {slow,med,fast}_dram options have been set, respect that ! option. */ ! if (cirrusChip == CLGD5465) { ! cirrusLgBCLK = *(unsigned char *)(cirrusMMIOBase + 0x2C0) & 0x1F; ! } else { ! cirrusLgBCLK = *(unsigned char *)(cirrusMMIOBase + 0x8C) & 0x1F; ! } ! ! /*** WARNING! WARNING! DANGER, WILL ROBINSON! DANGER! *****/ ! /* see the warning above */ ! ! if (OFLG_ISSET(OPTION_SLOW_DRAM, &vga256InfoRec.options)) { ! /* Use a safe (maybe even default) BCLK: 258MHz */ ! cirrusLgBCLK = 0x12; /* 18*14.31818 = 257.727 */ ! } else if (OFLG_ISSET(OPTION_MED_DRAM, &vga256InfoRec.options)) { ! /* Middle of the road speed. Pretty safe: 272MHz */ ! cirrusLgBCLK = 0x13; /* 19*14.31818 = 272.046 */ ! } else if (OFLG_ISSET(OPTION_FAST_DRAM, &vga256InfoRec.options)) { ! /* Fastest mode that I've tested without melting the ! chip. */ ! if (cirrusChip == CLGD5465) ! cirrusLgBCLK = 0x15; /* 21*14.31818 = 300.682 */ ! else ! cirrusLgBCLK = 0x14; /* 20*14.31818 = 286.364 */ ! } ! ! /* Overload the cirrusDRAMBandwidth variable to record the ! bandwidth available. Rambus memory samples the clock at ! both the rising and falling edges of the BCLK, to the bandwidth ! is twice BCLK * 14.31818MHz. */ ! cirrusDRAMBandwidth = 14318 * cirrusLgBCLK * 2; ! ! ! if (xf86Verbose) { ! if (OFLG_ISSET(OPTION_FAST_DRAM, &vga256InfoRec.options) || ! OFLG_ISSET(OPTION_MED_DRAM, &vga256InfoRec.options) || ! OFLG_ISSET(OPTION_SLOW_DRAM, &vga256InfoRec.options)) ! ErrorF("%s %s: %s: Memory clock overridden by option\n", ! XCONFIG_GIVEN, vga256InfoRec.name, vga256InfoRec.chipset); ! ErrorF("%s %s: %s: Internal memory clock register set to 0x%02x\n", ! XCONFIG_GIVEN, vga256InfoRec.name, vga256InfoRec.chipset, ! cirrusLgBCLK); ! ErrorF("%s %s: %s: Approximate DRAM bandwidth for drawing: " ! "%d of %d MB/s\n", XCONFIG_GIVEN, ! vga256InfoRec.name, vga256InfoRec.chipset, ! (cirrusDRAMBandwidth - ! vga256InfoRec.clock[vga256InfoRec.modes->Clock] * ! vgaBitsPerPixel / 8) / 1000, cirrusDRAMBandwidth / 1000); ! } ! ! ! } else { /* We shouldn't get here. This case is where we (1) have a 546X, but (2) don't have a PCI card. We won't handle *************** *** 2575,2581 **** ErrorF("%s: %s: CL-GD546X found on a non-PCI bus. Please report\n" "card information (name, manufacturer, bus) to " ! "corina@bdc.cirrus.com.\n", vga256InfoRec.name, vga256InfoRec.chipset); } } --- 2682,2688 ---- ErrorF("%s: %s: CL-GD546X found on a non-PCI bus. Please report\n" "card information (name, manufacturer, bus) to " ! "corina@the4cs.com.\n", vga256InfoRec.name, vga256InfoRec.chipset); } } *************** *** 4088,4094 **** /* GOOD numbers: 0x10 */ new->DTTC = (new->DTTC & 0xFFE0) | (0x0010); break; - default: case 800: /* BAD numbers: */ /* GOOD numbers: 0x11 */ --- 4195,4200 ---- *************** *** 4100,4105 **** --- 4206,4212 ---- /* GOOD numbers: */ new->DTTC = (new->DTTC & 0xFFE0) | (0x0017); break; + default: case 1280: /* BAD numbers: */ /* GOOD numbers: */ *************** *** 4126,4132 **** /* BAD numbers: */ new->DTTC = (new->DTTC & 0xFFE0) | (0x000E); break; - default: case 800: /* GOOD numbers: 0x17 */ /* BAD numbers: */ --- 4233,4238 ---- *************** *** 4133,4147 **** new->DTTC = (new->DTTC & 0xFFE0) | (0x0017); break; case 1024: ! /* GOOD numbers: */ ! /* OKAY numbers: 0x15 0x14 0x16 0x18 */ /* BAD numbers: 0x0E 0x12 0x13 0x0D */ ! new->DTTC = (new->DTTC & 0xFFE0) | (0x0019); break; case 1280: /* GOOD numbers: */ /* BAD numbers: */ ! new->DTTC = (new->DTTC & 0xFFE0) | (0x000E); /* 10 */ break; } break; --- 4239,4254 ---- new->DTTC = (new->DTTC & 0xFFE0) | (0x0017); break; case 1024: ! /* GOOD numbers: 0x1D */ ! /* OKAY numbers: 0x15 0x14 0x16 0x18 0x19 */ /* BAD numbers: 0x0E 0x12 0x13 0x0D */ ! new->DTTC = (new->DTTC & 0xFFE0) | (0x001D); break; + default: case 1280: /* GOOD numbers: */ /* BAD numbers: */ ! new->DTTC = (new->DTTC & 0xFFE0) | (0x0023); /* 10 */ break; } break; *************** *** 4195,4202 **** } /* memory size switch statement */ ! if (cirrusChip == CLGD5465) new->TileCtrl = new->DTTC & 0xFFC0; } /* if HAVE546X() */ --- 4302,4321 ---- } /* memory size switch statement */ ! if (cirrusChip == CLGD5465) { ! /* The tile control information in the DTTC is ! also mirrored elsewhere. */ new->TileCtrl = new->DTTC & 0xFFC0; + + /* The 5465's DTTC records _fetches_ per line, not + tiles per line. Fetchs are 128-byte fetches. */ + if (new->DTTC & 0x0040) { + /* Using 256-byte wide tiles. Double the fetches + per line field. */ + new->DTTC = (new->DTTC & 0xC0FF) | ((new->DTTC & 0x3F00) << 1); + } + } + } /* if HAVE546X() */ *************** *** 4272,4344 **** unsigned char lsb; const int bumpThresh = 4; ! #ifdef MONOVGA /* Remember where X thinks the screen is at. */ screenStartX = x; screenStartY = y; ! if (HAVE546X()) { ! /* If the screen isn't aligned to a tile boundry, the first tile ! is hosed. Tiles on the 546X are either 128 or 256 bytes wide. ! The width can be determined by looking at cirrusTilesPerLineTab ! at index cirrusTilesPerLineIndex and examining the width field. ! ! NOTE: This problem has been fixed in the CL-GD5465. ! */ ! ! int pixelsPerTile; ! int wideTiles = cirrusTilesPerLineTab[cirrusTilesPerLineIndex].width; ! unsigned short *pX = (unsigned short *)(cirrusMMIOBase + 0xE0); ! int screenWidth; ! ! if (vgaBitsPerPixel == 8) ! pixelsPerTile = wideTiles?256:128; ! else if (vgaBitsPerPixel == 16) ! pixelsPerTile = wideTiles?128:64; ! else if (vgaBitsPerPixel == 24) /* Screen boundary must be tile */ ! pixelsPerTile = wideTiles?256:128; /* boundary and pixel boundary. */ ! else if (vgaBitsPerPixel == 32) ! pixelsPerTile = wideTiles?64:32; ! ! screenWidth = vga256InfoRec.frameX1 - vga256InfoRec.frameX0; ! if (cirrusChip != CLGD5465 || ! (cirrusChip == CLGD5465 && vgaBitsPerPixel == 24)) { ! if (*pX < bumpThresh) { ! /* Bumping up against left edge. Bias screen to left. */ ! x = (x / pixelsPerTile) * pixelsPerTile; ! onLeftSide = 1; ! } else if (*pX > screenWidth - bumpThresh) { ! /* Bumping up against right edge. Bias screen to right. */ ! x = ((x+pixelsPerTile-1) / pixelsPerTile) * pixelsPerTile; ! onLeftSide = 0; ! } else if (onLeftSide) { ! /* Scrolling vertically, but screen is biased to left edge. */ ! x = (x / pixelsPerTile) * pixelsPerTile; ! } else /* !onLeftSide */ { ! /* Scrolling vertically, but screen is biased to right edge. */ ! x = ((x+pixelsPerTile-1) / pixelsPerTile) * pixelsPerTile; ! } ! ! /* Don't scroll the virtual desktop too far right. If the desktop ! gets aligned with one tile too far right, then you see the screen ! wrapped horizontally on the far right of the display. */ ! if (x > vga256InfoRec.displayWidth - screenWidth) ! x -= pixelsPerTile; ! } ! ! cirrusLgCursorXOffset = screenStartX - x; ! } ! Base = (y * vga256InfoRec.displayWidth + x); lsb = Base & 7; Base >>= 3; #else - /* Remember where X thinks the screen is at. */ - screenStartX = x; - screenStartY = y; - if (HAVE546X()) { /* If the screen isn't aligned to a tile boundry, the first tile is hosed. Tiles on the 546X are either 128 or 256 bytes wide. --- 4391,4410 ---- unsigned char lsb; const int bumpThresh = 4; ! static int oldX = -1; ! int cursorX = x; ! /* Remember where X thinks the screen is at. */ screenStartX = x; screenStartY = y; ! #ifdef MONOVGA Base = (y * vga256InfoRec.displayWidth + x); lsb = Base & 7; Base >>= 3; #else if (HAVE546X()) { /* If the screen isn't aligned to a tile boundry, the first tile is hosed. Tiles on the 546X are either 128 or 256 bytes wide. *************** *** 4367,4377 **** if (cirrusChip != CLGD5465 || (cirrusChip == CLGD5465 && vgaBitsPerPixel == 24)) { ! if (*pX < 2) { /* Bumping up against left edge. Bias screen to left. */ x = (x / pixelsPerTile) * pixelsPerTile; onLeftSide = 1; ! } else if (*pX > screenWidth - 2) { /* Bumping up against right edge. Bias screen to right. */ x = ((x+pixelsPerTile-1) / pixelsPerTile) * pixelsPerTile; onLeftSide = 0; --- 4433,4450 ---- if (cirrusChip != CLGD5465 || (cirrusChip == CLGD5465 && vgaBitsPerPixel == 24)) { ! ! if (!cirrusUsingHWCursor && cursorX < oldX) { ! onLeftSide = 1; ! x = (x / pixelsPerTile) * pixelsPerTile; ! } else if (!cirrusUsingHWCursor && oldX < cursorX) { ! onLeftSide = 0; ! x = ((x+pixelsPerTile-1) / pixelsPerTile) * pixelsPerTile; ! } else if (cirrusUsingHWCursor && *pX < 2) { /* Bumping up against left edge. Bias screen to left. */ x = (x / pixelsPerTile) * pixelsPerTile; onLeftSide = 1; ! } else if (cirrusUsingHWCursor && *pX > screenWidth - 2) { /* Bumping up against right edge. Bias screen to right. */ x = ((x+pixelsPerTile-1) / pixelsPerTile) * pixelsPerTile; onLeftSide = 0; *************** *** 4390,4395 **** --- 4463,4469 ---- x -= pixelsPerTile; } + cirrusLgCursorXOffset = screenStartX - x; } *************** *** 4435,4440 **** --- 4509,4516 ---- while (!(inb(vgaIOBase + 0xA) & 0x08)); } #endif + + oldX = cursorX; } /* *** ./programs/Xserver/hw/xfree86/vga256/drivers/cirrus/cir_driver.h@@/PUBLIC-LATEST Sat Jul 19 10:37:18 1997 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/cirrus/cir_driver.h Fri Mar 6 16:49:10 1998 *************** *** 1,4 **** ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/cirrus/cir_driver.h,v 3.32.2.1 1997/05/10 09:10:23 hohndel Exp $ */ /* * * Copyright 1993 by Simon P. Cooper, New Brunswick, New Jersey, USA. --- 1,4 ---- ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/cirrus/cir_driver.h,v 3.32.2.2 1998/02/15 16:09:35 hohndel Exp $ */ /* * * Copyright 1993 by Simon P. Cooper, New Brunswick, New Jersey, USA. *************** *** 23,33 **** * * Author: Simon P. Cooper, <scooper@vizlab.rutgers.edu> * Modified: Harm Hanemaayer, <hhanemaa@cs.ruu.nl> ! * Modified: Corin Anderson, <corina@bdc.cirrus.com> * * cir_driver.h,v 1.8 1994/09/14 13:58:59 scooper Exp */ ! /* $TOG: cir_driver.h /main/17 1997/07/19 10:37:20 kaleb $ */ #define CIRRUS_INCLUDE_COPYPLANE1TO8 --- 23,33 ---- * * Author: Simon P. Cooper, <scooper@vizlab.rutgers.edu> * Modified: Harm Hanemaayer, <hhanemaa@cs.ruu.nl> ! * Modified: Corin Anderson, <corina@the4cs.com> * * cir_driver.h,v 1.8 1994/09/14 13:58:59 scooper Exp */ ! /* $TOG: cir_driver.h /main/18 1998/03/06 16:50:47 kaleb $ */ #define CIRRUS_INCLUDE_COPYPLANE1TO8 *** ./programs/Xserver/hw/xfree86/vga256/drivers/cirrus/cir_fillLG.c@@/PUBLIC-LATEST Tue Nov 11 15:46:37 1997 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/cirrus/cir_fillLG.c Fri Mar 6 16:49:15 1998 *************** *** 1,8 **** ! /* $TOG: cir_fillLG.c /main/7 1997/11/11 15:46:39 msr $ */ /* * cir_fillLG.c * ! * Copyright 1996 by Corin Anderson, Bellevue, Washington * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that --- 1,8 ---- ! /* $TOG: cir_fillLG.c /main/8 1998/03/06 16:50:52 kaleb $ */ /* * cir_fillLG.c * ! * Copyright 1996 by Corin Anderson, Tukwila, Washington * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that *************** *** 22,32 **** * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. * ! * Author: Corin Anderson, <corina@bdc.cirrus.com> * */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/cirrus/cir_fillLG.c,v 3.1 1996/09/29 13:39:49 dawes Exp $ */ #include "vga256.h" --- 22,32 ---- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. * ! * Author: Corin Anderson, <corina@the4cs.com> * */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/cirrus/cir_fillLG.c,v 3.2.2.1 1998/02/15 16:09:35 hohndel Exp $ */ #include "vga256.h" *************** *** 186,191 **** --- 186,194 ---- extern void cfb16FillRectSolidCopy(); extern void cfb16FillRectSolidGeneral(); extern void cfb16FillRectTileOdd(); + extern void cfb24FillRectSolidCopy(); + extern void cfb24FillRectSolidGeneral(); + extern void cfb24FillRectTileOdd(); extern void cfb32FillRectSolidCopy(); extern void cfb32FillRectSolidGeneral(); extern void cfb32FillRectTileOdd(); *************** *** 261,266 **** --- 264,271 ---- BoxFill = vga256FillRectTileOdd; } else if (vgaBitsPerPixel == 16) { BoxFill = cfb16FillRectTileOdd; + } else if (vgaBitsPerPixel == 24) { + BoxFill = cfb24FillRectTileOdd; } else { BoxFill = cfb32FillRectTileOdd; } *** ./programs/Xserver/hw/xfree86/vga256/drivers/et4000/Imakefile@@/PUBLIC-LATEST Sat Jul 19 10:39:45 1997 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/et4000/Imakefile Fri Mar 6 16:49:23 1998 *************** *** 1,15 **** ! XCOMM $TOG: Imakefile /main/11 1997/07/19 10:39:48 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/et4000/Imakefile,v 3.10.2.2 1997/05/09 13:49:45 hohndel Exp $ #include <Server.tmpl> ! SRCS = et4_driver.c et4_accel.c et4_bank.s tseng_acl.c tseng_ramdac.c tseng_clock.c tseng_cursor.c ! OBJS = et4_driver.o et4_accel.o et4_bank.o tseng_acl.o tseng_ramdac.o tseng_clock.o tseng_cursor.o #if XF86LinkKit INCLUDES = -I. -I../../../include -I../../../include/X11 -I../.. -I../../../xaa --- 1,17 ---- ! XCOMM $TOG: Imakefile /main/12 1998/03/06 16:51:01 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/et4000/Imakefile,v 3.10.2.3 1998/02/01 16:05:04 robin Exp $ #include <Server.tmpl> ! SRCS = et4_driver.c et4_accel.c et4_bank.s tseng_acl.c tseng_ramdac.c \ ! tseng_clock.c tseng_cursor.c tseng_colexp.c tseng_dpms.c ! OBJS = et4_driver.o et4_accel.o et4_bank.o tseng_acl.o tseng_ramdac.o \ ! tseng_clock.o tseng_cursor.o tseng_colexp.o tseng_dpms.o #if XF86LinkKit INCLUDES = -I. -I../../../include -I../../../include/X11 -I../.. -I../../../xaa *************** *** 36,41 **** --- 38,46 ---- InstallLinkKitNonExecFile(et4_accel.c,$(LINKKITDIR)/drivers/vga256/et4000) InstallLinkKitNonExecFile(tseng_acl.c,$(LINKKITDIR)/drivers/vga256/et4000) InstallLinkKitNonExecFile(tseng_acl.h,$(LINKKITDIR)/drivers/vga256/et4000) + InstallLinkKitNonExecFile(tseng_inline.h,$(LINKKITDIR)/drivers/vga256/et4000) + InstallLinkKitNonExecFile(tseng_colexp.c,$(LINKKITDIR)/drivers/vga256/et4000) + InstallLinkKitNonExecFile(tseng_colexp.h,$(LINKKITDIR)/drivers/vga256/et4000) InstallLinkKitNonExecFile(tseng_ramdac.c,$(LINKKITDIR)/drivers/vga256/et4000) InstallLinkKitNonExecFile(tseng_clock.c,$(LINKKITDIR)/drivers/vga256/et4000) InstallLinkKitNonExecFile(tseng_cursor.c,$(LINKKITDIR)/drivers/vga256/et4000) *************** *** 42,47 **** --- 47,53 ---- InstallLinkKitNonExecFile(tseng_cursor.h,$(LINKKITDIR)/drivers/vga256/et4000) InstallLinkKitNonExecFile(tseng.h,$(LINKKITDIR)/drivers/vga256/et4000) InstallLinkKitNonExecFile(bank.s,$(LINKKITDIR)/drivers/vga256/et4000) + InstallLinkKitNonExecFile(tseng_dpms.c,$(LINKKITDIR)/drivers/vga256/et4000) InstallLinkKitNonExecFile(Imakefile,$(LINKKITDIR)/drivers/vga256/et4000) DependTarget() *** ./programs/Xserver/hw/xfree86/vga256/drivers/et4000/et4_driver.c@@/PUBLIC-LATEST Sun Aug 10 13:05:12 1997 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/et4000/et4_driver.c Fri Mar 6 16:49:33 1998 *************** *** 1,5 **** /* ! * $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/et4000/et4_driver.c,v 3.45.2.16 1997/07/10 08:02:26 hohndel Exp $ * * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany. * --- 1,5 ---- /* ! * $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/et4000/et4_driver.c,v 3.45.2.22 1998/02/28 11:11:42 dawes Exp $ * * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany. * *************** *** 25,31 **** * ET6000 and ET4000W32 16/24/32 bpp support by Koen Gadeyne * DPMS support by Harald Nordgård Hansen */ ! /* $TOG: et4_driver.c /main/29 1997/08/10 13:03:48 kaleb $ */ #include "X.h" #include "input.h" --- 25,31 ---- * ET6000 and ET4000W32 16/24/32 bpp support by Koen Gadeyne * DPMS support by Harald Nordgård Hansen */ ! /* $TOG: et4_driver.c /main/30 1998/03/06 16:51:11 kaleb $ */ #include "X.h" #include "input.h" *************** *** 45,55 **** #include "vga.h" #include "vgaPCI.h" - /* W32_ACCEL_SUPPORT is set for the XF86_W32 server, not for the SVGA server */ - #ifdef W32_ACCEL_SUPPORT - #include "w32.h" - #endif - #ifdef XFreeXDGA #include "X.h" #include "Xproto.h" --- 45,50 ---- *************** *** 63,82 **** #define MONOVGA #endif - #ifndef W32_ACCEL_SUPPORT #ifndef MONOVGA - #define USE_XAA /* not XF86_W32 and not MONO and not VGA16 == XF86_SVGA */ #include "tseng_acl.h" #endif - #endif - #include "tseng.h" - #ifndef MONOVGA #include "vga256.h" #endif - static Bool ET4000Probe(); static char * ET4000Ident(); static void ET4000EnterLeave(); --- 58,71 ---- *************** *** 86,95 **** static void ET4000Restore(); static void ET4000Adjust(); static void ET4000FbInit(); - #ifdef DPMSExtension - static void TsengCrtcDPMSSet(); - static void TsengHVSyncDPMSSet(); - #endif extern void ET4000SetRead(); extern void ET4000SetWrite(); extern void ET4000SetReadWrite(); --- 75,80 ---- *************** *** 100,139 **** extern void ET4000HWSaveScreen(); unsigned char tseng_save_divide = 0; ! #ifdef USE_XAA /* Do we use PCI-retry or busy-waiting */ ! Bool Use_Pci_Retry = 0; /* Do we use the XAA acceleration architecture */ ! static Bool Use_ACL = FALSE; ! #endif #ifndef MONOVGA #include "tseng_cursor.h" extern vgaHWCursorRec vgaHWCursor; static unsigned char initialRCConf = 0x70; - #ifdef W32_SUPPORT /* these should be taken from the "Saved" register set instead of this way */ static unsigned char initialCompatibility = 0x18; static unsigned char initialVSConf1 = 0x03; static unsigned char initialVSConf2 = 0x0b; static unsigned char initialIMAPortCtrl = 0x20; - #endif - #endif static unsigned char initialET6KMemBase = 0xF0; static unsigned char initialET6KMclkM = 0x56, initialET6KMclkN = 0x25; static unsigned char initialET6KPerfContr = 0x3a; ! static unsigned char save_VSConf1=0x03; static int bustype=0; /* W32 bus type (currently used for lin mem on W32i) */ /* some exported variables */ t_tseng_type et4000_type = TYPE_UNKNOWN; unsigned long ET6Kbase; /* PCI config space base address for ET6000 */ static pciConfigPtr tseng_pcr = NULL; --- 85,134 ---- extern void ET4000HWSaveScreen(); unsigned char tseng_save_divide = 0; ! /* Do we use PCI-retry or busy-waiting */ ! Bool tseng_use_PCI_Retry = 0; /* Do we use the XAA acceleration architecture */ ! Bool tseng_use_ACL = FALSE; + /* Is this a card limited to 1Mb of linear memory */ + static Bool tseng_linmem_1meg = FALSE; + #ifndef MONOVGA #include "tseng_cursor.h" extern vgaHWCursorRec vgaHWCursor; + #endif static unsigned char initialRCConf = 0x70; /* these should be taken from the "Saved" register set instead of this way */ static unsigned char initialCompatibility = 0x18; static unsigned char initialVSConf1 = 0x03; static unsigned char initialVSConf2 = 0x0b; static unsigned char initialIMAPortCtrl = 0x20; static unsigned char initialET6KMemBase = 0xF0; static unsigned char initialET6KMclkM = 0x56, initialET6KMclkN = 0x25; static unsigned char initialET6KPerfContr = 0x3a; + static unsigned char initialET6KRasCas = 0x15; + static unsigned char initialET6KDispFeat = 0x00; ! /* To hold the clock data between Init and Restore */ ! static unsigned long icd2061_dwv; static int bustype=0; /* W32 bus type (currently used for lin mem on W32i) */ + static unsigned char save_VSConf1=0x03; + /* some exported variables */ t_tseng_type et4000_type = TYPE_UNKNOWN; + int Tseng_bus; + static unsigned long Tseng_MemBase_mask = -1L; + unsigned long ET6Kbase; /* PCI config space base address for ET6000 */ + int tseng_bytesperpixel; + static pciConfigPtr tseng_pcr = NULL; *************** *** 183,189 **** static SymTabRec chipsets[] = { { TYPE_ET4000, "ET4000" }, - #ifdef W32_SUPPORT { TYPE_ET4000W32, "ET4000W32" }, { TYPE_ET4000W32I, "ET4000W32i" }, { TYPE_ET4000W32Ib, "ET4000W32i_rev_b" }, --- 178,183 ---- *************** *** 193,200 **** { TYPE_ET4000W32Pb, "ET4000W32p_rev_b" }, { TYPE_ET4000W32Pc, "ET4000W32p_rev_c" }, { TYPE_ET4000W32Pd, "ET4000W32p_rev_d" }, - #endif { TYPE_ET6000, "ET6000" }, { -1, "" }, }; --- 187,197 ---- { TYPE_ET4000W32Pb, "ET4000W32p_rev_b" }, { TYPE_ET4000W32Pc, "ET4000W32p_rev_c" }, { TYPE_ET4000W32Pd, "ET4000W32p_rev_d" }, { TYPE_ET6000, "ET6000" }, + { TYPE_ET6100, "ET6100" }, + #if 0 + { TYPE_ET6300, "ET6300" }, + #endif { -1, "" }, }; *************** *** 201,209 **** Bool (*ClockSelect)(); static unsigned ET4000_ExtPorts[] = {0x3B8, 0x3BF, 0x3CD, 0x3CB, 0x3D8, - #ifdef W32_SUPPORT 0x217a, 0x217b, /* These last two are W32 specific */ - #endif }; static int Num_ET4000_ExtPorts = --- 198,204 ---- *************** *** 230,281 **** } - #ifdef USE_XAA /* ! * ET4000LinMem -- ! * handle linear memory mode stuff */ ! static Bool ! ET4000LinMem(Bool autodetect) { - /* W32p cards can give us their Lin. memory address through the PCI - * configuration. For W32i, this is not possible (VL-bus, MCA or ISA). W32i - * cards have three extra external "address" lines, SEG2..SEG0 which _can_ - * be connected to any set of address lines in addition to the already - * connected A23..A0. SEG2..SEG0 are either for three extra address lines - * or to connect an external address decoder (mostly an 74F27). It is NOT - * possible to know how SEG2..SEG0 are connected. We _assume_ they are - * connected to A26..A24 (most likely case). This means linear memory can - * be decoded into any 4MB block in the address range 0..128MB. - */ - - /* - * For non-PCI cards (especially VLB), most motherboards don't decode all - * 32 address bits. The weird default memory base below will always end up - * at the end of the decoded address space -- independent of the number of - * address bits that are decoded. - */ - #define DEFAULT_LIN_MEMBASE ( (256 + 128 + 64 + 32 + 16 + 8 + 4) * 1024*1024 ) - #define DEFAULT_LIN_MEMBASE_PCI (DEFAULT_LIN_MEMBASE & 0xFF000000) - - /* This code will probably only work for PCI and VLB bus cards. MCA is weird, - * ISA is out of the question (I think). - */ - - unsigned long mask = -1L; unsigned char bus; ! ! if (vgaBitsPerPixel < 8) return FALSE; ! ! if (et4000_type < TYPE_ET4000W32I) { ! ErrorF("%s %s: This chipset does not support linear memory.\n", ! XCONFIG_PROBED, vga256InfoRec.name); ! return (FALSE); /* no can do */ ! } ! switch(et4000_type) { case TYPE_ET4000W32I: case TYPE_ET4000W32Ib: case TYPE_ET4000W32Ic: --- 225,246 ---- } /* ! * TsengFindBusType -- ! * determine bus interface type ! * (also determines Lin Mem address mask, because that depends on bustype) */ ! static void ! TsengFindBusType() { unsigned char bus; ! ! Tseng_bus = BUS_ISA; ! switch(et4000_type) { + case TYPE_ET4000W32: case TYPE_ET4000W32I: case TYPE_ET4000W32Ib: case TYPE_ET4000W32Ic: *************** *** 284,313 **** * * We assume the driver code disables the image port (which it does) * ! * ISA: [ A23, A22, A21, A20 ] == [ SM1, SM0, 0, 0 ] * MCA: [ A24, A23, A22, A21, A20 ] == [ SM2, SM1, SM0, 0, 0 ] * VLB: [ /A26, /A25, /A24, A23, A22, A21, A20 ] == ("/" means inverted!) * [ SM4, SM3, SM2, SM1, SM0, 0 , 0 ] */ outb(0x217A, 0xEF); bus = inb(0x217B) & 0x60; /* Determine bus type */ ! ErrorF("%s %s: Detected W32i bus type: ", XCONFIG_PROBED, vga256InfoRec.name); switch (bus) { case 0x40: ErrorF("MCA.\n"); ! bustype = BUS_MCA; ! mask = 0x01C00000; /* MADE24, A23 and A22 are decoded */ break; case 0x60: ErrorF("Local Bus.\n"); ! bustype = BUS_VLB; ! mask = 0x07C00000; /* A26..A22 are decoded */ break; case 0x00: case 0x20: default: ErrorF("ISA.\n"); ! bustype = BUS_ISA; ! mask = 0x00C00000; /* SEGE and A22 are decoded */ break; } break; --- 249,278 ---- * * We assume the driver code disables the image port (which it does) * ! * ISA: [ A23==SEGE, A22, A21, A20 ] == [ SM1, SM0, 0, 0 ] * MCA: [ A24, A23, A22, A21, A20 ] == [ SM2, SM1, SM0, 0, 0 ] * VLB: [ /A26, /A25, /A24, A23, A22, A21, A20 ] == ("/" means inverted!) * [ SM4, SM3, SM2, SM1, SM0, 0 , 0 ] */ outb(0x217A, 0xEF); bus = inb(0x217B) & 0x60; /* Determine bus type */ ! ErrorF("%s %s: Detected W32/W32i bus type: ", XCONFIG_PROBED, vga256InfoRec.name); switch (bus) { case 0x40: ErrorF("MCA.\n"); ! Tseng_bus = BUS_MCA; ! Tseng_MemBase_mask = 0x01C00000; /* MADE24, A23 and A22 are decoded */ break; case 0x60: ErrorF("Local Bus.\n"); ! Tseng_bus = BUS_VLB; ! Tseng_MemBase_mask = 0x07C00000; /* A26..A22 are decoded */ break; case 0x00: case 0x20: default: ErrorF("ISA.\n"); ! Tseng_bus = BUS_ISA; ! Tseng_MemBase_mask = 0x00C00000; /* SEGE and A22 are decoded */ break; } break; *************** *** 321,363 **** XCONFIG_PROBED, vga256InfoRec.name, bus); switch (bus) { case 0x1C: ! ErrorF("Local Buffered Bus or PCI.\n"); ! bustype = BUS_PCI; ! mask = 0x3FC00000; /* A29..A22 */ break; case 0x13: ErrorF("Local Bus option 1a.\n"); ! bustype = BUS_VLB; ! mask = 0x1FC00000; /* SEGI,A27..A22 */ break; case 0x11: ErrorF("Local Bus option 1b.\n"); ! bustype = BUS_VLB; ! mask = 0x00C00000; /* SEGI,A22 */ break; case 0x08: case 0x0B: default: ErrorF("Local Bus option 2.\n"); ! bustype = BUS_VLB; ! mask = 0x3FC00000; /* A29..A22 */ break; } ! if ( (et4000_type >= TYPE_ET4000W32Pc) && (mask = 0x3FC00000) ) ! mask |= 0xC0000000; /* A31,A30 decoded from PCI config space */ break; case TYPE_ET6000: ! mask = 0xFF000000; break; } if (vga256InfoRec.MemBase != 0) /* MemBase given from XF86Config */ { /* check for possible errors in given linear base address */ ! if ((vga256InfoRec.MemBase & (~mask)) != 0) { ErrorF("%s %s: MemBase out of range. Must be <= 0x%x on 0x%x boundary.\n", ! XCONFIG_PROBED, vga256InfoRec.name, mask, ~(mask | 0xFF000000) + 1); ! vga256InfoRec.MemBase &= ~mask; } } else /* MemBase not given: find it */ --- 286,400 ---- XCONFIG_PROBED, vga256InfoRec.name, bus); switch (bus) { case 0x1C: ! if (tseng_pcr) /* PCI bus detected. Can we read this from some register instead? */ ! { ! Tseng_bus = BUS_PCI; ! Tseng_MemBase_mask = 0x3FC00000; /* A29..A22 */ ! ErrorF("PCI.\n"); ! } ! else ! { ! Tseng_bus = BUS_VLB; ! Tseng_MemBase_mask = 0x3FC00000; /* A29..A22 */ ! ErrorF("Local Buffered Bus\n"); ! tseng_linmem_1meg = TRUE; /* IMA bus support allows for only 1M linear memory */ ! } break; case 0x13: ErrorF("Local Bus option 1a.\n"); ! Tseng_bus = BUS_VLB; ! if (et4000_type == TYPE_ET4000W32Pa) ! Tseng_MemBase_mask = 0x07C00000; ! else ! Tseng_MemBase_mask = 0x1FC00000; /* SEGI,A27..A22 */ break; case 0x11: ErrorF("Local Bus option 1b.\n"); ! Tseng_bus = BUS_VLB; ! Tseng_MemBase_mask = 0x00C00000; /* SEGI,A22 */ ! tseng_linmem_1meg = TRUE; /* IMA bus support allows for only 1M linear memory */ break; case 0x08: case 0x0B: default: ErrorF("Local Bus option 2.\n"); ! Tseng_bus = BUS_VLB; ! Tseng_MemBase_mask = 0x3FC00000; /* A29..A22 */ break; } ! if ( Is_W32p_cd && (Tseng_MemBase_mask = 0x3FC00000) ) ! Tseng_MemBase_mask |= 0xC0000000; /* A31,A30 decoded from PCI config space */ break; case TYPE_ET6000: ! case TYPE_ET6100: ! case TYPE_ET6300: ! Tseng_bus = BUS_PCI; ! Tseng_MemBase_mask = 0xFF000000; break; } + + } + + + /* + * ET4000LinMem -- + * handle linear memory mode stuff + */ + + static void + ET4000LinMem(Bool autodetect) + { + /* + * Check if a linear framebuffer is supported. + */ + + if (vgaBitsPerPixel < 8) { + FatalError("%s %s: Linear memory is not supported for color depth %d.\n", + XCONFIG_PROBED, vga256InfoRec.name, vgaBitsPerPixel); + } + + if (!CHIP_SUPPORTS_LINEAR) { + if (vgaBitsPerPixel > 8) + FatalError("%s %s: A color depth of %dbpp is not supported (linear memory required).\n", + XCONFIG_PROBED, vga256InfoRec.name, vgaBitsPerPixel); + else + FatalError("%s %s: This chipset does not support linear memory.\n", + XCONFIG_PROBED, vga256InfoRec.name); + } + + if (!xf86LinearVidMem()) { + FatalError("%s %s: This operating system does not support a linear framebuffer.\n", + XCONFIG_PROBED, vga256InfoRec.name); + } + + /* W32p cards can give us their Lin. memory address through the PCI + * configuration. For W32i, this is not possible (VL-bus, MCA or ISA). W32i + * cards have three extra external "address" lines, SEG2..SEG0 which _can_ + * be connected to any set of address lines in addition to the already + * connected A23..A0. SEG2..SEG0 are either for three extra address lines + * or to connect an external address decoder (mostly an 74F27). It is NOT + * possible to know how SEG2..SEG0 are connected. We _assume_ they are + * connected to A26..A24 (most likely case). This means linear memory can + * be decoded into any 4MB block in the address range 0..128MB. + */ + + /* + * For non-PCI cards (especially VLB), most motherboards don't decode all + * 32 address bits. The weird default memory base below will always end up + * at the end of the decoded address space -- independent of the number of + * address bits that are decoded. + */ + #define DEFAULT_LIN_MEMBASE ( (256 + 128 + 64 + 32 + 16 + 8 + 4) * 1024*1024 ) + #define DEFAULT_LIN_MEMBASE_PCI (DEFAULT_LIN_MEMBASE & 0xFF000000) + if (vga256InfoRec.MemBase != 0) /* MemBase given from XF86Config */ { /* check for possible errors in given linear base address */ ! if ((vga256InfoRec.MemBase & (~Tseng_MemBase_mask)) != 0) { ErrorF("%s %s: MemBase out of range. Must be <= 0x%x on 0x%x boundary.\n", ! XCONFIG_PROBED, vga256InfoRec.name, Tseng_MemBase_mask, ~(Tseng_MemBase_mask | 0xFF000000) + 1); ! vga256InfoRec.MemBase &= ~Tseng_MemBase_mask; } } else /* MemBase not given: find it */ *************** *** 364,369 **** --- 401,407 ---- { switch(et4000_type) { + case TYPE_ET4000W32: case TYPE_ET4000W32I: case TYPE_ET4000W32Ib: case TYPE_ET4000W32Ic: *************** *** 374,402 **** case TYPE_ET4000W32Pb: if (tseng_pcr) vga256InfoRec.MemBase = tseng_pcr->_base0; else vga256InfoRec.MemBase = DEFAULT_LIN_MEMBASE; ! if (vga256InfoRec.MemBase > mask) /* ... except if we can't decode that much */ ! vga256InfoRec.MemBase = mask - 4*1024*1024; /* top of decodable memory */ break; case TYPE_ET4000W32Pc: /* A31,A30 decoded from PCI config space, but in PCI mode only */ case TYPE_ET4000W32Pd: if (tseng_pcr) vga256InfoRec.MemBase = tseng_pcr->_base0; else vga256InfoRec.MemBase = 0xC0000000 | DEFAULT_LIN_MEMBASE_PCI; ! if (vga256InfoRec.MemBase > mask) /* ... except if we can't decode that much */ ! vga256InfoRec.MemBase = mask - 4*1024*1024; /* top of decodable memory */ break; case TYPE_ET6000: if (tseng_pcr && autodetect) /* don't trust PCI when not autodetecting */ vga256InfoRec.MemBase = tseng_pcr->_base0; else if (inb(ET6Kbase+0x13) != 0) { vga256InfoRec.MemBase = inb(ET6Kbase+0x13) << 24; ! ErrorF("%s %s: ET6000: port-probed linear memory base = 0x%x\n", ! XCONFIG_PROBED, vga256InfoRec.name, vga256InfoRec.MemBase); } else vga256InfoRec.MemBase = 0xF0000000; /* map memory near top of memory by default */ break; } ! vga256InfoRec.MemBase &= mask; } /* One final check for a valid MemBase */ --- 412,443 ---- case TYPE_ET4000W32Pb: if (tseng_pcr) vga256InfoRec.MemBase = tseng_pcr->_base0; else vga256InfoRec.MemBase = DEFAULT_LIN_MEMBASE; ! if (vga256InfoRec.MemBase > Tseng_MemBase_mask) /* ... except if we can't decode that much */ ! vga256InfoRec.MemBase = Tseng_MemBase_mask - 4*1024*1024; /* top of decodable memory */ break; case TYPE_ET4000W32Pc: /* A31,A30 decoded from PCI config space, but in PCI mode only */ case TYPE_ET4000W32Pd: if (tseng_pcr) vga256InfoRec.MemBase = tseng_pcr->_base0; else vga256InfoRec.MemBase = 0xC0000000 | DEFAULT_LIN_MEMBASE_PCI; ! if (vga256InfoRec.MemBase > Tseng_MemBase_mask) /* ... except if we can't decode that much */ ! vga256InfoRec.MemBase = Tseng_MemBase_mask - 4*1024*1024; /* top of decodable memory */ break; case TYPE_ET6000: + case TYPE_ET6100: + case TYPE_ET6300: if (tseng_pcr && autodetect) /* don't trust PCI when not autodetecting */ vga256InfoRec.MemBase = tseng_pcr->_base0; else if (inb(ET6Kbase+0x13) != 0) { vga256InfoRec.MemBase = inb(ET6Kbase+0x13) << 24; ! ErrorF("%s %s: %s: port-probed linear memory base = 0x%x\n", ! XCONFIG_PROBED, vga256InfoRec.name, ! vga256InfoRec.chipset, vga256InfoRec.MemBase); } else vga256InfoRec.MemBase = 0xF0000000; /* map memory near top of memory by default */ break; } ! vga256InfoRec.MemBase &= Tseng_MemBase_mask; } /* One final check for a valid MemBase */ *************** *** 438,451 **** if (ET4000.ChipLinearBase==0L) { ! ErrorF("%s %s: Linear memory address == 0x0. KABOOM! Going back to banked mode.\n", XCONFIG_PROBED, vga256InfoRec.name); - ET4000.ChipUseLinearAddressing = FALSE; - return(FALSE); } - return(TRUE); } - #endif static Bool --- 479,488 ---- if (ET4000.ChipLinearBase==0L) { ! FatalError("%s %s: Linear MemBase == 0. Giving up (please report this to XFree86@XFree86.Org).\n", XCONFIG_PROBED, vga256InfoRec.name); } } static Bool *************** *** 475,482 **** outb(vgaIOBase + 4, 0x21); ET6Kbase = (inb(vgaIOBase + 5) << 8); outb(vgaIOBase + 4, 0x22); ET6Kbase += (inb(vgaIOBase + 5) << 16); outb(vgaIOBase + 4, 0x23); ET6Kbase += (inb(vgaIOBase + 5) << 24); /* keep this split up */ ! ErrorF("%s %s: ET6000: port-probed I/O base = 0x%x\n", ! XCONFIG_PROBED, vga256InfoRec.name, ET6Kbase); } /* define used IO ports... Is this really necessary for PCI config space IO? */ --- 512,519 ---- outb(vgaIOBase + 4, 0x21); ET6Kbase = (inb(vgaIOBase + 5) << 8); outb(vgaIOBase + 4, 0x22); ET6Kbase += (inb(vgaIOBase + 5) << 16); outb(vgaIOBase + 4, 0x23); ET6Kbase += (inb(vgaIOBase + 5) << 24); /* keep this split up */ ! ErrorF("%s %s: %s: port-probed I/O base = 0x%x\n", ! XCONFIG_PROBED, vga256InfoRec.name, vga256InfoRec.chipset, ET6Kbase); } /* define used IO ports... Is this really necessary for PCI config space IO? */ *************** *** 490,499 **** ClockSelect = Tseng_ET6000ClockSelect; - outb(ET6Kbase+0x67, 0x0f); - ErrorF("%s %s: ET6000: CLKDAC ID: 0x%X\n", - XCONFIG_PROBED, vga256InfoRec.name, inb(ET6Kbase+0x69)); - #ifdef DO_WE_NEED_THIS vga256InfoRec.clocks = 3; vga256InfoRec.clock[0] = 25175; --- 527,532 ---- *************** *** 501,511 **** vga256InfoRec.clock[2] = 31500; /* this one will be reprogrammed */ #endif ! /* avoid autoprobing for what we already know */ ! vga256InfoRec.ramdac = xf86TokenToString(TsengDacTable, ET6000_DAC); ! ErrorF("%s %s: ET6000: Using built-in 135 MHz programmable Clock Chip/RAMDAC\n", ! XCONFIG_PROBED, vga256InfoRec.name); return(TRUE); } --- 534,543 ---- vga256InfoRec.clock[2] = 31500; /* this one will be reprogrammed */ #endif ! outb(ET6Kbase+0x67, 0x0f); /* select CLKDAC ID register */ ! ErrorF("%s %s: %s: Using built-in programmable Clock Chip/RAMDAC (ID=0x%X)\n", ! XCONFIG_PROBED, vga256InfoRec.name, vga256InfoRec.chipset, inb(ET6Kbase+0x69)); return(TRUE); } *************** *** 549,555 **** et4000_type = TYPE_ET4000; - #ifdef W32_SUPPORT /* * Now check for an ET4000/W32. * Test for writability of 0x3cb. --- 581,586 ---- *************** *** 595,601 **** return(FALSE); } } - #endif vga256InfoRec.chipset = xf86TokenToString(chipsets, et4000_type); --- 626,631 ---- *************** *** 638,653 **** int save_vidmem; if (ram > 4096) { ! ErrorF("%s %s: ET6000: Detected more than 4096 kb of video RAM. Clipped to 4096kb\n", ! XCONFIG_PROBED, vga256InfoRec.name); ram = 4096; } - /* vga256InfoRec.VGAbase is NULL at this point, because the VGA aperture - * hasn't been memory-mapped yet when we enter the probing code. - */ check_vgabase = xf86MapVidMem(vga256InfoRec.scrnIndex, VGA_REGION, ! (pointer)0xA0000, 0x10000); /* * We need to set the VGA controller in VGA graphics mode, or else we won't --- 668,680 ---- int save_vidmem; if (ram > 4096) { ! ErrorF("%s %s: %s: Detected more than 4096 kb of video RAM. Clipped to 4096kb\n", ! XCONFIG_PROBED, vga256InfoRec.name, vga256InfoRec.chipset); ram = 4096; } check_vgabase = xf86MapVidMem(vga256InfoRec.scrnIndex, VGA_REGION, ! (pointer)vga256InfoRec.VGAbase, 0x10000); /* * We need to set the VGA controller in VGA graphics mode, or else we won't *************** *** 719,725 **** outb(0x3C4, 4); outb(0x3C5, oldSEQ4); xf86UnMapVidMem(vga256InfoRec.scrnIndex, VGA_REGION, ! check_vgabase, 0x10000); return real_ram; } --- 746,752 ---- outb(0x3C4, 4); outb(0x3C5, oldSEQ4); xf86UnMapVidMem(vga256InfoRec.scrnIndex, VGA_REGION, ! check_vgabase, 0x10000); return real_ram; } *************** *** 735,741 **** unsigned char config; int ramtype=0; ! if (et4000_type >= TYPE_ET6000) { ramtype = inb(0x3C2) & 0x03; switch (ramtype) --- 762,768 ---- unsigned char config; int ramtype=0; ! if (Is_ET6K) { ramtype = inb(0x3C2) & 0x03; switch (ramtype) *************** *** 750,767 **** /* 8*32kb MDRAM refresh control granularity in the ET6000 fails to */ /* recognize 2.25 MB of memory (detects 2.5 instead) */ vga256InfoRec.videoRam = et6000_check_videoram(vga256InfoRec.videoRam); ! ErrorF("%s %s: ET6000: Detected %d kb of multi-bank DRAM\n", ! XCONFIG_PROBED, vga256InfoRec.name, vga256InfoRec.videoRam); break; case 0x00: /* DRAM */ ramtype=1; vga256InfoRec.videoRam = 1024 << (inb(ET6Kbase+0x45) & 0x03); ! ErrorF("%s %s: ET6000: Detected %d Mb of standard DRAM\n", ! XCONFIG_PROBED, vga256InfoRec.name, vga256InfoRec.videoRam); break; default: /* unknown RAM type */ ! ErrorF("%s %s: ET6000: Unknown video memory type %d -- assuming 1 MB (unless specified)\n", ! XCONFIG_PROBED, vga256InfoRec.name, ramtype); vga256InfoRec.videoRam = 1024; } } --- 777,794 ---- /* 8*32kb MDRAM refresh control granularity in the ET6000 fails to */ /* recognize 2.25 MB of memory (detects 2.5 instead) */ vga256InfoRec.videoRam = et6000_check_videoram(vga256InfoRec.videoRam); ! ErrorF("%s %s: %s: Detected %d kb of multi-bank DRAM\n", ! XCONFIG_PROBED, vga256InfoRec.name, vga256InfoRec.chipset, vga256InfoRec.videoRam); break; case 0x00: /* DRAM */ ramtype=1; vga256InfoRec.videoRam = 1024 << (inb(ET6Kbase+0x45) & 0x03); ! ErrorF("%s %s: %s: Detected %d Mb of standard DRAM\n", ! XCONFIG_PROBED, vga256InfoRec.name, vga256InfoRec.chipset, vga256InfoRec.videoRam); break; default: /* unknown RAM type */ ! ErrorF("%s %s: %s: Unknown video memory type %d -- assuming 1 MB (unless specified)\n", ! XCONFIG_PROBED, vga256InfoRec.name, vga256InfoRec.chipset, ramtype); vga256InfoRec.videoRam = 1024; } } *************** *** 777,783 **** if (config & 0x80) vga256InfoRec.videoRam <<= 1; - #ifdef W32_SUPPORT /* Check for interleaving on W32i/p. */ if (et4000_type >= TYPE_ET4000W32I) { --- 804,809 ---- *************** *** 790,796 **** XCONFIG_PROBED, vga256InfoRec.name); } } - #endif } } --- 816,821 ---- *************** *** 843,850 **** switch(tseng_pcr->_device) { case PCI_CHIP_ET6000: ! et4000_type = TYPE_ET6000; break; case PCI_CHIP_ET4000_W32P_A: et4000_type = TYPE_ET4000W32Pa; break; --- 868,881 ---- switch(tseng_pcr->_device) { case PCI_CHIP_ET6000: ! if (tseng_pcr->_rev_id < 0x70) ! et4000_type = TYPE_ET6000; ! else ! et4000_type = TYPE_ET6100; break; + case PCI_CHIP_ET6300: + et4000_type = TYPE_ET6300; + break; case PCI_CHIP_ET4000_W32P_A: et4000_type = TYPE_ET4000W32Pa; break; *************** *** 873,879 **** if (ET4000AutoDetect()==FALSE) return(FALSE); } ! if (et4000_type >= TYPE_ET6000) ET6000InitVars(autodetect); ET4000EnterLeave(ENTER); --- 904,910 ---- if (ET4000AutoDetect()==FALSE) return(FALSE); } ! if (Is_ET6K) ET6000InitVars(autodetect); ET4000EnterLeave(ENTER); *************** *** 885,891 **** if (!vga256InfoRec.videoRam) TsengDetectMem(); ! #ifdef W32_SUPPORT /* * If more than 1MB of RAM is available on the W32i/p, use the * W32-specific banking function that can address 4MB. --- 916,923 ---- if (!vga256InfoRec.videoRam) TsengDetectMem(); ! tseng_bytesperpixel = vgaBitsPerPixel/8; ! /* * If more than 1MB of RAM is available on the W32i/p, use the * W32-specific banking function that can address 4MB. *************** *** 895,910 **** ET4000.ChipSetWrite= ET4000W32SetWrite; ET4000.ChipSetReadWrite = ET4000W32SetReadWrite; } - #endif /* * Check for RAMDAC type */ Check_Tseng_Ramdac(); ! tseng_init_clockscale(vgaBitsPerPixel/8); ! tseng_set_dacspeed(vgaBitsPerPixel/8); ! #ifdef USE_XAA /* * Linear mode and >8bpp mode handling. * --- 927,946 ---- ET4000.ChipSetWrite= ET4000W32SetWrite; ET4000.ChipSetReadWrite = ET4000W32SetReadWrite; } /* * Check for RAMDAC type */ Check_Tseng_Ramdac(); ! tseng_init_clockscale(); ! tseng_set_dacspeed(); ! /* ! * ... and system bus type ! */ ! TsengFindBusType(); ! ! #ifndef MONOVGA /* * Linear mode and >8bpp mode handling. * *************** *** 914,943 **** * unless of course it is overridden from XF86Config. */ if (CHIP_SUPPORTS_LINEAR) { - /* enable using option "linear" in XF86Config */ OFLG_SET(OPTION_LINEAR, &ET4000.ChipOptionFlags); } - else { - /* clear the option flag if it isn't supported */ - OFLG_CLR(OPTION_LINEAR, &vga256InfoRec.options); - } - - if (vgaBitsPerPixel > 8) { - if (!CHIP_SUPPORTS_LINEAR) { - FatalError("%s %s: A color depth of %d bits per pixel is not supported on this device.\n", - XCONFIG_PROBED, vga256InfoRec.name, vgaBitsPerPixel); - } - /* OK, so we can do > 8bpp. Force linear mode -- can't do banked at >8bpp */ - OFLG_SET(OPTION_LINEAR, &vga256InfoRec.options); - } ! if (OFLG_ISSET(OPTION_LINEAR, &vga256InfoRec.options)) { ! if (!ET4000LinMem(autodetect)) ! FatalError("%s %s: Linear memory mode not supported on this device.\n", ! XCONFIG_PROBED, vga256InfoRec.name); } ! /* what color depths can we handle? */ switch(TsengRamdacType) { case ET6000_DAC: --- 950,969 ---- * unless of course it is overridden from XF86Config. */ + if (vgaBitsPerPixel >= 8) { + + /* enable option "linear" in XF86Config */ if (CHIP_SUPPORTS_LINEAR) { OFLG_SET(OPTION_LINEAR, &ET4000.ChipOptionFlags); } ! /* check if linear memory is supported and check for a suitable MemBase */ ! /* for >8bpp, linear memory is _required_ */ ! if (OFLG_ISSET(OPTION_LINEAR, &vga256InfoRec.options) || (vgaBitsPerPixel > 8)) ! { ! ET4000LinMem(autodetect); } ! /* what color depths can we handle? */ switch(TsengRamdacType) { case ET6000_DAC: *************** *** 952,962 **** case ATT20C491_DAC: case ATT20C492_DAC: case ATT20C493_DAC: ET4000.ChipHas16bpp = TRUE; ET4000.ChipHas24bpp = TRUE; break; ! case CH8398_DAC: /* CH8398 seems to have trouble with "hibit" (MCLK/2) clocks at 24bpp */ ET4000.ChipHas16bpp = TRUE; break; case STG1700_DAC: /* STG1700 can't do packed 24bpp over a 16-bit bus */ ET4000.ChipHas16bpp = TRUE; --- 978,991 ---- case ATT20C491_DAC: case ATT20C492_DAC: case ATT20C493_DAC: + case ICS5301_DAC: + case MUSIC4910_DAC: ET4000.ChipHas16bpp = TRUE; ET4000.ChipHas24bpp = TRUE; break; ! case CH8398_DAC: ET4000.ChipHas16bpp = TRUE; + ET4000.ChipHas24bpp = TRUE; break; case STG1700_DAC: /* STG1700 can't do packed 24bpp over a 16-bit bus */ ET4000.ChipHas16bpp = TRUE; *************** *** 965,994 **** } /* ! * Acceleration is currently only supported on W32p or newer chips. W32i ! * doesn't work yet. */ ! if (et4000_type < TYPE_ET4000W32P) { ! /* this makes life easier in the rest of the server code */ ! OFLG_SET(OPTION_NOACCEL, &vga256InfoRec.options); } ! ! /* ! * Acceleration combined with linear mode doesn't work yet on chips before ! * W32p rev c. ! */ ! ! if (!OFLG_ISSET(OPTION_NOACCEL, &vga256InfoRec.options) ! && OFLG_ISSET(OPTION_LINEAR, &vga256InfoRec.options)) { ! if (et4000_type < TYPE_ET4000W32Pc) ! { ! ErrorF("%s %s: Acceleration disabled (not yet supported in linear mode).\n", ! XCONFIG_PROBED, vga256InfoRec.name); ! OFLG_SET(OPTION_NOACCEL, &vga256InfoRec.options); ! } } /* --- 994,1023 ---- } /* ! * Acceleration is only supported on W32 or newer chips. ! * ! * Also, some bus configurations only allow for a 1MB linear memory ! * aperture instead of the default 4M aperture used on all Tseng devices. ! * If acceleration is also enabled, you only get 512k + (with some aperture ! * tweaking) 2*128k for a total of max 768 kb of memory. This just isn't ! * worth having a lot of conditionals in the accelerator code (the ! * memory-mapped registers move to the top of the 1M aperture), so we ! * simply don't allow acceleration and linear mode combined on these cards. ! * */ ! if ( (et4000_type < TYPE_ET4000W32) || (tseng_linmem_1meg && ET4000.ChipUseLinearAddressing) ) { ! tseng_use_ACL = FALSE; } ! else { ! /* enable acceleration-related options */ ! OFLG_SET(OPTION_NOACCEL, &ET4000.ChipOptionFlags); ! OFLG_SET(OPTION_PCI_RETRY, &ET4000.ChipOptionFlags); ! OFLG_SET(OPTION_SHOWCACHE, &ET4000.ChipOptionFlags); ! ! tseng_use_ACL = !OFLG_ISSET(OPTION_NOACCEL, &vga256InfoRec.options); } /* *************** *** 999,1095 **** { \ if (vga256InfoRec.videoRam > (m)) \ { \ ! ErrorF("%s %s: Only %d kb of memory can be used in %s.\n", \ XCONFIG_PROBED, vga256InfoRec.name, (m), (reason)); \ vga256InfoRec.videoRam = (m); \ } \ } ! /* This is from experience, and not from the data book. Should get fixed some day */ ! if ( (et4000_type >= TYPE_ET4000W32P) && (et4000_type < TYPE_ET4000W32Pc) ! && OFLG_ISSET(OPTION_LINEAR, &vga256InfoRec.options) ) { ! TSENG_MEMLIMIT(1024, "linear memory mode on W32p rev a & b"); } ! /* more differentiation could be used later, but it'll do for now */ ! if ( (et4000_type < TYPE_ET6000) ! && OFLG_ISSET(OPTION_LINEAR, &vga256InfoRec.options) ! && !OFLG_ISSET(OPTION_NOACCEL, &vga256InfoRec.options) ) { ! TSENG_MEMLIMIT(2048, "accelerated mode with linear memory mapping on any W32"); ! } ! #ifdef KMG_FORGOT_WHY_THIS_WAS ! if ( (et4000_type < TYPE_ET6000) ! && !OFLG_ISSET(OPTION_LINEAR, &vga256InfoRec.options) ! && !OFLG_ISSET(OPTION_NOACCEL, &vga256InfoRec.options) ) ! { ! TSENG_MEMLIMIT(4096-516, "banked accelerated mode on any W32"); ! } ! #endif ! if ( !OFLG_ISSET(OPTION_NOACCEL, &vga256InfoRec.options) ! && OFLG_ISSET(OPTION_LINEAR, &vga256InfoRec.options) ) ! { ! TSENG_MEMLIMIT(4096-8, "accelerated mode with linear memory mapping on any Tseng card"); ! } ! TSENG_MEMLIMIT(4096, "Tseng cards"); ! ! /* ! * Acceleration requires 1kb scratch buffer memory. ! */ ! ! if (!OFLG_ISSET(OPTION_NOACCEL, &vga256InfoRec.options)) ! { ! ErrorF("%s %s: Reserving 1kb of video memory for accelerator.\n", ! XCONFIG_PROBED, vga256InfoRec.name); ! vga256InfoRec.videoRam -= 1; ! scratchVidBase = vga256InfoRec.videoRam * 1024; } ! /* Hardware Cursor support */ #ifdef W32_HW_CURSOR_FIXED if (et4000_type >= TYPE_ET4000W32P) #else ! if (et4000_type >= TYPE_ET6000) #endif { ! /* Set HW Cursor option valid */ OFLG_SET(OPTION_HW_CURSOR, &ET4000.ChipOptionFlags); } ! if (OFLG_ISSET(OPTION_HW_CURSOR, &vga256InfoRec.options)) ! { ! #ifdef W32_HW_CURSOR_FIXED ! if (et4000_type >= TYPE_ET4000W32P) ! #else ! if (et4000_type >= TYPE_ET6000) ! #endif ! { ! ErrorF("%s %s: Reserving 1kb of video memory for hardware cursor.\n", ! XCONFIG_PROBED, vga256InfoRec.name); ! vga256InfoRec.videoRam -= 1; /* 1kb reserved for hardware cursor */ ! tsengCursorAddress = vga256InfoRec.videoRam * 1024; ! } ! else /* clear illegal option */ ! OFLG_CLR(OPTION_HW_CURSOR, &vga256InfoRec.options); } - - /* Set PCI_RETRY option valid */ - OFLG_SET(OPTION_PCI_RETRY, &ET4000.ChipOptionFlags); ! OFLG_SET(OPTION_NOACCEL, &ET4000.ChipOptionFlags); - #endif - - #ifdef MONOVGA - OFLG_CLR(OPTION_HW_CURSOR, &vga256InfoRec.options); - OFLG_CLR(OPTION_LINEAR, &vga256InfoRec.options); - OFLG_SET(OPTION_NOACCEL, &vga256InfoRec.options); - #endif - if (et4000_type < TYPE_ET6000) { /* Initialize option flags allowed for this driver */ --- 1028,1091 ---- { \ if (vga256InfoRec.videoRam > (m)) \ { \ ! ErrorF("%s %s: Only %d kb of memory can be used %s.\n", \ XCONFIG_PROBED, vga256InfoRec.name, (m), (reason)); \ vga256InfoRec.videoRam = (m); \ } \ } ! if(ET4000.ChipUseLinearAddressing && tseng_linmem_1meg) { ! TSENG_MEMLIMIT(1024, "in linear mode on this VGA board/bus configuration"); } ! if (tseng_use_ACL && ET4000.ChipUseLinearAddressing) { ! if (Is_W32_any) ! { ! /* <= W32p_ab : ! * 2 MB direct access + 2*512kb via apertures MBP0 and MBP1 ! * == W32p_cd : ! * 2*1MB via apertures MBP0 and MBP1 ! */ ! if (Is_W32p_cd) ! TSENG_MEMLIMIT(2048, "in linear + accelerated mode on W32p rev c and d"); ! TSENG_MEMLIMIT(2048+1024, "in linear + accelerated mode on W32/W32i/W32p"); ! /* upper 516kb of 4MB linear map used for "externally mapped registers" */ ! TSENG_MEMLIMIT(4096-516, "in linear + accelerated mode on W32/W32i/W32p"); ! } ! if (Is_ET6K) ! { ! /* upper 8kb used for externally mapped and memory mapped registers */ ! TSENG_MEMLIMIT(4096-8, "in linear + accelerated mode on ET6000/6100/6300"); ! } } ! TSENG_MEMLIMIT(4096, "on any Tseng card"); ! ! /* Hardware Cursor support */ #ifdef W32_HW_CURSOR_FIXED if (et4000_type >= TYPE_ET4000W32P) #else ! if (Is_ET6K) #endif { ! /* Set HW Cursor option valid */ OFLG_SET(OPTION_HW_CURSOR, &ET4000.ChipOptionFlags); } ! } /* if (vgaBitsPerPixel >= 8) */ ! else { ! OFLG_CLR(OPTION_HW_CURSOR, &vga256InfoRec.options); ! ET4000.ChipUseLinearAddressing = FALSE; ! tseng_use_ACL = FALSE; } ! #endif /* MONOVGA */ if (et4000_type < TYPE_ET6000) { /* Initialize option flags allowed for this driver */ *************** *** 1096,1102 **** OFLG_SET(OPTION_LEGEND, &ET4000.ChipOptionFlags); OFLG_SET(OPTION_HIBIT_HIGH, &ET4000.ChipOptionFlags); OFLG_SET(OPTION_HIBIT_LOW, &ET4000.ChipOptionFlags); ! #ifndef MONOVGA OFLG_SET(OPTION_PCI_BURST_ON, &ET4000.ChipOptionFlags); OFLG_SET(OPTION_PCI_BURST_OFF, &ET4000.ChipOptionFlags); OFLG_SET(OPTION_W32_INTERLEAVE_ON, &ET4000.ChipOptionFlags); --- 1092,1098 ---- OFLG_SET(OPTION_LEGEND, &ET4000.ChipOptionFlags); OFLG_SET(OPTION_HIBIT_HIGH, &ET4000.ChipOptionFlags); OFLG_SET(OPTION_HIBIT_LOW, &ET4000.ChipOptionFlags); ! if (vgaBitsPerPixel >= 8) { OFLG_SET(OPTION_PCI_BURST_ON, &ET4000.ChipOptionFlags); OFLG_SET(OPTION_PCI_BURST_OFF, &ET4000.ChipOptionFlags); OFLG_SET(OPTION_W32_INTERLEAVE_ON, &ET4000.ChipOptionFlags); *************** *** 1103,1109 **** OFLG_SET(OPTION_W32_INTERLEAVE_OFF, &ET4000.ChipOptionFlags); OFLG_SET(OPTION_SLOW_DRAM, &ET4000.ChipOptionFlags); OFLG_SET(OPTION_FAST_DRAM, &ET4000.ChipOptionFlags); ! #endif /* * because of some problems with W32 cards, SLOW_DRAM is _always_ enabled --- 1099,1105 ---- OFLG_SET(OPTION_W32_INTERLEAVE_OFF, &ET4000.ChipOptionFlags); OFLG_SET(OPTION_SLOW_DRAM, &ET4000.ChipOptionFlags); OFLG_SET(OPTION_FAST_DRAM, &ET4000.ChipOptionFlags); ! } /* * because of some problems with W32 cards, SLOW_DRAM is _always_ enabled *************** *** 1116,1139 **** OFLG_SET(OPTION_SLOW_DRAM, &vga256InfoRec.options); } - #ifdef W32_SUPPORT if (OFLG_ISSET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions)) { ! if (OFLG_ISSET(CLOCK_OPTION_ICS5341, &vga256InfoRec.clockOptions)) { ! ClockSelect = Tseng_ICS5341ClockSelect; numClocks = 3; } ! else if (OFLG_ISSET(CLOCK_OPTION_STG1703, &vga256InfoRec.clockOptions)) { ClockSelect = Tseng_STG1703ClockSelect; numClocks = 3; } ! else if (OFLG_ISSET(CLOCK_OPTION_ICD2061A, &vga256InfoRec.clockOptions)) { ClockSelect = Tseng_ICD2061AClockSelect; numClocks = 3; } else { ErrorF("Unsuported programmable Clock chip.\n"); --- 1112,1139 ---- OFLG_SET(OPTION_SLOW_DRAM, &vga256InfoRec.options); } if (OFLG_ISSET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions)) { ! if (Gendac_programmable_clock) { ! ClockSelect = Tseng_GenDACClockSelect; numClocks = 3; } ! else if (STG170x_programmable_clock) { ClockSelect = Tseng_STG1703ClockSelect; numClocks = 3; } ! else if (ICD2061a_programmable_clock) { ClockSelect = Tseng_ICD2061AClockSelect; numClocks = 3; } + else if (CH8398_programmable_clock) + { + ClockSelect = Tseng_ET4000ClockSelect; + numClocks = 3; + } else { ErrorF("Unsuported programmable Clock chip.\n"); *************** *** 1142,1148 **** } } else - #endif { if (OFLG_ISSET(OPTION_LEGEND, &vga256InfoRec.options)) { --- 1142,1147 ---- *************** *** 1154,1163 **** ClockSelect = Tseng_ET4000ClockSelect; /* * The CH8398 RAMDAC uses CS3 for register selection (RS2), not for clock selection. ! * The ICS5341 RAMDAC only has 8 clocks. Together with MCLK/2, that's 16 clocks. */ ! if ( ( et4000_type > TYPE_ET4000 ) && (TsengRamdacType != CH8398_DAC) ! && (TsengRamdacType != ICS5341_DAC) ) numClocks = 32; else numClocks = 16; --- 1153,1162 ---- ClockSelect = Tseng_ET4000ClockSelect; /* * The CH8398 RAMDAC uses CS3 for register selection (RS2), not for clock selection. ! * The GenDAC family only has 8 clocks. Together with MCLK/2, that's 16 clocks. */ ! if ( ( et4000_type > TYPE_ET4000 ) ! && (!DAC_is_GenDAC) && (TsengRamdacType != CH8398_DAC) ) numClocks = 32; else numClocks = 16; *************** *** 1184,1221 **** ErrorF("%s %s: ET4000: Initial hibit state: %s\n", XCONFIG_PROBED, vga256InfoRec.name, tseng_save_divide & 0x40 ? "high" : "low"); } - } /* et4000_type < ET6000 */ - - #ifndef MONOVGA /* Save initial RCConf value */ outb(vgaIOBase + 4, 0x32); initialRCConf = inb(vgaIOBase + 5); ! #ifdef W32_SUPPORT if (et4000_type > TYPE_ET4000) { /* Save initial Auxctrl (CRTC 0x34) value */ outb(vgaIOBase + 4, 0x34); initialCompatibility = inb(vgaIOBase + 5); - /* Save initial VSConf1 (CRTC 0x36) value */ - outb(vgaIOBase + 4, 0x36); initialVSConf1 = inb(vgaIOBase + 5); - /* Save initial VSConf2 (CRTC 0x37) value */ - outb(vgaIOBase + 4, 0x37); initialVSConf2 = inb(vgaIOBase + 5); if (et4000_type < TYPE_ET6000) { /* Save initial IMAPortCtrl value */ outb(0x217a, 0xF7); initialIMAPortCtrl = inb(0x217b); } } ! #endif ! #endif ! if (et4000_type >= TYPE_ET6000) { int tmp = inb(ET6Kbase+0x67); initialET6KMemBase = inb(ET6Kbase+0x13); initialET6KPerfContr = inb(ET6Kbase+0x41); outb(ET6Kbase+0x67, 10); initialET6KMclkM = inb(ET6Kbase+0x69); initialET6KMclkN = inb(ET6Kbase+0x69); outb(ET6Kbase+0x67, tmp); ! ErrorF("%s %s: ET6000: MClk: %3.2f MHz\n", XCONFIG_PROBED, ! vga256InfoRec.name, gendacMNToClock(initialET6KMclkM, initialET6KMclkN)/1000.0); } if (!OFLG_ISSET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions)) { --- 1183,1223 ---- ErrorF("%s %s: ET4000: Initial hibit state: %s\n", XCONFIG_PROBED, vga256InfoRec.name, tseng_save_divide & 0x40 ? "high" : "low"); } /* Save initial RCConf value */ outb(vgaIOBase + 4, 0x32); initialRCConf = inb(vgaIOBase + 5); ! } /* et4000_type < ET6000 */ ! if (et4000_type > TYPE_ET4000) { /* Save initial Auxctrl (CRTC 0x34) value */ outb(vgaIOBase + 4, 0x34); initialCompatibility = inb(vgaIOBase + 5); if (et4000_type < TYPE_ET6000) { + /* Save initial VSConf1 (CRTC 0x36) value */ + outb(vgaIOBase + 4, 0x36); initialVSConf1 = inb(vgaIOBase + 5); + /* Save initial VSConf2 (CRTC 0x37) value */ + outb(vgaIOBase + 4, 0x37); initialVSConf2 = inb(vgaIOBase + 5); /* Save initial IMAPortCtrl value */ outb(0x217a, 0xF7); initialIMAPortCtrl = inb(0x217b); } } ! if (Is_ET6K) { int tmp = inb(ET6Kbase+0x67); initialET6KMemBase = inb(ET6Kbase+0x13); initialET6KPerfContr = inb(ET6Kbase+0x41); + initialET6KRasCas = inb(ET6Kbase+0x44); + initialET6KDispFeat = inb(ET6Kbase+0x46); outb(ET6Kbase+0x67, 10); initialET6KMclkM = inb(ET6Kbase+0x69); initialET6KMclkN = inb(ET6Kbase+0x69); outb(ET6Kbase+0x67, tmp); ! ErrorF("%s %s: %s: MClk: %3.2f MHz, R/C: 0x%x\n", XCONFIG_PROBED, ! vga256InfoRec.name, vga256InfoRec.chipset, ! gendacMNToClock(initialET6KMclkM, initialET6KMclkN)/1000.0, ! initialET6KRasCas); ! OFLG_SET(OPTION_SLOW_DRAM, &ET4000.ChipOptionFlags); ! OFLG_SET(OPTION_MED_DRAM, &ET4000.ChipOptionFlags); ! OFLG_SET(OPTION_FAST_DRAM, &ET4000.ChipOptionFlags); } if (!OFLG_ISSET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions)) { *************** *** 1223,1233 **** } vga256InfoRec.bankedMono = TRUE; - #ifndef MONOVGA #ifdef XFreeXDGA ! vga256InfoRec.directMode = XF86DGADirectPresent; #endif - #endif #ifdef DPMSExtension /* Support for DPMS, the ET4000W32Pc and newer uses a different and --- 1225,1234 ---- } vga256InfoRec.bankedMono = TRUE; #ifdef XFreeXDGA ! if (vgaBitsPerPixel >= 8) ! vga256InfoRec.directMode = XF86DGADirectPresent; #endif #ifdef DPMSExtension /* Support for DPMS, the ET4000W32Pc and newer uses a different and *************** *** 1254,1260 **** --- 1255,1264 ---- { #ifndef MONOVGA int useSpeedUp; + int FBmem = (vga256InfoRec.virtualY * vga256InfoRec.displayWidth * tseng_bytesperpixel)/1024; + if (vgaBitsPerPixel < 8) return; + if (xf86Verbose && ET4000.ChipUseLinearAddressing) ErrorF("%s %s: %s: Using linear framebuffer at 0x%08X.\n", XCONFIG_PROBED, vga256InfoRec.name, *************** *** 1302,1343 **** } } ! /* Hardware cursor setup */ ! if (OFLG_ISSET(OPTION_HW_CURSOR, &vga256InfoRec.options)) { ! tsengCursorWidth = 64; ! tsengCursorHeight = 64; ! vgaHWCursor.Initialized = TRUE; ! vgaHWCursor.Init = TsengCursorInit; ! vgaHWCursor.Restore = TsengRestoreCursor; ! vgaHWCursor.Warp = TsengWarpCursor; ! vgaHWCursor.QueryBestSize = TsengQueryBestSize; ! if (xf86Verbose) ! ErrorF("%s %s: %s: Using hardware cursor\n", ! XCONFIG_PROBED, vga256InfoRec.name, ! vga256InfoRec.chipset); } if (OFLG_ISSET(OPTION_PCI_RETRY, &vga256InfoRec.options)) { ErrorF("%s %s: Using PCI retrys.\n",XCONFIG_PROBED, vga256InfoRec.name); ! Use_Pci_Retry = 1; } ! #ifdef USE_XAA ! if (vgaBitsPerPixel >= 8) { ! if (OFLG_ISSET(OPTION_NOACCEL, &vga256InfoRec.options)) { ! Use_ACL = FALSE; } - else - { - /* initialize the XAA interface software */ - /* TsengAccelInit(); - This relies on variables that are setup later, so it's called there */ - Use_ACL = TRUE; - } - } - #endif #endif /* MONOVGA */ } --- 1306,1385 ---- } } ! /* Hardware cursor setup */ ! if (OFLG_ISSET(OPTION_HW_CURSOR, &vga256InfoRec.options) && ! #ifdef W32_HW_CURSOR_FIXED ! (et4000_type >= TYPE_ET4000W32P) ! #else ! (Is_ET6K) ! #endif ! ) ! { ! if ((vga256InfoRec.videoRam - FBmem) < 1) ! { ! ErrorF("%s %s: Hardware cursor disabled. It requires 1kb of free video memory\n", ! XCONFIG_PROBED, vga256InfoRec.name); ! OFLG_CLR(OPTION_HW_CURSOR, &vga256InfoRec.options); ! } ! else ! { ! vga256InfoRec.videoRam -= 1; /* 1kb reserved for hardware cursor */ ! tsengCursorAddress = vga256InfoRec.videoRam * 1024; ! ! tsengCursorWidth = 64; ! tsengCursorHeight = 64; ! vgaHWCursor.Initialized = TRUE; ! vgaHWCursor.Init = TsengCursorInit; ! vgaHWCursor.Restore = TsengRestoreCursor; ! vgaHWCursor.Warp = TsengWarpCursor; ! vgaHWCursor.QueryBestSize = TsengQueryBestSize; ! if (xf86Verbose) ! ErrorF("%s %s: %s: Using hardware cursor\n", ! XCONFIG_PROBED, vga256InfoRec.name, vga256InfoRec.chipset); ! } } if (OFLG_ISSET(OPTION_PCI_RETRY, &vga256InfoRec.options)) { ErrorF("%s %s: Using PCI retrys.\n",XCONFIG_PROBED, vga256InfoRec.name); ! tseng_use_PCI_Retry = 1; } ! if ( (vgaBitsPerPixel >= 8) && (tseng_use_ACL) ) { ! if ((vga256InfoRec.videoRam - FBmem) < 1) ! { ! ErrorF("%s %s: Acceleration disabled. It requires AT LEAST 1kb of free video memory\n", ! XCONFIG_PROBED, vga256InfoRec.name); ! tseng_use_ACL = FALSE; ! } ! else ! { ! vga256InfoRec.videoRam -= 1; ! tsengScratchVidBase = vga256InfoRec.videoRam * 1024; ! /* initialize the XAA interface software */ ! /* TsengAccelInit(); ! This relies on variables that are setup later, so it's called there */ ! } ! ! /* ! * XAA ImageWrite support needs two entire line buffers + 3 and rounded ! * up to the next DWORD boundary. ! */ ! if (tseng_use_ACL) ! { ! int req_ram = (vga256InfoRec.displayWidth * tseng_bytesperpixel + 6) * 2; ! req_ram = (req_ram + 1023) / 1024; /* in kb */ ! if ((vga256InfoRec.videoRam - FBmem) > req_ram) ! { ! vga256InfoRec.videoRam -= req_ram; ! tsengImageWriteBase = vga256InfoRec.videoRam * 1024; ! ErrorF("%s %s: Using %dkb of unused display memory for extra acceleration functions.\n", ! XCONFIG_PROBED, vga256InfoRec.name, req_ram); ! } ! } ! } #endif /* MONOVGA */ } *************** *** 1355,1364 **** #ifndef MONOVGA #ifdef XFreeXDGA ! if (vga256InfoRec.directMode&XF86DGADirectGraphics && !enter) { ! if (vgaHWCursor.Initialized == TRUE) ! TsengHideCursor(); ! return; } #endif #endif --- 1397,1408 ---- #ifndef MONOVGA #ifdef XFreeXDGA ! if (vgaBitsPerPixel >= 8) { ! if (vga256InfoRec.directMode&XF86DGADirectGraphics && !enter) { ! if (vgaHWCursor.Initialized == TRUE) ! TsengHideCursor(); ! return; ! } } #endif #endif *************** *** 1398,1415 **** { unsigned char i; - #ifndef W32_ACCEL_SUPPORT vgaProtect(TRUE); - #endif outb(0x3CD, 0x00); /* segment select bits 0..3 */ if (et4000_type > TYPE_ET4000) outb(0x3CB, 0x00); /* segment select bits 4,5 */ ! #ifdef W32_SUPPORT ! if (TsengRamdacType == ICS5341_DAC) { ! /* Restore ICS 5341 GenDAC Command and PLL registers */ outb(vgaIOBase + 4, 0x31); i = inb(vgaIOBase + 5); outb(vgaIOBase + 5, i | 0x40); --- 1442,1456 ---- { unsigned char i; vgaProtect(TRUE); outb(0x3CD, 0x00); /* segment select bits 0..3 */ if (et4000_type > TYPE_ET4000) outb(0x3CB, 0x00); /* segment select bits 4,5 */ ! if (DAC_is_GenDAC) { ! /* Restore GenDAC Command and PLL registers */ outb(vgaIOBase + 4, 0x31); i = inb(vgaIOBase + 5); outb(vgaIOBase + 5, i | 0x40); *************** *** 1416,1427 **** outb(0x3c6, restore->gendac.cmd_reg); /* Enhanced command register*/ ! if ( (OFLG_ISSET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions)) && ! (OFLG_ISSET(CLOCK_OPTION_ICS5341, &vga256InfoRec.clockOptions)) ) { outb(0x3c8, 2); /* index to f2 reg */ outb(0x3c9, restore->gendac.PLL_f2_M); /* f2 PLL M divider */ outb(0x3c9, restore->gendac.PLL_f2_N); /* f2 PLL N1/N2 divider */ outb(0x3c8, 0x0e); /* index to PLL control */ outb(0x3c9, restore->gendac.PLL_ctrl); /* PLL control */ outb(0x3c8, restore->gendac.PLL_w_idx); /* PLL write index */ --- 1457,1473 ---- outb(0x3c6, restore->gendac.cmd_reg); /* Enhanced command register*/ ! if (Gendac_programmable_clock) { outb(0x3c8, 2); /* index to f2 reg */ outb(0x3c9, restore->gendac.PLL_f2_M); /* f2 PLL M divider */ outb(0x3c9, restore->gendac.PLL_f2_N); /* f2 PLL N1/N2 divider */ + if (vga256InfoRec.MemClk > 0) { + outb(0x3c7, 10); /* index to Mclk reg */ + outb(0x3c9, restore->MClkM); /* MClk PLL M divider */ + outb(0x3c9, restore->MClkN); /* MClk PLL N1/N2 divider */ + } + outb(0x3c8, 0x0e); /* index to PLL control */ outb(0x3c9, restore->gendac.PLL_ctrl); /* PLL control */ outb(0x3c8, restore->gendac.PLL_w_idx); /* PLL write index */ *************** *** 1431,1438 **** outb(vgaIOBase + 5, i & ~0x40); } ! if ( (TsengRamdacType == STG1702_DAC) || (TsengRamdacType == STG1703_DAC) ! || (TsengRamdacType == STG1700_DAC) ) { /* Restore STG 170x GenDAC Command and PLL registers * we share one data structure with the gendac code, so the names --- 1477,1483 ---- outb(vgaIOBase + 5, i & ~0x40); } ! if (DAC_is_STG170x) { /* Restore STG 170x GenDAC Command and PLL registers * we share one data structure with the gendac code, so the names *************** *** 1439,1452 **** * are not too good. */ ! if ( (OFLG_ISSET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions)) && ! (OFLG_ISSET(CLOCK_OPTION_STG1703, &vga256InfoRec.clockOptions)) ) { STG1703setIndex(0x24,restore->gendac.PLL_f2_M); outb(0x3c6,restore->gendac.PLL_f2_N); /* use autoincrement */ } ! STG1703setIndex(0x03,restore->gendac.PLL_ctrl);/* write same value to */ ! outb(0x3c6,restore->gendac.PLL_ctrl); /* primary and secondary ! * pixel mode select register */ STG1703magic(0); xf86dactopel(); xf86setdaccomm(restore->gendac.cmd_reg); /* write enh command reg */ --- 1484,1498 ---- * are not too good. */ ! if (STG170x_programmable_clock) { STG1703setIndex(0x24,restore->gendac.PLL_f2_M); outb(0x3c6,restore->gendac.PLL_f2_N); /* use autoincrement */ } ! STG1703setIndex(0x03,restore->gendac.PLL_ctrl);/* primary pixel mode */ ! outb(0x3c6,restore->gendac.PLL_ctrl); /* secondary pixel mode */ ! outb(0x3c6,restore->gendac.timingctrl); /* pipeline timing control */ ! usleep(500); /* 500 usec PLL settling time required */ ! STG1703magic(0); xf86dactopel(); xf86setdaccomm(restore->gendac.cmd_reg); /* write enh command reg */ *************** *** 1456,1466 **** xf86dactopel(); xf86setdaccomm(restore->gendac.cmd_reg); } - #endif ! if (OFLG_ISSET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions)) ! { ! if (OFLG_ISSET(CLOCK_OPTION_ET6000, &vga256InfoRec.clockOptions)) { /* Restore ET6000 CLKDAC PLL registers */ i = inb(ET6Kbase+0x67); /* remember old CLKDAC index register pointer */ --- 1502,1531 ---- xf86dactopel(); xf86setdaccomm(restore->gendac.cmd_reg); } ! if (CH8398_programmable_clock) { ! outb(vgaIOBase + 4, 0x31); ! i = inb(vgaIOBase + 5); ! outb(vgaIOBase + 5, i | (1<<6)); /* Set RS2 through CS3 */ ! /* We are in ClockRAM mode 0x3c7 = CRA, 0x3c8 = CWA, 0x3c9 = CDR */ ! outb(0x3c7,restore->gendac.PLL_r_idx); ! outb(0x3c8,10); /* 2|((tseng_save_divide & 0x40)>>3)); yuck */ ! outb(0x3c9,restore->gendac.PLL_f2_N); ! outb(0x3c9,restore->gendac.PLL_f2_M); ! outb(0x3c8,restore->gendac.PLL_w_idx); ! usleep(500); ! inb(0x3c7); /* reset sequence */ ! inb(0x3c8); /* loop to Clock Select Register */ ! inb(0x3c8); ! inb(0x3c8); ! inb(0x3c8); ! outb(0x3c8,restore->gendac.PLL_ctrl); ! outb(vgaIOBase + 4, 0x31); ! outb(vgaIOBase + 5, i); ! /* If CS3 wasn't set before then we are outside ClockRAM mode */ ! } ! ! if (ET6000_programmable_clock) { /* Restore ET6000 CLKDAC PLL registers */ i = inb(ET6Kbase+0x67); /* remember old CLKDAC index register pointer */ *************** *** 1468,1494 **** outb(ET6Kbase+0x69, restore->gendac.PLL_f2_M); outb(ET6Kbase+0x69, restore->gendac.PLL_f2_N); /* set MClk values if needed, but don't touch them if not needed */ ! #ifdef ALLOW_ET6K_FAST_DRAM ! if (OFLG_ISSET(OPTION_FAST_DRAM, &vga256InfoRec.options)) { outb(ET6Kbase+0x67, 10); ! outb(ET6Kbase+0x69, restore->ET6KMclkM); ! outb(ET6Kbase+0x69, restore->ET6KMclkN); } - #endif /* restore old index register */ outb(ET6Kbase+0x67, i); } - } if (DAC_IS_ATT49x) xf86setdaccomm(restore->ATTdac_cmd); ! if (et4000_type >= TYPE_ET6000) { outb(ET6Kbase+0x13, restore->ET6KMemBase); outb(ET6Kbase+0x40, restore->ET6KMMAPCtrl); outb(ET6Kbase+0x58, restore->ET6KVidCtrl1); outb(ET6Kbase+0x41, restore->ET6KPerfContr); outb(ET6Kbase+0x46, restore->ET6KDispFeat); } --- 1533,1557 ---- outb(ET6Kbase+0x69, restore->gendac.PLL_f2_M); outb(ET6Kbase+0x69, restore->gendac.PLL_f2_N); /* set MClk values if needed, but don't touch them if not needed */ ! if (vga256InfoRec.MemClk > 0) { outb(ET6Kbase+0x67, 10); ! outb(ET6Kbase+0x69, restore->MClkM); ! outb(ET6Kbase+0x69, restore->MClkN); } /* restore old index register */ outb(ET6Kbase+0x67, i); } if (DAC_IS_ATT49x) xf86setdaccomm(restore->ATTdac_cmd); ! if (Is_ET6K) { outb(ET6Kbase+0x13, restore->ET6KMemBase); outb(ET6Kbase+0x40, restore->ET6KMMAPCtrl); outb(ET6Kbase+0x58, restore->ET6KVidCtrl1); outb(ET6Kbase+0x41, restore->ET6KPerfContr); + outb(ET6Kbase+0x44, restore->ET6KRasCas); outb(ET6Kbase+0x46, restore->ET6KDispFeat); } *************** *** 1506,1514 **** if (restore->std.NoClock >= 0) outw(vgaIOBase + 4, (restore->Compatibility << 8) | 0x34); outw(vgaIOBase + 4, (restore->OverflowHigh << 8) | 0x35); ! #ifndef MONOVGA ! #ifdef W32_SUPPORT ! if (et4000_type > TYPE_ET4000) { outw(vgaIOBase + 4, (restore->VSConf1 << 8) | 0x36); /* --- 1569,1575 ---- if (restore->std.NoClock >= 0) outw(vgaIOBase + 4, (restore->Compatibility << 8) | 0x34); outw(vgaIOBase + 4, (restore->OverflowHigh << 8) | 0x35); ! if (Is_W32_any) { outw(vgaIOBase + 4, (restore->VSConf1 << 8) | 0x36); /* *************** *** 1518,1534 **** */ save_VSConf1 = restore->VSConf1; outw(vgaIOBase + 4, (restore->VSConf2 << 8) | 0x37); ! if (et4000_type < TYPE_ET6000) ! { ! outw(0x217a, (restore->IMAPortCtrl << 8) | 0xF7); ! } } ! #endif #ifdef WHY_WOULD_YOU_RESTRICT_THAT_TO_THIS_OPTION if (OFLG_ISSET(OPTION_FAST_DRAM, &vga256InfoRec.options)) #endif outw(vgaIOBase + 4, (restore->RCConf << 8) | 0x32); ! #endif outb(0x3CD, restore->SegSel1); if (et4000_type > TYPE_ET4000) outb(0x3CB, restore->SegSel2); --- 1579,1592 ---- */ save_VSConf1 = restore->VSConf1; outw(vgaIOBase + 4, (restore->VSConf2 << 8) | 0x37); ! outw(0x217a, (restore->IMAPortCtrl << 8) | 0xF7); } ! if (et4000_type < TYPE_ET6000) { #ifdef WHY_WOULD_YOU_RESTRICT_THAT_TO_THIS_OPTION if (OFLG_ISSET(OPTION_FAST_DRAM, &vga256InfoRec.options)) #endif outw(vgaIOBase + 4, (restore->RCConf << 8) | 0x32); ! } outb(0x3CD, restore->SegSel1); if (et4000_type > TYPE_ET4000) outb(0x3CB, restore->SegSel2); *************** *** 1543,1561 **** { vgaProtect(TRUE); (ClockSelect)(restore->std.NoClock); - #ifdef W32_ACCEL_SUPPORT - vgaProtect(FALSE); - #endif } ! #ifdef USE_XAA ! if (Use_ACL & (restore->std.Attribute[16] & 1)) /* are we going to graphics mode? */ tseng_init_acl(); /* initialize acceleration hardware */ #endif - #ifndef W32_ACCEL_SUPPORT vgaProtect(FALSE); - #endif } --- 1601,1614 ---- { vgaProtect(TRUE); (ClockSelect)(restore->std.NoClock); } ! #ifndef MONOVGA ! if (tseng_use_ACL & (restore->std.Attribute[16] & 1)) /* are we going to graphics mode? */ tseng_init_acl(); /* initialize acceleration hardware */ #endif vgaProtect(FALSE); } *************** *** 1593,1636 **** outb(vgaIOBase + 4, 0x33); save->ExtStart = inb(vgaIOBase + 5); outb(vgaIOBase + 4, 0x35); save->OverflowHigh = inb(vgaIOBase + 5); ! #ifdef W32_SUPPORT ! if (et4000_type > TYPE_ET4000) { outb(vgaIOBase + 4, 0x36); save->VSConf1 = inb(vgaIOBase + 5); outb(vgaIOBase + 4, 0x37); save->VSConf2 = inb(vgaIOBase + 5); ! if (et4000_type < TYPE_ET6000) ! { ! outb(0x217a, 0xF7); save->IMAPortCtrl = inb(0x217b); ! } } ! #endif ! #ifndef MONOVGA #ifdef WHY_WOULD_YOU_RESTRICT_THAT_TO_THIS_OPTION if (OFLG_ISSET(OPTION_FAST_DRAM, &vga256InfoRec.options)) #endif outb(vgaIOBase + 4, 0x32); save->RCConf = inb(vgaIOBase + 5); ! #endif outb(0x3C4, 6); save->StateControl = inb(0x3C5); outb(0x3C4, 7); save->AuxillaryMode = inb(0x3C5); save->AuxillaryMode |= 0x14; temp = inb(vgaIOBase + 0x0A); /* reset flip-flop */ outb(0x3C0,0x36); save->Misc = inb(0x3C1); outb(0x3C0, save->Misc); ! #ifdef W32_SUPPORT ! if (TsengRamdacType == ICS5341_DAC) { ! /* Save ICS 5341 GenDAC Command and PLL registers */ outb(vgaIOBase + 4, 0x31); temp = inb(vgaIOBase + 5); outb(vgaIOBase + 5, temp | 0x40); save->gendac.cmd_reg = inb(0x3c6); /* Enhanced command register */ ! if ( (OFLG_ISSET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions)) && ! (OFLG_ISSET(CLOCK_OPTION_ICS5341, &vga256InfoRec.clockOptions)) ) { save->gendac.PLL_w_idx = inb(0x3c8); /* PLL write index */ save->gendac.PLL_r_idx = inb(0x3c7); /* PLL read index */ outb(0x3c7, 2); /* index to f2 reg */ save->gendac.PLL_f2_M = inb(0x3c9); /* f2 PLL M divider */ save->gendac.PLL_f2_N = inb(0x3c9); /* f2 PLL N1/N2 divider */ outb(0x3c7, 0x0e); /* index to PLL control */ save->gendac.PLL_ctrl = inb(0x3c9); /* PLL control */ } --- 1646,1685 ---- outb(vgaIOBase + 4, 0x33); save->ExtStart = inb(vgaIOBase + 5); outb(vgaIOBase + 4, 0x35); save->OverflowHigh = inb(vgaIOBase + 5); ! if (Is_W32_any) { outb(vgaIOBase + 4, 0x36); save->VSConf1 = inb(vgaIOBase + 5); outb(vgaIOBase + 4, 0x37); save->VSConf2 = inb(vgaIOBase + 5); ! outb(0x217a, 0xF7); save->IMAPortCtrl = inb(0x217b); } ! if (et4000_type < TYPE_ET6000) { #ifdef WHY_WOULD_YOU_RESTRICT_THAT_TO_THIS_OPTION if (OFLG_ISSET(OPTION_FAST_DRAM, &vga256InfoRec.options)) #endif outb(vgaIOBase + 4, 0x32); save->RCConf = inb(vgaIOBase + 5); ! } outb(0x3C4, 6); save->StateControl = inb(0x3C5); outb(0x3C4, 7); save->AuxillaryMode = inb(0x3C5); save->AuxillaryMode |= 0x14; temp = inb(vgaIOBase + 0x0A); /* reset flip-flop */ outb(0x3C0,0x36); save->Misc = inb(0x3C1); outb(0x3C0, save->Misc); ! if (DAC_is_GenDAC) { ! /* Save GenDAC Command and PLL registers */ outb(vgaIOBase + 4, 0x31); temp = inb(vgaIOBase + 5); outb(vgaIOBase + 5, temp | 0x40); save->gendac.cmd_reg = inb(0x3c6); /* Enhanced command register */ ! if (Gendac_programmable_clock) { save->gendac.PLL_w_idx = inb(0x3c8); /* PLL write index */ save->gendac.PLL_r_idx = inb(0x3c7); /* PLL read index */ outb(0x3c7, 2); /* index to f2 reg */ save->gendac.PLL_f2_M = inb(0x3c9); /* f2 PLL M divider */ save->gendac.PLL_f2_N = inb(0x3c9); /* f2 PLL N1/N2 divider */ + outb(0x3c7, 10); /* index to Mclk reg */ + save->MClkM = inb(0x3c9); /* MClk PLL M divider */ + save->MClkN = inb(0x3c9); /* MClk PLL N1/N2 divider */ outb(0x3c7, 0x0e); /* index to PLL control */ save->gendac.PLL_ctrl = inb(0x3c9); /* PLL control */ } *************** *** 1641,1647 **** if ( (TsengRamdacType == STG1702_DAC) || (TsengRamdacType == STG1703_DAC) || (TsengRamdacType == STG1700_DAC) ) { ! /* Restore STG 1703 GenDAC Command and PLL registers * unfortunately we reuse the gendac data structure, so the * field names are not really good. */ --- 1690,1696 ---- if ( (TsengRamdacType == STG1702_DAC) || (TsengRamdacType == STG1703_DAC) || (TsengRamdacType == STG1700_DAC) ) { ! /* Save STG 1703 GenDAC Command and PLL registers * unfortunately we reuse the gendac data structure, so the * field names are not really good. */ *************** *** 1648,1659 **** xf86dactopel(); save->gendac.cmd_reg = xf86getdaccomm();/* Enhanced command register */ ! if ( (OFLG_ISSET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions)) && ! (OFLG_ISSET(CLOCK_OPTION_STG1703, &vga256InfoRec.clockOptions)) ) { save->gendac.PLL_f2_M = STG1703getIndex(0x24); /* f2 PLL M divider */ save->gendac.PLL_f2_N = inb(0x3c6); /* f2 PLL N1/N2 divider */ } save->gendac.PLL_ctrl = STG1703getIndex(0x03); /* pixel mode select control */ } if (TsengRamdacType == CH8398_DAC) { --- 1697,1708 ---- xf86dactopel(); save->gendac.cmd_reg = xf86getdaccomm();/* Enhanced command register */ ! if (STG170x_programmable_clock) { save->gendac.PLL_f2_M = STG1703getIndex(0x24); /* f2 PLL M divider */ save->gendac.PLL_f2_N = inb(0x3c6); /* f2 PLL N1/N2 divider */ } save->gendac.PLL_ctrl = STG1703getIndex(0x03); /* pixel mode select control */ + save->gendac.timingctrl = STG1703getIndex(0x05); /* pll timing control */ } if (TsengRamdacType == CH8398_DAC) { *************** *** 1660,1669 **** xf86dactopel(); save->gendac.cmd_reg = xf86getdaccomm(); } ! #endif ! if ( (OFLG_ISSET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions)) && ! (OFLG_ISSET(CLOCK_OPTION_ET6000, &vga256InfoRec.clockOptions)) ) { /* Save ET6000 CLKDAC PLL registers */ temp = inb(ET6Kbase+0x67); /* remember old CLKDAC index register pointer */ outb(ET6Kbase+0x67, 2); --- 1709,1737 ---- xf86dactopel(); save->gendac.cmd_reg = xf86getdaccomm(); } ! if (CH8398_programmable_clock) { ! /* Save PLL */ ! outb(vgaIOBase + 4, 0x31); ! temp = inb(vgaIOBase + 5); ! outb(vgaIOBase + 5, temp | (1<<6)); /* set RS2 through CS3 */ ! /* We are in ClockRAM mode 0x3c7 = CRA, 0x3c8 = CWA, 0x3c9 = CDR */ ! save->gendac.PLL_r_idx = inb(0x3c7); ! save->gendac.PLL_w_idx = inb(0x3c8); ! outb(0x3c7,10); /* 2|((tseng_save_divide & 0x40)>>3)); yuck */ ! save->gendac.PLL_f2_N = inb(0x3c9); ! save->gendac.PLL_f2_M = inb(0x3c9); ! outb(0x3c7,save->gendac.PLL_r_idx); ! inb(0x3c8); /* loop to Clock Select Register */ ! inb(0x3c8); ! inb(0x3c8); ! inb(0x3c8); ! save->gendac.PLL_ctrl = inb(0x3c8); ! outb(vgaIOBase + 4, 0x31); ! outb(vgaIOBase + 5, temp); ! } ! if (ET6000_programmable_clock) ! { /* Save ET6000 CLKDAC PLL registers */ temp = inb(ET6Kbase+0x67); /* remember old CLKDAC index register pointer */ outb(ET6Kbase+0x67, 2); *************** *** 1671,1678 **** save->gendac.PLL_f2_N = inb(ET6Kbase+0x69); /* save MClk values */ outb(ET6Kbase+0x67, 10); ! save->ET6KMclkM = inb(ET6Kbase+0x69); ! save->ET6KMclkN = inb(ET6Kbase+0x69); /* restore old index register */ outb(ET6Kbase+0x67, temp); } --- 1739,1746 ---- save->gendac.PLL_f2_N = inb(ET6Kbase+0x69); /* save MClk values */ outb(ET6Kbase+0x67, 10); ! save->MClkM = inb(ET6Kbase+0x69); ! save->MClkN = inb(ET6Kbase+0x69); /* restore old index register */ outb(ET6Kbase+0x67, temp); } *************** *** 1679,1690 **** if (DAC_IS_ATT49x) save->ATTdac_cmd = xf86getdaccomm(); ! if (et4000_type >= TYPE_ET6000) { save->ET6KMemBase = inb(ET6Kbase+0x13); save->ET6KMMAPCtrl = inb(ET6Kbase+0x40); save->ET6KVidCtrl1 = inb(ET6Kbase+0x58); save->ET6KPerfContr = inb(ET6Kbase+0x41); save->ET6KDispFeat = inb(ET6Kbase+0x46); } --- 1747,1759 ---- if (DAC_IS_ATT49x) save->ATTdac_cmd = xf86getdaccomm(); ! if (Is_ET6K) { save->ET6KMemBase = inb(ET6Kbase+0x13); save->ET6KMMAPCtrl = inb(ET6Kbase+0x40); save->ET6KVidCtrl1 = inb(ET6Kbase+0x58); save->ET6KPerfContr = inb(ET6Kbase+0x41); + save->ET6KRasCas = inb(ET6Kbase+0x44); save->ET6KDispFeat = inb(ET6Kbase+0x46); } *************** *** 1707,1715 **** DisplayModePtr mode; { int row_offset; ! int BytesPerPix = vgaBitsPerPixel>>3; - #ifdef W32_SUPPORT /* * this is a kludge, but the ET4000Validate() code should already have --- 1776,1783 ---- DisplayModePtr mode; { int row_offset; ! int temp1,temp2,temp3; /* * this is a kludge, but the ET4000Validate() code should already have *************** *** 1717,1747 **** * there. I tried that, with no effect). But we seem to be getting a * different mode structure (a copy?) at this point. * ! * Another weirdness is that _here_, mode->Clock points to the clcok * _index_ in the array off clocks (usually 2 for a programmable clock), * while in ET4000Validate() mode->Clock is the actual pixel clock (in * kHZ). */ ! tseng_validate_mode(mode, BytesPerPix, TRUE); - #endif - if (!vgaHWInit(mode,sizeof(vgaET4000Rec))) return(FALSE); ! #ifdef MONOVGA ! /* Don't ask me why this is needed on the ET6000 and not on the others */ ! if (et4000_type >= TYPE_ET6000) new->std.Sequencer[1] |= 0x04; ! row_offset = new->std.CRTC[19]; ! #else ! new->std.Attribute[16] = 0x01; /* use the FAST 256 Color Mode */ ! row_offset = vga256InfoRec.displayWidth >> 3; /* overruled by 16/24/32 bpp code */ ! #endif ! new->std.CRTC[20] = 0x60; ! new->std.CRTC[23] = 0xAB; new->StateControl = 0x00; new->AuxillaryMode = 0xBC; new->ExtStart = 0x00; --- 1785,1819 ---- * there. I tried that, with no effect). But we seem to be getting a * different mode structure (a copy?) at this point. * ! * Another weirdness is that _here_, mode->Clock points to the clock * _index_ in the array off clocks (usually 2 for a programmable clock), * while in ET4000Validate() mode->Clock is the actual pixel clock (in * kHZ). */ ! tseng_validate_mode(mode, TRUE); if (!vgaHWInit(mode,sizeof(vgaET4000Rec))) return(FALSE); + if (vgaBitsPerPixel < 8) { + /* Don't ask me why this is needed on the ET6000 and not on the others */ + if (Is_ET6K) new->std.Sequencer[1] |= 0x04; + row_offset = new->std.CRTC[19]; + } + else { + new->std.Attribute[16] = 0x01; /* use the FAST 256 Color Mode */ + row_offset = vga256InfoRec.displayWidth >> 3; /* overruled by 16/24/32 bpp code */ + } ! if (vgaBitsPerPixel < 8) { ! new->std.CRTC[20] = 0x40; ! new->std.CRTC[23] = 0xC3; ! } else { ! new->std.CRTC[20] = 0x60; ! new->std.CRTC[23] = 0xAB; ! } new->StateControl = 0x00; new->AuxillaryMode = 0xBC; new->ExtStart = 0x00; *************** *** 1753,1767 **** | (((mode->CrtcVTotal -2) & 0x400) >> 9 ) | (((mode->CrtcVSyncStart) & 0x400) >> 10 ); ! #ifdef MONOVGA ! new->Misc = 0x00; ! #else ! new->Misc = 0x80; ! #endif - #ifndef MONOVGA new->RCConf = initialRCConf; ! if (OFLG_ISSET(OPTION_FAST_DRAM, &vga256InfoRec.options)) { /* * make sure Trsp is no more than 75ns --- 1825,1839 ---- | (((mode->CrtcVTotal -2) & 0x400) >> 9 ) | (((mode->CrtcVSyncStart) & 0x400) >> 10 ); ! if (vgaBitsPerPixel < 8) ! new->Misc = 0x00; ! else ! new->Misc = 0x80; new->RCConf = initialRCConf; ! if (vgaBitsPerPixel >= 8) { ! if (OFLG_ISSET(OPTION_FAST_DRAM, &vga256InfoRec.options) && ! et4000_type < TYPE_ET6000) { /* * make sure Trsp is no more than 75ns *************** *** 1779,1785 **** /* Trcd */ new->RCConf &= ~0x20; } ! #ifdef W32_SUPPORT /* * Here we make sure that CRTC regs 0x34 and 0x37 are untouched, except for * some bits we want to change. --- 1851,1857 ---- /* Trcd */ new->RCConf &= ~0x20; } ! } /* * Here we make sure that CRTC regs 0x34 and 0x37 are untouched, except for * some bits we want to change. *************** *** 1791,1802 **** * (those 135 MHz ramdac's...) */ if (et4000_type > TYPE_ET4000) { ! if (! OFLG_ISSET(OPTION_SLOW_DRAM, &vga256InfoRec.options)) new->Compatibility = (initialCompatibility & 0x7F) | 0x80; new->VSConf1 = initialVSConf1; new->VSConf2 = initialVSConf2; new->IMAPortCtrl = initialIMAPortCtrl; ! if ((vga256InfoRec.clock[mode->Clock] * BytesPerPix) > 80000) new->VSConf2 = (new->VSConf2 & 0x7f) | 0x80; } --- 1863,1875 ---- * (those 135 MHz ramdac's...) */ if (et4000_type > TYPE_ET4000) { ! if (! OFLG_ISSET(OPTION_SLOW_DRAM, &vga256InfoRec.options) && ! et4000_type < TYPE_ET6000) new->Compatibility = (initialCompatibility & 0x7F) | 0x80; new->VSConf1 = initialVSConf1; new->VSConf2 = initialVSConf2; new->IMAPortCtrl = initialIMAPortCtrl; ! if ((vga256InfoRec.clock[mode->Clock] * tseng_bytesperpixel) > 80000) new->VSConf2 = (new->VSConf2 & 0x7f) | 0x80; } *************** *** 1821,1842 **** if (OFLG_ISSET(OPTION_W32_INTERLEAVE_ON, &vga256InfoRec.options)) new->RCConf |= 0x80; } - #endif - #endif ! /* Set clock-related registers when not Legend * cannot really SET the clock here yet, since the ET4000Save() * is called LATER, so it would save the wrong state... ! * and since they use the ET4000Restore() to actually SET vga regs, ! * we can only set the clock there (that's why we copy Synthclock into ! * the other struct. */ ! #ifdef W32_SUPPORT ! if ( (OFLG_ISSET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions)) ! && ( (OFLG_ISSET(CLOCK_OPTION_STG1703, &vga256InfoRec.clockOptions))) ! || (OFLG_ISSET(CLOCK_OPTION_ICS5341, &vga256InfoRec.clockOptions)) ) { /* for pixmux: must use post-div of 4 on ICS GenDAC clock generator! */ --- 1894,1908 ---- if (OFLG_ISSET(OPTION_W32_INTERLEAVE_ON, &vga256InfoRec.options)) new->RCConf |= 0x80; } ! /* prepare clock-related registers when not Legend. * cannot really SET the clock here yet, since the ET4000Save() * is called LATER, so it would save the wrong state... ! * ET4000Restore() is used to actually SET vga regs. */ ! if (STG170x_programmable_clock || Gendac_programmable_clock) { /* for pixmux: must use post-div of 4 on ICS GenDAC clock generator! */ *************** *** 1861,1870 **** new->Compatibility = (new->Compatibility & 0xFD); new->std.MiscOutReg = (new->std.MiscOutReg & 0xF3) | 0x08; new->std.NoClock = 2; } else ! if ( (OFLG_ISSET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions)) ! && ( (OFLG_ISSET(CLOCK_OPTION_ICD2061A, &vga256InfoRec.clockOptions)))) { /* the programmed clock will be on clock index 2 */ /* disable MCLK/2 and MCLK/4 */ --- 1927,1942 ---- new->Compatibility = (new->Compatibility & 0xFD); new->std.MiscOutReg = (new->std.MiscOutReg & 0xF3) | 0x08; new->std.NoClock = 2; + + /* memory clock */ + if (Gendac_programmable_clock && (vga256InfoRec.MemClk > 0)) + { + commonCalcClock(vga256InfoRec.MemClk,1,1,31,1,3,100000,vga256InfoRec.dacSpeeds[0]*2+1, + &(new->MClkM), &(new->MClkN)); + } } else ! if (ICD2061a_programmable_clock) { /* the programmed clock will be on clock index 2 */ /* disable MCLK/2 and MCLK/4 */ *************** *** 1873,1884 **** new->Compatibility = (new->Compatibility & 0xFD); new->std.MiscOutReg = (new->std.MiscOutReg & 0xF3) | 0x08; new->std.NoClock = 2; ! Tseng_ICD2061AClockSelect(mode->SynthClock); } else ! #endif ! ! if (et4000_type >= TYPE_ET6000) { /* setting min_n2 to "1" will ensure a more stable clock ("0" is allowed though) */ commonCalcClock(vga256InfoRec.clock[new->std.NoClock],1,1,31,1,3, --- 1945,1974 ---- new->Compatibility = (new->Compatibility & 0xFD); new->std.MiscOutReg = (new->std.MiscOutReg & 0xF3) | 0x08; new->std.NoClock = 2; ! icd2061_dwv = AltICD2061CalcClock(mode->SynthClock*1000); ! /* Tseng_ICD2061AClockSelect(mode->SynthClock); */ } else ! if (CH8398_programmable_clock) { ! /* Let's call common_hw/Ch8391clk.c ! */ ! Chrontel8391CalcClock(mode->SynthClock,&temp1,&temp2,&temp3); ! new->gendac.PLL_f2_N = (unsigned char)(temp2); ! new->gendac.PLL_f2_M = (unsigned char)(temp1 | (temp3<<6)); ! /* ok LSB=PLL_f2_N and MSB=PLL_f2_M */ ! /* now set the Clock Select Register(CSR) */ ! new->gendac.PLL_ctrl = (new->gendac.PLL_ctrl | 0x90) & 0xF0; ! new->gendac.PLL_r_idx = 0; ! new->gendac.PLL_w_idx = 0; ! new->std.NoClock = 2; ! /* clear CS2: we need clock #2 */ ! new->Compatibility = (new->Compatibility & 0xFD); ! new->std.MiscOutReg = (new->std.MiscOutReg & 0xF3) | 0x08; ! /* disable MCLK/2 and MCLK/4, they don't seem to work in 24bpp ! anyway */ ! new->AuxillaryMode = (new->AuxillaryMode & 0xBE); ! } ! else ! if (Is_ET6K) { /* setting min_n2 to "1" will ensure a more stable clock ("0" is allowed though) */ commonCalcClock(vga256InfoRec.clock[new->std.NoClock],1,1,31,1,3, *************** *** 1887,1929 **** /* ErrorF("M=0x%x ; N=0x%x\n",new->gendac.PLL_f2_M, new->gendac.PLL_f2_N);*/ /* above 130MB/sec, we enable the "LOW FIFO threshold" */ ! if (vga256InfoRec.clock[new->std.NoClock] * BytesPerPix > 130000) { new->ET6KPerfContr = initialET6KPerfContr | 0x10; } else { new->ET6KPerfContr = initialET6KPerfContr & ~0x10; } ! #ifdef ALLOW_ET6K_FAST_DRAM ! if (OFLG_ISSET(OPTION_FAST_DRAM, &vga256InfoRec.options)) { ! /* ! * FAST_DRAM sets the memory clock to 100 MHz instead of the ! * standard 90 MHz. The lowest speed-grade of the MDRAMs is 100 MHz ! * anyway, and the ET6000 core is designed to run at 135 MHz. ! * ! * For the tweakers: every step increment of ET6KMclkM with 1 ! * increases the memory clock with about 2.5 MHz: Memory clock = ! * (ET6KMclkM+2)*14.31818/(2*3). ! * ! * 0x28 = 100 MHz ; 0x2C = 110 MHz; 0x30 = 120 MHz. ! * 120 MHz causes permanent mayhem on my system ! * -- don't try this at home! ! * ! * Currently disabled -- causes trouble [KMG]. ! */ ! new->ET6KMclkM = 0x28; ! new->ET6KMclkN = 0x21; } else { ! new->ET6KMclkM = initialET6KMclkM; ! new->ET6KMclkN = initialET6KMclkN; } - #endif /* force clock #2 */ new->Compatibility = (new->Compatibility & 0xFD); new->std.MiscOutReg = (new->std.MiscOutReg & 0xF3) | 0x08; --- 1977,2025 ---- /* ErrorF("M=0x%x ; N=0x%x\n",new->gendac.PLL_f2_M, new->gendac.PLL_f2_N);*/ /* above 130MB/sec, we enable the "LOW FIFO threshold" */ ! if (vga256InfoRec.clock[new->std.NoClock] * tseng_bytesperpixel > 130000) { new->ET6KPerfContr = initialET6KPerfContr | 0x10; + if (et4000_type >=TYPE_ET6100) + new->ET6KDispFeat = initialET6KDispFeat | 0x04; } else { new->ET6KPerfContr = initialET6KPerfContr & ~0x10; + if (et4000_type >=TYPE_ET6100) + new->ET6KDispFeat = initialET6KDispFeat & ~0x04; } ! if (vga256InfoRec.MemClk > 0) { ! /* according to Tseng Labs, N1 must be <= 4, and N2 should always be 1 for MClk */ ! commonCalcClock(vga256InfoRec.MemClk,1,1,4,1,1, ! 100000,vga256InfoRec.dacSpeeds[0]*2, ! &(new->MClkM), &(new->MClkN)); } else { ! /* not used right now (MClk ionly adjusted when explicitly set by "set_mclk" option) */ ! new->MClkM = initialET6KMclkM; ! new->MClkN = initialET6KMclkN; } + /* + * Even when we don't allow setting the MClk value as described + * above, we can use the FAST/MED/SLOW DRAM options to set up + * the RAS/CAS delays as decided by the value of ET6KRasCas. + * This is also a more correct use of the flags, as it describes + * how fast the RAM works. [HNH]. + */ + if (OFLG_ISSET(OPTION_FAST_DRAM, &vga256InfoRec.options)) + new->ET6KRasCas = 0x04; /* Fastest speed(?) */ + else if (OFLG_ISSET(OPTION_MED_DRAM, &vga256InfoRec.options)) + new->ET6KRasCas = 0x15; /* Medium speed */ + else if (OFLG_ISSET(OPTION_SLOW_DRAM, &vga256InfoRec.options)) + new->ET6KRasCas = 0x35; /* Slow speed */ + else + new->ET6KRasCas = initialET6KRasCas; /* keep current value */ + /* force clock #2 */ new->Compatibility = (new->Compatibility & 0xFD); new->std.MiscOutReg = (new->std.MiscOutReg & 0xF3) | 0x08; *************** *** 1952,1958 **** * linear mode handling */ ! if (et4000_type >= TYPE_ET6000) { if (ET4000.ChipUseLinearAddressing) { --- 2048,2054 ---- * linear mode handling */ ! if (Is_ET6K) { if (ET4000.ChipUseLinearAddressing) { *************** *** 1970,1979 **** if (ET4000.ChipUseLinearAddressing) { new->VSConf1 |= 0x10; ! new->SegMapComp = (vga256InfoRec.MemBase >> 22) & 0xFF; ! if ( (et4000_type < TYPE_ET4000W32P) && (bustype == BUS_VLB) ) { /* W32i */ ! new->SegMapComp = new->SegMapComp ^ 0x1c; /* invert A26..A24 */ ! } new->std.Graphics[6] &= ~0x0C; new->IMAPortCtrl &= ~0x01; /* disable IMA port (to get >1MB lin mem) */ } --- 2066,2075 ---- if (ET4000.ChipUseLinearAddressing) { new->VSConf1 |= 0x10; ! if (Is_W32p_up) ! new->SegMapComp = (vga256InfoRec.MemBase >> 22) & 0xFF; ! else ! new->SegMapComp = ((vga256InfoRec.MemBase >> 22) & 0x1F) ^ 0x1c; /* invert bits 4..2 */ new->std.Graphics[6] &= ~0x0C; new->IMAPortCtrl &= ~0x01; /* disable IMA port (to get >1MB lin mem) */ } *************** *** 1992,1999 **** */ if (vgaBitsPerPixel>=8) { ! tseng_set_ramdac_bpp(mode, new, BytesPerPix); ! row_offset *= BytesPerPix; } /* --- 2088,2095 ---- */ if (vgaBitsPerPixel>=8) { ! tseng_set_ramdac_bpp(mode, new); ! row_offset *= tseng_bytesperpixel; } /* *************** *** 2013,2024 **** * Enable memory mapped IO registers when acceleration is needed. */ ! #ifdef USE_XAA ! if (!OFLG_ISSET(OPTION_NOACCEL, &vga256InfoRec.options)) { ! if (et4000_type >= TYPE_ET6000) { ! if (OFLG_ISSET(OPTION_LINEAR, &vga256InfoRec.options)) new->ET6KMMAPCtrl |= 0x02; /* MMU can't be used here (causes system hang...) */ else new->ET6KMMAPCtrl |= 0x06; /* MMU is needed in banked accelerated mode */ --- 2109,2120 ---- * Enable memory mapped IO registers when acceleration is needed. */ ! #ifndef MONOVGA ! if (tseng_use_ACL) { ! if (Is_ET6K) { ! if (ET4000.ChipUseLinearAddressing) new->ET6KMMAPCtrl |= 0x02; /* MMU can't be used here (causes system hang...) */ else new->ET6KMMAPCtrl |= 0x06; /* MMU is needed in banked accelerated mode */ *************** *** 2045,2059 **** int x, y; { ! #ifdef MONOVGA ! int Base = (y * vga256InfoRec.displayWidth + x + 3) >> 3; ! #else ! int BytesPerPix = vgaBitsPerPixel>>3; ! int Base = ((y * vga256InfoRec.displayWidth + x + 1)*BytesPerPix) >> 2; ! /* adjust Base address so it is a non-fractional multiple of BytesPerPix */ ! Base -= (Base % BytesPerPix); ! #endif outw(vgaIOBase + 4, (Base & 0x00FF00) | 0x0C); outw(vgaIOBase + 4, ((Base & 0x00FF) << 8) | 0x0D); outw(vgaIOBase + 4, ((Base & 0x0F0000) >> 8) | 0x33); --- 2141,2160 ---- int x, y; { ! int Base; ! ! if (OFLG_ISSET(OPTION_SHOWCACHE, &vga256InfoRec.options)) { ! if(y) y += 256; ! } + if (vgaBitsPerPixel < 8) + Base = (y * vga256InfoRec.displayWidth + x + 3) >> 3; + else { + Base = ((y * vga256InfoRec.displayWidth + x + 1)*tseng_bytesperpixel) >> 2; + /* adjust Base address so it is a non-fractional multiple of tseng_bytesperpixel */ + Base -= (Base % tseng_bytesperpixel); + } + outw(vgaIOBase + 4, (Base & 0x00FF00) | 0x0C); outw(vgaIOBase + 4, ((Base & 0x00FF) << 8) | 0x0D); outw(vgaIOBase + 4, ((Base & 0x0F0000) >> 8) | 0x33); *************** *** 2090,2096 **** #ifndef PC98_EGC if (start == SS_START) { ! if (et4000_type > TYPE_ET4000) { outb(vgaIOBase + 4, 0x36); save_VSConf1 = inb(vgaIOBase + 5); --- 2191,2197 ---- #ifndef PC98_EGC if (start == SS_START) { ! if (Is_W32_any) { outb(vgaIOBase + 4, 0x36); save_VSConf1 = inb(vgaIOBase + 5); *************** *** 2100,2106 **** else { vgaHWSaveScreen(start); ! if (et4000_type > TYPE_ET4000) { outw(vgaIOBase + 4, (save_VSConf1 << 8) | 0x36); } --- 2201,2207 ---- else { vgaHWSaveScreen(start); ! if (Is_W32_any) { outw(vgaIOBase + 4, (save_VSConf1 << 8) | 0x36); } *************** *** 2120,2325 **** Bool verbose; int flag; { ! /* tseng_validate_mode(mode, verbose);*/ ! return MODE_OK; ! } ! ! #ifdef DPMSExtension ! /* ! * TsengCrtcDPMSSet -- ! * ! * Sets VESA Display Power Management Signaling (DPMS) Mode. ! * This routine is for the ET4000W32P rev. c and later, which can ! * use CRTC indexed register 34 to turn off H/V Sync signals. ! */ ! static void TsengCrtcDPMSSet(Mode) ! CARD16 Mode; ! { ! unsigned char seq1, crtc34; ! if (!xf86VTSema) return; ! switch (Mode) ! { ! case DPMSModeOn: ! /* Screen: On; HSync: On, VSync: On */ ! seq1 = 0x00; ! crtc34 = 0x00; ! break; ! case DPMSModeStandby: ! /* Screen: Off; HSync: Off, VSync: On */ ! seq1 = 0x20; ! crtc34 = 0x01; ! break; ! case DPMSModeSuspend: ! /* Screen: Off; HSync: On, VSync: Off */ ! seq1 = 0x20; ! crtc34 = 0x20; ! break; ! case DPMSModeOff: ! /* Screen: Off; HSync: Off, VSync: Off */ ! seq1 = 0x20; ! crtc34 = 0x21; ! break; ! } ! outb(0x3C4, 0x01); /* Select SEQ1 */ ! seq1 |= inb(0x3C5) & ~0x20; ! outb(0x3C5, seq1); ! outb(vgaIOBase+4, 0x34); /* Select CRTC34 */ ! crtc34 |= inb(vgaIOBase+5) & ~0x21; ! outb(vgaIOBase+5, crtc34); ! } ! ! ! /* ! * TsengHVSyncDPMSSet -- ! * ! * Sets VESA Display Power Management Signaling (DPMS) Mode. ! * This routine is for Tseng et4000 chips that do not have any ! * registers to disable sync output. ! */ ! static void TsengHVSyncDPMSSet(Mode) ! CARD16 Mode; ! { ! unsigned char seq1, tmpb; ! unsigned int HSync, VSync, HTot, VTot, tmp; ! Bool chgHSync, chgVSync; ! ! if (!xf86VTSema) return; ! ! /* Code here to read the current values of HSync through VTot: ! * HSYNC: ! * bits 0..7 : CRTC index 0x04 ! * bit 8 : CRTC index 0x3F, bit 4 */ ! outb(vgaIOBase+4, 0x04); ! HSync = inb(vgaIOBase+5); ! outb(vgaIOBase+4, 0x3F); ! HSync += (inb(vgaIOBase+5) & 0x10) << 4; ! /* VSYNC: ! * bits 0..7 : CRTC index 0x10 ! * bits 8..9 : CRTC index 0x07 bits 2 (VSYNC bit 8) and 7 (VSYNC bit 9) ! * bit 10 : CRTC index 0x35 bit 3 ! */ ! outb(vgaIOBase+4, 0x10); ! VSync = inb(vgaIOBase+5); ! outb(vgaIOBase+4, 0x07); ! tmp = inb(vgaIOBase+5); ! VSync += (tmp & 0x04)<< 6 + (tmp & 0x80) << 2; ! outb(vgaIOBase+4, 0x35); ! VSync += (inb(vgaIOBase+5) & 0x08) << 7; ! /* HTOT: ! * bits 0..7 : CRTC index 0x00. ! * bit 8 : CRTC index 0x3F, bit 0 ! */ ! outb(vgaIOBase+4, 0x00); ! HTot = inb(vgaIOBase+5); ! outb(vgaIOBase+4, 0x3F); ! HTot += (inb(vgaIOBase+5) & 0x01) << 8; ! /* VTOT: ! * bits 0..7 : CRTC index 0x06 ! * bits 8..9 : CRTC index 0x07 bits 0 (VTOT bit 8) and 5 (VTOT bit 9) ! * bit 10 : CRTC index 0x35 bit 1 ! */ ! outb(vgaIOBase+4, 0x06); ! VTot = inb(vgaIOBase+5); ! outb(vgaIOBase+4, 0x07); ! tmp = inb(vgaIOBase+5); ! VTot += (tmp & 0x01)<< 8 + (tmp & 0x20) << 4; ! outb(vgaIOBase+4, 0x35); ! VTot += (inb(vgaIOBase+5) & 0x02) << 9; ! /* Don't write these unless we have to. */ ! chgHSync = chgVSync = FALSE; ! ! switch (Mode) ! { ! case DPMSModeOn: ! /* Screen: On; HSync: On, VSync: On */ ! seq1 = 0x00; ! if(HSync > HTot +3) { /* Sync is off now, turn it on. */ ! HSync = (HTot - HSync) + HTot + 7; ! chgHSync = TRUE; ! } ! if(VSync > VTot +1) { /* Sync is off now, turn it on. */ ! VSync = (VTot - VSync) + VTot + 4; ! chgVSync = TRUE; ! } ! break; ! case DPMSModeStandby: ! /* Screen: Off; HSync: Off, VSync: On */ ! seq1 = 0x20; ! if(HSync <= HTot +3) { /* Sync is on now, turn it off. */ ! HSync = (HTot - HSync) + HTot + 7; ! chgHSync = TRUE; ! } ! if(VSync > VTot +1) { /* Sync is off now, turn it on. */ ! VSync = (VTot - VSync) + VTot + 4; ! chgVSync = TRUE; ! } ! break; ! case DPMSModeSuspend: ! /* Screen: Off; HSync: On, VSync: Off */ ! seq1 = 0x20; ! if(HSync > HTot +3) { /* Sync is off now, turn it on. */ ! HSync = (HTot - HSync) + HTot + 7; ! chgHSync = TRUE; ! } ! if(VSync <= VTot +1) { /* Sync is on now, turn it off. */ ! VSync = (VTot - VSync) + VTot + 4; ! chgVSync = TRUE; ! } ! break; ! case DPMSModeOff: ! /* Screen: Off; HSync: Off, VSync: Off */ ! seq1 = 0x20; ! if(HSync <= HTot +3) { /* Sync is on now, turn it off. */ ! HSync = (HTot - HSync) + HTot + 7; ! chgHSync = TRUE; ! } ! if(VSync <= VTot +1) { /* Sync is on now, turn it off. */ ! VSync = (VTot - VSync) + VTot + 4; ! chgVSync = TRUE; ! } ! break; ! } ! ! /* The code to turn on and off video output is equal for all. */ ! outb(0x3C4, 0x01); /* Select SEQ1 */ ! seq1 |= inb(0x3C5) & ~0x20; ! outb(0x3C5, seq1); ! ! /* Then the code to write VSync and HSync to the card. ! * HSYNC: ! * bits 0..7 : CRTC index 0x04 ! * bit 8 : CRTC index 0x3F, bit 4 ! */ ! if(chgHSync) { ! outb(vgaIOBase+4, 0x04); ! tmpb = HSync & 0xFF; ! outb(vgaIOBase+5, tmpb); ! outb(vgaIOBase+4, 0x3F); ! tmpb = (HSync & 0x100) >>4; ! tmpb |= inb(vgaIOBase+5) & ~0x10; ! outb(vgaIOBase+5, tmpb); } ! /* VSYNC: ! * bits 0..7 : CRTC index 0x10 ! * bits 8..9 : CRTC index 0x07 bits 2 (VSYNC bit 8) and 7 (VSYNC bit 9) ! * bit 10 : CRTC index 0x35 bit 3 ! */ ! if(chgVSync) { ! outb(vgaIOBase+4, 0x10); ! tmpb = VSync & 0xFF; ! outb(vgaIOBase+5, tmpb); ! outb(vgaIOBase+4, 0x07); ! tmpb = (VSync & 0x100) >> 6; ! tmpb |= (VSync & 0x200) >> 2; ! tmpb |= inb(vgaIOBase+5) & ~0x84; ! outb(vgaIOBase+5, tmpb); ! outb(vgaIOBase+4, 0x35); ! tmpb = (VSync & 0x400) >> 7; ! tmpb |= inb(vgaIOBase+5) & ~0x08; ! outb(vgaIOBase+5, tmpb); } } ! #endif --- 2221,2264 ---- Bool verbose; int flag; { ! #define Tseng_HMAX (4096-8) ! #define Tseng_VMAX (2048-1) ! /* ! * Check for pixmux and adjust clocks if needed. This has the rather ! * confusing side effect that the mode is suddenly reported as using only ! * half the clock specified in the modeline. We'd better be verbose enough ! * about that to avoid confusing the poor user. Could this be avoided? */ ! if ( (Tseng_pixMuxPossible) && ! (mode->Clock > Tseng_nonMuxMaxClock) && ! (mode->HDisplay >= Tseng_pixMuxMinWidth) && ! (!(mode->Flags & V_INTERLACE)) ) { ! mode->Flags |= V_PIXMUX; ! mode->Flags |= V_DBLCLK; ! mode->Clock /= 2; ! if (verbose) ! ErrorF("%s %s: Mode \"%s\" will use pixel multiplexing (clock will be reported as 1/2 of clock in modeline).\n", ! XCONFIG_PROBED, vga256InfoRec.name, mode->name); ! } ! /* Check for CRTC timing bits overflow. */ ! if (mode->HTotal > Tseng_HMAX) { ! if (verbose) ! ErrorF("%s %s: %s: Horizontal mode timing overflow (=%d, max=%d)\n", ! XCONFIG_PROBED, vga256InfoRec.name, ! vga256InfoRec.chipset, mode->HTotal, Tseng_HMAX); ! return MODE_BAD; } ! if (mode->VTotal > Tseng_VMAX) { ! if(verbose) ! ErrorF("%s %s: %s: Vertical mode timing overflow (=%d, max=%d)\n", ! XCONFIG_PROBED, vga256InfoRec.name, ! vga256InfoRec.chipset, mode->VTotal, Tseng_VMAX); ! return MODE_BAD; } + + return MODE_OK; } ! ! *** ./programs/Xserver/hw/xfree86/vga256/drivers/mga/Imakefile@@/PUBLIC-LATEST Sat Jul 19 19:33:46 1997 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/mga/Imakefile Sat Mar 7 16:40:44 1998 *************** *** 1,9 **** ! XCOMM $TOG: Imakefile /main/7 1997/07/19 19:33:48 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/mga/Imakefile,v 3.7.2.1 1997/05/09 09:09:06 hohndel Exp $ XCOMM XCOMM This is an Imakefile for the MGA driver. XCOMM --- 1,9 ---- ! XCOMM $TOG: Imakefile /main/9 1998/03/07 16:42:25 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/mga/Imakefile,v 3.7.2.2 1998/02/01 16:05:10 robin Exp $ XCOMM XCOMM This is an Imakefile for the MGA driver. XCOMM *************** *** 11,19 **** #include <Server.tmpl> SRCS = mga_driver.c mga_hwcurs.c mga_dac3026.c mga_dac1064.c \ ! mga_storm8.c mga_storm16.c mga_storm32.c OBJS = mga_driver.o mga_hwcurs.o mga_dac3026.o mga_dac1064.o \ ! mga_storm8.o mga_storm16.o mga_storm32.o #if XF86LinkKit INCLUDES = -I. -I../../../include -I../../../include/X11 -I../.. --- 11,19 ---- #include <Server.tmpl> SRCS = mga_driver.c mga_hwcurs.c mga_dac3026.c mga_dac1064.c \ ! mga_storm8.c mga_storm16.c mga_storm32.c mga_xaarepl.c OBJS = mga_driver.o mga_hwcurs.o mga_dac3026.o mga_dac1064.o \ ! mga_storm8.o mga_storm16.o mga_storm32.o mga_xaarepl.o #if XF86LinkKit INCLUDES = -I. -I../../../include -I../../../include/X11 -I../.. *************** *** 42,49 **** --- 42,51 ---- InstallLinkKitNonExecFile(mga_hwcurs.c,$(LINKKITDIR)/drivers/vga256/mga) InstallLinkKitNonExecFile(mga_storm.c,$(LINKKITDIR)/drivers/vga256/mga) InstallLinkKitNonExecFile(mga_map.h,$(LINKKITDIR)/drivers/vga256/mga) + InstallLinkKitNonExecFile(mga_macros.h,$(LINKKITDIR)/drivers/vga256/mga) InstallLinkKitNonExecFile(mga_dac3026.c,$(LINKKITDIR)/drivers/vga256/mga) InstallLinkKitNonExecFile(mga_dac1064.c,$(LINKKITDIR)/drivers/vga256/mga) + InstallLinkKitNonExecFile(mga_xaarepl.c,$(LINKKITDIR)/drivers/vga256/mga) InstallLinkKitNonExecFile(Imakefile,$(LINKKITDIR)/drivers/vga256/mga) DependTarget() *** ./programs/Xserver/hw/xfree86/vga256/drivers/mga/README@@/PUBLIC-LATEST Sun Aug 10 13:05:37 1997 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/mga/README Fri Mar 6 16:50:28 1998 *************** *** 1,22 **** ! $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/mga/README,v 3.6.2.5 1997/08/02 13:48:22 dawes Exp $ MGA Millennium (MGA2064W) with TVP3026 RAMDAC Driver v1.3 ========================================================= MGA Mystique (MGA1064W) with integrated RAMDAC Driver v1.3 ========================================================= ! MGA Millennium II (MGA2164W) with TVP3026 RAMDAC Driverv1.3 (experimental) - NOTE: This driver is fairly new, and not everything works like you expect - it to. It shouldn't crash your machine, and there are problems with 24 bpp, - but it should work pretty well. Please report any and all problems to - XFree86@Xfree86.org using the appropriate bug report sheet. - - This is an experimental build for the Millennium II, and not everything - works as you'd expect. Please report any bugs for the Mill II to - Andrew.van.der.Stock@member.sage-au.org.au - Features: --------- --- 1,13 ---- ! $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/mga/README,v 3.6.2.6 1998/02/01 16:05:10 robin Exp $ MGA Millennium (MGA2064W) with TVP3026 RAMDAC Driver v1.3 ========================================================= MGA Mystique (MGA1064W) with integrated RAMDAC Driver v1.3 ========================================================= ! MGA Millennium II (MGA2164W) with TVP3026 RAMDAC Driverv1.3 Features: --------- *************** *** 30,37 **** - 24 bits per pixel (packed true colour) ** - 32 bits per pixel (true colour) ! There are some 24 bpp mode problems - tiling doesn't work properly, so for some ! programs, notably Netscape, gimp, xsetroot, etc, you may see corrupted images. Planned Features --- 21,29 ---- - 24 bits per pixel (packed true colour) ** - 32 bits per pixel (true colour) ! ** We don't pass the xtest suite in 24bpp. This is possibly due to ! some uncaught planemask mishap (MGA has severe planemask usage ! restrictions in 24bpp). Planned Features *************** *** 42,48 **** * More hardware acceleration. * Support for more chipsets and RAMDACs. * 3D acceleration ! * other depths (16,24,32 bits) and acceleration features for Mystique board Technical Notes: ---------------- --- 34,40 ---- * More hardware acceleration. * Support for more chipsets and RAMDACs. * 3D acceleration ! * other depths (16,24,32 bits) Technical Notes: ---------------- *************** *** 59,65 **** - for Mystique board: - - - - - - - - - - - ! up to 170 MHz, This driver auto-detects the amount of installed WRAM and the RAMDAC speed, so you don't need to probe or specify these. Same goes for the clocks, which --- 51,57 ---- - for Mystique board: - - - - - - - - - - - ! up to 170 MHz (220 in Mystique-220) This driver auto-detects the amount of installed WRAM and the RAMDAC speed, so you don't need to probe or specify these. Same goes for the clocks, which *************** *** 105,113 **** Driver Options: --------------- ! "noaccel" - turns off Drawing Engine (mandatory for Mystique) ! "sw_cursor" - turns hardware cursor off "xaa_benchmark" - do some benchmarks during startup - for Mystique board: - - - - - - - - - - - --- 97,111 ---- Driver Options: --------------- ! "noaccel" - turns off Drawing Engine ! "sw_cursor" - turns hardware cursor off. You will need this in ! doublescan and interlaced modes because the ! hardware cursor is broken in those modes ! at the moment. "xaa_benchmark" - do some benchmarks during startup + "no_pci_disconnect" - turns off pci disconnects. Try this if you have + problems with the MGA interferring with + soundcard operation or similar. - for Mystique board: - - - - - - - - - - - *************** *** 169,175 **** lnz@dandelion.com Mark Vojkovich ! mvojkovi@sdcc10.ucsd.edu Michael Will zxmgv07@student.uni-tuebingen.de --- 167,173 ---- lnz@dandelion.com Mark Vojkovich ! mvojkovi@ucsd.edu Michael Will zxmgv07@student.uni-tuebingen.de *** ./programs/Xserver/hw/xfree86/vga256/drivers/mga/mga.h@@/PUBLIC-LATEST Sun Aug 10 13:05:43 1997 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/mga/mga.h Fri Mar 6 16:50:33 1998 *************** *** 1,4 **** ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/mga/mga.h,v 3.8.2.3 1997/07/26 06:30:53 dawes Exp $ */ /* * MGA Millennium (MGA2064W) functions * --- 1,4 ---- ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/mga/mga.h,v 3.8.2.4 1998/02/01 16:05:10 robin Exp $ */ /* * MGA Millennium (MGA2064W) functions * *************** *** 18,23 **** --- 18,24 ---- #define mb() __asm__ __volatile__("mb": : :"memory") #define INREG8(addr) xf86ReadSparse8(MGAMMIOBase, (addr)) #define INREG16(addr) xf86ReadSparse16(MGAMMIOBase, (addr)) + #define INREG(addr) xf86ReadSparse32(MGAMMIOBase, (addr)) #define OUTREG8(addr,val) do { xf86WriteSparse8((val),MGAMMIOBase,(addr)); \ mb();} while(0) #define OUTREG16(addr,val) do { xf86WriteSparse16((val),MGAMMIOBase,(addr)); \ *************** *** 27,32 **** --- 28,34 ---- #else /* __alpha__ */ #define INREG8(addr) *(volatile CARD8 *)(MGAMMIOBase + (addr)) #define INREG16(addr) *(volatile CARD16 *)(MGAMMIOBase + (addr)) + #define INREG(addr) *(volatile CARD32 *)(MGAMMIOBase + (addr)) #define OUTREG8(addr, val) *(volatile CARD8 *)(MGAMMIOBase + (addr)) = (val) #define OUTREG16(addr, val) *(volatile CARD16 *)(MGAMMIOBase + (addr)) = (val) #define OUTREG(addr, val) *(volatile CARD32 *)(MGAMMIOBase + (addr)) = (val) *************** *** 39,52 **** typedef struct { Bool isHwCursor; ! pointer (*RealizeCursor)(); ! void (*LoadCursor)(); ! void (*QueryCursorSize)(); ! Bool (*CursorState)(); ! void (*CursorOn)(); ! void (*CursorOff)(); ! void (*MoveCursor)(); ! void (*RecolorCursor)(); long maxPixelClock; long MemoryClock; } MGARamdacRec; --- 41,54 ---- typedef struct { Bool isHwCursor; ! int CursorMaxWidth; ! int CursorMaxHeight; ! int CursorFlags; ! void (*LoadCursorImage)(); ! void (*ShowCursor)(); ! void (*HideCursor)(); ! void (*SetCursorPosition)(); ! void (*SetCursorColors)(); long maxPixelClock; long MemoryClock; } MGARamdacRec; *************** *** 60,65 **** --- 62,78 ---- extern int MGAusefbitblt; extern int MGAydstorg; extern unsigned char *MGAMMIOBase; + + extern void Mga8AccelInit(); + extern void Mga16AccelInit(); + extern void Mga24AccelInit(); + extern void Mga32AccelInit(); + extern void MGAStormAccelInit(); + extern void MGAStormSync(); + extern void MGAStormEngineInit(); + extern void MGA3026RamdacInit(); + extern void MGA1064RamdacInit(); + #ifdef __alpha__ extern unsigned char *MGAMMIOBaseDENSE; #endif *************** *** 76,85 **** #define WAITUNTILFINISHED() MGAWAITFREE() #define SETBACKGROUNDCOLOR(col) OUTREG(MGAREG_BCOL, (col)) #define SETFOREGROUNDCOLOR(col) OUTREG(MGAREG_FCOL, (col)) ! #define SETRASTEROP(rop) mga_cmd |= (((rop & 1)==1)*8 | \ ! ((rop & 2)==2)*4 | \ ! ((rop & 4)==4)*2 | \ ! ((rop & 8)==8)) << 16; #define SETWRITEPLANEMASK(pm) OUTREG(MGAREG_PLNWT, (pm)) #define SETBLTXYDIR(x,y) OUTREG(MGAREG_SGN, ((-x+1)>>1)+4*((-y+1)>>1)) --- 89,95 ---- #define WAITUNTILFINISHED() MGAWAITFREE() #define SETBACKGROUNDCOLOR(col) OUTREG(MGAREG_BCOL, (col)) #define SETFOREGROUNDCOLOR(col) OUTREG(MGAREG_FCOL, (col)) ! #define SETRASTEROP(rop) mga_cmd |= MGARop[rop] #define SETWRITEPLANEMASK(pm) OUTREG(MGAREG_PLNWT, (pm)) #define SETBLTXYDIR(x,y) OUTREG(MGAREG_SGN, ((-x+1)>>1)+4*((-y+1)>>1)) *** /dev/null Tue Jun 30 11:49:55 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/mga/mga_macros.h Fri Mar 6 16:51:00 1998 *************** *** 0 **** --- 1,40 ---- + /* $TOG: mga_macros.h /main/1 1998/03/06 16:52:38 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/mga/mga_macros.h,v 1.1.2.2 1998/02/01 22:08:12 robin Exp $ */ + + #ifndef _MGA_MACROS_H_ + #define _MGA_MACROS_H_ + + #if PSZ == 8 + #define REPLICATE(r) r &= 0xFF; r |= r << 8; r |= r << 16 + #elif PSZ == 16 + #define REPLICATE(r) r &= 0xFFFF; r |= r << 16 + #else + #define REPLICATE(r) /* */ + #endif + + #if PSZ == 24 + #define REPLICATE24(r) r &= 0xFFFFFF; r |= r << 24 + #else + #define REPLICATE24(r) REPLICATE(r) + #endif + + #define RGBEQUAL(c) (!(((c >> 8) ^ c) & 0xffff)) + + #define WAITFIFO(n) if(!MGAUsePCIRetry) \ + {while(INREG8(MGAREG_FIFOSTATUS) < (n));} + + #define XYADDRESS(x,y) ((y) * xf86AccelInfoRec.FramebufferWidth + (x) + MGAydstorg) + + #define MAKEDMAINDEX(index) ((((index) >> 2) & 0x7f) | (((index) >> 6) & 0x80)) + + #define DMAINDICIES(one,two,three,four) \ + ( MAKEDMAINDEX(one) | \ + (MAKEDMAINDEX(two) << 8) | \ + (MAKEDMAINDEX(three) << 16) | \ + (MAKEDMAINDEX(four) << 24) ) + + + #endif /* _MGA_MACROS_H_ */ *** /dev/null Tue Jun 30 11:49:56 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/mga/mga_xaarepl.c Fri Mar 6 16:51:13 1998 *************** *** 0 **** --- 1,363 ---- + /* $TOG: mga_xaarepl.c /main/1 1998/03/06 16:52:51 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/mga/mga_xaarepl.c,v 1.1.2.1 1998/02/01 16:05:14 robin Exp $ */ + + + #define PSZ 8 + + #include "vga256.h" + #include "xf86.h" + #include "xf86xaa.h" + + #define MAX_BLIT_PIXELS 0x40000 + + #ifndef GNUC + #define __inline__ /**/ + #endif + + extern void MGAStormSync(); + + static __inline__ CARD32* MoveDWORDS(dest, src, dwords) + register CARD32* dest; + register CARD32* src; + register int dwords; + { + while(dwords & ~0x03) { + dest[0] = src[0]; + dest[1] = src[1]; + dest[2] = src[2]; + dest[3] = src[3]; + src += 4; + dest += 4; + dwords -= 4; + } + switch(dwords) { + case 0: return(dest); + case 1: dest[0] = src[0]; + return(dest + 1); + case 2: dest[0] = src[0]; + dest[1] = src[1]; + return(dest + 2); + case 3: dest[0] = src[0]; + dest[1] = src[1]; + dest[2] = src[2]; + return(dest + 3); + } + return dest; + } + + + void MGAWriteBitmap(x, y, w, h, src, srcwidth, srcx, srcy, + bg, fg, rop, planemask) + int x, y, w, h; + unsigned char *src; + int srcwidth; + int srcx, srcy; + int bg, fg; + int rop; + unsigned int planemask; + { + register unsigned char *srcp; + int dwords, skipleft, maxlines; + register CARD32 *destptr = + (CARD32*)xf86AccelInfoRec.CPUToScreenColorExpandBase; + CARD32 *maxptr; + + xf86AccelInfoRec.SetupForCPUToScreenColorExpand(bg, fg, rop, planemask); + + srcp = (srcwidth * srcy) + (srcx >> 3) + src; + srcx &= 0x07; + if(skipleft = (int)srcp & 0x03) { + skipleft = (skipleft << 3) + srcx; + maxlines = MAX_BLIT_PIXELS / (w + skipleft); + if(maxlines < h) { + int newmax = MAX_BLIT_PIXELS / (w + srcx); + if(newmax >= h) { /* do byte alignment to avoid the split */ + skipleft = srcx; + maxlines = newmax; + } else srcp = (unsigned char*)((int)srcp & ~0x03); + } else srcp = (unsigned char*)((int)srcp & ~0x03); + } else { + skipleft = srcx; + maxlines = MAX_BLIT_PIXELS / (w + skipleft); + } + + w += skipleft; + x -= skipleft; + + dwords = (w + 31) >> 5; + maxptr = destptr + (xf86AccelInfoRec.CPUToScreenColorExpandRange >> 2) + - dwords; + + while(h > maxlines) { + int numlines = maxlines; + xf86AccelInfoRec.SubsequentCPUToScreenColorExpand( + x, y, w, maxlines, skipleft); + while(numlines--) { + destptr = MoveDWORDS(destptr, (CARD32*)srcp, dwords); + srcp += srcwidth; + if(destptr > maxptr) + destptr = (CARD32*)xf86AccelInfoRec.CPUToScreenColorExpandBase; + } + h -= maxlines; + y += maxlines; + } + + xf86AccelInfoRec.SubsequentCPUToScreenColorExpand(x, y, w, h, skipleft); + + while(h--) { + destptr = MoveDWORDS(destptr, (CARD32*)srcp, dwords); + srcp += srcwidth; + if(destptr > maxptr) + destptr = (CARD32*)xf86AccelInfoRec.CPUToScreenColorExpandBase; + } + + MGAStormSync(); + } + + + static __inline__ CARD32* SetDWORDS(dest, value, dwords) + register CARD32* dest; + register CARD32 value; + register int dwords; + { + while(dwords & ~0x03) { + dest[0] = dest[1] = dest[2] = dest[3] = value; + dest += 4; + dwords -= 4; + } + switch(dwords) { + case 0: return(dest); + case 1: dest[0] = value; + return(dest + 1); + case 2: dest[0] = dest[1] = value; + return(dest + 2); + case 3: dest[0] = dest[1] = dest[2] = value; + return(dest + 3); + } + return dest; + } + + static unsigned int ShiftMasks[32] = { + 0x00000000, 0x00000001, 0x00000003, 0x00000007, + 0x0000000F, 0x0000001F, 0x0000003F, 0x0000007F, + 0x000000FF, 0x000001FF, 0x000003FF, 0x000007FF, + 0x00000FFF, 0x00001FFF, 0x00003FFF, 0x00007FFF, + 0x0000FFFF, 0x0001FFFF, 0x0003FFFF, 0x0007FFFF, + 0x000FFFFF, 0x001FFFFF, 0x003FFFFF, 0x007FFFFF, + 0x00FFFFFF, 0x01FFFFFF, 0x03FFFFFF, 0x07FFFFFF, + 0x0FFFFFFF, 0x1FFFFFFF, 0x3FFFFFFF, 0x7FFFFFFF + }; + + + static void + MGAFillStippledCPUToScreenColorExpand(x, y, dwords, h, src, srcwidth, + stipplewidth, stippleheight, srcx, srcy) + int x, y, dwords, h; + unsigned char *src; + int srcwidth; + int stipplewidth, stippleheight; + int srcx, srcy; + { + unsigned char *srcp = (srcwidth * srcy) + src; + register CARD32 *destptr = + (CARD32*)xf86AccelInfoRec.CPUToScreenColorExpandBase; + CARD32 *maxptr; + + maxptr = destptr + (xf86AccelInfoRec.CPUToScreenColorExpandRange >> 2) + - dwords; + + if(!((stipplewidth > 32) || (stipplewidth & (stipplewidth - 1)))) { + CARD32 pattern; + register unsigned char* kludge = (unsigned char*)(&pattern); + + while(h--) { + switch(stipplewidth) { + case 32: + pattern = *((CARD32*)srcp); + break; + case 16: + kludge[0] = kludge[2] = srcp[0]; + kludge[1] = kludge[3] = srcp[1]; + break; + case 8: + kludge[0] = kludge[1] = kludge[2] = kludge[3] = srcp[0]; + break; + case 4: + kludge[0] = kludge[1] = kludge[2] = kludge[3] = + (srcp[0] & 0x0F); + pattern |= (pattern << 4); + break; + case 2: + kludge[0] = kludge[1] = kludge[2] = kludge[3] = + (srcp[0] & 0x03); + pattern |= (pattern << 2); + pattern |= (pattern << 4); + break; + default: /* case 1: */ + if(srcp[0] & 0x01) pattern = 0xffffffff; + else pattern = 0x00000000; + break; + } + + if(srcx) + pattern = (pattern >> srcx) | (pattern << (32 - srcx)); + + + destptr = SetDWORDS(destptr, pattern, dwords); + if(destptr > maxptr) + destptr = (CARD32*)xf86AccelInfoRec.CPUToScreenColorExpandBase; + + srcy++; + srcp += srcwidth; + if (srcy >= stippleheight) { + srcy = 0; + srcp = src; + } + } + } else if(stipplewidth < 32) { + int count, width, offset; + register CARD32 pattern; + + while(h--) { + width = stipplewidth; + pattern = *((CARD32*)srcp) & ShiftMasks[width]; + while(!(width & ~15)) { + pattern |= (pattern << width); + width <<= 1; + } + pattern |= (pattern << width); + + offset = srcx; + + count = dwords; + while(count--) { + *(destptr++) = (pattern >> offset) | + (pattern << (width - offset)); + offset += 32; + while(offset >= width) + offset -= width; + } + + if(destptr > maxptr) + destptr = (CARD32*)xf86AccelInfoRec.CPUToScreenColorExpandBase; + + srcy++; + srcp += srcwidth; + if (srcy >= stippleheight) { + srcy = 0; + srcp = src; + } + } + } else { + register CARD32* scratch; + int shift, offset, scratch2, count; + + while(h--) { + count = dwords; + offset = srcx; + + while(count--) { + shift = stipplewidth - offset; + scratch = (CARD32*)(srcp + (offset >> 3)); + scratch2 = offset & 0x07; + + if(shift & ~31) { + if(scratch2) { + *(destptr++) = (*scratch >> scratch2) | + (scratch[1] << (32 - scratch2)); + } else + *(destptr++) = *scratch; + } else { + *(destptr++) = (*((CARD32*)srcp) << shift) | + ((*scratch >> scratch2) & ShiftMasks[shift]); + } + offset += 32; + while(offset >= stipplewidth) + offset -= stipplewidth; + } + + if(destptr > maxptr) + destptr = (CARD32*)xf86AccelInfoRec.CPUToScreenColorExpandBase; + + srcy++; + srcp += srcwidth; + if (srcy >= stippleheight) { + srcy = 0; + srcp = src; + } + } + } + + } + + + void + MGAFillRectStippled(pDrawable, pGC, nBoxInit, pBoxInit) + DrawablePtr pDrawable; + GCPtr pGC; + int nBoxInit; /* number of rectangles to fill */ + BoxPtr pBoxInit; /* Pointer to first rectangle to fill */ + { + PixmapPtr pPixmap; /* Pixmap of the area to draw */ + int rectWidth; /* Width of the rect to be drawn */ + int rectHeight; /* Height of the rect to be drawn */ + BoxPtr pBox; /* current rectangle to fill */ + int nBox; /* Number of rectangles to fill */ + int xoffset, yoffset; + Bool AlreadySetup = FALSE; + int maxlines, y; + + pPixmap = pGC->stipple; + + for (nBox = nBoxInit, pBox = pBoxInit; nBox > 0; nBox--, pBox++) { + + rectWidth = pBox->x2 - pBox->x1; + rectHeight = pBox->y2 - pBox->y1; + + if ((rectWidth > 0) && (rectHeight > 0)) { + if(!AlreadySetup) { + xf86AccelInfoRec.SetupForCPUToScreenColorExpand( + (pGC->fillStyle == FillStippled) ? -1 : pGC->bgPixel, + pGC->fgPixel, pGC->alu, pGC->planemask); + AlreadySetup = TRUE; + } + y = pBox->y1; + + xoffset = (pBox->x1 - (pGC->patOrg.x + pDrawable->x)) + % pPixmap->drawable.width; + if (xoffset < 0) + xoffset += pPixmap->drawable.width; + yoffset = (y - (pGC->patOrg.y + pDrawable->y)) + % pPixmap->drawable.height; + if (yoffset < 0) + yoffset += pPixmap->drawable.height; + + maxlines = MAX_BLIT_PIXELS / rectWidth; + + while(rectHeight > maxlines) { + xf86AccelInfoRec.SubsequentCPUToScreenColorExpand( + pBox->x1, y, rectWidth, maxlines, 0); + MGAFillStippledCPUToScreenColorExpand( + pBox->x1, y, (rectWidth + 31) >> 5, maxlines, + pPixmap->devPrivate.ptr, pPixmap->devKind, + pPixmap->drawable.width, pPixmap->drawable.height, + xoffset, yoffset); + rectHeight -= maxlines; + y += maxlines; + } + + xf86AccelInfoRec.SubsequentCPUToScreenColorExpand( + pBox->x1, y, rectWidth, rectHeight, 0); + MGAFillStippledCPUToScreenColorExpand( + pBox->x1, y, (rectWidth + 31) >> 5, rectHeight, + pPixmap->devPrivate.ptr, pPixmap->devKind, + pPixmap->drawable.width, pPixmap->drawable.height, + xoffset, yoffset); + } + } /* end for loop through each rectangle to draw */ + + MGAStormSync(); + } *** ./programs/Xserver/hw/xfree86/vga256/drivers/nv/Imakefile@@/PUBLIC-LATEST Sat Jul 19 10:41:21 1997 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/Imakefile Fri Mar 6 16:51:17 1998 *************** *** 1,14 **** ! XCOMM $TOG: Imakefile /main/3 1997/07/19 10:41:22 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/Imakefile,v 3.2 1996/12/27 07:05:41 dawes Exp $ #include <Server.tmpl> ! SRCS = nv_driver.c ! OBJS = nv_driver.o DEFINES = -DPSZ=8 --- 1,14 ---- ! XCOMM $TOG: Imakefile /main/4 1998/03/06 16:52:55 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/Imakefile,v 3.2.2.1 1998/01/18 10:35:35 hohndel Exp $ #include <Server.tmpl> ! SRCS = nv_driver.c nv1driver.c nv3driver.c nvaccel.c nv1setup.c nv3setup.c nv1cursor.c nv3cursor.c ! OBJS = nv_driver.o nv1driver.o nv3driver.o nvaccel.o nv1setup.o nv3setup.o nv1cursor.o nv3cursor.o DEFINES = -DPSZ=8 *************** *** 17,23 **** #else INCLUDES = -I. -I$(XF86COMSRC) -I$(XF86HWSRC) -I$(XF86OSSRC) \ -I$(SERVERSRC)/mfb -I$(SERVERSRC)/mi \ ! -I$(SERVERSRC)/cfb -I../../vga \ -I$(FONTINCSRC) -I$(SERVERSRC)/include -I$(XINCLUDESRC) #endif --- 17,23 ---- #else INCLUDES = -I. -I$(XF86COMSRC) -I$(XF86HWSRC) -I$(XF86OSSRC) \ -I$(SERVERSRC)/mfb -I$(SERVERSRC)/mi \ ! -I$(SERVERSRC)/cfb -I../../vga -I../../../xaa \ -I$(FONTINCSRC) -I$(SERVERSRC)/include -I$(XINCLUDESRC) #endif *************** *** 29,36 **** NormalRelocatableTarget(nv_drv,$(OBJS)) ! InstallLinkKitNonExecFile(nv_driver.c,$(LINKKITDIR)/drivers/vga256/nv) InstallLinkKitNonExecFile(nvreg.h,$(LINKKITDIR)/drivers/vga256/nv) InstallLinkKitNonExecFile(Imakefile,$(LINKKITDIR)/drivers/vga256/nv) DependTarget() --- 29,48 ---- NormalRelocatableTarget(nv_drv,$(OBJS)) ! InstallLinkKitNonExecFile(nv1ref.h,$(LINKKITDIR)/drivers/vga256/nv) ! InstallLinkKitNonExecFile(nv3ref.h,$(LINKKITDIR)/drivers/vga256/nv) InstallLinkKitNonExecFile(nvreg.h,$(LINKKITDIR)/drivers/vga256/nv) + InstallLinkKitNonExecFile(nvuser.h,$(LINKKITDIR)/drivers/vga256/nv) + InstallLinkKitNonExecFile(nvvga.h,$(LINKKITDIR)/drivers/vga256/nv) + InstallLinkKitNonExecFile(nvcursor.h,$(LINKKITDIR)/drivers/vga256/nv) + InstallLinkKitNonExecFile(nv1cursor.c,$(LINKKITDIR)/drivers/vga256/nv) + InstallLinkKitNonExecFile(nv3cursor.c,$(LINKKITDIR)/drivers/vga256/nv) + InstallLinkKitNonExecFile(nv_driver.c,$(LINKKITDIR)/drivers/vga256/nv) + InstallLinkKitNonExecFile(nv1driver.c,$(LINKKITDIR)/drivers/vga256/nv) + InstallLinkKitNonExecFile(nv3driver.c,$(LINKKITDIR)/drivers/vga256/nv) + InstallLinkKitNonExecFile(nvaccel.c,$(LINKKITDIR)/drivers/vga256/nv) + InstallLinkKitNonExecFile(nv1setup.c,$(LINKKITDIR)/drivers/vga256/nv) + InstallLinkKitNonExecFile(nv3setup.c,$(LINKKITDIR)/drivers/vga256/nv) InstallLinkKitNonExecFile(Imakefile,$(LINKKITDIR)/drivers/vga256/nv) DependTarget() *** ./programs/Xserver/hw/xfree86/vga256/drivers/nv/nv_driver.c@@/PUBLIC-LATEST Sat Jul 19 10:41:27 1997 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/nv_driver.c Fri Mar 6 16:52:10 1998 *************** *** 1,6 **** ! /* $TOG: nv_driver.c /main/4 1997/07/19 10:41:29 kaleb $ */ /* ! * Copyright 1996 David J. McKay * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), --- 1,6 ---- ! /* $TOG: nv_driver.c /main/5 1998/03/06 16:53:47 kaleb $ */ /* ! * Copyright 1996-1997 David J. McKay * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), *************** *** 21,29 **** * SOFTWARE. */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/nv_driver.c,v 3.5.2.2 1997/05/09 07:15:44 hohndel Exp $ */ #include <math.h> #include "X.h" #include "input.h" #include "screenint.h" --- 21,32 ---- * SOFTWARE. */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/nv_driver.c,v 3.5.2.5 1998/02/07 09:23:34 hohndel Exp $ */ #include <math.h> + #include <stdlib.h> + + #include "X.h" #include "input.h" #include "screenint.h" *************** *** 53,139 **** #include "extensions/xf86dgastr.h" #endif ! /* ! * This header is required for drivers that implement NVFbInit(). ! */ ! #if !defined(MONOVGA) && !defined(XF86VGA16) ! #include "vga256.h" ! #endif ! ! #define NV_1764_MAX_CLOCK_IN_KHZ 170000 ! #define NV_1732_MAX_CLOCK_IN_KHZ 135000 ! ! #define NV_MAX_VCLK_PIN_CLOCK_IN_KHZ 50000 ! ! #include "nvreg.h" ! /* This holds the pointer to the ramdac micro port */ ! volatile int *nvPort = NULL; - /* Function to read extended register */ - - static int MapNvRegs(void *base) - { - nvPort=(int *)xf86MapVidMem(vga256InfoRec.scrnIndex,LINEAR_REGION, - (pointer)base,NV_FRAME_BUFFER); - } - - /* - * Driver data structures. - */ - typedef struct { - vgaHWRec std; /* good old IBM VGA */ - /* These values hold the params for the programmable PLL */ - unsigned char Nparam, Mparam, Oparam, Pparam; - unsigned char dacConfReg0; - unsigned char dacConfReg1; - unsigned char dacRgbPalCtrl; - unsigned long confReg0; - unsigned long memoryTrace; - unsigned long startAddr; /* Where to start readin out from the buffer */ - /* All the following registers control the display */ - unsigned long prmConfig0; /* Controls if text mode on or off */ - unsigned long horFrontPorch; /* Front porch in pixels */ - unsigned long horSyncWidth; /* Sync Width in pixels */ - unsigned long horBackPorch; /* horizontal back porch in in pixels */ - unsigned long horDispWidth; /* Horizontal display width in pixels */ - unsigned long verFrontPorch; /* Vertical front porch in lines */ - unsigned long verSyncWidth; /* Vertical sync width in lines */ - unsigned long verBackPorch; /* Vertical back porch in lines */ - unsigned long verDispWidth; /* Vertical display width in lines */ - } vgaNVRec, *vgaNVPtr; - - /* - * Forward definitions for the functions that make up the driver. See - * the definitions of these functions for the real scoop. - */ - static Bool NVProbe(void); static char *NVIdent(int n); ! static void NVEnterLeave(Bool enter); ! static Bool NVInit(DisplayModePtr mode); ! static int NVValidMode(DisplayModePtr mode,Bool verbose, int flag); ! static void *NVSave(void *data); ! static void NVRestore(void *data); ! static void NVAdjust(int x,int y); - vgaVideoChipRec NV = { NVProbe, NVIdent, ! NVEnterLeave, ! NVInit, ! NVValidMode, ! NVSave, ! NVRestore, ! NVAdjust, ! vgaHWSaveScreen, ! (void (*)())NoopDDA, ! (void (*)())NoopDDA, ! (void (*)())NoopDDA, ! (void (*)())NoopDDA, ! (void (*)())NoopDDA, 0x10000,/* This is the size of the mapped memory window, usually 64k */ 0x10000,/* This is the size of a video memory bank for this chipset */ 16, /* Number of bits to shift addressto determine the bank number */ --- 56,87 ---- #include "extensions/xf86dgastr.h" #endif ! /* Little hack to declare all the base pointers */ ! #define extern #include "nvreg.h" + #undef extern ! #include "nvvga.h" static char *NVIdent(int n); ! static Bool NVProbe(void); vgaVideoChipRec NV = { NVProbe, NVIdent, ! NULL, /* EnterLeave */ ! NULL, /* Init */ ! NULL, /* ValidMode */ ! NULL, /* Save */ ! NULL, /* Restore */ ! NULL, /* Adjust */ ! NULL, /* SaveScreen */ ! NULL, /* GetMode */ ! NULL, /* FbInit */ ! (void (*)(int))NoopDDA, /* We always assume linear memory */ ! (void (*)(int))NoopDDA, ! (void (*)(int))NoopDDA, 0x10000,/* This is the size of the mapped memory window, usually 64k */ 0x10000,/* This is the size of a video memory bank for this chipset */ 16, /* Number of bits to shift addressto determine the bank number */ *************** *** 147,606 **** 8, /* Multiple to which the virtual width rounded */ TRUE, /* Support linear-mapped frame buffer */ 0, /* Physical base address of the linear-mapped frame buffer */ ! 0 , /* Size of the linear-mapped frame buffer */ ! TRUE, /* Support for 16 bpp */ ! FALSE, /* Support for 24 bpp */ ! FALSE, /* Support for 32 bpp */ NULL, /* Pointer to a list of builtin driver modes */ ! 1, /* Scale factor used to multiply the raw clocks to pixel clocks */ ! 1 /* Scale factor used to divide the raw clocks to pixel clocks */ }; ! /* ! * This is a convenience macro, so that entries in the driver structure ! * can simply be dereferenced with 'new->xxx'. ! */ ! #define new ((vgaNVPtr)vgaNewVideoState) ! static char *NVIdent(int n) { ! static char *chipsets[]={"NV1", "STG2000"}; ! ! if(n + 1 > sizeof (chipsets) / sizeof (char *)) { ! return NULL; ! }else { ! return (chipsets[n]); ! } } ! #define VPLL_INPUT_FREQ 12096.0 ! #define PLL_LOWER_BOUND 64000 ! #define PLL_UPPER_BOUND vga256InfoRec.maxClock ! /* ! * The following equation defines the output frequency of the PLL ! * fout = ( N/(M*P) ) * fin; ! * ! * It must also obey the following restraints! ! * 1Mhz <= fin/M <= 2Mhz (This means M in the range 12 -> 7) ! * ! * 64Mhz <= ((N*O)/M)*fin <=135 (or whatever the max ramdac speed is) ! * ! * The following function simple does a brute force search I'm afraid. ! * I know that it is possible to write a much faster function, but ! * there are more important things to work on, and at least I know ! * this one will always get the right answer! ! */ ! static int NVClockSelect(float clockIn,float *clockOut, ! int *Mparam,int *Nparam,int *Oparam,int *Pparam) ! { ! int m,n,o,p; ! float bestDiff=1e10; /* Set to silly value for first range */ ! float target=0.0; ! float best=0.0; - *clockOut=0; - for(p=1;p<=8;p*=2) { - float fp=(float)p; - for(n=8;n<=255;n++) { - float fn=(float)n; - for(m=12;m>=7;m--) { - float fm=(float)m; - for(o=1;o<=15;o++) { - float fo=(float) o; - float check= ((fn*fo)/fm)*VPLL_INPUT_FREQ; - if(check>PLL_LOWER_BOUND && check <= PLL_UPPER_BOUND) break; - } - if(o!=16) { - float diff; - target=(fn/(fm*fp))*VPLL_INPUT_FREQ; - diff=fabs(target - clockIn); - if(diff < bestDiff) { - bestDiff=diff; - best=target; - *Mparam=m;*Nparam=n;*Oparam=o;*Pparam=p; - *clockOut=best; - } - } - } - } - } - return (best!=0.0); - } ! static void * NVMemBase(void) ! { ! int idx=0; ! void *ret=NULL; ! pciConfigPtr pcrp,*pciList; - pciList=xf86scanpci(vga256InfoRec.scrnIndex); - if(pciList==NULL) { - ErrorF("%s %s: %s: No PCI devices present\n", - XCONFIG_PROBED, vga256InfoRec.name, vga256InfoRec.chipset); - return NULL; - } ! while(pcrp = pciList[idx]) { ! #ifdef DEBUG ! ErrorF("PCI[%d]: Vendor:0x%X, Device:0x%X, Base:0x%X\n", ! idx, pcrp->_vendor, pcrp->_device, pcrp->_base0); ! #endif ! if((pcrp->_vendor == PCI_VENDOR_NVIDIA ! && (pcrp->_device & 0xFFFB) == PCI_CHIP_DAC64) || ! (pcrp->_vendor == PCI_VENDOR_SGS ! && (pcrp->_device & 0xFFFB) == PCI_CHIP_STG1764)) { ! if(pcrp->_base0 != 0) { ! ret = (void*) (pcrp->_base0 & 0xFF800000); ! break; ! } ! } ! idx++; ! } ! if(ret == NULL) { ! ErrorF("%s %s: %s: Can't find valid PCI Base Address\n", ! XCONFIG_PROBED, vga256InfoRec.name, vga256InfoRec.chipset); ! } ! return ret; ! } ! static int pixelPortWidth=0; /* Holds how big it is,needed in NVInit() */ ! ! static int ProbeRamdac(void) { ! int id=ReadExtReg(NV_DAC_COMPANY_ID); ! if(id!=NV_DAC_SGS_ID) { ! ErrorF("Unsupported RAMDAC (vendor number 0x%02x)\n",id); ! return 0; ! } ! /* Figure out what sort of RAMDAC we have. I don't know if the RAMDACS ! * have different PCI device numbers, but this test will always work ! */ ! switch(id=ReadExtReg(NV_DAC_DEVICE_ID)) { ! case NV_DAC_1764_ID: ! /* I believe all Diamond Edge3D boards use the 1764 */ ! vga256InfoRec.maxClock = NV_1764_MAX_CLOCK_IN_KHZ; ! break; ! case NV_DAC_1732_ID: ! vga256InfoRec.maxClock = NV_1732_MAX_CLOCK_IN_KHZ; ! break; ! default: ! ErrorF("Unsupported SGS RAMDAC (id number 0x%02x)\n",id); ! return 0; ! break; ! } ! /* We need to figure out what the pixel port width is. This depends ! * on memory configuration etc, so we read it here so the NVInit() ! * function can put it back in. ! */ ! pixelPortWidth=GETBITFIELD(ReadExtReg(NV_DAC_CONF_0), ! NV_DAC_CONF_0_PORT_WIDTH); ! return 1; } static Bool NVProbe(void) { ! void *base; ! int ramdacId; ! /* Check if the user has forced the chipset */ ! if(vga256InfoRec.chipset) { ! int i = 0; ! char *chipName; ! while((chipName = NVIdent (i++)) != NULL) { ! if(!StrCaseCmp(vga256InfoRec.chipset, chipName)) ! break; } ! if(!chipName) return FALSE; ! }else { ! /* Now we must scan the PCI data structures to test for the NV1/STG200 */ ! ! if(!vgaPCIInfo) return FALSE; /* No PCI - no NV */ ! ! if(vgaPCIInfo->Vendor==PCI_VENDOR_NVIDIA && ! vgaPCIInfo->ChipType==PCI_CHIP_NV1) { ! vga256InfoRec.chipset=NVIdent(0); ! }else if(vgaPCIInfo->Vendor==PCI_VENDOR_SGS && ! vgaPCIInfo->ChipType==PCI_CHIP_STG2000) { ! vga256InfoRec.chipset=NVIdent(1); ! }else { return FALSE; } } - /* I/o ports are needed for things like pallete selection etc */ - xf86ClearIOPortList (vga256InfoRec.scrnIndex); - xf86AddIOPorts(vga256InfoRec.scrnIndex,Num_VGA_IOPorts,VGA_IOPorts); - - if((base=NVMemBase())==NULL) return FALSE; - NV.ChipLinearBase=(int)base+NV_FRAME_BUFFER; - /* Now memory map the registers */ - MapNvRegs((pointer)base); - - /* Calculate how much RAM, unless user supplies */ - if(!vga256InfoRec.videoRam) { - vga256InfoRec.videoRam = 1024 << - GETBITFIELD(nvPort[NV_PFB_BOOT_0],NV_PFB_BOOT_0_RAM_AMOUNT); - } - NV.ChipLinearSize=vga256InfoRec.videoRam*1024; - /* Now force programmable clock */ OFLG_SET(CLOCK_OPTION_PROGRAMABLE,&vga256InfoRec.clockOptions); - vga256InfoRec.clocks = 0; ! if(!ProbeRamdac()) return FALSE; ! ! #ifndef MONOVGA #ifdef XFreeXDGA vga256InfoRec.directMode = XF86DGADirectPresent; #endif - #endif vga256InfoRec.bankedMono = FALSE; - - NVEnterLeave(ENTER); - vgaIOBase = (inb (0x3CC) & 0x01) ? 0x3D0 : 0x3B0; - return (TRUE); - } - /* - * NVEnterLeave -- - * - * This function is called when the virtual terminal on which the server - * is running is entered or left, as well as when the server starts up - * and is shut down. Its function is to obtain and relinquish I/O - * permissions for the SVGA device. This includes unlocking access to - * any registers that may be protected on the chipset, and locking those - * registers again on exit. - */ - static void NVEnterLeave(Bool enter) - { - unsigned char temp; ! #ifndef MONOVGA ! #ifdef XFreeXDGA ! if(vga256InfoRec.directMode&XF86DGADirectGraphics && !enter) return; ! #endif ! #endif ! ! if (enter) { ! xf86EnableIOPorts (vga256InfoRec.scrnIndex); ! } else { ! xf86DisableIOPorts (vga256InfoRec.scrnIndex); ! } ! } ! ! /* ! * NVRestore -- ! * ! * This function restores a video mode. It basically writes out all of ! * the registers that have previously been saved in the vgaNVRec data ! * structure. ! * ! * Note that "Restore" is a little bit incorrect. This function is also ! * used when the server enters/changes video modes. The mode definitions ! * have previously been initialized by the Init() function, below. ! */ ! static void NVRestore(void *data) ! { ! vgaNVPtr restore = data; ! vgaProtect(TRUE); ! ! /* ! * This function handles restoring the generic VGA registers. ! */ ! vgaHWRestore ((vgaHWPtr) restore); ! ! /* Set the clock registers */ ! nvPort[NV_MEMORY_TRACE]=restore->memoryTrace; ! nvPort[NV_PRM_CONFIG_0]=restore->prmConfig0; ! ! WriteExtReg(NV_DAC_VPLL_M_PARAM,restore->Mparam); ! WriteExtReg(NV_DAC_VPLL_N_PARAM,restore->Nparam); ! WriteExtReg(NV_DAC_VPLL_O_PARAM,restore->Oparam); ! WriteExtReg(NV_DAC_VPLL_P_PARAM,restore->Pparam); ! ! /* Set the dac conf reg that sets the pixel depth */ ! WriteExtReg(NV_DAC_CONF_0,restore->dacConfReg0); ! WriteExtReg(NV_DAC_CONF_1,restore->dacConfReg1); ! WriteExtReg(NV_DAC_RGB_PAL_CTRL,restore->dacRgbPalCtrl); ! ! /* Write out the registers that control the dumb framebuffer */ ! nvPort[NV_PFB_CONFIG_0]=restore->confReg0; ! nvPort[NV_PFB_START]=restore->startAddr; ! ! nvPort[NV_PFB_HOR_FRONT_PORCH]=restore->horFrontPorch; ! nvPort[NV_PFB_HOR_SYNC_WIDTH]=restore->horSyncWidth; ! nvPort[NV_PFB_HOR_BACK_PORCH]=restore->horBackPorch; ! nvPort[NV_PFB_HOR_DISP_WIDTH]=restore->horDispWidth; ! nvPort[NV_PFB_VER_FRONT_PORCH]=restore->verFrontPorch; ! nvPort[NV_PFB_VER_SYNC_WIDTH]=restore->verSyncWidth; ! nvPort[NV_PFB_VER_BACK_PORCH]=restore->verBackPorch; ! nvPort[NV_PFB_VER_DISP_WIDTH]=restore->verDispWidth; ! ! vgaProtect(FALSE); ! } ! ! /* ! * NVSave -- ! * ! * This function saves the video state. It reads all of the SVGA registers ! * into the vgaNVRec data structure. There is in general no need to ! * mask out bits here - just read the registers. ! */ ! static void *NVSave(void *data) ! { ! vgaNVPtr save = data; ! /* ! * This function will handle creating the data structure and filling ! * in the generic VGA portion. ! */ ! save = (vgaNVPtr) vgaHWSave ((vgaHWPtr) save, sizeof (vgaNVRec)); ! ! save->prmConfig0=nvPort[NV_PRM_CONFIG_0]; ! save->memoryTrace=nvPort[NV_MEMORY_TRACE]; ! ! save->dacConfReg0=ReadExtReg(NV_DAC_CONF_0); ! save->dacConfReg1=ReadExtReg(NV_DAC_CONF_1); ! save->dacRgbPalCtrl=ReadExtReg(NV_DAC_RGB_PAL_CTRL); ! save->Mparam=ReadExtReg(NV_DAC_VPLL_M_PARAM); ! save->Nparam=ReadExtReg(NV_DAC_VPLL_N_PARAM); ! save->Oparam=ReadExtReg(NV_DAC_VPLL_O_PARAM); ! save->Pparam=ReadExtReg(NV_DAC_VPLL_P_PARAM); ! ! save->confReg0=nvPort[NV_PFB_CONFIG_0]; ! save->startAddr=nvPort[NV_PFB_START]; ! ! save->horFrontPorch=nvPort[NV_PFB_HOR_FRONT_PORCH]; ! save->horSyncWidth=nvPort[NV_PFB_HOR_SYNC_WIDTH]; ! save->horBackPorch=nvPort[NV_PFB_HOR_BACK_PORCH]; ! save->horDispWidth=nvPort[NV_PFB_HOR_DISP_WIDTH]; ! save->verFrontPorch=nvPort[NV_PFB_VER_FRONT_PORCH]; ! save->verSyncWidth=nvPort[NV_PFB_VER_SYNC_WIDTH]; ! save->verBackPorch=nvPort[NV_PFB_VER_BACK_PORCH]; ! save->verDispWidth=nvPort[NV_PFB_VER_DISP_WIDTH]; ! ! return ((void *) save); ! } ! ! ! static int VirtualScreenOk(DisplayModePtr mode) ! { ! if(mode->CrtcHDisplay!=vga256InfoRec.virtualX) return 0; ! ! if(mode->Flags & V_DBLSCAN) { ! return (2*vga256InfoRec.virtualY==mode->CrtcVDisplay); ! } ! ! return (vga256InfoRec.virtualY==mode->CrtcVDisplay); ! } ! ! static Bool NVInit(DisplayModePtr mode) ! { ! int bppShift=(vgaBitsPerPixel==8) ? 1 : 2; ! int m,n,o,p; ! float clockIn=(float)vga256InfoRec.clock[mode->Clock]; ! float clockOut; ! int pclkVclkRatio; ! int i; ! ! /* Check to see that we are not trying to do a virtual screen */ ! if(!VirtualScreenOk(mode)) { ! ErrorF("%s %s: %s: Can't select mode %s : virtual desktop not supported\n", ! XCONFIG_PROBED, vga256InfoRec.name,vga256InfoRec.chipset,mode->name); ! return FALSE; ! } ! ! if(!NVClockSelect(clockIn,&clockOut,&m,&n,&o,&p)) { ! ErrorF("Unable to set desired clock\n"); ! return FALSE; ! ! } ! /* Figure out divide down for clock. The Vclk pin is rated for ! * 25-50Mhz but can actually be driven higher than this on most ! * silicon ! */ ! for(i=1,pclkVclkRatio=0;i<=16;i*=2,pclkVclkRatio++) { ! if((clockOut/(double)i) <= NV_MAX_VCLK_PIN_CLOCK_IN_KHZ) break; ! } ! ! ErrorF("%s %s: %s: Using %.3fMhz clock\n",XCONFIG_PROBED, vga256InfoRec.name, ! vga256InfoRec.chipset,clockOut/1000); ! ! ! /* ! * This will allocate the datastructure and initialize all of the ! * generic VGA registers. ! */ ! ! if (!vgaHWInit (mode, sizeof (vgaNVRec))) { ! return (FALSE); ! } ! ! new->Mparam=m;new->Nparam=n;new->Oparam=o;new->Pparam=p; ! new->dacConfReg0=0; ! SETBITFIELD(new->dacConfReg0,NV_DAC_CONF_0_VGA_STATE,1); ! SETBITFIELD(new->dacConfReg0,NV_DAC_CONF_0_PORT_WIDTH,pixelPortWidth); ! SETBITFIELD(new->dacConfReg0,NV_DAC_CONF_0_VISUAL_DEPTH,bppShift); ! SETBITFIELD(new->dacConfReg0,NV_DAC_CONF_0_IDC_MODE,vgaBitsPerPixel==8); ! ! new->dacConfReg1=0; ! SETBITFIELD(new->dacConfReg1,NV_DAC_CONF_1_VCLK_IMPEDANCE,1); ! SETBITFIELD(new->dacConfReg1,NV_DAC_CONF_1_PCLK_VCLK_RATIO,pclkVclkRatio); ! ! new->dacRgbPalCtrl=0; ! new->prmConfig0=0; ! new->memoryTrace=0; ! ! new->confReg0=0; ! /* We should set resolution here, but it doesn't seem to do anything */ ! SETBITFIELD(new->confReg0,NV_PFB_CONFIG_0_PIXEL_DEPTH,bppShift); ! SETBITFIELD(new->confReg0,NV_PFB_CONFIG_0_PCLK_VCLK_RATIO,pclkVclkRatio); ! SETBITFIELD(new->confReg0,NV_PFB_CONFIG_0_RESOLUTION,4); ! ! new->startAddr=0; ! /* Calculate the monitor timings */ ! new->horFrontPorch=mode->CrtcHSyncStart - mode->CrtcHDisplay+1; ! new->horBackPorch=mode->CrtcHTotal - mode->CrtcHSyncEnd+1; ! new->horSyncWidth=mode->CrtcHSyncEnd - mode->CrtcHSyncStart+1; ! ! new->horDispWidth=mode->CrtcHDisplay; ! ! new->verFrontPorch=mode->CrtcVSyncStart - mode->CrtcVDisplay+1; ! new->verBackPorch=mode->CrtcVTotal - mode->CrtcVSyncEnd+1; ! new->verSyncWidth=mode->CrtcVSyncEnd - mode->CrtcVSyncStart+1; ! new->verDispWidth=mode->CrtcVDisplay; ! ! /* Probably need a bit more in here */ ! if(mode->Flags & V_DBLSCAN) { ! SETBITFIELD(new->confReg0,NV_PFB_CONFIG_0_SCANLINE,1); ! } ! ! return (TRUE); ! } ! ! /* ! * NVAdjust -- ! * ! * This function is used to initialize the SVGA Start Address - the first ! * displayed location in the video memory. This is used to implement the ! * virtual window. ! */ ! static void NVAdjust(int x, int y) ! { ! int bppShift=(vgaBitsPerPixel==8) ? 1 : 2; ! ! /* Wait for vertical blank */ ! while(GETBITFIELD(nvPort[NV_PFB_CONFIG_0],NV_PFB_CONFIG_0_VERTICAL)==0); ! ! nvPort[NV_PFB_START]=(y * vga256InfoRec.displayWidth + x)*bppShift; ! ! } ! ! static int NVValidMode(DisplayModePtr mode,Bool verbose, int flag) ! { ! return (MODE_OK); } --- 95,200 ---- 8, /* Multiple to which the virtual width rounded */ TRUE, /* Support linear-mapped frame buffer */ 0, /* Physical base address of the linear-mapped frame buffer */ ! 0 , /* Size of the linear-mapped frame buffer */ ! TRUE, /* 16 bpp */ ! FALSE, /* 24 bpp */ ! FALSE, /* 32 bpp */ NULL, /* Pointer to a list of builtin driver modes */ ! 1, /* Scale factor used to scale the raw clocks to pixel clocks */ ! 1 }; ! static NVChipType chipis=NV1; ! NVChipType GetChipType(void) { ! return chipis; } ! typedef Bool (*NVProbeFuncType)(vgaVideoChipRec *rec,void *base0,void *base1); ! Bool NV1Probe(vgaVideoChipRec *rec,void *base0,void *base1); ! Bool NV3Probe(vgaVideoChipRec *rec,void *base0,void *base1); ! static NVProbeFuncType NVProbeFuncList[NumNVChips]= { ! NV1Probe, ! NV3Probe ! }; + typedef struct { + char *name; + NVChipType type; + int vendor; + int device; + }NVProbeInfo; ! static NVProbeInfo probeList[]={ ! { "NV1",NV1,PCI_VENDOR_NVIDIA,PCI_CHIP_DAC64}, ! { "STG2000",NV1,PCI_VENDOR_SGS,PCI_CHIP_STG1764}, ! { "RIVA128",NV3,PCI_VENDOR_NVIDIA_SGS,PCI_CHIP_RIVA128} ! }; ! #define NUM_PROBE_ENTRIES (sizeof(probeList)/sizeof(NVProbeInfo)) ! static char *NVIdent(int n) { ! if( (n<0) || (n>=NUM_PROBE_ENTRIES)) return NULL; ! return probeList[n].name; } + static Bool NVProbe(void) { ! int i; ! void *base0=NULL,*base1=NULL; ! Bool ret; ! int idx=0,found=0; ! pciConfigPtr pcrp,*pciList; ! int noaccelSet; ! /* first things first; if a chipset is given, then we check if it is ! one we support, otherwise we silently go away... */ ! if (vga256InfoRec.chipset) { ! char *chipset; ! for (i = 0; (chipset = NVIdent(i)); i++) { ! if (!StrCaseCmp(vga256InfoRec.chipset, chipset)) ! break; } ! if (!chipset) return FALSE; + } + if (vgaPCIInfo && vgaPCIInfo->AllCards) { + pciList=vgaPCIInfo->AllCards; + while((pcrp=pciList[idx++]) && (!found)) { + for(i=0;i<NUM_PROBE_ENTRIES && !found;i++) { + if((pcrp->_vendor==probeList[i].vendor) && + ( ((pcrp->_device & 0xFFFB)==probeList[i].device) || + (vga256InfoRec.chipset && + !StrCaseCmp(vga256InfoRec.chipset,probeList[i].name)))) { + base0=(void*) (pcrp->_base0 & 0xFF800000); + base1=(void*) (pcrp->_base1 & 0xFF800000); + chipis=probeList[i].type; + vga256InfoRec.chipset=probeList[i].name; + found=1; + } + } } } + if(!found) return FALSE; /* Now force programmable clock */ OFLG_SET(CLOCK_OPTION_PROGRAMABLE,&vga256InfoRec.clockOptions); ! vga256InfoRec.clocks = 0; #ifdef XFreeXDGA vga256InfoRec.directMode = XF86DGADirectPresent; #endif vga256InfoRec.bankedMono = FALSE; ! return NVProbeFuncList[GetChipType()](&NV,base0,base1); } *** ./programs/Xserver/hw/xfree86/vga256/drivers/nv/nvreg.h@@/PUBLIC-LATEST Sat Jul 19 10:41:34 1997 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/nvreg.h Fri Mar 6 16:52:22 1998 *************** *** 1,130 **** ! /* $TOG: nvreg.h /main/3 1997/07/19 10:41:36 kaleb $ */ ! /***************************************************************************\ ! |* *| ! |* Copyright (c) 1996 NVIDIA, Corp. All rights reserved. *| ! |* *| ! |* NOTICE TO USER: The source code is copyrighted under U.S. and *| ! |* international laws. NVIDIA, Corp. of Sunnyvale, California owns *| ! |* the copyright and as design patents pending on the design and *| ! |* interface of the NV chips. Users and possessors of this source *| ! |* code are hereby granted a nonexclusive, royalty-free copyright *| ! |* and design patent license to use this code in individual and *| ! |* commercial software. *| ! |* *| ! |* Any use of this source code must include, in the user documenta- *| ! |* tion and internal comments to the code, notices to the end user *| ! |* as follows: *| ! |* *| ! |* Copyright (c) 1996 NVIDIA, Corp. NVIDIA design patents pending *| ! |* in the U.S. and foreign countries. *| ! |* *| ! |* NVIDIA, CORP. MAKES NO REPRESENTATION ABOUT THE SUITABILITY OF *| ! |* THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" WITHOUT *| ! |* EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORP. DISCLAIMS *| ! |* ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, INCLUDING ALL *| ! |* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *| ! |* PARTICULAR PURPOSE. IN NO EVENT SHALL NVIDIA, CORP. BE LIABLE *| ! |* FOR ANY SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, *| ! |* OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR *| ! |* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER *| ! |* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR *| ! |* PERFORMANCE OF THIS SOURCE CODE. *| ! |* *| ! \***************************************************************************/ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/nvreg.h,v 3.2 1996/12/27 07:05:43 dawes Exp $ */ #ifndef __NVREG_H_ #define __NVREG_H_ ! #define NV_FRAME_BUFFER 0x01000000 /* Frame buffer is at this BYTE address*/ ! /* Frame buffer registers */ ! #define NV_PFB_BOOT_0 (0x600000/4) ! #define NV_PFB_CONFIG_0 (0x600200/4) ! #define NV_PFB_START (0x600400/4) ! #define NV_PFB_HOR_FRONT_PORCH (0x600500/4) ! #define NV_PFB_HOR_SYNC_WIDTH (0x600510/4) ! #define NV_PFB_HOR_BACK_PORCH (0x600520/4) ! #define NV_PFB_HOR_DISP_WIDTH (0x600530/4) ! #define NV_PFB_VER_FRONT_PORCH (0x600540/4) ! #define NV_PFB_VER_SYNC_WIDTH (0x600550/4) ! #define NV_PFB_VER_BACK_PORCH (0x600560/4) ! #define NV_PFB_VER_DISP_WIDTH (0x600570/4) ! #define NV_PFB_BOOT_0_RAM_AMOUNT 1,0 ! #define NV_PFB_CONFIG_0_VERTICAL 0,0 /* 1 during blank */ ! #define NV_PFB_CONFIG_0_PIXEL_DEPTH 9,8 ! #define NV_PFB_CONFIG_0_SCANLINE 20,20 ! #define NV_PFB_CONFIG_0_PCLK_VCLK_RATIO 26,24 ! #define NV_PFB_CONFIG_0_RESOLUTION 6,4 ! /* Text mode config registers */ ! #define NV_PRM_CONFIG_0 (0x6c0200/4) ! #define NV_MEMORY_TRACE (0x6c1f00/4) ! #define NV_PBUS_ACCESS (0x1200/4) ! /* Addreses for the DAC micro port */ ! #define NV_DAC_WRITE_PALETTE (0x609000/4) ! #define NV_DAC_COLOUR_DATA (0x609004/4) ! #define NV_DAC_PIXEL_MASK (0x609008/4) ! #define NV_DAC_READ_PALETTE (0x60900c/4) ! #define NV_DAC_INDEX_LO (0x609010/4) ! #define NV_DAC_INDEX_HI (0x609014/4) ! #define NV_DAC_INDEX_DATA (0x609018/4) ! #define NV_DAC_GAME_PORT (0x60901c/4) ! /* Extended register values */ ! #define NV_DAC_COMPANY_ID 0x00 ! #define NV_DAC_DEVICE_ID 0x01 ! #define NV_DAC_REVISION_ID 0x02 ! #define NV_DAC_CONF_0 0x04 ! #define NV_DAC_CONF_1 0x05 ! #define NV_DAC_RGB_PAL_CTRL 0x09 ! #define NV_DAC_VPLL_M_PARAM 0x18 ! #define NV_DAC_VPLL_N_PARAM 0x19 ! #define NV_DAC_VPLL_O_PARAM 0x1a ! #define NV_DAC_VPLL_P_PARAM 0x1b ! #define NV_DAC_CONF_0_IDC_MODE 5,5 ! #define NV_DAC_CONF_0_VGA_STATE 4,4 ! #define NV_DAC_CONF_0_PORT_WIDTH 3,2 ! #define NV_DAC_CONF_0_VISUAL_DEPTH 1,0 ! #define NV_DAC_CONF_1_VCLK_IMPEDANCE 3,3 ! #define NV_DAC_CONF_1_PCLK_VCLK_RATIO 2,0 ! #define NV_DAC_SGS_ID 0x44 ! #define NV_DAC_1764_ID 0x64 ! #define NV_DAC_1732_ID 0x32 ! /* This points at the base of the memory mapped for the NV1 ! * Note that it is an int pointer, all writes must be 32 bit ! */ ! extern volatile int *nvPort; ! #define ReadExtReg(reg) \ ! ((nvPort[NV_DAC_INDEX_LO] = (reg) & 0xff),\ ! (nvPort[NV_DAC_INDEX_HI] = ((reg) >> 8) & 0xff),\ ! (nvPort[NV_DAC_INDEX_DATA] & 0xff)) ! #define WriteExtReg(reg,value)\ ! nvPort[NV_DAC_INDEX_LO] = (reg) & 0xff,\ ! nvPort[NV_DAC_INDEX_HI] = ((reg) >> 8) & 0xff,\ ! nvPort[NV_DAC_INDEX_DATA] = ((value) & 0xff) ! /* Little macro to construct bitmask for contiguous ranges of bits */ ! #define BITFIELDMASK(t,b) (((unsigned)(1U << (((t)-(b)+1)))-1) << (b)) ! #define LOW_VALUE_OF_BITFIELDMASK(t,b) (b) ! /* Macro to set specific bitfields (mask has to be a macro x,y) ! */ ! #define SETBITFIELD(var,mask,value) var=((var) & (~BITFIELDMASK(mask))) | \ ! ((value) << LOW_VALUE_OF_BITFIELDMASK(mask)) ! #define GETBITFIELD(var,mask) (((unsigned)((var) & BITFIELDMASK(mask))) \ ! >> LOW_VALUE_OF_BITFIELDMASK(mask)) #endif --- 1,192 ---- ! /* $TOG: nvreg.h /main/4 1998/03/06 16:54:00 kaleb $ */ ! /* ! * Copyright 1996-1997 David J. McKay ! * ! * Permission is hereby granted, free of charge, to any person obtaining a ! * copy of this software and associated documentation files (the "Software"), ! * to deal in the Software without restriction, including without limitation ! * the rights to use, copy, modify, merge, publish, distribute, sublicense, ! * and/or sell copies of the Software, and to permit persons to whom the ! * Software is furnished to do so, subject to the following conditions: ! * ! * The above copyright notice and this permission notice shall be included in ! * all copies or substantial portions of the Software. ! * ! * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ! * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ! * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ! * DAVID J. MCKAY BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ! * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF ! * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE ! * SOFTWARE. ! */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/nvreg.h,v 3.2.2.1 1998/01/18 10:35:36 hohndel Exp $ */ #ifndef __NVREG_H_ #define __NVREG_H_ ! /* Little macro to construct bitmask for contiguous ranges of bits */ ! #define BITMASK(t,b) (((unsigned)(1U << (((t)-(b)+1)))-1) << (b)) ! #define MASKEXPAND(mask) BITMASK(1?mask,0?mask) ! /* Macro to set specific bitfields (mask has to be a macro x:y) ! */ ! #define SetBF(mask,value) ((value) << (0?mask)) ! #define GetBF(var,mask) (((unsigned)((var) & MASKEXPAND(mask))) >> (0?mask) ) ! #define MaskAndSetBF(var,mask,value) (var)=(((var)&(~MASKEXPAND(mask)) \ ! | SetBF(mask,value))) ! #define DEVICE_BASE(device) (0?NV##_##device) ! #define DEVICE_SIZE(device) ((1?NV##_##device) - DEVICE_BASE(device)+1) ! /* This is where we will have to have conditional compilation */ ! #define DEVICE_ACCESS(device,reg) \ ! nv##device##Port[((NV_##device##_##reg)-DEVICE_BASE(device))/4] + #define DEVICE_WRITE(device,reg,value) DEVICE_ACCESS(device,reg)=(value) + #define DEVICE_READ(device,reg) DEVICE_ACCESS(device,reg) + #define DEVICE_PRINT(device,reg) \ + ErrorF("NV_"#device"_"#reg"=#%08lx\n",DEVICE_ACCESS(device,reg)) + #define DEVICE_DEF(device,mask,value) \ + SetBF(NV_##device##_##mask,NV_##device##_##mask##_##value) + #define DEVICE_VALUE(device,mask,value) SetBF(NV_##device##_##mask,value) + #define DEVICE_MASK(device,mask) MASKEXPAND(NV_##device##_##mask) ! #define PDAC_Write(reg,value) DEVICE_WRITE(PDAC,reg,value) ! #define PDAC_Read(reg) DEVICE_READ(PDAC,reg) ! #define PDAC_Print(reg) DEVICE_PRINT(PDAC,reg) ! #define PDAC_Def(mask,value) DEVICE_DEF(PDAC,mask,value) ! #define PDAC_Val(mask,value) DEVICE_VALUE(PDAC,mask,value) ! #define PDAC_Mask(mask) DEVICE_MASK(PDAC,mask) + #define PFB_Write(reg,value) DEVICE_WRITE(PFB,reg,value) + #define PFB_Read(reg) DEVICE_READ(PFB,reg) + #define PFB_Print(reg) DEVICE_PRINT(PFB,reg) + #define PFB_Def(mask,value) DEVICE_DEF(PFB,mask,value) + #define PFB_Val(mask,value) DEVICE_VALUE(PFB,mask,value) + #define PFB_Mask(mask) DEVICE_MASK(PFB,mask) ! #define PRM_Write(reg,value) DEVICE_WRITE(PRM,reg,value) ! #define PRM_Read(reg) DEVICE_READ(PRM,reg) ! #define PRM_Print(reg) DEVICE_PRINT(PRM,reg) ! #define PRM_Def(mask,value) DEVICE_DEF(PRM,mask,value) ! #define PRM_Val(mask,value) DEVICE_VALUE(PRM,mask,value) ! #define PRM_Mask(mask) DEVICE_MASK(PRM,mask) ! #define PGRAPH_Write(reg,value) DEVICE_WRITE(PGRAPH,reg,value) ! #define PGRAPH_Read(reg) DEVICE_READ(PGRAPH,reg) ! #define PGRAPH_Print(reg) DEVICE_PRINT(PGRAPH,reg) ! #define PGRAPH_Def(mask,value) DEVICE_DEF(PGRAPH,mask,value) ! #define PGRAPH_Val(mask,value) DEVICE_VALUE(PGRAPH,mask,value) ! #define PGRAPH_Mask(mask) DEVICE_MASK(PGRAPH,mask) ! #define PDMA_Write(reg,value) DEVICE_WRITE(PDMA,reg,value) ! #define PDMA_Read(reg) DEVICE_READ(PDMA,reg) ! #define PDMA_Print(reg) DEVICE_PRINT(PDMA,reg) ! #define PDMA_Def(mask,value) DEVICE_DEF(PDMA,mask,value) ! #define PDMA_Val(mask,value) DEVICE_VALUE(PDMA,mask,value) ! #define PDMA_Mask(mask) DEVICE_MASK(PDMA,mask) ! #define PFIFO_Write(reg,value) DEVICE_WRITE(PFIFO,reg,value) ! #define PFIFO_Read(reg) DEVICE_READ(PFIFO,reg) ! #define PFIFO_Print(reg) DEVICE_PRINT(PFIFO,reg) ! #define PFIFO_Def(mask,value) DEVICE_DEF(PFIFO,mask,value) ! #define PFIFO_Val(mask,value) DEVICE_VALUE(PFIFO,mask,value) ! #define PFIFO_Mask(mask) DEVICE_MASK(PFIFO,mask) + #define PRAM_Write(reg,value) DEVICE_WRITE(PRAM,reg,value) + #define PRAM_Read(reg) DEVICE_READ(PRAM,reg) + #define PRAM_Print(reg) DEVICE_PRINT(PRAM,reg) + #define PRAM_Def(mask,value) DEVICE_DEF(PRAM,mask,value) + #define PRAM_Val(mask,value) DEVICE_VALUE(PRAM,mask,value) + #define PRAM_Mask(mask) DEVICE_MASK(PRAM,mask) + #define PRAMFC_Write(reg,value) DEVICE_WRITE(PRAMFC,reg,value) + #define PRAMFC_Read(reg) DEVICE_READ(PRAMFC,reg) + #define PRAMFC_Print(reg) DEVICE_PRINT(PRAMFC,reg) + #define PRAMFC_Def(mask,value) DEVICE_DEF(PRAMFC,mask,value) + #define PRAMFC_Val(mask,value) DEVICE_VALUE(PRAMFC,mask,value) + #define PRAMFC_Mask(mask) DEVICE_MASK(PRAMFC,mask) ! #define PMC_Write(reg,value) DEVICE_WRITE(PMC,reg,value) ! #define PMC_Read(reg) DEVICE_READ(PMC,reg) ! #define PMC_Print(reg) DEVICE_PRINT(PMC,reg) ! #define PMC_Def(mask,value) DEVICE_DEF(PMC,mask,value) ! #define PMC_Val(mask,value) DEVICE_VALUE(PMC,mask,value) ! #define PMC_Mask(mask) DEVICE_MASK(PMC,mask) ! #define PMC_Write(reg,value) DEVICE_WRITE(PMC,reg,value) ! #define PMC_Read(reg) DEVICE_READ(PMC,reg) ! #define PMC_Print(reg) DEVICE_PRINT(PMC,reg) ! #define PMC_Def(mask,value) DEVICE_DEF(PMC,mask,value) ! #define PMC_Val(mask,value) DEVICE_VALUE(PMC,mask,value) ! #define PMC_Mask(mask) DEVICE_MASK(PMC,mask) ! ! #define PBUS_Write(reg,value) DEVICE_WRITE(PBUS,reg,value) ! #define PBUS_Read(reg) DEVICE_READ(PBUS,reg) ! #define PBUS_Print(reg) DEVICE_PRINT(PBUS,reg) ! #define PBUS_Def(mask,value) DEVICE_DEF(PBUS,mask,value) ! #define PBUS_Val(mask,value) DEVICE_VALUE(PBUS,mask,value) ! #define PBUS_Mask(mask) DEVICE_MASK(PBUS,mask) ! ! ! #define PRAMDAC_Write(reg,value) DEVICE_WRITE(PRAMDAC,reg,value) ! #define PRAMDAC_Read(reg) DEVICE_READ(PRAMDAC,reg) ! #define PRAMDAC_Print(reg) DEVICE_PRINT(PRAMDAC,reg) ! #define PRAMDAC_Def(mask,value) DEVICE_DEF(PRAMDAC,mask,value) ! #define PRAMDAC_Val(mask,value) DEVICE_VALUE(PRAMDAC,mask,value) ! #define PRAMDAC_Mask(mask) DEVICE_MASK(PRAMDAC,mask) ! ! ! #define PDAC_ReadExt(reg) \ ! ((PDAC_Write(INDEX_LO,(NV_PDAC_EXT_##reg) & 0xff)),\ ! (PDAC_Write(INDEX_HI,((NV_PDAC_EXT_##reg) >> 8) & 0xff)),\ ! (PDAC_Read(INDEX_DATA))) ! ! #define PDAC_WriteExt(reg,value)\ ! ((PDAC_Write(INDEX_LO,(NV_PDAC_EXT_##reg) & 0xff)),\ ! (PDAC_Write(INDEX_HI,((NV_PDAC_EXT_##reg) >> 8) & 0xff)),\ ! (PDAC_Write(INDEX_DATA,(value)))) ! ! #define CRTC_Write(index,value) outb(0x3d4,(index));outb(0x3d5,value) ! #define CRTC_Read(index) (outb(0x3d4,index),inb(0x3d5)) ! ! #define PCRTC_Write(index,value) CRTC_Write(NV_PCRTC_##index,value) ! #define PCRTC_Read(index) CRTC_Read(NV_PCRTC_##index) ! ! #define PCRTC_Def(mask,value) DEVICE_DEF(PCRTC,mask,value) ! #define PCRTC_Val(mask,value) DEVICE_VALUE(PCRTC,mask,value) ! #define PCRTC_Mask(mask) DEVICE_MASK(PCRTC,mask) ! ! #define SR_Write(index,value) outb(0x3c4,(index));outb(0x3c5,value) ! #define SR_Read(index) (outb(0x3c4,index),inb(0x3c5)) ! ! ! /* These are the variables which actually point at the register blocks */ ! extern volatile unsigned *nvPDACPort; /* Points to the DAC */ ! extern volatile unsigned *nvPFBPort; /* Points to the Frame buffer */ ! extern volatile unsigned *nvPRMPort; /* Points to real mode stuff */ ! extern volatile unsigned *nvPGRAPHPort; /* Graphics unit */ ! extern volatile unsigned *nvPDMAPort; /* DMA engine */ ! extern volatile unsigned *nvPFIFOPort; /* FIFO registers */ ! extern volatile unsigned *nvPRAMPort; /* Priviliged RAM registers */ ! extern volatile unsigned *nvPRAMFCPort; /* Priviliged RAM (Fifo) */ ! extern volatile unsigned *nvPRAMHTPort; /* Priviliged RAM (hash) */ ! extern volatile unsigned *nvPMCPort; /* Priviliged RAM (hash) */ ! extern volatile unsigned *nvCHAN0Port; /* User channel 0 */ ! extern volatile unsigned *nvPRAMDACPort; /* Points to the RAMDAC */ ! extern volatile unsigned *nvPRAMINPort; /* Privileges instance memory */ ! extern volatile unsigned *nvPBUSPort; /* Priviled Bus */ ! extern volatile unsigned *nvPNVMPort; /* Priviled Bus */ ! extern volatile unsigned *dumb; /* FrameBuffer - hack!!!! */ ! ! ! typedef enum {NV1,NV3,NumNVChips} NVChipType; ! ! NVChipType GetChipType(void); ! #endif *** /dev/null Tue Jun 30 11:50:02 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/nv1cursor.c Fri Mar 6 16:51:34 1998 *************** *** 0 **** --- 1,396 ---- + /* $TOG: nv1cursor.c /main/1 1998/03/06 16:53:11 kaleb $ */ + + + + /* + * Copyright 1996-1997 David J. McKay + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * DAVID J. MCKAY BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/nv1cursor.c,v 1.1.2.2 1998/01/24 00:04:37 robin Exp $ */ + + #include "X.h" + #include "Xproto.h" + #include "misc.h" + #include "input.h" + #include "cursorstr.h" + #include "regionstr.h" + #include "scrnintstr.h" + #include "servermd.h" + #include "windowstr.h" + + #include "compiler.h" + #include "vga256.h" + #include "xf86.h" + #include "mipointer.h" + #include "xf86Priv.h" + #include "xf86_Option.h" + #include "xf86_OSlib.h" + #include "vga.h" + + #include "miline.h" + #include "nv1ref.h" + #include "nvreg.h" + #include "nvcursor.h" + + + static Bool NVRealizeCursor(); + static Bool NVUnrealizeCursor(); + static void NVSetCursor(); + static void NVMoveCursor(); + static void NVRecolorCursor(); + + static miPointerSpriteFuncRec NVPointerSpriteFuncs = + { + NVRealizeCursor, + NVUnrealizeCursor, + NVSetCursor, + NVMoveCursor, + }; + + /* vga256 interface defines Init, Restore, Warp, QueryBestSize. */ + + + extern miPointerScreenFuncRec xf86PointerScreenFuncs; + extern xf86InfoRec xf86Info; + + static int NVCursorGeneration = -1; + + /* + * This is the set variables that defines the cursor state within the + * driver. + */ + + static int NVCursorHotX; + static int NVCursorHotY; + static CursorPtr NVCursorpCurs; + + + /* + * This is a high-level init function, called once; it passes a local + * miPointerSpriteFuncRec with additional functions that we need to provide. + * It is called by the SVGA server. + */ + + Bool NVCursorInit(char *pm,ScreenPtr pScr) + { + unsigned char power; + + NVCursorHotX = 0; + NVCursorHotY = 0; + + + if(NVCursorGeneration != serverGeneration) { + if(!(miPointerInitialize(pScr, &NVPointerSpriteFuncs, + &xf86PointerScreenFuncs, FALSE))) { + return FALSE; + } + pScr->RecolorCursor = NVRecolorCursor; + NVCursorGeneration = serverGeneration; + } + return TRUE; + } + + /* + * This enables displaying of the cursor by the NV graphics chip. + * It's a local function, it's not called from outside of the module. + */ + + static void NVShowCursor(void) + { + PDAC_WriteExt(CURSOR_CTRL_A,NV_PDAC_CURSOR_CTRL_A_XWIN); + } + + /* + * This disables displaying of the cursor by the NV graphics chip. + * This is also a local function, it's not called from outside. + */ + void NVHideCursor(void) + { + PDAC_WriteExt(CURSOR_CTRL_A,NV_PDAC_CURSOR_CTRL_A_OFF); + } + + /* + * This function is called when a new cursor image is requested by + * the server. The main thing to do is convert the bitwise image + * provided by the server into a format that the graphics card + * can conveniently handle, and store that in system memory. + * Adapted from accel/s3/s3Cursor.c. + */ + + static Bool NVRealizeCursor(ScreenPtr pScr,CursorPtr pCurs) + { + register int i, j; + unsigned char *pServMsk; + unsigned char *pServSrc; + int index = pScr->myNum; + pointer *pPriv = &pCurs->bits->devPriv[index]; + int wsrc, h; + unsigned char *ram; + CursorBits *bits = pCurs->bits; + + /* Presumably this checks to see if this is already the cursor in there */ + if(pCurs->bits->refcnt > 1) return TRUE; + + /* What do we need ram for ???? */ + ram = (unsigned char *)xalloc(1024); + *pPriv = (pointer) ram; + if(!ram) return FALSE; + + pServSrc = (unsigned char *)bits->source; + pServMsk = (unsigned char *)bits->mask; + + #define MAX_CURS 32 + + h = bits->height; + if(h > MAX_CURS) h = MAX_CURS; + + wsrc = PixmapBytePad(bits->width, 1); /* Bytes per line. */ + + for (i = 0; i < MAX_CURS; i++) { + for (j = 0; j < MAX_CURS / 8; j++) { + unsigned char mask, source; + + if(i < h && j < wsrc) { + mask = *pServMsk++; + source = *pServSrc++; + #if 0 + /* We don't need to do this on the NV1, as it supports bitmaps + * in the "right" order + */ + mask = byte_reversed[mask]; + source = byte_reversed[source]; + #endif + if(j < MAX_CURS / 8) { /* ??? */ + *ram++ = mask; + *ram++ = source; + } + } else { + *ram++ = 0x00; + *ram++ = 0xFF; + } + } + /* + * if we still have more bytes on this line (j < wsrc), + * we have to ignore the rest of the line. + */ + while (j++ < wsrc) + pServMsk++, pServSrc++; + } + return TRUE; + } + + /* + * This is called when a cursor is no longer used. The intermediate + * cursor image storage that we created needs to be deallocated. + */ + + static Bool NVUnrealizeCursor(ScreenPtr pScr,CursorPtr pCurs) + { + pointer priv; + + if(pCurs->bits->refcnt <= 1 && + (priv = pCurs->bits->devPriv[pScr->myNum])) { + xfree(priv); + pCurs->bits->devPriv[pScr->myNum] = 0x0; + } + return TRUE; + } + + /* + * This function uploads a cursor image to the video memory of the + * graphics card. The source image has already been converted by the + * Realize function to a format that can be quickly transferred to + * the card. + * This is a local function that is not called from outside of this + * module. + */ + + extern void NVSetWrite(); + + static void NVLoadCursorToCard(ScreenPtr pScr,CursorPtr pCurs,int x,int y) + { + unsigned char *cursor_image,*p; + int index = pScr->myNum; + int i; + + if(!xf86VTSema) + return; + + p=cursor_image = pCurs->bits->devPriv[index]; + /* Upload the cursor to the card */ + for(i=0;i<MAX_CURS*4;i++) { + PDAC_WriteExt(CURSOR_PLANE_1+i,*p++); + PDAC_WriteExt(CURSOR_PLANE_0+i,*p++); + } + + } + + /* + * This function should make the graphics chip display new cursor that + * has already been "realized". We need to upload it to video memory, + * make the graphics chip display it. + * This is a local function that is not called from outside of this + * module (although it largely corresponds to what the SetCursor + * function in the Pointer record needs to do). + */ + + static void NVLoadCursor(ScreenPtr pScr,CursorPtr pCurs,int x,int y) + { + if(!xf86VTSema) + return; + + if(!pCurs) + return; + + /* Remember the cursor currently loaded into this cursor slot. */ + NVCursorpCurs = pCurs; + + NVHideCursor(); + + NVLoadCursorToCard(pScr, pCurs, x, y); + + NVRecolorCursor(pScr, pCurs, 1); + + /* Position cursor */ + NVMoveCursor(pScr, x, y); + + /* Turn it on. */ + NVShowCursor(); + } + + /* + * This function should display a new cursor at a new position. + */ + + static void NVSetCursor(ScreenPtr pScr,CursorPtr pCurs,int x,int y, + Bool generateEvent) + { + if(!pCurs) + return; + + NVCursorHotX = pCurs->bits->xhot; + NVCursorHotY = pCurs->bits->yhot; + + NVLoadCursor(pScr, pCurs, x, y); + } + + /* + * This function should redisplay a cursor that has been + * displayed earlier. It is called by the SVGA server. + */ + + void NVRestoreCursor(ScreenPtr pScr) + { + int x, y; + + miPointerPosition(&x, &y); + + NVLoadCursor(pScr, NVCursorpCurs, x, y); + } + + /* + * This function is called when the current cursor is moved. It makes + * the graphic chip display the cursor at the new position. + */ + + int nvMiLineZeroBias=OCTANT4 | OCTANT3 | OCTANT1 | OCTANT6; + + static void NVMoveCursor(ScreenPtr pScr,int x,int y) + { + int xorigin, yorigin; + + if(!xf86VTSema) return; + + + x -= vga256InfoRec.frameX0 + NVCursorHotX; + y -= vga256InfoRec.frameY0 + NVCursorHotY; + + PDAC_WriteExt(CURSOR_X_POS_LO,x & 0xff); + PDAC_WriteExt(CURSOR_X_POS_HI,(x >>8) & 0xff); + + PDAC_WriteExt(CURSOR_Y_POS_LO,y & 0xff); + PDAC_WriteExt(CURSOR_Y_POS_HI,(y >>8) & 0xff); + + } + + /* + * This is a local function that programs the colors of the cursor + * on the graphics chip. + * Adapted from accel/s3/s3Cursor.c. + */ + + static void NVRecolorCursor(ScreenPtr pScr,CursorPtr pCurs,Bool displayed) + { + ColormapPtr pmap; + unsigned short packedcolfg, packedcolbg; + xColorItem sourceColor, maskColor; + + if(!xf86VTSema) return; + + if(!displayed) return; + + PDAC_WriteExt(CURSOR_COLOUR_3_RED,pCurs->foreRed >> 8); + PDAC_WriteExt(CURSOR_COLOUR_3_GREEN,pCurs->foreGreen >> 8); + PDAC_WriteExt(CURSOR_COLOUR_3_BLUE,pCurs->foreBlue >> 8); + + PDAC_WriteExt(CURSOR_COLOUR_2_RED,pCurs->backRed >> 8); + PDAC_WriteExt(CURSOR_COLOUR_2_GREEN,pCurs->backGreen >> 8); + PDAC_WriteExt(CURSOR_COLOUR_2_BLUE,pCurs->backBlue >> 8); + + } + + /* + * This doesn't do very much. It just calls the mi routine. It is called + * by the SVGA server. + */ + + void NVWarpCursor(ScreenPtr pScr,int x,int y) + { + miPointerWarpCursor(pScr, x, y); + xf86Info.currentScreen = pScr; + } + + /* + * This function is called by the SVGA server. It returns the + * size of the hardware cursor that we support when asked for. + * It is called by the SVGA server. + */ + + + + void NVQueryBestSize(int class,unsigned short *pwidth, + unsigned short *pheight,ScreenPtr pScreen) + { + #if 0 + + /* miSetZeroLineBias(pScreen,OCTANT4 | OCTANT3 | OCTANT1 | OCTANT6);*/ + miSetZeroLineBias(pScreen,nvMiLineZeroBias); + ErrorF("Zero Bias is 0x%02x\n",nvMiLineZeroBias); + #endif + + if(*pwidth > 0) { + if(class == CursorShape) { + *pwidth = MAX_CURS; + *pheight = MAX_CURS; + } else + (void)mfbQueryBestSize(class, pwidth, pheight, pScreen); + } + } *** /dev/null Tue Jun 30 11:50:03 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/nv1driver.c Sat Mar 7 17:08:50 1998 *************** *** 0 **** --- 1,874 ---- + + /* $TOG: nv1driver.c /main/2 1998/03/07 17:10:31 kaleb $ */ + /* + * Copyright 1996-1997 David J. McKay + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * DAVID J. MCKAY BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/nv1driver.c,v 1.1.2.3 1998/01/24 11:55:08 dawes Exp $ */ + + #include <math.h> + #include <stdlib.h> + + + #include "X.h" + #include "input.h" + #include "screenint.h" + + #include "compiler.h" + #include "xf86.h" + #include "xf86Priv.h" + #include "xf86_OSlib.h" + #include "xf86_HWlib.h" + #include "vga.h" + + #include "vgaPCI.h" + /* + * If the driver makes use of XF86Config 'Option' flags, the following will be + * required + */ + #define XCONFIG_FLAGS_ONLY + #include "xf86_Config.h" + + + #ifdef XFreeXDGA + #include "X.h" + #include "Xproto.h" + #include "scrnintstr.h" + #include "servermd.h" + #define _XF86DGA_SERVER_ + #include "extensions/xf86dgastr.h" + #endif + + #define NV_1764_MAX_CLOCK_IN_KHZ 170000 + #define NV_1732_MAX_CLOCK_IN_KHZ 135000 + + #define NV_MAX_VCLK_PIN_CLOCK_IN_KHZ 50000 + + #include "nv1ref.h" + #include "nvreg.h" + #include "nvcursor.h" + #include "nvvga.h" + + + /* Function to read extended register */ + + #define MapDevice(device,base) \ + nv##device##Port=(unsigned*)xf86MapVidMem(vga256InfoRec.scrnIndex,\ + MMIO_REGION,\ + ((char*)(base))+DEVICE_BASE(device),\ + DEVICE_SIZE(device)) + + #define NV_CHAN0 0x0080ffff:0x00800000 + + #define NV_FRAME_BUFFER 0x01000000 + + static void MapNvRegs(void *base) + { + MapDevice(PDAC,base); + MapDevice(PFB,base); + MapDevice(PRM,base); + MapDevice(PGRAPH,base); + MapDevice(PDMA,base); + MapDevice(PFIFO,base); + MapDevice(PRAM,base); + MapDevice(PRAMFC,base); + MapDevice(PRAMHT,base); + MapDevice(PMC,base); + MapDevice(CHAN0,base); + } + + + #define PALETTE_SIZE 256 + + #define VPLL_INPUT_FREQ 12096.0 + #define PLL_LOWER_BOUND 64000 + #define PLL_UPPER_BOUND vga256InfoRec.maxClock + + + /* + * The following equation defines the output frequency of the PLL + * fout = ( N/(M*P) ) * fin; + * + * It must also obey the following restraints! + * 1Mhz <= fin/M <= 2Mhz (This means M in the range 12 -> 7) + * + * 64Mhz <= ((N*O)/M)*fin <=135 (or whatever the max ramdac speed is) + * + * The following function simple does a brute force search I'm afraid. + * I know that it is possible to write a much faster function, but + * there are more important things to work on, and at least I know + * this one will always get the right answer! + */ + + static int NVClockSelect(float clockIn,float *clockOut, + int *Mparam,int *Nparam,int *Oparam,int *Pparam) + { + int m,n,o,p; + float bestDiff=1e10; /* Set to silly value for first range */ + float target=0.0; + float best=0.0; + + *clockOut=0; + for(p=1;p<=8;p*=2) { + float fp=(float)p; + for(n=8;n<=255;n++) { + float fn=(float)n; + for(m=12;m>=7;m--) { + float fm=(float)m; + for(o=1;o<=15;o++) { + float fo=(float) o; + float check= ((fn*fo)/fm)*VPLL_INPUT_FREQ; + if(check>PLL_LOWER_BOUND && check <= PLL_UPPER_BOUND) break; + } + if(o!=16) { + float diff; + target=(fn/(fm*fp))*VPLL_INPUT_FREQ; + diff=fabs(target - clockIn); + if(diff < bestDiff) { + bestDiff=diff; + best=target; + *Mparam=m;*Nparam=n;*Oparam=o;*Pparam=p; + *clockOut=best; + } + } + } + } + } + return (best!=0.0); + } + + static int pixelPortWidth=0; /* Holds how big it is,needed in NVInit() */ + + + static int ProbeRamdac(void) + { + int id=PDAC_ReadExt(COMPANY_ID); + + if(id!=NV_PDAC_SGS_ID) { + ErrorF("%s %s: %s: Unsupported RAMDAC (vendor number 0x%02x)\n", + XCONFIG_PROBED,vga256InfoRec.name,vga256InfoRec.chipset,id); + return 0; + } + /* Figure out what sort of RAMDAC we have. I don't know if the RAMDACS + * have different PCI device numbers, but this test will always work + */ + switch(id=PDAC_ReadExt(DEVICE_ID)) { + case NV_PDAC_1764_ID: + /* I believe all Diamond Edge3D boards use the 1764 */ + vga256InfoRec.maxClock = NV_1764_MAX_CLOCK_IN_KHZ; + break; + case NV_PDAC_1732_ID: + vga256InfoRec.maxClock = NV_1732_MAX_CLOCK_IN_KHZ; + break; + default: + ErrorF("%s %s: %s: Unsupported SGS RAMDAC (id number 0x%02x)\n", + XCONFIG_PROBED,vga256InfoRec.name,vga256InfoRec.chipset,id); + return 0; + break; + } + /* We need to figure out what the pixel port width is. This depends + * on memory configuration etc, so we read it here so the NVInit() + * function can put it back in. + */ + pixelPortWidth=GetBF(PDAC_ReadExt(CONF_0),NV_PDAC_CONF_0_PORT_WIDTH); + + return 1; + } + + /* Forward declarations for Probe() */ + static void NV1FlipFunctions(vgaVideoChipRec *nv); + static void NV1DisplayPowerManagementSet(int mode); + static Bool NV1BlankScreen(ScreenPtr pScreen,Bool on); + static Bool NV1ScreenInit(ScreenPtr pScreen,pointer pbits, + int xsize,int ysize,int dpix,int dpiy,int width); + + int NV1Probe(vgaVideoChipRec *nv,void *base0,void *base1) + { + int ramdacId; + + ErrorF("NV1Probe() %p %p\n",base0,base1); + + /* I/o ports are needed for things like pallete selection etc */ + xf86ClearIOPortList (vga256InfoRec.scrnIndex); + xf86AddIOPorts(vga256InfoRec.scrnIndex,Num_VGA_IOPorts,VGA_IOPorts); + + nv->ChipLinearBase=(int)base0+NV_FRAME_BUFFER; + /* Now memory map the registers */ + MapNvRegs((pointer)base0); + + /* Calculate how much RAM, unless user supplies */ + + if(!vga256InfoRec.videoRam) { + vga256InfoRec.videoRam = (1024 << + GetBF(PFB_Read(BOOT_0),NV_PFB_BOOT_0_RAM_AMOUNT)); + } + nv->ChipLinearSize=vga256InfoRec.videoRam*1024; + nv->ChipHas32bpp=FALSE; + + if(getenv("NV_NORAMDAC_PROBE")) { + ErrorF("%s %s: %s: Skipping RAMDAC test (Hi Kent!)\n",XCONFIG_PROBED, + vga256InfoRec.name, + vga256InfoRec.chipset); + vga256InfoRec.maxClock = NV_1764_MAX_CLOCK_IN_KHZ; + pixelPortWidth=GetBF(PDAC_ReadExt(CONF_0),NV_PDAC_CONF_0_PORT_WIDTH); + }else { + if(!ProbeRamdac()) return FALSE; + } + #ifdef XFreeXDGA + vga256InfoRec.directMode = XF86DGADirectPresent; + #endif + vga256InfoRec.bankedMono = FALSE; + + #ifdef DPMSExtension + vga256InfoRec.DPMSSet = NV1DisplayPowerManagementSet; + #endif + + /* Hook blank screen function. Standard VGA one doesn't work */ + vgaBlankScreenFunc=NV1BlankScreen; + /* Hook install palette */ + vgaSetScreenInitHook(NV1ScreenInit); + + /* The NV1 only supports 555 weighting, so force it here */ + if(vgaBitsPerPixel==16) { + ErrorF("%s %s: %s: Setting RGB weight to 555\n",XCONFIG_PROBED, + vga256InfoRec.name, + vga256InfoRec.chipset); + xf86weight.green=xf86weight.blue=xf86weight.red=5; + } + + OFLG_SET(OPTION_DAC_8_BIT,&(nv->ChipOptionFlags)); + OFLG_SET(OPTION_NOACCEL, &(nv->ChipOptionFlags)); + OFLG_SET(OPTION_SW_CURSOR, &(nv->ChipOptionFlags)); + + NV1FlipFunctions(nv); + + return (TRUE); + } + + /* This function does nothing for the NV1 as it is not driven + * though the VGA + */ + static void NV1EnterLeave(Bool enter) + { + } + + /* + * NV1Restore -- + * + * This function restores a video mode. It basically writes out all of + * the registers that have previously been saved in the vgaNVRec data + * structure. + * + * Note that "Restore" is a little bit incorrect. This function is also + / * used when the server enters/changes video modes. The mode definitions + * have previously been initialized by the Init() function, below. + */ + static void NV1Restore(void *data) + { + int i; + vgaNVPtr restore = data; + NV1Registers *nv1=&(restore->regs.nv1); + int toTextMode; + + /* Only restore generic vga IF WE ARE GOING TO TEXT MODE */ + if(restore->vgaValid) { + xf86EnableIOPorts(vga256InfoRec.scrnIndex); + vgaHWRestore ((vgaHWPtr) restore); + xf86DisableIOPorts(vga256InfoRec.scrnIndex); + } + + /* Set the clock registers */ + + PRM_Write(TRACE,nv1->memoryTrace); + PRM_Write(CONFIG_0,nv1->prmConfig0); + + PDAC_WriteExt(VPLL_M_PARAM,nv1->Mparam); + PDAC_WriteExt(VPLL_N_PARAM,nv1->Nparam); + PDAC_WriteExt(VPLL_O_PARAM,nv1->Oparam); + PDAC_WriteExt(VPLL_P_PARAM,nv1->Pparam); + + PDAC_WriteExt(MPLL_M_PARAM,nv1->MparamMPLL); + PDAC_WriteExt(MPLL_N_PARAM,nv1->NparamMPLL); + PDAC_WriteExt(MPLL_O_PARAM,nv1->OparamMPLL); + PDAC_WriteExt(MPLL_P_PARAM,nv1->PparamMPLL); + + /* Set the dac conf reg that sets the pixel depth */ + PDAC_WriteExt(CONF_0,nv1->dacConfReg0); + PDAC_WriteExt(CONF_1,nv1->dacConfReg1); + PDAC_WriteExt(RGB_PAL_CTRL,nv1->dacRgbPalCtrl); + + /* Write out the registers that control the dumb framebuffer */ + PFB_Write(CONFIG_0,nv1->confReg0); + PFB_Write(GREEN_0,nv1->green0); + PFB_Write(START,nv1->startAddr); + + PFB_Write(HOR_FRONT_PORCH,nv1->horFrontPorch); + PFB_Write(HOR_SYNC_WIDTH,nv1->horSyncWidth); + PFB_Write(HOR_BACK_PORCH,nv1->horBackPorch); + PFB_Write(HOR_DISP_WIDTH,nv1->horDispWidth); + PFB_Write(VER_FRONT_PORCH,nv1->verFrontPorch); + PFB_Write(VER_SYNC_WIDTH,nv1->verSyncWidth); + PFB_Write(VER_BACK_PORCH,nv1->verBackPorch); + PFB_Write(VER_DISP_WIDTH,nv1->verDispWidth); + + /* Now restore cursor registers. I don't know if this is strictly + * needed or not, but it isn't hard to do + */ + PDAC_WriteExt(CURSOR_CTRL_A,nv1->cursorCtrl); + PDAC_WriteExt(CURSOR_X_POS_LO,nv1->xLo); + PDAC_WriteExt(CURSOR_X_POS_HI,nv1->xHi); + PDAC_WriteExt(CURSOR_Y_POS_LO,nv1->yLo); + PDAC_WriteExt(CURSOR_Y_POS_HI,nv1->yHi); + + for(i=0;i<3;i++) { + PDAC_WriteExt(CURSOR_COLOUR_1_RGB+i,nv1->colour1[i]); + PDAC_WriteExt(CURSOR_COLOUR_2_RGB+i,nv1->colour2[i]); + PDAC_WriteExt(CURSOR_COLOUR_3_RGB+i,nv1->colour3[i]); + } + for(i=0;i<NV_PDAC_CURSOR_PLANE_SIZE;i++) { + PDAC_WriteExt(CURSOR_PLANE_0+i,nv1->plane0[i]); + PDAC_WriteExt(CURSOR_PLANE_1+i,nv1->plane1[i]); + } + + /* Restore pallette */ + for(i=0;i<PALETTE_SIZE;i++) { + PDAC_Write(WRITE_PALETTE,(unsigned char)i); + PDAC_Write(COLOUR_DATA,nv1->palette[i][0]); + PDAC_Write(COLOUR_DATA,nv1->palette[i][1]); + PDAC_Write(COLOUR_DATA,nv1->palette[i][2]); + } + } + + /* + * NV1Save -- + * + * This function saves the video state. It reads all of the SVGA registers + * into the vgaNVRec data structure. There is in general no need to + * mask out bits here - just read the registers. + */ + static void *NV1Save(void *data) + { + vgaNVPtr save=NULL; + int i; + int inTextMode; + NV1Registers *nv1; + inTextMode=(PRM_Read(CONFIG_0) & PRM_Def(CONFIG_0_TEXT,ENABLED)); + if(inTextMode) { + xf86EnableIOPorts(vga256InfoRec.scrnIndex); + save = (vgaNVPtr) vgaHWSave ((vgaHWPtr) data, sizeof (vgaNVRec)); + xf86DisableIOPorts(vga256InfoRec.scrnIndex); + save->vgaValid=1; + }else { + save=(data) ? data : Xcalloc(sizeof(vgaNVRec)); + save->vgaValid=0; + } + nv1=&(save->regs.nv1); + nv1->prmConfig0=PRM_Read(CONFIG_0); + nv1->memoryTrace=PRM_Read(TRACE); + + nv1->dacConfReg0=PDAC_ReadExt(CONF_0); + nv1->dacConfReg1=PDAC_ReadExt(CONF_1); + nv1->dacRgbPalCtrl=PDAC_ReadExt(RGB_PAL_CTRL); + + nv1->Mparam=PDAC_ReadExt(VPLL_M_PARAM); + nv1->Nparam=PDAC_ReadExt(VPLL_N_PARAM); + nv1->Oparam=PDAC_ReadExt(VPLL_O_PARAM); + nv1->Pparam=PDAC_ReadExt(VPLL_P_PARAM); + + nv1->MparamMPLL=PDAC_ReadExt(MPLL_M_PARAM); + nv1->NparamMPLL=PDAC_ReadExt(MPLL_N_PARAM); + nv1->OparamMPLL=PDAC_ReadExt(MPLL_O_PARAM); + nv1->PparamMPLL=PDAC_ReadExt(MPLL_P_PARAM); + + nv1->confReg0=PFB_Read(CONFIG_0); + nv1->green0=PFB_Read(GREEN_0); + nv1->startAddr=PFB_Read(START); + + nv1->horFrontPorch=PFB_Read(HOR_FRONT_PORCH); + nv1->horSyncWidth=PFB_Read(HOR_SYNC_WIDTH); + nv1->horBackPorch=PFB_Read(HOR_BACK_PORCH); + nv1->horDispWidth=PFB_Read(HOR_DISP_WIDTH); + nv1->verFrontPorch=PFB_Read(VER_FRONT_PORCH); + nv1->verSyncWidth=PFB_Read(VER_SYNC_WIDTH); + nv1->verBackPorch=PFB_Read(VER_BACK_PORCH); + nv1->verDispWidth=PFB_Read(VER_DISP_WIDTH); + + /* Restore the HW cursor registers */ + nv1->cursorCtrl=PDAC_ReadExt(CURSOR_CTRL_A); + nv1->xLo=PDAC_ReadExt(CURSOR_X_POS_LO); + nv1->xHi=PDAC_ReadExt(CURSOR_X_POS_HI); + nv1->yLo=PDAC_ReadExt(CURSOR_Y_POS_LO); + nv1->yHi=PDAC_ReadExt(CURSOR_Y_POS_HI); + + for(i=0;i<3;i++) { + nv1->colour1[i]=PDAC_ReadExt(CURSOR_COLOUR_1_RGB+i); + nv1->colour2[i]=PDAC_ReadExt(CURSOR_COLOUR_2_RGB+i); + nv1->colour3[i]=PDAC_ReadExt(CURSOR_COLOUR_3_RGB+i); + } + for(i=0;i<NV_PDAC_CURSOR_PLANE_SIZE;i++) { + nv1->plane0[i]=PDAC_ReadExt(CURSOR_PLANE_0+i); + nv1->plane1[i]=PDAC_ReadExt(CURSOR_PLANE_1+i); + } + + /* Save pallette */ + for(i=0;i<PALETTE_SIZE;i++) { + PDAC_Write(READ_PALETTE,(unsigned char)i); + nv1->palette[i][0]=PDAC_Read(COLOUR_DATA); + nv1->palette[i][1]=PDAC_Read(COLOUR_DATA); + nv1->palette[i][2]=PDAC_Read(COLOUR_DATA); + } + + return ((void*)save); + } + + + + static int VirtualScreenOk(DisplayModePtr mode) + { + if(mode->CrtcHDisplay!=vga256InfoRec.virtualX) return 0; + + if(mode->Flags & V_DBLSCAN) { + return (2*vga256InfoRec.virtualY==mode->CrtcVDisplay); + } + + return (vga256InfoRec.virtualY==mode->CrtcVDisplay); + } + + + #define RESOLUTION_NOT_SUPPORTED (-1) + + static int GetResolutionValue(int xwidth) + { + int resolution; + + /* We need to do more here with respect to rejecting modes !! */ + switch(xwidth) { + case 576: + resolution=0;break; + case 640: + resolution=1;break; + case 800: + resolution=2;break; + case 1024: + resolution=3;break; + case 1152: + resolution=4;break; + case 1280: + resolution=5;break; + case 1600: + resolution=6;break; + default: + /* Oops. Will have to switch off accel */ + resolution=RESOLUTION_NOT_SUPPORTED; + break; + } + return resolution; + } + + + static unsigned long currentGreen0=0; + + static unsigned long SetSync(DisplayModePtr mode) + { + unsigned long green0=0; + + if((mode->Flags & (V_PHSYNC | V_NHSYNC)) && + (mode->Flags & (V_PVSYNC | V_NVSYNC)) ) { + if(mode->Flags & V_PHSYNC) { + green0|=PFB_Def(GREEN_0_POLAR_HSYNC,POSITIVE); + }else { + green0|=PFB_Def(GREEN_0_POLAR_HSYNC,NEGATIVE); + } + if(mode->Flags & V_PVSYNC) { + green0|=PFB_Def(GREEN_0_POLAR_VSYNC,POSITIVE); + }else { + green0|=PFB_Def(GREEN_0_POLAR_VSYNC,NEGATIVE); + } + }else { + int v = (mode->Flags & V_DBLSCAN) ? mode->VDisplay*2 : mode->VDisplay; + if(v < 400) + green0|=PFB_Def(GREEN_0_POLAR_HSYNC,POSITIVE) | + PFB_Def(GREEN_0_POLAR_VSYNC,NEGATIVE); + else if(v < 480) { + green0|=PFB_Def(GREEN_0_POLAR_HSYNC,NEGATIVE) | + PFB_Def(GREEN_0_POLAR_VSYNC,POSITIVE); + }else if(v < 768) { + green0|=PFB_Def(GREEN_0_POLAR_HSYNC,NEGATIVE) | + PFB_Def(GREEN_0_POLAR_VSYNC,NEGATIVE); + }else { + green0|=PFB_Def(GREEN_0_POLAR_HSYNC,POSITIVE) | + PFB_Def(GREEN_0_POLAR_VSYNC,POSITIVE); + } + } + currentGreen0=green0; + /* We should also check for composite sync here as well */ + return green0; + + } + + + #define DROP_MCLOCK_THRESHOLD 28300.0 + #define MCLOCK_VCLOCK_RATIO 3.5 + #define DEFAULT_MCLOCK 100669.0 + + static int SetMclock(float vclock,float *clockOut,int *m,int *n,int *o,int *p) + { + + /* Drive it to the max if we can */ + if(vclock > DROP_MCLOCK_THRESHOLD) { + *m=11;*n=91;*o=1;*p=1; + *clockOut=DEFAULT_MCLOCK; + return 1; + } + /* Hmm. Will have to drop MCLOCK to allow the DAC to function + * correctly. + */ + return NVClockSelect(vclock*MCLOCK_VCLOCK_RATIO,clockOut,m,n,o,p); + + } + + #define new ((vgaNVPtr)vgaNewVideoState) + + static Bool NV1Init(DisplayModePtr mode) + { + int bppShift=(vgaBitsPerPixel==8) ? 1 : 2; + int m,n,o,p; + int mm,nm,om,pm; + float clockIn=(float)vga256InfoRec.clock[mode->Clock]; + float clockOut,mclockOut; + int pclkVclkRatio; + int i; + int resolution; + int dac8bit= OFLG_ISSET(OPTION_DAC_8_BIT,&vga256InfoRec.options); + NV1Registers *nv1; + int vertSyncStart,vertDisplay,vertTotal,vertSyncEnd; + + /* Check to see that we are not trying to do a virtual screen */ + if(!VirtualScreenOk(mode)) { + ErrorF("%s %s: %s: Can't select mode %s : virtual desktop not supported\n", + XCONFIG_PROBED, vga256InfoRec.name,vga256InfoRec.chipset,mode->name); + return FALSE; + } + + if(!NVClockSelect(clockIn,&clockOut,&m,&n,&o,&p)) { + ErrorF("%s %s: %s: Unable to set desired video clock\n", + XCONFIG_PROBED, vga256InfoRec.name,vga256InfoRec.chipset); + return FALSE; + + } + /* Figure out divide down for clock. The Vclk pin is rated for + * 25-50Mhz but can actually be driven higher than this on most + * silicon + */ + for(i=1,pclkVclkRatio=0;i<=16;i*=2,pclkVclkRatio++) { + if((clockOut/(double)i) <= NV_MAX_VCLK_PIN_CLOCK_IN_KHZ) break; + } + ErrorF("%s %s: %s: Using %.3fMhz video clock\n",XCONFIG_PROBED, + vga256InfoRec.name,vga256InfoRec.chipset,clockOut/1000); + + if(!SetMclock(clockOut,&mclockOut,&mm,&nm,&om,&pm)) { + ErrorF("%s %s: %s: Unable to set desired master clock\n", + XCONFIG_PROBED, vga256InfoRec.name,vga256InfoRec.chipset); + return FALSE; + } + ErrorF("%s %s: %s: Using %.3fMhz master clock\n",XCONFIG_PROBED, + vga256InfoRec.name,vga256InfoRec.chipset,mclockOut/1000); + + /* + * This will allocate the datastructure and initialize all of the + * generic VGA registers. It doesn`t actually write to any VGA registers. + */ + if (!vgaHWInit (mode, sizeof (vgaNVRec))) { + return (FALSE); + } + nv1=&((new)->regs.nv1); + new->vgaValid=0; + nv1->Mparam=m;nv1->Nparam=n;nv1->Oparam=o;nv1->Pparam=p; + nv1->MparamMPLL=mm;nv1->NparamMPLL=nm;nv1->OparamMPLL=om;nv1->PparamMPLL=pm; + + nv1->dacConfReg0= PDAC_Val(CONF_0_VGA_STATE,1) | + PDAC_Val(CONF_0_PORT_WIDTH,pixelPortWidth) | + PDAC_Val(CONF_0_VISUAL_DEPTH,bppShift) | + PDAC_Val(CONF_0_IDC_MODE,vgaBitsPerPixel==8); + + nv1->dacConfReg1=PDAC_Val(CONF_1_VCLK_IMPEDANCE,1) | + PDAC_Val(CONF_1_PCLK_VCLK_RATIO,pclkVclkRatio); + + + nv1->dacRgbPalCtrl=(dac8bit) ? PDAC_Def(EXT_RGB_PAL_CTRL_DAC_WIDTH,BITS_8) : + PDAC_Def(EXT_RGB_PAL_CTRL_DAC_WIDTH,BITS_6) ; + + nv1->prmConfig0=(dac8bit) ? PRM_Def(CONFIG_0_DAC_WIDTH,BITS_8) : + PRM_Def(CONFIG_0_DAC_WIDTH,BITS_6); + nv1->memoryTrace=0; + + resolution=GetResolutionValue(vga256InfoRec.virtualX); + /* If we have an "error" here , just set it to zero. If we are + * not using any acceleration, the value doesn't matter + */ + if(resolution==RESOLUTION_NOT_SUPPORTED) resolution=0; + + nv1->confReg0=PFB_Val(CONFIG_0_PIXEL_DEPTH,bppShift) | + PFB_Val(CONFIG_0_PCLK_VCLK_RATIO,pclkVclkRatio) | + PFB_Val(CONFIG_0_RESOLUTION,resolution) | + PFB_Val(CONFIG_0_SCANLINE, + (mode->Flags & V_DBLSCAN)==V_DBLSCAN); + + nv1->green0=SetSync(mode); + nv1->startAddr=0; + /* Calculate the monitor timings */ + nv1->horFrontPorch=mode->CrtcHSyncStart - mode->CrtcHDisplay+1; + nv1->horBackPorch=mode->CrtcHTotal - mode->CrtcHSyncEnd+1; + nv1->horSyncWidth=mode->CrtcHSyncEnd - mode->CrtcHSyncStart+1; + + nv1->horDispWidth=mode->CrtcHDisplay; + + nv1->verFrontPorch=mode->CrtcVSyncStart - mode->CrtcVDisplay+1; + nv1->verBackPorch=mode->CrtcVTotal - mode->CrtcVSyncEnd+1; + nv1->verSyncWidth=mode->CrtcVSyncEnd - mode->CrtcVSyncStart+1; + nv1->verDispWidth=mode->CrtcVDisplay; + + /* The server will initialise the cursor correctly, so we just set it + * all to zero here + */ + nv1->cursorCtrl=NV_PDAC_CURSOR_CTRL_A_OFF; + nv1->xLo=0;nv1->xHi=0;nv1->yLo=0;nv1->yHi=0; + + for(i=0;i<3;i++) { + nv1->colour1[i]=0;nv1->colour2[i]=0;nv1->colour3[i]=0; + } + for(i=0;i<NV_PDAC_CURSOR_PLANE_SIZE;i++) { + nv1->plane0[i]=0;nv1->plane1[i]=0; + } + + for(i=0;i<PALETTE_SIZE;i++) { + nv1->palette[i][0]=0; + nv1->palette[i][1]=0; + nv1->palette[i][2]=0; + } + + return (TRUE); + } + + static void NV1Adjust(int x, int y) + { + int bppShift=(vgaBitsPerPixel==8) ? 1 : 2; + + /* Wait for vertical blank */ + while(GetBF(PFB_Read(CONFIG_0),NV_PFB_CONFIG_0_VERTICAL)==0); + + PFB_Write(START,(y * vga256InfoRec.displayWidth + x)*bppShift); + + } + + static int NV1ValidMode(DisplayModePtr mode,Bool verbose,int flag) + { + return (MODE_OK); + } + + + + extern vgaHWCursorRec vgaHWCursor; + + static void NV1FbInit(void) + { + + if(GetResolutionValue(vga256InfoRec.virtualX)==RESOLUTION_NOT_SUPPORTED) { + OFLG_SET(OPTION_NOACCEL,&vga256InfoRec.options); + ErrorF("%s %s: %s: Display width must be " + "576,640,800,1024,1152,1280 or 1600 pixels\n", + XCONFIG_PROBED,vga256InfoRec.name,vga256InfoRec.chipset); + ErrorF("%s %s: %s: Acceleration switched off\n", + XCONFIG_PROBED,vga256InfoRec.name,vga256InfoRec.chipset); + } + /* Is this the correct thing to do ?? */ + if(!OFLG_ISSET(OPTION_SW_CURSOR, &vga256InfoRec.options)) { + /* Initialise the hardware cursor */ + vgaHWCursor.Initialized = TRUE; + vgaHWCursor.Init = NVCursorInit; + vgaHWCursor.Restore = NVRestoreCursor; + vgaHWCursor.Warp = NVWarpCursor; + vgaHWCursor.QueryBestSize = NVQueryBestSize; + if(xf86Verbose) { + ErrorF("%s %s: %s: Using hardware cursor\n",XCONFIG_PROBED, + vga256InfoRec.name,vga256InfoRec.chipset); + } + } + + if(!OFLG_ISSET(OPTION_NOACCEL, &vga256InfoRec.options)) { + NVAccelInit(); + } + } + + static Bool NV1BlankScreen(ScreenPtr pScreen,Bool on) + { + unsigned long green; + + green=PFB_Read(GREEN_0) & ~(PFB_Mask(GREEN_0_LEVEL)); + if(on) { + green|=PFB_Def(GREEN_0_LEVEL,VIDEO_ENABLED); + }else { + green|=PFB_Def(GREEN_0_LEVEL,VIDEO_DISABLED); + } + PFB_Write(GREEN_0,green); + return TRUE; + + } + + + static int DGADirectMode(void) + { + #ifdef XFreeXDGA + return ( ((vga256InfoRec.directMode & XF86DGADirectGraphics) && + !(vga256InfoRec.directMode & XF86DGADirectColormap)) + || (vga256InfoRec.directMode & XF86DGAHasColormap)); + #else + return 0; + #endif + } + + + #ifdef DEBUG + /* If the Vclock is too low for the Mclock, the first sympton is + * that reads from the palette start failing. Set this to + * check that you can read back the palette value that you wrote + */ + #define PARANOID_PALETTE_CHECK + #endif + + static void NVStoreColors(ColormapPtr pmap,int ndef,xColorItem *pdefs) + { + int i; + xColorItem directDefs[256]; + int shift=(vgaDAC8BitComponents) ? 8 : 10; + + if(vgaCheckColorMap(pmap)) return; + if((pmap->pVisual->class | DynamicClass) == DirectColor) { + ndef = cfbExpandDirectColors (pmap, ndef, pdefs, directDefs); + pdefs = directDefs; + } + + if(!(xf86VTSema || DGADirectMode())) return; + + for(i=0;i<ndef;i++) { + int r,g,b; + PDAC_Write(WRITE_PALETTE,pdefs[i].pixel); + r=(pdefs[i].red >> shift);g=(pdefs[i].green >> shift); + b=(pdefs[i].blue >> shift); + PDAC_Write(COLOUR_DATA,r); + PDAC_Write(COLOUR_DATA,g); + PDAC_Write(COLOUR_DATA,b); + #ifdef PARANOID_PALETTE_CHECK + /* Checks that what you write can be read ! */ + { + int rout,bout,gout; + PDAC_Write(READ_PALETTE,pdefs[i].pixel); + rout=PDAC_Read(COLOUR_DATA);gout=PDAC_Read(COLOUR_DATA); + bout=PDAC_Read(COLOUR_DATA); + if(rout!=r || gout!=g || bout!=b) + ErrorF("Entry %d In -> [%02x:%02x:%02x] Out -> [%02x:%02x:%02x]\n", + pdefs[i].pixel,r,g,b, + rout,gout,bout); + } + #endif + } + + } + + static Bool NV1ScreenInit(ScreenPtr pScreen,pointer pbits, + int xsize,int ysize,int dpix,int dpiy,int width) + { + /* Hook the palette function. The standard VGA one sets overscan which + * results in a corrupt pixel on the screen as the NV1 will write it + * through to the framebuffer + */ + pScreen->StoreColors = NVStoreColors; + } + + + #ifdef DPMSExtension + static void NV1DisplayPowerManagementSet(int mode) + { + int level; + int hsyncOn=0,vsyncOn=0; + unsigned long green=0; + + if (!xf86VTSema) return; + + switch(mode) { + case DPMSModeOn: + /* Screen: On; HSync: On, VSync: On */ + level=0;hsyncOn=1;vsyncOn=1; + break; + case DPMSModeStandby: + /* Screen: Off; HSync: Off, VSync: On */ + level=1;hsyncOn=0;vsyncOn=1; + break; + case DPMSModeSuspend: + /* Screen: Off; HSync: On, VSync: Off */ + level=1;hsyncOn=1;vsyncOn=0; + break; + case DPMSModeOff: + /* Screen: Off; HSync: Off, VSync: Off */ + level=2;hsyncOn=0;vsyncOn=0; + break; + } + + if(hsyncOn) { + green|= (currentGreen0 & PFB_Mask(GREEN_0_POLAR_HSYNC)); + }else { + green|=PFB_Def(GREEN_0_POLAR_HSYNC,LOW); + } + if(vsyncOn) { + green|= (currentGreen0 & PFB_Mask(GREEN_0_POLAR_VSYNC)); + }else { + green|=PFB_Def(GREEN_0_POLAR_VSYNC,LOW); + } + green|=PFB_Val(GREEN_0_LEVEL,level); + PFB_Write(GREEN_0,green); + + } + #endif + + static void NV1SaveScreen(int on) + { + } + + static void NV1GetMode(DisplayModePtr display) + { + } + + /* Changes the entries in the NV struct to point at the correct function + * pointers. Called from the Probe() function + */ + static void NV1FlipFunctions(vgaVideoChipRec *nv) + { + nv->ChipEnterLeave=NV1EnterLeave; + nv->ChipInit=NV1Init; + nv->ChipValidMode=NV1ValidMode; + nv->ChipSave=NV1Save; + nv->ChipRestore=NV1Restore; + nv->ChipAdjust=NV1Adjust; + nv->ChipSaveScreen=NV1SaveScreen; + nv->ChipGetMode=NV1GetMode; + nv->ChipFbInit=NV1FbInit; + + } *** /dev/null Tue Jun 30 11:50:04 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/nv1ref.h Fri Mar 6 16:51:43 1998 *************** *** 0 **** --- 1,782 ---- + /* $TOG: nv1ref.h /main/1 1998/03/06 16:53:20 kaleb $ */ + + + + /***************************************************************************\ + |* *| + |* Copyright (c) 1996-1998 NVIDIA, Corp. All rights reserved. *| + |* *| + |* NOTICE TO USER: The source code is copyrighted under U.S. and *| + |* international laws. NVIDIA, Corp. of Sunnyvale, California owns *| + |* the copyright and as design patents pending on the design and *| + |* interface of the NV chips. Users and possessors of this source *| + |* code are hereby granted a nonexclusive, royalty-free copyright *| + |* and design patent license to use this code in individual and *| + |* commercial software. *| + |* *| + |* Any use of this source code must include, in the user documenta- *| + |* tion and internal comments to the code, notices to the end user *| + |* as follows: *| + |* *| + |* Copyright (c) 1996-1998 NVIDIA, Corp. NVIDIA design patents *| + |* pending in the U.S. and foreign countries. *| + |* *| + |* NVIDIA, CORP. MAKES NO REPRESENTATION ABOUT THE SUITABILITY OF *| + |* THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" WITHOUT *| + |* EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORP. DISCLAIMS *| + |* ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, INCLUDING ALL *| + |* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *| + |* PARTICULAR PURPOSE. IN NO EVENT SHALL NVIDIA, CORP. BE LIABLE *| + |* FOR ANY SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, *| + |* OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR *| + |* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER *| + |* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR *| + |* PERFORMANCE OF THIS SOURCE CODE. *| + |* *| + \***************************************************************************/ + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/nv1ref.h,v 1.1.2.3 1998/01/24 00:04:37 robin Exp $ */ + + #ifndef __NV1REF_H_ + #define __NV1REF_H_ + + /* Where the hardware units are. Used to generate context */ + + #define NV_UBLIT 0x00501FFF:0x00500000 + #define NV_UCLIP 0x00451FFF:0x00450000 + #define NV_URECT 0x004C1FFF:0x004C0000 + #define NV_UROP 0x00421FFF:0x00420000 + #define NV_ULINE 0x00491FFF:0x00490000 + #define NV_ULIN 0x004A1FFF:0x004A0000 + #define NV_UBITMAP 0x00521FFF:0x00520000 + #define NV_UTRI 0x004B1FFF:0x004B0000 + #define NV_UPATT 0x00461FFF:0x00460000 + + /***************************************** + * Definitions for DAC + *****************************************/ + + #define NV_PDAC 0x00609FFF:0x00609000 /* RW--D */ + #define NV_PDAC_WRITE_PALETTE 0x609000 + #define NV_PDAC_COLOUR_DATA 0x609004 + #define NV_PDAC_PIXEL_MASK 0x609008 + #define NV_PDAC_READ_PALETTE 0x60900c + #define NV_PDAC_INDEX_LO 0x609010 + #define NV_PDAC_INDEX_HI 0x609014 + #define NV_PDAC_INDEX_DATA 0x609018 + #define NV_PDAC_GAME_PORT 0x60901c + + + /* Extended register values */ + #define NV_PDAC_EXT_COMPANY_ID 0x00 + #define NV_PDAC_SGS_ID 0x44 + + #define NV_PDAC_EXT_DEVICE_ID 0x01 + #define NV_PDAC_1764_ID 0x64 + #define NV_PDAC_1732_ID 0x32 + + #define NV_PDAC_EXT_REVISION_ID 0x02 + + #define NV_PDAC_EXT_CONF_0 0x04 + #define NV_PDAC_CONF_0_IDC_MODE 5:5 + #define NV_PDAC_CONF_0_VGA_STATE 4:4 + #define NV_PDAC_CONF_0_PORT_WIDTH 3:2 + #define NV_PDAC_CONF_0_VISUAL_DEPTH 1:0 + + #define NV_PDAC_EXT_CONF_1 0x05 + #define NV_PDAC_CONF_1_VCLK_IMPEDANCE 3:3 + #define NV_PDAC_CONF_1_PCLK_VCLK_RATIO 2:0 + + #define NV_PDAC_EXT_RGB_PAL_CTRL 0x09 + #define NV_PDAC_EXT_RGB_PAL_CTRL_DAC_WIDTH 7:7 + #define NV_PDAC_EXT_RGB_PAL_CTRL_DAC_WIDTH_BITS_6 0x1 + #define NV_PDAC_EXT_RGB_PAL_CTRL_DAC_WIDTH_BITS_8 0x0 + + + #define NV_PDAC_EXT_VPLL_M_PARAM 0x18 + #define NV_PDAC_EXT_VPLL_N_PARAM 0x19 + #define NV_PDAC_EXT_VPLL_O_PARAM 0x1a + #define NV_PDAC_EXT_VPLL_P_PARAM 0x1b + + #define NV_PDAC_EXT_MPLL_M_PARAM 0x10 + #define NV_PDAC_EXT_MPLL_N_PARAM 0x11 + #define NV_PDAC_EXT_MPLL_O_PARAM 0x12 + #define NV_PDAC_EXT_MPLL_P_PARAM 0x13 + + + /* Hardware cursor registers */ + #define NV_PDAC_EXT_CURSOR_CTRL_A 0x20 + #define NV_PDAC_CURSOR_CTRL_A_TYPE 1:0 + #define NV_PDAC_CURSOR_CTRL_A_OFF 0 + #define NV_PDAC_CURSOR_CTRL_A_XWIN 3 + + #define NV_PDAC_EXT_CURSOR_X_POS_LO 0x22 + #define NV_PDAC_EXT_CURSOR_X_POS_HI 0x23 + + #define NV_PDAC_EXT_CURSOR_Y_POS_LO 0x24 + #define NV_PDAC_EXT_CURSOR_Y_POS_HI 0x25 + + #define NV_PDAC_EXT_CURSOR_COLOUR_1_RGB 0x50 + #define NV_PDAC_EXT_CURSOR_COLOUR_1_RED 0x50 + #define NV_PDAC_EXT_CURSOR_COLOUR_1_GREEN 0x51 + #define NV_PDAC_EXT_CURSOR_COLOUR_1_BLUE 0x52 + + #define NV_PDAC_EXT_CURSOR_COLOUR_2_RGB 0x54 + #define NV_PDAC_EXT_CURSOR_COLOUR_2_RED 0x54 + #define NV_PDAC_EXT_CURSOR_COLOUR_2_GREEN 0x55 + #define NV_PDAC_EXT_CURSOR_COLOUR_2_BLUE 0x56 + + #define NV_PDAC_EXT_CURSOR_COLOUR_3_RGB 0x58 + #define NV_PDAC_EXT_CURSOR_COLOUR_3_RED 0x58 + #define NV_PDAC_EXT_CURSOR_COLOUR_3_GREEN 0x59 + #define NV_PDAC_EXT_CURSOR_COLOUR_3_BLUE 0x5a + + #define NV_PDAC_EXT_CURSOR_PLANE_0 0x100 + #define NV_PDAC_EXT_CURSOR_PLANE_1 0x180 + + #define NV_PDAC_EXT_CURSOR_PLANE_0_READ 0x500 + #define NV_PDAC_EXT_CURSOR_PLANE_1_READ 0x580 + + #define NV_PDAC_CURSOR_SIZE 32 + #define NV_PDAC_CURSOR_PLANE_SIZE (NV_PDAC_CURSOR_SIZE*4) + + /***************************************** + * Definitions for DMA device + *****************************************/ + + #define NV_PDMA 0x00100FFF:0x00100000 /* RW--D */ + #define NV_PDMA_GR_CHANNEL 0x00100810 /* RW-4R */ + #define NV_PDMA_GR_CHANNEL_ACCESS 0:0 /* RWIVF */ + #define NV_PDMA_GR_CHANNEL_ACCESS_DISABLED 0x00000000 /* RWI-V */ + #define NV_PDMA_GR_CHANNEL_ACCESS_ENABLED 0x00000001 /* RW--V */ + #define NV_PDMA_GR_INSTANCE 0x00100880 /* RW-4R */ + #define NV_PDMA_GR_INSTANCE_ID 15:0 /* RWIUF */ + #define NV_PDMA_GR_INSTANCE_ID_0 0x00000000 /* RWI-V */ + + /***************************************** + * Defintions for frame buffer device + *****************************************/ + + #define NV_PFB 0x00600FFF:0x00600000 + + #define NV_PFB_BOOT_0 0x600000 + #define NV_PFB_BOOT_0_RAM_AMOUNT 1:0 + + #define NV_PFB_CONFIG_0 0x600200 + #define NV_PFB_CONFIG_0_VERTICAL 0:0 /* 1 during blank */ + #define NV_PFB_CONFIG_0_PIXEL_DEPTH 9:8 + #define NV_PFB_CONFIG_0_SCANLINE 20:20 + #define NV_PFB_CONFIG_0_PCLK_VCLK_RATIO 26:24 + #define NV_PFB_CONFIG_0_RESOLUTION 6:4 + + #define NV_PFB_START 0x600400 + #define NV_PFB_HOR_FRONT_PORCH 0x600500 + #define NV_PFB_HOR_SYNC_WIDTH 0x600510 + #define NV_PFB_HOR_BACK_PORCH 0x600520 + #define NV_PFB_HOR_DISP_WIDTH 0x600530 + #define NV_PFB_VER_FRONT_PORCH 0x600540 + #define NV_PFB_VER_SYNC_WIDTH 0x600550 + #define NV_PFB_VER_BACK_PORCH 0x600560 + #define NV_PFB_VER_DISP_WIDTH 0x600570 + + + /* Green registers */ + #define NV_PFB_GREEN_0 0x006000C0 /* RW-4R */ + #define NV_PFB_GREEN_0_LEVEL 1:0 /* RWIVF */ + #define NV_PFB_GREEN_0_LEVEL_VIDEO_ENABLED 0x00000000 /* RW--V */ + #define NV_PFB_GREEN_0_LEVEL_VIDEO_DISABLED 0x00000001 /* RW--V */ + #define NV_PFB_GREEN_0_LEVEL_TIMING_DISABLED 0x00000002 /* RW--V */ + #define NV_PFB_GREEN_0_LEVEL_MEMORY_DISABLED 0x00000003 /* RWI-V */ + #define NV_PFB_GREEN_0_POLAR_HSYNC 17:16 /* RWIVF */ + #define NV_PFB_GREEN_0_POLAR_HSYNC_HIGH 0x00000000 /* RWI-V */ + #define NV_PFB_GREEN_0_POLAR_HSYNC_LOW 0x00000001 /* RW--V */ + #define NV_PFB_GREEN_0_POLAR_HSYNC_POSITIVE 0x00000002 /* RW--V */ + #define NV_PFB_GREEN_0_POLAR_HSYNC_NEGATIVE 0x00000003 /* RW--V */ + #define NV_PFB_GREEN_0_POLAR_VSYNC 21:20 /* RWIVF */ + #define NV_PFB_GREEN_0_POLAR_VSYNC_LOW 0x00000000 /* RWI-V */ + #define NV_PFB_GREEN_0_POLAR_VSYNC_HIGH 0x00000001 /* RW--V */ + #define NV_PFB_GREEN_0_POLAR_VSYNC_POSITIVE 0x00000002 /* RW--V */ + #define NV_PFB_GREEN_0_POLAR_VSYNC_NEGATIVE 0x00000003 /* RW--V */ + #define NV_PFB_GREEN_0_CSYNC 24:24 /* RWIVF */ + #define NV_PFB_GREEN_0_CSYNC_DISABLED 0x00000000 /* RWI-V */ + #define NV_PFB_GREEN_0_CSYNC_ENABLED 0x00000001 /* RW--V */ + + + /***************************************** + * Definitions for FIFO + *****************************************/ + + #define NV_PFIFO 0x00003FFF:0x00002000 /* RW--D */ + + #define NV_PFIFO_INTR_0 0x00002100 /* RW-4R */ + #define NV_PFIFO_INTR_0_CACHE_ERROR 0:0 /* RWXVF */ + #define NV_PFIFO_INTR_0_CACHE_ERROR_NOT_PENDING 0x00000000 /* R---V */ + #define NV_PFIFO_INTR_0_CACHE_ERROR_PENDING 0x00000001 /* R---V */ + #define NV_PFIFO_INTR_0_CACHE_ERROR_RESET 0x00000001 /* -W--V */ + #define NV_PFIFO_INTR_0_RUNOUT 4:4 /* RWXVF */ + #define NV_PFIFO_INTR_0_RUNOUT_NOT_PENDING 0x00000000 /* R---V */ + #define NV_PFIFO_INTR_0_RUNOUT_PENDING 0x00000001 /* R---V */ + #define NV_PFIFO_INTR_0_RUNOUT_RESET 0x00000001 /* -W--V */ + #define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW 8:8 /* RWXVF */ + #define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW_NOT_PENDING 0x00000000 /* R---V */ + #define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW_PENDING 0x00000001 /* R---V */ + #define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW_RESET 0x00000001 /* -W--V */ + + #define NV_PFIFO_INTR_EN_0 0x00002140 /* RW-4R */ + #define NV_PFIFO_INTR_EN_0_CACHE_ERROR 0:0 /* RWIVF */ + #define NV_PFIFO_INTR_EN_0_CACHE_ERROR_DISABLED 0x00000000 /* RWI-V */ + #define NV_PFIFO_INTR_EN_0_CACHE_ERROR_ENABLED 0x00000001 /* RW--V */ + #define NV_PFIFO_INTR_EN_0_RUNOUT 4:4 /* RWIVF */ + #define NV_PFIFO_INTR_EN_0_RUNOUT_DISABLED 0x00000000 /* RWI-V */ + #define NV_PFIFO_INTR_EN_0_RUNOUT_ENABLED 0x00000001 /* RW--V */ + #define NV_PFIFO_INTR_EN_0_RUNOUT_OVERFLOW 8:8 /* RWIVF */ + #define NV_PFIFO_INTR_EN_0_RUNOUT_OVERFLOW_DISABLED 0x00000000 /* RWI-V */ + #define NV_PFIFO_INTR_EN_0_RUNOUT_OVERFLOW_ENABLED 0x00000001 /* RW--V */ + + #define NV_PFIFO_CONFIG_0 0x00002200 /* RW-4R */ + #define NV_PFIFO_CONFIG_0_FREE_LIE 1:0 /* RWXVF */ + #define NV_PFIFO_CONFIG_0_FREE_LIE_DISABLED 0x00000000 /* RW--V */ + #define NV_PFIFO_CONFIG_0_FREE_LIE_252_BYTES 0x00000001 /* RW--V */ + #define NV_PFIFO_CONFIG_0_FREE_LIE_508_BYTES 0x00000002 /* RW--V */ + #define NV_PFIFO_CONFIG_0_FREE_LIE_1020_BYTES 0x00000003 /* RW--V */ + + #define NV_PFIFO_CACHES 0x00002500 /* RW-4R */ + #define NV_PFIFO_CACHES_REASSIGN 0:0 /* RWIVF */ + #define NV_PFIFO_CACHES_REASSIGN_DISABLED 0x00000000 /* RWI-V */ + #define NV_PFIFO_CACHES_REASSIGN_ENABLED 0x00000001 /* RW--V */ + #define NV_PFIFO_CACHE0_PUSH0 0x00003000 /* RW-4R */ + #define NV_PFIFO_CACHE0_PUSH0_ACCESS 0:0 /* RWIVF */ + #define NV_PFIFO_CACHE0_PUSH0_ACCESS_DISABLED 0x00000000 /* RWI-V */ + #define NV_PFIFO_CACHE0_PUSH0_ACCESS_ENABLED 0x00000001 /* RW--V */ + #define NV_PFIFO_CACHE1_PUSH0 0x00003200 /* RW-4R */ + #define NV_PFIFO_CACHE1_PUSH0_ACCESS 0:0 /* RWIVF */ + #define NV_PFIFO_CACHE1_PUSH0_ACCESS_DISABLED 0x00000000 /* RWI-V */ + #define NV_PFIFO_CACHE1_PUSH0_ACCESS_ENABLED 0x00000001 /* RW--V */ + #define NV_PFIFO_CACHE0_PUSH1 0x00003010 /* RW-4R */ + #define NV_PFIFO_CACHE0_PUSH1_CHID 6:0 /* RWXUF */ + #define NV_PFIFO_CACHE1_PUSH1 0x00003210 /* RW-4R */ + #define NV_PFIFO_CACHE1_PUSH1_CHID 6:0 /* RWXUF */ + #define NV_PFIFO_CACHE0_PULL0 0x00003040 /* RW-4R */ + #define NV_PFIFO_CACHE0_PULL0_ACCESS 0:0 /* RWIVF */ + #define NV_PFIFO_CACHE0_PULL0_ACCESS_DISABLED 0x00000000 /* RWI-V */ + #define NV_PFIFO_CACHE0_PULL0_ACCESS_ENABLED 0x00000001 /* RW--V */ + #define NV_PFIFO_CACHE1_PULL0 0x00003240 /* R--4R */ + #define NV_PFIFO_CACHE1_PULL0_ACCESS 0:0 /* RWIVF */ + #define NV_PFIFO_CACHE1_PULL0_ACCESS_DISABLED 0x00000000 /* RWI-V */ + #define NV_PFIFO_CACHE1_PULL0_ACCESS_ENABLED 0x00000001 /* RW--V */ + #define NV_PFIFO_CACHE1_PULL0_HASH 4:4 /* R-XVF */ + #define NV_PFIFO_CACHE1_PULL0_HASH_SUCCEEDED 0x00000000 /* R---V */ + #define NV_PFIFO_CACHE1_PULL0_HASH_FAILED 0x00000001 /* R---V */ + #define NV_PFIFO_CACHE1_PULL0_DEVICE 8:8 /* R-XVF */ + #define NV_PFIFO_CACHE1_PULL0_DEVICE_HARDWARE 0x00000000 /* R---V */ + #define NV_PFIFO_CACHE1_PULL0_DEVICE_SOFTWARE 0x00000001 /* R---V */ + #define NV_PFIFO_CACHE0_PULL1 0x00003050 /* RW-4R */ + #define NV_PFIFO_CACHE0_PULL1_OBJECT 8:8 /* RWXVF */ + #define NV_PFIFO_CACHE0_PULL1_OBJECT_UNCHANGED 0x00000000 /* RW--V */ + #define NV_PFIFO_CACHE0_PULL1_OBJECT_CHANGED 0x00000001 /* RW--V */ + #define NV_PFIFO_CACHE1_PULL1 0x00003250 /* RW-4R */ + #define NV_PFIFO_CACHE1_PULL1_SUBCHANNEL 2:0 /* RWXUF */ + #define NV_PFIFO_CACHE1_PULL1_CTX 4:4 /* RWXVF */ + #define NV_PFIFO_CACHE1_PULL1_CTX_CLEAN 0x00000000 /* RW--V */ + #define NV_PFIFO_CACHE1_PULL1_CTX_DIRTY 0x00000001 /* RW--V */ + #define NV_PFIFO_CACHE1_PULL1_OBJECT 8:8 /* RWXVF */ + #define NV_PFIFO_CACHE1_PULL1_OBJECT_UNCHANGED 0x00000000 /* RW--V */ + #define NV_PFIFO_CACHE1_PULL1_OBJECT_CHANGED 0x00000001 /* RW--V */ + + #define NV_PFIFO_CACHE0_PUT 0x00003030 /* RW-4R */ + #define NV_PFIFO_CACHE0_PUT_ADDRESS 2:2 /* RWXUF */ + #define NV_PFIFO_CACHE1_PUT 0x00003230 /* RW-4R */ + #define NV_PFIFO_CACHE1_PUT_ADDRESS 6:2 /* RWXUF */ + #define NV_PFIFO_CACHE0_GET 0x00003070 /* RW-4R */ + #define NV_PFIFO_CACHE0_GET_ADDRESS 2:2 /* RWXUF */ + #define NV_PFIFO_CACHE1_GET 0x00003270 /* RW-4R */ + #define NV_PFIFO_CACHE1_GET_ADDRESS 6:2 /* RWXUF */ + + #define NV_PFIFO_CACHE0_CTX(i) (0x00003080+(i)*16) /* RW-4A */ + #define NV_PFIFO_CACHE0_CTX__SIZE_1 1 /* */ + + #define NV_PFIFO_CACHE1_CTX(i) (0x00003280+(i)*16) /* RW-4A */ + #define NV_PFIFO_CACHE1_CTX__SIZE_1 8 /* */ + + + #define NV_PFIFO_RUNOUT_PUT 0x00002410 /* RW-4R */ + #define NV_PFIFO_RUNOUT_GET 0x00002420 /* RW-4R */ + + /***************************************** + * Definitions for PGRAPH device + *****************************************/ + + #define NV_PGRAPH 0x00400FFF:0x00400000 /* RW--D */ + + #define NV_PGRAPH_DEBUG_0 0x00400080 /* RW-4R */ + #define NV_PGRAPH_DEBUG_0_STATE 0:0 /* CW-VF */ + #define NV_PGRAPH_DEBUG_0_STATE_NORMAL 0x00000000 /* CW--V */ + #define NV_PGRAPH_DEBUG_0_STATE_RESET 0x00000001 /* -W--V */ + #define NV_PGRAPH_DEBUG_0_BULK_READS 4:4 /* RWIVF */ + #define NV_PGRAPH_DEBUG_0_BULK_READS_DISABLED 0x00000000 /* RWI-V */ + #define NV_PGRAPH_DEBUG_0_BULK_READS_ENABLED 0x00000001 /* RW--V */ + #define NV_PGRAPH_DEBUG_0_BLOCK 8:8 /* RWIVF */ + #define NV_PGRAPH_DEBUG_0_BLOCK_DISABLED 0x00000000 /* RWI-V */ + #define NV_PGRAPH_DEBUG_0_BLOCK_ENABLED 0x00000001 /* RW--V */ + #define NV_PGRAPH_DEBUG_0_BLOCK_BROAD 12:12 /* RWIVF */ + #define NV_PGRAPH_DEBUG_0_BLOCK_BROAD_DISABLED 0x00000000 /* RWI-V */ + #define NV_PGRAPH_DEBUG_0_BLOCK_BROAD_ENABLED 0x00000001 /* RW--V */ + #define NV_PGRAPH_DEBUG_0_NONBLOCK_BROAD 16:16 /* RWIVF */ + #define NV_PGRAPH_DEBUG_0_NONBLOCK_BROAD_DISABLED 0x00000000 /* RWI-V */ + #define NV_PGRAPH_DEBUG_0_NONBLOCK_BROAD_ENABLED 0x00000001 /* RW--V */ + #define NV_PGRAPH_DEBUG_0_WRITE_ONLY_ROPS 20:20 /* RWIVF */ + #define NV_PGRAPH_DEBUG_0_WRITE_ONLY_ROPS_DISABLED 0x00000000 /* RWI-V */ + #define NV_PGRAPH_DEBUG_0_WRITE_ONLY_ROPS_ENABLED 0x00000001 /* RW--V */ + #define NV_PGRAPH_DEBUG_0_EDGE_FILLING 24:24 /* RWIVF */ + #define NV_PGRAPH_DEBUG_0_EDGE_FILLING_DISABLED 0x00000000 /* RWI-V */ + #define NV_PGRAPH_DEBUG_0_EDGE_FILLING_ENABLED 0x00000001 /* RW--V */ + #define NV_PGRAPH_DEBUG_0_ALPHA_ABORT 28:28 /* RWIVF */ + #define NV_PGRAPH_DEBUG_0_ALPHA_ABORT_DISABLED 0x00000000 /* RWI-V */ + #define NV_PGRAPH_DEBUG_0_ALPHA_ABORT_ENABLED 0x00000001 /* RW--V */ + + #define NV_PGRAPH_DEBUG_1 0x00400084 /* RW-4R */ + #define NV_PGRAPH_DEBUG_1_VOLATILE_RESET 0:0 /* RWIVF */ + #define NV_PGRAPH_DEBUG_1_VOLATILE_RESET_NOT_LAST 0x00000000 /* RWI-V */ + #define NV_PGRAPH_DEBUG_1_VOLATILE_RESET_LAST 0x00000001 /* RW--V */ + #define NV_PGRAPH_DEBUG_1_DMA_ACTIVITY 4:4 /* CW-VF */ + #define NV_PGRAPH_DEBUG_1_DMA_ACTIVITY_IGNORE 0x00000000 /* CW--V */ + #define NV_PGRAPH_DEBUG_1_DMA_ACTIVITY_CANCEL 0x00000001 /* -W--V */ + #define NV_PGRAPH_DEBUG_1_BI_RECTS 8:8 /* RWIVF */ + #define NV_PGRAPH_DEBUG_1_BI_RECTS_DISABLED 0x00000000 /* RWI-V */ + #define NV_PGRAPH_DEBUG_1_BI_RECTS_ENABLED 0x00000001 /* RW--V */ + #define NV_PGRAPH_DEBUG_1_TRI_OPTS 12:12 /* RWIVF */ + #define NV_PGRAPH_DEBUG_1_TRI_OPTS_DISABLED 0x00000000 /* RWI-V */ + #define NV_PGRAPH_DEBUG_1_TRI_OPTS_ENABLED 0x00000001 /* RW--V */ + #define NV_PGRAPH_DEBUG_1_PATT_BLOCK 16:16 /* RWIVF */ + #define NV_PGRAPH_DEBUG_1_PATT_BLOCK_DISABLED 0x00000000 /* RWI-V */ + #define NV_PGRAPH_DEBUG_1_PATT_BLOCK_ENABLED 0x00000001 /* RW--V */ + #define NV_PGRAPH_DEBUG_1_FAST_RMW_BLITS 20:20 /* RWIVF */ + #define NV_PGRAPH_DEBUG_1_FAST_RMW_BLITS_DISABLED 0x00000000 /* RWI-V */ + #define NV_PGRAPH_DEBUG_1_FAST_RMW_BLITS_ENABLED 0x00000001 /* RW--V */ + #define NV_PGRAPH_DEBUG_1_TM_QUAD_HANDOFF 24:24 /* RWIVF */ + #define NV_PGRAPH_DEBUG_1_TM_QUAD_HANDOFF_DISABLED 0x00000000 /* RWI-V */ + #define NV_PGRAPH_DEBUG_1_TM_QUAD_HANDOFF_ENABLED 0x00000001 /* RW--V */ + #define NV_PGRAPH_DEBUG_1_FAST_BUS 28:28 /* RWIVF */ + #define NV_PGRAPH_DEBUG_1_FAST_BUS_DISABLED 0x00000000 /* RWI-V */ + #define NV_PGRAPH_DEBUG_1_FAST_BUS_ENABLED 0x00000001 /* RW--V */ + #define NV_PGRAPH_DEBUG_1_HIRES_TM 29:29 /* RWIVF */ + #define NV_PGRAPH_DEBUG_1_HIRES_TM_DISABLED 0x00000000 /* RWI-V */ + #define NV_PGRAPH_DEBUG_1_HIRES_TM_ENABLED 0x00000001 /* RW--V */ + + #define NV_PGRAPH_DEBUG_2 0x00400088 /* RW-4R */ + #define NV_PGRAPH_DEBUG_2_AVOID_RMW_BLEND 0:0 /* RWIVF */ + #define NV_PGRAPH_DEBUG_2_AVOID_RMW_BLEND_DISABLED 0x00000000 /* RWI-V */ + #define NV_PGRAPH_DEBUG_2_AVOID_RMW_BLEND_ENABLED 0x00000001 /* RW--V */ + #define NV_PGRAPH_DEBUG_2_ALPHA_ABORT 4:4 /* RWIVF */ + #define NV_PGRAPH_DEBUG_2_ALPHA_ABORT_DISABLED 0x00000000 /* RWI-V */ + #define NV_PGRAPH_DEBUG_2_ALPHA_ABORT_ENABLED 0x00000001 /* RW--V */ + #define NV_PGRAPH_DEBUG_2_BETA_ABORT 8:8 /* RWIVF */ + #define NV_PGRAPH_DEBUG_2_BETA_ABORT_DISABLED 0x00000000 /* RWI-V */ + #define NV_PGRAPH_DEBUG_2_BETA_ABORT_ENABLED 0x00000001 /* RW--V */ + #define NV_PGRAPH_DEBUG_2_MONO_ABORT 12:12 /* RWIVF */ + #define NV_PGRAPH_DEBUG_2_MONO_ABORT_DISABLED 0x00000000 /* RWI-V */ + #define NV_PGRAPH_DEBUG_2_MONO_ABORT_ENABLED 0x00000001 /* RW--V */ + #define NV_PGRAPH_DEBUG_2_TRAPEZOID_TEXEL 16:16 /* RWIVF */ + #define NV_PGRAPH_DEBUG_2_TRAPEZOID_TEXEL_DISABLED 0x00000000 /* RWI-V */ + #define NV_PGRAPH_DEBUG_2_TRAPEZOID_TEXEL_ENABLED 0x00000001 /* RW--V */ + #define NV_PGRAPH_DEBUG_2_BUSY_PATIENCE 20:20 /* RWIVF */ + #define NV_PGRAPH_DEBUG_2_BUSY_PATIENCE_DISABLED 0x00000000 /* RWI-V */ + #define NV_PGRAPH_DEBUG_2_BUSY_PATIENCE_ENABLED 0x00000001 /* RW--V */ + #define NV_PGRAPH_DEBUG_2_TM_FASTINPUT 24:24 /* RWIVF */ + #define NV_PGRAPH_DEBUG_2_TM_FASTINPUT_DISABLED 0x00000000 /* RWI-V */ + #define NV_PGRAPH_DEBUG_2_TM_FASTINPUT_ENABLED 0x00000001 /* RW--V */ + #define NV_PGRAPH_DEBUG_2_VOLATILE_RESET 28:28 /* RWIVF */ + #define NV_PGRAPH_DEBUG_2_VOLATILE_RESET_DISABLED 0x00000000 /* RWI-V */ + #define NV_PGRAPH_DEBUG_2_VOLATILE_RESET_ENABLED 0x00000001 /* RW--V */ + + #define NV_PGRAPH_DEBUG_3 0x0040008c /* RW-4R */ + #define NV_PGRAPH_DEBUG_3_TM_RANGE_INTERRUPT 0:0 /* RWIVF */ + #define NV_PGRAPH_DEBUG_3_TM_RANGE_INTERRUPT_DISABLED 0x00000000 /* RWI-V */ + #define NV_PGRAPH_DEBUG_3_TM_RANGE_INTERRUPT_ENABLED 0x00000001 /* RW--V */ + #define NV_PGRAPH_DEBUG_3_MONO_BLOCK 4:4 /* RWIVF */ + #define NV_PGRAPH_DEBUG_3_MONO_BLOCK_DISABLED 0x00000000 /* RWI-V */ + #define NV_PGRAPH_DEBUG_3_MONO_BLOCK_ENABLED 0x00000001 /* RW--V */ + + #define NV_PGRAPH_INTR_0 0x00400100 /* RW-4R */ + #define NV_PGRAPH_INTR_0_RESERVED 0:0 /* RW-VF */ + #define NV_PGRAPH_INTR_0_RESERVED_NOT_PENDING 0x00000000 /* R---V */ + #define NV_PGRAPH_INTR_0_RESERVED_PENDING 0x00000001 /* R---V */ + #define NV_PGRAPH_INTR_0_RESERVED_RESET 0x00000001 /* -W--V */ + #define NV_PGRAPH_INTR_0_CONTEXT_SWITCH 4:4 /* RWIVF */ + #define NV_PGRAPH_INTR_0_CONTEXT_SWITCH_NOT_PENDING 0x00000000 /* R-I-V */ + #define NV_PGRAPH_INTR_0_CONTEXT_SWITCH_PENDING 0x00000001 /* R---V */ + #define NV_PGRAPH_INTR_0_CONTEXT_SWITCH_RESET 0x00000001 /* -W--V */ + #define NV_PGRAPH_INTR_0_VBLANK 8:8 /* RWIVF */ + #define NV_PGRAPH_INTR_0_VBLANK_NOT_PENDING 0x00000000 /* R-I-V */ + #define NV_PGRAPH_INTR_0_VBLANK_PENDING 0x00000001 /* R---V */ + #define NV_PGRAPH_INTR_0_VBLANK_RESET 0x00000001 /* -W--V */ + #define NV_PGRAPH_INTR_0_RANGE 12:12 /* RWIVF */ + #define NV_PGRAPH_INTR_0_RANGE_NOT_PENDING 0x00000000 /* R-I-V */ + #define NV_PGRAPH_INTR_0_RANGE_PENDING 0x00000001 /* R---V */ + #define NV_PGRAPH_INTR_0_RANGE_RESET 0x00000001 /* -W--V */ + #define NV_PGRAPH_INTR_0_METHOD_COUNT 16:16 /* RWIVF */ + #define NV_PGRAPH_INTR_0_METHOD_COUNT_NOT_PENDING 0x00000000 /* R-I-V */ + #define NV_PGRAPH_INTR_0_METHOD_COUNT_PENDING 0x00000001 /* R---V */ + #define NV_PGRAPH_INTR_0_METHOD_COUNT_RESET 0x00000001 /* -W--V */ + #define NV_PGRAPH_INTR_0_SOFTWARE 20:20 /* RWIVF */ + #define NV_PGRAPH_INTR_0_SOFTWARE_NOT_PENDING 0x00000000 /* R-I-V */ + #define NV_PGRAPH_INTR_0_SOFTWARE_PENDING 0x00000001 /* R---V */ + #define NV_PGRAPH_INTR_0_SOFTWARE_RESET 0x00000001 /* -W--V */ + #define NV_PGRAPH_INTR_0_COMPLEX_CLIP 24:24 /* RWIVF */ + #define NV_PGRAPH_INTR_0_COMPLEX_CLIP_NOT_PENDING 0x00000000 /* R-I-V */ + #define NV_PGRAPH_INTR_0_COMPLEX_CLIP_PENDING 0x00000001 /* R---V */ + #define NV_PGRAPH_INTR_0_COMPLEX_CLIP_RESET 0x00000001 /* -W--V */ + #define NV_PGRAPH_INTR_0_NOTIFY 28:28 /* RWIVF */ + #define NV_PGRAPH_INTR_0_NOTIFY_NOT_PENDING 0x00000000 /* R-I-V */ + #define NV_PGRAPH_INTR_0_NOTIFY_PENDING 0x00000001 /* R---V */ + #define NV_PGRAPH_INTR_0_NOTIFY_RESET 0x00000001 /* -W--V */ + + #define NV_PGRAPH_INTR_1 0x00400104 /* RW-4R */ + #define NV_PGRAPH_INTR_1_METHOD 0:0 /* RWIVF */ + #define NV_PGRAPH_INTR_1_METHOD_NOT_PENDING 0x00000000 /* R-I-V */ + #define NV_PGRAPH_INTR_1_METHOD_PENDING 0x00000001 /* R---V */ + #define NV_PGRAPH_INTR_1_METHOD_RESET 0x00000001 /* -W--V */ + #define NV_PGRAPH_INTR_1_DATA 4:4 /* RWIVF */ + #define NV_PGRAPH_INTR_1_DATA_NOT_PENDING 0x00000000 /* R-I-V */ + #define NV_PGRAPH_INTR_1_DATA_PENDING 0x00000001 /* R---V */ + #define NV_PGRAPH_INTR_1_DATA_RESET 0x00000001 /* -W--V */ + #define NV_PGRAPH_INTR_1_NOTIFY_INST 8:8 /* RWIVF */ + #define NV_PGRAPH_INTR_1_NOTIFY_INST_NOT_PENDING 0x00000000 /* R-I-V */ + #define NV_PGRAPH_INTR_1_NOTIFY_INST_PENDING 0x00000001 /* R---V */ + #define NV_PGRAPH_INTR_1_NOTIFY_INST_RESET 0x00000001 /* -W--V */ + #define NV_PGRAPH_INTR_1_DOUBLE_NOTIFY 12:12 /* RWIVF */ + #define NV_PGRAPH_INTR_1_DOUBLE_NOTIFY_NOT_PENDING 0x00000000 /* R-I-V */ + #define NV_PGRAPH_INTR_1_DOUBLE_NOTIFY_PENDING 0x00000001 /* R---V */ + #define NV_PGRAPH_INTR_1_DOUBLE_NOTIFY_RESET 0x00000001 /* -W--V */ + #define NV_PGRAPH_INTR_1_CTXSW_NOTIFY 16:16 /* RWIVF */ + #define NV_PGRAPH_INTR_1_CTXSW_NOTIFY_NOT_PENDING 0x00000000 /* R-I-V */ + #define NV_PGRAPH_INTR_1_CTXSW_NOTIFY_PENDING 0x00000001 /* R---V */ + #define NV_PGRAPH_INTR_1_CTXSW_NOTIFY_RESET 0x00000001 /* -W--V */ + + #define NV_PGRAPH_INTR_EN_0 0x00400140 /* RW-4R */ + #define NV_PGRAPH_INTR_EN_0_RESERVED 0:0 /* RWIVF */ + #define NV_PGRAPH_INTR_EN_0_RESERVED_DISABLED 0x00000000 /* RWI-V */ + #define NV_PGRAPH_INTR_EN_0_RESERVED_ENABLED 0x00000001 /* RW--V */ + #define NV_PGRAPH_INTR_EN_0_CONTEXT_SWITCH 4:4 /* RWIVF */ + #define NV_PGRAPH_INTR_EN_0_CONTEXT_SWITCH_DISABLED 0x00000000 /* RWI-V */ + #define NV_PGRAPH_INTR_EN_0_CONTEXT_SWITCH_ENABLED 0x00000001 /* RW--V */ + #define NV_PGRAPH_INTR_EN_0_VBLANK 8:8 /* RWIVF */ + #define NV_PGRAPH_INTR_EN_0_VBLANK_DISABLED 0x00000000 /* RWI-V */ + #define NV_PGRAPH_INTR_EN_0_VBLANK_ENABLED 0x00000001 /* RW--V */ + #define NV_PGRAPH_INTR_EN_0_RANGE 12:12 /* RWIVF */ + #define NV_PGRAPH_INTR_EN_0_RANGE_DISABLED 0x00000000 /* RWI-V */ + #define NV_PGRAPH_INTR_EN_0_RANGE_ENABLED 0x00000001 /* RW--V */ + #define NV_PGRAPH_INTR_EN_0_METHOD_COUNT 16:16 /* RWIVF */ + #define NV_PGRAPH_INTR_EN_0_METHOD_COUNT_DISABLED 0x00000000 /* RWI-V */ + #define NV_PGRAPH_INTR_EN_0_METHOD_COUNT_ENABLED 0x00000001 /* RW--V */ + #define NV_PGRAPH_INTR_EN_0_SOFTWARE 20:20 /* RWIVF */ + #define NV_PGRAPH_INTR_EN_0_SOFTWARE_DISABLED 0x00000000 /* RWI-V */ + #define NV_PGRAPH_INTR_EN_0_SOFTWARE_ENABLED 0x00000001 /* RW--V */ + #define NV_PGRAPH_INTR_EN_0_COMPLEX_CLIP 24:24 /* RWIVF */ + #define NV_PGRAPH_INTR_EN_0_COMPLEX_CLIP_DISABLED 0x00000000 /* RWI-V */ + #define NV_PGRAPH_INTR_EN_0_COMPLEX_CLIP_ENABLED 0x00000001 /* RW--V */ + #define NV_PGRAPH_INTR_EN_0_NOTIFY 28:28 /* RWIVF */ + #define NV_PGRAPH_INTR_EN_0_NOTIFY_DISABLED 0x00000000 /* RWI-V */ + #define NV_PGRAPH_INTR_EN_0_NOTIFY_ENABLED 0x00000001 /* RW--V */ + + #define NV_PGRAPH_INTR_EN_1 0x00400144 /* RW-4R */ + #define NV_PGRAPH_INTR_EN_1_METHOD 0:0 /* RWIVF */ + #define NV_PGRAPH_INTR_EN_1_METHOD_DISABLED 0x00000000 /* RWI-V */ + #define NV_PGRAPH_INTR_EN_1_METHOD_ENABLED 0x00000001 /* RW--V */ + #define NV_PGRAPH_INTR_EN_1_DATA 4:4 /* RWIVF */ + #define NV_PGRAPH_INTR_EN_1_DATA_DISABLED 0x00000000 /* RWI-V */ + #define NV_PGRAPH_INTR_EN_1_DATA_ENABLED 0x00000001 /* RW--V */ + #define NV_PGRAPH_INTR_EN_1_NOTIFY_INST 8:8 /* RWIVF */ + #define NV_PGRAPH_INTR_EN_1_NOTIFY_INST_DISABLED 0x00000000 /* RWI-V */ + #define NV_PGRAPH_INTR_EN_1_NOTIFY_INST_ENABLED 0x00000001 /* RW--V */ + #define NV_PGRAPH_INTR_EN_1_DOUBLE_NOTIFY 12:12 /* RWIVF */ + #define NV_PGRAPH_INTR_EN_1_DOUBLE_NOTIFY_DISABLED 0x00000000 /* RWI-V */ + #define NV_PGRAPH_INTR_EN_1_DOUBLE_NOTIFY_ENABLED 0x00000001 /* RW--V */ + #define NV_PGRAPH_INTR_EN_1_CTXSW_NOTIFY 16:16 /* RWIVF */ + #define NV_PGRAPH_INTR_EN_1_CTXSW_NOTIFY_DISABLED 0x00000000 /* RWI-V */ + #define NV_PGRAPH_INTR_EN_1_CTXSW_NOTIFY_ENABLED 0x00000001 /* RW--V */ + + #define NV_PGRAPH_CTX_SWITCH 0x00400180 /* RW-4R */ + + #define NV_PGRAPH_CTX_CONTROL 0x00400190 /* RW-4R */ + #define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME 1:0 /* RWIVF */ + #define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME_33US 0x00000000 /* RWI-V */ + #define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME_262US 0x00000001 /* RW--V */ + #define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME_2MS 0x00000002 /* RW--V */ + #define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME_17MS 0x00000003 /* RW--V */ + #define NV_PGRAPH_CTX_CONTROL_TIME 8:8 /* RWIVF */ + #define NV_PGRAPH_CTX_CONTROL_TIME_EXPIRED 0x00000000 /* RWI-V */ + #define NV_PGRAPH_CTX_CONTROL_TIME_NOT_EXPIRED 0x00000001 /* RW--V */ + #define NV_PGRAPH_CTX_CONTROL_CHID 16:16 /* RWIVF */ + #define NV_PGRAPH_CTX_CONTROL_CHID_INVALID 0x00000000 /* RWI-V */ + #define NV_PGRAPH_CTX_CONTROL_CHID_VALID 0x00000001 /* RW--V */ + #define NV_PGRAPH_CTX_CONTROL_SWITCH 20:20 /* R--VF */ + #define NV_PGRAPH_CTX_CONTROL_SWITCH_UNAVAILABLE 0x00000000 /* R---V */ + #define NV_PGRAPH_CTX_CONTROL_SWITCH_AVAILABLE 0x00000001 /* R---V */ + #define NV_PGRAPH_CTX_CONTROL_SWITCHING 24:24 /* RWIVF */ + #define NV_PGRAPH_CTX_CONTROL_SWITCHING_IDLE 0x00000000 /* RWI-V */ + #define NV_PGRAPH_CTX_CONTROL_SWITCHING_BUSY 0x00000001 /* RW--V */ + #define NV_PGRAPH_CTX_CONTROL_DEVICE 28:28 /* RWIVF */ + #define NV_PGRAPH_CTX_CONTROL_DEVICE_DISABLED 0x00000000 /* RWI-V */ + #define NV_PGRAPH_CTX_CONTROL_DEVICE_ENABLED 0x00000001 /* RW--V */ + + #define NV_PGRAPH_MISC 0x004006A4 /* RW-4R */ + #define NV_PGRAPH_MISC_FIFO 0:0 /* RWIVF */ + #define NV_PGRAPH_MISC_FIFO_DISABLED 0x00000000 /* RW--V */ + #define NV_PGRAPH_MISC_FIFO_ENABLED 0x00000001 /* RWI-V */ + #define NV_PGRAPH_MISC_DMA 4:4 /* RWIVF */ + #define NV_PGRAPH_MISC_DMA_DISABLED 0x00000000 /* RW--V */ + #define NV_PGRAPH_MISC_DMA_ENABLED 0x00000001 /* RWI-V */ + #define NV_PGRAPH_MISC_FLOWTHRU 8:8 /* RWIVF */ + #define NV_PGRAPH_MISC_FLOWTHRU_DISABLED 0x00000000 /* RW--V */ + #define NV_PGRAPH_MISC_FLOWTHRU_ENABLED 0x00000001 /* RWI-V */ + #define NV_PGRAPH_MISC_CLASS 16:12 /* RWXVF */ + #define NV_PGRAPH_MISC_FIFO_WRITE 24:24 /* CW-VF */ + #define NV_PGRAPH_MISC_FIFO_WRITE_IGNORED 0x00000000 /* -W--V */ + #define NV_PGRAPH_MISC_FIFO_WRITE_ENABLED 0x00000001 /* CW--V */ + #define NV_PGRAPH_MISC_DMA_WRITE 25:25 /* CW-VF */ + #define NV_PGRAPH_MISC_DMA_WRITE_IGNORED 0x00000000 /* -W--V */ + #define NV_PGRAPH_MISC_DMA_WRITE_ENABLED 0x00000001 /* CW--V */ + #define NV_PGRAPH_MISC_FLOWTHRU_WRITE 26:26 /* CW-VF */ + #define NV_PGRAPH_MISC_FLOWTHRU_WRITE_IGNORED 0x00000000 /* -W--V */ + #define NV_PGRAPH_MISC_FLOWTHRU_WRITE_ENABLED 0x00000001 /* CW--V */ + #define NV_PGRAPH_MISC_CLASS_WRITE 27:27 /* CW-VF */ + #define NV_PGRAPH_MISC_CLASS_WRITE_IGNORED 0x00000000 /* -W--V */ + #define NV_PGRAPH_MISC_CLASS_WRITE_ENABLED 0x00000001 /* CW--V */ + + #define NV_PGRAPH_STATUS 0x004006B0 /* R--4R */ + #define NV_PGRAPH_STATUS_STATE 0:0 /* R-IVF */ + #define NV_PGRAPH_STATUS_STATE_IDLE 0x00000000 /* R-I-V */ + #define NV_PGRAPH_STATUS_STATE_BUSY 0x00000001 /* R---V */ + #define NV_PGRAPH_STATUS_XY_LOGIC 4:4 /* R-IVF */ + #define NV_PGRAPH_STATUS_XY_LOGIC_IDLE 0x00000000 /* R-I-V */ + #define NV_PGRAPH_STATUS_XY_LOGIC_BUSY 0x00000001 /* R---V */ + #define NV_PGRAPH_STATUS_PORT_NOTIFY 8:8 /* R-IVF */ + #define NV_PGRAPH_STATUS_PORT_NOTIFY_IDLE 0x00000000 /* R-I-V */ + #define NV_PGRAPH_STATUS_PORT_NOTIFY_BUSY 0x00000001 /* R---V */ + #define NV_PGRAPH_STATUS_PORT_REGISTER 12:12 /* R-IVF */ + #define NV_PGRAPH_STATUS_PORT_REGISTER_IDLE 0x00000000 /* R-I-V */ + #define NV_PGRAPH_STATUS_PORT_REGISTER_BUSY 0x00000001 /* R---V */ + #define NV_PGRAPH_STATUS_PORT_DMA 16:16 /* R-IVF */ + #define NV_PGRAPH_STATUS_PORT_DMA_IDLE 0x00000000 /* R-I-V */ + #define NV_PGRAPH_STATUS_PORT_DMA_BUSY 0x00000001 /* R---V */ + #define NV_PGRAPH_STATUS_DMA_NOTIFY 20:20 /* R-IVF */ + #define NV_PGRAPH_STATUS_DMA_NOTIFY_IDLE 0x00000000 /* R-I-V */ + #define NV_PGRAPH_STATUS_DMA_NOTIFY_BUSY 0x00000001 /* R---V */ + #define NV_PGRAPH_STATUS_PORT_FIFO 24:24 /* R-IVF */ + #define NV_PGRAPH_STATUS_PORT_FIFO_IDLE 0x00000000 /* R-I-V */ + #define NV_PGRAPH_STATUS_PORT_FIFO_BUSY 0x00000001 /* R---V */ + + #define NV_PGRAPH_TRAPPED_ADDR 0x004006A8 /* R--4R */ + #define NV_PGRAPH_TRAPPED_ADDR_VALUE 20:2 /* R-XUF */ + #define NV_PGRAPH_TRAPPED_DATA 0x004006AC /* R--4R */ + #define NV_PGRAPH_TRAPPED_DATA_VALUE 31:0 /* R-XVF */ + + #define NV_PGRAPH_CANVAS_MISC 0x00400634 /* RW-4R */ + #define NV_PGRAPH_CANVAS_MISC_DAC_BYPASS 0:0 /* RWXVF */ + #define NV_PGRAPH_CANVAS_MISC_DAC_BYPASS_DISABLED 0x00000000 /* RW--V */ + #define NV_PGRAPH_CANVAS_MISC_DAC_BYPASS_ENABLED 0x00000001 /* RW--V */ + #define NV_PGRAPH_CANVAS_MISC_RETAINED 4:4 /* RWXVF */ + #define NV_PGRAPH_CANVAS_MISC_RETAINED_DISABLED 0x00000000 /* RW--V */ + #define NV_PGRAPH_CANVAS_MISC_RETAINED_ENABLED 0x00000001 /* RW--V */ + #define NV_PGRAPH_CANVAS_MISC_DAC_DECODE 12:12 /* RWXVF */ + #define NV_PGRAPH_CANVAS_MISC_DAC_DECODE_SINGLE 0x00000000 /* RW--V */ + #define NV_PGRAPH_CANVAS_MISC_DAC_DECODE_TRIPLE 0x00000001 /* RW--V */ + #define NV_PGRAPH_CANVAS_MISC_DITHER 16:16 /* RWXVF */ + #define NV_PGRAPH_CANVAS_MISC_DITHER_DISABLED 0x00000000 /* RW--V */ + #define NV_PGRAPH_CANVAS_MISC_DITHER_ENABLED 0x00000001 /* RW--V */ + #define NV_PGRAPH_CANVAS_MISC_REPLICATE 20:20 /* RWXVF */ + #define NV_PGRAPH_CANVAS_MISC_REPLICATE_DISABLED 0x00000000 /* RW--V */ + #define NV_PGRAPH_CANVAS_MISC_REPLICATE_ENABLED 0x00000001 /* RW--V */ + #define NV_PGRAPH_CANVAS_MISC_SOFTWARE 24:24 /* RWXVF */ + #define NV_PGRAPH_CANVAS_MISC_SOFTWARE_DISABLED 0x00000000 /* RW--V */ + #define NV_PGRAPH_CANVAS_MISC_SOFTWARE_ENABLED 0x00000001 /* RW--V */ + + #define NV_PGRAPH_CLIP_MISC 0x004006A0 /* RW-4R */ + #define NV_PGRAPH_CLIP_MISC_REGIONS 1:0 /* RWIUF */ + #define NV_PGRAPH_CLIP_MISC_REGIONS_DISABLED 0x00000000 /* RWI-V */ + #define NV_PGRAPH_CLIP_MISC_REGIONS_1 0x00000001 /* RW--V */ + #define NV_PGRAPH_CLIP_MISC_REGIONS_2 0x00000002 /* RW--V */ + #define NV_PGRAPH_CLIP_MISC_RENDER 4:4 /* RWIVF */ + #define NV_PGRAPH_CLIP_MISC_RENDER_INCLUDED 0x00000000 /* RWI-V */ + #define NV_PGRAPH_CLIP_MISC_RENDER_OCCLUDED 0x00000001 /* RW--V */ + #define NV_PGRAPH_CLIP_MISC_COMPLEX 8:8 /* RWIVF */ + #define NV_PGRAPH_CLIP_MISC_COMPLEX_DISABLED 0x00000000 /* RWI-V */ + #define NV_PGRAPH_CLIP_MISC_COMPLEX_ENABLED 0x00000001 /* RW--V */ + + #define NV_PGRAPH_CANVAS_MIN 0x00400688 /* RW-4R */ + #define NV_PGRAPH_CANVAS_MIN_X 15:0 /* RWXSF */ + #define NV_PGRAPH_CANVAS_MIN_Y 31:16 /* RWXSF */ + #define NV_PGRAPH_CANVAS_MAX 0x0040068C /* RW-4R */ + #define NV_PGRAPH_CANVAS_MAX_X 11:0 /* RWXUF */ + #define NV_PGRAPH_CANVAS_MAX_Y 27:16 /* RWXUF */ + + #define NV_PGRAPH_CLIP0_MIN 0x00400690 /* RW-4R */ + #define NV_PGRAPH_CLIP0_MIN_X 11:0 /* RWXSF */ + #define NV_PGRAPH_CLIP0_MIN_Y 27:16 /* RWXSF */ + #define NV_PGRAPH_CLIP1_MIN 0x00400698 /* RW-4R */ + #define NV_PGRAPH_CLIP1_MIN_X 11:0 /* RWXSF */ + #define NV_PGRAPH_CLIP1_MIN_Y 27:16 /* RWXSF */ + #define NV_PGRAPH_CLIP0_MAX 0x00400694 /* RW-4R */ + #define NV_PGRAPH_CLIP0_MAX_X 11:0 /* RWXSF */ + #define NV_PGRAPH_CLIP0_MAX_Y 27:16 /* RWXSF */ + #define NV_PGRAPH_CLIP1_MAX 0x0040069C /* RW-4R */ + #define NV_PGRAPH_CLIP1_MAX_X 11:0 /* RWXSF */ + #define NV_PGRAPH_CLIP1_MAX_Y 27:16 /* RWXSF */ + + #define NV_PGRAPH_DMA 0x00400680 /* RW-4R */ + #define NV_PGRAPH_NOTIFY 0x00400684 /* RW-4R */ + + #define NV_PGRAPH_PATT_COLOR0_0 0x00400600 /* RW-4R */ + #define NV_PGRAPH_PATT_COLOR0_1 0x00400604 /* RW-4R */ + #define NV_PGRAPH_PATT_COLOR1_0 0x00400608 /* RW-4R */ + #define NV_PGRAPH_PATT_COLOR1_1 0x0040060C /* RW-4R */ + #define NV_PGRAPH_PATTERN(i) (0x00400610+(i)*4) /* RW-4A */ + #define NV_PGRAPH_PATTERN__SIZE_1 2 /* */ + #define NV_PGRAPH_PATTERN_SHAPE 0x00400618 /* RW-4R */ + + #define NV_PGRAPH_MONO_COLOR0 0x0040061C /* RW-4R */ + #define NV_PGRAPH_MONO_COLOR1 0x00400620 /* RW-4R */ + + #define NV_PGRAPH_ROP3 0x00400624 /* RW-4R */ + #define NV_PGRAPH_PLANE_MASK 0x00400628 /* RW-4R */ + + #define NV_PGRAPH_CHROMA 0x0040062C /* RW-4R */ + + #define NV_PGRAPH_BETA 0x00400630 /* RW-4R */ + + #define NV_PGRAPH_ABS_X_RAM(i) (0x00400400+(i)*4) /* RW-4A */ + #define NV_PGRAPH_ABS_X_RAM__SIZE_1 18 /* */ + + #define NV_PGRAPH_ABS_Y_RAM(i) (0x00400480+(i)*4) /* RW-4A */ + #define NV_PGRAPH_ABS_Y_RAM__SIZE_1 18 /* */ + #define NV_PGRAPH_REL_Y_RAM(i) (0x00400580+(i)*4) /* RW-4A */ + #define NV_PGRAPH_REL_Y_RAM__SIZE_1 18 /* */ + + #define NV_PGRAPH_XY_LOGIC_MISC0 0x00400640 /* RW-4R */ + #define NV_PGRAPH_XY_LOGIC_MISC1 0x00400644 /* RW-4R */ + + #define NV_PGRAPH_X_MISC 0x00400648 /* RW-4R */ + #define NV_PGRAPH_Y_MISC 0x0040064c /* RW-4R */ + + #define NV_PGRAPH_ABS_UCLIP_XMIN 0x00400460 /* RW-4R */ + #define NV_PGRAPH_ABS_UCLIP_XMAX 0x00400464 /* RW-4R */ + #define NV_PGRAPH_ABS_UCLIP_YMIN 0x00400468 /* RW-4R */ + #define NV_PGRAPH_ABS_UCLIP_YMAX 0x0040046C /* RW-4R */ + + + #define NV_PGRAPH_ABS_ICLIP_XMAX 0x00400450 /* RW-4R */ + #define NV_PGRAPH_ABS_ICLIP_YMAX 0x00400454 /* RW-4R */ + + #define NV_PGRAPH_SOURCE_COLOR 0x00400654 /* RW-4R */ + #define NV_PGRAPH_SUBDIVIDE 0x00400658 /* RW-4R */ + #define NV_PGRAPH_EXCEPTIONS 0x00400650 /* RW-4R */ + #define NV_PGRAPH_EDGEFILL 0x0040065c /* RW-4R */ + + #define NV_PGRAPH_BETA_RAM(i) (0x00400700+(i)*4) /* RW-4A */ + #define NV_PGRAPH_BETA_RAM__SIZE_1 14 /* */ + + #define NV_PGRAPH_BETA_RAM_BPORT(i) (0x00400d00+(i)*4) /* R--4A */ + #define NV_PGRAPH_BETA_RAM_BPORT__SIZE_1 14 /* */ + + #define NV_PGRAPH_BIT33 0x00400660 /* RW-4R */ + + /***************************************** + * Defintions for Master control device + *****************************************/ + + #define NV_PMC 0x00000FFF:0x00000000 /* RW--D */ + + #define NV_PMC_INTR_0 0x00000100 /* RW-4R */ + #define NV_PMC_INTR_0_PAUDIO 0:0 /* R--VF */ + #define NV_PMC_INTR_0_PAUDIO_NOT_PENDING 0x00000000 /* R---V */ + #define NV_PMC_INTR_0_PAUDIO_PENDING 0x00000001 /* R---V */ + #define NV_PMC_INTR_0_PDMA 4:4 /* R--VF */ + #define NV_PMC_INTR_0_PDMA_NOT_PENDING 0x00000000 /* R---V */ + #define NV_PMC_INTR_0_PDMA_PENDING 0x00000001 /* R---V */ + #define NV_PMC_INTR_0_PFIFO 8:8 /* R--VF */ + #define NV_PMC_INTR_0_PFIFO_NOT_PENDING 0x00000000 /* R---V */ + #define NV_PMC_INTR_0_PFIFO_PENDING 0x00000001 /* R---V */ + #define NV_PMC_INTR_0_PGRAPH 12:12 /* R--VF */ + #define NV_PMC_INTR_0_PGRAPH_NOT_PENDING 0x00000000 /* R---V */ + #define NV_PMC_INTR_0_PGRAPH_PENDING 0x00000001 /* R---V */ + #define NV_PMC_INTR_0_PRM 16:16 /* R--VF */ + #define NV_PMC_INTR_0_PRM_NOT_PENDING 0x00000000 /* R---V */ + #define NV_PMC_INTR_0_PRM_PENDING 0x00000001 /* R---V */ + #define NV_PMC_INTR_0_PTIMER 20:20 /* R--VF */ + #define NV_PMC_INTR_0_PTIMER_NOT_PENDING 0x00000000 /* R---V */ + #define NV_PMC_INTR_0_PTIMER_PENDING 0x00000001 /* R---V */ + #define NV_PMC_INTR_0_PFB 24:24 /* R--VF */ + #define NV_PMC_INTR_0_PFB_NOT_PENDING 0x00000000 /* R---V */ + #define NV_PMC_INTR_0_PFB_PENDING 0x00000001 /* R---V */ + #define NV_PMC_INTR_0_SOFTWARE 28:28 /* RWIVF */ + #define NV_PMC_INTR_0_SOFTWARE_NOT_PENDING 0x00000000 /* RWI-V */ + #define NV_PMC_INTR_0_SOFTWARE_PENDING 0x00000001 /* RW--V */ + + #define NV_PMC_ENABLE 0x00000200 /* RW-4R */ + #define NV_PMC_ENABLE_PAUDIO 0:0 /* RWIVF */ + #define NV_PMC_ENABLE_PAUDIO_DISABLED 0x00000000 /* RWI-V */ + #define NV_PMC_ENABLE_PAUDIO_ENABLED 0x00000001 /* RW--V */ + #define NV_PMC_ENABLE_PDMA 4:4 /* RWIVF */ + #define NV_PMC_ENABLE_PDMA_DISABLED 0x00000000 /* RWI-V */ + #define NV_PMC_ENABLE_PDMA_ENABLED 0x00000001 /* RW--V */ + #define NV_PMC_ENABLE_PFIFO 8:8 /* RWIVF */ + #define NV_PMC_ENABLE_PFIFO_DISABLED 0x00000000 /* RWI-V */ + #define NV_PMC_ENABLE_PFIFO_ENABLED 0x00000001 /* RW--V */ + #define NV_PMC_ENABLE_PGRAPH 12:12 /* RWIVF */ + #define NV_PMC_ENABLE_PGRAPH_DISABLED 0x00000000 /* RWI-V */ + #define NV_PMC_ENABLE_PGRAPH_ENABLED 0x00000001 /* RW--V */ + #define NV_PMC_ENABLE_PRM 16:16 /* RWIVF */ + #define NV_PMC_ENABLE_PRM_DISABLED 0x00000000 /* RWI-V */ + #define NV_PMC_ENABLE_PRM_ENABLED 0x00000001 /* RW--V */ + #define NV_PMC_ENABLE_PFB 24:24 /* RWIVF */ + #define NV_PMC_ENABLE_PFB_DISABLED 0x00000000 /* RWI-V */ + #define NV_PMC_ENABLE_PFB_ENABLED 0x00000001 /* RW--V */ + + /***************************************** + * Definitions for priviliged RAM device + *****************************************/ + + #define NV_PRAM 0x00602FFF:0x00602000 /* RW--D */ + #define NV_PRAM_CONFIG_0 0x00602200 /* RW-4R */ + #define NV_PRAM_CONFIG_0_SIZE 1:0 /* RWIVF */ + #define NV_PRAM_CONFIG_0_SIZE_12KB 0x00000000 /* RWI-V */ + #define NV_PRAM_CONFIG_0_SIZE_20KB 0x00000001 /* RW--V */ + #define NV_PRAM_CONFIG_0_SIZE_36KB 0x00000002 /* RW--V */ + #define NV_PRAM_CONFIG_0_SIZE_68KB 0x00000003 /* RW--V */ + #define NV_PRAM_HASH_VIRTUAL(i) (0x00602400+(i)*4) /* -W-4A */ + #define NV_PRAM_HASH_VIRTUAL__SIZE_1 128 /* */ + #define NV_PRAM_HASH_VIRTUAL_HANDLE 31:0 /* -W-VF */ + #define NV_PRAM_HASH_PHYSICAL 0x00602600 /* R--4R */ + #define NV_PRAM_HASH_PHYSICAL_INSTANCE 15:0 /* R-IUF */ + #define NV_PRAM_HASH_PHYSICAL_INSTANCE_0 0x00000000 /* R-I-V */ + #define NV_PRAM_HASH_PHYSICAL_DEVICE 22:16 /* R-IUF */ + #define NV_PRAM_HASH_PHYSICAL_DEVICE_NOT_FOUND 0x00000000 /* R-I-V */ + #define NV_PRAM_HASH_PHYSICAL_FREE_LIE 24:24 /* R-IVF */ + #define NV_PRAM_HASH_PHYSICAL_FREE_LIE_DISABLED 0x00000000 /* R-I-V */ + #define NV_PRAM_HASH_PHYSICAL_FREE_LIE_ENABLED 0x00000001 /* R---V */ + + #define NV_PRAMFC 0x0064BFFF:0x00648000 /* RW--D */ + + + #define NV_PRAMHT 0x00647FFF:0x00640000 /* RW--D */ + + + /***************************************** + * Defintions for real mode device + *****************************************/ + + #define NV_PRM 0x006C7FFF:0x006C0000 /* RW--D */ + + #define NV_PRM_CONFIG_0 0x006C0200 /* RW-4R */ + #define NV_PRM_CONFIG_0_TEXT 0:0 /* RWIVF */ + #define NV_PRM_CONFIG_0_TEXT_DISABLED 0x00000000 /* RWI-V */ + #define NV_PRM_CONFIG_0_TEXT_ENABLED 0x00000001 /* RW--V */ + #define NV_PRM_CONFIG_0_DAC_WIDTH 4:4 /* RWIVF */ + #define NV_PRM_CONFIG_0_DAC_WIDTH_BITS_6 0x00000000 /* RWI-V */ + #define NV_PRM_CONFIG_0_DAC_WIDTH_BITS_8 0x00000001 /* RW--V */ + + #define NV_PRM_TRACE 0x006C1F00 /* RW-4R */ + + + #endif *** /dev/null Tue Jun 30 11:50:06 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/nv1setup.c Fri Mar 6 16:51:48 1998 *************** *** 0 **** --- 1,600 ---- + /* $TOG: nv1setup.c /main/1 1998/03/06 16:53:25 kaleb $ */ + + + + /* + * Copyright 1996-1997 David J. McKay + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * DAVID J. MCKAY BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/nv1setup.c,v 1.1.2.3 1998/01/24 11:55:08 dawes Exp $ */ + + + #include <stdlib.h> + + + #include "nvuser.h" + #include "nv1ref.h" + #include "nvreg.h" + + typedef struct { + UINT32 id; /* 32 bit unique identifer for this object */ + UINT32 channel; /* What channel this object belongs to */ + UINT32 context; /* Holds configuration of pipeline. Written to CTX SWITCH */ + }NVObject; + + + + static int graphicsEngineOk; + + #define WaitForIdle() while(PGRAPH_Read(STATUS)) + + static void EnableOptimisations(void) + { + /* Now switch on all the optimisations that there are */ + PGRAPH_Write(DEBUG_0,PGRAPH_Def(DEBUG_0_EDGE_FILLING,ENABLED) | + PGRAPH_Def(DEBUG_0_WRITE_ONLY_ROPS,ENABLED) | + PGRAPH_Def(DEBUG_0_NONBLOCK_BROAD,ENABLED) | + PGRAPH_Def(DEBUG_0_BLOCK_BROAD,ENABLED) | + PGRAPH_Def(DEBUG_0_BLOCK,ENABLED) | + PGRAPH_Def(DEBUG_0_BULK_READS,ENABLED)); + + PGRAPH_Write(DEBUG_1,PGRAPH_Def(DEBUG_1_HIRES_TM,DISABLED) | + PGRAPH_Def(DEBUG_1_FAST_BUS,DISABLED) | + PGRAPH_Def(DEBUG_1_TM_QUAD_HANDOFF,ENABLED) | + PGRAPH_Def(DEBUG_1_FAST_RMW_BLITS,ENABLED) | + PGRAPH_Def(DEBUG_1_PATT_BLOCK,ENABLED) | + PGRAPH_Def(DEBUG_1_TRI_OPTS,DISABLED) | + PGRAPH_Def(DEBUG_1_BI_RECTS,DISABLED) | + PGRAPH_Def(DEBUG_1_DMA_ACTIVITY,IGNORE) | + PGRAPH_Def(DEBUG_1_VOLATILE_RESET,NOT_LAST)); + + PGRAPH_Write(DEBUG_2,PGRAPH_Def(DEBUG_2_VOLATILE_RESET,ENABLED) | + PGRAPH_Def(DEBUG_2_TM_FASTINPUT,ENABLED) | + PGRAPH_Def(DEBUG_2_BUSY_PATIENCE,ENABLED) | + PGRAPH_Def(DEBUG_2_TRAPEZOID_TEXEL,ENABLED) | + PGRAPH_Def(DEBUG_2_MONO_ABORT,DISABLED) | + PGRAPH_Def(DEBUG_2_BETA_ABORT,ENABLED) | + PGRAPH_Def(DEBUG_2_ALPHA_ABORT,ENABLED) | + PGRAPH_Def(DEBUG_2_AVOID_RMW_BLEND,DISABLED)); + + /* + * REV c parts have another debug register here, but ignore for the + * moment + */ + } + + static void InitDMAInstance(void) + { + PDMA_Write(GR_CHANNEL,PDMA_Def(GR_CHANNEL_ACCESS,DISABLED)); + PDMA_Write(GR_INSTANCE,0); + PGRAPH_Write(DMA,0); + PGRAPH_Write(NOTIFY,0); + PDMA_Write(GR_CHANNEL,PDMA_Def(GR_CHANNEL_ACCESS,ENABLED)); + } + + + + static void DisableFifo(void) + { + /* Disable CACHE1 first */ + PFIFO_Write(CACHES,PFIFO_Def(CACHES_REASSIGN,DISABLED)); + PFIFO_Write(CACHE1_PUSH0,PFIFO_Def(CACHE1_PUSH0_ACCESS,DISABLED)); + PFIFO_Write(CACHE1_PULL0,PFIFO_Def(CACHE1_PULL0_ACCESS,DISABLED)); + PFIFO_Write(CACHE0_PUSH0,PFIFO_Def(CACHE1_PUSH0_ACCESS,DISABLED)); + PFIFO_Write(CACHE0_PULL0,PFIFO_Def(CACHE1_PULL0_ACCESS,DISABLED)); + + } + + static void EnableFifo(void) + { + /* Enable CACHE1 first */ + PFIFO_Write(CACHE1_PUSH0,PFIFO_Def(CACHE1_PUSH0_ACCESS,ENABLED)); + PFIFO_Write(CACHE1_PULL0,PFIFO_Def(CACHE1_PULL0_ACCESS,ENABLED)); + PFIFO_Write(CACHES,PFIFO_Def(CACHES_REASSIGN,ENABLED)); + } + + + #define PRIV_RAM_SIZE 0 + #define NUM_FIFO_CONTEXT ((PRIV_RAM_SIZE)? 128 : 64) + + /* Clear out channel 0 fifo context */ + static void ClearOutFifoContext(void) + { + int i; + + /* Set up size of PRAM */ + PRAM_Write(CONFIG_0,PRAM_Val(CONFIG_0_SIZE,PRIV_RAM_SIZE)); + + for(i=0;i<NUM_FIFO_CONTEXT;i++) { + nvPRAMFCPort[i]=0; + } + } + + int NvKbRamUsedByHW(void) + { + /* Audio scratch and password context are fixed at 4K, + * but hash table, runout and fifo vary with PRIV_RAM_SIZE + */ + return ( (8<<PRIV_RAM_SIZE)+4 ); + } + + + + static void ClearOutContext(void) + { + int i; + + /* Init context register */ + PGRAPH_Write(CTX_SWITCH,0); + + ClearOutFifoContext(); + + /* Set PUT and GET pointers to address 0*/ + PFIFO_Write(CACHE1_PUT,0);PFIFO_Write(CACHE1_GET,0); + + /* Make sure there is no runout data */ + PFIFO_Write(RUNOUT_PUT,0); + PFIFO_Write(RUNOUT_GET,0); + + /* Nobody is allowed to lie about how much space in the fifo */ + PFIFO_Write(CONFIG_0,PFIFO_Def(CONFIG_0_FREE_LIE,DISABLED)); + + /* Clear out CACHED CONTEXT registers */ + for(i=0;i<NV_PFIFO_CACHE1_CTX__SIZE_1;i++) { + PFIFO_Write(CACHE1_CTX(i),0); + } + } + + #define HASH_TABLE_COLS (2<<PRIV_RAM_SIZE) + #define HASH_TABLE_ROWS 256 + + typedef struct { + UINT32 id; + UINT32 context; + }HashTableEntry; + + static HashTableEntry localHash[HASH_TABLE_ROWS][HASH_TABLE_COLS]; + static HashTableEntry *realHash=NULL; + + + #define HASH_FIFO(h,c) ((((h)^((h)>>8)^((h)>>16)^((h)>>24))&0xFF)^((c)&0x7F)) + + #define HASH_ENTRY(index,depth) (((index)*HASH_TABLE_COLS)+(depth)) + + static void ClearOutHashTables(void) + { + int i,j; + + if(!realHash) realHash=(HashTableEntry *) nvPRAMHTPort; + + /* Clear out host copy of hash table */ + for(i=0;i<HASH_TABLE_ROWS;i++) { + for(j=0;j<HASH_TABLE_COLS;j++) { + localHash[i][j].id=0; + localHash[i][j].context=0; + (realHash+HASH_ENTRY(i,j))->id=0; + (realHash+HASH_ENTRY(i,j))->context=0; + } + } + /* Clear out hash virtual registers */ + for(i=0;i<NV_PRAM_HASH_VIRTUAL__SIZE_1;i++) { + PRAM_Write(HASH_VIRTUAL(i),0); + } + } + + /* Defaults the context for the channel to be something sensible. + * This code is the basis of what needs to be context switched if this + * driver ever expands to cope with multiple channels at the same time. + */ + + static void LoadChannelContext(void) + { + int i; + UINT32 read; + + + /* Force Cache 0 and Cache 1 to be set for channel 0 */ + + PFIFO_Write(CACHE0_PUSH1,0); + PFIFO_Write(CACHE1_PUSH1,0); + + PFIFO_Write(CACHE1_PULL1, 0); + read=PFIFO_Read(CACHE1_PULL1); + PFIFO_Write(CACHE1_PULL1,read|PFIFO_Def(CACHE1_PULL1_CTX,DIRTY)); + read=PFIFO_Read(CACHE1_PULL1); + PFIFO_Write(CACHE1_PULL1,read|PFIFO_Def(CACHE1_PULL1_OBJECT,CHANGED)); + + /* Set context control. Don't enable channel yet */ + PGRAPH_Write(CTX_CONTROL,PGRAPH_Def(CTX_CONTROL_MINIMUM_TIME,2MS) | + PGRAPH_Def(CTX_CONTROL_TIME,EXPIRED) | + PGRAPH_Def(CTX_CONTROL_CHID,INVALID) | + PGRAPH_Def(CTX_CONTROL_SWITCHING,IDLE) | + PGRAPH_Def(CTX_CONTROL_DEVICE,ENABLED)); + + PGRAPH_Write(CANVAS_MIN,0); + PGRAPH_Write(CANVAS_MAX,PACK_UINT16(MAX_UINT16,MAX_UINT16)); + + PGRAPH_Write(CLIP_MISC,0); + PGRAPH_Write(CLIP0_MIN,0); + PGRAPH_Write(CLIP1_MIN,0); + PGRAPH_Write(CLIP0_MAX,0); + PGRAPH_Write(CLIP1_MAX,0); + + PGRAPH_Write(CANVAS_MISC,PGRAPH_Def(CANVAS_MISC_DAC_BYPASS,DISABLED)| + PGRAPH_Def(CANVAS_MISC_DITHER,ENABLED)| + PGRAPH_Def(CANVAS_MISC_REPLICATE,ENABLED)); + + PGRAPH_Write(SOURCE_COLOR,0); + PGRAPH_Write(MONO_COLOR0,0); + PGRAPH_Write(MONO_COLOR1,0); + + PGRAPH_Write(ABS_UCLIP_XMIN,0); + PGRAPH_Write(ABS_UCLIP_YMIN,0); + PGRAPH_Write(ABS_UCLIP_XMAX,0); + PGRAPH_Write(ABS_UCLIP_YMAX,0); + + /* Beta and Plane Mask */ + PGRAPH_Write(PLANE_MASK,0xffffffff); + PGRAPH_Write(BETA,0); + for(i=0;i<NV_PGRAPH_BETA_RAM__SIZE_1;i++) { + PGRAPH_Write(BETA_RAM(i),0); + } + + for(i=0;i<NV_PGRAPH_ABS_X_RAM__SIZE_1;i++) { + PGRAPH_Write(ABS_X_RAM(i),0); + + } + for(i=0;i<NV_PGRAPH_ABS_Y_RAM__SIZE_1;i++) { + PGRAPH_Write(ABS_Y_RAM(i),0); + } + + PGRAPH_Write(ABS_ICLIP_XMAX,0);PGRAPH_Write(ABS_ICLIP_YMAX,0); + + PGRAPH_Write(XY_LOGIC_MISC0,0);PGRAPH_Write(XY_LOGIC_MISC1,0); + PGRAPH_Write(X_MISC,0);PGRAPH_Write(Y_MISC,0); + + PGRAPH_Write(SUBDIVIDE,0);PGRAPH_Write(EDGEFILL,0); + + /* Pattern registers . Initialise to something sensible */ + PGRAPH_Write(PATT_COLOR0_0,0);PGRAPH_Write(PATT_COLOR0_1,0xff); + PGRAPH_Write(PATT_COLOR1_0,1);PGRAPH_Write(PATT_COLOR1_1,0xff); + PGRAPH_Write(PATTERN(0),0xffffffff);PGRAPH_Write(PATTERN(1),0xffffffff); + PGRAPH_Write(PATTERN_SHAPE,0); + + /* Set the ROP to be COPY (Uses Microshaft raster op codes) */ + PGRAPH_Write(ROP3,0xcc); + + PGRAPH_Write(EXCEPTIONS,0); + PGRAPH_Write(BIT33,0); + + } + + static void EnableFlowThru(void) + { + /* Disable the fifo and the DMA engine, but keep flowthu enabled. + * This state is needed to actually access many of the registers + * in the graphics engine that we are going to set up + */ + PGRAPH_Write(MISC,PGRAPH_Def(MISC_FLOWTHRU_WRITE,ENABLED) | + PGRAPH_Def(MISC_FLOWTHRU,ENABLED) | + PGRAPH_Def(MISC_FIFO_WRITE,ENABLED) | + PGRAPH_Def(MISC_FIFO,DISABLED) | + PGRAPH_Def(MISC_DMA_WRITE,ENABLED) | + PGRAPH_Def(MISC_DMA,DISABLED) | + PGRAPH_Def(MISC_CLASS_WRITE,ENABLED) | + PGRAPH_Val(MISC_CLASS, 0)); + + } + + + /* Will need to define here what all this lot actually does */ + + #define COLOR_CONTEXT_R5G5B5 0x0 + #define COLOR_CONTEXT_R8G8B8 0x1 + #define COLOR_CONTEXT_R10G10B10 0x2 + #define COLOR_CONTEXT_Y8 0x3 + #define COLOR_CONTEXT_Y16 0x4 + + + #define GENERATE_CONTEXT(device,cfg,chroma,plane,clip,color,alpha) \ + DEVICE_BASE(device)|\ + SetBF(4:0,cfg)|SetBF(5:5,chroma)|SetBF(6:6,plane)|\ + SetBF(7:7,clip)|SetBF(8:8,0)|SetBF(12:9,color)|\ + SetBF(13:13,alpha)|SetBF(14:14,0)|SetBF(15:15,0) + + /* This value does SRC & PATTERN */ + /* The pattern is disabled/enabled by the ROP code we set up */ + #define PATCH_CONTEXT 0x10 + + /* All contexts will be generated at run time as we need to set the color + * format dynamically + */ + static NVObject ropObject; + static NVObject clipObject; + static NVObject patternObject; + static NVObject rectObject; + static NVObject blitObject; + static NVObject colourExpandObject; + static NVObject lineObject; + static NVObject linObject; + static NVObject chromaObject; + + #define Info ErrorF + + static void InitObject(NVObject *object) + { + UINT32 hash; + int i; + + /* Will put an entry into the hash table */ + hash=HASH_FIFO(object->id,object->channel); + + for(i=0;i<HASH_TABLE_COLS;i++) { + if(localHash[hash][i].id==0) break; /* Found an empty slot!!! */ + /* is object already in cache? */ + if(localHash[hash][i].context==object->id) return; + } + if(i==HASH_TABLE_COLS) { + /* There is no room at the inn. Since we can't cope with reloading + * context we had better abort here!! + */ + Info("**** NO ROOM FOR OBJECT %08lx IN HASH TABLE ****\n",object->id); + graphicsEngineOk=0; /* Set flag so that we won't use accel */ + return; + } + /* Ok, bung entry in at appropriate place */ + localHash[hash][i].id=object->id; + localHash[hash][i].context=object->context; + (realHash+HASH_ENTRY(hash,i))->id=object->id; + (realHash+HASH_ENTRY(hash,i))->context=object->context; + } + + static void SetUpObjects(int bpp) + { + int colorContext=(bpp==8) ? COLOR_CONTEXT_R8G8B8 : COLOR_CONTEXT_R5G5B5; + + ropObject.id=ROP_OBJECT_ID; + ropObject.channel=0; + ropObject.context=GENERATE_CONTEXT(UROP,0,0,0,0,0,0); + InitObject(&ropObject); + + clipObject.id=CLIP_OBJECT_ID; + clipObject.channel=0; + clipObject.context=GENERATE_CONTEXT(UCLIP,0,0,0,0,0,0); + InitObject(&clipObject); + + patternObject.id=PATTERN_OBJECT_ID; + patternObject.channel=0; + patternObject.context= + GENERATE_CONTEXT(UPATT,0,0,0,0,colorContext,0); + InitObject(&patternObject); + + rectObject.id=RECT_OBJECT_ID; + rectObject.channel=0; + rectObject.context= + GENERATE_CONTEXT(URECT,PATCH_CONTEXT,0,0,1,colorContext,0); + InitObject(&rectObject); + + + blitObject.id=BLIT_OBJECT_ID; + blitObject.channel=0; + blitObject.context= + GENERATE_CONTEXT(UBLIT,PATCH_CONTEXT,0,0,1,colorContext,0); + InitObject(&blitObject); + + colourExpandObject.id=COLOUR_EXPAND_OBJECT_ID; + colourExpandObject.channel=0; + colourExpandObject.context= + GENERATE_CONTEXT(UBITMAP,PATCH_CONTEXT,0,0,1,colorContext,1); + InitObject(&colourExpandObject); + + lineObject.id=LINE_OBJECT_ID; + lineObject.channel=0; + lineObject.context= + GENERATE_CONTEXT(ULINE,PATCH_CONTEXT,0,0,1,colorContext,0); + InitObject(&lineObject); + + linObject.id=LIN_OBJECT_ID; + linObject.channel=0; + linObject.context= + GENERATE_CONTEXT(ULIN,PATCH_CONTEXT,0,0,1,colorContext,0); + InitObject(&linObject); + } + + + + static void ClearAndEnableInterrupts(void) + { + PGRAPH_Write(INTR_0,PGRAPH_Def(INTR_0_RESERVED,RESET)| + PGRAPH_Def(INTR_0_CONTEXT_SWITCH,RESET)| + PGRAPH_Def(INTR_0_VBLANK,RESET)| + PGRAPH_Def(INTR_0_RANGE,RESET)| + PGRAPH_Def(INTR_0_METHOD_COUNT,RESET)| + PGRAPH_Def(INTR_0_SOFTWARE,RESET)| + PGRAPH_Def(INTR_0_COMPLEX_CLIP,RESET)| + PGRAPH_Def(INTR_0_NOTIFY,RESET)); + + + /* Enable all interrupts except VBLANK */ + PGRAPH_Write(INTR_EN_0,PGRAPH_Def(INTR_EN_0_RESERVED,ENABLED)| + PGRAPH_Def(INTR_EN_0_CONTEXT_SWITCH,ENABLED)| + PGRAPH_Def(INTR_EN_0_VBLANK,DISABLED)| + PGRAPH_Def(INTR_EN_0_RANGE,ENABLED)| + PGRAPH_Def(INTR_EN_0_METHOD_COUNT,ENABLED)| + PGRAPH_Def(INTR_EN_0_SOFTWARE,ENABLED)| + PGRAPH_Def(INTR_EN_0_COMPLEX_CLIP,ENABLED)| + PGRAPH_Def(INTR_EN_0_NOTIFY,ENABLED)); + + PGRAPH_Write(INTR_1,PGRAPH_Def(INTR_1_METHOD,RESET)| + PGRAPH_Def(INTR_1_DATA,RESET)| + PGRAPH_Def(INTR_1_NOTIFY_INST,RESET)| + PGRAPH_Def(INTR_1_DOUBLE_NOTIFY,RESET)| + PGRAPH_Def(INTR_1_CTXSW_NOTIFY,RESET)); + + /* Don't care about any of this lot */ + PGRAPH_Write(INTR_EN_1,0); + + /* Reset the FIFO interrupt state */ + PFIFO_Write(INTR_0, PFIFO_Def(INTR_0_CACHE_ERROR,RESET)| + PFIFO_Def(INTR_0_RUNOUT,RESET)| + PFIFO_Def(INTR_0_RUNOUT_OVERFLOW,RESET)); + + PFIFO_Write(INTR_EN_0, PFIFO_Def(INTR_EN_0_CACHE_ERROR,ENABLED)| + PFIFO_Def(INTR_EN_0_RUNOUT,ENABLED)| + PFIFO_Def(INTR_EN_0_RUNOUT_OVERFLOW,ENABLED)); + + /* Switch on all the user devices in the master control */ + PMC_Write(ENABLE,PMC_Def(ENABLE_PAUDIO,ENABLED) | + PMC_Def(ENABLE_PDMA,ENABLED) | + PMC_Def(ENABLE_PFIFO,ENABLED) | + PMC_Def(ENABLE_PGRAPH,ENABLED) | + PMC_Def(ENABLE_PRM,ENABLED) | + PMC_Def(ENABLE_PFB,ENABLED)); + } + + static void ResetEngine(void) + { + /* Reset the graphics engine state machine */ + PGRAPH_Write(DEBUG_1,PGRAPH_Def(DEBUG_1_VOLATILE_RESET,LAST)); + PGRAPH_Write(DEBUG_0,PGRAPH_Def(DEBUG_0_STATE,RESET)); + } + + static void EnableChannel(void) + { + + /* Set context control */ + PGRAPH_Write(CTX_CONTROL,PGRAPH_Def(CTX_CONTROL_MINIMUM_TIME,2MS) | + PGRAPH_Def(CTX_CONTROL_TIME,EXPIRED) | + PGRAPH_Def(CTX_CONTROL_CHID,VALID) | + PGRAPH_Def(CTX_CONTROL_SWITCHING,IDLE) | + PGRAPH_Def(CTX_CONTROL_DEVICE,ENABLED)); + + + PGRAPH_Write(MISC,PGRAPH_Def(MISC_FLOWTHRU_WRITE,ENABLED) | + PGRAPH_Def(MISC_FLOWTHRU,ENABLED) | + PGRAPH_Def(MISC_FIFO_WRITE,ENABLED) | + PGRAPH_Def(MISC_FIFO,ENABLED) | + PGRAPH_Def(MISC_DMA_WRITE,ENABLED) | + PGRAPH_Def(MISC_DMA,ENABLED) | + PGRAPH_Def(MISC_CLASS_WRITE,IGNORED) | + PGRAPH_Val(MISC_CLASS, 0)); + } + + int NV1SetupGraphicsEngine(int width,int height,int bpp) + { + graphicsEngineOk=1; + + WaitForIdle(); + /* Possibly enable the hardware engines here. Should already be on though */ + + DisableFifo(); + + EnableFlowThru(); + + ResetEngine(); + + EnableOptimisations(); + + InitDMAInstance(); + + ClearAndEnableInterrupts(); + + ClearOutContext(); + + ClearOutHashTables(); + + LoadChannelContext(); + + SetUpObjects(bpp); + + EnableChannel(); + + EnableFifo(); + + return graphicsEngineOk; + + } + + static int channelOpen=0; + + NvChannel *NvOpenChannel(void) + { + if(channelOpen) return NULL; + + channelOpen=1; + return (NvChannel*) nvCHAN0Port; + } + + /* Bit of future-proofing here */ + void NvCloseChannel(void) + { + channelOpen=0; + } + + void NV1Sync(void) + { + WaitForIdle(); + } + + /* This function checks to see if an interrupt has been raised, then + * prints out the appropriate registers so that you can attempt to + * figure out what is going on + * if you start mucking around with this chip this will happen a lot + */ + + + + #define CheckBit(var,device,bitfield) \ + if(var & device##_Mask(bitfield)) {\ + Info(#device"_"#bitfield" Set\n");\ + } + + + void NvCheckForErrors(void) + { + UINT32 val=PMC_Read(INTR_0); + /* Has an interrupt been raised ???? */ + /*if(val==0) return;*/ + /* Info("An Interrupt has been raised.\n");*/ + CheckBit(val,PMC,INTR_0_PAUDIO); + CheckBit(val,PMC,INTR_0_PDMA); + CheckBit(val,PMC,INTR_0_PFIFO); + CheckBit(val,PMC,INTR_0_PGRAPH); + CheckBit(val,PMC,INTR_0_PRM); + CheckBit(val,PMC,INTR_0_PTIMER); + CheckBit(val,PMC,INTR_0_PFB); + CheckBit(val,PMC,INTR_0_SOFTWARE); + + val=PGRAPH_Read(INTR_0); + CheckBit(val,PGRAPH,INTR_0_RESERVED); + CheckBit(val,PGRAPH,INTR_0_CONTEXT_SWITCH); + /* CheckBit(val,PGRAPH,INTR_0_VBLANK);*/ + CheckBit(val,PGRAPH,INTR_0_RANGE); + CheckBit(val,PGRAPH,INTR_0_METHOD_COUNT); + CheckBit(val,PGRAPH,INTR_0_SOFTWARE); + CheckBit(val,PGRAPH,INTR_0_COMPLEX_CLIP); + CheckBit(val,PGRAPH,INTR_0_NOTIFY); + + val=PFIFO_Read(INTR_0); + CheckBit(val,PFIFO,INTR_0_CACHE_ERROR); + CheckBit(val,PFIFO,INTR_0_RUNOUT); + CheckBit(val,PFIFO,INTR_0_RUNOUT_OVERFLOW); + } *** /dev/null Tue Jun 30 11:50:07 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/nv3cursor.c Fri Mar 6 16:51:52 1998 *************** *** 0 **** --- 1,427 ---- + /* $TOG: nv3cursor.c /main/1 1998/03/06 16:53:30 kaleb $ */ + + + + /* + * Copyright 1996-1997 David J. McKay + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * DAVID J. MCKAY BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/nv3cursor.c,v 1.1.2.3 1998/02/08 01:12:44 dawes Exp $ */ + + #include "X.h" + #include "Xproto.h" + #include "misc.h" + #include "input.h" + #include "cursorstr.h" + #include "regionstr.h" + #include "scrnintstr.h" + #include "servermd.h" + #include "windowstr.h" + + #include "compiler.h" + #include "vga256.h" + #include "xf86.h" + #include "mipointer.h" + #include "xf86Priv.h" + #include "xf86_Option.h" + #include "xf86_OSlib.h" + #include "vga.h" + + #include "miline.h" + + #include "nv3ref.h" + #include "nvreg.h" + #include "nvcursor.h" + + + static Bool NV3RealizeCursor(); + static Bool NV3UnrealizeCursor(); + static void NV3SetCursor(); + static void NV3MoveCursor(); + static void NV3RecolorCursor(); + + static miPointerSpriteFuncRec NV3PointerSpriteFuncs = + { + NV3RealizeCursor, + NV3UnrealizeCursor, + NV3SetCursor, + NV3MoveCursor, + }; + + /* vga256 interface defines Init, Restore, Warp, QueryBestSize. */ + + + extern miPointerScreenFuncRec xf86PointerScreenFuncs; + extern xf86InfoRec xf86Info; + + static int NV3CursorGeneration = -1; + + /* + * This is the set variables that defines the cursor state within the + * driver. + */ + + static int NV3CursorHotX; + static int NV3CursorHotY; + static CursorPtr NV3CursorpCurs; + + + /* + * This is a high-level init function, called once; it passes a local + * miPointerSpriteFuncRec with additional functions that we need to provide. + * It is called by the SVGA server. + */ + + Bool NV3CursorInit(char *pm,ScreenPtr pScr) + { + unsigned char power; + + NV3CursorHotX = 0; + NV3CursorHotY = 0; + + + if(NV3CursorGeneration != serverGeneration) { + if(!(miPointerInitialize(pScr, &NV3PointerSpriteFuncs, + &xf86PointerScreenFuncs, FALSE))) { + return FALSE; + } + pScr->RecolorCursor = NV3RecolorCursor; + NV3CursorGeneration = serverGeneration; + } + return TRUE; + } + + /* + * This enables displaying of the cursor by the NV3 graphics chip. + * It's a local function, it's not called from outside of the module. + */ + + static void NV3ShowCursor(void) + { + unsigned char tmp; + tmp = PCRTC_Read(GRCURSOR1)|1|PCRTC_Def(GRCURSOR1_CURSOR,ENABLE); + PCRTC_Write(GRCURSOR1,tmp); + } + + /* + * This disables displaying of the cursor by the NV3 graphics chip. + * This is also a local function, it's not called from outside. + */ + void NV3HideCursor(void) + { + unsigned char tmp; + tmp = PCRTC_Read(GRCURSOR1)&(~PCRTC_Def(GRCURSOR1_CURSOR,ENABLE)); + PCRTC_Write(GRCURSOR1,tmp); + } + + /* + * This function is called when a new cursor image is requested by + * the server. The main thing to do is convert the bitwise image + * provided by the server into a format that the graphics card + * can conveniently handle, and store that in system memory. + * Adapted from accel/s3/s3Cursor.c. + */ + + + /* The NV3 supports true colour cursors, useless for X but essential + * for those animated cursors under Win95! + */ + #define MAX_CURS 32 + #define TRANSPARENT_PIXEL 0 + #define SHOW + typedef struct { + unsigned short foreColour, /* Colour for this cursor in RGB555 */ + backColour; + unsigned short image[MAX_CURS*MAX_CURS]; /* Image */ + int address; /* Pramin where image loaded */ + }NV3Cursor; + + + static unsigned short ConvertToRGB555(int red,int green,int blue) + { + unsigned short colour; + + colour=((red>>11)&0x1f)<<10; + colour|=((green>>11)&0x1f)<<5; + colour|=((blue>>11)&0x1f); + colour|=1<<15; /* We must set the top bit, else it appears transparent */ + + return colour; + } + + static void RenderCursor(CursorBits *bits,NV3Cursor *cursor) + { + int x,y,i; + int byteIndex,bitIndex,maskBit,sourceBit; + int height,width; + int pad,lineOffset; + unsigned char *source,*mask; + + height = bits->height; + width=bits->width; + source=(unsigned char*)bits->source; + pad=PixmapBytePad(bits->width, 1);/* Bytes per line. */ + mask=(unsigned char*)bits->mask; + for(y=0,i=0,lineOffset=0;y<MAX_CURS;y++,lineOffset+=pad) { + for(x=0;x<MAX_CURS;x++,i++) { + if(x<width && y<height) { + byteIndex=lineOffset+(x/8);bitIndex=x%8; + maskBit=mask[byteIndex]&(1<<bitIndex); + sourceBit=source[byteIndex]&(1<<bitIndex); + if(maskBit) { + cursor->image[i]=(sourceBit) ? cursor->foreColour : + cursor->backColour; + }else { + cursor->image[i]=TRANSPARENT_PIXEL; + } + }else { + cursor->image[i]=TRANSPARENT_PIXEL; + } + } + } + } + + static Bool NV3RealizeCursor(ScreenPtr pScr,CursorPtr pCurs) + { + NV3Cursor *ram; + int index = pScr->myNum; + pointer *pPriv = &pCurs->bits->devPriv[index]; + CursorBits *bits = pCurs->bits; + + /* Presumably this checks to see if this is already the cursor in there */ + if(pCurs->bits->refcnt > 1) return TRUE; + + ram = (NV3Cursor*)xalloc(sizeof(NV3Cursor)); + *pPriv = (pointer) ram; + if(!ram) return FALSE; + + ram->foreColour= + ConvertToRGB555(pCurs->foreRed,pCurs->foreGreen,pCurs->foreBlue); + ram->backColour= + ConvertToRGB555(pCurs->backRed,pCurs->backGreen,pCurs->backBlue); + + RenderCursor(bits,ram); + + return TRUE; + } + + /* + * This is called when a cursor is no longer used. The intermediate + * cursor image storage that we created needs to be deallocated. + */ + + static Bool NV3UnrealizeCursor(ScreenPtr pScr,CursorPtr pCurs) + { + pointer priv; + + if(pCurs->bits->refcnt <= 1 && + (priv = pCurs->bits->devPriv[pScr->myNum])) { + xfree(priv); + pCurs->bits->devPriv[pScr->myNum] = 0x0; + } + return TRUE; + } + + /* + * This function uploads a cursor image to the video memory of the + * graphics card. The source image has already been converted by the + * Realize function to a format that can be quickly transferred to + * the card. + * This is a local function that is not called from outside of this + * module. + */ + + #define PRAMINRead nvPRAMINPort(addr) nvPRAMINPort[addr] + #define PRAMINWrite(addr,val) nvPRAMINPort[addr]=(val) + + #define CURSOR_ADDRESS ((8192-2048)/4) + + #define SetBitField(value,from,to) SetBF(to,GetBF(value,from)) + #define SetBit(n) (1<<(n)) + #define Set8Bits(value) ((value)&0xff) + + static void NV3LoadCursorToCard(ScreenPtr pScr,CursorPtr pCurs) + { + NV3Cursor *cursor; + int index = pScr->myNum; + int i; + int numInts; + int *image; + int save; + + if(!xf86VTSema) + return; + + cursor=(NV3Cursor*) pCurs->bits->devPriv[index]; + numInts=sizeof(cursor->image)/sizeof(int); + image=(int*)cursor->image; + + save=PCRTC_Read(GRCURSOR1); + + PCRTC_Write(GRCURSOR1,0); + + /* Upload the cursor to the card */ + for(i=0;i<numInts;i++) { + PRAMINWrite(CURSOR_ADDRESS+i,image[i]); + } + /* Tell the ramdac where we are */ + PCRTC_Write(GRCURSOR0,SetBitField(CURSOR_ADDRESS*4,21:16,5:0)); + save&=0x7; + PCRTC_Write(GRCURSOR1,save|SetBitField(CURSOR_ADDRESS*4,15:11,7:3)); + + + } + + /* + * This function should make the graphics chip display new cursor that + * has already been "realized". We need to upload it to video memory, + * make the graphics chip display it. + * This is a local function that is not called from outside of this + * module (although it largely corresponds to what the SetCursor + * function in the Pointer record needs to do). + */ + + static void NV3LoadCursor(ScreenPtr pScr,CursorPtr pCurs,int x,int y) + { + + if(!xf86VTSema) + return; + + if(!pCurs) + return; + + /* Remember the cursor currently loaded into this cursor slot. */ + NV3CursorpCurs = pCurs; + + NV3HideCursor(); + + NV3LoadCursorToCard(pScr, pCurs); + + /* Position cursor */ + NV3MoveCursor(pScr, x, y); + + /* Turn it on. */ + NV3ShowCursor(); + } + + /* + * This function should display a new cursor at a new position. + */ + + static void NV3SetCursor(ScreenPtr pScr,CursorPtr pCurs,int x,int y, + Bool generateEvent) + { + if(!pCurs) + return; + + NV3CursorHotX = pCurs->bits->xhot; + NV3CursorHotY = pCurs->bits->yhot; + + NV3LoadCursor(pScr, pCurs, x, y); + } + + /* + * This function should redisplay a cursor that has been + * displayed earlier. It is called by the SVGA server. + */ + + void NV3RestoreCursor(ScreenPtr pScr) + { + int x, y; + + miPointerPosition(&x, &y); + + NV3LoadCursor(pScr, NV3CursorpCurs, x, y); + } + + /* + * This function is called when the current cursor is moved. It makes + * the graphic chip display the cursor at the new position. + */ + + static void NV3MoveCursor(ScreenPtr pScr,int x,int y) + { + int xorigin, yorigin; + + if(!xf86VTSema) return; + + x -= vga256InfoRec.frameX0 + NV3CursorHotX; + y -= vga256InfoRec.frameY0 + NV3CursorHotY; + x&=PRAMDAC_Mask(GRCURSOR_START_POS_X); + PRAMDAC_Write(GRCURSOR_START_POS,PRAMDAC_Val(GRCURSOR_START_POS_X,x)| + PRAMDAC_Val(GRCURSOR_START_POS_Y,y)); + } + + /* + * This is a local function that programs the colors of the cursor + * on the graphics chip. + * Adapted from accel/s3/s3Cursor.c. + */ + + static void NV3RecolorCursor(ScreenPtr pScr,CursorPtr pCurs,Bool displayed) + { + CursorBits *bits = pCurs->bits; + int index = pScr->myNum; + NV3Cursor *cursor=(NV3Cursor*) pCurs->bits->devPriv[index]; + unsigned short fore,back; + + if(!xf86VTSema) return; + + if(!displayed) return; + + fore=ConvertToRGB555(pCurs->foreRed,pCurs->foreGreen,pCurs->foreBlue); + back=ConvertToRGB555(pCurs->backRed,pCurs->backGreen,pCurs->backBlue); + + if(cursor->foreColour==fore && cursor->backColour==back) return; + + NV3LoadCursorToCard(pScr,pCurs); + + } + + /* + * This doesn't do very much. It just calls the mi routine. It is called + * by the SVGA server. + */ + + void NV3WarpCursor(ScreenPtr pScr,int x,int y) + { + miPointerWarpCursor(pScr, x, y); + xf86Info.currentScreen = pScr; + } + + /* + * This function is called by the SVGA server. It returns the + * size of the hardware cursor that we support when asked for. + * It is called by the SVGA server. + */ + + void NV3QueryBestSize(int class,unsigned short *pwidth, + unsigned short *pheight,ScreenPtr pScreen) + { + if(*pwidth > 0) { + if(class == CursorShape) { + *pwidth = MAX_CURS; + *pheight = MAX_CURS; + } else + (void)mfbQueryBestSize(class, pwidth, pheight, pScreen); + } + } + *** /dev/null Tue Jun 30 11:50:09 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/nv3driver.c Fri Mar 6 16:51:56 1998 *************** *** 0 **** --- 1,498 ---- + /* $TOG: nv3driver.c /main/1 1998/03/06 16:53:34 kaleb $ */ + + + + /* + * Copyright 1996-1997 David J. McKay + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * DAVID J. MCKAY BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/nv3driver.c,v 1.1.2.3 1998/01/24 11:55:09 dawes Exp $ */ + + #include <math.h> + #include <stdlib.h> + + + #include "X.h" + #include "input.h" + #include "screenint.h" + + #include "compiler.h" + #include "xf86.h" + #include "xf86Priv.h" + #include "xf86_OSlib.h" + #include "xf86_HWlib.h" + #include "vga.h" + + #include "vgaPCI.h" + + #define XCONFIG_FLAGS_ONLY + #include "xf86_Config.h" + + + #ifdef XFreeXDGA + #include "X.h" + #include "Xproto.h" + #include "scrnintstr.h" + #include "servermd.h" + #define _XF86DGA_SERVER_ + #include "extensions/xf86dgastr.h" + #endif + + #include "nv3ref.h" + #include "nvcursor.h" + #include "nvreg.h" + + + #include "nvvga.h" + + void NV3EnterLeave(Bool enter) + { + unsigned char temp; + + if(enter) { + xf86EnableIOPorts(vga256InfoRec.scrnIndex); + outb(vgaIOBase + 4, 0x11); temp = inb(vgaIOBase + 5); + outb(vgaIOBase + 5, temp & 0x7F); + SR_Write(LOCK_EXT_INDEX,UNLOCK_EXT_MAGIC); + }else { + outb(vgaIOBase + 4, 0x11); temp = inb(vgaIOBase + 5); + outb(vgaIOBase + 5, (temp & 0x7F) | 0x80); + SR_Write(LOCK_EXT_INDEX,LOCK_EXT_MAGIC); + xf86DisableIOPorts(vga256InfoRec.scrnIndex); + } + } + + #define MapDevice(device,base) \ + nv##device##Port=(unsigned*)xf86MapVidMem(vga256InfoRec.scrnIndex,\ + MMIO_REGION,\ + ((char*)(base))+DEVICE_BASE(device),\ + DEVICE_SIZE(device)) + + + static void MapNV3Regs(void *regBase,void *frameBase) + { + MapDevice(PRAMDAC,regBase); + MapDevice(PFB,regBase); + MapDevice(PFIFO,regBase); + MapDevice(PGRAPH,regBase); + MapDevice(PMC,regBase); + MapDevice(CHAN0,regBase); + MapDevice(PRAMIN,frameBase); + } + + #define NV3_MAX_CLOCK_IN_KHZ 230000 + + static void NV3FlipFunctions(vgaVideoChipRec *nv); + + int NV3Probe(vgaVideoChipRec *nv,void *base0,void *base1) + { + int noaccel= OFLG_ISSET(OPTION_NOACCEL,&vga256InfoRec.options); + + /* By the time we have got here, we know it is an NV3 */ + vga256InfoRec.maxClock = NV3_MAX_CLOCK_IN_KHZ; + + MapNV3Regs(base0,base1); + + if(!vga256InfoRec.videoRam) { + vga256InfoRec.videoRam = (1024 << + (PFB_Read(BOOT_0) & PFB_Mask(BOOT_0_RAM_AMOUNT))); + } + nv->ChipLinearSize=vga256InfoRec.videoRam*1024; + /* Doesn't feel right that this should be an int! */ + nv->ChipLinearBase=(int)base1; + nv->ChipHas32bpp=TRUE; + /* I/O ports are needed for things like pallete selection etc */ + xf86ClearIOPortList (vga256InfoRec.scrnIndex); + xf86AddIOPorts(vga256InfoRec.scrnIndex,Num_VGA_IOPorts,VGA_IOPorts); + xf86EnableIOPorts(vga256InfoRec.scrnIndex); + vgaIOBase = (inb(0x3CC) & 0x01) ? 0x3D0 : 0x3B0; + NV3EnterLeave(ENTER); + + /* The NV1 only supports 555 weighting, so force it here */ + if(vgaBitsPerPixel==16 && !noaccel) { + ErrorF("%s %s: %s: Setting RGB weight to 555\n",XCONFIG_PROBED, + vga256InfoRec.name, + vga256InfoRec.chipset); + xf86weight.green=xf86weight.blue=xf86weight.red=5; + } + + OFLG_SET(OPTION_NOACCEL, &(nv->ChipOptionFlags)); + OFLG_SET(OPTION_SW_CURSOR, &(nv->ChipOptionFlags)); + + NV3FlipFunctions(nv); + + return 1; + } + + /* + * Fout=(Fin *(N/M)) / (1<<P) + * + * Constraints: + * 1Mhz <= Fin/M <= 2Mhz + * 128Hhz <= Fin * (N/M) <= 256Mhz + * + */ + + /* NTSC cards have approx 14.3Mhz. Need to detect, but leave for now*/ + #define PLL_INPUT_FREQ 13500 + #define M_MIN 7 + #define M_MAX 13 + + #define P_MIN 0 + #define P_MAX 7 /* Not sure about this. Could be 4 */ + + static int NV3ClockSelect(float clockIn,float *clockOut,int *mOut, + int *nOut,int *pOut) + { + int m,n,p; + float bestDiff=1e10; + float target=0.0; + float best=0.0; + float diff; + int nMax,nMin; + + *clockOut=0.0; + for(p=P_MIN;p<=P_MAX;p++) { + for(m=M_MIN;m<=M_MAX;m++) { + float fm=(float)m; + /* Now calculate maximum and minimum values for n */ + nMax=(int) (((256000/PLL_INPUT_FREQ)*fm)-0.5); + nMin=(int) (((128000/PLL_INPUT_FREQ)*fm)+0.5); + n=(int)(((clockIn*((float)(1<<p)))/PLL_INPUT_FREQ)*fm); + if(n>=nMin && n<=nMax) { + float fn=(float)n; + target=(PLL_INPUT_FREQ*(fn/fm))/((float)(1<<p)); + diff=fabs(target-clockIn); + if(diff<bestDiff) { + bestDiff=diff; + best=target; + *mOut=m;*nOut=n;*pOut=p; + *clockOut=best; + } + } + } + } + return (best!=0.0); + } + + #define new ((vgaNVPtr)vgaNewVideoState) + + /* Very useful macro that allows you to set overflow bits */ + #define SetBitField(value,from,to) SetBF(to,GetBF(value,from)) + #define SetBit(n) (1<<(n)) + #define Set8Bits(value) ((value)&0xff) + + static int CalculateCRTC(DisplayModePtr mode) + { + int bpp=vgaBitsPerPixel/8, + horizDisplay = (mode->CrtcHDisplay/8) - 1, + horizStart = (mode->CrtcHSyncStart/8) - 1, + horizEnd = (mode->CrtcHSyncEnd/8) - 1, + horizTotal = (mode->CrtcHTotal/8) - 1, + vertDisplay = mode->CrtcVDisplay - 1, + vertStart = mode->CrtcVSyncStart - 1, + vertEnd = mode->CrtcVSyncEnd - 1, + vertTotal = mode->CrtcVTotal - 2; + + /* Calculate correct value for offset register */ + new->std.CRTC[0x13]=((vga256InfoRec.displayWidth/8)*bpp)&0xff; + /* Extra bits for CRTC offset register */ + new->regs.nv3.repaint0= + SetBitField((vga256InfoRec.displayWidth/8)*bpp,10:8,7:5); + + /* The NV3 manuals states that for native modes, there should be no + * borders. This code should also be tidied up to use symbolic names + */ + new->std.CRTC[0x0]=Set8Bits(horizTotal - 4); + new->std.CRTC[0x1]=Set8Bits(horizDisplay); + new->std.CRTC[0x2]=Set8Bits(horizDisplay); + new->std.CRTC[0x3]=SetBitField(horizTotal,4:0,4:0) | SetBit(7); + new->std.CRTC[0x4]=Set8Bits(horizStart); + new->std.CRTC[0x5]=SetBitField(horizTotal,5:5,7:7)| + SetBitField(horizEnd,4:0,4:0); + new->std.CRTC[0x6]=SetBitField(vertTotal,7:0,7:0); + + new->std.CRTC[0x7]=SetBitField(vertTotal,8:8,0:0)| + SetBitField(vertDisplay,8:8,1:1)| + SetBitField(vertStart,8:8,2:2)| + SetBitField(vertDisplay,8:8,3:3)| + SetBit(4)| + SetBitField(vertTotal,9:9,5:5)| + SetBitField(vertDisplay,9:9,6:6)| + SetBitField(vertStart,9:9,7:7); + + new->std.CRTC[0x9]= SetBitField(vertDisplay,9:9,5:5) | SetBit(6); + new->std.CRTC[0x10]= Set8Bits(vertStart); + new->std.CRTC[0x11]= SetBitField(vertEnd,3:0,3:0) | SetBit(5); + new->std.CRTC[0x12]= Set8Bits(vertDisplay); + new->std.CRTC[0x15]= Set8Bits(vertDisplay); + new->std.CRTC[0x16]= Set8Bits(vertTotal + 1); + + new->regs.nv3.screenExtra= SetBitField(horizTotal,6:6,4:4) | + SetBitField(vertDisplay,10:10,3:3) | + SetBitField(vertStart,10:10,2:2) | + SetBitField(vertDisplay,10:10,1:1) | + SetBitField(vertTotal,10:10,0:0); + + if(mode->Flags & V_DBLSCAN) new->std.CRTC[0x9]|=0x80; + + /* I think this should be SetBitField(horizTotal,8:8,0:0), but this + * doesn't work apparently. Why 260 ? 256 would make sense. + */ + new->regs.nv3.horizExtra= (horizTotal < 260 ? 0 : 1); + return 1; + } + + /* Gamma seems possible only for 15bpp and 32bpp. Need to fiddle + * around to confirm this + */ + #define GammaMode() (!(vgaBitsPerPixel==8 || xf86weight.green==6)) + + static void InitPalette(DisplayModePtr mode) + { + int bpp=vgaBitsPerPixel/8; + int i; + + if(!GammaMode()) return; + /* Put simple ramp in for now !! */ + /* Do any other drivers implement gamma ?? */ + for(i=0;i<256;i++) { + new->std.DAC[i*3]=i>>2; + new->std.DAC[(i*3)+1]=i>>2; + new->std.DAC[(i*3)+2]=i>>2; + } + } + + + static Bool NV3Init(DisplayModePtr mode) + { + int m,n,p; + float clockIn=(float)vga256InfoRec.clock[mode->Clock]; + float clockOut; + int time,data; + int i; + int pixelDepth; + + /* Calculate standard VGA settings */ + if(!vgaHWInit (mode, sizeof (vgaNVRec))) { + return 0; + } + + /* Calculate Vclock frequency */ + if(!NV3ClockSelect(clockIn,&clockOut,&m,&n,&p)) { + ErrorF("%s %s: %s: Unable to set desired video clock\n", + XCONFIG_PROBED, vga256InfoRec.name,vga256InfoRec.chipset); + return FALSE; + } + new->regs.nv3.vpllCoeff=PRAMDAC_Val(VPLL_COEFF_NDIV,n) | + PRAMDAC_Val(VPLL_COEFF_MDIV,m) | + PRAMDAC_Val(VPLL_COEFF_PDIV,p); + + /* VGA is always valid for the NV3 */ + new->vgaValid=1; + + CalculateCRTC(mode); + InitPalette(mode); + + /* For now I don't support 8 bit pallettes but it is easy to add */ + new->regs.nv3.repaint1= + PCRTC_Val(REPAINT1_LARGE_SCREEN,mode->CrtcHDisplay<1280) | + PCRTC_Def(REPAINT1_PALETTE_WIDTH,6BITS); + + /* Need to figure out what the algorithm to set these are */ + new->regs.nv3.fifoControl=0x82;/*PCRTC_Def(FIFO_CONTROL_BURST_LENGTH,64);*/ + new->regs.nv3.fifo=0x22;/*PCRTC_Val(FIFO_WATERMARK,256>>3)| + PCRTC_Val(FIFO_RESET,1);*/ + + + /* PixelFormat controls how many bits per pixel. + * There is another register in the + * DAC which controls if mode is 5:5:5 or 5:6:5 + */ + pixelDepth=(vgaBitsPerPixel+1)/8; + if(pixelDepth>3) pixelDepth=3; + new->regs.nv3.pixelFormat=pixelDepth; + + new->regs.nv3.generalControl= + PRAMDAC_Def(GENERAL_CONTROL_IDC_MODE,GAMMA)| + PRAMDAC_Val(GENERAL_CONTROL_565_MODE,xf86weight.green==6)| + PRAMDAC_Def(GENERAL_CONTROL_TERMINATION,37OHM)| + PRAMDAC_Def(GENERAL_CONTROL_BPC,6BITS)| + PRAMDAC_Def(GENERAL_CONTROL_VGA_STATE,SEL); /* Not sure about this */ + + /* This makes sure that the Mclock and Vclock are are actually selected + * via the PLL. It also sets the Vclock/Pclock ratio to be divide by 2 + * or not. Not sure when this should be divide by 1, presumably for + * very high Vclock???? + */ + new->regs.nv3.coeffSelect=PRAMDAC_Def(PLL_COEFF_SELECT_MPLL_SOURCE,PROG)| + PRAMDAC_Def(PLL_COEFF_SELECT_VPLL_SOURCE,PROG)| + PRAMDAC_Def(PLL_COEFF_SELECT_VCLK_RATIO,DB2); + + /* Disable Tetris tiling for now. This looks completely mad but could + * give some significant performance gains. Will perhaps experiment + * later on with this stuff! + */ + new->regs.nv3.config0= + PFB_Val(CONFIG_0_RESOLUTION,((vga256InfoRec.displayWidth+31)/32))| + PFB_Val(CONFIG_0_PIXEL_DEPTH,pixelDepth)| + PFB_Def(CONFIG_0_TILING,DISABLED); + + return TRUE; + } + + + + static void NV3Restore(void *data) + { + vgaNVPtr restore=data; + NV3Registers *nv3=&(restore->regs.nv3); + + /* I do not know what this does */ + vgaProtect(TRUE); + + PCRTC_Write(REPAINT0,nv3->repaint0); + PCRTC_Write(REPAINT1,nv3->repaint1); + PCRTC_Write(EXTRA,nv3->screenExtra); + PCRTC_Write(PIXEL,nv3->pixelFormat); + PCRTC_Write(HORIZ_EXTRA,nv3->horizExtra); + PCRTC_Write(FIFO_CONTROL,nv3->fifoControl); + + PFB_Write(CONFIG_0,nv3->config0); + + PRAMDAC_Write(VPLL_COEFF,nv3->vpllCoeff); + PRAMDAC_Write(PLL_COEFF_SELECT,nv3->coeffSelect); + PRAMDAC_Write(GENERAL_CONTROL,nv3->generalControl); + + vgaHWRestore((vgaHWPtr)restore); + + vgaProtect(FALSE); + } + + static void *NV3Save(void *data) + { + vgaNVPtr save=NULL; + + save=(vgaNVPtr)vgaHWSave((vgaHWPtr)data,sizeof(vgaNVRec)); + save->regs.nv3.repaint0=PCRTC_Read(REPAINT0); + save->regs.nv3.repaint1=PCRTC_Read(REPAINT1); + save->regs.nv3.screenExtra=PCRTC_Read(EXTRA); + save->regs.nv3.pixelFormat=PCRTC_Read(PIXEL); + save->regs.nv3.horizExtra=PCRTC_Read(HORIZ_EXTRA); + save->regs.nv3.fifoControl=PCRTC_Read(FIFO_CONTROL); + save->regs.nv3.fifo=PCRTC_Read(FIFO); + save->regs.nv3.config0=PFB_Read(CONFIG_0); + + save->regs.nv3.vpllCoeff=PRAMDAC_Read(VPLL_COEFF); + save->regs.nv3.coeffSelect=PRAMDAC_Read(PLL_COEFF_SELECT); + save->regs.nv3.generalControl=PRAMDAC_Read(GENERAL_CONTROL); + + return (void*)save; + } + + + static void NV3Adjust(int x,int y) + { + int bpp=vgaBitsPerPixel/8; + int startAddr=(((y*vga256InfoRec.virtualX)+x)*bpp); + int offset=startAddr>>2; + int pan=(startAddr&3)*2; + unsigned char byte; + + /* Now shift start address. Word aligned */ + CRTC_Write(0x0d,Set8Bits(offset)); + CRTC_Write(0x0c,SetBitField(offset,15:8,7:0)); + byte=PCRTC_Read(REPAINT0) & ~PCRTC_Mask(REPAINT0_START_ADDR_20_16); + PCRTC_Write(REPAINT0,SetBitField(offset,20:16,4:0)|byte); + /* Attribute register 0x13 is used to provide up to 4 pixel shift */ + byte=inb(vgaIOBase+0x0a); + outb(0x3c0,0x13); + outb(0x3c0,pan); + } + + + static int NV3ValidMode(DisplayModePtr mode,Bool verbose,int flag) + { + return MODE_OK; + } + + + extern vgaHWCursorRec vgaHWCursor; + + static void NV3FbInit(void) + { + /* Need check in here for wierd resolutions !! */ + + if(!OFLG_ISSET(OPTION_SW_CURSOR, &vga256InfoRec.options)) { + /* Initialise the hardware cursor */ + vgaHWCursor.Initialized = TRUE; + vgaHWCursor.Init = NV3CursorInit; + vgaHWCursor.Restore = NV3RestoreCursor; + vgaHWCursor.Warp = NV3WarpCursor; + vgaHWCursor.QueryBestSize = NV3QueryBestSize; + if(xf86Verbose) { + ErrorF("%s %s: %s: Using hardware cursor\n",XCONFIG_PROBED, + vga256InfoRec.name,vga256InfoRec.chipset); + } + } + + if(!OFLG_ISSET(OPTION_NOACCEL, &vga256InfoRec.options)) { + NVAccelInit(); + } + + } + + static void NV3DisplayPowerManagementSet(int mode) + { + } + + static Bool NV3ScreenInit(ScreenPtr pScreen,pointer pbits, + int xsize,int ysize,int dpix,int dpiy,int width) + { + return TRUE; + } + + + + static void NV3SaveScreen(int on) + { + vgaHWSaveScreen(on); + } + + static void NV3GetMode(DisplayModePtr display) + { + } + + /* Changes the entries in the NV struct to point at the correct function + * pointers. Called from the Probe() function + */ + static void NV3FlipFunctions(vgaVideoChipRec *nv) + { + nv->ChipEnterLeave=NV3EnterLeave; + nv->ChipInit=NV3Init; + nv->ChipValidMode=NV3ValidMode; + nv->ChipSave=NV3Save; + nv->ChipRestore=NV3Restore; + nv->ChipAdjust=NV3Adjust; + nv->ChipSaveScreen=NV3SaveScreen; + nv->ChipGetMode=(void (*)())NoopDDA; + nv->ChipFbInit=NV3FbInit; + } *** /dev/null Tue Jun 30 11:50:10 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/nv3ref.h Fri Mar 6 16:52:00 1998 *************** *** 0 **** --- 1,642 ---- + /* $TOG: nv3ref.h /main/1 1998/03/06 16:53:38 kaleb $ */ + + + + /***************************************************************************\ + |* *| + |* Copyright (c) 1996-1998 NVIDIA, Corp. All rights reserved. *| + |* *| + |* NOTICE TO USER: The source code is copyrighted under U.S. and *| + |* international laws. NVIDIA, Corp. of Sunnyvale, California owns *| + |* the copyright and as design patents pending on the design and *| + |* interface of the NV chips. Users and possessors of this source *| + |* code are hereby granted a nonexclusive, royalty-free copyright *| + |* and design patent license to use this code in individual and *| + |* commercial software. *| + |* *| + |* Any use of this source code must include, in the user documenta- *| + |* tion and internal comments to the code, notices to the end user *| + |* as follows: *| + |* *| + |* Copyright (c) 1996-1998 NVIDIA, Corp. NVIDIA design patents *| + |* pending in the U.S. and foreign countries. *| + |* *| + |* NVIDIA, CORP. MAKES NO REPRESENTATION ABOUT THE SUITABILITY OF *| + |* THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" WITHOUT *| + |* EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORP. DISCLAIMS *| + |* ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, INCLUDING ALL *| + |* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *| + |* PARTICULAR PURPOSE. IN NO EVENT SHALL NVIDIA, CORP. BE LIABLE *| + |* FOR ANY SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, *| + |* OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR *| + |* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER *| + |* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR *| + |* PERFORMANCE OF THIS SOURCE CODE. *| + |* *| + \***************************************************************************/ + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/nv3ref.h,v 1.1.2.3 1998/01/24 00:04:39 robin Exp $ */ + + #ifndef __NV3REF_H__ + #define __NV3REF_H__ + + + /* Magic values to lock/unlock extended regs */ + #define UNLOCK_EXT_MAGIC 0x57 + #define LOCK_EXT_MAGIC 0x99 /* Any value other than 0x57 will do */ + + #define LOCK_EXT_INDEX 0x6 + + /* Extended offset and start address */ + #define NV_PCRTC_REPAINT0 0x19 + #define NV_PCRTC_REPAINT0_OFFSET_10_8 7:5 + #define NV_PCRTC_REPAINT0_START_ADDR_20_16 4:0 + + /* Horizonal extended bits */ + #define NV_PCRTC_HORIZ_EXTRA 0x2d + #define NV_PCRTC_HORIZ_EXTRA_INTER_HALF_START_8 4:4 + #define NV_PCRTC_HORIZ_EXTRA_HORIZ_RETRACE_START_8 3:3 + #define NV_PCRTC_HORIZ_EXTRA_HORIZ_BLANK_START_8 2:2 + #define NV_PCRTC_HORIZ_EXTRA_DISPLAY_END_8 1:1 + #define NV_PCRTC_HORIZ_EXTRA_DISPLAY_TOTAL_8 0:0 + + /* Assorted extra bits */ + #define NV_PCRTC_EXTRA 0x25 + #define NV_PCRTC_EXTRA_OFFSET_11 5:5 + #define NV_PCRTC_EXTRA_HORIZ_BLANK_END_6 4:4 + #define NV_PCRTC_EXTRA_VERT_BLANK_START_10 3:3 + #define NV_PCRTC_EXTRA_VERT_RETRACE_START_10 2:2 + #define NV_PCRTC_EXTRA_VERT_DISPLAY_END_10 1:1 + #define NV_PCRTC_EXTRA_VERT_TOTAL_10 0:0 + + + /* Controls how much data the refresh fifo requests */ + #define NV_PCRTC_FIFO_CONTROL 0x1b + #define NV_PCRTC_FIFO_CONTROL_UNDERFLOW_WARN 7:7 + #define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH 2:0 + #define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_8 0x0 + #define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_32 0x1 + #define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_64 0x2 + #define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_128 0x3 + #define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_256 0x4 + + /* When the fifo occupancy falls below *twice* the watermark, + * the refresh fifo will start to be refilled. If this value is + * too low, you will get junk on the screen. Too high, and performance + * will suffer. Watermark in units of 8 bytes + */ + #define NV_PCRTC_FIFO 0x20 + #define NV_PCRTC_FIFO_RESET 7:7 + #define NV_PCRTC_FIFO_WATERMARK 5:0 + + + /* Various flags */ + #define NV_PCRTC_REPAINT1 0x1a + #define NV_PCRTC_REPAINT1_HSYNC 7:7 + #define NV_PCRTC_REPAINT1_HYSNC_DISABLE 0x01 + #define NV_PCRTC_REPAINT1_HYSNC_ENABLE 0x00 + #define NV_PCRTC_REPAINT1_VSYNC 6:6 + #define NV_PCRTC_REPAINT1_VYSNC_DISABLE 0x01 + #define NV_PCRTC_REPAINT1_VYSNC_ENABLE 0x00 + #define NV_PCRTC_REPAINT1_COMPATIBLE_TEXT 4:4 + #define NV_PCRTC_REPAINT1_COMPATIBLE_TEXT_ENABLE 0x01 + #define NV_PCRTC_REPAINT1_COMPATIBLE_TEXT_DISABLE 0x00 + #define NV_PCRTC_REPAINT1_LARGE_SCREEN 2:2 + #define NV_PCRTC_REPAINT1_LARGE_SCREEN_DISABLE 0x01 + #define NV_PCRTC_REPAINT1_LARGE_SCREEN_ENABLE 0x00 /* >=1280 */ + #define NV_PCRTC_REPAINT1_PALETTE_WIDTH 1:1 + #define NV_PCRTC_REPAINT1_PALETTE_WIDTH_8BITS 0x00 + #define NV_PCRTC_REPAINT1_PALETTE_WIDTH_6BITS 0x01 + + + #define NV_PCRTC_GRCURSOR0 0x30 + #define NV_PCRTC_GRCURSOR0_START_ADDR_21_16 5:0 + + #define NV_PCRTC_GRCURSOR1 0x31 + #define NV_PCRTC_GRCURSOR1_START_ADDR_15_11 7:3 + #define NV_PCRTC_GRCURSOR1_SCAN_DBL 1:1 + #define NV_PCRTC_GRCURSOR1_SCAN_DBL_DISABLE 0 + #define NV_PCRTC_GRCURSOR1_SCAN_DBL_ENABLE 1 + #define NV_PCRTC_GRCURSOR1_CURSOR 0:0 + #define NV_PCRTC_GRCURSOR1_CURSOR_DISABLE 0 + #define NV_PCRTC_GRCURSOR1_CURSOR_ENABLE 1 + + + + /* Controls what the format of the framebuffer is */ + #define NV_PCRTC_PIXEL 0x28 + #define NV_PCRTC_PIXEL_MODE 7:7 + #define NV_PCRTC_PIXEL_MODE_TV 0x01 + #define NV_PCRTC_PIXEL_MODE_VGA 0x00 + #define NV_PCRTC_PIXEL_TV_MODE 6:6 + #define NV_PCRTC_PIXEL_TV_MODE_NTSC 0x00 + #define NV_PCRTC_PIXEL_TV_MODE_PAL 0x01 + #define NV_PCRTC_PIXEL_TV_HORIZ_ADJUST 5:3 + #define NV_PCRTC_PIXEL_FORMAT 1:0 + #define NV_PCRTC_PIXEL_FORMAT_VGA 0x00 + #define NV_PCRTC_PIXEL_FORMAT_8BPP 0x01 + #define NV_PCRTC_PIXEL_FORMAT_16BPP 0x02 + #define NV_PCRTC_PIXEL_FORMAT_32BPP 0x03 + + + #define NV_PRAMDAC 0x00680FFF:0x00680000 /* RW--D */ + + #define NV_PRAMDAC_VPLL_COEFF 0x00680508 /* RW-4R */ + #define NV_PRAMDAC_VPLL_COEFF_MDIV 7:0 /* RWIUF */ + #define NV_PRAMDAC_VPLL_COEFF_NDIV 15:8 /* RWIUF */ + #define NV_PRAMDAC_VPLL_COEFF_PDIV 18:16 /* RWIVF */ + + + #define NV_PRAMDAC_PLL_COEFF_SELECT 0x0068050C /* RW-4R */ + #define NV_PRAMDAC_PLL_COEFF_SELECT_DLL_BYPASS 4:4 /* RWIVF */ + #define NV_PRAMDAC_PLL_COEFF_SELECT_DLL_BYPASS_FALSE 0x00000000 /* RWI-V */ + #define NV_PRAMDAC_PLL_COEFF_SELECT_DLL_BYPASS_TRUE 0x00000001 /* RW--V */ + #define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_SOURCE 8:8 /* RWIVF */ + #define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_SOURCE_DEFAULT 0x00000000 /* RWI-V */ + #define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_SOURCE_PROG 0x00000001 /* RW--V */ + #define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_BYPASS 12:12 /* RWIVF */ + #define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_BYPASS_FALSE 0x00000000 /* RWI-V */ + #define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_BYPASS_TRUE 0x00000001 /* RW--V */ + #define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_SOURCE 16:16 /* RWIVF */ + #define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_SOURCE_DEFAULT 0x00000000 /* RWI-V */ + #define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_SOURCE_PROG 0x00000001 /* RW--V */ + #define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_BYPASS 20:20 /* RWIVF */ + #define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_BYPASS_FALSE 0x00000000 /* RWI-V */ + #define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_BYPASS_TRUE 0x00000001 /* RW--V */ + #define NV_PRAMDAC_PLL_COEFF_SELECT_PCLK_SOURCE 25:24 /* RWIVF */ + #define NV_PRAMDAC_PLL_COEFF_SELECT_PCLK_SOURCE_VPLL 0x00000000 /* RWI-V */ + #define NV_PRAMDAC_PLL_COEFF_SELECT_PCLK_SOURCE_VIP 0x00000001 /* RW--V */ + #define NV_PRAMDAC_PLL_COEFF_SELECT_PCLK_SOURCE_XTALOSC 0x00000002 /* RW--V */ + #define NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO 28:28 /* RWIVF */ + #define NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB1 0x00000000 /* RWI-V */ + #define NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB2 0x00000001 /* RW--V */ + + + /* Various flags for DAC. BPC controls the width of the palette */ + + #define NV_PRAMDAC_GENERAL_CONTROL 0x00680600 /* RW-4R */ + #define NV_PRAMDAC_GENERAL_CONTROL_FF_COEFF 1:0 /* RWIVF */ + #define NV_PRAMDAC_GENERAL_CONTROL_FF_COEFF_DEF 0x00000000 /* RWI-V */ + #define NV_PRAMDAC_GENERAL_CONTROL_IDC_MODE 4:4 /* RWIVF */ + #define NV_PRAMDAC_GENERAL_CONTROL_IDC_MODE_GAMMA 0x00000000 /* RWI-V */ + #define NV_PRAMDAC_GENERAL_CONTROL_IDC_MODE_INDEX 0x00000001 /* RW--V */ + #define NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE 8:8 /* RWIVF */ + #define NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_NOTSE 0x00000000 /* RWI-V */ + #define NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_SEL 0x00000001 /* RW--V */ + #define NV_PRAMDAC_GENERAL_CONTROL_565_MODE 12:12 /* RWIVF */ + #define NV_PRAMDAC_GENERAL_CONTROL_565_MODE_NOTSEL 0x00000000 /* RWI-V */ + #define NV_PRAMDAC_GENERAL_CONTROL_565_MODE_SEL 0x00000001 /* RW--V */ + #define NV_PRAMDAC_GENERAL_CONTROL_BLK_PEDSTL 16:16 /* RWIVF */ + #define NV_PRAMDAC_GENERAL_CONTROL_BLK_PEDSTL_OFF 0x00000000 /* RWI-V */ + #define NV_PRAMDAC_GENERAL_CONTROL_BLK_PEDSTL_ON 0x00000001 /* RW--V */ + #define NV_PRAMDAC_GENERAL_CONTROL_TERMINATION 17:17 /* RWIVF */ + #define NV_PRAMDAC_GENERAL_CONTROL_TERMINATION_37OHM 0x00000000 /* RWI-V */ + #define NV_PRAMDAC_GENERAL_CONTROL_TERMINATION_75OHM 0x00000001 /* RW--V */ + #define NV_PRAMDAC_GENERAL_CONTROL_BPC 20:20 /* RWIVF */ + #define NV_PRAMDAC_GENERAL_CONTROL_BPC_6BITS 0x00000000 /* RWI-V */ + #define NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS 0x00000001 /* RW--V */ + #define NV_PRAMDAC_GENERAL_CONTROL_DAC_SLEEP 24:24 /* RWIVF */ + #define NV_PRAMDAC_GENERAL_CONTROL_DAC_SLEEP_DIS 0x00000000 /* RWI-V */ + #define NV_PRAMDAC_GENERAL_CONTROL_DAC_SLEEP_EN 0x00000001 /* RW--V */ + #define NV_PRAMDAC_GENERAL_CONTROL_PALETTE_CLK 28:28 /* RWIVF */ + #define NV_PRAMDAC_GENERAL_CONTROL_PALETTE_CLK_EN 0x00000000 /* RWI-V */ + #define NV_PRAMDAC_GENERAL_CONTROL_PALETTE_CLK_DIS 0x00000001 /* RW--V */ + + + #define NV_PRAMDAC_GRCURSOR_START_POS 0x00680300 /* RW-4R */ + #define NV_PRAMDAC_GRCURSOR_START_POS_X 11:0 /* RWXSF */ + #define NV_PRAMDAC_GRCURSOR_START_POS_Y 27:16 /* RWXSF */ + + #define NV_PMC 0x00000FFF:0x00000000 /* RW--D */ + #define NV_PMC_INTR_0 0x00000100 /* RW-4R */ + #define NV_PMC_INTR_0_PAUDIO 0:0 /* R--VF */ + #define NV_PMC_INTR_0_PAUDIO_NOT_PENDING 0x00000000 /* R---V */ + #define NV_PMC_INTR_0_PAUDIO_PENDING 0x00000001 /* R---V */ + #define NV_PMC_INTR_0_PMEDIA 4:4 /* R--VF */ + #define NV_PMC_INTR_0_PMEDIA_NOT_PENDING 0x00000000 /* R---V */ + #define NV_PMC_INTR_0_PMEDIA_PENDING 0x00000001 /* R---V */ + #define NV_PMC_INTR_0_PFIFO 8:8 /* R--VF */ + #define NV_PMC_INTR_0_PFIFO_NOT_PENDING 0x00000000 /* R---V */ + #define NV_PMC_INTR_0_PFIFO_PENDING 0x00000001 /* R---V */ + #define NV_PMC_INTR_0_PGRAPH0 12:12 /* R--VF */ + #define NV_PMC_INTR_0_PGRAPH0_NOT_PENDING 0x00000000 /* R---V */ + #define NV_PMC_INTR_0_PGRAPH0_PENDING 0x00000001 /* R---V */ + #define NV_PMC_INTR_0_PGRAPH1 13:13 /* R--VF */ + #define NV_PMC_INTR_0_PGRAPH1_NOT_PENDING 0x00000000 /* R---V */ + #define NV_PMC_INTR_0_PGRAPH1_PENDING 0x00000001 /* R---V */ + #define NV_PMC_INTR_0_PVIDEO 16:16 /* R--VF */ + #define NV_PMC_INTR_0_PVIDEO_NOT_PENDING 0x00000000 /* R---V */ + #define NV_PMC_INTR_0_PVIDEO_PENDING 0x00000001 /* R---V */ + #define NV_PMC_INTR_0_PTIMER 20:20 /* R--VF */ + #define NV_PMC_INTR_0_PTIMER_NOT_PENDING 0x00000000 /* R---V */ + #define NV_PMC_INTR_0_PTIMER_PENDING 0x00000001 /* R---V */ + #define NV_PMC_INTR_0_PFB 24:24 /* R--VF */ + #define NV_PMC_INTR_0_PFB_NOT_PENDING 0x00000000 /* R---V */ + #define NV_PMC_INTR_0_PFB_PENDING 0x00000001 /* R---V */ + #define NV_PMC_INTR_0_PBUS 28:28 /* R--VF */ + #define NV_PMC_INTR_0_PBUS_NOT_PENDING 0x00000000 /* R---V */ + #define NV_PMC_INTR_0_PBUS_PENDING 0x00000001 /* R---V */ + #define NV_PMC_INTR_0_SOFTWARE 31:31 /* RWIVF */ + #define NV_PMC_INTR_0_SOFTWARE_NOT_PENDING 0x00000000 /* RWI-V */ + #define NV_PMC_INTR_0_SOFTWARE_PENDING 0x00000001 /* RW--V */ + + #define NV_PMC_INTR_EN_0 0x00000140 /* RW-4R */ + #define NV_PMC_INTR_EN_0_INTA 1:0 /* RWIVF */ + #define NV_PMC_INTR_EN_0_INTA_DISABLED 0x00000000 /* RWI-V */ + #define NV_PMC_INTR_EN_0_INTA_HARDWARE 0x00000001 /* RW--V */ + #define NV_PMC_INTR_EN_0_INTA_SOFTWARE 0x00000002 /* RW--V */ + + #define NV_PMC_ENABLE 0x00000200 /* RW-4R */ + + #define NV_PFIFO 0x00003FFF:0x00002000 /* RW--D */ + #define NV_PFIFO_INTR_0 0x00002100 /* RW-4R */ + #define NV_PFIFO_INTR_0_CACHE_ERROR 0:0 /* RWXVF */ + #define NV_PFIFO_INTR_0_CACHE_ERROR_NOT_PENDING 0x00000000 /* R---V */ + #define NV_PFIFO_INTR_0_CACHE_ERROR_PENDING 0x00000001 /* R---V */ + #define NV_PFIFO_INTR_0_CACHE_ERROR_RESET 0x00000001 /* -W--V */ + #define NV_PFIFO_INTR_0_RUNOUT 4:4 /* RWXVF */ + #define NV_PFIFO_INTR_0_RUNOUT_NOT_PENDING 0x00000000 /* R---V */ + #define NV_PFIFO_INTR_0_RUNOUT_PENDING 0x00000001 /* R---V */ + #define NV_PFIFO_INTR_0_RUNOUT_RESET 0x00000001 /* -W--V */ + #define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW 8:8 /* RWXVF */ + #define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW_NOT_PENDING 0x00000000 /* R---V */ + #define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW_PENDING 0x00000001 /* R---V */ + #define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW_RESET 0x00000001 /* -W--V */ + #define NV_PFIFO_INTR_0_DMA_PUSHER 12:12 /* RWXVF */ + #define NV_PFIFO_INTR_0_DMA_PUSHER_NOT_PENDING 0x00000000 /* R---V */ + #define NV_PFIFO_INTR_0_DMA_PUSHER_PENDING 0x00000001 /* R---V */ + #define NV_PFIFO_INTR_0_DMA_PUSHER_RESET 0x00000001 /* -W--V */ + #define NV_PFIFO_INTR_0_DMA_PTE 16:16 /* RWXVF */ + #define NV_PFIFO_INTR_0_DMA_PTE_NOT_PENDING 0x00000000 /* R---V */ + #define NV_PFIFO_INTR_0_DMA_PTE_PENDING 0x00000001 /* R---V */ + #define NV_PFIFO_INTR_0_DMA_PTE_RESET 0x00000001 /* -W--V */ + #define NV_PFIFO_INTR_EN_0 0x00002140 /* RW-4R */ + #define NV_PFIFO_INTR_EN_0_CACHE_ERROR 0:0 /* RWIVF */ + #define NV_PFIFO_INTR_EN_0_CACHE_ERROR_DISABLED 0x00000000 /* RWI-V */ + #define NV_PFIFO_INTR_EN_0_CACHE_ERROR_ENABLED 0x00000001 /* RW--V */ + #define NV_PFIFO_INTR_EN_0_RUNOUT 4:4 /* RWIVF */ + #define NV_PFIFO_INTR_EN_0_RUNOUT_DISABLED 0x00000000 /* RWI-V */ + #define NV_PFIFO_INTR_EN_0_RUNOUT_ENABLED 0x00000001 /* RW--V */ + #define NV_PFIFO_INTR_EN_0_RUNOUT_OVERFLOW 8:8 /* RWIVF */ + #define NV_PFIFO_INTR_EN_0_RUNOUT_OVERFLOW_DISABLED 0x00000000 /* RWI-V */ + #define NV_PFIFO_INTR_EN_0_RUNOUT_OVERFLOW_ENABLED 0x00000001 /* RW--V */ + #define NV_PFIFO_CONFIG_0 0x00002200 /* RW-4R */ + #define NV_PFIFO_RAMHT 0x00002210 /* RW-4R */ + #define NV_PFIFO_RAMHT_BASE_ADDRESS 15:12 /* RWXVF */ + #define NV_PFIFO_RAMHT_SIZE 17:16 /* RWXVF */ + #define NV_PFIFO_RAMHT_SIZE_4K 0x00000000 /* RWI-V */ + #define NV_PFIFO_RAMHT_SIZE_8K 0x00000001 /* RW--V */ + #define NV_PFIFO_RAMHT_SIZE_16K 0x00000002 /* RW--V */ + #define NV_PFIFO_RAMHT_SIZE_32K 0x00000003 /* RW--V */ + #define NV_PFIFO_RAMFC 0x00002214 /* RW-4R */ + #define NV_PFIFO_RAMFC_BASE_ADDRESS 15:9 /* RWXVF */ + #define NV_PFIFO_RAMRO 0x00002218 /* RW-4R */ + #define NV_PFIFO_RAMRO_BASE_ADDRESS 15:9 /* RWXVF */ + #define NV_PFIFO_RAMRO_SIZE 16:16 /* RWXVF */ + #define NV_PFIFO_RAMRO_SIZE_512 0x00000000 /* RWI-V */ + #define NV_PFIFO_RAMRO_SIZE_8K 0x00000001 /* RW--V */ + #define NV_PFIFO_CACHES 0x00002500 /* RW-4R */ + #define NV_PFIFO_CACHES_REASSIGN 0:0 /* RWIVF */ + #define NV_PFIFO_CACHES_REASSIGN_DISABLED 0x00000000 /* RWI-V */ + #define NV_PFIFO_CACHES_REASSIGN_ENABLED 0x00000001 /* RW--V */ + #define NV_PFIFO_CACHE0_PUSH0 0x00003000 /* RW-4R */ + #define NV_PFIFO_CACHE0_PUSH0_ACCESS 0:0 /* RWIVF */ + #define NV_PFIFO_CACHE0_PUSH0_ACCESS_DISABLED 0x00000000 /* RWI-V */ + #define NV_PFIFO_CACHE0_PUSH0_ACCESS_ENABLED 0x00000001 /* RW--V */ + #define NV_PFIFO_CACHE1_PUSH0 0x00003200 /* RW-4R */ + #define NV_PFIFO_CACHE1_PUSH0_ACCESS 0:0 /* RWIVF */ + #define NV_PFIFO_CACHE1_PUSH0_ACCESS_DISABLED 0x00000000 /* RWI-V */ + #define NV_PFIFO_CACHE1_PUSH0_ACCESS_ENABLED 0x00000001 /* RW--V */ + #define NV_PFIFO_CACHE0_PUSH1 0x00003004 /* RW-4R */ + #define NV_PFIFO_CACHE0_PUSH1_CHID 6:0 /* RWXUF */ + #define NV_PFIFO_CACHE1_PUSH1 0x00003204 /* RW-4R */ + #define NV_PFIFO_CACHE1_PUSH1_CHID 6:0 /* RWXUF */ + #define NV_PFIFO_CACHE1_DMA0 0x00003220 /* RW-4R */ + #define NV_PFIFO_CACHE1_DMA1 0x00003224 /* RW-4R */ + #define NV_PFIFO_CACHE1_DMA2 0x00003228 /* RW-4R */ + #define NV_PFIFO_CACHE0_PULL0 0x00003040 /* RW-4R */ + #define NV_PFIFO_CACHE0_PULL0_ACCESS 0:0 /* RWIVF */ + #define NV_PFIFO_CACHE0_PULL0_ACCESS_DISABLED 0x00000000 /* RWI-V */ + #define NV_PFIFO_CACHE0_PULL0_ACCESS_ENABLED 0x00000001 /* RW--V */ + #define NV_PFIFO_CACHE1_PULL0 0x00003240 /* RW-4R */ + #define NV_PFIFO_CACHE1_PULL0_ACCESS 0:0 /* RWIVF */ + #define NV_PFIFO_CACHE1_PULL0_ACCESS_DISABLED 0x00000000 /* RWI-V */ + #define NV_PFIFO_CACHE1_PULL0_ACCESS_ENABLED 0x00000001 /* RW--V */ + #define NV_PFIFO_CACHE1_PULL1 0x00003250 /* RW-4R */ + #define NV_PFIFO_CACHE1_PULL1_CTX 4:4 /* RWXVF */ + #define NV_PFIFO_CACHE1_PULL1_CTX_CLEAN 0x00000000 /* RW--V */ + #define NV_PFIFO_CACHE1_PULL1_CTX_DIRTY 0x00000001 /* RW--V */ + #define NV_PFIFO_CACHE1_PUT 0x00003210 /* RW-4R */ + #define NV_PFIFO_CACHE1_PUT_ADDRESS 6:2 /* RWXUF */ + #define NV_PFIFO_CACHE1_GET 0x00003270 /* RW-4R */ + #define NV_PFIFO_CACHE1_GET_ADDRESS 6:2 /* RWXUF */ + #define NV_PFIFO_CACHE1_CTX(i) (0x00003280+(i)*16) /* RW-4A */ + #define NV_PFIFO_CACHE1_CTX__SIZE_1 8 /* */ + #define NV_PFIFO_RUNOUT_PUT 0x00002410 /* RW-4R */ + #define NV_PFIFO_RUNOUT_GET 0x00002420 /* RW-4R */ + #define NV_PFIFO_RUNOUT_STATUS 0x00002400 /* R--4R */ + + #define NV_PGRAPH 0x00401FFF:0x00400000 /* RW--D */ + #define NV_PGRAPH_DEBUG_0 0x00400080 /* RW-4R */ + #define NV_PGRAPH_DEBUG_0_STATE 0:0 /* CW-VF */ + #define NV_PGRAPH_DEBUG_0_STATE_NORMAL 0x00000000 /* CW--V */ + #define NV_PGRAPH_DEBUG_0_STATE_RESET 0x00000001 /* -W--V */ + #define NV_PGRAPH_DEBUG_0_BULK_READS 4:4 /* RWIVF */ + #define NV_PGRAPH_DEBUG_0_BULK_READS_DISABLED 0x00000000 /* RWI-V */ + #define NV_PGRAPH_DEBUG_0_BULK_READS_ENABLED 0x00000001 /* RW--V */ + #define NV_PGRAPH_DEBUG_0_WRITE_ONLY_ROPS_2D 20:20 /* RWIVF */ + #define NV_PGRAPH_DEBUG_0_WRITE_ONLY_ROPS_2D_DISABLED 0x00000000 /* RWI-V */ + #define NV_PGRAPH_DEBUG_0_WRITE_ONLY_ROPS_2D_ENABLED 0x00000001 /* RW--V */ + #define NV_PGRAPH_DEBUG_0_DRAWDIR_AUTO 24:24 /* RWIVF */ + #define NV_PGRAPH_DEBUG_0_DRAWDIR_AUTO_DISABLED 0x00000000 /* RWI-V */ + #define NV_PGRAPH_DEBUG_0_DRAWDIR_AUTO_ENABLED 0x00000001 /* RW--V */ + #define NV_PGRAPH_DEBUG_1 0x00400084 /* RW-4R */ + #define NV_PGRAPH_DEBUG_1_VOLATILE_RESET 0:0 /* RWIVF */ + #define NV_PGRAPH_DEBUG_1_VOLATILE_RESET_NOT_LAST 0x00000000 /* RWI-V */ + #define NV_PGRAPH_DEBUG_1_VOLATILE_RESET_LAST 0x00000001 /* RW--V */ + #define NV_PGRAPH_DEBUG_1_INSTANCE 16:16 /* RWIVF */ + #define NV_PGRAPH_DEBUG_1_INSTANCE_DISABLED 0x00000000 /* RWI-V */ + #define NV_PGRAPH_DEBUG_1_INSTANCE_ENABLED 0x00000001 /* RW--V */ + #define NV_PGRAPH_DEBUG_1_CTX 20:20 /* RWIVF */ + #define NV_PGRAPH_DEBUG_1_CTX_DISABLED 0x00000000 /* RWI-V */ + #define NV_PGRAPH_DEBUG_1_CTX_ENABLED 0x00000001 /* RW--V */ + #define NV_PGRAPH_DEBUG_2 0x00400088 /* RW-4R */ + #define NV_PGRAPH_DEBUG_2_AVOID_RMW_BLEND 0:0 /* RWIVF */ + #define NV_PGRAPH_DEBUG_2_AVOID_RMW_BLEND_DISABLED 0x00000000 /* RWI-V */ + #define NV_PGRAPH_DEBUG_2_AVOID_RMW_BLEND_ENABLED 0x00000001 /* RW--V */ + #define NV_PGRAPH_DEBUG_2_DPWR_FIFO 8:8 /* RWIVF */ + #define NV_PGRAPH_DEBUG_2_DPWR_FIFO_DISABLED 0x00000000 /* RWI-V */ + #define NV_PGRAPH_DEBUG_2_DPWR_FIFO_ENABLED 0x00000001 /* RW--V */ + #define NV_PGRAPH_DEBUG_2_VOLATILE_RESET 28:28 /* RWIVF */ + #define NV_PGRAPH_DEBUG_2_VOLATILE_RESET_DISABLED 0x00000000 /* RWI-V */ + #define NV_PGRAPH_DEBUG_2_VOLATILE_RESET_ENABLED 0x00000001 /* RW--V */ + #define NV_PGRAPH_DEBUG_3 0x0040008C /* RW-4R */ + #define NV_PGRAPH_DEBUG_3_HONOR_ALPHA 24:24 /* RWIVF */ + #define NV_PGRAPH_DEBUG_3_HONOR_ALPHA_DISABLED 0x00000000 /* RWI-V */ + #define NV_PGRAPH_DEBUG_3_HONOR_ALPHA_ENABLED 0x00000001 /* RW--V */ + + #define NV_PGRAPH_INTR_0 0x00400100 /* RW-4R */ + #define NV_PGRAPH_INTR_0_RESERVED 0:0 /* RW-VF */ + #define NV_PGRAPH_INTR_0_RESERVED_NOT_PENDING 0x00000000 /* R---V */ + #define NV_PGRAPH_INTR_0_RESERVED_PENDING 0x00000001 /* R---V */ + #define NV_PGRAPH_INTR_0_RESERVED_RESET 0x00000001 /* -W--V */ + #define NV_PGRAPH_INTR_0_CONTEXT_SWITCH 4:4 /* RWIVF */ + #define NV_PGRAPH_INTR_0_CONTEXT_SWITCH_NOT_PENDING 0x00000000 /* R-I-V */ + #define NV_PGRAPH_INTR_0_CONTEXT_SWITCH_PENDING 0x00000001 /* R---V */ + #define NV_PGRAPH_INTR_0_CONTEXT_SWITCH_RESET 0x00000001 /* -W--V */ + #define NV_PGRAPH_INTR_0_VBLANK 8:8 /* RWIVF */ + #define NV_PGRAPH_INTR_0_VBLANK_NOT_PENDING 0x00000000 /* R-I-V */ + #define NV_PGRAPH_INTR_0_VBLANK_PENDING 0x00000001 /* R---V */ + #define NV_PGRAPH_INTR_0_VBLANK_RESET 0x00000001 /* -W--V */ + #define NV_PGRAPH_INTR_0_RANGE 12:12 /* RWIVF */ + #define NV_PGRAPH_INTR_0_RANGE_NOT_PENDING 0x00000000 /* R-I-V */ + #define NV_PGRAPH_INTR_0_RANGE_PENDING 0x00000001 /* R---V */ + #define NV_PGRAPH_INTR_0_RANGE_RESET 0x00000001 /* -W--V */ + #define NV_PGRAPH_INTR_0_METHOD_COUNT 16:16 /* RWIVF */ + #define NV_PGRAPH_INTR_0_METHOD_COUNT_NOT_PENDING 0x00000000 /* R-I-V */ + #define NV_PGRAPH_INTR_0_METHOD_COUNT_PENDING 0x00000001 /* R---V */ + #define NV_PGRAPH_INTR_0_METHOD_COUNT_RESET 0x00000001 /* -W--V */ + #define NV_PGRAPH_INTR_0_FORMAT 20:20 /* RWIVF */ + #define NV_PGRAPH_INTR_0_FORMAT_NOT_PENDING 0x00000000 /* R-I-V */ + #define NV_PGRAPH_INTR_0_FORMAT_PENDING 0x00000001 /* R---V */ + #define NV_PGRAPH_INTR_0_FORMAT_RESET 0x00000001 /* -W--V */ + #define NV_PGRAPH_INTR_0_COMPLEX_CLIP 24:24 /* RWIVF */ + #define NV_PGRAPH_INTR_0_COMPLEX_CLIP_NOT_PENDING 0x00000000 /* R-I-V */ + #define NV_PGRAPH_INTR_0_COMPLEX_CLIP_PENDING 0x00000001 /* R---V */ + #define NV_PGRAPH_INTR_0_COMPLEX_CLIP_RESET 0x00000001 /* -W--V */ + #define NV_PGRAPH_INTR_0_NOTIFY 28:28 /* RWIVF */ + #define NV_PGRAPH_INTR_0_NOTIFY_NOT_PENDING 0x00000000 /* R-I-V */ + #define NV_PGRAPH_INTR_0_NOTIFY_PENDING 0x00000001 /* R---V */ + #define NV_PGRAPH_INTR_0_NOTIFY_RESET 0x00000001 /* -W--V */ + + #define NV_PGRAPH_INTR_1 0x00400104 /* RW-4R */ + #define NV_PGRAPH_INTR_1_METHOD 0:0 /* RWIVF */ + #define NV_PGRAPH_INTR_1_METHOD_NOT_PENDING 0x00000000 /* R-I-V */ + #define NV_PGRAPH_INTR_1_METHOD_PENDING 0x00000001 /* R---V */ + #define NV_PGRAPH_INTR_1_METHOD_RESET 0x00000001 /* -W--V */ + #define NV_PGRAPH_INTR_1_DATA 4:4 /* RWIVF */ + #define NV_PGRAPH_INTR_1_DATA_NOT_PENDING 0x00000000 /* R-I-V */ + #define NV_PGRAPH_INTR_1_DATA_PENDING 0x00000001 /* R---V */ + #define NV_PGRAPH_INTR_1_DATA_RESET 0x00000001 /* -W--V */ + #define NV_PGRAPH_INTR_1_DOUBLE_NOTIFY 12:12 /* RWIVF */ + #define NV_PGRAPH_INTR_1_DOUBLE_NOTIFY_NOT_PENDING 0x00000000 /* R-I-V */ + #define NV_PGRAPH_INTR_1_DOUBLE_NOTIFY_PENDING 0x00000001 /* R---V */ + #define NV_PGRAPH_INTR_1_DOUBLE_NOTIFY_RESET 0x00000001 /* -W--V */ + #define NV_PGRAPH_INTR_1_CTXSW_NOTIFY 16:16 /* RWIVF */ + #define NV_PGRAPH_INTR_1_CTXSW_NOTIFY_NOT_PENDING 0x00000000 /* R-I-V */ + #define NV_PGRAPH_INTR_1_CTXSW_NOTIFY_PENDING 0x00000001 /* R---V */ + #define NV_PGRAPH_INTR_1_CTXSW_NOTIFY_RESET 0x00000001 /* -W--V */ + + #define NV_PGRAPH_INTR_EN_0 0x00400140 /* RW-4R */ + + #define NV_PGRAPH_INTR_EN_1 0x00400144 /* RW-4R */ + + #define NV_PGRAPH_CTX_CACHE(i) (0x004001a0+(i)*4) /* RW-4A */ + #define NV_PGRAPH_CTX_CACHE__SIZE_1 8 /* */ + + #define NV_PGRAPH_CTX_SWITCH 0x00400180 /* RW-4R */ + + #define NV_PGRAPH_CTX_CONTROL 0x00400190 /* RW-4R */ + #define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME 1:0 /* RWIVF */ + #define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME_33US 0x00000000 /* RWI-V */ + #define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME_262US 0x00000001 /* RW--V */ + #define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME_2MS 0x00000002 /* RW--V */ + #define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME_17MS 0x00000003 /* RW--V */ + #define NV_PGRAPH_CTX_CONTROL_TIME 8:8 /* RWIVF */ + #define NV_PGRAPH_CTX_CONTROL_TIME_EXPIRED 0x00000000 /* RWI-V */ + #define NV_PGRAPH_CTX_CONTROL_TIME_NOT_EXPIRED 0x00000001 /* RW--V */ + #define NV_PGRAPH_CTX_CONTROL_CHID 16:16 /* RWIVF */ + #define NV_PGRAPH_CTX_CONTROL_CHID_INVALID 0x00000000 /* RWI-V */ + #define NV_PGRAPH_CTX_CONTROL_CHID_VALID 0x00000001 /* RW--V */ + #define NV_PGRAPH_CTX_CONTROL_SWITCH 20:20 /* R--VF */ + #define NV_PGRAPH_CTX_CONTROL_SWITCH_UNAVAILABLE 0x00000000 /* R---V */ + #define NV_PGRAPH_CTX_CONTROL_SWITCH_AVAILABLE 0x00000001 /* R---V */ + #define NV_PGRAPH_CTX_CONTROL_SWITCHING 24:24 /* RWIVF */ + #define NV_PGRAPH_CTX_CONTROL_SWITCHING_IDLE 0x00000000 /* RWI-V */ + #define NV_PGRAPH_CTX_CONTROL_SWITCHING_BUSY 0x00000001 /* RW--V */ + #define NV_PGRAPH_CTX_CONTROL_DEVICE 28:28 /* RWIVF */ + #define NV_PGRAPH_CTX_CONTROL_DEVICE_DISABLED 0x00000000 /* RWI-V */ + #define NV_PGRAPH_CTX_CONTROL_DEVICE_ENABLED 0x00000001 /* RW--V */ + + #define NV_PGRAPH_CTX_USER 0x00400194 /* RW-4R */ + + #define NV_PGRAPH_FIFO 0x004006A4 /* RW-4R */ + #define NV_PGRAPH_FIFO_ACCESS 0:0 /* RWIVF */ + #define NV_PGRAPH_FIFO_ACCESS_DISABLED 0x00000000 /* RW--V */ + #define NV_PGRAPH_FIFO_ACCESS_ENABLED 0x00000001 /* RWI-V */ + + #define NV_PGRAPH_STATUS 0x004006B0 /* R--4R */ + + #define NV_PGRAPH_CLIP_MISC 0x004006A0 /* RW-4R */ + #define NV_PGRAPH_SRC_CANVAS_MIN 0x00400550 /* RW-4R */ + #define NV_PGRAPH_DST_CANVAS_MIN 0x00400558 /* RW-4R */ + #define NV_PGRAPH_SRC_CANVAS_MAX 0x00400554 /* RW-4R */ + #define NV_PGRAPH_DST_CANVAS_MAX 0x0040055C /* RW-4R */ + #define NV_PGRAPH_CLIP0_MIN 0x00400690 /* RW-4R */ + #define NV_PGRAPH_CLIP1_MIN 0x00400698 /* RW-4R */ + #define NV_PGRAPH_CLIP0_MAX 0x00400694 /* RW-4R */ + #define NV_PGRAPH_CLIP1_MAX 0x0040069C /* RW-4R */ + #define NV_PGRAPH_DMA 0x00400680 /* RW-4R */ + #define NV_PGRAPH_NOTIFY 0x00400684 /* RW-4R */ + #define NV_PGRAPH_INSTANCE 0x00400688 /* RW-4R */ + #define NV_PGRAPH_MEMFMT 0x0040068C /* RW-4R */ + #define NV_PGRAPH_BOFFSET0 0x00400630 /* RW-4R */ + #define NV_PGRAPH_BOFFSET1 0x00400634 /* RW-4R */ + #define NV_PGRAPH_BOFFSET2 0x00400638 /* RW-4R */ + #define NV_PGRAPH_BOFFSET3 0x0040063C /* RW-4R */ + #define NV_PGRAPH_BPITCH0 0x00400650 /* RW-4R */ + #define NV_PGRAPH_BPITCH1 0x00400654 /* RW-4R */ + #define NV_PGRAPH_BPITCH2 0x00400658 /* RW-4R */ + #define NV_PGRAPH_BPITCH3 0x0040065C /* RW-4R */ + + #define NV_PGRAPH_BPIXEL 0x004006a8 /* RW-4R */ + #define NV_PGRAPH_BPIXEL_DEPTH0_FMT 1:0 /* RWXVF */ + #define NV_PGRAPH_BPIXEL_DEPTH0_FMT_Y16_BITS 0x00000000 /* RW--V */ + #define NV_PGRAPH_BPIXEL_DEPTH0_FMT_BITS_8 0x00000001 /* RW--V */ + #define NV_PGRAPH_BPIXEL_DEPTH0_FMT_BITS_16 0x00000002 /* RW--V */ + #define NV_PGRAPH_BPIXEL_DEPTH0_FMT_BITS_32 0x00000003 /* RW--V */ + #define NV_PGRAPH_BPIXEL_DEPTH0 2:2 /* RWXVF */ + #define NV_PGRAPH_BPIXEL_DEPTH0_NOT_VALID 0x00000000 /* RW--V */ + #define NV_PGRAPH_BPIXEL_DEPTH0_VALID 0x00000001 /* RW--V */ + #define NV_PGRAPH_BPIXEL_DEPTH1_FMT 5:4 /* RWXVF */ + #define NV_PGRAPH_BPIXEL_DEPTH1_FMT_Y16_BITS 0x00000000 /* RW--V */ + #define NV_PGRAPH_BPIXEL_DEPTH1_FMT_BITS_8 0x00000001 /* RW--V */ + #define NV_PGRAPH_BPIXEL_DEPTH1_FMT_BITS_16 0x00000002 /* RW--V */ + #define NV_PGRAPH_BPIXEL_DEPTH1_FMT_BITS_32 0x00000003 /* RW--V */ + #define NV_PGRAPH_BPIXEL_DEPTH1 6:6 /* RWXVF */ + #define NV_PGRAPH_BPIXEL_DEPTH1_NOT_VALID 0x00000000 /* RW--V */ + #define NV_PGRAPH_BPIXEL_DEPTH1_VALID 0x00000001 /* RW--V */ + #define NV_PGRAPH_BPIXEL_DEPTH2_FMT 9:8 /* RWXVF */ + #define NV_PGRAPH_BPIXEL_DEPTH2_FMT_Y16_BITS 0x00000000 /* RW--V */ + #define NV_PGRAPH_BPIXEL_DEPTH2_FMT_BITS_8 0x00000001 /* RW--V */ + #define NV_PGRAPH_BPIXEL_DEPTH2_FMT_BITS_16 0x00000002 /* RW--V */ + #define NV_PGRAPH_BPIXEL_DEPTH2_FMT_BITS_32 0x00000003 /* RW--V */ + #define NV_PGRAPH_BPIXEL_DEPTH2 10:10 /* RWXVF */ + #define NV_PGRAPH_BPIXEL_DEPTH2_NOT_VALID 0x00000000 /* RW--V */ + #define NV_PGRAPH_BPIXEL_DEPTH2_VALID 0x00000001 /* RW--V */ + #define NV_PGRAPH_BPIXEL_DEPTH3_FMT 13:12 /* RWXVF */ + #define NV_PGRAPH_BPIXEL_DEPTH3_FMT_Y16_BITS 0x00000000 /* RW--V */ + #define NV_PGRAPH_BPIXEL_DEPTH3_FMT_BITS_8 0x00000001 /* RW--V */ + #define NV_PGRAPH_BPIXEL_DEPTH3_FMT_BITS_16 0x00000002 /* RW--V */ + #define NV_PGRAPH_BPIXEL_DEPTH3_FMT_BITS_32 0x00000003 /* RW--V */ + #define NV_PGRAPH_BPIXEL_DEPTH3 14:14 /* RWXVF */ + #define NV_PGRAPH_BPIXEL_DEPTH3_NOT_VALID 0x00000000 /* RW--V */ + #define NV_PGRAPH_BPIXEL_DEPTH3_VALID 0x00000001 /* RW--V */ + + #define NV_PGRAPH_PATT_COLOR0_0 0x00400600 /* RW-4R */ + #define NV_PGRAPH_PATT_COLOR0_1 0x00400604 /* RW-4R */ + #define NV_PGRAPH_PATT_COLOR1_0 0x00400608 /* RW-4R */ + #define NV_PGRAPH_PATT_COLOR1_1 0x0040060C /* RW-4R */ + #define NV_PGRAPH_PATTERN(i) (0x00400610+(i)*4) /* RW-4A */ + #define NV_PGRAPH_PATTERN_SHAPE 0x00400618 /* RW-4R */ + #define NV_PGRAPH_PATTERN_SHAPE_VALUE 1:0 /* RWXVF */ + #define NV_PGRAPH_PATTERN_SHAPE_VALUE_8X8 0x00000000 /* RW--V */ + #define NV_PGRAPH_PATTERN_SHAPE_VALUE_64X1 0x00000001 /* RW--V */ + #define NV_PGRAPH_PATTERN_SHAPE_VALUE_1X64 0x00000002 /* RW--V */ + #define NV_PGRAPH_MONO_COLOR0 0x0040061C /* RW-4R */ + #define NV_PGRAPH_ROP3 0x00400624 /* RW-4R */ + #define NV_PGRAPH_PLANE_MASK 0x00400628 /* RW-4R */ + #define NV_PGRAPH_CHROMA 0x0040062C /* RW-4R */ + #define NV_PGRAPH_BETA 0x00400640 /* RW-4R */ + #define NV_PGRAPH_CONTROL_OUT 0x00400644 /* RW-4R */ + #define NV_PGRAPH_ABS_X_RAM(i) (0x00400400+(i)*4) /* RW-4A */ + #define NV_PGRAPH_ABS_X_RAM__SIZE_1 32 /* */ + #define NV_PGRAPH_ABS_Y_RAM(i) (0x00400480+(i)*4) /* RW-4A */ + #define NV_PGRAPH_ABS_Y_RAM__SIZE_1 32 /* */ + + #define NV_PGRAPH_XY_LOGIC_MISC0 0x00400514 /* RW-4R */ + #define NV_PGRAPH_XY_LOGIC_MISC1 0x00400518 /* RW-4R */ + #define NV_PGRAPH_XY_LOGIC_MISC2 0x0040051C /* RW-4R */ + #define NV_PGRAPH_XY_LOGIC_MISC1_DVDY_VALUE 0x00000000 /* RWI-V */ + #define NV_PGRAPH_XY_LOGIC_MISC3 0x00400520 /* RW-4R */ + #define NV_PGRAPH_X_MISC 0x00400500 /* RW-4R */ + #define NV_PGRAPH_Y_MISC 0x00400504 /* RW-4R */ + #define NV_PGRAPH_ABS_UCLIP_XMIN 0x0040053C /* RW-4R */ + #define NV_PGRAPH_ABS_UCLIP_XMAX 0x00400544 /* RW-4R */ + #define NV_PGRAPH_ABS_UCLIP_YMIN 0x00400540 /* RW-4R */ + #define NV_PGRAPH_ABS_UCLIP_YMAX 0x00400548 /* RW-4R */ + #define NV_PGRAPH_ABS_UCLIPA_XMIN 0x00400560 /* RW-4R */ + #define NV_PGRAPH_ABS_UCLIPA_XMAX 0x00400568 /* RW-4R */ + #define NV_PGRAPH_ABS_UCLIPA_YMIN 0x00400564 /* RW-4R */ + #define NV_PGRAPH_ABS_UCLIPA_YMAX 0x0040056C /* RW-4R */ + #define NV_PGRAPH_SOURCE_COLOR 0x0040050C /* RW-4R */ + #define NV_PGRAPH_EXCEPTIONS 0x00400508 /* RW-4R */ + #define NV_PGRAPH_ABS_ICLIP_XMAX 0x00400534 /* RW-4R */ + #define NV_PGRAPH_ABS_ICLIP_YMAX 0x00400538 /* RW-4R */ + #define NV_PGRAPH_CLIPX_0 0x00400524 /* RW-4R */ + #define NV_PGRAPH_CLIPX_1 0x00400528 /* RW-4R */ + #define NV_PGRAPH_CLIPY_0 0x0040052c /* RW-4R */ + #define NV_PGRAPH_CLIPY_1 0x00400530 /* RW-4R */ + #define NV_PGRAPH_DMA_INTR_0 0x00401100 /* RW-4R */ + #define NV_PGRAPH_DMA_INTR_0_INSTANCE 0:0 /* RWXVF */ + #define NV_PGRAPH_DMA_INTR_0_INSTANCE_NOT_PENDING 0x00000000 /* R---V */ + #define NV_PGRAPH_DMA_INTR_0_INSTANCE_PENDING 0x00000001 /* R---V */ + #define NV_PGRAPH_DMA_INTR_0_INSTANCE_RESET 0x00000001 /* -W--V */ + #define NV_PGRAPH_DMA_INTR_0_PRESENT 4:4 /* RWXVF */ + #define NV_PGRAPH_DMA_INTR_0_PRESENT_NOT_PENDING 0x00000000 /* R---V */ + #define NV_PGRAPH_DMA_INTR_0_PRESENT_PENDING 0x00000001 /* R---V */ + #define NV_PGRAPH_DMA_INTR_0_PRESENT_RESET 0x00000001 /* -W--V */ + #define NV_PGRAPH_DMA_INTR_0_PROTECTION 8:8 /* RWXVF */ + #define NV_PGRAPH_DMA_INTR_0_PROTECTION_NOT_PENDING 0x00000000 /* R---V */ + #define NV_PGRAPH_DMA_INTR_0_PROTECTION_PENDING 0x00000001 /* R---V */ + #define NV_PGRAPH_DMA_INTR_0_PROTECTION_RESET 0x00000001 /* -W--V */ + #define NV_PGRAPH_DMA_INTR_0_LINEAR 12:12 /* RWXVF */ + #define NV_PGRAPH_DMA_INTR_0_LINEAR_NOT_PENDING 0x00000000 /* R---V */ + #define NV_PGRAPH_DMA_INTR_0_LINEAR_PENDING 0x00000001 /* R---V */ + #define NV_PGRAPH_DMA_INTR_0_LINEAR_RESET 0x00000001 /* -W--V */ + #define NV_PGRAPH_DMA_INTR_0_NOTIFY 16:16 /* RWXVF */ + #define NV_PGRAPH_DMA_INTR_0_NOTIFY_NOT_PENDING 0x00000000 /* R---V */ + #define NV_PGRAPH_DMA_INTR_0_NOTIFY_PENDING 0x00000001 /* R---V */ + #define NV_PGRAPH_DMA_INTR_0_NOTIFY_RESET 0x00000001 /* -W--V */ + #define NV_PGRAPH_DMA_INTR_EN_0 0x00401140 /* RW-4R */ + #define NV_PGRAPH_DMA_CONTROL 0x00401210 /* RW-4R */ + + #define NV_PFB 0x00100FFF:0x00100000 /* RW--D */ + #define NV_PFB_BOOT_0 0x00100000 /* RW-4R */ + #define NV_PFB_BOOT_0_RAM_AMOUNT 1:0 /* RWIVF */ + #define NV_PFB_BOOT_0_RAM_AMOUNT_1MB 0x00000000 /* RW--V */ + #define NV_PFB_BOOT_0_RAM_AMOUNT_2MB 0x00000001 /* RW--V */ + #define NV_PFB_BOOT_0_RAM_AMOUNT_4MB 0x00000002 /* RW--V */ + + #define NV_PFB_CONFIG_0 0x00100200 /* RW-4R */ + #define NV_PFB_CONFIG_0_RESOLUTION 5:0 /* RWIVF */ + #define NV_PFB_CONFIG_0_RESOLUTION_320_PIXELS 0x0000000a /* RW--V */ + #define NV_PFB_CONFIG_0_RESOLUTION_400_PIXELS 0x0000000d /* RW--V */ + #define NV_PFB_CONFIG_0_RESOLUTION_480_PIXELS 0x0000000f /* RW--V */ + #define NV_PFB_CONFIG_0_RESOLUTION_512_PIXELS 0x00000010 /* RW--V */ + #define NV_PFB_CONFIG_0_RESOLUTION_640_PIXELS 0x00000014 /* RW--V */ + #define NV_PFB_CONFIG_0_RESOLUTION_800_PIXELS 0x00000019 /* RW--V */ + #define NV_PFB_CONFIG_0_RESOLUTION_960_PIXELS 0x0000001e /* RW--V */ + #define NV_PFB_CONFIG_0_RESOLUTION_1024_PIXELS 0x00000020 /* RW--V */ + #define NV_PFB_CONFIG_0_RESOLUTION_1152_PIXELS 0x00000024 /* RW--V */ + #define NV_PFB_CONFIG_0_RESOLUTION_1280_PIXELS 0x00000028 /* RW--V */ + #define NV_PFB_CONFIG_0_RESOLUTION_1600_PIXELS 0x00000032 /* RW--V */ + #define NV_PFB_CONFIG_0_RESOLUTION_DEFAULT 0x00000014 /* RWI-V */ + #define NV_PFB_CONFIG_0_PIXEL_DEPTH 9:8 /* RWIVF */ + #define NV_PFB_CONFIG_0_PIXEL_DEPTH_8_BITS 0x00000001 /* RW--V */ + #define NV_PFB_CONFIG_0_PIXEL_DEPTH_16_BITS 0x00000002 /* RW--V */ + #define NV_PFB_CONFIG_0_PIXEL_DEPTH_32_BITS 0x00000003 /* RW--V */ + #define NV_PFB_CONFIG_0_PIXEL_DEPTH_DEFAULT 0x00000001 /* RWI-V */ + #define NV_PFB_CONFIG_0_TILING 12:12 /* RWIVF */ + #define NV_PFB_CONFIG_0_TILING_ENABLED 0x00000000 /* RW--V */ + #define NV_PFB_CONFIG_0_TILING_DISABLED 0x00000001 /* RWI-V */ + + + #define NV_PRAMIN 0x00FFFFFF:0x00C00000 + #define NV_PNVM 0x00BFFFFF:0x00800000 + #define NV_CHAN0 0x0080ffff:0x00800000 + + #define NV_UROP 0x00421FFF:0x00420000 /* -W--D */ + #define NV_UCHROMA 0x00431FFF:0x00430000 /* -W--D */ + #define NV_UPLANE 0x00441FFF:0x00440000 /* -W--D */ + #define NV_UCLIP 0x00451FFF:0x00450000 /* -W--D */ + #define NV_UPATT 0x00461FFF:0x00460000 /* -W--D */ + #define NV_ULINE 0x00491FFF:0x00490000 /* -W--D */ + #define NV_ULIN 0x004A1FFF:0x004A0000 /* -W--D */ + #define NV_UTRI 0x004B1FFF:0x004B0000 /* -W--D */ + #define NV_URECT 0x00471FFF:0x00470000 /* -W--D */ + #define NV_UBLIT 0x00501FFF:0x00500000 /* -W--D */ + #define NV_UBITMAP 0x00521FFF:0x00520000 /* -W--D */ + + + #endif *** /dev/null Tue Jun 30 11:50:12 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/nv3setup.c Fri Mar 6 16:52:05 1998 *************** *** 0 **** --- 1,733 ---- + /* $TOG: nv3setup.c /main/1 1998/03/06 16:53:43 kaleb $ */ + + + + /* + * Copyright 1996-1997 David J. McKay + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * DAVID J. MCKAY BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/nv3setup.c,v 1.1.2.4 1998/01/24 11:55:09 dawes Exp $ */ + + #include <stdlib.h> + + + #include "nvuser.h" + #include "nv3ref.h" + #include "nvreg.h" + + + typedef struct { + UINT32 id; + UINT32 context; + }HashTableEntry; + + #if 0 + typedef struct { + UINT32 context; /* Configuration for graphics pipe */ + UINT32 dmaNotifyInst; /* Pointers to DMA and notify instance data */ + UINT32 memFormatInst; /* Not sure what the hell this is */ + UINT32 unknown; /* Don't know what the 4th word does */ + }ObjInstEntry; + + /* Low level hardware representation of object */ + typedef struct { + HashTableEntry hash; + ObjInstEntry inst; + }NVObject; + #endif + + typedef struct { + char patchConfig; /* How H/W is configured */ + char zwrite; /* Write to Z buffer */ + char chroma; /* Chroma keying enabled */ + char plane; /* Plane mask enabled */ + char clip; /* User clip enabled */ + char colourFormat; /* 555RGB 888RGB etc */ + char alpha; /* Alpha enabled */ + }ObjectProperties; + + typedef struct { + int chid; /* Channel ID (always 0 in this driver) */ + int id; /* Unique number for this object */ + int device; /* Which hardware device this object will use */ + int instance; /* Instance number (if it has one) */ + ObjectProperties properties; /* Enabled for this object */ + }NVObject; + + extern int ErrorF(const char *fmt,...); + + #define Info ErrorF + + static int graphicsEngineOk; + + #define WaitForIdle() while(PGRAPH_Read(STATUS)&1) + + static void EnableOptimisations(void) + { + /* Forget about this for the moment */ + /* Most of the opts are to do with 3D anyway */ + + PGRAPH_Write(DEBUG_0,PGRAPH_Def(DEBUG_0_BULK_READS,ENABLED)| + PGRAPH_Def(DEBUG_0_WRITE_ONLY_ROPS_2D,ENABLED)| + PGRAPH_Def(DEBUG_0_DRAWDIR_AUTO,ENABLED)); + + PGRAPH_Write(DEBUG_1,PGRAPH_Def(DEBUG_1_INSTANCE,ENABLED)| + PGRAPH_Def(DEBUG_1_CTX,ENABLED)); + + PGRAPH_Write(DEBUG_2,PGRAPH_Def(DEBUG_2_DPWR_FIFO, ENABLED)| + PGRAPH_Def(DEBUG_2_VOLATILE_RESET,ENABLED)| + PGRAPH_Def(DEBUG_2_AVOID_RMW_BLEND,ENABLED)| + PGRAPH_Def(DEBUG_2_DPWR_FIFO,ENABLED)); + + PGRAPH_Write(DEBUG_3,PGRAPH_Def(DEBUG_3_HONOR_ALPHA, ENABLED)); + } + + static void InitDMAInstance(void) + { + PGRAPH_Write(DMA,0); + PGRAPH_Write(NOTIFY,0); + } + + + + static void DisableFifo(void) + { + /* Disable CACHE1 first */ + PFIFO_Write(CACHES,PFIFO_Def(CACHES_REASSIGN,DISABLED)); + PFIFO_Write(CACHE1_PUSH0,PFIFO_Def(CACHE1_PUSH0_ACCESS,DISABLED)); + PFIFO_Write(CACHE1_PULL0,PFIFO_Def(CACHE1_PULL0_ACCESS,DISABLED)); + PFIFO_Write(CACHE0_PUSH0,PFIFO_Def(CACHE1_PUSH0_ACCESS,DISABLED)); + PFIFO_Write(CACHE0_PULL0,PFIFO_Def(CACHE1_PULL0_ACCESS,DISABLED)); + } + + static void EnableFifo(void) + { + /* Enable CACHE1 first */ + PFIFO_Write(CACHE1_PUSH0,PFIFO_Def(CACHE1_PUSH0_ACCESS,ENABLED)); + PFIFO_Write(CACHE1_PULL0,PFIFO_Def(CACHE1_PULL0_ACCESS,ENABLED)); + PFIFO_Write(CACHE0_PUSH0,PFIFO_Def(CACHE0_PUSH0_ACCESS,DISABLED)); + PFIFO_Write(CACHE0_PULL0,PFIFO_Def(CACHE0_PULL0_ACCESS,DISABLED)); + PFIFO_Write(CACHES,PFIFO_Def(CACHES_REASSIGN,ENABLED)); + } + + #define HASH_TABLE_ADDR (0/4) + #define HASH_TABLE_SIZE (4096/4) + + #define HASH_TABLE_NUM_COLS 2 + #define HASH_TABLE_NUM_ROWS 256 + + /* All sizes in words */ + #define FIFO_CTX_ADDR (4608/4) + #define FIFO_CTX_SIZE (512/4) + + #define RUN_OUT_ADDR (4096/4) + #define RUN_OUT_SIZE (512/4) + + #define FREE_INSTANCE_ADDR (5120/4) + + #define FREE_INST (FREE_INSTANCE_ADDR/16) + + #define PRIVILEGED_RAM_SIZE 8192 + + #define PRAMINRead nvPRAMINPort(addr) nvPRAMINPort[addr] + #define PRAMINWrite(addr,val) nvPRAMINPort[addr]=(val) + + /* Clear out channel 0 fifo context */ + static void ClearOutFifoContext(void) + { + int i; + + for(i=FIFO_CTX_ADDR;i<FIFO_CTX_SIZE;i++) { + PRAMINWrite(i,0); + } + } + + int NV3KbRamUsedByHW(void) + { + return (PRIVILEGED_RAM_SIZE); + } + + + + static void ClearOutContext(void) + { + int i; + + /* Init context register */ + PGRAPH_Write(CTX_SWITCH,0); + PGRAPH_Write(CTX_USER,0); + + ClearOutFifoContext(); + + /* Set PUT and GET pointers to address 0*/ + PFIFO_Write(CACHE1_PUT,0);PFIFO_Write(CACHE1_GET,0); + + /* Make sure there is no runout data */ + PFIFO_Write(RUNOUT_PUT,0); + PFIFO_Write(RUNOUT_GET,0); + PFIFO_Write(RUNOUT_STATUS,0); + + /* Clear out CACHED CONTEXT registers */ + for(i=0;i<NV_PFIFO_CACHE1_CTX__SIZE_1;i++) { + PFIFO_Write(CACHE1_CTX(i),0); + } + for(i=0;i<NV_PGRAPH_CTX_CACHE__SIZE_1;i++) { + PGRAPH_Write(CTX_CACHE(i),0); + } + + } + + static HashTableEntry localHash[HASH_TABLE_NUM_ROWS][HASH_TABLE_NUM_COLS]; + static HashTableEntry *realHash=NULL; + + + #define HASH_FIFO(h,c) ((((h)^((h)>>8)^((h)>>16)^((h)>>24))&0xFF)^((c)&0x7F)) + + #define HASH_ENTRY(row,col) ((((row)*HASH_TABLE_NUM_COLS)+(col))*2) + + static void ClearOutHashTables(void) + { + int i,j; + + + /* if(!realHash) realHash=(HashTableEntry *) nvPRAMINPort;*/ + + /* Clear out host copy of hash table */ + for(i=0;i<HASH_TABLE_NUM_ROWS;i++) { + for(j=0;j<HASH_TABLE_NUM_COLS;j++) { + localHash[i][j].id=0; + localHash[i][j].context=0; + PRAMINWrite(HASH_ENTRY(i,j),0); + PRAMINWrite(HASH_ENTRY(i,j)+1,0); + } + } + } + + /* Defaults the context for the channel to be something sensible. + * This code is the basis of what needs to be context switched if this + * driver ever expands to cope with multiple channels at the same time. + */ + + static void LoadChannelContext(int screenWidth,int screenHeight,int bpp) + { + int i; + UINT32 read; + int pitch=((bpp+1)/8)*screenWidth; + + + /* Force Cache 0 and Cache 1 to be set for channel 0 */ + + PFIFO_Write(CACHE0_PUSH1,0); + PFIFO_Write(CACHE1_PUSH1,0); + + /* Disable DMA FIFO pusher */ + PFIFO_Write(CACHE1_DMA0,0); + PFIFO_Write(CONFIG_0,0); + + PFIFO_Write(CACHE1_PULL1, 0); + read=PFIFO_Read(CACHE1_PULL1); + PFIFO_Write(CACHE1_PULL1,read|PFIFO_Def(CACHE1_PULL1_CTX,DIRTY)); + read=PFIFO_Read(CACHE1_PULL1); + /* PFIFO_Write(CACHE1_PULL1,read|PFIFO_Def(CACHE1_PULL1_OBJECT,CHANGED));*/ + + /* Set context control. Don't enable channel yet */ + PGRAPH_Write(CTX_CONTROL,PGRAPH_Def(CTX_CONTROL_MINIMUM_TIME,2MS) | + PGRAPH_Def(CTX_CONTROL_TIME,EXPIRED) | + PGRAPH_Def(CTX_CONTROL_CHID,INVALID) | + PGRAPH_Def(CTX_CONTROL_SWITCHING,IDLE) | + PGRAPH_Def(CTX_CONTROL_DEVICE,ENABLED)); + + + /* Make sure FIFO can access engines */ + PGRAPH_Write(FIFO,PGRAPH_Def(FIFO_ACCESS,ENABLED)); + + /* NV3 has src and dest canvases */ + PGRAPH_Write(SRC_CANVAS_MIN,0); + PGRAPH_Write(SRC_CANVAS_MAX,PACK_UINT16(MAX_UINT16,MAX_UINT16)); + + PGRAPH_Write(DST_CANVAS_MIN,0); + PGRAPH_Write(DST_CANVAS_MAX,PACK_UINT16(MAX_UINT16,MAX_UINT16)); + + /* May as well init this lot. Not sure though */ + PGRAPH_Write(DMA,0); + PGRAPH_Write(NOTIFY,0); + PGRAPH_Write(INSTANCE,0); + PGRAPH_Write(MEMFMT,0); + + /* Set BOFFSET */ + /* I don't understand how these interact with the canvas registers. + * They do not seem to provide the same degree of functionality as + * pixel addressing is not possible. Shame really, as it looks like + * SGI style direct rendering is out. Perhaps I am missing something, + * as if you can't do this there seems to be no purpose served by + * having multiple channels! + */ + PGRAPH_Write(BOFFSET0,0);PGRAPH_Write(BOFFSET1,0); + PGRAPH_Write(BOFFSET2,0);PGRAPH_Write(BOFFSET3,0); + + /* Pitch is the length of a line in bytes */ + PGRAPH_Write(BPITCH0,pitch);PGRAPH_Write(BPITCH1,pitch); + PGRAPH_Write(BPITCH2,pitch);PGRAPH_Write(BPITCH3,pitch); + + + switch(bpp) { + case 8: + PGRAPH_Write(BPIXEL,PGRAPH_Def(BPIXEL_DEPTH0_FMT,BITS_8)| + PGRAPH_Def(BPIXEL_DEPTH1_FMT,BITS_8)| + PGRAPH_Def(BPIXEL_DEPTH2_FMT,BITS_8)| + PGRAPH_Def(BPIXEL_DEPTH3_FMT,BITS_8)); + break; + case 15: + case 16: + PGRAPH_Write(BPIXEL,PGRAPH_Def(BPIXEL_DEPTH0_FMT,BITS_16)| + PGRAPH_Def(BPIXEL_DEPTH1_FMT,BITS_16)| + PGRAPH_Def(BPIXEL_DEPTH2_FMT,BITS_16)| + PGRAPH_Def(BPIXEL_DEPTH3_FMT,BITS_16)); + break; + case 32: + PGRAPH_Write(BPIXEL,PGRAPH_Def(BPIXEL_DEPTH0_FMT,BITS_32)| + PGRAPH_Def(BPIXEL_DEPTH1_FMT,BITS_32)| + PGRAPH_Def(BPIXEL_DEPTH2_FMT,BITS_32)| + PGRAPH_Def(BPIXEL_DEPTH3_FMT,BITS_32)); + break; + default: + break; + } + + + PGRAPH_Write(CLIP_MISC,0); + PGRAPH_Write(CLIP0_MIN,0); + PGRAPH_Write(CLIP1_MIN,0); + PGRAPH_Write(CLIP0_MAX,0); + PGRAPH_Write(CLIP1_MAX,0); + + PGRAPH_Write(ABS_UCLIP_XMIN,0); + PGRAPH_Write(ABS_UCLIP_YMIN,0); + PGRAPH_Write(ABS_UCLIP_XMAX,0x7fff); + PGRAPH_Write(ABS_UCLIP_YMAX,0x7fff); + + /* Used for the win95 text class */ + PGRAPH_Write(ABS_UCLIPA_XMIN,0); + PGRAPH_Write(ABS_UCLIPA_YMIN,0); + PGRAPH_Write(ABS_UCLIPA_XMAX,0); + PGRAPH_Write(ABS_UCLIPA_YMAX,0); + + PGRAPH_Write(CLIPX_0,0); + PGRAPH_Write(CLIPX_1,0); + PGRAPH_Write(CLIPY_0,0); + PGRAPH_Write(CLIPY_1,0); + + PGRAPH_Write(SOURCE_COLOR,0); + /* These are dubious. Probable doc error + + PGRAPH_Write(MONO_COLOR0,0); + PGRAPH_Write(MONO_COLOR1,0); + */ + PGRAPH_Write(CHROMA,0); + + PGRAPH_Write(CONTROL_OUT,0); + + /* Beta and Plane Mask */ + PGRAPH_Write(PLANE_MASK,0xffffffff); + PGRAPH_Write(BETA,0); + + for(i=0;i<NV_PGRAPH_ABS_X_RAM__SIZE_1;i++) { + PGRAPH_Write(ABS_X_RAM(i),0); + + } + for(i=0;i<NV_PGRAPH_ABS_Y_RAM__SIZE_1;i++) { + PGRAPH_Write(ABS_Y_RAM(i),0); + } + + PGRAPH_Write(ABS_ICLIP_XMAX,0);PGRAPH_Write(ABS_ICLIP_YMAX,0); + + PGRAPH_Write(XY_LOGIC_MISC0,0);PGRAPH_Write(XY_LOGIC_MISC1,0); + PGRAPH_Write(XY_LOGIC_MISC2,0);PGRAPH_Write(XY_LOGIC_MISC3,0); + PGRAPH_Write(X_MISC,0);PGRAPH_Write(Y_MISC,0); + + /* Pattern registers . Initialise to something sensible */ + PGRAPH_Write(PATT_COLOR0_0,0);PGRAPH_Write(PATT_COLOR0_1,0xff); + PGRAPH_Write(PATT_COLOR1_0,1);PGRAPH_Write(PATT_COLOR1_1,0xff); + PGRAPH_Write(PATTERN(0),0xffffffff);PGRAPH_Write(PATTERN(1),0xffffffff); + PGRAPH_Write(PATTERN_SHAPE,0); + + /* Set the ROP to be COPY (Uses Microshaft raster op codes) */ + PGRAPH_Write(ROP3,0xcc); + + PGRAPH_Write(EXCEPTIONS,0); + + } + + /* Will need to define here what all this lot actually does */ + + #define COLOR_CONTEXT_R5G5B5 0x0 + #define COLOR_CONTEXT_R8G8B8 0x1 + #define COLOR_CONTEXT_R10G10B10 0x2 + #define COLOR_CONTEXT_Y8 0x3 + #define COLOR_CONTEXT_Y16 0x4 + + + /* This value does SRC & PATTERN */ + /* The pattern is disabled/enabled by the ROP code we set up */ + #define PATCH_CONTEXT 0x10 + + /* All contexts will be generated at run time as we need to set the color + * format dynamically + */ + static NVObject ropObject; + static NVObject clipObject; + static NVObject patternObject; + static NVObject rectObject; + static NVObject blitObject; + static NVObject colourExpandObject; + static NVObject lineObject; + static NVObject linObject; + + + static void PlaceObjectInHashTable(NVObject *object) + { + UINT32 hash; + UINT32 context; + int i; + + /* Will put an entry into the hash table */ + /* Always use channel0 for now !! */ + hash=HASH_FIFO(object->id,object->chid); + + for(i=0;i<HASH_TABLE_NUM_COLS;i++) { + if(localHash[hash][i].id==0) break; /* Found an empty slot!!! */ + /* is object already in cache? */ + if(localHash[hash][i].context==object->id) return; + } + if(i==HASH_TABLE_NUM_COLS) { + /* There is no room at the inn. Since we can't cope with reloading + * context we had better abort here!! + */ + Info("**** NO ROOM FOR OBJECT %08lx IN HASH TABLE ****\n",object->id); + graphicsEngineOk=0; /* Set flag so that we won't use accel */ + return; + } + + context=((object->device)<<16)|SetBF(23:23,1)|SetBF(15:0,object->instance)| + SetBF(30:24,object->chid); + #ifdef DEBUG + ErrorF("Placing object %x instance %x in hash\n",object->id,context); + #endif + /* Ok, bung entry in at appropriate place */ + localHash[hash][i].id=object->id; + localHash[hash][i].context=context; + PRAMINWrite(HASH_ENTRY(hash,i),object->id); + PRAMINWrite(HASH_ENTRY(hash,i)+1,context); + } + + + + + static void PlaceObjectInInstTable(NVObject *object) + { + ObjectProperties *p=&(object->properties); + UINT32 context; + + /* This DEFINATELY needs to be symbolic !!!! */ + context=SetBF(28:24,p->patchConfig)|SetBF(13:13,p->chroma)| + SetBF(14:14,p->plane)|SetBF(15:15,p->clip)| + SetBF(2:0,p->colourFormat)|SetBF(3:3,p->alpha)|(1<<20); + + #ifdef DEBUG + ErrorF("Object %x instance %x context %x\n",object->id,object->instance, + context); + #endif + PRAMINWrite((object->instance<<2)+0,context); + PRAMINWrite((object->instance<<2)+1,0); + PRAMINWrite((object->instance<<2)+2,0); + PRAMINWrite((object->instance<<2)+3,0); + + } + + + /* Not exactly terribly complex at the moment, but if we ever get + * round to destroying objects .... + */ + static int AllocateFreeInstance(void) + { + static int freeInstance=FREE_INST; + + return freeInstance++; + } + + static int defaultColourFormat=COLOR_CONTEXT_R8G8B8; + + static void InitObject(NVObject *o,int id,int device) + { + ObjectProperties *p=&(o->properties); + + o->id=id; + o->chid=0; + o->instance=AllocateFreeInstance(); + o->device=device; + + p->patchConfig=PATCH_CONTEXT; + p->zwrite=0; + p->chroma=0; + p->plane=0; + p->clip=1; + p->colourFormat=defaultColourFormat; + p->alpha=0; + } + + + #define OBJECT_CLASS(dev) ((DEVICE_BASE(dev)&0x007f0000)>>16) + + static void SetUpObjects(int bpp) + { + defaultColourFormat=(bpp==16) ? COLOR_CONTEXT_R5G5B5 : COLOR_CONTEXT_R8G8B8; + + InitObject(&ropObject,ROP_OBJECT_ID,OBJECT_CLASS(UROP)); + PlaceObjectInHashTable(&ropObject); + PlaceObjectInInstTable(&ropObject); + + InitObject(&clipObject,CLIP_OBJECT_ID,OBJECT_CLASS(UCLIP)); + PlaceObjectInHashTable(&clipObject); + PlaceObjectInInstTable(&clipObject); + + InitObject(&rectObject,RECT_OBJECT_ID,OBJECT_CLASS(URECT)); + PlaceObjectInHashTable(&rectObject); + PlaceObjectInInstTable(&rectObject); + + InitObject(&blitObject,BLIT_OBJECT_ID,OBJECT_CLASS(UBLIT)); + PlaceObjectInHashTable(&blitObject); + PlaceObjectInInstTable(&blitObject); + + InitObject(&colourExpandObject,COLOUR_EXPAND_OBJECT_ID, + OBJECT_CLASS(UBITMAP)); + colourExpandObject.properties.alpha=1; /* Alpha on for transparency */ + PlaceObjectInHashTable(&colourExpandObject); + PlaceObjectInInstTable(&colourExpandObject); + + InitObject(&lineObject,LINE_OBJECT_ID,OBJECT_CLASS(ULINE)); + PlaceObjectInHashTable(&lineObject); + PlaceObjectInInstTable(&lineObject); + + InitObject(&linObject,LIN_OBJECT_ID,OBJECT_CLASS(ULIN)); + PlaceObjectInHashTable(&linObject); + PlaceObjectInInstTable(&linObject); + + } + + + + static void ClearAndEnableInterrupts(void) + { + + PGRAPH_Write(INTR_0,PGRAPH_Def(INTR_0_RESERVED,RESET)| + PGRAPH_Def(INTR_0_CONTEXT_SWITCH,RESET)| + PGRAPH_Def(INTR_0_VBLANK,RESET)| + PGRAPH_Def(INTR_0_RANGE,RESET)| + PGRAPH_Def(INTR_0_METHOD_COUNT,RESET)| + PGRAPH_Def(INTR_0_FORMAT,RESET)| + PGRAPH_Def(INTR_0_COMPLEX_CLIP,RESET)| + PGRAPH_Def(INTR_0_NOTIFY,RESET)); + + PGRAPH_Write(INTR_EN_0,0xffffffff); + + PGRAPH_Write(INTR_1,PGRAPH_Def(INTR_1_METHOD,RESET)| + PGRAPH_Def(INTR_1_DATA,RESET)| + PGRAPH_Def(INTR_1_DOUBLE_NOTIFY,RESET)| + PGRAPH_Def(INTR_1_CTXSW_NOTIFY,RESET)); + + /* Don't care about any of this lot */ + PGRAPH_Write(INTR_EN_1,0xffffffff); + + PGRAPH_Write(DMA_INTR_0,0xffffffff); + PGRAPH_Write(DMA_INTR_EN_0,0xffffffff); + + + /* Reset the FIFO interrupt state */ + PFIFO_Write(INTR_0, PFIFO_Def(INTR_0_CACHE_ERROR,RESET)| + PFIFO_Def(INTR_0_RUNOUT,RESET)| + PFIFO_Def(INTR_0_RUNOUT_OVERFLOW,RESET)| + PFIFO_Def(INTR_0_DMA_PUSHER,RESET)| + PFIFO_Def(INTR_0_DMA_PTE,RESET)); + + PFIFO_Write(INTR_EN_0, PFIFO_Def(INTR_EN_0_CACHE_ERROR,ENABLED)| + PFIFO_Def(INTR_EN_0_RUNOUT,ENABLED)| + PFIFO_Def(INTR_EN_0_RUNOUT_OVERFLOW,ENABLED)); + + /* Switch on all the user devices in the master control */ + PMC_Write(ENABLE,0xffffffff); + + PMC_Write(INTR_EN_0,PMC_Def(INTR_EN_0_INTA,HARDWARE)); + } + + static void ResetEngine(void) + { + PMC_Write(ENABLE,0xffff00ff); + PMC_Write(ENABLE,0xffffffff); + /* Reset the graphics engine state machine */ + PGRAPH_Write(DEBUG_1,PGRAPH_Def(DEBUG_1_VOLATILE_RESET,LAST)); + PGRAPH_Write(DEBUG_0,PGRAPH_Def(DEBUG_0_STATE,RESET)); + + } + + static void EnableChannel(void) + { + + /* Set context control */ + PGRAPH_Write(CTX_CONTROL,PGRAPH_Def(CTX_CONTROL_MINIMUM_TIME,2MS) | + PGRAPH_Def(CTX_CONTROL_TIME,EXPIRED) | + PGRAPH_Def(CTX_CONTROL_CHID,VALID) | + PGRAPH_Def(CTX_CONTROL_SWITCHING,IDLE) | + PGRAPH_Def(CTX_CONTROL_DEVICE,ENABLED)); + } + + /* This function sets up instance memory to be layed out as follows + * + * 4K hash Table + */ + static void InitInstanceMemory(void) + { + int i; + /* This will set the hash table to be 4K, located at address 0 + * in instance memory + */ + PFIFO_Write(RAMHT,PFIFO_Val(RAMHT_BASE_ADDRESS,0)| + PFIFO_Def(RAMHT_SIZE,4K)); + + /* NB, these values must be aligned on a 512 byte boundary !! */ + PFIFO_Write(RAMRO,PFIFO_Val(RAMRO_BASE_ADDRESS,16)| + PFIFO_Def(RAMRO_SIZE,512)); + + /* Set FIFO context. Need 32 bytes per channel . Smallest size is + * 512 bytes which is more than enough for this driver + */ + PFIFO_Write(RAMFC,PFIFO_Val(RAMFC_BASE_ADDRESS,17)); + + /* This means that the first FREE instance memory starts at address + * 320 (in 16 byte lumps !!) + */ + for(i=0;i<(1024*1024)/4;i++) { + PRAMINWrite(i,0x0); + } + } + + + + + int NV3SetupGraphicsEngine(int screenWidth,int screenHeight,int bpp) + { + graphicsEngineOk=1; + + DisableFifo(); + + ResetEngine(); + + EnableOptimisations(); + + InitDMAInstance(); + + ClearAndEnableInterrupts(); + + InitInstanceMemory(); + + ClearOutContext(); + + ClearOutHashTables(); + + LoadChannelContext(screenWidth,screenHeight,bpp); + + SetUpObjects(bpp); + + EnableChannel(); + + EnableFifo(); + + return graphicsEngineOk; + + } + + + void NV3Sync(void) + { + WaitForIdle(); + } + + /* This function checks to see if an interrupt has been raised, then + * prints out the appropriate registers so that you can attempt to + * figure out what is going on + * if you start mucking around with this chip this will happen a lot + */ + + + + #define CheckBit(var,device,bitfield) \ + if(var & device##_Mask(bitfield)) {\ + Info("<%s %d> "#device"_"#bitfield" Set\n",fileName,lineNo);\ + } + + + void NV3CheckForErrors(char *fileName,int lineNo) + { + UINT32 val=PMC_Read(INTR_0); + /* Has an interrupt been raised ???? */ + /*if(val==0) return;*/ + /* Info("An Interrupt has been raised.\n");*/ + CheckBit(val,PMC,INTR_0_PAUDIO); + CheckBit(val,PMC,INTR_0_PFIFO); + CheckBit(val,PMC,INTR_0_PGRAPH0); + CheckBit(val,PMC,INTR_0_PGRAPH1); + CheckBit(val,PMC,INTR_0_PVIDEO); + CheckBit(val,PMC,INTR_0_PTIMER); + CheckBit(val,PMC,INTR_0_PFB); + CheckBit(val,PMC,INTR_0_PBUS); + CheckBit(val,PMC,INTR_0_SOFTWARE); + + val=PGRAPH_Read(INTR_0); + CheckBit(val,PGRAPH,INTR_0_RESERVED); + CheckBit(val,PGRAPH,INTR_0_CONTEXT_SWITCH); + CheckBit(val,PGRAPH,INTR_0_VBLANK); + CheckBit(val,PGRAPH,INTR_0_RANGE); + CheckBit(val,PGRAPH,INTR_0_METHOD_COUNT); + CheckBit(val,PGRAPH,INTR_0_COMPLEX_CLIP); + CheckBit(val,PGRAPH,INTR_0_NOTIFY); + + val=PGRAPH_Read(INTR_1); + CheckBit(val,PGRAPH,INTR_1_METHOD); + CheckBit(val,PGRAPH,INTR_1_DATA); + CheckBit(val,PGRAPH,INTR_1_DOUBLE_NOTIFY); + CheckBit(val,PGRAPH,INTR_1_CTXSW_NOTIFY); + + val=PFIFO_Read(INTR_0); + CheckBit(val,PFIFO,INTR_0_CACHE_ERROR); + CheckBit(val,PFIFO,INTR_0_RUNOUT); + CheckBit(val,PFIFO,INTR_0_RUNOUT_OVERFLOW); + CheckBit(val,PFIFO,INTR_0_DMA_PUSHER); + CheckBit(val,PFIFO,INTR_0_DMA_PTE); + + + val=PGRAPH_Read(DMA_INTR_0); + CheckBit(val,PGRAPH,DMA_INTR_0_INSTANCE); + CheckBit(val,PGRAPH,DMA_INTR_0_PRESENT); + CheckBit(val,PGRAPH,DMA_INTR_0_PROTECTION); + CheckBit(val,PGRAPH,DMA_INTR_0_LINEAR); + CheckBit(val,PGRAPH,DMA_INTR_0_NOTIFY); + + + } *** /dev/null Tue Jun 30 11:50:14 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/nvaccel.c Fri Mar 6 16:52:14 1998 *************** *** 0 **** --- 1,489 ---- + /* $TOG: nvaccel.c /main/1 1998/03/06 16:53:52 kaleb $ */ + + + + /* + * Copyright 1996-1997 David J. McKay + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * DAVID J. MCKAY BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/nvaccel.c,v 1.1.2.3 1998/01/24 11:55:10 dawes Exp $ */ + + #include <stdlib.h> + + #include "vga256.h" + #include "xf86.h" + #include "vga.h" + #include "xf86xaa.h" + #include "miline.h" + + #define XCONFIG_FLAGS_ONLY + #include "xf86_Config.h" + + #include "nvuser.h" + #include "nvreg.h" + + #ifdef DEBUG + #define CHECK() NV3CheckForErrors(__FILE__,__LINE__) + #else + #define CHECK() + #endif + + /* These are the subchannels where the various objects are */ + + #define ROP_SUBCHANNEL 0 + #define BLIT_SUBCHANNEL 1 + #define PATTERN_SUBCHANNEL 2 + #define RECT_SUBCHANNEL 3 + #define CLIP_SUBCHANNEL 4 + #define COLOUR_EXPAND_SUBCHANNEL 5 + #define LINE_SUBCHANNEL 6 + #define LIN_SUBCHANNEL 7 + + + /* This is the pointer to the channel */ + static NvChannel *chan0=NULL; + /* Pointers to fixed subchannels */ + static NvSubChannel *ropChan=NULL; + static NvSubChannel *rectChan=NULL; + static NvSubChannel *blitChan=NULL; + static NvSubChannel *clipChan=NULL; + static NvSubChannel *colourExpandChan=NULL; + + /*#define NV_ENABLE_LINES*/ + + /* Lines are disables at the moment. I have been unable to get the + * lines produced by the NV1 hardware to match the software routines. + * The NV1 draws lines a la windows, which is different to what X wants + * Even fiddling with the zero bias does not get it correct. Will need a + * lot of work to get it to work + */ + #ifdef NV_ENABLE_LINES + static NvSubChannel *lineChan=NULL; + static NvSubChannel *linChan=NULL; + #endif + + /* Holds number of free slots in fifo. Means we don't have to re-read + * the fifo count every time we want to write to the chip + */ + static int freeSlots=0; + + #if 1 + #define WaitForSlots(n,words) \ + while((freeSlots-=((words)*4)) < 0) {\ + freeSlots=chan0->subChannel[n].control.free;\ + } + #endif + + #if 0 + #define WaitForSlots(n,words) (chan0->subChannel[n].control.free<((words)*4)) + #endif + + static int currentRop=-1; + + static void NVSetRop(int rop) + { + static int ropTrans[16] = { + 0x0, /* GXclear */ + 0x88, /* Gxand */ + 0x44, /* GXandReverse */ + 0xcc, /* GXcopy */ + 0x22, /* GXandInverted */ + 0xaa, /* GXnoop */ + 0x66, /* GXxor */ + 0xee, /* GXor */ + 0x11, /* GXnor */ + 0x99, /* Gxequiv */ + 0x55, /* GXinvert */ + 0xdd, /* GXorReverse */ + 0x33, /* GXcopyInverted */ + 0xbb, /* GXorInverted */ + 0x77, /* GXnand */ + 0xff /* GXset */ + }; + currentRop=rop; + WaitForSlots(ROP_SUBCHANNEL,1); + ropChan->method.ropSolid.setRop=ropTrans[rop]; + CHECK(); + } + + /* I haven't figured out how Patterns work yet, so this code is + * not used at present + */ + #if 0 + static NVSetPatternRop(int rop) + { + static int ropTrans[16]={ + 0x00, /* GXclear */ + 0xa0, /* Gxand */ + 0x0a, /* GXandReverse */ + 0xf0, /* GXcopy */ + 0x30, /* GXandInverted */ + 0xaa, /* GXnoop */ + 0x3a, /* GXxor */ + 0xfa, /* GXor */ + 0x03, /* GXnor */ + 0xa0, /* Gxequiv */ + 0x0f, /* GXinvert */ + 0xaf, /* GXorReverse */ + 0x33, /* GXcopyInverted */ + 0xbb, /* GXorInverted */ + 0xf3, /* GXnand */ + 0xff /* GXset */ + }; + currentRop=rop+16; /* +16 is important */ + WaitForSlots(ROP_SUBCHANNEL,1); + ropChan->method.ropSolid.setRop=ropTrans[rop]; + CHECK(); + + } + + #endif + + /* + * Due to the fact that the SetupForFillRectSolid() is also used + * to setup for lines we have to record the colour in a static + * variable and write it out every time we do a drawing operation. + * This costs some performance and is IMHO wrong anyway. Why should + * you call a routine for filled rectangles when you are drawing lines? + * Will get round to "fixing" this if I ever get lines on the NV1 to work + * correctly + */ + + #if 1 + static int currentColor; + #endif + + static void NVSetupForFillRectSolid(int color,int rop,unsigned planemask) + { + if(currentRop!=rop) { + NVSetRop(rop); + } + + #if 1 + currentColor=color; + #else + WaitForSlots(RECT_SUBCHANNEL,1); + rectChan->method.renderSolidRectangle.color=color; + #endif + + CHECK(); + } + + static void NVSubsequentFillRectSolid(int x,int y,int w,int h) + { + + #if 1 + WaitForSlots(RECT_SUBCHANNEL,3); + rectChan->method.renderSolidRectangle.color=currentColor; + #else + WaitForSlots(RECT_SUBCHANNEL,2); + #endif + + rectChan->method.renderSolidRectangle.rectangle[0].yx=PACK_UINT16(y,x); + rectChan->method.renderSolidRectangle.rectangle[0].heightWidth= + PACK_UINT16(h,w); + CHECK(); + } + + + + + static int clippingOn=0; + + static void NVSetClippingRectangle(int x1,int y1,int x2,int y2) + { + int height,width; + + width=x2-x1+1;height=y2-y1+1; + WaitForSlots(CLIP_SUBCHANNEL,2); + clipChan->method.clip.setRectangle.yx=PACK_INT16(y1,x1); + clipChan->method.clip.setRectangle.heightWidth=PACK_UINT16(height,width); + clippingOn=1; + CHECK(); + } + + + #define NVResetClippingRectangle() \ + { NVSetClippingRectangle(0,0,MAX_INT16,MAX_INT16);\ + clippingOn=0;} + + + + #ifdef NV_ENABLE_LINES + static void NVSubsequentTwoPointLine(int x1,int y1,int x2,int y2,int bias) + { + NvRenderSolidLine *line; + + line = (bias&0x0100) ? &(linChan->method.line) : &(lineChan->method.line); + /* We should really check appropriate subchannel here */ + WaitForSlots(LINE_SUBCHANNEL,3); + line->color=currentColor; + line->line[0].y0_x0=PACK_INT16(y1,x1); + line->line[0].y1_x1=PACK_INT16(y2,x2); + /* Reset clipping rectangle to normal */ + if(clippingOn) { + NVResetClippingRectangle(); + } + } + + #endif + + static void NVSetupForScreenToScreenCopy(int xdir,int ydir,int rop, + unsigned planemask, + int transparency_color) + { + if(rop!=currentRop) { + NVSetRop(rop); + } + + /* When transparency is implemented, will have to flip object */ + } + + static void NVSubsequentScreenToScreenCopy(int x1,int y1, + int x2,int y2,int w,int h) + { + WaitForSlots(BLIT_SUBCHANNEL,3); + blitChan->method.blit.yxIn=PACK_UINT16(y1,x1); + blitChan->method.blit.yxOut=PACK_UINT16(y2,x2); + blitChan->method.blit.heightWidth=PACK_UINT16(h,w); + CHECK(); + } + + + /* How much date to transfer */ + static int scanlineWordCount; + static unsigned char scratchBuffer[512]; + static int colourExpandMask=0; + + static void NVSetupForScanlineScreenToScreenColorExpand(int x,int y,int w, + int h,int bg,int fg, + int rop, + unsigned planemask) + { + if(currentRop!=rop) { + NVSetRop(rop); + } + WaitForSlots(COLOUR_EXPAND_SUBCHANNEL,5); + if(bg==-1) { + colourExpandChan->method.imageMonochromeFromCpu.color0=0; + }else { + colourExpandChan->method.imageMonochromeFromCpu.color0=bg|colourExpandMask; + } + colourExpandChan->method.imageMonochromeFromCpu.color1=fg|colourExpandMask; + colourExpandChan->method.imageMonochromeFromCpu.point=PACK_UINT16(y,x); + colourExpandChan->method.imageMonochromeFromCpu.size=PACK_UINT16(h,w); + colourExpandChan->method.imageMonochromeFromCpu.sizeIn= + PACK_UINT16(h,(w+31)&(~31)); + scanlineWordCount = (w + 31) >> 5; + CHECK(); + } + + static void NVSubsequentScanlineScreenToScreenColorExpand(int srcAddr) + { + unsigned long *ptr = (unsigned long*)scratchBuffer; + int count = scanlineWordCount; + int i=0; + + /* This rather simple algorithm seems to perform better than + * the more complex variants with loop unrolling that I have tried + */ + for(i=0;i<count;i++) { + WaitForSlots(COLOUR_EXPAND_SUBCHANNEL,1); + colourExpandChan->method.imageMonochromeFromCpu.monochrome[i%32]=(*(ptr++)); + } + CHECK(); + } + + + static void SetupSubChans(void) + { + /* Map subchannels */ + ropChan=&(chan0->subChannel[ROP_SUBCHANNEL]); + rectChan=&(chan0->subChannel[RECT_SUBCHANNEL]); + blitChan=&(chan0->subChannel[BLIT_SUBCHANNEL]); + clipChan=&(chan0->subChannel[CLIP_SUBCHANNEL]); + colourExpandChan=&(chan0->subChannel[COLOUR_EXPAND_SUBCHANNEL]); + + #ifdef NV_ENABLE_LINES + lineChan=&(chan0->subChannel[LINE_SUBCHANNEL]); + linChan=&(chan0->subChannel[LIN_SUBCHANNEL]); + #endif + + /* Bung the appropriate objects into the subchannels */ + ropChan->control.object=ROP_OBJECT_ID; + blitChan->control.object=BLIT_OBJECT_ID; + rectChan->control.object=RECT_OBJECT_ID; + clipChan->control.object=CLIP_OBJECT_ID; + + colourExpandChan->control.object=COLOUR_EXPAND_OBJECT_ID; + + #ifdef NV_ENABLE_LINES + lineChan->control.object=LINE_OBJECT_ID; + linChan->control.object=LIN_OBJECT_ID; + #endif + + CHECK(); + } + + + /* These should really be in a separate file */ + void NV3Sync(void); + void NV1Sync(void); + + int NV3SetupGraphicsEngine(int width,int height,int bpp); + int NV1SetupGraphicsEngine(int width,int height,int bpp); + + + void NVAccelInit(void) + { + int i; + int ret; + + #ifdef DEBUG + if(getenv("NV_NOACCEL")) return; + #endif + + ret=(GetChipType()==NV1) ? NV1SetupGraphicsEngine(vga256InfoRec.virtualX, + vga256InfoRec.virtualY, + vgaBitsPerPixel) + : NV3SetupGraphicsEngine(vga256InfoRec.virtualX, + vga256InfoRec.virtualY, + vgaBitsPerPixel); + if(!ret) { + ErrorF("Failed to init graphics engine - no acceleration\n"); + } + switch(vgaBitsPerPixel) { + case 8: + case 32: + colourExpandMask=0xff000000; + break; + case 15: + case 16: + colourExpandMask=0xffff8000; + break; + } + CHECK(); + + chan0=NvOpenChannel(); + if(chan0==NULL) return; + SetupSubChans(); + NVResetClippingRectangle(); + + /* There are still some problems with delayed syncing */ + xf86AccelInfoRec.Flags = BACKGROUND_OPERATIONS/*| DELAYED_SYNC*/; + + if(GetChipType()==NV1) { + xf86AccelInfoRec.Sync = NV1Sync; + }else { + xf86AccelInfoRec.Sync = NV3Sync; + } + + xf86GCInfoRec.PolyFillRectSolidFlags = NO_PLANEMASK | NO_TRANSPARENCY; + + /* + * Install the low-level functions for drawing solid filled rectangles. + */ + xf86AccelInfoRec.SetupForFillRectSolid = NVSetupForFillRectSolid; + xf86AccelInfoRec.SubsequentFillRectSolid = NVSubsequentFillRectSolid; + + + xf86GCInfoRec.CopyAreaFlags = NO_PLANEMASK | NO_TRANSPARENCY; + + xf86AccelInfoRec.SetupForScreenToScreenCopy = + NVSetupForScreenToScreenCopy; + xf86AccelInfoRec.SubsequentScreenToScreenCopy = + NVSubsequentScreenToScreenCopy; + + #ifdef DEBUG + if(getenv("NV_NOCOLOUREXPAND")==NULL) + #endif + { + /* Colour Expansion */ + xf86AccelInfoRec.Flags|=NO_SYNC_AFTER_CPU_COLOR_EXPAND | + COP_FRAMEBUFFER_CONCURRENCY; + + xf86AccelInfoRec.ColorExpandFlags = /*NO_TRANSPARENCY | */ + NO_PLANEMASK | + SCANLINE_PAD_DWORD | + CPU_TRANSFER_PAD_DWORD | + BIT_ORDER_IN_BYTE_LSBFIRST | + VIDEO_SOURCE_GRANULARITY_DWORD; + + xf86AccelInfoRec.ScratchBufferAddr = 1; + xf86AccelInfoRec.ScratchBufferSize = 1024; + xf86AccelInfoRec.ScratchBufferBase = (void*)scratchBuffer; + xf86AccelInfoRec.PingPongBuffers = 1; + + xf86AccelInfoRec.SetupForScanlineScreenToScreenColorExpand = + NVSetupForScanlineScreenToScreenColorExpand; + xf86AccelInfoRec.SubsequentScanlineScreenToScreenColorExpand = + NVSubsequentScanlineScreenToScreenColorExpand; + + } + + #ifdef NV_ENABLE_LINES + #ifdef DEBUG + if(getenv("NV_NOLINES")==NULL) + #endif + { + extern int nvMiLineZeroBias; + + + #ifdef DEBUG + ErrorF("NV_ZEROBIAS is %s\n",getenv("NV_ZEROBIAS")); + + if(getenv("NV_ZEROBIAS")!=NULL) { + nvMiLineZeroBias=atoi((char*)getenv("NV_ZEROBIAS")); + ErrorF("Setting bias to %d\n",nvMiLineZeroBias); + } + #endif + + /* Lines and lins */ + xf86AccelInfoRec.Flags|=HARDWARE_CLIP_LINE| + USE_TWO_POINT_LINE| + TWO_POINT_LINE_NOT_LAST; + xf86AccelInfoRec.SubsequentTwoPointLine = NVSubsequentTwoPointLine; + xf86AccelInfoRec.SetClippingRectangle = NVSetClippingRectangle; + + + } + #endif + + /* + * Finally, we set up the video memory space available to the pixmap + * cache. In this case, all memory from the end of the virtual screen + * to the end of video memory minus 13K, can be used. + */ + #ifdef DEBUG + if(getenv("NV_NOPIXMAPCACHE")==NULL) + #endif + { + xf86AccelInfoRec.Flags|= PIXMAP_CACHE; + xf86InitPixmapCache( &vga256InfoRec, + vga256InfoRec.virtualY * vga256InfoRec.displayWidth * + vga256InfoRec.bitsPerPixel / 8, + (vga256InfoRec.videoRam-(63 /*NvKbRamUsedByHW()*/+1))*1024); + } + + + } + + *** /dev/null Tue Jun 30 11:50:15 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/nvcursor.h Fri Mar 6 16:52:18 1998 *************** *** 0 **** --- 1,42 ---- + /* $TOG: nvcursor.h /main/1 1998/03/06 16:53:56 kaleb $ */ + /* + * Copyright 1996-1997 David J. McKay + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * DAVID J. MCKAY BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/nvcursor.h,v 1.1.2.2 1998/01/24 00:04:40 robin Exp $ */ + + #ifndef _NVCURSOR_H_ + #define _NVCURSOR_H_ + + Bool NVCursorInit(char *pm,ScreenPtr pScr); + void NVRestoreCursor(ScreenPtr pScr); + void NVWarpCursor(ScreenPtr pScr,int x,int y); + void NVQueryBestSize(int class,unsigned short *pwidth, + unsigned short *pheight,ScreenPtr pScreen); + + + Bool NV3CursorInit(char *pm,ScreenPtr pScr); + void NV3RestoreCursor(ScreenPtr pScr); + void NV3WarpCursor(ScreenPtr pScr,int x,int y); + void NV3QueryBestSize(int class,unsigned short *pwidth, + unsigned short *pheight,ScreenPtr pScreen); + + #endif *** /dev/null Tue Jun 30 11:50:16 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/nvsetup.c Fri Mar 6 16:52:26 1998 *************** *** 0 **** --- 1,596 ---- + /* $TOG: nvsetup.c /main/1 1998/03/06 16:54:04 kaleb $ */ + /* + * Copyright 1996-1997 David J. McKay + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * DAVID J. MCKAY BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/nvsetup.c,v 1.1.2.3 1998/01/24 11:55:10 dawes Exp $ */ + + #include <stdlib.h> + + + #include "nvuser.h" + #include "nv1ref.h" + #include "nvreg.h" + + typedef struct { + UINT32 id; /* 32 bit unique identifer for this object */ + UINT32 channel; /* What channel this object belongs to */ + UINT32 context; /* Holds configuration of pipeline. Written to CTX SWITCH */ + }NVObject; + + + + static int graphicsEngineOk; + + #define WaitForIdle() while(PGRAPH_Read(STATUS)) + + static void EnableOptimisations(void) + { + /* Now switch on all the optimisations that there are */ + PGRAPH_Write(DEBUG_0,PGRAPH_Def(DEBUG_0_EDGE_FILLING,ENABLED) | + PGRAPH_Def(DEBUG_0_WRITE_ONLY_ROPS,ENABLED) | + PGRAPH_Def(DEBUG_0_NONBLOCK_BROAD,ENABLED) | + PGRAPH_Def(DEBUG_0_BLOCK_BROAD,ENABLED) | + PGRAPH_Def(DEBUG_0_BLOCK,ENABLED) | + PGRAPH_Def(DEBUG_0_BULK_READS,ENABLED)); + + PGRAPH_Write(DEBUG_1,PGRAPH_Def(DEBUG_1_HIRES_TM,DISABLED) | + PGRAPH_Def(DEBUG_1_FAST_BUS,DISABLED) | + PGRAPH_Def(DEBUG_1_TM_QUAD_HANDOFF,ENABLED) | + PGRAPH_Def(DEBUG_1_FAST_RMW_BLITS,ENABLED) | + PGRAPH_Def(DEBUG_1_PATT_BLOCK,ENABLED) | + PGRAPH_Def(DEBUG_1_TRI_OPTS,DISABLED) | + PGRAPH_Def(DEBUG_1_BI_RECTS,DISABLED) | + PGRAPH_Def(DEBUG_1_DMA_ACTIVITY,IGNORE) | + PGRAPH_Def(DEBUG_1_VOLATILE_RESET,NOT_LAST)); + + PGRAPH_Write(DEBUG_2,PGRAPH_Def(DEBUG_2_VOLATILE_RESET,ENABLED) | + PGRAPH_Def(DEBUG_2_TM_FASTINPUT,ENABLED) | + PGRAPH_Def(DEBUG_2_BUSY_PATIENCE,ENABLED) | + PGRAPH_Def(DEBUG_2_TRAPEZOID_TEXEL,ENABLED) | + PGRAPH_Def(DEBUG_2_MONO_ABORT,DISABLED) | + PGRAPH_Def(DEBUG_2_BETA_ABORT,ENABLED) | + PGRAPH_Def(DEBUG_2_ALPHA_ABORT,ENABLED) | + PGRAPH_Def(DEBUG_2_AVOID_RMW_BLEND,DISABLED)); + + /* + * REV c parts have another debug register here, but ignore for the + * moment + */ + } + + static void InitDMAInstance(void) + { + PDMA_Write(GR_CHANNEL,PDMA_Def(GR_CHANNEL_ACCESS,DISABLED)); + PDMA_Write(GR_INSTANCE,0); + PGRAPH_Write(DMA,0); + PGRAPH_Write(NOTIFY,0); + PDMA_Write(GR_CHANNEL,PDMA_Def(GR_CHANNEL_ACCESS,ENABLED)); + } + + + + static void DisableFifo(void) + { + /* Disable CACHE1 first */ + PFIFO_Write(CACHES,PFIFO_Def(CACHES_REASSIGN,DISABLED)); + PFIFO_Write(CACHE1_PUSH0,PFIFO_Def(CACHE1_PUSH0_ACCESS,DISABLED)); + PFIFO_Write(CACHE1_PULL0,PFIFO_Def(CACHE1_PULL0_ACCESS,DISABLED)); + PFIFO_Write(CACHE0_PUSH0,PFIFO_Def(CACHE1_PUSH0_ACCESS,DISABLED)); + PFIFO_Write(CACHE0_PULL0,PFIFO_Def(CACHE1_PULL0_ACCESS,DISABLED)); + + } + + static void EnableFifo(void) + { + /* Enable CACHE1 first */ + PFIFO_Write(CACHE1_PUSH0,PFIFO_Def(CACHE1_PUSH0_ACCESS,ENABLED)); + PFIFO_Write(CACHE1_PULL0,PFIFO_Def(CACHE1_PULL0_ACCESS,ENABLED)); + PFIFO_Write(CACHES,PFIFO_Def(CACHES_REASSIGN,ENABLED)); + } + + + #define PRIV_RAM_SIZE 0 + #define NUM_FIFO_CONTEXT ((PRIV_RAM_SIZE)? 128 : 64) + + /* Clear out channel 0 fifo context */ + static void ClearOutFifoContext(void) + { + int i; + + /* Set up size of PRAM */ + PRAM_Write(CONFIG_0,PRAM_Val(CONFIG_0_SIZE,PRIV_RAM_SIZE)); + + for(i=0;i<NUM_FIFO_CONTEXT;i++) { + nvPRAMFCPort[i]=0; + } + } + + int NvKbRamUsedByHW(void) + { + /* Audio scratch and password context are fixed at 4K, + * but hash table, runout and fifo vary with PRIV_RAM_SIZE + */ + return ( (8<<PRIV_RAM_SIZE)+4 ); + } + + + + static void ClearOutContext(void) + { + int i; + + /* Init context register */ + PGRAPH_Write(CTX_SWITCH,0); + + ClearOutFifoContext(); + + /* Set PUT and GET pointers to address 0*/ + PFIFO_Write(CACHE1_PUT,0);PFIFO_Write(CACHE1_GET,0); + + /* Make sure there is no runout data */ + PFIFO_Write(RUNOUT_PUT,0); + PFIFO_Write(RUNOUT_GET,0); + + /* Nobody is allowed to lie about how much space in the fifo */ + PFIFO_Write(CONFIG_0,PFIFO_Def(CONFIG_0_FREE_LIE,DISABLED)); + + /* Clear out CACHED CONTEXT registers */ + for(i=0;i<NV_PFIFO_CACHE1_CTX__SIZE_1;i++) { + PFIFO_Write(CACHE1_CTX(i),0); + } + } + + #define HASH_TABLE_DEPTH (2<<PRIV_RAM_SIZE) + #define HASH_TABLE_SIZE 256 + + typedef struct { + UINT32 id; + UINT32 context; + }HashTableEntry; + + static HashTableEntry localHash[HASH_TABLE_SIZE][HASH_TABLE_DEPTH]; + static HashTableEntry *realHash=NULL; + + + #define HASH_FIFO(h,c) ((((h)^((h)>>8)^((h)>>16)^((h)>>24))&0xFF)^((c)&0x7F)) + + #define HASH_ENTRY(index,depth) (((index)*HASH_TABLE_DEPTH)+(depth)) + + static void ClearOutHashTables(void) + { + int i,j; + + if(!realHash) realHash=(HashTableEntry *) nvPRAMHTPort; + + /* Clear out host copy of hash table */ + for(i=0;i<HASH_TABLE_SIZE;i++) { + for(j=0;j<HASH_TABLE_DEPTH;j++) { + localHash[i][j].id=0; + localHash[i][j].context=0; + (realHash+HASH_ENTRY(i,j))->id=0; + (realHash+HASH_ENTRY(i,j))->context=0; + } + } + /* Clear out hash virtual registers */ + for(i=0;i<NV_PRAM_HASH_VIRTUAL__SIZE_1;i++) { + PRAM_Write(HASH_VIRTUAL(i),0); + } + } + + /* Defaults the context for the channel to be something sensible. + * This code is the basis of what needs to be context switched if this + * driver ever expands to cope with multiple channels at the same time. + */ + + void LoadChannelContext(void) + { + int i; + UINT32 read; + + + /* Force Cache 0 and Cache 1 to be set for channel 0 */ + + PFIFO_Write(CACHE0_PUSH1,0); + PFIFO_Write(CACHE1_PUSH1,0); + + PFIFO_Write(CACHE1_PULL1, 0); + read=PFIFO_Read(CACHE1_PULL1); + PFIFO_Write(CACHE1_PULL1,read|PFIFO_Def(CACHE1_PULL1_CTX,DIRTY)); + read=PFIFO_Read(CACHE1_PULL1); + PFIFO_Write(CACHE1_PULL1,read|PFIFO_Def(CACHE1_PULL1_OBJECT,CHANGED)); + + /* Set context control. Don't enable channel yet */ + PGRAPH_Write(CTX_CONTROL,PGRAPH_Def(CTX_CONTROL_MINIMUM_TIME,2MS) | + PGRAPH_Def(CTX_CONTROL_TIME,EXPIRED) | + PGRAPH_Def(CTX_CONTROL_CHID,INVALID) | + PGRAPH_Def(CTX_CONTROL_SWITCHING,IDLE) | + PGRAPH_Def(CTX_CONTROL_DEVICE,ENABLED)); + + PGRAPH_Write(CANVAS_MIN,0); + PGRAPH_Write(CANVAS_MAX,PACK_UINT16(MAX_UINT16,MAX_UINT16)); + + PGRAPH_Write(CLIP_MISC,0); + PGRAPH_Write(CLIP0_MIN,0); + PGRAPH_Write(CLIP1_MIN,0); + PGRAPH_Write(CLIP0_MAX,0); + PGRAPH_Write(CLIP1_MAX,0); + + PGRAPH_Write(CANVAS_MISC,PGRAPH_Def(CANVAS_MISC_DAC_BYPASS,DISABLED)| + PGRAPH_Def(CANVAS_MISC_DITHER,ENABLED)| + PGRAPH_Def(CANVAS_MISC_REPLICATE,ENABLED)); + + PGRAPH_Write(SOURCE_COLOR,0); + PGRAPH_Write(MONO_COLOR0,0); + PGRAPH_Write(MONO_COLOR1,0); + + PGRAPH_Write(ABS_UCLIP_XMIN,0); + PGRAPH_Write(ABS_UCLIP_YMIN,0); + PGRAPH_Write(ABS_UCLIP_XMAX,0); + PGRAPH_Write(ABS_UCLIP_YMAX,0); + + /* Beta and Plane Mask */ + PGRAPH_Write(PLANE_MASK,0xffffffff); + PGRAPH_Write(BETA,0); + for(i=0;i<NV_PGRAPH_BETA_RAM__SIZE_1;i++) { + PGRAPH_Write(BETA_RAM(i),0); + } + + for(i=0;i<NV_PGRAPH_ABS_X_RAM__SIZE_1;i++) { + PGRAPH_Write(ABS_X_RAM(i),0); + + } + for(i=0;i<NV_PGRAPH_ABS_Y_RAM__SIZE_1;i++) { + PGRAPH_Write(ABS_Y_RAM(i),0); + } + + PGRAPH_Write(ABS_ICLIP_XMAX,0);PGRAPH_Write(ABS_ICLIP_YMAX,0); + + PGRAPH_Write(XY_LOGIC_MISC0,0);PGRAPH_Write(XY_LOGIC_MISC1,0); + PGRAPH_Write(X_MISC,0);PGRAPH_Write(Y_MISC,0); + + PGRAPH_Write(SUBDIVIDE,0);PGRAPH_Write(EDGEFILL,0); + + /* Pattern registers . Initialise to something sensible */ + PGRAPH_Write(PATT_COLOR0_0,0);PGRAPH_Write(PATT_COLOR0_1,0xff); + PGRAPH_Write(PATT_COLOR1_0,1);PGRAPH_Write(PATT_COLOR1_1,0xff); + PGRAPH_Write(PATTERN(0),0xffffffff);PGRAPH_Write(PATTERN(1),0xffffffff); + PGRAPH_Write(PATTERN_SHAPE,0); + + /* Set the ROP to be COPY (Uses Microshaft raster op codes) */ + PGRAPH_Write(ROP3,0xcc); + + PGRAPH_Write(EXCEPTIONS,0); + PGRAPH_Write(BIT33,0); + + } + + static void EnableFlowThru(void) + { + /* Disable the fifo and the DMA engine, but keep flowthu enabled. + * This state is needed to actually access many of the registers + * in the graphics engine that we are going to set up + */ + PGRAPH_Write(MISC,PGRAPH_Def(MISC_FLOWTHRU_WRITE,ENABLED) | + PGRAPH_Def(MISC_FLOWTHRU,ENABLED) | + PGRAPH_Def(MISC_FIFO_WRITE,ENABLED) | + PGRAPH_Def(MISC_FIFO,DISABLED) | + PGRAPH_Def(MISC_DMA_WRITE,ENABLED) | + PGRAPH_Def(MISC_DMA,DISABLED) | + PGRAPH_Def(MISC_CLASS_WRITE,ENABLED) | + PGRAPH_Val(MISC_CLASS, 0)); + + } + + + /* Will need to define here what all this lot actually does */ + + #define COLOR_CONTEXT_R5G5B5 0x0 + #define COLOR_CONTEXT_R8G8B8 0x1 + #define COLOR_CONTEXT_R10G10B10 0x2 + #define COLOR_CONTEXT_Y8 0x3 + #define COLOR_CONTEXT_Y16 0x4 + + + #define GENERATE_CONTEXT(device,cfg,chroma,plane,clip,color,alpha) \ + DEVICE_BASE(device)|\ + SetBF(4:0,cfg)|SetBF(5:5,chroma)|SetBF(6:6,plane)|\ + SetBF(7:7,clip)|SetBF(8:8,0)|SetBF(12:9,color)|\ + SetBF(13:13,alpha)|SetBF(14:14,0)|SetBF(15:15,0) + + /* This value does SRC & PATTERN */ + /* The pattern is disabled/enabled by the ROP code we set up */ + #define PATCH_CONTEXT 0x10 + + /* All contexts will be generated at run time as we need to set the color + * format dynamically + */ + static NVObject ropObject; + static NVObject clipObject; + static NVObject patternObject; + static NVObject rectObject; + static NVObject blitObject; + static NVObject colourExpandObject; + static NVObject lineObject; + static NVObject linObject; + static NVObject chromaObject; + + #define Info ErrorF + + static void InitObject(NVObject *object) + { + UINT32 hash; + int i; + + /* Will put an entry into the hash table */ + hash=HASH_FIFO(object->id,object->channel); + + for(i=0;i<HASH_TABLE_DEPTH;i++) { + if(localHash[hash][i].id==0) break; /* Found an empty slot!!! */ + /* is object already in cache? */ + if(localHash[hash][i].context==object->id) return; + } + if(i==HASH_TABLE_DEPTH) { + /* There is no room at the inn. Since we can't cope with reloading + * context we had better abort here!! + */ + Info("**** NO ROOM FOR OBJECT %08lx IN HASH TABLE ****\n",object->id); + graphicsEngineOk=0; /* Set flag so that we won't use accel */ + return; + } + /* Ok, bung entry in at appropriate place */ + localHash[hash][i].id=object->id; + localHash[hash][i].context=object->context; + (realHash+HASH_ENTRY(hash,i))->id=object->id; + (realHash+HASH_ENTRY(hash,i))->context=object->context; + } + + static void SetUpObjects(int bpp) + { + int colorContext=(bpp==8) ? COLOR_CONTEXT_R8G8B8 : COLOR_CONTEXT_R5G5B5; + + ropObject.id=ROP_OBJECT_ID; + ropObject.channel=0; + ropObject.context=GENERATE_CONTEXT(UROP,0,0,0,0,0,0); + InitObject(&ropObject); + + clipObject.id=CLIP_OBJECT_ID; + clipObject.channel=0; + clipObject.context=GENERATE_CONTEXT(UCLIP,0,0,0,0,0,0); + InitObject(&clipObject); + + patternObject.id=PATTERN_OBJECT_ID; + patternObject.channel=0; + patternObject.context= + GENERATE_CONTEXT(UPATT,0,0,0,0,colorContext,0); + InitObject(&patternObject); + + rectObject.id=RECT_OBJECT_ID; + rectObject.channel=0; + rectObject.context= + GENERATE_CONTEXT(URECT,PATCH_CONTEXT,0,0,1,colorContext,0); + InitObject(&rectObject); + + + blitObject.id=BLIT_OBJECT_ID; + blitObject.channel=0; + blitObject.context= + GENERATE_CONTEXT(UBLIT,PATCH_CONTEXT,0,0,1,colorContext,0); + InitObject(&blitObject); + + colourExpandObject.id=COLOUR_EXPAND_OBJECT_ID; + colourExpandObject.channel=0; + colourExpandObject.context= + GENERATE_CONTEXT(UBITMAP,PATCH_CONTEXT,0,0,1,colorContext,1); + InitObject(&colourExpandObject); + + lineObject.id=LINE_OBJECT_ID; + lineObject.channel=0; + lineObject.context= + GENERATE_CONTEXT(ULINE,PATCH_CONTEXT,0,0,1,colorContext,0); + InitObject(&lineObject); + + linObject.id=LIN_OBJECT_ID; + linObject.channel=0; + linObject.context= + GENERATE_CONTEXT(ULIN,PATCH_CONTEXT,0,0,1,colorContext,0); + InitObject(&linObject); + } + + + + static void ClearAndEnableInterrupts(void) + { + PGRAPH_Write(INTR_0,PGRAPH_Def(INTR_0_RESERVED,RESET)| + PGRAPH_Def(INTR_0_CONTEXT_SWITCH,RESET)| + PGRAPH_Def(INTR_0_VBLANK,RESET)| + PGRAPH_Def(INTR_0_RANGE,RESET)| + PGRAPH_Def(INTR_0_METHOD_COUNT,RESET)| + PGRAPH_Def(INTR_0_SOFTWARE,RESET)| + PGRAPH_Def(INTR_0_COMPLEX_CLIP,RESET)| + PGRAPH_Def(INTR_0_NOTIFY,RESET)); + + + /* Enable all interrupts except VBLANK */ + PGRAPH_Write(INTR_EN_0,PGRAPH_Def(INTR_EN_0_RESERVED,ENABLED)| + PGRAPH_Def(INTR_EN_0_CONTEXT_SWITCH,ENABLED)| + PGRAPH_Def(INTR_EN_0_VBLANK,DISABLED)| + PGRAPH_Def(INTR_EN_0_RANGE,ENABLED)| + PGRAPH_Def(INTR_EN_0_METHOD_COUNT,ENABLED)| + PGRAPH_Def(INTR_EN_0_SOFTWARE,ENABLED)| + PGRAPH_Def(INTR_EN_0_COMPLEX_CLIP,ENABLED)| + PGRAPH_Def(INTR_EN_0_NOTIFY,ENABLED)); + + PGRAPH_Write(INTR_1,PGRAPH_Def(INTR_1_METHOD,RESET)| + PGRAPH_Def(INTR_1_DATA,RESET)| + PGRAPH_Def(INTR_1_NOTIFY_INST,RESET)| + PGRAPH_Def(INTR_1_DOUBLE_NOTIFY,RESET)| + PGRAPH_Def(INTR_1_CTXSW_NOTIFY,RESET)); + + /* Don't care about any of this lot */ + PGRAPH_Write(INTR_EN_1,0); + + /* Reset the FIFO interrupt state */ + PFIFO_Write(INTR_0, PFIFO_Def(INTR_0_CACHE_ERROR,RESET)| + PFIFO_Def(INTR_0_RUNOUT,RESET)| + PFIFO_Def(INTR_0_RUNOUT_OVERFLOW,RESET)); + + PFIFO_Write(INTR_EN_0, PFIFO_Def(INTR_EN_0_CACHE_ERROR,ENABLED)| + PFIFO_Def(INTR_EN_0_RUNOUT,ENABLED)| + PFIFO_Def(INTR_EN_0_RUNOUT_OVERFLOW,ENABLED)); + + /* Switch on all the user devices in the master control */ + PMC_Write(ENABLE,PMC_Def(ENABLE_PAUDIO,ENABLED) | + PMC_Def(ENABLE_PDMA,ENABLED) | + PMC_Def(ENABLE_PFIFO,ENABLED) | + PMC_Def(ENABLE_PGRAPH,ENABLED) | + PMC_Def(ENABLE_PRM,ENABLED) | + PMC_Def(ENABLE_PFB,ENABLED)); + } + + static void ResetEngine(void) + { + /* Reset the graphics engine state machine */ + PGRAPH_Write(DEBUG_1,PGRAPH_Def(DEBUG_1_VOLATILE_RESET,LAST)); + PGRAPH_Write(DEBUG_0,PGRAPH_Def(DEBUG_0_STATE,RESET)); + } + + static void EnableChannel(void) + { + + /* Set context control */ + PGRAPH_Write(CTX_CONTROL,PGRAPH_Def(CTX_CONTROL_MINIMUM_TIME,2MS) | + PGRAPH_Def(CTX_CONTROL_TIME,EXPIRED) | + PGRAPH_Def(CTX_CONTROL_CHID,VALID) | + PGRAPH_Def(CTX_CONTROL_SWITCHING,IDLE) | + PGRAPH_Def(CTX_CONTROL_DEVICE,ENABLED)); + + + PGRAPH_Write(MISC,PGRAPH_Def(MISC_FLOWTHRU_WRITE,ENABLED) | + PGRAPH_Def(MISC_FLOWTHRU,ENABLED) | + PGRAPH_Def(MISC_FIFO_WRITE,ENABLED) | + PGRAPH_Def(MISC_FIFO,ENABLED) | + PGRAPH_Def(MISC_DMA_WRITE,ENABLED) | + PGRAPH_Def(MISC_DMA,ENABLED) | + PGRAPH_Def(MISC_CLASS_WRITE,IGNORED) | + PGRAPH_Val(MISC_CLASS, 0)); + } + + int SetupGraphicsEngine(int bpp) + { + graphicsEngineOk=1; + + WaitForIdle(); + /* Possibly enable the hardware engines here. Should already be on though */ + + DisableFifo(); + + EnableFlowThru(); + + ResetEngine(); + + EnableOptimisations(); + + InitDMAInstance(); + + ClearAndEnableInterrupts(); + + ClearOutContext(); + + ClearOutHashTables(); + + LoadChannelContext(); + + SetUpObjects(bpp); + + EnableChannel(); + + EnableFifo(); + + return graphicsEngineOk; + + } + + static int channelOpen=0; + + NvChannel *NvOpenChannel(void) + { + if(channelOpen) return NULL; + + channelOpen=1; + return (NvChannel*) nvCHAN0Port; + } + + /* Bit of future-proofing here */ + void NvCloseChannel(void) + { + channelOpen=0; + } + + void NvSync(void) + { + WaitForIdle(); + } + + /* This function checks to see if an interrupt has been raised, then + * prints out the appropriate registers so that you can attempt to + * figure out what is going on + * if you start mucking around with this chip this will happen a lot + */ + + + + #define CheckBit(var,device,bitfield) \ + if(var & device##_Mask(bitfield)) {\ + Info(#device"_"#bitfield" Set\n");\ + } + + + void NvCheckForErrors(void) + { + UINT32 val=PMC_Read(INTR_0); + /* Has an interrupt been raised ???? */ + /*if(val==0) return;*/ + /* Info("An Interrupt has been raised.\n");*/ + CheckBit(val,PMC,INTR_0_PAUDIO); + CheckBit(val,PMC,INTR_0_PDMA); + CheckBit(val,PMC,INTR_0_PFIFO); + CheckBit(val,PMC,INTR_0_PGRAPH); + CheckBit(val,PMC,INTR_0_PRM); + CheckBit(val,PMC,INTR_0_PTIMER); + CheckBit(val,PMC,INTR_0_PFB); + CheckBit(val,PMC,INTR_0_SOFTWARE); + + val=PGRAPH_Read(INTR_0); + CheckBit(val,PGRAPH,INTR_0_RESERVED); + CheckBit(val,PGRAPH,INTR_0_CONTEXT_SWITCH); + /* CheckBit(val,PGRAPH,INTR_0_VBLANK);*/ + CheckBit(val,PGRAPH,INTR_0_RANGE); + CheckBit(val,PGRAPH,INTR_0_METHOD_COUNT); + CheckBit(val,PGRAPH,INTR_0_SOFTWARE); + CheckBit(val,PGRAPH,INTR_0_COMPLEX_CLIP); + CheckBit(val,PGRAPH,INTR_0_NOTIFY); + + val=PFIFO_Read(INTR_0); + CheckBit(val,PFIFO,INTR_0_CACHE_ERROR); + CheckBit(val,PFIFO,INTR_0_RUNOUT); + CheckBit(val,PFIFO,INTR_0_RUNOUT_OVERFLOW); + } *** /dev/null Tue Jun 30 11:50:18 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/nvuser.h Fri Mar 6 16:52:30 1998 *************** *** 0 **** --- 1,265 ---- + /* $TOG: nvuser.h /main/1 1998/03/06 16:54:08 kaleb $ */ + /***************************************************************************\ + |* *| + |* Copyright (c) 1996-1998 NVIDIA, Corp. All rights reserved. *| + |* *| + |* NOTICE TO USER: The source code is copyrighted under U.S. and *| + |* international laws. NVIDIA, Corp. of Sunnyvale, California owns *| + |* the copyright and as design patents pending on the design and *| + |* interface of the NV chips. Users and possessors of this source *| + |* code are hereby granted a nonexclusive, royalty-free copyright *| + |* and design patent license to use this code in individual and *| + |* commercial software. *| + |* *| + |* Any use of this source code must include, in the user documenta- *| + |* tion and internal comments to the code, notices to the end user *| + |* as follows: *| + |* *| + |* Copyright (c) 1996-1998 NVIDIA, Corp. NVIDIA design patents *| + |* pending in the U.S. and foreign countries. *| + |* *| + |* NVIDIA, CORP. MAKES NO REPRESENTATION ABOUT THE SUITABILITY OF *| + |* THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" WITHOUT *| + |* EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORP. DISCLAIMS *| + |* ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, INCLUDING ALL *| + |* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *| + |* PARTICULAR PURPOSE. IN NO EVENT SHALL NVIDIA, CORP. BE LIABLE *| + |* FOR ANY SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, *| + |* OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR *| + |* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER *| + |* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR *| + |* PERFORMANCE OF THIS SOURCE CODE. *| + |* *| + \***************************************************************************/ + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/nvuser.h,v 1.1.2.2 1998/01/24 00:04:41 robin Exp $ */ + + #ifndef __NVUSER_H_ + #define __NVUSER_H_ + + /* Basic types */ + #ifndef XMD_H + typedef int INT32; + typedef short INT16; + #endif + + typedef unsigned UINT32; + typedef unsigned short UINT16; + + + + /* + * The first 256 bytes of each subchannel. + */ + typedef volatile struct { + UINT32 object; /* current object register 0000-0003*/ + UINT32 reserved01[0x003]; + UINT16 free; /* free count, only readable reg. 0010-0011*/ + UINT16 reserved02[0x001]; + UINT32 reserved03[0x003]; + UINT32 unimp01[4]; /* Don't implement lunatic password stuff */ + UINT32 unimp02[2]; /* Don't implement push/pop channel state */ + UINT32 reserved04[0x032]; + } NvControl; + + typedef volatile struct { + UINT32 unimp01; /* Was SetNotifyCtxDma */ + UINT32 unimp02; /* Was SetNotify */ + UINT32 reserved01[0x03e]; + UINT32 unimp03; /* Was SetRopOutput */ + UINT32 reserved02[0x03f]; + UINT32 setRop; /* 8-bit index to std. MS Win ROPs 0300-0303*/ + UINT32 reserved03[0x73f]; + } NvRopSolid; + + + typedef volatile struct { + UINT32 unimp01; /* Was SetNotifyCtxDma */ + UINT32 unimp02; /* Was SetNotify */ + UINT32 reserved01[0x03e]; + UINT32 unimp03; /* SetImageOutput */ + UINT32 reserved02[0x03f]; + UINT32 unimp04; /* SetColorFormat */ + UINT32 unimp05; /* SetMonochromeFormat */ + UINT32 setPatternShape; /* NV_PATTERN_SHAPE_{8X8,64X1,1X64}0308-030b*/ + UINT32 reserved03[0x001]; + UINT32 setColor0; /* "background" color where pat=0 0310-0313*/ + UINT32 setColor1; /* "foreground" color where pat=1 0314-0317*/ + struct { + UINT32 monochrome[2]; + } setPattern; /* 64 bits of pattern data 0318-031f*/ + UINT32 reserved04[0x738]; + } NvImagePattern; + + /* values for NV_IMAGE_PATTERN SetPatternShape() */ + #define NV_PATTERN_SHAPE_8X8 0 + #define NV_PATTERN_SHAPE_64X1 1 + #define NV_PATTERN_SHAPE_1X64 2 + + + typedef volatile struct { + UINT32 unimp01; /* Was SetNotifyCtxDma */ + UINT32 unimp02; /* SetNotify */ + UINT32 reserved01[0x03e]; + UINT32 unimp03; /* SetImageOutput */ + UINT32 reserved02[0x03f]; + struct { + UINT32 yx; /* S16_S16 in pixels, 0 at top left 00-04*/ + UINT32 heightWidth; /* U16_U16 in pixels 05-07*/ + } setRectangle; /* region in image where alpha=1 0300-0307*/ + UINT32 reserved03[0x73e]; + } NvClip,NvImageBlackRectangle; + + + typedef volatile struct { + UINT32 unimp01; /* SetNotifyCtxDma */ + UINT32 unimp02; /* SetNotify */ + UINT32 reserved01[0x03e]; + UINT32 unimp03; /* SetImageOutput */ + UINT32 reserved02[0x03f]; + UINT32 unimp04; /* SetColorFormat */ + UINT32 color; /* 0304-0307*/ + UINT32 reserved03[0x03e]; + struct { + UINT32 yx; /* S16_S16 in pixels, 0 at top left 00-03*/ + UINT32 heightWidth; /* U16_U16 in pixels 04-07*/ + } rectangle[16]; /* 0400-047f*/ + UINT32 reserved04[0x6e0]; + } NvRenderSolidRectangle; + + /***** Image Rendering Classes *****/ + + /* class NV_IMAGE_BLIT */ + #define NV_IMAGE_BLIT 31 + typedef volatile struct + tagNvImageBlit { + UINT32 unimp01; /* SetNotifyCtxDma */ + UINT32 unimp02; /* SetNotify */ + UINT32 reserved01[0x03e]; + UINT32 unimp03; /* SetImageOutput */ + UINT32 unimp04; /* SetImageInput */ + UINT32 reserved02[0x03e]; + UINT32 yxIn; /* S16_S16 in pixels, u.r. of src 300-0303*/ + UINT32 yxOut; /* S16_16 in pixels, u.r. of dest 0304-0307*/ + UINT32 heightWidth; /* U16_U16 in pixels 0308-030b*/ + UINT32 reserved03[0x73d]; + } NvImageBlit; + + #define NV_IMAGE_MONOCHROME_FROM_CPU 34 + typedef volatile struct + tagNvImageMonochromeFromCpu { + UINT32 unimp01; /* SetNotifyCtxDma */ + UINT32 unimp02; /* SetNotify */ + UINT32 reserved01[0x03e]; + UINT32 unimp03; /* SetImage Output */ + UINT32 reserved02[0x03f]; + UINT32 unimp04; /* SetColorFormat */ + UINT32 unimp05; /* SetMonochromeFormat */ + UINT32 color0; + UINT32 color1; + UINT32 point; + UINT32 size; + UINT32 sizeIn; + UINT32 reserved03[0x039]; + UINT32 monochrome[32]; + UINT32 reserved04[0x6e0]; + } NvImageMonochromeFromCpu; + + + #define NV_RENDER_SOLID_LINE 27 + typedef volatile struct { + UINT32 unimp01; + UINT32 unimp02; + UINT32 reserved01[0x03e]; + UINT32 unimp03; + UINT32 reserved02[0x03f]; + UINT32 unimp04; + UINT32 color; + UINT32 reserved03[0x03e]; + struct { + UINT32 y0_x0; + UINT32 y1_x1; + } line[16]; + struct { + INT32 x0; + INT32 y0; + INT32 x1; + INT32 y1; + } line32[8]; + UINT32 polyLine[32]; + struct { + INT32 x; + INT32 y; + } polyLine32[16]; + struct { + UINT32 color; + UINT32 y_x; + } colorPolyLine[16]; + UINT32 reserved04[0x660]; + } NvRenderSolidLine; + + typedef struct { + NvControl control; + union { + NvRopSolid ropSolid; + NvImagePattern imagePattern; + NvClip clip; + NvRenderSolidRectangle renderSolidRectangle; + NvImageBlit blit; + NvImageMonochromeFromCpu imageMonochromeFromCpu; + NvRenderSolidLine line; + }method; + }NvSubChannel; + + /* A channel consists of 8 subchannels */ + typedef struct { + NvSubChannel subChannel[8]; + } NvChannel; + + + + /* Used to load 16 bit values into a packed 32 value */ + /* We must do the AND */ + #define PACK_INT16(y,x) (((((UINT32)(y))<<16))| ((x)&0xffff)) + /* For unsigned 16 bits we don't need to AND. Make sure the X coord + * can never be negative or strange things will happen + */ + #define PACK_UINT16(y,x) ((((y)<<16))|(x)) + + #define MAX_UINT16 0xffff + #define MAX_INT16 0x7fff + + + /* These are the objects that are hard coded into the driver. + * DON'T USE ANYTHING OTHER THAN THESE NUMBERS + * YOU WILL LOCK THE GRAPHICS ENGINE UP + */ + + /* "Control" objects */ + #define ROP_OBJECT_ID 0x99000000 + #define CLIP_OBJECT_ID 0x99000001 + #define PATTERN_OBJECT_ID 0x99000002 + + /* Rendering objects */ + #define RECT_OBJECT_ID 0x88000000 + #define BLIT_OBJECT_ID 0x88000001 + #define COLOUR_EXPAND_OBJECT_ID 0x88000002 + #define LINE_OBJECT_ID 0x88000003 + #define LIN_OBJECT_ID 0x88000004 + + /* Maps the user channel into the address space of the client */ + /* NULL on failure */ + NvChannel * NvOpenChannel(void); + + /* Shuts down the channel */ + void NvCloseChannel(void); + + /* Checks to see if an interrupt has been raised */ + void NvCheckForErrors(void); + + /* How much ram is reserved by the graphics hardware. + * Returns amount used in KiloBytes + */ + int NvKbRamUsedByHW(void); + + #endif *** /dev/null Tue Jun 30 11:50:19 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/nvvga.h Fri Mar 6 16:52:35 1998 *************** *** 0 **** --- 1,103 ---- + /* $TOG: nvvga.h /main/1 1998/03/06 16:54:12 kaleb $ */ + /* + * Copyright 1996-1997 David J. McKay + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * DAVID J. MCKAY BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/nvvga.h,v 1.1.2.2 1998/01/24 00:04:41 robin Exp $ */ + + #ifndef __NVVGA_H__ + #define __NVVGA_H__ + + #define PALETTE_SIZE 256 + + #if 1 + #define NV_PDAC_CURSOR_SIZE 32 + #define NV_PDAC_CURSOR_PLANE_SIZE (NV_PDAC_CURSOR_SIZE*4) + + /* This is the structure for the NV1. It is not a VGA based core */ + + typedef struct { + unsigned char Nparam, Mparam, Oparam, Pparam; + unsigned char NparamMPLL, MparamMPLL, OparamMPLL, PparamMPLL; + unsigned char dacConfReg0; + unsigned char dacConfReg1; + unsigned char dacRgbPalCtrl; + unsigned long confReg0; + unsigned long green0; /* DPMS and sync polarity control */ + unsigned long memoryTrace; + unsigned long startAddr; /* Where to start reading out from the buffer */ + /* All the following registers control the display */ + unsigned long prmConfig0; /* Controls if text mode on or off */ + unsigned long horFrontPorch; /* Front porch in pixels */ + unsigned long horSyncWidth; /* Sync Width in pixels */ + unsigned long horBackPorch; /* horizontal back porch in in pixels */ + unsigned long horDispWidth; /* Horizontal display width in pixels */ + unsigned long verFrontPorch; /* Vertical front porch in lines */ + unsigned long verSyncWidth; /* Vertical sync width in lines */ + unsigned long verBackPorch; /* Vertical back porch in lines */ + unsigned long verDispWidth; /* Vertical display width in lines */ + /* Hardware cursor registers */ + unsigned char cursorCtrl; + unsigned char xHi,xLo,yHi,yLo; + unsigned char colour1[3]; /* RGB values for cursor planes */ + unsigned char colour2[3]; + unsigned char colour3[3]; + unsigned char plane0[NV_PDAC_CURSOR_PLANE_SIZE]; + unsigned char plane1[NV_PDAC_CURSOR_PLANE_SIZE]; + unsigned char palette[PALETTE_SIZE][3]; + }NV1Registers; + #endif + + + /* This is for the NV3, AKA RIVA128. It does have a VGA core, so + * fits into the SVGA server much easier than the NV1 does + */ + typedef struct { + unsigned char offset, + repaint0, + repaint1, + screenExtra, + pixelFormat, + horizExtra, + fifoControl, + fifo; + + unsigned long vpllCoeff, + config0, + coeffSelect, + generalControl; + }NV3Registers; + + /* + * Driver data structures. + */ + typedef struct { + vgaHWRec std; /* good old IBM VGA */ + int vgaValid; /* is the above state valid?? */ + NVChipType type; /* What the union holds */ + union { + NV1Registers nv1; + NV3Registers nv3; + }regs; + } vgaNVRec, *vgaNVPtr; + + + #endif *** /dev/null Tue Jun 30 11:50:20 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/README.NV1 Fri Mar 6 16:51:21 1998 *************** *** 0 **** --- 1,30 ---- + $TOG: README.NV1 /main/1 1998/03/06 16:52:59 kaleb $ + + + + $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/README.NV1,v 1.1.2.2 1998/01/24 00:04:36 robin Exp $ + + + XFree driver for NVidia NV1 / SGS-Thomson STG2000 + ================================================= + + This driver now accelerates bitblits,filled rectangles and colour expansion. + It also support a hardware cursor. + + More graphic acceleration is planned. There is no plan to support the audio + functionality of the chip. + + Notes + ----- + + * THE DRIVER DOES NOT SUPPORT THE VIRTUAL DESKTOP FEATURES OF XFREE86 + This is because the NV1 does not have the necessary hardware to support this + feature. If you want to change resolutions, you will have to modify your + config file. Comment out all but the mode you wish to use. + + Known Bugs + ---------- + + * Problems with certain Cyrix chips. + + *** /dev/null Tue Jun 30 11:50:21 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/README.RIVA128 Fri Mar 6 16:51:25 1998 *************** *** 0 **** --- 1,33 ---- + $TOG: README.RIVA128 /main/1 1998/03/06 16:53:03 kaleb $ + + + + $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/README.RIVA128,v 1.1.2.2 1998/01/24 00:04:36 robin Exp $ + + XFree driver for NVidia/SGS-Thomson RIVA128 + =========================================== + + This driver now accelerates bitblits,filled rectangles and colour expansion. + It also support a hardware cursor. + + Note that requesting 16bpp actually gives 15bpp. This is because the RIVA128 + cannot accelerate many functions at 565 colour depth. If you put + "option noaccel" in the config file then 565 will be available - but without + acceleration of course. + + Known Bugs + ========== + + * Pixel noise at high resolution in 32bpp + + Thanks + ====== + + Thanks to Chris Cox of STB systems for supplying a board. + Also many thanks to Curtis,Dwight and Don at Nvidia for their help and support. + + + Dave McKay + January 1998 + + *** /dev/null Tue Jun 30 11:50:22 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/README.tech Fri Mar 6 16:51:29 1998 *************** *** 0 **** --- 1,63 ---- + $TOG: README.tech /main/1 1998/03/06 16:53:07 kaleb $ + + + + $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/README.tech,v 1.1.2.2 1998/01/24 00:04:37 robin Exp $ + + Brief technical note on the NV1 + ------------------------------- + + This document attempts to explain some of the technical features of the NV1. + + Central to the chip is the concept that user-space programs should be allowed + to have direct access to the chip. To enable this, the chip supports the + concepts of "channels". Each application that wants to draw to screen is + given a channel which allows it to perform graphics operations by writing to + specified locations. Each channel is a 64K region of memory mapped registers, + divided into 8 identical subchannels. The NV1 supports 128 channels in total. + + Each channel can be mapped to a specific area of the screen. All coordinates + supplied by the application are relative to this, the application doesn't + actually know where on the screen it's window is mapped. The chip also + supports clipping of this region, with multiple clip regions. If the number of + clip regions is exceeded then the object has to be drawn multiple times, + changing the clip regions for each invocation to ensure the correct clipping + behaviour. + + Another feature of the chip is that all drawing is done via objects. For + example, if I want to draw a rectangle, I create a rectangle object. Each + object is given a unique 32 bit id. To actually draw a rectangle, I would load + the rectangle object id into the subchannel, and then write the + coordinates. The chip will add these coordinates to the channel's window offset + to get the real screen coordinates, handle clipping, and then finally draw the + rectangle. + + Each object has data associated with it, which specifies how to configure + the graphics hardware for that operation. The hardware has a hash table to + perform look up of objects. If you load a different object into the subchannel + then the hardware will look at the hash table for that id number and load the + associated data for that object into the graphics hardware. + + Software is needed to control this functionality. If the subchannel is loaded + with an object that isn't in the hash table, an interrupt is raised. + Software will be expected to load the appropriate object into the hash + table and restart the drawing operation. + + Also, if multiple channels are drawing at the same time, the hardware will + multiplex between them. An interrupt will be raised when a context switch is + needed and the software will be expected to load the state for the channel to + be swapped to and restart drawing. + + In the case of XFree86, since the driver cannot handle interrupts as it + is not part of the kernel, we have to be extremely careful not to raise an + interrupt, as the chip will not do anything until the interrupt is dealt + with. It also means that we can only ever use one channel, and cannot + do any operations which require DMA such as host memory to screen blits, + the 3D texture mapping, or any of the sound functionality. If these features + are to be supported the driver will need to be moved into the kernel. + + For more details, download Nvidia's NVlib SDK. + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/README.tech,v 1.1.2.2 1998/01/24 00:04:37 robin Exp $ */ *** ./programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/Imakefile@@/PUBLIC-LATEST Sat Jul 19 10:43:49 1997 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/Imakefile Fri Mar 6 16:52:43 1998 *************** *** 1,22 **** ! XCOMM $TOG: Imakefile /main/7 1997/07/19 10:43:51 kaleb $ - XCOMM $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/Imakefile,v 3.5 1996/12/23 06:58:21 dawes Exp $ #include <Server.tmpl> ! SRCS = s3_driver.c s3_bank.s ! OBJS = s3_driver.o s3_bank.o #if XF86LinkKit INCLUDES = -I. -I../../../include -I../../../include/X11 -I../.. #else INCLUDES = -I. -I$(XF86COMSRC) -I$(XF86HWSRC) -I$(XF86OSSRC) \ ! -I../../vga -I$(SERVERSRC)/include \ ! -I$(XINCLUDESRC) #endif #if MakeHasPosixVariableSubstitutions --- 1,27 ---- ! XCOMM $TOG: Imakefile /main/8 1998/03/06 16:54:20 kaleb $ + XCOMM $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/Imakefile,v 3.5.2.2 1998/02/24 13:54:26 hohndel Exp $ #include <Server.tmpl> ! SRCS = s3driver.c s3probe.c s3BtCursor.c s3ELSA.c s3ramdacs.c s3init.c \ ! s3fbinit.c s3save.c s3TiCursor.c Ti3026Curs.c s3misc.c \ ! s3cursor.c IBMRGBCurs.c s3accel_pio.c s3accel_newmmio.c s3bank.s ! OBJS = s3driver.o s3probe.o s3BtCursor.o s3ELSA.o s3ramdacs.o s3init.o \ ! s3fbinit.o s3save.o s3TiCursor.o Ti3026Curs.o s3misc.o \ ! s3cursor.o IBMRGBCurs.o s3accel_pio.o s3accel_newmmio.o s3bank.o #if XF86LinkKit INCLUDES = -I. -I../../../include -I../../../include/X11 -I../.. #else INCLUDES = -I. -I$(XF86COMSRC) -I$(XF86HWSRC) -I$(XF86OSSRC) \ ! -I$(XF86SRC)/vga256/vga -I$(SERVERSRC)/include \ ! -I$(XINCLUDESRC) -I$(SERVERSRC)/mi -I$(XF86SRC)/xaa \ ! -I$(FONTINCSRC) -I$(SERVERSRC)/cfb -I$(SERVERSRC)/mfb #endif #if MakeHasPosixVariableSubstitutions *************** *** 24,34 **** #endif NormalLibraryObjectRule() NormalAsmObjectRule() ! NormalRelocatableTarget(s3_drv, $(OBJS)) ! InstallLinkKitNonExecFile(s3_driver.c,$(LINKKITDIR)/drivers/vga256/s3_svga) ! InstallLinkKitNonExecFile(s3_bank.s,$(LINKKITDIR)/drivers/vga256/s3_svga) InstallLinkKitNonExecFile(Imakefile,$(LINKKITDIR)/drivers/vga256/s3_svga) DependTarget() --- 29,59 ---- #endif NormalLibraryObjectRule() NormalAsmObjectRule() + NormalRelocatableTarget(s3_svga_drv, $(OBJS)) ! ObjectFromSpecialSource(s3accel_pio, s3accel, -DS3_GENERIC) ! ObjectFromSpecialSource(s3accel_newmmio, s3accel, -DS3_NEWMMIO) ! InstallLinkKitNonExecFile(newmmio.h,$(LINKKITDIR)/drivers/vga256/s3_svga) ! InstallLinkKitNonExecFile(s3.h,$(LINKKITDIR)/drivers/vga256/s3_svga) ! InstallLinkKitNonExecFile(s3Bt485.h,$(LINKKITDIR)/drivers/vga256/s3_svga) ! InstallLinkKitNonExecFile(s3ELSA.h,$(LINKKITDIR)/drivers/vga256/s3_svga) ! InstallLinkKitNonExecFile(s3reg.h,$(LINKKITDIR)/drivers/vga256/s3_svga) ! InstallLinkKitNonExecFile(IBMRGBCurs.c,$(LINKKITDIR)/drivers/vga256/s3_svga) ! InstallLinkKitNonExecFile(Ti3026Curs.c,$(LINKKITDIR)/drivers/vga256/s3_svga) ! InstallLinkKitNonExecFile(s3BtCursor.c,$(LINKKITDIR)/drivers/vga256/s3_svga) ! InstallLinkKitNonExecFile(s3ELSA.c,$(LINKKITDIR)/drivers/vga256/s3_svga) ! InstallLinkKitNonExecFile(s3TiCursor.c,$(LINKKITDIR)/drivers/vga256/s3_svga) ! InstallLinkKitNonExecFile(s3accel.c,$(LINKKITDIR)/drivers/vga256/s3_svga) ! InstallLinkKitNonExecFile(s3cursor.c,$(LINKKITDIR)/drivers/vga256/s3_svga) ! InstallLinkKitNonExecFile(s3driver.c,$(LINKKITDIR)/drivers/vga256/s3_svga) ! InstallLinkKitNonExecFile(s3fbinit.c,$(LINKKITDIR)/drivers/vga256/s3_svga) ! InstallLinkKitNonExecFile(s3init.c,$(LINKKITDIR)/drivers/vga256/s3_svga) ! InstallLinkKitNonExecFile(s3misc.c,$(LINKKITDIR)/drivers/vga256/s3_svga) ! InstallLinkKitNonExecFile(s3probe.c,$(LINKKITDIR)/drivers/vga256/s3_svga) ! InstallLinkKitNonExecFile(s3ramdacs.c,$(LINKKITDIR)/drivers/vga256/s3_svga) ! InstallLinkKitNonExecFile(s3save.c,$(LINKKITDIR)/drivers/vga256/s3_svga) ! InstallLinkKitNonExecFile(s3bank.s,$(LINKKITDIR)/drivers/vga256/s3_svga) InstallLinkKitNonExecFile(Imakefile,$(LINKKITDIR)/drivers/vga256/s3_svga) DependTarget() *** ./programs/Xserver/hw/xfree86/vga256/drivers/sis/sis86c201.c@@/PUBLIC-LATEST Tue Nov 11 15:46:53 1997 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/sis/sis86c201.c Sat Mar 7 16:31:30 1998 *************** *** 1,4 **** ! /* $TOG: sis86c201.c /main/15 1997/11/11 15:46:55 msr $ */ /* * Copyright 1995 by Alan Hourihane, Wigan, England. * --- 1,4 ---- ! /* $TOG: sis86c201.c /main/17 1998/03/07 16:33:11 kaleb $ */ /* * Copyright 1995 by Alan Hourihane, Wigan, England. * *************** *** 585,591 **** /* We support Direct Video Access */ vga256InfoRec.directMode = XF86DGADirectPresent; #endif - /* MaxClock set at 90MHz for 256 - ??? */ OFLG_SET(OPTION_HW_CURSOR, &SIS.ChipOptionFlags); --- 585,590 ---- *** ./programs/Xserver/hw/xfree86/vga256/drivers/tvga8900/t89_driver.c@@/PUBLIC-LATEST Sun Aug 10 13:06:52 1997 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/tvga8900/t89_driver.c Fri Mar 6 16:55:01 1998 *************** *** 1,4 **** ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/tvga8900/t89_driver.c,v 3.66.2.13 1997/07/26 06:30:57 dawes Exp $ */ /* * Copyright 1992 by Alan Hourihane, Wigan, England. * --- 1,4 ---- ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/tvga8900/t89_driver.c,v 3.66.2.19 1998/02/26 13:59:12 dawes Exp $ */ /* * Copyright 1992 by Alan Hourihane, Wigan, England. * *************** *** 51,57 **** * Massimiliano Ghilardi, max@Linuz.sns.it, some fixes to the * clockchip programming code. */ ! /* $TOG: t89_driver.c /main/35 1997/08/10 13:05:27 kaleb $ */ #include "X.h" #include "input.h" --- 51,57 ---- * Massimiliano Ghilardi, max@Linuz.sns.it, some fixes to the * clockchip programming code. */ ! /* $TOG: t89_driver.c /main/36 1998/03/06 16:56:39 kaleb $ */ #include "X.h" #include "input.h" *************** *** 126,133 **** unsigned char DRAMTiming; /* For 9400/9420/9430 DRAM */ unsigned char FIFOControl; /* For 9400/9420/9430 FIFO */ unsigned char Performance; /* For 968x FIFO */ - unsigned char DispLat; /* For Display Latency for 96xx */ unsigned char ClockControl; /* For 16bit/10bit Clocks */ } vgaTVGA8900Rec, *vgaTVGA8900Ptr; static Bool TVGA8900ClockSelect(); --- 126,136 ---- unsigned char DRAMTiming; /* For 9400/9420/9430 DRAM */ unsigned char FIFOControl; /* For 9400/9420/9430 FIFO */ unsigned char Performance; /* For 968x FIFO */ unsigned char ClockControl; /* For 16bit/10bit Clocks */ + unsigned char TVinterface; /* For 9685 TVinterface */ + unsigned char TVMode; /* For 9685 TVmode */ + unsigned char VSPS; + unsigned char VSP; } vgaTVGA8900Rec, *vgaTVGA8900Ptr; static Bool TVGA8900ClockSelect(); *************** *** 193,199 **** int tridentHWCursorType = 0; int tridentDisplayWidth; int tridentDACtype = -1; ! int GE_OP; Bool tridentHasAcceleration = FALSE; Bool tridentUseLinear = FALSE; Bool tridentTGUIProgrammableClocks = FALSE; --- 196,202 ---- int tridentHWCursorType = 0; int tridentDisplayWidth; int tridentDACtype = -1; ! int GE_OP = 0; Bool tridentHasAcceleration = FALSE; Bool tridentUseLinear = FALSE; Bool tridentTGUIProgrammableClocks = FALSE; *************** *** 201,210 **** --- 204,216 ---- Bool tridentLinearOK = FALSE; Bool IsCyber = FALSE; Bool NewClockCode = FALSE; + Bool ClearTV = FALSE; + Bool TVconnected = FALSE; static int CyberLCDHeight, CyberLCDWidth; static unsigned char DRAMspeed; static int TridentDisplayableMemory; unsigned char *tguiMMIOBase = NULL; + Bool ClipOn = FALSE; static unsigned TGUI_ExtPorts[] = { 0x210A, 0x210C, 0x210D, 0x210E, 0x210F, /* For Old GE */ *************** *** 271,276 **** --- 277,284 ---- TGUISetClock(no) int no; { + #define NTSC 14.31818 + #define PAL 17.73448 int powerup[4] = { 1,2,4,8 }; int clock_diff = 750; int freq, ffreq; *************** *** 278,287 **** --- 286,308 ---- int p, q, r, s; int startn, endn; int endm, endk; + float FREQUENCY; unsigned char temp; p = q = r = s = 0; + if (ClearTV) + { + outb(vgaIOBase + 4, 0xC0); + temp = inb(vgaIOBase + 5); + if (temp & 0x80) + FREQUENCY = PAL; + else + FREQUENCY = NTSC; + } else { + FREQUENCY = NTSC; + } + if (NewClockCode) { startn = 64; *************** *** 291,297 **** } else { ! startn = 1; endn = 121; endm = 31; endk = 1; --- 312,318 ---- } else { ! startn = 0; endn = 121; endm = 31; endk = 1; *************** *** 299,316 **** freq = vga256InfoRec.clock[no]; ! if ((vgaBitsPerPixel == 16) && (TVGAchipset <= TGUI9320LCD)) freq *= 2; if (vgaBitsPerPixel == 32) freq *= 2; - if (vgaBitsPerPixel == 24) - freq *= 3; for (k=0;k<=endk;k++) for (n=startn;n<=endn;n++) for (m=1;m<=endm;m++) { ! ffreq = ( ( ((n + 8) * 14.31818) / ((m + 2) * powerup[k]) ) * 1000); if ((ffreq > freq - clock_diff) && (ffreq < freq + clock_diff)) { /* --- 320,337 ---- freq = vga256InfoRec.clock[no]; ! if ((vgaBitsPerPixel == 16) && (TVGAchipset <= CYBER9320)) freq *= 2; + if ((TVGAchipset < TGUI96xx) && (vgaBitsPerPixel == 24)) + freq *= 3; if (vgaBitsPerPixel == 32) freq *= 2; for (k=0;k<=endk;k++) for (n=startn;n<=endn;n++) for (m=1;m<=endm;m++) { ! ffreq = ( ( ((n + 8) * FREQUENCY) / ((m + 2) * powerup[k]) ) * 1000); if ((ffreq > freq - clock_diff) && (ffreq < freq + clock_diff)) { /* *************** *** 367,377 **** "tvga8900c", "tvga8900cl", "tvga8900d", "tvga9000", "tvga9000i", "tvga9100b", ! "tvga9200cxr", "tgui9320lcd", "tgui9400cxi", "tgui9420", "tgui9420dgi", "tgui9430dgi", ! "tgui9440agi", "tgui96xx", ! "cyber938x", }; if (n + 1 > sizeof(chipsets) / sizeof(char *)) --- 388,401 ---- "tvga8900c", "tvga8900cl", "tvga8900d", "tvga9000", "tvga9000i", "tvga9100b", ! "tvga9200cxr", "tgui9400cxi", "tgui9420", "tgui9420dgi", "tgui9430dgi", ! "tgui9440agi", "cyber9320", ! "tgui9660", "tgui9680", "tgui9682", ! "tgui9685", "cyber9382", "cyber9385", ! "cyber9388", "cyber9397", "cyber9520", ! "3dimage975", "3dimage985" }; if (n + 1 > sizeof(chipsets) / sizeof(char *)) *************** *** 495,508 **** --- 519,537 ---- #ifdef PC98_TGUI OFLG_SET(OPTION_PC98TGUI, &TVGA8900.ChipOptionFlags); + xf86ClearIOPortList(vga256InfoRec.scrnIndex); + xf86AddIOPorts(vga256InfoRec.scrnIndex, Num_VGA_IOPorts, VGA_IOPorts); + xf86EnableIOPorts(vga256InfoRec.scrnIndex); if( BoardInit() == FALSE ) return(FALSE); #endif + #ifndef PC98_TGUI /* * Set up I/O ports to be used by this card */ xf86ClearIOPortList(vga256InfoRec.scrnIndex); xf86AddIOPorts(vga256InfoRec.scrnIndex, Num_VGA_IOPorts, VGA_IOPorts); + #endif if (vga256InfoRec.chipset) { *************** *** 536,560 **** else if (!StrCaseCmp(vga256InfoRec.chipset, TVGA8900Ident(9))) TVGAchipset = TVGA9200CXr; else if (!StrCaseCmp(vga256InfoRec.chipset, TVGA8900Ident(10))) - TVGAchipset = TGUI9320LCD; - else if (!StrCaseCmp(vga256InfoRec.chipset, TVGA8900Ident(11))) TVGAchipset = TGUI9400CXi; ! else if (!StrCaseCmp(vga256InfoRec.chipset, TVGA8900Ident(12))) TVGAchipset = TGUI9420; ! else if (!StrCaseCmp(vga256InfoRec.chipset, TVGA8900Ident(13))) TVGAchipset = TGUI9420DGi; ! else if (!StrCaseCmp(vga256InfoRec.chipset, TVGA8900Ident(14))) TVGAchipset = TGUI9430DGi; ! else if (!StrCaseCmp(vga256InfoRec.chipset, TVGA8900Ident(15))) TVGAchipset = TGUI9440AGi; else if (!StrCaseCmp(vga256InfoRec.chipset, TVGA8900Ident(16))) ! TVGAchipset = TGUI96xx; else if (!StrCaseCmp(vga256InfoRec.chipset, TVGA8900Ident(17))) { ! TVGAchipset = TGUI96xx; IsCyber = TRUE; NewClockCode = TRUE; } else return(FALSE); TVGA8900EnterLeave(ENTER); --- 565,636 ---- else if (!StrCaseCmp(vga256InfoRec.chipset, TVGA8900Ident(9))) TVGAchipset = TVGA9200CXr; else if (!StrCaseCmp(vga256InfoRec.chipset, TVGA8900Ident(10))) TVGAchipset = TGUI9400CXi; ! else if (!StrCaseCmp(vga256InfoRec.chipset, TVGA8900Ident(11))) TVGAchipset = TGUI9420; ! else if (!StrCaseCmp(vga256InfoRec.chipset, TVGA8900Ident(12))) TVGAchipset = TGUI9420DGi; ! else if (!StrCaseCmp(vga256InfoRec.chipset, TVGA8900Ident(13))) TVGAchipset = TGUI9430DGi; ! else if (!StrCaseCmp(vga256InfoRec.chipset, TVGA8900Ident(14))) TVGAchipset = TGUI9440AGi; + else if (!StrCaseCmp(vga256InfoRec.chipset, TVGA8900Ident(15))) + { + TVGAchipset = CYBER9320; + IsCyber = TRUE; + } else if (!StrCaseCmp(vga256InfoRec.chipset, TVGA8900Ident(16))) ! TVGAchipset = TGUI9660; else if (!StrCaseCmp(vga256InfoRec.chipset, TVGA8900Ident(17))) + TVGAchipset = TGUI9680; + else if (!StrCaseCmp(vga256InfoRec.chipset, TVGA8900Ident(18))) + TVGAchipset = TGUI9682; + else if (!StrCaseCmp(vga256InfoRec.chipset, TVGA8900Ident(19))) + TVGAchipset = TGUI9685; + else if (!StrCaseCmp(vga256InfoRec.chipset, TVGA8900Ident(20))) { ! TVGAchipset = CYBER9382; IsCyber = TRUE; NewClockCode = TRUE; } + else if (!StrCaseCmp(vga256InfoRec.chipset, TVGA8900Ident(21))) + { + TVGAchipset = CYBER9385; + IsCyber = TRUE; + NewClockCode = TRUE; + } + else if (!StrCaseCmp(vga256InfoRec.chipset, TVGA8900Ident(22))) + { + TVGAchipset = CYBER9388; + IsCyber = TRUE; + NewClockCode = TRUE; + } + else if (!StrCaseCmp(vga256InfoRec.chipset, TVGA8900Ident(23))) + { + TVGAchipset = CYBER9397; + IsCyber = TRUE; + NewClockCode = TRUE; + tridentHasAcceleration = FALSE; + } + else if (!StrCaseCmp(vga256InfoRec.chipset, TVGA8900Ident(24))) + { + TVGAchipset = CYBER9520; + IsCyber = TRUE; + NewClockCode = TRUE; + tridentHasAcceleration = FALSE; + } + else if (!StrCaseCmp(vga256InfoRec.chipset, TVGA8900Ident(25))) + { + TVGAchipset = IMAGE975; + NewClockCode = TRUE; + tridentHasAcceleration = FALSE; + } + else if (!StrCaseCmp(vga256InfoRec.chipset, TVGA8900Ident(26))) + { + TVGAchipset = IMAGE985; + NewClockCode = TRUE; + tridentHasAcceleration = FALSE; + } else return(FALSE); TVGA8900EnterLeave(ENTER); *************** *** 659,665 **** TVGAName = "TGUI9400CXi"; break; case 0xA3: ! TVGAchipset = TGUI9320LCD; TVGAName = "Cyber9320"; break; case 0xD3: --- 735,741 ---- TVGAName = "TGUI9400CXi"; break; case 0xA3: ! TVGAchipset = CYBER9320; TVGAName = "Cyber9320"; break; case 0xD3: *************** *** 677,682 **** --- 753,799 ---- default: TVGAName = "UNKNOWN"; } + if (vgaPCIInfo && vgaPCIInfo->Vendor == PCI_VENDOR_TRIDENT) + { + switch (vgaPCIInfo->ChipType) { + case PCI_CHIP_9320: + TVGAchipset = CYBER9320; + TVGAName = "Cyber9320"; + break; + case PCI_CHIP_9420: + TVGAchipset = TGUI9420; + TVGAName = "TGUI9420"; + break; + case PCI_CHIP_9440: + TVGAchipset = TGUI9440AGi; + TVGAName = "TGUI9440AGi"; + break; + case PCI_CHIP_9660: + TVGAchipset = TGUI96xx; + TVGAName = "TGUI96xx"; + break; + case PCI_CHIP_9388: + TVGAchipset = CYBER9388; + TVGAName = "Cyber9388"; + break; + case PCI_CHIP_9397: + TVGAchipset = CYBER9397; + TVGAName = "Cyber9397"; + break; + case PCI_CHIP_9520: + TVGAchipset = CYBER9520; + TVGAName = "Cyber9520"; + break; + case PCI_CHIP_9750: + TVGAchipset = IMAGE975; + TVGAName = "3DImage975"; + break; + case PCI_CHIP_9850: + TVGAchipset = IMAGE985; + TVGAName = "3DImage985"; + break; + } + } ErrorF("%s Trident chipset version: 0x%02x (%s)\n", XCONFIG_PROBED, temp, TVGAName); if (TreatAs != (char *)NULL) *************** *** 716,722 **** tridentDACtype = TKD8001; TVGA8900.ChipHas16bpp = TRUE; break; ! case TGUI9320LCD: tridentIsTGUI = TRUE; tridentLinearOK = TRUE; tridentDACtype = TGUIDAC; --- 833,839 ---- tridentDACtype = TKD8001; TVGA8900.ChipHas16bpp = TRUE; break; ! case CYBER9320: tridentIsTGUI = TRUE; tridentLinearOK = TRUE; tridentDACtype = TGUIDAC; *************** *** 772,779 **** --- 889,907 ---- #endif break; case TGUI96xx: + case TGUI9680: + case TGUI9682: + case TGUI9685: + case CYBER9382: + case CYBER9385: + case CYBER9388: + case CYBER9397: + case CYBER9520: tridentHasAcceleration = TRUE; TVGA8900.ChipHas16bpp = TRUE; + TVGA8900.ChipHas24bpp = TRUE; + if (vgaBitsPerPixel == 24) + tridentHasAcceleration = FALSE; TVGA8900.ChipHas32bpp = TRUE; /* We've found a 96xx graphics engine */ /* Let's probe furthur */ *************** *** 780,818 **** switch (revision) { case 0x00: REV = "9660"; break; case 0x01: REV = "9680"; break; case 0x10: REV = "ProVidia 9682"; break; case 0x21: REV = "ProVidia 9685"; NewClockCode = TRUE; ! /* Disable for now, bugs ! */ ! if (vgaBitsPerPixel == 32) ! tridentHasAcceleration = FALSE; break; case 0x30: case 0x33: /* Guessing */ case 0x34: case 0xB3: REV = "9385"; IsCyber = TRUE; break; case 0x38: REV = "9385-1"; IsCyber = TRUE; break; case 0x40: case 0x42: /* Guessing */ REV = "9382"; ! IsCyber = TRUE; break; case 0x50: REV = "ProVidia 9692"; break; default: REV = "Unknown ID - Please report to trident@xfree86.org"; break; --- 908,969 ---- switch (revision) { case 0x00: REV = "9660"; + TVGAchipset = TGUI9660; break; case 0x01: REV = "9680"; + TVGAchipset = TGUI9680; break; case 0x10: REV = "ProVidia 9682"; + TVGAchipset = TGUI9682; break; case 0x21: REV = "ProVidia 9685"; + TVGAchipset = TGUI9685; NewClockCode = TRUE; ! ClearTV = TRUE; ! OFLG_SET(OPTION_PCI_RETRY, &TVGA8900.ChipOptionFlags); ! TVGA8900.ChipHas24bpp = FALSE; ! TVGA8900.ChipHas32bpp = FALSE; break; + case 0x22: + case 0x23: + REV = "Cyber 9397"; + TVGAchipset = CYBER9397; + tridentHasAcceleration = FALSE; + NewClockCode = TRUE; + IsCyber = TRUE; + break; case 0x30: case 0x33: /* Guessing */ case 0x34: + case 0x35: case 0xB3: REV = "9385"; + TVGAchipset = CYBER9385; + NewClockCode = TRUE; IsCyber = TRUE; break; + case 0x3A: case 0x38: REV = "9385-1"; + TVGAchipset = CYBER9385; + NewClockCode = TRUE; IsCyber = TRUE; break; case 0x40: case 0x42: /* Guessing */ REV = "9382"; ! TVGAchipset = CYBER9382; ! NewClockCode = TRUE; break; case 0x50: REV = "ProVidia 9692"; break; + TVGAchipset = TGUI9685; + NewClockCode = TRUE; + break; default: REV = "Unknown ID - Please report to trident@xfree86.org"; break; *************** *** 832,841 **** --- 983,1006 ---- TVGA8900.ChipUse2Banks = TRUE; #endif break; + case IMAGE975: + case IMAGE985: + tridentIsTGUI = TRUE; + tridentLinearOK = TRUE; + tridentHasAcceleration = FALSE; + tridentTGUIProgrammableClocks = TRUE; + tridentDACtype = TGUIDAC; + tridentHWCursorType = 1; + TVGA8900.ChipHas16bpp = TRUE; + TVGA8900.ChipHas24bpp = TRUE; + TVGA8900.ChipHas32bpp = TRUE; + break; } if (IsCyber) { + /* Allow Shadow register switch */ + OFLG_SET(OPTION_CYBER_SHADOW, &TVGA8900.ChipOptionFlags); /* Allow stretch mode on LCD */ OFLG_SET(OPTION_LCD_STRETCH, &TVGA8900.ChipOptionFlags); /* Allow LCD centering */ *************** *** 883,888 **** --- 1048,1083 ---- ErrorF("%s %s: Revision %d.\n", XCONFIG_PROBED, vga256InfoRec.name, revision); + if (ClearTV) + { + unsigned char TVinterface; + + OFLG_SET(OPTION_TGUI_TVOUT, &TVGA8900.ChipOptionFlags); + + outb(vgaIOBase + 4, 0xC0); + TVinterface = inb(vgaIOBase + 5); + + ErrorF("%s %s: TV interface is %s\n", XCONFIG_PROBED, + vga256InfoRec.name, (TVinterface & 0x80) ? "PAL" : "NTSC"); + + ErrorF("%s %s: DAC is %sabled for TV\n", XCONFIG_PROBED, + vga256InfoRec.name, (TVinterface & 0x08) ? "en" : "dis"); + + if (OFLG_ISSET(OPTION_TGUI_TVOUT, &vga256InfoRec.options)) { + TVconnected = TRUE; + ErrorF("%s %s: %s display is connected, but TV forced.\n", + XCONFIG_PROBED, vga256InfoRec.name, + (TVinterface & 0x02) ? "TV" : "VGA"); + } else { + ErrorF("%s %s: %s display is connected.\n", + XCONFIG_PROBED, vga256InfoRec.name, + (TVinterface & 0x02) ? "TV" : "VGA"); + } + + if (TVinterface & 0x02) + TVconnected = TRUE; + } + /* * Set up 2 bank registers */ *************** *** 912,918 **** break; case 1: case 5: /* New TGUI's don't support less than 1MB */ ! if (TVGAchipset == TGUI96xx) vga256InfoRec.videoRam = 4096; else vga256InfoRec.videoRam = 512; --- 1107,1113 ---- break; case 1: case 5: /* New TGUI's don't support less than 1MB */ ! if (TVGAchipset >= TGUI96xx) vga256InfoRec.videoRam = 4096; else vga256InfoRec.videoRam = 512; *************** *** 925,931 **** vga256InfoRec.videoRam = 1024; break; case 7: ! if (((temp & 0x0F) == 0x0F) && (revision == TGUI9685)) /* This is for the 9685 */ vga256InfoRec.videoRam = 4096; else --- 1120,1126 ---- vga256InfoRec.videoRam = 1024; break; case 7: ! if (((temp & 0x0F)==0x0F) && (TVGAchipset >= TGUI9685)) /* This is for the 9685 */ vga256InfoRec.videoRam = 4096; else *************** *** 964,970 **** if (OFLG_ISSET(OPTION_TGUI_MCLK_66, &vga256InfoRec.options)) ErrorF("%s %s: Forcing MCLK to 66MHz\n", XCONFIG_GIVEN, vga256InfoRec.name); - OFLG_SET(OPTION_NO_PROGRAM_CLOCKS, &TVGA8900.ChipOptionFlags); /* Do some sanity checking first ! */ --- 1159,1164 ---- *************** *** 1127,1132 **** --- 1321,1334 ---- } break; case 24: + vga256InfoRec.maxClock = + tridentClockLimit24bpp[TVGAchipset]; + if (!tridentTGUIProgrammableClocks) + { + TVGA8900.ChipClockMulFactor = 3; + vga256InfoRec.maxClock *= 3; + } + break; case 32: vga256InfoRec.maxClock = tridentClockLimit32bpp[TVGAchipset]; *************** *** 1172,1201 **** static void TVGA8900DisplayPowerManagementSet(PowerManagementMode) int PowerManagementMode; { ! unsigned char Cont; if (!xf86VTSema) return; ! outb(0x3CE, 0x23); /* Read DPMS Control */ ! Cont = inb(0x3CF) & 0xFC; switch (PowerManagementMode) { case DPMSModeOn: /* Screen: On, HSync: On, VSync: On */ ! Cont |= 0x00; break; case DPMSModeStandby: /* Screen: Off, HSync: Off, VSync: On */ ! Cont |= 0x01; break; case DPMSModeSuspend: /* Screen: Off, HSync: On, VSync: Off */ ! Cont |= 0x02; break; case DPMSModeOff: /* Screen: Off, HSync: Off, VSync: Off */ ! Cont |= 0x03; break; } ! outb(0x3CF, Cont); } #endif --- 1374,1415 ---- static void TVGA8900DisplayPowerManagementSet(PowerManagementMode) int PowerManagementMode; { ! unsigned char DPMSCont, PMCont, temp; if (!xf86VTSema) return; ! outb(0x3C4, 0x0E); ! temp = inb(0x3C5); ! outb(0x3C5, 0xC2); ! outb(0x83C8, 0x04); /* Read DPMS Control */ ! PMCont = inb(0x83C6) & 0xFC; ! outb(0x3CE, 0x23); ! DPMSCont = inb(0x3CF) & 0xFC; switch (PowerManagementMode) { case DPMSModeOn: /* Screen: On, HSync: On, VSync: On */ ! PMCont |= 0x03; ! DPMSCont |= 0x00; break; case DPMSModeStandby: /* Screen: Off, HSync: Off, VSync: On */ ! PMCont |= 0x02; ! DPMSCont |= 0x01; break; case DPMSModeSuspend: /* Screen: Off, HSync: On, VSync: Off */ ! PMCont |= 0x02; ! DPMSCont |= 0x02; break; case DPMSModeOff: /* Screen: Off, HSync: Off, VSync: Off */ ! PMCont |= 0x00; ! DPMSCont |= 0x03; break; } ! outb(0x3CF, DPMSCont); ! outb(0x83C8, 0x04); ! outb(0x83C6, PMCont); ! outw(0x3C4, (temp<<8) | 0x0E); } #endif *************** *** 1487,1494 **** outb(0x43C7, restore->MCLK_B); } outb(0x3C2, restore->VCLK_O); ! outb(0x43C8, restore->VCLK_A); ! outb(0x43C9, restore->VCLK_B); } outw(vgaIOBase + 4, ((restore->CRTHiOrd) << 8) | 0x27); --- 1701,1715 ---- outb(0x43C7, restore->MCLK_B); } outb(0x3C2, restore->VCLK_O); ! if (TVGAchipset < CYBER9397) { ! outb(0x43C8, restore->VCLK_A); ! outb(0x43C9, restore->VCLK_B); ! } else { ! outb(0x3C4, 0x18); ! outb(0x3C5, restore->VCLK_A); ! outb(0x3C4, 0x19); ! outb(0x3C5, restore->VCLK_B); ! } } outw(vgaIOBase + 4, ((restore->CRTHiOrd) << 8) | 0x27); *************** *** 1516,1523 **** outw(vgaIOBase + 4, ((restore->GraphEngReg) << 8) | 0x36); if (TVGAchipset >= TGUI96xx) { - outw(vgaIOBase + 4, ((restore->DispLat)<<8) - | 0x30); outw(vgaIOBase + 4, ((restore->Performance)<<8) | 0x2F); if (NewClockCode) --- 1737,1742 ---- *************** *** 1555,1560 **** --- 1774,1791 ---- outw(0x3C4, ((restore->NewMode1 ^ 0x02) << 8) | 0x0E); + if (ClearTV) { + if (OFLG_ISSET(OPTION_TGUI_TVOUT, &vga256InfoRec.options)) { + outw(vgaIOBase + 4, + ((restore->TVinterface) << 8) | 0xC0); + } + if (TVconnected) { + outw(vgaIOBase + 4, ((restore->TVMode) << 8) | 0xC1); + outw(vgaIOBase + 4, ((restore->VSPS) << 8) | 0xC6); + outw(vgaIOBase + 4, ((restore->VSP) << 8) | 0xC7); + } + } + if (TVGAchipset >= TGUI96xx) vgaHWRestore((vgaHWPtr)restore); *************** *** 1678,1687 **** if (tridentTGUIProgrammableClocks) { save->VCLK_O = inb(0x3CC); ! save->VCLK_A = inb(0x43C8); ! save->VCLK_B = inb(0x43C9); ! save->MCLK_A = inb(0x43C6); ! save->MCLK_B = inb(0x43C7); } #ifndef MONOVGA --- 1909,1925 ---- if (tridentTGUIProgrammableClocks) { save->VCLK_O = inb(0x3CC); ! if (TVGAchipset < CYBER9397) { ! save->VCLK_A = inb(0x43C8); ! save->VCLK_B = inb(0x43C9); ! save->MCLK_A = inb(0x43C6); ! save->MCLK_B = inb(0x43C7); ! } else { ! outb(vgaIOBase + 4, 0x18); ! save->VCLK_A = inb(0x3C5); ! outb(vgaIOBase + 4, 0x19); ! save->VCLK_B = inb(0x3C5); ! } } #ifndef MONOVGA *************** *** 1697,1704 **** { outb(vgaIOBase + 4, 0x2F); save->Performance = inb(vgaIOBase + 5); - outb(vgaIOBase + 4, 0x30); - save->DispLat = inb(vgaIOBase + 5); if (NewClockCode) { outb(vgaIOBase + 4, 0xCF); save->ClockControl = inb(vgaIOBase + 5); --- 1935,1940 ---- *************** *** 1726,1731 **** --- 1962,1982 ---- save->TRDReg = inb(0x3C7); #endif + if (ClearTV) { + if (OFLG_ISSET(OPTION_TGUI_TVOUT, &vga256InfoRec.options)) { + outb(vgaIOBase + 4, 0xC0); + save->TVinterface = inb(vgaIOBase + 5); + } + if (TVconnected) { + outb(vgaIOBase + 4, 0xC1); + save->TVMode = inb(vgaIOBase + 5); + outb(vgaIOBase + 4, 0xC6); + save->VSPS = inb(vgaIOBase + 5); + outb(vgaIOBase + 4, 0xC7); + save->VSP = inb(vgaIOBase + 5); + } + } + return ((void *) save); } *************** *** 1831,1836 **** --- 2082,2126 ---- new->CRTCModuleTest = (mode->Flags & V_INTERLACE ? 0x84 : 0x80); + if (ClearTV) { + if (OFLG_ISSET(OPTION_TGUI_TVOUT, &vga256InfoRec.options)) { + outb(vgaIOBase + 4, 0xC0); + new->TVinterface = inb(vgaIOBase + 5) | 0x02; + } + if (TVconnected) { + outb(vgaIOBase + 4, 0xC1); + new->TVMode = inb(vgaIOBase + 5) & 0xEF; + #if 0 + if (mode->Flags & V_INTERLACE) + new->TVMode &= 0xEF; + else + new->TVMode |= 0x10; + #endif + new->VSPS = 0; + new->VSP = 0; + + new->TVMode &= 0xF0; + if (mode->HDisplay <= 320) + new->TVMode |= 0x00; + else + if (mode->HDisplay <= 640) + new->TVMode |= 0x01; + else + if (mode->HDisplay <= 720) + new->TVMode |= 0x02; + else + if (mode->HDisplay <= 800) + new->TVMode |= 0x03; + + #if 0 + if (vgaBitsPerPixel <= 16) + new->TVMode |= 0x08; /* Enable double queue */ + else + new->TVMode |= 0x04; /* Enable Underscan */ + #endif + } + } + if (tridentUseLinear) { new->LinearAddReg = *************** *** 1861,1869 **** --- 2151,2162 ---- new->VLBusReg = inb(vgaIOBase + 5) | 0x40; /* 32bit mode */ outb(0x3CE, 0x0F); new->MiscExtFunc = inb(0x3CF) | 0x07; /* Set Dual Banks */ + if (TVGAchipset >= CYBER9397) + new->MiscExtFunc |= 0x10; } new->CommandReg = 0x00; /* DAC Standard colourmap */ + GE_OP = 0; #if 0 /* Disabled for 3.3 */ if (tridentHWCursorType) if (OFLG_ISSET(OPTION_HW_CURSOR, &vga256InfoRec.options)) *************** *** 1968,1974 **** if (mode->CrtcVDisplay > 480) new->CyberEnhance |= 0x10; outb(0x3CE, 0x30); ! new->CyberCont = inb(0x3CF) & 0x7E; outb(0x3CE, 0x52); new->CyberVExp = inb(0x3CF); outb(0x3CE, 0x53); --- 2261,2269 ---- if (mode->CrtcVDisplay > 480) new->CyberEnhance |= 0x10; outb(0x3CE, 0x30); ! new->CyberCont = inb(0x3CF); ! if (!OFLG_ISSET(OPTION_CYBER_SHADOW, &vga256InfoRec.options)) ! new->CyberCont &= 0x7E; outb(0x3CE, 0x52); new->CyberVExp = inb(0x3CF); outb(0x3CE, 0x53); *************** *** 2005,2020 **** if (NewClockCode) { outb(vgaIOBase + 4, 0xCF); new->ClockControl = inb(vgaIOBase + 5); ! new->ClockControl &= 0xFE; } outb(vgaIOBase + 4, 0x2F); - #ifndef PC98_TGUI new->Performance = inb(vgaIOBase + 5) | 0x10; - new->DispLat = 0x0F; - #else - new->Performance = inb(vgaIOBase + 5) & ~0x10; - /* disable 12depth FIFO */ - #endif } if (vgaBitsPerPixel >= 8) { --- 2300,2309 ---- if (NewClockCode) { outb(vgaIOBase + 4, 0xCF); new->ClockControl = inb(vgaIOBase + 5); ! new->ClockControl |= 0x01; } outb(vgaIOBase + 4, 0x2F); new->Performance = inb(vgaIOBase + 5) | 0x10; } if (vgaBitsPerPixel >= 8) { *************** *** 2044,2050 **** new->GraphEngReg = 0x80; /* Enable 0x21XX, GER */ #endif /* PC98_TGUI */ } - GE_OP = 0x0000; /* Use XY */ switch (vga256InfoRec.displayWidth * vgaBitsPerPixel / 8) { case 512: GE_OP |= 0x00; --- 2333,2338 ---- *************** *** 2063,2072 **** outb(0x3CE, 0x2F); new->MiscIntContReg = inb(0x3CF) | 0x04; /* double line width */ new->PixelBusReg = 0x00; if (vgaBitsPerPixel == 16) { new->std.Attribute[17] = 0x00; ! if (TVGAchipset <= TGUI9320LCD) new->MiscExtFunc |= 0x08; /* Clock Div. by 2 */ new->CommandReg = 0x30; /* 16bpp */ new->PixelBusReg |= 0x04; --- 2351,2362 ---- outb(0x3CE, 0x2F); new->MiscIntContReg = inb(0x3CF) | 0x04; /* double line width */ new->PixelBusReg = 0x00; + if ((IsTGUI9682) || (IsAdvCyber)) + GE_OP |= 0x100; if (vgaBitsPerPixel == 16) { new->std.Attribute[17] = 0x00; ! if (TVGAchipset <= CYBER9320) new->MiscExtFunc |= 0x08; /* Clock Div. by 2 */ new->CommandReg = 0x30; /* 16bpp */ new->PixelBusReg |= 0x04; *************** *** 2078,2085 **** { new->std.Attribute[17] = 0x00; new->CommandReg = 0xD0; /* 24bpp */ ! new->MiscExtFunc |= 0x40; /* Clock Division by 3 */ ! new->PixelBusReg |= 0x08; GE_OP |= 0x03; /* 24bpp in GE */ } if (vgaBitsPerPixel == 32) --- 2368,2379 ---- { new->std.Attribute[17] = 0x00; new->CommandReg = 0xD0; /* 24bpp */ ! if (TVGAchipset < TGUI96xx) { ! new->MiscExtFunc |= 0x40; /* Clock Div. by 3 */ ! new->PixelBusReg |= 0x08; ! } else { ! new->PixelBusReg |= 0x29; ! } GE_OP |= 0x03; /* 24bpp in GE */ } if (vgaBitsPerPixel == 32) *************** *** 2086,2092 **** { new->std.Attribute[17] = 0x00; new->CommandReg = 0xD0; /* 32bpp */ ! new->MiscExtFunc |= 0x08; /* Clock Division by 2 */ new->PixelBusReg |= 0x09; /* 16bit bus */ GE_OP |= 0x02; /* 32bpp in GE */ } --- 2380,2386 ---- { new->std.Attribute[17] = 0x00; new->CommandReg = 0xD0; /* 32bpp */ ! new->MiscExtFunc |= 0x08; /* Clock Div. by 2 */ new->PixelBusReg |= 0x09; /* 16bit bus */ GE_OP |= 0x02; /* 32bpp in GE */ } *************** *** 2100,2115 **** TGUISetClock(new->std.NoClock); if (OFLG_ISSET(OPTION_TGUI_MCLK_66, &vga256InfoRec.options)) { ! if (NewClockCode) ! { ! new->MCLK_A = 0xBD; ! new->MCLK_B = 0x58; ! } ! else ! { ! new->MCLK_A = 0x8F; ! new->MCLK_B = 0x00; ! } } } else --- 2394,2401 ---- TGUISetClock(new->std.NoClock); if (OFLG_ISSET(OPTION_TGUI_MCLK_66, &vga256InfoRec.options)) { ! new->MCLK_A = 0x8F; ! new->MCLK_B = 0x00; } } else *************** *** 2140,2146 **** int shift = 0; if (vgaBitsPerPixel >= 8) { ! if ((TVGAchipset >= TGUI96xx) && (vgaBitsPerPixel == 8)) base &= 0xFFFFFFF8; if (vgaBitsPerPixel == 16) shift = 1; --- 2426,2433 ---- int shift = 0; if (vgaBitsPerPixel >= 8) { ! if ((TVGAchipset >= TGUI96xx) && ((vgaBitsPerPixel == 8) || ! (vgaBitsPerPixel == 24)) ) base &= 0xFFFFFFF8; if (vgaBitsPerPixel == 16) shift = 1; *************** *** 2220,2225 **** --- 2507,2523 ---- } } + if (TVconnected) { + if (mode->HDisplay > 800) { + if (verbose) { + ErrorF("%s %s: ClearTV(TM) only supports max. width" + "of 800, Adjust Modes in XF86Config.\n", + XCONFIG_PROBED, vga256InfoRec.name); + } + return(MODE_BAD); + } + } + if (IsCyber) { if (mode->VDisplay > 1024) *************** *** 2226,2232 **** { if (verbose) ErrorF("%s %s: Chipset supports a max. height" ! "of 1024, Adjust Modes in XF86Conig.\n", XCONFIG_PROBED, vga256InfoRec.name); return(MODE_BAD); } --- 2524,2530 ---- { if (verbose) ErrorF("%s %s: Chipset supports a max. height" ! "of 1024, Adjust Modes in XF86Config.\n", XCONFIG_PROBED, vga256InfoRec.name); return(MODE_BAD); } *************** *** 2274,2288 **** if (memory > vga256InfoRec.videoRam) { ! TVGA8900EnterLeave(LEAVE); ! FatalError("%s %s: Too Little VideoRam for Accelerator Engine\n" ! "%s %s: Required resolution with accelerator is %dx%d.\n" ! "%s %s: Reduce your Virtual X resolution to %d, or use Option \"noaccel\".\n", ! XCONFIG_PROBED, vga256InfoRec.name, ! XCONFIG_PROBED, vga256InfoRec.name, ! pitch, vga256InfoRec.virtualY, ! XCONFIG_PROBED, vga256InfoRec.name, ! pitch/2); } return pitch; --- 2572,2581 ---- if (memory > vga256InfoRec.videoRam) { ! ErrorF("%s %s: Disabling Engine due to lack of video memory.\n", ! XCONFIG_PROBED, vga256InfoRec.name); ! OFLG_SET(OPTION_NOACCEL, &vga256InfoRec.options); ! return X; } return pitch; *** ./programs/Xserver/hw/xfree86/vga256/drivers/tvga8900/t89_driver.h@@/PUBLIC-LATEST Sun Aug 10 13:06:58 1997 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/tvga8900/t89_driver.h Fri Mar 6 16:55:08 1998 *************** *** 1,4 **** ! /* $TOG: t89_driver.h /main/5 1997/08/10 13:05:34 kaleb $ */ /* * Copyright 1995 by Alan Hourihane, Wigan, England. * --- 1,4 ---- ! /* $TOG: t89_driver.h /main/6 1998/03/06 16:56:46 kaleb $ */ /* * Copyright 1995 by Alan Hourihane, Wigan, England. * *************** *** 22,29 **** * * Author: Alan Hourihane, alanh@fairlite.demon.co.uk */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/tvga8900/t89_driver.h,v 3.9.2.5 1997/07/26 06:30:57 dawes Exp $ */ /* * Trident Chipset Definitions */ --- 22,31 ---- * * Author: Alan Hourihane, alanh@fairlite.demon.co.uk */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/tvga8900/t89_driver.h,v 3.9.2.6 1998/01/18 10:35:38 hohndel Exp $ */ + extern int TVGAchipset; + extern Bool IsCyber; /* * Trident Chipset Definitions */ *************** *** 43,54 **** #define TGUI9420DGi 12 #define TGUI9430DGi 13 #define TGUI9440AGi 14 ! #define TGUI9320LCD 15 ! #define TGUI96xx 16 ! #define CYBER938x 17 ! /* Revisions */ ! #define TGUI9685 0x21 #ifdef INITIALIZE_LIMITS /* Clock Limits */ --- 45,73 ---- #define TGUI9420DGi 12 #define TGUI9430DGi 13 #define TGUI9440AGi 14 ! #define CYBER9320 15 ! #define TGUI96xx 16 /* backwards compatibility */ ! #define TGUI9660 16 ! #define TGUI9680 17 ! #define TGUI9682 18 ! #define TGUI9685 19 ! #define CYBER9382 20 ! #define CYBER9385 21 ! #define CYBER9388 22 ! #define CYBER9397 23 ! #define CYBER9520 24 ! #define IMAGE975 25 ! #define IMAGE985 26 ! #define IsTGUI9440 (TVGAchipset == TGUI9440AGi) ! #define IsTGUI9660 (TVGAchipset == TGUI9660) ! #define IsTGUI9680 (TVGAchipset == TGUI9680) ! #define IsTGUI9682 (TVGAchipset == TGUI9682) ! #define IsTGUI9685 (TVGAchipset == TGUI9685) ! #define IsAdvCyber ((TVGAchipset == CYBER9382) || \ ! (TVGAchipset == CYBER9385) || \ ! (TVGAchipset == CYBER9388) || \ ! (TVGAchipset == CYBER9397)) #ifdef INITIALIZE_LIMITS /* Clock Limits */ *************** *** 67,75 **** 80000, 80000, 80000, - 80000, 90000, 135000, }; int tridentClockLimit16bpp[] = { --- 86,104 ---- 80000, 80000, 80000, 90000, + 90000, 135000, + 135000, + 135000, + 170000, + 135000, + 135000, + 170000, + 170000, + 230000, + 230000, + 230000, }; int tridentClockLimit16bpp[] = { *************** *** 87,97 **** 40000, 40000, 40000, - 40000, 45000, 135000, }; int tridentClockLimit32bpp[] = { 25180, 25180, --- 116,166 ---- 40000, 40000, 40000, 45000, + 45000, 135000, + 135000, + 135000, + 170000, + 135000, + 135000, + 170000, + 170000, + 230000, + 230000, + 230000, }; + int tridentClockLimit24bpp[] = { + 25180, + 25180, + 25180, + 25180, + 25180, + 25180, + 25180, + 25180, + 25180, + 25180, + 25180, + 25180, + 25180, + 25180, + 25180, + 25180, + 70000, + 70000, + 70000, + 85000, + 70000, + 70000, + 85000, + 85000, + 115000, + 115000, + 115000, + }; + int tridentClockLimit32bpp[] = { 25180, 25180, *************** *** 110,115 **** --- 179,194 ---- 25180, 25180, 70000, + 70000, + 70000, + 85000, + 70000, + 70000, + 85000, + 85000, + 115000, + 115000, + 115000, }; #else *************** *** 116,121 **** --- 195,201 ---- extern int tridentClockLimit[]; extern int tridentClockLimit16bpp[]; + extern int tridentClockLimit24bpp[]; extern int tridentClockLimit32bpp[]; #endif *************** *** 127,132 **** #define TKD8001 0 #define TGUIDAC 1 - - extern int TVGAchipset; - extern Bool IsCyber; --- 207,209 ---- *** ./programs/Xserver/hw/xfree86/vga256/drivers/tvga8900/tgui_ger.h@@/PUBLIC-LATEST Sun Aug 10 13:07:13 1997 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/tvga8900/tgui_ger.h Fri Mar 6 16:55:17 1998 *************** *** 1,4 **** ! /* $TOG: tgui_ger.h /main/5 1997/08/10 13:05:48 kaleb $ */ /* * Copyright 1995 by Alan Hourihane, Wigan, England. * --- 1,4 ---- ! /* $TOG: tgui_ger.h /main/6 1998/03/06 16:56:54 kaleb $ */ /* * Copyright 1995 by Alan Hourihane, Wigan, England. * *************** *** 22,28 **** * * Author: Alan Hourihane, alanh@fairlite.demon.co.uk */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/tvga8900/tgui_ger.h,v 3.9.2.2 1997/06/25 08:16:57 hohndel Exp $ */ /* Graphics Engine for 9420/9430 */ --- 22,28 ---- * * Author: Alan Hourihane, alanh@fairlite.demon.co.uk */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/tvga8900/tgui_ger.h,v 3.9.2.3 1998/01/18 10:35:39 hohndel Exp $ */ /* Graphics Engine for 9420/9430 */ *************** *** 64,69 **** --- 64,74 ---- #define GE_ELLIP_FILL 0x09 /* Ellipse Fill (96xx only) (RES)*/ #define GER_FMIX 0x27 #define GER_DRAWFLAG 0x28 /* long */ + #define CLIPENABLE 0x40000000 + #define SRCLINEAR 0x10000000 + #define DSTLINEAR 0x08000000 + #define BYTEPACK 0x00400000 + #define DSTTRANS 0x00010000 #define STENCIL 0x8000 #define SOLIDFILL 0x4000 #define TRANS_ENABLE 0x1000 *************** *** 89,94 **** --- 94,102 ---- #define GER_DIM_Y 0x42 /* Word */ #define GER_PATTERN 0x80 /* from 0x2180 to 0x21FF */ + /* Additional - Graphics Engine for 9440 */ + #define GER_PENSTYLE 0x44 /* Word */ + /* Additional - Graphics Engine for 96xx */ #define GER_SRCCLIP_XY 0x48 #define GER_SRCCLIP_X 0x48 /* Word */ *************** *** 98,105 **** --- 106,121 ---- #define GER_DSTCLIP_Y 0x4E /* Word */ /* Additional - Graphics Engine for 9685 */ + #define GER_BBDST 0x00 + #define GER_BBSRC 0x08 + #define GER_BBDSTSIZE 0x04 + #define GER_BBSRCSIZE 0x0C + #define GER_DEST_LINEAR 0x50 + #define GER_DEST_PITCH 0x54 + #define GER_DSTKEY 0x68 #define GER_FPATCOL 0x78 #define GER_BPATCOL 0x7C + #define GER_PLANEMASK 0x80 /* ROPS */ #define TGUIROP_0 0x00 /* 0 */ *** ./programs/Xserver/hw/xfree86/vga256/enhanced/fBitBlt.s@@/PUBLIC-LATEST Sat Jul 19 10:45:49 1997 --- xc/programs/Xserver/hw/xfree86/vga256/enhanced/fBitBlt.s Fri Mar 6 16:55:24 1998 *************** *** 1,4 **** ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/enhanced/fBitBlt.s,v 1.1.1.2 1996/01/03 07:25:27 dawes Exp $ */ /* * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany. * --- 1,4 ---- ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/enhanced/fBitBlt.s,v 3.1 1996/12/23 06:59:01 dawes Exp $ */ /* * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany. * *************** *** 21,29 **** * PERFORMANCE OF THIS SOFTWARE. * * Author: Thomas Roell, roell@informatik.tu-muenchen.de - * */ ! /* $TOG: fBitBlt.s /main/5 1997/07/19 10:45:51 kaleb $ */ /* --- 21,28 ---- * PERFORMANCE OF THIS SOFTWARE. * * Author: Thomas Roell, roell@informatik.tu-muenchen.de */ ! /* $TOG: fBitBlt.s /main/6 1998/03/06 16:57:02 kaleb $ */ /* *** ./programs/Xserver/hw/xfree86/vga256/enhanced/fFill.s@@/PUBLIC-LATEST Sat Jul 19 10:45:55 1997 --- xc/programs/Xserver/hw/xfree86/vga256/enhanced/fFill.s Fri Mar 6 16:55:29 1998 *************** *** 1,5 **** ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/enhanced/fFill.s,v 3.6 1996 ! /12/23 06:59:02 dawes Exp $ */ /* * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany. * --- 1,4 ---- ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/enhanced/fFill.s,v 3.6 1996/12/23 06:59:02 dawes Exp $ */ /* * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany. * *************** *** 28,34 **** * form by David Wexelblat (dwex@goblin.org). * */ ! /* $TOG: fFill.s /main/7 1997/07/19 10:45:57 kaleb $ */ #include "assyntax.h" --- 27,33 ---- * form by David Wexelblat (dwex@goblin.org). * */ ! /* $TOG: fFill.s /main/8 1998/03/06 16:57:07 kaleb $ */ #include "assyntax.h" *** ./programs/Xserver/hw/xfree86/vga256/vga/vga.c@@/PUBLIC-LATEST Fri Nov 14 17:36:37 1997 --- xc/programs/Xserver/hw/xfree86/vga256/vga/vga.c Sat Mar 7 13:58:48 1998 *************** *** 1,4 **** ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/vga/vga.c,v 3.71.2.10 1997/06/01 12:33:41 dawes Exp $ */ /* * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany. * --- 1,4 ---- ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/vga/vga.c,v 3.71.2.14 1998/02/15 16:09:40 hohndel Exp $ */ /* * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany. * *************** *** 23,29 **** * Author: Thomas Roell, roell@informatik.tu-muenchen.de * */ ! /* $TOG: vga.c /main/34 1997/11/14 17:40:04 kaleb $ */ #include "X.h" #include "Xmd.h" --- 23,29 ---- * Author: Thomas Roell, roell@informatik.tu-muenchen.de * */ ! /* $TOG: vga.c /main/37 1998/03/07 14:00:29 kaleb $ */ #include "X.h" #include "Xmd.h" *************** *** 45,54 **** #include "vga.h" #include "vgaPCI.h" - #ifdef PC98 - #include "pc98_vers.h" - #endif - #ifdef XFreeXDGA #include "scrnintstr.h" #include "servermd.h" --- 45,50 ---- *************** *** 197,209 **** 0, /* int s3MClk */ 0, /* int chipID */ 0, /* int chipRev */ ! 0, /* unsigned long VGAbase */ 0, /* int s3RefClk */ -1, /* int s3BlankDelay */ 0, /* int textClockFreq */ NULL, /* char* DCConfig */ NULL, /* char* DCOptions */ ! 0 /* int MemClk */ #ifdef XFreeXDGA ,0, /* int directMode */ NULL, /* Set Vid Page */ --- 193,218 ---- 0, /* int s3MClk */ 0, /* int chipID */ 0, /* int chipRev */ ! #if defined (PC98_WAB) || defined(PC98_WABEP) ! 0x0E0000, /* unsigned long VGAbase */ ! #else ! #if defined(PC98_GANB_WAP) || defined(PC98_WSNA) || defined(PC98_NKVNEC) ! 0xF00000, /* unsigned long VGAbase */ ! #else ! #if defined(PC98_EGC) || defined(PC98_PEGC) ! 0x0A8000, /* unsigned long VGAbase */ ! #else ! 0x0A0000, /* unsigned long VGAbase */ ! #endif /* PC98_EGC || PC98_PEGC */ ! #endif /* PC98_GANB_WAP || PC98_WSNA || PC98_NKVNEC */ ! #endif /* PC98_WAB || PC98_WABEP */ 0, /* int s3RefClk */ -1, /* int s3BlankDelay */ 0, /* int textClockFreq */ NULL, /* char* DCConfig */ NULL, /* char* DCOptions */ ! 0, /* int MemClk */ ! 0 /* int LCDClk */ #ifdef XFreeXDGA ,0, /* int directMode */ NULL, /* Set Vid Page */ *************** *** 363,384 **** c += strlen(id); } ErrorF("\n"); - #ifdef PC98 - ErrorF(" PC98: Supported Video Boards:\n\t"); - #endif - #ifdef PC98_EGC - ErrorF("%s\n",PC98_VGA16_BOARDS); - #endif - #ifdef PC98_NEC480 - ErrorF("%s\n",PC98_VGA256_BOARDS); - #endif - #if defined(PC98_WAB)||defined(PC98_WABEP)||defined(PC98_GANB_WAP)||\ - defined(PC98_NKVNEC)||defined(PC98_WSNA) - ErrorF("%s\n",PC98_CIRRUS_BOARDS); - #endif - #ifdef PC98_TGUI - ErrorF("%s\n",PC98_TGUI_BOARDS); - #endif } #ifdef DPMSExtension --- 372,377 ---- *************** *** 549,555 **** } } ! #if !defined(PC98) || defined(PC98_TGUI) /* First do a general PCI probe (unless disabled) */ if (!OFLG_ISSET(OPTION_NO_PCI_PROBE, &vga256InfoRec.options)) { vgaPCIInfo = vgaGetPCIInfo(); --- 542,548 ---- } } ! #if !defined(PC98) || defined(PC98_TGUI) || defined(PC98_MGA) || defined(PC98_SVGA) /* First do a general PCI probe (unless disabled) */ if (!OFLG_ISSET(OPTION_NO_PCI_PROBE, &vga256InfoRec.options)) { vgaPCIInfo = vgaGetPCIInfo(); *************** *** 558,566 **** for (i=0; Drivers[i]; i++) { - vgaSaveScreenFunc = Drivers[i]->ChipSaveScreen; if ((Drivers[i]->ChipProbe)()) { xf86ProbeFailed = FALSE; #ifdef MONOVGA #ifdef BANKEDMONOVGA --- 551,559 ---- for (i=0; Drivers[i]; i++) { if ((Drivers[i]->ChipProbe)()) { + vgaSaveScreenFunc = Drivers[i]->ChipSaveScreen; xf86ProbeFailed = FALSE; #ifdef MONOVGA #ifdef BANKEDMONOVGA *************** *** 1153,1159 **** #endif /* !MONOVGA */ #endif /* !XF86VGA16 */ ! #if !defined(PC98) || defined(PC98_TGUI) if (!OFLG_ISSET(OPTION_NO_PCI_PROBE, &vga256InfoRec.options)) { /* Free PCI information */ xf86cleanpci(); --- 1146,1152 ---- #endif /* !MONOVGA */ #endif /* !XF86VGA16 */ ! #if !defined(PC98) || defined(PC98_TGUI) || defined(PC98_MGA) || defined(PC98_SVGA) if (!OFLG_ISSET(OPTION_NO_PCI_PROBE, &vga256InfoRec.options)) { /* Free PCI information */ xf86cleanpci(); *************** *** 1165,1171 **** #endif return TRUE; ! } } vgaSaveScreenFunc = vgaHWSaveScreen; --- 1158,1164 ---- #endif return TRUE; ! } } vgaSaveScreenFunc = vgaHWSaveScreen; *************** *** 1406,1413 **** vga256InfoRec.displayWidth); #endif /* XF86VGA16 */ - pScreen->CloseScreen = vgaCloseScreen; - pScreen->SaveScreen = vgaSaveScreen; pScreen->whitePixel = 1; pScreen->blackPixel = 0; XF86FLIP_PIXELS(); --- 1399,1404 ---- *************** *** 1442,1447 **** --- 1433,1441 ---- miDCInitialize (pScreen, &xf86PointerScreenFuncs); } + pScreen->CloseScreen = vgaCloseScreen; + pScreen->SaveScreen = vgaSaveScreen; + #ifndef XF86VGA16 #ifdef MONOVGA if (!mfbCreateDefColormap(pScreen)) *************** *** 1640,1652 **** if (!xf86Resetting) { ScrnInfoPtr pScr = XF86SCRNINFO(pScreen); - - if (vgaHWCursor.Initialized) - { - vgaHWCursor.Init(0, pScreen); - vgaHWCursor.Restore(pScreen); - vgaAdjustFunc(pScr->frameX0, pScr->frameY0); - } if ((pointer)pspix->devPrivate.ptr != (pointer)vgaVirtBase && ppix) { --- 1634,1639 ---- *** ./programs/Xserver/hw/xfree86/vga256/vga/vga.h@@/PUBLIC-LATEST Sat Jul 19 10:47:37 1997 --- xc/programs/Xserver/hw/xfree86/vga256/vga/vga.h Fri Mar 6 16:55:39 1998 *************** *** 1,4 **** ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/vga/vga.h,v 3.23.2.4 1997/05/09 09:31:44 hohndel Exp $ */ /* * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany. * --- 1,4 ---- ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/vga/vga.h,v 3.23.2.6 1998/02/01 16:05:16 robin Exp $ */ /* * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany. * *************** *** 23,29 **** * Author: Thomas Roell, roell@informatik.tu-muenchen.de * */ ! /* $TOG: vga.h /main/13 1997/07/19 10:47:39 kaleb $ */ #ifndef _XF86_VGA_H_ #define _XF86_VGA_H_ --- 23,29 ---- * Author: Thomas Roell, roell@informatik.tu-muenchen.de * */ ! /* $TOG: vga.h /main/14 1998/03/06 16:57:17 kaleb $ */ #ifndef _XF86_VGA_H_ #define _XF86_VGA_H_ *************** *** 37,42 **** --- 37,43 ---- #include "input.h" #include "scrnintstr.h" #include "colormapst.h" + #include "xf86.h" #ifdef DPMSExtension #include "opaque.h" *************** *** 287,292 **** --- 288,297 ---- int #endif ); + + + extern Bool (*vgaBlankScreenFunc)(ScreenPtr pScreen,Bool On); + extern int vgaMapSize; extern int vgaSegmentSize; extern int vgaSegmentShift; *************** *** 351,364 **** #define OVERSCAN 0x11 /* Index of OverScan register */ - #ifdef MONOVGA #define BIT_PLANE 3 /* Which plane we write to in mono mode */ - #else #define BITS_PER_GUN 6 #define COLORMAP_SIZE 256 - #endif - #define DACDelay \ { \ unsigned char temp = inb(vgaIOBase + 0x0A); \ --- 356,365 ---- *************** *** 553,557 **** --- 554,564 ---- ColormapPtr pmap #endif ); + + /* Blanks screen */ + Bool vgaBlankScreen(ScreenPtr pScreen,Bool On); + + /* Checks if color map already installed ? */ + int vgaCheckColorMap(ColormapPtr pmap); #endif /* _XF86_VGA_H_ */ *** ./programs/Xserver/hw/xfree86/vga256/vga/vgaCmap.c@@/PUBLIC-LATEST Sun Oct 19 15:01:10 1997 --- xc/programs/Xserver/hw/xfree86/vga256/vga/vgaCmap.c Fri Mar 6 16:55:44 1998 *************** *** 1,4 **** ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/vga/vgaCmap.c,v 3.15 1996/12/23 06:59:30 dawes Exp $ */ /* * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany. * --- 1,4 ---- ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/vga/vgaCmap.c,v 3.15.2.2 1998/02/01 16:05:17 robin Exp $ */ /* * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany. * *************** *** 21,27 **** * PERFORMANCE OF THIS SOFTWARE. * */ ! /* $TOG: vgaCmap.c /main/17 1997/10/19 15:03:14 kaleb $ */ #include "X.h" #include "Xproto.h" --- 21,27 ---- * PERFORMANCE OF THIS SOFTWARE. * */ ! /* $TOG: vgaCmap.c /main/18 1998/03/06 16:57:21 kaleb $ */ #include "X.h" #include "Xproto.h" *************** *** 71,76 **** --- 71,81 ---- } + int vgaCheckColorMap(ColormapPtr pmap) + { + return (pmap != InstalledMaps[pmap->pScreen->myNum]); + } + void vgaStoreColors(pmap, ndef, pdefs) ColormapPtr pmap; *************** *** 84,90 **** unsigned char overscan = ((vgaHWPtr)vgaNewVideoState)->Attribute[OVERSCAN]; unsigned char tmp_overscan; ! if (pmap != InstalledMaps[pmap->pScreen->myNum]) return; /* GJA -- We don't want cfb code right now (in vga16 server) */ --- 89,95 ---- unsigned char overscan = ((vgaHWPtr)vgaNewVideoState)->Attribute[OVERSCAN]; unsigned char tmp_overscan; ! if (vgaCheckColorMap(pmap)) return; /* GJA -- We don't want cfb code right now (in vga16 server) */ *************** *** 235,241 **** Pixel * ppix; xrgb * prgb; xColorItem *defs; ! int i,j; if (pmap == oldmap) --- 240,246 ---- Pixel * ppix; xrgb * prgb; xColorItem *defs; ! int i; if (pmap == oldmap) *************** *** 259,304 **** for ( i=0; i<entries; i++) ppix[i] = i; ! if (pmap->class == GrayScale || pmap->class == PseudoColor) { ! for ( i=j=0; i<entries; i++) ! { ! if (pmap->red[i].fShared || pmap->red[i].refcnt != 0) ! { ! defs[j].pixel = i; ! defs[j].flags = DoRed|DoGreen|DoBlue; ! if (pmap->red[i].fShared) ! { ! defs[j].red = pmap->red[i].co.shco.red->color; ! defs[j].green = pmap->red[i].co.shco.green->color; ! defs[j].blue = pmap->red[i].co.shco.blue->color; ! } ! else if (pmap->red[i].refcnt != 0) ! { ! defs[j].red = pmap->red[i].co.local.red; ! defs[j].green = pmap->red[i].co.local.green; ! defs[j].blue = pmap->red[i].co.local.blue; ! } ! j++; ! } ! } ! entries = j; } - else - { - QueryColors( pmap, entries, ppix, prgb); ! for ( i=0; i<entries; i++) /* convert xrgbs to xColorItems */ ! { ! defs[i].pixel = ppix[i]; ! defs[i].red = prgb[i].red; ! defs[i].green = prgb[i].green; ! defs[i].blue = prgb[i].blue; ! defs[i].flags = DoRed|DoGreen|DoBlue; ! } ! } ! ! vgaStoreColors( pmap, entries, defs); WalkTree(pmap->pScreen, TellGainedMap, &pmap->mid); --- 264,281 ---- for ( i=0; i<entries; i++) ppix[i] = i; ! QueryColors( pmap, entries, ppix, prgb); ! ! for ( i=0; i<entries; i++) /* convert xrgbs to xColorItems */ { ! defs[i].pixel = ppix[i]; ! defs[i].red = prgb[i].red; ! defs[i].green = prgb[i].green; ! defs[i].blue = prgb[i].blue; ! defs[i].flags = DoRed|DoGreen|DoBlue; } ! pmap->pScreen->StoreColors( pmap, entries, defs); WalkTree(pmap->pScreen, TellGainedMap, &pmap->mid); *** ./programs/Xserver/hw/xfree86/vga256/vga/vgaHW.c@@/PUBLIC-LATEST Sat Jul 19 10:48:20 1997 --- xc/programs/Xserver/hw/xfree86/vga256/vga/vgaHW.c Fri Mar 6 16:55:48 1998 *************** *** 1,5 **** /* ! * $XFree86: xc/programs/Xserver/hw/xfree86/vga256/vga/vgaHW.c,v 3.50.2.1 1997/05/10 07:03:00 hohndel Exp $ * * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany. * --- 1,5 ---- /* ! * $XFree86: xc/programs/Xserver/hw/xfree86/vga256/vga/vgaHW.c,v 3.50.2.3 1998/02/01 16:05:17 robin Exp $ * * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany. * *************** *** 23,29 **** * * Author: Thomas Roell, roell@informatik.tu-muenchen.de */ ! /* $TOG: vgaHW.c /main/20 1997/07/19 10:48:22 kaleb $ */ #ifdef ISC202 #include <sys/types.h> --- 23,29 ---- * * Author: Thomas Roell, roell@informatik.tu-muenchen.de */ ! /* $TOG: vgaHW.c /main/21 1998/03/06 16:57:26 kaleb $ */ #ifdef ISC202 #include <sys/types.h> *************** *** 71,77 **** #define EGC_LENGTH 0x4ae /* EGC Bit length */ #endif ! #if !defined(PC98_NEC480) && !defined(PC98_EGC) #if !defined(MONOVGA) && !defined(SCO) #ifndef SAVE_FONT1 #define SAVE_FONT1 --- 71,77 ---- #define EGC_LENGTH 0x4ae /* EGC Bit length */ #endif ! #if !defined(PC98_NEC480) && !defined(PC98_EGC) && !defined(PC98_MGA) #if !defined(MONOVGA) && !defined(SCO) #ifndef SAVE_FONT1 #define SAVE_FONT1 *************** *** 101,107 **** /* bytes per plane to save for font data */ #define FONT_AMOUNT 8192 ! #endif /* !defined(PC98_NEC480) && !defined(PC98_EGC) */ #if defined(CSRG_BASED) || defined(MACH386) #include <sys/time.h> --- 101,107 ---- /* bytes per plane to save for font data */ #define FONT_AMOUNT 8192 ! #endif /* !defined(PC98_NEC480) && !defined(PC98_EGC) && !defined(PC98_MGA) */ #if defined(CSRG_BASED) || defined(MACH386) #include <sys/time.h> *************** *** 153,158 **** --- 153,160 ---- static int currentGraphicsClock = -1; static int currentExternClock = -1; + Bool (*vgaBlankScreenFunc)()=vgaBlankScreen; + int vgaRamdacMask = 0x3F; #define new ((vgaHWPtr)vgaNewVideoState) *************** *** 302,307 **** --- 304,340 ---- } /* + * vgaBlankScreen -- blank the screen. + */ + + Bool vgaBlankScreen(ScreenPtr ptr, Bool on) + { + + #if !defined(PC98_EGC) && !defined(PC98_PEGC) + unsigned char scrn; + + outb(0x3C4,1); + scrn = inb(0x3C5); + + if(on) { + scrn &= 0xDF; /* enable screen */ + }else { + scrn |= 0x20; /* blank screen */ + } + + (*vgaSaveScreenFunc)(SS_START); + outw(0x3C4, (scrn << 8) | 0x01); /* change mode */ + (*vgaSaveScreenFunc)(SS_FINISH); + #else + if(on) + outb(0xa2, 0xd); + else + outb(0xa2, 0xc); + #endif + return TRUE; + } + + /* * vgaSaveScreen -- blank the screen. */ *************** *** 310,350 **** ScreenPtr pScreen; Bool on; { - #if !defined(PC98_EGC) && !defined(PC98_NEC480) - unsigned char scrn; - if (on) SetTimeSinceLastInputEvent(); if (xf86VTSema) { ! /* the server is running on the current vt */ ! /* so just go for it */ ! ! outb(0x3C4,1); ! scrn = inb(0x3C5); ! ! if (on) { ! scrn &= 0xDF; /* enable screen */ ! } else { ! scrn |= 0x20; /* blank screen */ ! } ! ! (*vgaSaveScreenFunc)(SS_START); ! outw(0x3C4, (scrn << 8) | 0x01); /* change mode */ ! (*vgaSaveScreenFunc)(SS_FINISH); } - #else /* PC98_EGC || PC98_NEC480 */ - if (on) - SetTimeSinceLastInputEvent(); - - if (xf86VTSema) - { - if (on) - outb(0xa2, 0xd); - else - outb(0xa2, 0xc); - } - #endif /* PC98_EGC || PC98_NEC480 */ return (TRUE); } --- 343,354 ---- ScreenPtr pScreen; Bool on; { if (on) SetTimeSinceLastInputEvent(); if (xf86VTSema) { ! (*vgaBlankScreenFunc)(pScreen,on); } return (TRUE); } *** ./programs/Xserver/hw/xfree86/vga256/vga/vgaPCI.c@@/PUBLIC-LATEST Sat Jul 19 10:48:27 1997 --- xc/programs/Xserver/hw/xfree86/vga256/vga/vgaPCI.c Fri Mar 6 16:55:53 1998 *************** *** 1,4 **** ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/vga/vgaPCI.c,v 3.11.2.2 1997/05/14 08:39:45 dawes Exp $ */ /* * PCI Probe * --- 1,4 ---- ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/vga/vgaPCI.c,v 3.11.2.3 1998/02/01 16:05:18 robin Exp $ */ /* * PCI Probe * *************** *** 7,13 **** * A lot of this comes from Robin Cutshaw's scanpci * */ ! /* $TOG: vgaPCI.c /main/11 1997/07/19 10:48:29 kaleb $ */ #include "xf86.h" #include "xf86Priv.h" --- 7,13 ---- * A lot of this comes from Robin Cutshaw's scanpci * */ ! /* $TOG: vgaPCI.c /main/12 1998/03/06 16:57:31 kaleb $ */ #include "xf86.h" #include "xf86Priv.h" *************** *** 34,43 **** --- 34,56 ---- return NULL; while (pcrp = pcrpp[i]) { + #if !defined(PC98_TGUI) && !defined(PC98_MGA) if ((pcrp->_base_class == PCI_CLASS_PREHISTORIC && pcrp->_sub_class == PCI_SUBCLASS_PREHISTORIC_VGA) || (pcrp->_base_class == PCI_CLASS_DISPLAY && pcrp->_sub_class == PCI_SUBCLASS_DISPLAY_VGA)) { + #else /* PC98 */ + #ifdef PC98_TGUI + if (pcrp->_base_class == PCI_CLASS_DISPLAY && + pcrp->_sub_class == PCI_SUBCLASS_DISPLAY_VGA && + pcrp->_vendor == PCI_VENDOR_TRIDENT) { + #endif + #ifdef PC98_MGA + if (pcrp->_base_class == PCI_CLASS_DISPLAY && + pcrp->_sub_class == PCI_SUBCLASS_DISPLAY_MISC && + pcrp->_vendor == PCI_VENDOR_MATROX) { + #endif + #endif /* PC98 */ found = TRUE; if ((info = (vgaPCIInformation *) xalloc(sizeof(vgaPCIInformation))) == NULL) *** ./programs/Xserver/hw/xfree86/vga256/vga/vgaPCI.h@@/PUBLIC-LATEST Sun Aug 10 13:07:21 1997 --- xc/programs/Xserver/hw/xfree86/vga256/vga/vgaPCI.h Fri Mar 6 16:55:57 1998 *************** *** 1,4 **** ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/vga/vgaPCI.h,v 3.22.2.8 1997/08/02 13:48:23 dawes Exp $ */ /* * PCI Probe * --- 1,4 ---- ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/vga/vgaPCI.h,v 3.22.2.11 1998/02/20 14:28:02 robin Exp $ */ /* * PCI Probe * *************** *** 7,13 **** * A lot of this comes from Robin Cutshaw's scanpci * */ ! /* $TOG: vgaPCI.h /main/18 1997/08/10 13:05:57 kaleb $ */ #ifndef _VGA_PCI_H #define _VGA_PCI_H --- 7,13 ---- * A lot of this comes from Robin Cutshaw's scanpci * */ ! /* $TOG: vgaPCI.h /main/19 1998/03/06 16:57:35 kaleb $ */ #ifndef _VGA_PCI_H #define _VGA_PCI_H *************** *** 30,36 **** --- 30,40 ---- #define PCI_VENDOR_NUMNINE 0x105D #define PCI_VENDOR_UMC 0x1060 #define PCI_VENDOR_NVIDIA 0x10DE + #define PCI_VENDOR_INTERGRAPHICS 0x10ea #define PCI_VENDOR_ALLIANCE 0x1142 + #define PCI_VENDOR_NVIDIA_SGS 0x12d2 + #define PCI_VENDOR_SIGMADESIGNS 0x1236 + #define PCI_VENDOR_RENDITION 0x1163 #define PCI_VENDOR_3DLABS 0x3D3D #define PCI_VENDOR_S3 0x5333 #define PCI_VENDOR_ARK 0xEDD8 *************** *** 44,53 **** #define PCI_CHIP_MACH64ET 0x4554 #define PCI_CHIP_MACH64VT 0x5654 #define PCI_CHIP_MACH64VU 0x5655 - #define PCI_CHIP_MACH64GP 0x4750 #define PCI_CHIP_MACH64GT 0x4754 #define PCI_CHIP_MACH64GU 0x4755 #define PCI_CHIP_MACH64LT 0x4C47 /* Avance Logic */ #define PCI_CHIP_ALG2301 0x2301 --- 48,61 ---- #define PCI_CHIP_MACH64ET 0x4554 #define PCI_CHIP_MACH64VT 0x5654 #define PCI_CHIP_MACH64VU 0x5655 #define PCI_CHIP_MACH64GT 0x4754 #define PCI_CHIP_MACH64GU 0x4755 #define PCI_CHIP_MACH64LT 0x4C47 + #define PCI_CHIP_MACH64GB 0x4742 + #define PCI_CHIP_MACH64GD 0x4744 + #define PCI_CHIP_MACH64GI 0x4749 + #define PCI_CHIP_MACH64GP 0x4750 + #define PCI_CHIP_MACH64GQ 0x4751 /* Avance Logic */ #define PCI_CHIP_ALG2301 0x2301 *************** *** 58,63 **** --- 66,72 ---- #define PCI_CHIP_ET4000_W32P_D 0x3206 #define PCI_CHIP_ET4000_W32P_C 0x3207 #define PCI_CHIP_ET6000 0x3208 + #define PCI_CHIP_ET6300 0x4702 /* Weitek */ #define PCI_CHIP_P9000 0x9001 *************** *** 65,70 **** --- 74,80 ---- /* Cirrus Logic */ #define PCI_CHIP_GD7548 0x0038 + #define PCI_CHIP_GD7555 0x0040 #define PCI_CHIP_GD5430 0x00A0 #define PCI_CHIP_GD5434_4 0x00A4 #define PCI_CHIP_GD5434_8 0x00A8 *************** *** 78,83 **** --- 88,94 ---- #define PCI_CHIP_GD7541 0x1204 #define PCI_CHIP_GD7542 0x1200 #define PCI_CHIP_GD7543 0x1202 + #define PCI_CHIP_GD7541 0x1204 /* Trident */ #define PCI_CHIP_9320 0x9320 *************** *** 84,93 **** #define PCI_CHIP_9420 0x9420 #define PCI_CHIP_9440 0x9440 #define PCI_CHIP_9660 0x9660 ! #if 0 ! #define PCI_CHIP_9680 0x9680 ! #define PCI_CHIP_9682 0x9682 ! #endif /* Matrox */ #define PCI_CHIP_MGA2085 0x0518 --- 95,105 ---- #define PCI_CHIP_9420 0x9420 #define PCI_CHIP_9440 0x9440 #define PCI_CHIP_9660 0x9660 ! #define PCI_CHIP_9388 0x9388 ! #define PCI_CHIP_9397 0x9397 ! #define PCI_CHIP_9520 0x9520 ! #define PCI_CHIP_9750 0x9750 ! #define PCI_CHIP_9850 0x9850 /* Matrox */ #define PCI_CHIP_MGA2085 0x0518 *************** *** 94,99 **** --- 106,112 ---- #define PCI_CHIP_MGA2064 0x0519 #define PCI_CHIP_MGA1064 0x051a #define PCI_CHIP_MGA2164 0x051b + #define PCI_CHIP_MGA2164_AGP 0x051f /* Chips & Tech */ #define PCI_CHIP_65545 0x00D8 *************** *** 120,130 **** --- 133,149 ---- #define PCI_CHIP_NV1 0x0008 #define PCI_CHIP_DAC64 0x0009 + /* NVIDIA & SGS */ + #define PCI_CHIP_RIVA128 0x0018 + /* Alliance Semiconductor */ #define PCI_CHIP_AP6410 0x3210 #define PCI_CHIP_AP6422 0x6422 #define PCI_CHIP_AT24 0x6424 + /* Rendition */ + #define PCI_CHIP_V1000 0x0001 + /* 3Dlabs */ #define PCI_CHIP_300SX 0x0001 #define PCI_CHIP_500TX 0x0002 *************** *** 140,145 **** --- 159,166 ---- #define PCI_CHIP_PLATO_PX 0x8902 #define PCI_CHIP_VIRGE_VX 0x883D #define PCI_CHIP_VIRGE_DXGX 0x8A01 + #define PCI_CHIP_VIRGE_GX2 0x8A10 + #define PCI_CHIP_VIRGE_MX 0x8C01 #define PCI_CHIP_868 0x8880 #define PCI_CHIP_928 0x88B0 #define PCI_CHIP_864_0 0x88C0 *************** *** 154,161 **** #define PCI_CHIP_2000MT 0xA0A1 #define PCI_CHIP_2000MI 0xA0A9 /* Increase this as required */ ! #define MAX_DEV_PER_VENDOR 16 typedef struct vgaPCIInformation { int Vendor; --- 175,189 ---- #define PCI_CHIP_2000MT 0xA0A1 #define PCI_CHIP_2000MI 0xA0A9 + /* SIGMA DESIGNS */ + #define PCI_CHIP_SD_REALMAGIG64GX 0x6401 + + /* Intergraphics */ + #define PCI_CHIP_INTERG_1680 0x1680 + #define PCI_CHIP_INTERG_1682 0x1682 + /* Increase this as required */ ! #define MAX_DEV_PER_VENDOR 20 typedef struct vgaPCIInformation { int Vendor; *************** *** 202,211 **** {PCI_CHIP_MACH64ET, "Mach64 ET"}, {PCI_CHIP_MACH64VT, "Mach64 VT"}, {PCI_CHIP_MACH64VU, "Mach64 VT"}, - {PCI_CHIP_MACH64GP, "Mach64 GT"}, {PCI_CHIP_MACH64GT, "Mach64 GT"}, {PCI_CHIP_MACH64GU, "Mach64 GT"}, {PCI_CHIP_MACH64LT, "Mach64 LT"}, {0x0000, NULL}}}, {PCI_VENDOR_AVANCE, "Avance Logic", { {PCI_CHIP_ALG2301, "ALG2301"}, --- 230,243 ---- {PCI_CHIP_MACH64ET, "Mach64 ET"}, {PCI_CHIP_MACH64VT, "Mach64 VT"}, {PCI_CHIP_MACH64VU, "Mach64 VT"}, {PCI_CHIP_MACH64GT, "Mach64 GT"}, {PCI_CHIP_MACH64GU, "Mach64 GT"}, {PCI_CHIP_MACH64LT, "Mach64 LT"}, + {PCI_CHIP_MACH64GB, "Mach64 GT"}, + {PCI_CHIP_MACH64GD, "Mach64 GT"}, + {PCI_CHIP_MACH64GI, "Mach64 GT"}, + {PCI_CHIP_MACH64GP, "Mach64 GT"}, + {PCI_CHIP_MACH64GQ, "Mach64 GT"}, {0x0000, NULL}}}, {PCI_VENDOR_AVANCE, "Avance Logic", { {PCI_CHIP_ALG2301, "ALG2301"}, *************** *** 215,221 **** {PCI_CHIP_ET4000_W32P_B, "ET4000W32P revB"}, {PCI_CHIP_ET4000_W32P_C, "ET4000W32P revC"}, {PCI_CHIP_ET4000_W32P_D, "ET4000W32P revD"}, ! {PCI_CHIP_ET6000, "ET6000"}, {0x0000, NULL}}}, {PCI_VENDOR_WEITEK, "Weitek", { {PCI_CHIP_P9000, "P9000"}, --- 247,254 ---- {PCI_CHIP_ET4000_W32P_B, "ET4000W32P revB"}, {PCI_CHIP_ET4000_W32P_C, "ET4000W32P revC"}, {PCI_CHIP_ET4000_W32P_D, "ET4000W32P revD"}, ! {PCI_CHIP_ET6000, "ET6000/6100"}, ! {PCI_CHIP_ET6300, "ET6300"}, {0x0000, NULL}}}, {PCI_VENDOR_WEITEK, "Weitek", { {PCI_CHIP_P9000, "P9000"}, *************** *** 238,255 **** {PCI_CHIP_GD7542, "GD7542"}, {PCI_CHIP_GD7543, "GD7543"}, {PCI_CHIP_GD7548, "GD7548"}, {0x0000, NULL}}}, {PCI_VENDOR_NCR_2, "NCR", { {0x0000, NULL}}}, {PCI_VENDOR_TRIDENT, "Trident", { ! {PCI_CHIP_9320, "TGUI 9320"}, {PCI_CHIP_9420, "TGUI 9420"}, {PCI_CHIP_9440, "TGUI 9440"}, ! {PCI_CHIP_9660, "TGUI 9660/9680/9682"}, ! #if 0 ! {PCI_CHIP_9680, "TGUI 9680"}, ! {PCI_CHIP_9682, "TGUI 9682"}, ! #endif {0x0000, NULL}}}, {PCI_VENDOR_MATROX, "Matrox", { {PCI_CHIP_MGA2085, "MGA 2085PX"}, --- 271,290 ---- {PCI_CHIP_GD7542, "GD7542"}, {PCI_CHIP_GD7543, "GD7543"}, {PCI_CHIP_GD7548, "GD7548"}, + {PCI_CHIP_GD7555, "GD7555"}, {0x0000, NULL}}}, {PCI_VENDOR_NCR_2, "NCR", { {0x0000, NULL}}}, {PCI_VENDOR_TRIDENT, "Trident", { ! {PCI_CHIP_9320, "Cyber 9320"}, {PCI_CHIP_9420, "TGUI 9420"}, {PCI_CHIP_9440, "TGUI 9440"}, ! {PCI_CHIP_9660, "TGUI 96xx"}, ! {PCI_CHIP_9388, "Cyber 9388"}, ! {PCI_CHIP_9397, "Cyber 9397"}, ! {PCI_CHIP_9520, "Cyber 9520"}, ! {PCI_CHIP_9750, "3DImage975"}, ! {PCI_CHIP_9850, "3DImage985"}, {0x0000, NULL}}}, {PCI_VENDOR_MATROX, "Matrox", { {PCI_CHIP_MGA2085, "MGA 2085PX"}, *************** *** 256,261 **** --- 291,297 ---- {PCI_CHIP_MGA2064, "MGA 2064W"}, {PCI_CHIP_MGA1064, "MGA 1064SG"}, {PCI_CHIP_MGA2164, "MGA 2164W"}, + {PCI_CHIP_MGA2164_AGP, "MGA 2164W AGP"}, {0x0000, NULL}}}, {PCI_VENDOR_CHIPSTECH, "C&T", { {PCI_CHIP_65545, "65545"}, *************** *** 282,293 **** {PCI_VENDOR_NVIDIA, "NVidia", { {PCI_CHIP_NV1, "NV1"}, {0x0000, NULL}}}, {PCI_VENDOR_ALLIANCE, "Alliance Semiconductor", { {PCI_CHIP_AP6410, "ProMotion 6410"}, {PCI_CHIP_AP6422, "ProMotion 6422"}, {PCI_CHIP_AT24, "ProMotion AT24"}, {0x0000, NULL}}}, ! {PCI_VENDOR_3DLABS, "3Dlabs", { {PCI_CHIP_300SX, "GLINT 300SX"}, {PCI_CHIP_500TX, "GLINT 500TX"}, {PCI_CHIP_DELTA, "GLINT Delta"}, --- 318,335 ---- {PCI_VENDOR_NVIDIA, "NVidia", { {PCI_CHIP_NV1, "NV1"}, {0x0000, NULL}}}, + {PCI_VENDOR_NVIDIA_SGS, "NVidia/SGS-Thomson", { + {PCI_CHIP_RIVA128, "Riva128"}, + {0x0000, NULL}}}, {PCI_VENDOR_ALLIANCE, "Alliance Semiconductor", { {PCI_CHIP_AP6410, "ProMotion 6410"}, {PCI_CHIP_AP6422, "ProMotion 6422"}, {PCI_CHIP_AT24, "ProMotion AT24"}, {0x0000, NULL}}}, ! {PCI_VENDOR_RENDITION, "Rendition", { ! {PCI_CHIP_V1000, "Verite 1000"}, ! {0x0000, NULL}}}, ! {PCI_VENDOR_3DLABS, "3Dlabs", { {PCI_CHIP_300SX, "GLINT 300SX"}, {PCI_CHIP_500TX, "GLINT 500TX"}, {PCI_CHIP_DELTA, "GLINT Delta"}, *************** *** 302,307 **** --- 344,351 ---- {PCI_CHIP_PLATO_PX, "PLATO/PX"}, {PCI_CHIP_VIRGE_VX, "ViRGE/VX"}, {PCI_CHIP_VIRGE_DXGX, "ViRGE/DX or /GX"}, + {PCI_CHIP_VIRGE_GX2, "ViRGE/GX2"}, + {PCI_CHIP_VIRGE_MX, "ViRGE/MX"}, {PCI_CHIP_868, "868"}, {PCI_CHIP_928, "928"}, {PCI_CHIP_864_0, "864"}, *************** *** 315,320 **** --- 359,371 ---- {PCI_CHIP_2000PV, "2000PV"}, {PCI_CHIP_2000MT, "2000MT"}, {PCI_CHIP_2000MI, "2000MI"}, + {0x0000, NULL}}}, + {PCI_VENDOR_SIGMADESIGNS, "Sigma Designs", { + {PCI_CHIP_SD_REALMAGIG64GX, "REALmagic64/GX (SD 6425)"}, + {0x0000, NULL}}}, + {PCI_VENDOR_INTERGRAPHICS, "Intergraphics", { + {PCI_CHIP_INTERG_1680, "IGA-1680"}, + {PCI_CHIP_INTERG_1682, "IGA-1682"}, {0x0000, NULL}}}, {0x0000, NULL, { {0x0000, NULL}}}, *** ./programs/Xserver/hw/xfree86/xf86Version.h@@/PUBLIC-LATEST Sun Aug 10 13:07:49 1997 --- xc/programs/Xserver/hw/xfree86/xf86Version.h Fri Mar 6 16:25:51 1998 *************** *** 1,11 **** ! /* $XFree86: xc/programs/Xserver/hw/xfree86/xf86Version.h,v 3.236.2.39 1997/08/04 02:50:58 dawes Exp $ */ ! #define XF86_VERSION " 3.3.1 " /* The finer points in versions... */ #define XF86_VERSION_MAJOR 3 #define XF86_VERSION_MINOR 3 ! #define XF86_VERSION_SUBMINOR 1 #define XF86_VERSION_BETA 0 /* 0="", 1="A", 2="B", etc... */ #define XF86_VERSION_ALPHA 0 /* 0="", 1="a", 2="b", etc... */ --- 1,11 ---- ! /* $XFree86: xc/programs/Xserver/hw/xfree86/xf86Version.h,v 3.236.2.50 1998/03/02 09:58:21 dawes Exp $ */ ! #define XF86_VERSION " 3.3.2 " /* The finer points in versions... */ #define XF86_VERSION_MAJOR 3 #define XF86_VERSION_MINOR 3 ! #define XF86_VERSION_SUBMINOR 2 #define XF86_VERSION_BETA 0 /* 0="", 1="A", 2="B", etc... */ #define XF86_VERSION_ALPHA 0 /* 0="", 1="a", 2="b", etc... */ *************** *** 18,23 **** XF86_VERSION_BETA, \ XF86_VERSION_ALPHA) ! #define XF86_DATE "Jun 2 1997" ! /* $TOG: xf86Version.h /main/80 1997/08/10 13:06:25 kaleb $ */ --- 18,23 ---- XF86_VERSION_BETA, \ XF86_VERSION_ALPHA) ! #define XF86_DATE "March 2 1998" ! /* $TOG: xf86Version.h /main/81 1998/03/06 16:27:28 kaleb $ */ *** ./programs/Xserver/hw/xfree86/xf86config/Cards@@/PUBLIC-LATEST Sun Aug 10 13:07:54 1997 --- xc/programs/Xserver/hw/xfree86/xf86config/Cards Fri Mar 6 16:57:10 1998 *************** *** 1,4 **** ! # $TOG: Cards /main/29 1997/08/10 13:06:30 kaleb $ # This is the database of card definitions used by xf86config. # Each definition should have a NAME entry, CHIPSET (descriptive) and # SERVER (one of Mono, VGA16, SVGA, S3, 8514, Mach8, Mach32, Mach64, AGX, --- 1,4 ---- ! # $TOG: Cards /main/30 1998/03/06 16:58:48 kaleb $ # This is the database of card definitions used by xf86config. # Each definition should have a NAME entry, CHIPSET (descriptive) and # SERVER (one of Mono, VGA16, SVGA, S3, 8514, Mach8, Mach32, Mach64, AGX, *************** *** 18,24 **** # The majority of entries are just a binding of a model name to a # chipset/server and untested. # ! # $XFree86: xc/programs/Xserver/hw/xfree86/xf86config/Cards,v 3.51.2.11 1997/08/02 13:48:24 dawes Exp $ #Chips & Technologies --- 18,24 ---- # The majority of entries are just a binding of a model name to a # chipset/server and untested. # ! # $XFree86: xc/programs/Xserver/hw/xfree86/xf86config/Cards,v 3.51.2.15 1998/02/27 15:28:57 dawes Exp $ #Chips & Technologies *************** *** 645,650 **** --- 645,676 ---- NAME ELSA WINNER 1000/T2D SEE S3 Trio64V2/DX (generic) + + # S3 Aurora64V+ + + NAME S3 Aurora64V+ (generic) + CHIPSET S3 Aurora64V+ + SERVER S3 + NOCLOCKPROBE + LINE # Option "lcd_center" + LINE # Set_LCDClk <pixel_clock_for_LCD> + + NAME S3 86CM65 + SEE S3 Aurora64V+ (generic) + + NAME SHARP 9080 + SEE S3 Aurora64V+ (generic) + + NAME SHARP 9090 + SEE S3 Aurora64V+ (generic) + + NAME COMPAQ Armada 7730MT + SEE S3 Aurora64V+ (generic) + + NAME COMPAQ Armada 7380DMT + SEE S3 Aurora64V+ (generic) + + # S3 964/968 NAME S3 964 (generic) *************** *** 953,959 **** # S3 ViRGE,/DX,/GX and ViRGE/VX ! NAME S3 ViRGE (S3V server) CHIPSET S3 ViRGE SERVER S3V NOCLOCKPROBE --- 979,985 ---- # S3 ViRGE,/DX,/GX and ViRGE/VX ! NAME S3 ViRGE (old S3V server) CHIPSET S3 ViRGE SERVER S3V NOCLOCKPROBE *************** *** 966,972 **** LINE #Option "fifo_moderate" LINE #Option "pci_burst_on" LINE #Option "pci_retry" - LINE #Option "hw_cursor" NAME S3 ViRGE/DX (generic) CHIPSET S3 ViRGE/DX --- 992,997 ---- *************** *** 976,982 **** LINE #Option "fifo_moderate" LINE #Option "pci_burst_on" LINE #Option "pci_retry" - LINE #Option "hw_cursor" NAME S3 ViRGE/GX (generic) CHIPSET S3 ViRGE/GX --- 1001,1006 ---- *************** *** 986,994 **** LINE #Option "fifo_moderate" LINE #Option "pci_burst_on" LINE #Option "pci_retry" - LINE #Option "hw_cursor" NAME S3 86C325 (generic) SEE S3 ViRGE (generic) --- 1010,1040 ---- LINE #Option "fifo_moderate" LINE #Option "pci_burst_on" LINE #Option "pci_retry" + NAME S3 ViRGE/GX2 (generic) + CHIPSET S3 ViRGE/GX2 + SERVER SVGA + NOCLOCKPROBE + LINE #Option "xaa_benchmark" + LINE #Option "fifo_moderate" + LINE #Option "pci_burst_on" + LINE #Option "pci_retry" + + NAME S3 ViRGE/MX (generic) + CHIPSET S3 ViRGE/MX + SERVER SVGA + NOCLOCKPROBE + LINE #Option "lcd_center" + LINE #Set_LCDClk <pixel_clock_for_LCD> + LINE #Option "xaa_benchmark" + LINE #Option "fifo_moderate" + LINE #Option "pci_burst_on" + LINE #Option "pci_retry" + + + + NAME S3 86C325 (generic) SEE S3 ViRGE (generic) *************** *** 998,1004 **** --- 1044,1056 ---- NAME S3 86C385 (generic) SEE S3 ViRGE/GX (generic) + NAME S3 86C357 (generic) + SEE S3 ViRGE/GX2 (generic) + NAME S3 86C260 (generic) + SEE S3 ViRGE/MX (generic) + + NAME ELSA Victory 3D SEE S3 ViRGE (generic) *************** *** 1050,1055 **** --- 1102,1113 ---- NAME WinFast 3D S600 SEE LeadTek WinFast 3D S600 + NAME LeadTek WinFast 3D S680 + SEE S3 ViRGE/GX2 (generic) + + NAME WinFast 3D S600 + SEE LeadTek WinFast 3D S680 + NAME miro miroMedia 3D SEE S3 ViRGE (generic) *************** *** 1078,1084 **** LINE #Option "fifo_moderate" LINE #Option "pci_burst_on" LINE #Option "pci_retry" - LINE #Option "hw_cursor" NAME S3 86C988 (generic) --- 1136,1141 ---- *************** *** 1106,1114 **** --- 1163,1184 ---- SEE S3 ViRGE/VX (generic) + NAME Toshiba Tecra 750CDT + SEE S3 ViRGE/MX (generic) + NAME Toshiba Tecra 750DVD + SEE S3 ViRGE/MX (generic) + NAME Toshiba Tecra 540CDT + SEE S3 ViRGE/MX (generic) + NAME Toshiba Tecra 550CDT + SEE S3 ViRGE/MX (generic) + + + + + # ET4000/ET6000 NAME ET3000 (generic) *************** *** 1151,1156 **** --- 1221,1231 ---- LINE #Option "hw_cursor" # Use hardware cursor (see docs for limitations) LINE #Option "xaa_no_color_exp" # When text (or bitmap) is not rendered correctly + NAME ET6100 (generic) + CHIPSET ET6100 + SERVER XSuSE_Tseng + NOCLOCKPROBE + NAME Diamond Stealth 32 CLOCKCHIP icd2061a NOCLOCKPROBE *************** *** 1328,1333 **** --- 1403,1412 ---- CHIPSET ATI-Mach32 SERVER Mach32 + NAME ATI Mach32 + CHIPSET ATI-Mach32 + SERVER Mach32 + NAME ATI Mach64 CHIPSET ATI-Mach64 SERVER Mach64 *************** *** 1376,1381 **** --- 1455,1475 ---- SERVER Mach64 NOCLOCKPROBE + NAME ATI Xpert@Play PCI and AGP, 3D Rage Pro + CHIPSET ATI-Mach64 + SERVER Mach64 + NOCLOCKPROBE + + NAME ATI Xpert@Work, 3D Rage Pro + CHIPSET ATI-Mach64 + SERVER Mach64 + NOCLOCKPROBE + + NAME ATI Pro Turbo+PC2TV, 3D Rage II+DVD + CHIPSET ATI-Mach64 + SERVER Mach64 + NOCLOCKPROBE + NAME ATI Graphics Xpression with STG1702 RAMDAC SEE ATI Mach64 *************** *** 1744,1749 **** --- 1838,1873 ---- SERVER SVGA NOCLOCKPROBE + NAME Trident TGUI9682 (generic) + CHIPSET TGUI9682 + SERVER SVGA + NOCLOCKPROBE + + NAME Trident TGUI9685 (generic) + CHIPSET TGUI9685 + SERVER SVGA + NOCLOCKPROBE + + NAME Trident Cyber 9382 (generic) + CHIPSET Cyber9382 + SERVER SVGA + NOCLOCKPROBE + + NAME Trident Cyber 9385 (generic) + CHIPSET Cyber9385 + SERVER SVGA + NOCLOCKPROBE + + NAME Trident Cyber 9388 (generic) + CHIPSET Cyber9388 + SERVER SVGA + NOCLOCKPROBE + + NAME Trident Cyber 9397 (generic) + CHIPSET Cyber9397 + SERVER SVGA + NOCLOCKPROBE + # SiS NAME SiS SG86C201 *************** *** 1789,1794 **** --- 1913,1923 ---- SERVER SVGA NOCLOCKPROBE + NAME Matrox Millennium II AGP + CHIPSET mga2164w AGP + SERVER SVGA + NOCLOCKPROBE + NAME Matrox Mystique CHIPSET mga1064sg SERVER SVGA *************** *** 1801,1806 **** --- 1930,1971 ---- SERVER SVGA NOCLOCKPROBE + NAME RIVA128 + CHIPSET RIVA128 + SERVER SVGA + NOCLOCKPROBE + + NAME ELSA VICTORY ERAZOR + SEE RIVA128 + + NAME Diamond Viper 330 + SEE RIVA128 + + NAME STB Velocity 128 + SEE RIVA128 + + NAME ASUS 3Dexplorer + SEE RIVA128 + + # Alliance Semiconductor + + NAME Diamond Stealth Video 2500 + CHIPSET Alliance AT24 + SERVER SVGA + NOCLOCKPROBE + + NAME AT3D + CHIPSET Alliance AT3D + SERVER SVGA + NOCLOCKPROBE + LINE #Option "no_accel" + + NAME AT25 + SEE AT3D + + NAME Hercules Stingray 128 3D + SEE AT3D + # Misc NAME Techworks Ultimate 3D *************** *** 1817,1827 **** NAME Jaton Video-58P SEE ET6000 (generic) - - NAME Diamond Stealth Video 2500 - CHIPSET Alliance AT24 - SERVER SVGA - NOCLOCKPROBE NAME Rendition Verite 1000 CHIPSET Verite 1000 --- 1982,1987 ---- *** ./programs/Xserver/hw/xfree86/xf86config/cards.c@@/PUBLIC-LATEST Sat Jul 19 10:52:52 1997 --- xc/programs/Xserver/hw/xfree86/xf86config/cards.c Fri Mar 6 16:57:16 1998 *************** *** 1,10 **** ! /* $TOG: cards.c /main/10 1997/07/19 10:52:54 kaleb $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/xf86config/cards.c,v 3.11 1996/12/23 07:04:43 dawes Exp $ */ /* * Functions to manipulate card database. --- 1,10 ---- ! /* $TOG: cards.c /main/11 1998/03/06 16:58:53 kaleb $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/xf86config/cards.c,v 3.11.2.1 1998/01/18 10:35:45 hohndel Exp $ */ /* * Functions to manipulate card database. *************** *** 254,262 **** * Add general comments. */ for (i = 0; i <= lastcard; i++) { ! if (strcmp(card[i].server, "S3") == 0) appendstring(&card[i].lines, s3_comment); ! if (strncmp(card[i].chipset, "CL-GD", 5) == 0) appendstring(&card[i].lines, cirrus_comment); } --- 254,263 ---- * Add general comments. */ for (i = 0; i <= lastcard; i++) { ! if (card[i].server && strcmp(card[i].server, "S3") == 0) appendstring(&card[i].lines, s3_comment); ! if (card[i].chipset && ! strncmp(card[i].chipset, "CL-GD", 5) == 0) appendstring(&card[i].lines, cirrus_comment); } *** ./programs/Xserver/hw/xfree86/xf86config/xf86conf.man@@/PUBLIC-LATEST Tue Nov 4 21:18:04 1997 --- xc/programs/Xserver/hw/xfree86/xf86config/xf86conf.man Fri Mar 6 16:57:19 1998 *************** *** 1,5 **** .\" $XFree86: xc/programs/Xserver/hw/xfree86/xf86config/xf86conf.man,v 3.5 1996/12/23 07:04:44 dawes Exp $ ! .TH xf86config 1 "Release 6.4 (XFree86 3.3.1)" "X Version 11" .SH NAME xf86config \- generate an XF86Config file .SH SYNOPSIS --- 1,5 ---- .\" $XFree86: xc/programs/Xserver/hw/xfree86/xf86config/xf86conf.man,v 3.5 1996/12/23 07:04:44 dawes Exp $ ! .TH xf86config 1 "Version 3.2" "XFree86" .SH NAME xf86config \- generate an XF86Config file .SH SYNOPSIS *************** *** 13,16 **** XFree86(1), XF86Config(4/5), reconfig(1) .SH AUTHOR Harm Hanemaayer. ! .\" $TOG: xf86conf.man /main/10 1997/11/04 21:20:59 kaleb $ --- 13,16 ---- XFree86(1), XF86Config(4/5), reconfig(1) .SH AUTHOR Harm Hanemaayer. ! .\" $TOG: xf86conf.man /main/11 1998/03/06 16:58:57 kaleb $ *** ./programs/Xserver/hw/xfree86/xf86config/xf86config.c@@/PUBLIC-LATEST Sun Aug 10 13:08:00 1997 --- xc/programs/Xserver/hw/xfree86/xf86config/xf86config.c Fri Mar 6 16:57:23 1998 *************** *** 1,4 **** ! /* $XFree86: xc/programs/Xserver/hw/xfree86/xf86config/xf86config.c,v 3.37.2.4 1997/07/19 04:59:37 dawes Exp $ */ /* * This is a configuration program that will create a base XF86Config --- 1,4 ---- ! /* $XFree86: xc/programs/Xserver/hw/xfree86/xf86config/xf86config.c,v 3.37.2.5 1998/02/22 01:28:28 robin Exp $ */ /* * This is a configuration program that will create a base XF86Config *************** *** 71,77 **** * - The card database. * */ ! /* $TOG: xf86config.c /main/23 1997/08/10 13:06:35 kaleb $ */ #include <stdlib.h> #include <stdio.h> --- 71,77 ---- * - The card database. * */ ! /* $TOG: xf86config.c /main/24 1998/03/06 16:59:01 kaleb $ */ #include <stdlib.h> #include <stdio.h> *************** *** 139,151 **** #define TREEROOT "/usr/X11R6" #define TREEROOTLX "/usr/X11R6/lib/X11" #define MODULEPATH "/usr/X11R6/lib/modules" - #define CONFIGNAME "XF86Config" #else #define TREEROOT "/XFree86" #define TREEROOTLX "/XFree86/lib/X11" #define MODULEPATH "/XFree86/lib/modules" - #define CONFIGNAME "XConfig" #endif int config_mousetype; /* Mouse. */ int config_emulate3buttons; --- 139,150 ---- #define TREEROOT "/usr/X11R6" #define TREEROOTLX "/usr/X11R6/lib/X11" #define MODULEPATH "/usr/X11R6/lib/modules" #else #define TREEROOT "/XFree86" #define TREEROOTLX "/XFree86/lib/X11" #define MODULEPATH "/XFree86/lib/modules" #endif + #define CONFIGNAME "XF86Config" int config_mousetype; /* Mouse. */ int config_emulate3buttons; *************** *** 2852,2862 **** #else /* __EMX__ */ { printf("Please answer the following question with either 'y' or 'n'.\n"); ! printf("Shall I write it to the default location, drive:/XFree86/lib/X11/XConfig? "); getstring(s); printf("\n"); if (answerisyes(s)) { ! return __XOS2RedirRoot("/XFree86/lib/X11/XConfig",'/'); } #endif /* __EMX__ */ } --- 2851,2861 ---- #else /* __EMX__ */ { printf("Please answer the following question with either 'y' or 'n'.\n"); ! printf("Shall I write it to the default location, drive:/XFree86/lib/X11/XF86Config? "); getstring(s); printf("\n"); if (answerisyes(s)) { ! return __XOS2RedirRoot("/XFree86/lib/X11/XF86Config",'/'); } #endif /* __EMX__ */ } *************** *** 2865,2875 **** getstring(s); printf("\n"); if (answerisyes(s)) - #ifndef __EMX__ return "XF86Config"; - #else - return "XConfig"; - #endif printf("Please give a filename to write to: "); getstring(s); --- 2864,2870 ---- *** ./programs/Xserver/hw/xfree98/Imakefile@@/PUBLIC-LATEST Sun Jul 20 13:45:41 1997 --- xc/programs/Xserver/hw/xfree98/Imakefile Fri Mar 6 14:10:51 1998 *************** *** 1,9 **** ! XCOMM $TOG: Imakefile /main/10 1997/07/20 13:45:44 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree98/Imakefile,v 3.14 1996/12/23 07:04:53 dawes Exp $ #include <Server.tmpl> #define IHaveSubdirs --- 1,9 ---- ! XCOMM $TOG: Imakefile /main/11 1998/03/06 14:12:28 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree98/Imakefile,v 3.14.2.2 1998/02/24 13:54:31 hohndel Exp $ #include <Server.tmpl> #define IHaveSubdirs *************** *** 10,16 **** #if XF98GANBWAPServer || XF98NEC480Server || XF98NKVNECServer || \ XF98WABSServer || XF98WABEPServer || XF98WSNAServer || \ ! XF98TGUIServer VGA256SCREEN = vga256 #endif --- 10,16 ---- #if XF98GANBWAPServer || XF98NEC480Server || XF98NKVNECServer || \ XF98WABSServer || XF98WABEPServer || XF98WSNAServer || \ ! XF98TGUIServer || XF98MGAServer || XF98SVGAServer VGA256SCREEN = vga256 #endif *************** *** 81,87 **** #endif #ifdef FreeBSDArchitecture ! FREEBSDMOUSEDEV=" Device \"/dev/mse0\"" #else FREEBSDMOUSEDEV="XCOMM Device \"/dev/mse0\"" #endif --- 81,87 ---- #endif #ifdef FreeBSDArchitecture ! FREEBSDMOUSEDEV=" Device \"/dev/mse0\"" #else FREEBSDMOUSEDEV="XCOMM Device \"/dev/mse0\"" #endif *************** *** 99,104 **** --- 99,110 ---- NETBSDNEWMOUSEDEV="XCOMM Device \"/dev/lms0\"" #endif + #ifdef LinuxArchitecture + LINUXMOUSEDEV=" Device \"/dev/mouse\"" + #else + LINUXMOUSEDEV="XCOMM Device \"/dev/mouse\"" + #endif + #ifdef MinixArchitecture CppFileTarget($(XF86CONFIG), XF98Conf.cpp, -DRGBPATH=$(RGBPATH) -DMISCFONTPATH=$(MISCFONTPATH) *************** *** 110,115 **** --- 116,122 ---- -DFREEBSDMOUSEDEV=$(FREEBSDMOUSEDEV) -DNETBSDOLDMOUSEDEV=$(NETBSDOLDMOUSEDEV) -DNETBSDNEWMOUSEDEV=$(NETBSDNEWMOUSEDEV) + -DLINUXMOUSEDEV=$(LINUXMOUSEDEV) -DMODULEPATH=\"$(MODULEDIR)\" -DMANPAGE=$(MANPAGE), $(ICONFIGFILES)) #else *************** *** 124,129 **** --- 131,137 ---- -DFREEBSDMOUSEDEV=$(FREEBSDMOUSEDEV) \ -DNETBSDOLDMOUSEDEV=$(NETBSDOLDMOUSEDEV) \ -DNETBSDNEWMOUSEDEV=$(NETBSDNEWMOUSEDEV) \ + -DLINUXMOUSEDEV=$(LINUXMOUSEDEV) \ -DMODULEPATH=\"$(MODULEDIR)\" \ -DMANPAGE=$(MANPAGE), $(ICONFIGFILES)) #endif *** ./programs/Xserver/hw/xfree98/SuperProbe/Imakefile@@/PUBLIC-LATEST Sun Jul 20 13:46:03 1997 --- xc/programs/Xserver/hw/xfree98/SuperProbe/Imakefile Fri Mar 6 14:11:10 1998 *************** *** 1,10 **** ! XCOMM $TOG: Imakefile /main/10 1997/07/20 13:46:05 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree98/SuperProbe/Imakefile,v 3.12.2.2 1997/05/06 13:29:35 dawes Exp $ #if defined(SVR3Architecture) || defined(SVR4Architecture) || defined(SCOArchitecture) # define OSModule OS_SYSV #endif --- 1,10 ---- ! XCOMM $TOG: Imakefile /main/11 1998/03/06 14:12:48 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree98/SuperProbe/Imakefile,v 3.12.2.3 1998/02/20 14:28:03 robin Exp $ #if defined(SVR3Architecture) || defined(SVR4Architecture) || defined(SCOArchitecture) # define OSModule OS_SYSV #endif *************** *** 19,25 **** --- 19,29 ---- #endif #if defined(LinuxArchitecture) # define OSModule OS_Linux + #if defined(AlphaArchitecture) && !UseElfFormat /* fix/replacement for broken libc-0.43 io.c */ + OS_IO_SRC = glibcAxpIo.c + OS_IO_OBJ = glibcAxpIo.o #endif + #endif #if defined(LynxOSArchitecture) # define OSModule OS_LynxOS #endif *************** *** 37,43 **** # define OSModule OS_Os2 CCOPTIONS = -Zmts #endif ! #if defined(NetBSDArchitecture) \ && ((OSMajorVersion == 1 && OSMinorVersion >= 1) || OSMajorVersion >= 2) IOPERMDEFINES = -DUSE_I386_IOPL SYS_LIBRARIES = -li386 --- 41,47 ---- # define OSModule OS_Os2 CCOPTIONS = -Zmts #endif ! #if defined(OpenBSDArchitecture) || defined(NetBSDArchitecture) \ && ((OSMajorVersion == 1 && OSMinorVersion >= 1) || OSMajorVersion >= 2) IOPERMDEFINES = -DUSE_I386_IOPL SYS_LIBRARIES = -li386 *************** *** 50,60 **** SVGA_SRC = Tseng.c WD.c ChipsTech.c Video7.c Genoa.c Trident.c Oak.c \ Cirrus.c Ahead.c ATI.c S3.c AL.c Yamaha.c NCR.c MX.c \ RealTek.c Primus.c Compaq.c HMC.c UMC.c Weitek.c SiS.c \ ! ARK.c Alliance.c Matrox.c SigmaDesigns.c SVGA_OBJ = Tseng.o WD.o ChipsTech.o Video7.o Genoa.o Trident.o Oak.o \ Cirrus.o Ahead.o ATI.o S3.o AL.o Yamaha.o NCR.o MX.o \ RealTek.o Primus.o Compaq.o HMC.o UMC.o Weitek.o SiS.o \ ! ARK.o Alliance.o Matrox.o SigmaDesigns.o COPROC_SRC = 8514.c ATIMach.c I128.c GLINT.c COPROC_OBJ = 8514.o ATIMach.o I128.o GLINT.o SRCS = Main.c $(SVGA_SRC) $(COPROC_SRC) $(BASE_SRC) Print.c Utils.c $(OS_SRC) --- 54,64 ---- SVGA_SRC = Tseng.c WD.c ChipsTech.c Video7.c Genoa.c Trident.c Oak.c \ Cirrus.c Ahead.c ATI.c S3.c AL.c Yamaha.c NCR.c MX.c \ RealTek.c Primus.c Compaq.c HMC.c UMC.c Weitek.c SiS.c \ ! ARK.c Alliance.c Matrox.c SigmaDesigns.c Intergraphics.c SVGA_OBJ = Tseng.o WD.o ChipsTech.o Video7.o Genoa.o Trident.o Oak.o \ Cirrus.o Ahead.o ATI.o S3.o AL.o Yamaha.o NCR.o MX.o \ RealTek.o Primus.o Compaq.o HMC.o UMC.o Weitek.o SiS.o \ ! ARK.o Alliance.o Matrox.o SigmaDesigns.o Intergraphics.o COPROC_SRC = 8514.c ATIMach.c I128.c GLINT.c COPROC_OBJ = 8514.o ATIMach.o I128.o GLINT.o SRCS = Main.c $(SVGA_SRC) $(COPROC_SRC) $(BASE_SRC) Print.c Utils.c $(OS_SRC) *************** *** 74,85 **** PROG = SuperProbe AllTarget(ProgramTargetName($(PROG))) ! SetUIDProgramTarget($(PROG),$(OBJS),NullParameter,$(SPECIALS),NullParameter) #ifndef DontInstallPC98Version ! InstallProgramWithFlags($(PROG),$(BINDIR),$(INSTUIDFLAGS)) InstallManPage($(PROG),$(MANDIR)) #endif LinkSourceFile(00README,$(XF86SRC)/SuperProbe) LinkSourceFile(01.CopyRights,$(XF86SRC)/SuperProbe) LinkSourceFile(8514.c,$(XF86SRC)/SuperProbe) --- 78,93 ---- PROG = SuperProbe AllTarget(ProgramTargetName($(PROG))) ! NormalProgramTarget($(PROG),$(OBJS),NullParameter,$(SPECIALS),NullParameter) #ifndef DontInstallPC98Version ! InstallProgram($(PROG),$(BINDIR)) InstallManPage($(PROG),$(MANDIR)) #endif + #if defined(LinuxArchitecture) && defined(AlphaArchitecture) && !UseElfFormat + LinkSourceFile(glibcAxpIo.c,../common_hw) + #endif + LinkSourceFile(00README,$(XF86SRC)/SuperProbe) LinkSourceFile(01.CopyRights,$(XF86SRC)/SuperProbe) LinkSourceFile(8514.c,$(XF86SRC)/SuperProbe) *************** *** 102,107 **** --- 110,116 ---- LinkSourceFile(HMC.c,$(XF86SRC)/SuperProbe) LinkSourceFile(Herc.c,$(XF86SRC)/SuperProbe) LinkSourceFile(I128.c,$(XF86SRC)/SuperProbe) + LinkSourceFile(Intergraphics.c,$(XF86SRC)/SuperProbe) LinkSourceFile(MDA.c,$(XF86SRC)/SuperProbe) LinkSourceFile(MX.c,$(XF86SRC)/SuperProbe) LinkSourceFile(Main.c,$(XF86SRC)/SuperProbe) *** ./programs/Xserver/hw/xfree98/XF86Setup/Imakefile@@/PUBLIC-LATEST Sun Jul 20 13:46:13 1997 --- xc/programs/Xserver/hw/xfree98/XF86Setup/Imakefile Fri Mar 6 14:11:14 1998 *************** *** 1,9 **** ! XCOMM $TOG: Imakefile /main/7 1997/07/20 13:46:15 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree98/XF86Setup/Imakefile,v 3.10.2.1 1997/05/17 12:25:23 dawes Exp $ #include <Server.tmpl> #define IHaveSubdirs --- 1,9 ---- ! XCOMM $TOG: Imakefile /main/8 1998/03/06 14:12:52 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree98/XF86Setup/Imakefile,v 3.10.2.4 1998/02/26 13:59:13 dawes Exp $ #include <Server.tmpl> #define IHaveSubdirs *************** *** 30,36 **** TCL_FILES = phase1.tcl phase2.tcl phase3.tcl phase4.tcl phase5.tcl \ setuplib.tcl srvflags.tcl carddata.tcl \ card.tcl done.tcl filelist.tcl keyboard.tcl \ ! mondata.tcl monitor.tcl mouse.tcl LICENSE TCLLIB_FILES = tcllib/button.tcl tcllib/combobox.tcl tcllib/misc.tcl \ tcllib/downarrow.xbm tcllib/dialog.tcl tcllib/entry.tcl \ tcllib/focus.tcl tcllib/init.tcl tcllib/listbox.tcl \ --- 30,37 ---- TCL_FILES = phase1.tcl phase2.tcl phase3.tcl phase4.tcl phase5.tcl \ setuplib.tcl srvflags.tcl carddata.tcl \ card.tcl done.tcl filelist.tcl keyboard.tcl \ ! mseproto.tcl \ ! mondata.tcl monitor.tcl modeselect.tcl mouse.tcl LICENSE TCLLIB_FILES = tcllib/button.tcl tcllib/combobox.tcl tcllib/misc.tcl \ tcllib/downarrow.xbm tcllib/dialog.tcl tcllib/entry.tcl \ tcllib/focus.tcl tcllib/init.tcl tcllib/listbox.tcl \ *************** *** 40,46 **** tcllib/tkerror.tcl tcllib/uparrow.xbm tcllib/license.terms PICS_FILES = pics/vidcard.xbm pics/vidcard.msk \ pics/XFree86.xbm pics/XFree86.msk ! SUBDIRS = tcllib pics scripts #if BuildServersOnly && !defined(UseInstalled) /* Use installed X libraries and headers */ --- 41,47 ---- tcllib/tkerror.tcl tcllib/uparrow.xbm tcllib/license.terms PICS_FILES = pics/vidcard.xbm pics/vidcard.msk \ pics/XFree86.xbm pics/XFree86.msk ! SUBDIRS = tcllib pics scripts texts #if BuildServersOnly && !defined(UseInstalled) /* Use installed X libraries and headers */ *************** *** 70,76 **** $(TCLTK_LIBRARIES) $(XXF86VMLIB) $(XXF86MISCLIB) \ $(USEINSTALLEDLIB) XawClientLibs MathLibrary DEPLIBS = XawClientDepLibs $(DEPXXF86VMLIB) ! CARDDBFILE = $(LIBDIR)/Cards XCONFIGSRC = xf86Config XCONFIGFILE = XF86Config --- 71,77 ---- $(TCLTK_LIBRARIES) $(XXF86VMLIB) $(XXF86MISCLIB) \ $(USEINSTALLEDLIB) XawClientLibs MathLibrary DEPLIBS = XawClientDepLibs $(DEPXXF86VMLIB) ! CARDDBFILE = $(LIBDIR)/Cards98 XCONFIGSRC = xf86Config XCONFIGFILE = XF86Config *************** *** 80,104 **** XF86SETUPLIBDIR = $(LIBDIR)/XF86Setup DEFINES = -DCARD_DATABASE_FILE='"$(CARDDBFILE)"' \ ! $(XCONFIG_DEFINES) INCLUDES = -I../os-support -I../common \ -I$(SERVERSRC)/include -I$(XINCLUDESRC) \ -I$(EXTINCSRC) $(USEINSTALLEDINC) \ -I$(TCLINCDIR) -I$(TKINCDIR) #if HasLdRunPath CCENVSETUP = LD_RUN_PATH=$(USRLIBDIR):$(TCLLIBDIR) CCLINK = $(CCENVSETUP) $(CC) #endif ! AllTarget(ProgramTargetName(XF86Setup)) ! LinkSourceFile(Cards,$(XF86SRC)/xf86config) LinkSourceFile(cards.h,$(XF86SRC)/xf86config) LinkSourceFile(cards.c,$(XF86SRC)/xf86config) LinkSourceFile(xf86Config.c,$(XF86SRC)/common) LinkSourceFile(xf86_Config.h,$(XF86SRC)/common) LinkSourceFile(CHANGELOG,$(XF86SRC)/XF86Setup) LinkSourceFile(LICENSE,$(XF86SRC)/XF86Setup) LinkSourceFile(README,$(XF86SRC)/XF86Setup) --- 81,109 ---- XF86SETUPLIBDIR = $(LIBDIR)/XF86Setup DEFINES = -DCARD_DATABASE_FILE='"$(CARDDBFILE)"' \ ! $(XCONFIG_DEFINES) -DPC98 INCLUDES = -I../os-support -I../common \ -I$(SERVERSRC)/include -I$(XINCLUDESRC) \ -I$(EXTINCSRC) $(USEINSTALLEDINC) \ -I$(TCLINCDIR) -I$(TKINCDIR) + MSEPROTODEFS = $(STD_DEFINES) -DPC98 + #if HasLdRunPath CCENVSETUP = LD_RUN_PATH=$(USRLIBDIR):$(TCLLIBDIR) CCLINK = $(CCENVSETUP) $(CC) #endif ! AllTarget(ProgramTargetName(XF98Setup)) ! LinkSourceFile(Cards98,$(XF98SRC)/xf86config) LinkSourceFile(cards.h,$(XF86SRC)/xf86config) LinkSourceFile(cards.c,$(XF86SRC)/xf86config) LinkSourceFile(xf86Config.c,$(XF86SRC)/common) LinkSourceFile(xf86_Config.h,$(XF86SRC)/common) + CppFileTarget(mseproto.tcl, mseproto.cpp, $(MSEPROTODEFS), NullParameter) + LinkSourceFile(CHANGELOG,$(XF86SRC)/XF86Setup) LinkSourceFile(LICENSE,$(XF86SRC)/XF86Setup) LinkSourceFile(README,$(XF86SRC)/XF86Setup) *************** *** 108,119 **** LinkSourceFile(card.tcl,$(XF86SRC)/XF86Setup) LinkSourceFile(carddata.tcl,$(XF86SRC)/XF86Setup) LinkSourceFile(done.tcl,$(XF86SRC)/XF86Setup) - LinkSourceFile(filelist.tcl,$(XF86SRC)/XF86Setup) LinkSourceFile(keyboard.tcl,$(XF86SRC)/XF86Setup) LinkSourceFile(main.c,$(XF86SRC)/XF86Setup) LinkSourceFile(mondata.tcl,$(XF86SRC)/XF86Setup) LinkSourceFile(monitor.tcl,$(XF86SRC)/XF86Setup) LinkSourceFile(mouse.tcl,$(XF86SRC)/XF86Setup) LinkSourceFile(phase1.tcl,$(XF86SRC)/XF86Setup) LinkSourceFile(phase2.tcl,$(XF86SRC)/XF86Setup) LinkSourceFile(phase3.tcl,$(XF86SRC)/XF86Setup) --- 113,125 ---- LinkSourceFile(card.tcl,$(XF86SRC)/XF86Setup) LinkSourceFile(carddata.tcl,$(XF86SRC)/XF86Setup) LinkSourceFile(done.tcl,$(XF86SRC)/XF86Setup) LinkSourceFile(keyboard.tcl,$(XF86SRC)/XF86Setup) LinkSourceFile(main.c,$(XF86SRC)/XF86Setup) + LinkSourceFile(modeselect.tcl,$(XF86SRC)/XF86Setup) LinkSourceFile(mondata.tcl,$(XF86SRC)/XF86Setup) LinkSourceFile(monitor.tcl,$(XF86SRC)/XF86Setup) LinkSourceFile(mouse.tcl,$(XF86SRC)/XF86Setup) + LinkSourceFile(mseproto.cpp,$(XF86SRC)/XF86Setup) LinkSourceFile(phase1.tcl,$(XF86SRC)/XF86Setup) LinkSourceFile(phase2.tcl,$(XF86SRC)/XF86Setup) LinkSourceFile(phase3.tcl,$(XF86SRC)/XF86Setup) *************** *** 133,142 **** LinkSourceFile(tkother.c,$(XF86SRC)/XF86Setup) LinkSourceFile(xfsconf.h,$(XF86SRC)/XF86Setup) ! NormalProgramTarget(XF86Setup,$(OBJS),$(DEPLIBS),$(LOCAL_LIBRARIES) $(SYSTEM_LIBRARIES) $(EXTRASYSLIBS),NullParameter) ! #ifndef DontInstallPC98Version ! InstallProgram(XF86Setup,$(BINDIR)) ! #endif DependTarget() MakeSubdirs($(SUBDIRS)) --- 139,146 ---- LinkSourceFile(tkother.c,$(XF86SRC)/XF86Setup) LinkSourceFile(xfsconf.h,$(XF86SRC)/XF86Setup) ! NormalProgramTarget(XF98Setup,$(OBJS),$(DEPLIBS),$(LOCAL_LIBRARIES) $(SYSTEM_LIBRARIES) $(EXTRASYSLIBS),NullParameter) ! InstallProgram(XF98Setup,$(BINDIR)) DependTarget() MakeSubdirs($(SUBDIRS)) *** /dev/null Tue Jun 30 11:50:54 1998 --- xc/programs/Xserver/hw/xfree98/XF86Setup/filelist.tcl Fri Mar 6 14:11:19 1998 *************** *** 0 **** --- 1,100 ---- + # $TOG: filelist.tcl /main/1 1998/03/06 14:12:56 kaleb $ + # + # + # + # + # $XFree86: xc/programs/Xserver/hw/xfree98/XF86Setup/filelist.tcl,v 1.1.2.1 1998/02/26 13:59:14 dawes Exp $ + # + # Copyright 1996 by Joseph V. Moss <joe@XFree86.Org> + # + # See the file "LICENSE" for information regarding redistribution terms, + # and for a DISCLAIMER OF ALL WARRANTIES. + # + + # List of files that are needed by this program or programs spawned by it. + # These lists are not meant to be exhaustive, but they should be + # complete enough to ensure that all the needed .tgz files have been + # installed + + array set FilePermsDescriptions { + Libs "X11 libraries" + Cfg "configuration and application default files" + Fonts "standard font files" + DB "device, keysym, error, locale, and color databases" + Bin "standard X client programs" + VidTune "xvidtune configuration files and/or the xvidtune program" + XKB "X keyboard extension programs and configuration files" + } + + array set FilePermsLibs { + lib/libX11* 644 + lib/libXaw* 644 + lib/libXext* 644 + lib/libXi* 644 + lib/libXmu* 644 + lib/libXtst* 644 + lib/libSM* 644 + lib/libICE* 644 + } + + array set FilePermsCfg { + lib/X11/xinit/xinitrc 444 + lib/X11/app-defaults/Bitmap 444 + lib/X11/app-defaults/XLogo 444 + lib/X11/app-defaults/XTerm 444 + } + + array set FilePermsFonts { + lib/X11/fonts/misc/fonts.dir 444 + lib/X11/fonts/misc/fonts.alias 444 + lib/X11/fonts/misc/6x13.pc* 444 + lib/X11/fonts/75dpi/fonts.dir 444 + lib/X11/fonts/75dpi/symb10.pc* 444 + } + + array set FilePermsDB { + lib/X11/XErrorDB 444 + lib/X11/XKeysymDB 444 + lib/X11/rgb.txt 444 + lib/X11/Cards98 444 + lib/X11/locale/locale.dir 444 + lib/X11/locale/C/XLC_LOCALE 444 + } + + array set FilePermsBin { + bin/bitmap 755 + bin/mkfontdir 755 + bin/twm 755 + bin/xdpyinfo 755 + bin/xinit 755 + bin/xset 755 + bin/xterm 755 + } + + array set FilePermsVidTune { + bin/xvidtune 755 + lib/X11/app-defaults/Xvidtune 444 + } + + array set FilePermsXKB { + bin/xkbcomp 755 + lib/X11/xkb/xkbcomp 755 + lib/X11/xkb/compat/default 444 + lib/X11/xkb/compiled/README 444 + lib/X11/xkb/geometry/pc 444 + lib/X11/xkb/keycodes/xfree98 444 + lib/X11/xkb/keymap/xfree98 444 + lib/X11/xkb/semantics/default 444 + lib/X11/xkb/symbols/us 444 + lib/X11/xkb/types/default 444 + lib/X11/xkb/rules/xfree86 444 + lib/X11/xkb/rules/xfree86.lst 444 + } + + array set FilePermsReadMe { + lib/X11/doc/README.MGA 444 + lib/X11/doc/README.S3 444 + lib/X11/doc/README.cirrus 444 + lib/X11/doc/README.trident 444 + } + *** ./programs/Xserver/hw/xfree98/XF86Setup/scripts/Imakefile@@/PUBLIC-LATEST Sun Jul 20 13:46:23 1997 --- xc/programs/Xserver/hw/xfree98/XF86Setup/scripts/Imakefile Fri Mar 6 14:11:26 1998 *************** *** 1,9 **** ! XCOMM $TOG: Imakefile /main/3 1997/07/20 13:46:24 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree98/XF86Setup/scripts/Imakefile,v 3.1 1996/12/27 07:05:59 dawes Exp $ XF86SETUPLIBDIR = $(LIBDIR)/XF86Setup SCRIPTSDIR = $(XF86SETUPLIBDIR)/scripts --- 1,9 ---- ! XCOMM $TOG: Imakefile /main/4 1998/03/06 14:13:03 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree98/XF86Setup/scripts/Imakefile,v 3.1.2.1 1998/02/15 16:09:43 hohndel Exp $ XF86SETUPLIBDIR = $(LIBDIR)/XF86Setup SCRIPTSDIR = $(XF86SETUPLIBDIR)/scripts *************** *** 20,25 **** #endif LinkSourceFile(mseconfig.tcl,$(XF86SRC)/XF86Setup/scripts) - LinkSourceFile(xmseconfig,$(XF86SRC)/XF86Setup/scripts) LinkSourceFile(xmseconfig.man,$(XF86SRC)/XF86Setup/scripts) --- 20,24 ---- *** /dev/null Tue Jun 30 11:50:58 1998 --- xc/programs/Xserver/hw/xfree98/XF86Setup/scripts/xmseconfig Fri Mar 6 14:11:30 1998 *************** *** 0 **** --- 1,10 ---- + #! /bin/sh + # $TOG: xmseconfig /main/1 1998/03/06 14:13:07 kaleb $ + # + # + # + # + # $XFree86: xc/programs/Xserver/hw/xfree98/XF86Setup/scripts/xmseconfig,v 1.1.2.1 1998/02/15 16:09:44 hohndel Exp $ + # + + exec XF98Setup -script mseconfig.tcl "$@" *** /dev/null Tue Jun 30 11:50:59 1998 --- xc/programs/Xserver/hw/xfree98/XF86Setup/texts/Imakefile Fri Mar 6 14:11:34 1998 *************** *** 0 **** --- 1,22 ---- + XCOMM $TOG: Imakefile /main/1 1998/03/06 14:13:11 kaleb $ + + + + #include <Server.tmpl> + #define IHaveSubdirs + + XF86SETUPLIBDIR = $(LIBDIR)/XF86Setup + SCRIPTSDIR = $(XF86SETUPLIBDIR)/texts + + SCRIPTFILES = local_text.tcl + + SUBDIRS = generic ja + + all:: + + #ifndef DontInstallPC98Version + InstallMultiple($(SCRIPTFILES),$(SCRIPTSDIR)) + #endif + + LinkSourceFile(local_text.tcl,$(XF86SRC)/XF86Setup/texts) + *** /dev/null Tue Jun 30 11:51:00 1998 --- xc/programs/Xserver/hw/xfree98/XF86Setup/texts/generic/Imakefile Fri Mar 6 14:11:41 1998 *************** *** 0 **** --- 1,29 ---- + XCOMM $TOG: Imakefile /main/1 1998/03/06 14:13:18 kaleb $ + + + + + XF86SETUPLIBDIR = $(LIBDIR)/XF86Setup + SCRIPTSDIR = $(XF86SETUPLIBDIR)/texts/generic + + SCRIPTFILES = messages.tcl message_proc.tcl \ + help_card.tcl help_done.tcl help_keyboard.tcl \ + help_monitor.tcl help_mouse.tcl help_other.tcl \ + help_intro.tcl help_modeselect.tcl + + all:: + + #ifndef DontInstallPC98Version + InstallMultiple($(SCRIPTFILES),$(SCRIPTSDIR)) + #endif + + LinkSourceFile(messages.tcl,$(XF86SRC)/XF86Setup/texts/generic) + LinkSourceFile(message_proc.tcl,$(XF86SRC)/XF86Setup/texts/generic) + LinkSourceFile(help_card.tcl,$(XF86SRC)/XF86Setup/texts/generic) + LinkSourceFile(help_done.tcl,$(XF86SRC)/XF86Setup/texts/generic) + LinkSourceFile(help_keyboard.tcl,$(XF86SRC)/XF86Setup/texts/generic) + LinkSourceFile(help_monitor.tcl,$(XF86SRC)/XF86Setup/texts/generic) + LinkSourceFile(help_mouse.tcl,$(XF86SRC)/XF86Setup/texts/generic) + LinkSourceFile(help_other.tcl,$(XF86SRC)/XF86Setup/texts/generic) + LinkSourceFile(help_intro.tcl,$(XF86SRC)/XF86Setup/texts/generic) + LinkSourceFile(help_modeselect.tcl,$(XF86SRC)/XF86Setup/texts/generic) *** /dev/null Tue Jun 30 11:51:01 1998 --- xc/programs/Xserver/hw/xfree98/XF86Setup/texts/ja/Imakefile Fri Mar 6 14:11:44 1998 *************** *** 0 **** --- 1,29 ---- + XCOMM $TOG: Imakefile /main/1 1998/03/06 14:13:22 kaleb $ + + + + + XF86SETUPLIBDIR = $(LIBDIR)/XF86Setup + SCRIPTSDIR = $(XF86SETUPLIBDIR)/texts/ja/ + + SCRIPTFILES = messages.tcl message_proc.tcl \ + help_card.tcl help_done.tcl help_keyboard.tcl \ + help_monitor.tcl help_mouse.tcl help_other.tcl \ + help_intro.tcl help_modeselect.tcl + + all:: + + #ifndef DontInstallPC98Version + InstallMultiple($(SCRIPTFILES),$(SCRIPTSDIR)) + #endif + + LinkSourceFile(messages.tcl,$(XF86SRC)/XF86Setup/texts/ja) + LinkSourceFile(message_proc.tcl,$(XF86SRC)/XF86Setup/texts/ja) + LinkSourceFile(help_card.tcl,$(XF86SRC)/XF86Setup/texts/ja) + LinkSourceFile(help_done.tcl,$(XF86SRC)/XF86Setup/texts/ja) + LinkSourceFile(help_keyboard.tcl,$(XF86SRC)/XF86Setup/texts/ja) + LinkSourceFile(help_monitor.tcl,$(XF86SRC)/XF86Setup/texts/ja) + LinkSourceFile(help_mouse.tcl,$(XF86SRC)/XF86Setup/texts/ja) + LinkSourceFile(help_other.tcl,$(XF86SRC)/XF86Setup/texts/ja) + LinkSourceFile(help_intro.tcl,$(XF86SRC)/XF86Setup/texts/ja) + LinkSourceFile(help_modeselect.tcl,$(XF86SRC)/XF86Setup/texts/ja) *** ./programs/Xserver/hw/xfree98/XF98Conf.cpp@@/PUBLIC-LATEST Sun Jul 20 13:45:49 1997 --- xc/programs/Xserver/hw/xfree98/XF98Conf.cpp Fri Mar 6 14:10:57 1998 *************** *** 1,4 **** ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree98/XF98Conf.cpp,v 3.13 1997/01/19 12:51:41 dawes Exp $ XCOMM XCOMM Copyright (c) 1994 by The XFree86 Project, Inc. XCOMM --- 1,4 ---- ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree98/XF98Conf.cpp,v 3.13.2.3 1998/02/24 13:54:31 hohndel Exp $ XCOMM XCOMM Copyright (c) 1994 by The XFree86 Project, Inc. XCOMM *************** *** 25,31 **** XCOMM dealings in this Software without prior written authorization from the XCOMM XFree86 Project. XCOMM ! XCOMM $TOG: XF98Conf.cpp /main/10 1997/07/20 13:45:50 kaleb $ XCOMM ********************************************************************** XCOMM Refer to the XF86Config(4/5) man page for details about the format of --- 25,31 ---- XCOMM dealings in this Software without prior written authorization from the XCOMM XFree86 Project. XCOMM ! XCOMM $TOG: XF98Conf.cpp /main/11 1998/03/06 14:12:34 kaleb $ XCOMM ********************************************************************** XCOMM Refer to the XF86Config(4/5) man page for details about the format of *************** *** 42,48 **** XCOMM file minus the extension (like ".txt" or ".db"). There is normally XCOMM no need to change the default. ! RgbPath RGBPATH XCOMM Multiple FontPath entries are allowed (which are concatenated together), XCOMM as well as specifying multiple comma-separated entries in one FontPath --- 42,48 ---- XCOMM file minus the extension (like ".txt" or ".db"). There is normally XCOMM no need to change the default. ! RgbPath RGBPATH XCOMM Multiple FontPath entries are allowed (which are concatenated together), XCOMM as well as specifying multiple comma-separated entries in one FontPath *************** *** 168,184 **** XCOMM lines below (which are the defaults). XCOMM These are the default XKB settings for XFree98 ! XCOMM Xkbkeycodes "xfree98" ! XCOMM XkbTypes "default" ! XCOMM XkbCompat "pc98" ! XCOMM XkbSymbols "nec/jp(pc98)" ! XCOMM XkbGeometry "nec(pc98)" - XCOMM To specify a keymap file entry to use, use XkbKeymap. This will - XCOMM override the other Xkb parameters described above. - XCOMM An example is: - XCOMM XkbKeymap "xfree98" - EndSection --- 168,179 ---- XCOMM lines below (which are the defaults). XCOMM These are the default XKB settings for XFree98 ! XCOMM XkbRules "xfree98" ! XCOMM XkbModel "pc98" ! XCOMM XkbLayout "nec/jp" ! XCOMM XkbVariant "" ! XCOMM XkbOptions "" EndSection *************** *** 195,200 **** --- 190,197 ---- NETBSDNEWMOUSEDEV XCOMM For NetBSD/pc98 (based on NetBSD 1.0) NETBSDOLDMOUSEDEV + XCOMM For Linux/98 + LINUXMOUSEDEV XCOMM When using XQUEUE, comment out the above two lines, and uncomment XCOMM the following line. *************** *** 482,487 **** --- 479,485 ---- ChipSet "clgd5434" ClockChip "cirrus" Option "ga98nb1" + Option "no_mmio" XCOMM Option "mmio" XCOMM Option "sw_cursor" EndSection *************** *** 493,498 **** --- 491,497 ---- ChipSet "clgd5434" ClockChip "cirrus" Option "ga98nb2" + Option "no_mmio" XCOMM Option "mmio" XCOMM Option "sw_cursor" EndSection *************** *** 504,509 **** --- 503,509 ---- ChipSet "clgd5434" ClockChip "cirrus" Option "ga98nb4" + Option "no_mmio" XCOMM Option "mmio" XCOMM Option "sw_cursor" EndSection *************** *** 513,518 **** --- 513,519 ---- VendorName "MELCO" BoardName "WAP-2000/4000" Chipset "clgd5434" + Option "no_mmio" XCOMM Option "epsonmemwin" Option "wap" EndSection *************** *** 523,528 **** --- 524,531 ---- BoardName "PCNKV/PCNKV2/NEC_CIRRUS" Chipset "clgd5428" XCOMM Chipset "clgd5429" + XCOMM Chipset "clgd5430" + XCOMM Option "no_mmio" XCOMM Option "nec_cirrus" XCOMM Option "fast_dram" VideoRam 1024 *************** *** 532,537 **** --- 535,542 ---- Identifier "NECTrident" VendorName "NEC" BoardName "NEC Trident" + Option "xaa_no_color_exp" + XCOMM Option "noaccel" XCOMM Option "Linear" XCOMM Option "med_dram" XCOMM Option "hw_cursor" *************** *** 541,551 **** --- 546,565 ---- Identifier "GA-DRV98" VendorName "IO DATA" BoardName "GA-DRV/98" + Option "noaccel" XCOMM Option "med_dram" XCOMM Option "hw_cursor" + VideoRam 4096 + XCOMM VideoRam 2048 Endsection Section "Device" + Identifier "MGA" + VendorName "Matrox" + BoardName "Millennium" + EndSection + + Section "Device" Identifier "PW" VendorName "canopus" BoardName "PowerWndow928/801" *************** *** 693,698 **** --- 707,714 ---- Chipset "s3_generic" XCOMM Chipset "mmio_928" XCOMM Option "ga968" + VideoRam 4096 + XCOMM VideoRam 2048 Endsection XCOMM ********************************************************************** *************** *** 714,730 **** XCOMM Device "GA98NB4" XCOMM Device "NECTrident" XCOMM Device "GA-DRV98" Monitor "Multi sync" Subsection "Display" Depth 8 Modes "800x600" "640x480" "1024x768" XCOMM Modes "NEC480" "640x400" ViewPort 0 0 XCOMM Virtual 1024 1024 XCOMM Virtual 1024 1022 XCOMM Virtual 640 480 XCOMM Virtual 640 400 ! Virtual 1280 816 EndSubsection EndSection --- 730,749 ---- XCOMM Device "GA98NB4" XCOMM Device "NECTrident" XCOMM Device "GA-DRV98" + XCOMM Device "MGA" Monitor "Multi sync" Subsection "Display" Depth 8 Modes "800x600" "640x480" "1024x768" + XCOMM Modes "1024x768H" "640x400" XCOMM Modes "NEC480" "640x400" ViewPort 0 0 XCOMM Virtual 1024 1024 XCOMM Virtual 1024 1022 + Virtual 1024 768 XCOMM Virtual 640 480 XCOMM Virtual 640 400 ! XCOMM Virtual 1280 816 EndSubsection EndSection *** ./programs/Xserver/hw/xfree98/accel/s3nec/s3pc98.c@@/PUBLIC-LATEST Sun Jul 20 13:47:19 1997 --- xc/programs/Xserver/hw/xfree98/accel/s3nec/s3pc98.c Fri Mar 6 14:11:48 1998 *************** *** 1,9 **** ! /* $XFree86: xc/programs/Xserver/hw/xfree98/accel/s3nec/s3pc98.c,v 3.8 1996/12/23 07:05:51 dawes Exp $ */ ! /* $TOG: s3pc98.c /main/8 1997/07/20 13:47:20 kaleb $ */ #include "misc.h" #include "cfb.h" --- 1,9 ---- ! /* $XFree86: xc/programs/Xserver/hw/xfree98/accel/s3nec/s3pc98.c,v 3.8.2.1 1998/02/15 16:09:44 hohndel Exp $ */ ! /* $TOG: s3pc98.c /main/9 1998/03/06 14:13:25 kaleb $ */ #include "misc.h" #include "cfb.h" *************** *** 18,24 **** extern int xf86bpp; - #include "pc98_vers.h" #include "s3pc98.h" #define MasterClock 52000000l /* 52MHz */ --- 18,23 ---- *** ./programs/Xserver/hw/xfree98/common/Imakefile@@/PUBLIC-LATEST Sun Jul 20 13:50:16 1997 --- xc/programs/Xserver/hw/xfree98/common/Imakefile Fri Mar 6 14:11:53 1998 *************** *** 1,10 **** ! XCOMM $TOG: Imakefile /main/20 1997/07/20 13:50:17 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree98/common/Imakefile,v 3.28.2.1 1997/05/04 03:44:47 dawes Exp $ --- 1,10 ---- ! XCOMM $TOG: Imakefile /main/21 1998/03/06 14:13:30 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree98/common/Imakefile,v 3.28.2.3 1998/02/07 14:51:59 dawes Exp $ *************** *** 135,140 **** --- 135,141 ---- xf86Io.c \ xf86Lock.c \ xf86_Mouse.c \ + xf86_PnPMouse.c \ xf86_Option.c \ $(KBD).c \ $(XF86_XINPUT_SRC) \ *************** *** 155,160 **** --- 156,162 ---- xf86Io.o \ xf86Lock.o \ xf86_Mouse.o \ + xf86_PnPMouse.o \ $(XF86_XINPUT_OBJ) \ $(JOYSTICK_OBJ) \ $(WACOM_OBJ) \ *************** *** 230,236 **** SpecialObjectRule(xf86Init.o,xf86Init.c $(ICONFIGFILES),$(OSNAMEDEF) $(EXT_DEFINES) $(BETADEFS)) SpecialCObjectRule(xf86Events,$(ICONFIGFILES),$(EXT_DEFINES)) #if XF98GANBWAPServer || XF98NEC480Server || XF98NKVNECServer ||\ ! XF98WABSServer || XF98WABEPServer || XF98WSNAServer || XF98TGUIServer SpecialObjectRule(XF86_SVGA.o,XF86_SVGA.c $(ICONFIGFILES),$(XF86SCREENFLAGS)) all:: XF86_SVGA.o #endif --- 232,239 ---- SpecialObjectRule(xf86Init.o,xf86Init.c $(ICONFIGFILES),$(OSNAMEDEF) $(EXT_DEFINES) $(BETADEFS)) SpecialCObjectRule(xf86Events,$(ICONFIGFILES),$(EXT_DEFINES)) #if XF98GANBWAPServer || XF98NEC480Server || XF98NKVNECServer ||\ ! XF98WABSServer || XF98WABEPServer || XF98WSNAServer || XF98TGUIServer || \ ! XF98MGAServer || XF98SVGAServer SpecialObjectRule(XF86_SVGA.o,XF86_SVGA.c $(ICONFIGFILES),$(XF86SCREENFLAGS)) all:: XF86_SVGA.o #endif *************** *** 307,312 **** --- 310,316 ---- LinkSourceFile(xf86_Mouse.c,$(XF86SRC)/common) LinkSourceFile(xf86_Option.c,$(XF86SRC)/common) LinkSourceFile(xf86_Option.h,$(XF86SRC)/common) + LinkSourceFile(xf86_PnPMouse.c,$(XF86SRC)/common) InstallLinkKitLibrary(xf86,$(XF98LINKKITDIR)/lib98) InstallLinkKitNonExecFile(xf86Init.o,$(XF98LINKKITDIR)/lib98) *** ./programs/Xserver/hw/xfree98/common_hw/Imakefile@@/PUBLIC-LATEST Sun Jul 20 13:50:24 1997 --- xc/programs/Xserver/hw/xfree98/common_hw/Imakefile Fri Mar 6 14:11:58 1998 *************** *** 1,10 **** ! XCOMM $TOG: Imakefile /main/6 1997/07/20 13:50:25 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree98/common_hw/Imakefile,v 3.6 1996/12/23 07:06:39 dawes Exp $ #include <Server.tmpl> #define IHaveSubdirs --- 1,10 ---- ! XCOMM $TOG: Imakefile /main/7 1998/03/06 14:13:35 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree98/common_hw/Imakefile,v 3.6.2.1 1998/02/01 16:05:28 robin Exp $ #include <Server.tmpl> #define IHaveSubdirs *************** *** 23,29 **** #endif #if XF98GANBWAPServer || XF98NEC480Server || XF98NKVNECServer || \ XF98WABSServer || XF98WABEPServer || XF98WSNAServer || \ ! XF98TGUIServer || XF98EGCServer GENERICDIR = generic #endif --- 23,30 ---- #endif #if XF98GANBWAPServer || XF98NEC480Server || XF98NKVNECServer || \ XF98WABSServer || XF98WABEPServer || XF98WSNAServer || \ ! XF98TGUIServer || XF98MGAServer || XF98SVGAServer || \ ! XF98EGCServer GENERICDIR = generic #endif *** /dev/null Tue Jun 30 11:51:08 1998 --- xc/programs/Xserver/hw/xfree98/common_hw/Imakefile.chw Fri Mar 6 14:12:02 1998 *************** *** 0 **** --- 1,81 ---- + XCOMM $TOG: Imakefile.chw /main/1 1998/03/06 14:13:39 kaleb $ + + + + + XCOMM $XFree86: xc/programs/Xserver/hw/xfree98/common_hw/Imakefile.chw,v 1.3.2.1 1998/02/01 16:42:16 robin Exp $ + + #include <Server.tmpl> + + #if defined(LinuxArchitecture) && defined(AlphaArchitecture) + XSRCS = BUSmemcpy.c IODelay.c SlowBcopy.c + XOBJS = BUSmemcpy.o IODelay.o SlowBcopy.o + #else + XSRCS = BUSmemcpy.s IODelay.s SlowBcopy.s + XOBJS = BUSmemcpy.o IODelay.o SlowBcopy.o + #endif + + SRCS = I2061Acal.c I2061Aset.c I2061Aalt.c xf86_ClkPr.c \ + SC11412.c ATTDac.c S3gendac.c Ti3025clk.c \ + ICS2595.c CirrusClk.c Ch8391clk.c xf86_PCI.c Ti3026clk.c IBMRGB.c \ + STG1703clk.c $(XSRCS) + + OBJS = I2061Acal.o I2061Aset.o I2061Aalt.o xf86_ClkPr.o \ + SC11412.o ATTDac.o S3gendac.o Ti3025clk.o \ + ICS2595.o CirrusClk.o Ch8391clk.o xf86_PCI.o Ti3026clk.o IBMRGB.o \ + STG1703clk.o $(XOBJS) + + INCLUDES = -I. -I$(XF86COMSRC) -I$(XF86OSSRC) \ + -I$(SERVERSRC)/include -I$(XINCLUDESRC) -I$(XF86SRC)/accel/s3 + + DEFINES = -DPC98 CHWDEFINES + + NormalLibraryObjectRule() + NormalAsmObjectRule() + + NormalLibraryTarget(xf86_hw,$(OBJS)) + + #if !(defined(LinuxArchitecture) && defined(AlphaArchitecture)) + ObjectFromAsmSource(BUSmemcpy,NullParameter) + ObjectFromAsmSource(IODelay,NullParameter) + ObjectFromAsmSource(SlowBcopy,NullParameter) + #endif + + LinkSourceFile(ATTDac.c,$(XF86SRC)/common_hw) + LinkSourceFile(BUSmemcpy.c,$(XF86SRC)/common_hw) + LinkSourceFile(BUSmemcpy.s,$(XF86SRC)/common_hw) + LinkSourceFile(Ch8391clk.c,$(XF86SRC)/common_hw) + LinkSourceFile(CirrusClk.c,$(XF86SRC)/common_hw) + LinkSourceFile(CirrusClk.h,$(XF86SRC)/common_hw) + LinkSourceFile(I2061Aalt.c,$(XF86SRC)/common_hw) + LinkSourceFile(I2061Acal.c,$(XF86SRC)/common_hw) + LinkSourceFile(I2061Aset.c,$(XF86SRC)/common_hw) + LinkSourceFile(IBMRGB.c,$(XF86SRC)/common_hw) + LinkSourceFile(IBMRGB.h,$(XF86SRC)/common_hw) + LinkSourceFile(ICD2061A.h,$(XF86SRC)/common_hw) + LinkSourceFile(ICS2595.c,$(XF86SRC)/common_hw) + LinkSourceFile(ICS2595.h,$(XF86SRC)/common_hw) + LinkSourceFile(IODelay.c,$(XF86SRC)/common_hw) + LinkSourceFile(IODelay.s,$(XF86SRC)/common_hw) + LinkSourceFile(S3gendac.c,$(XF86SRC)/common_hw) + LinkSourceFile(S3gendac.h,$(XF86SRC)/common_hw) + LinkSourceFile(SC11412.c,$(XF86SRC)/common_hw) + LinkSourceFile(SC11412.h,$(XF86SRC)/common_hw) + LinkSourceFile(STG1703clk.c,$(XF86SRC)/common_hw) + LinkSourceFile(SlowBcopy.c,$(XF86SRC)/common_hw) + LinkSourceFile(SlowBcopy.s,$(XF86SRC)/common_hw) + LinkSourceFile(Ti3025clk.c,$(XF86SRC)/common_hw) + LinkSourceFile(Ti3026clk.c,$(XF86SRC)/common_hw) + LinkSourceFile(Ti302X.h,$(XF86SRC)/common_hw) + LinkSourceFile(xf86_ClkPr.c,$(XF86SRC)/common_hw) + LinkSourceFile(xf86_HWlib.h,$(XF86SRC)/common_hw) + LinkSourceFile(xf86_PCI.c,$(XF86SRC)/common_hw) + LinkSourceFile(xf86_PCI.h,$(XF86SRC)/common_hw) + + InstallLinkKitNamedLibrary(xf86_hw,xf86_hwgen,$(XF98LINKKITDIR)/lib98) + #ifndef DontInstallPC98Version + InstallLinkKitNonExecFile(xf86_HWlib.h,$(XF98LINKKITDIR)/include) + InstallLinkKitNonExecFile(xf86_PCI.h,$(XF98LINKKITDIR)/include) + #endif + + DependTarget() *** ./programs/Xserver/hw/xfree98/common_hw/ga968/Imakefile@@/PUBLIC-LATEST Sun Jul 20 13:50:28 1997 --- xc/programs/Xserver/hw/xfree98/common_hw/ga968/Imakefile Fri Mar 6 14:12:06 1998 *************** *** 1,87 **** ! XCOMM $TOG: Imakefile /main/4 1997/07/20 13:50:29 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree98/common_hw/ga968/Imakefile,v 3.3 1996/12/27 07:07:00 dawes Exp $ - - - #include <Server.tmpl> - - #if defined(LinuxArchitecture) && defined(AlphaArchitecture) - XSRCS = BUSmemcpy.c IODelay.c SlowBcopy.c - XOBJS = BUSmemcpy.o IODelay.o SlowBcopy.o - #else - XSRCS = BUSmemcpy.s IODelay.s SlowBcopy.s - XOBJS = BUSmemcpy.o IODelay.o SlowBcopy.o - #endif - - SRCS = I2061Acal.c I2061Aset.c I2061Aalt.c xf86_ClkPr.c \ - SC11412.c ATTDac.c S3gendac.c Ti3025clk.c \ - ICS2595.c CirrusClk.c Ch8391clk.c xf86_PCI.c Ti3026clk.c IBMRGB.c \ - STG1703clk.c $(XSRCS) - - OBJS = I2061Acal.o I2061Aset.o I2061Aalt.o xf86_ClkPr.o \ - SC11412.o ATTDac.o S3gendac.o Ti3025clk.o \ - ICS2595.o CirrusClk.o Ch8391clk.o xf86_PCI.o Ti3026clk.o IBMRGB.o \ - STG1703clk.o $(XOBJS) - - INCLUDES = -I. -I$(XF86COMSRC) -I$(XF86OSSRC) \ - -I$(SERVERSRC)/include -I$(XINCLUDESRC) -I$(XF86SRC)/accel/s3 - - DEFINES = -DPC98 -DPC98_GA968 - - NormalLibraryObjectRule() - NormalAsmObjectRule() - - NormalLibraryTarget(xf86_hw,$(OBJS)) - - #if !(defined(LinuxArchitecture) && defined(AlphaArchitecture)) - ObjectFromAsmSource(BUSmemcpy,NullParameter) - ObjectFromAsmSource(IODelay,NullParameter) - ObjectFromAsmSource(SlowBcopy,NullParameter) - #endif - - LinkSourceFile(ATTDac.c,$(XF86SRC)/common_hw) - LinkSourceFile(BUSmemcpy.c,$(XF86SRC)/common_hw) - LinkSourceFile(BUSmemcpy.s,$(XF86SRC)/common_hw) - LinkSourceFile(Ch8391clk.c,$(XF86SRC)/common_hw) - LinkSourceFile(CirrusClk.c,$(XF86SRC)/common_hw) - LinkSourceFile(CirrusClk.h,$(XF86SRC)/common_hw) - LinkSourceFile(I2061Aalt.c,$(XF86SRC)/common_hw) - LinkSourceFile(I2061Acal.c,$(XF86SRC)/common_hw) - LinkSourceFile(I2061Aset.c,$(XF86SRC)/common_hw) - LinkSourceFile(IBMRGB.c,$(XF86SRC)/common_hw) - LinkSourceFile(IBMRGB.h,$(XF86SRC)/common_hw) - LinkSourceFile(ICD2061A.h,$(XF86SRC)/common_hw) - LinkSourceFile(ICS2595.c,$(XF86SRC)/common_hw) - LinkSourceFile(ICS2595.h,$(XF86SRC)/common_hw) - LinkSourceFile(IODelay.c,$(XF86SRC)/common_hw) - LinkSourceFile(IODelay.s,$(XF86SRC)/common_hw) - LinkSourceFile(S3gendac.c,$(XF86SRC)/common_hw) - LinkSourceFile(S3gendac.h,$(XF86SRC)/common_hw) - LinkSourceFile(SC11412.c,$(XF86SRC)/common_hw) - LinkSourceFile(SC11412.h,$(XF86SRC)/common_hw) - LinkSourceFile(STG1703clk.c,$(XF86SRC)/common_hw) - LinkSourceFile(SlowBcopy.c,$(XF86SRC)/common_hw) - LinkSourceFile(SlowBcopy.s,$(XF86SRC)/common_hw) - LinkSourceFile(Ti3025clk.c,$(XF86SRC)/common_hw) - LinkSourceFile(Ti3026clk.c,$(XF86SRC)/common_hw) - LinkSourceFile(Ti302X.h,$(XF86SRC)/common_hw) - LinkSourceFile(xf86_ClkPr.c,$(XF86SRC)/common_hw) - LinkSourceFile(xf86_HWlib.h,$(XF86SRC)/common_hw) - LinkSourceFile(xf86_PCI.c,$(XF86SRC)/common_hw) - LinkSourceFile(xf86_PCI.h,$(XF86SRC)/common_hw) - InstallLinkKitNamedLibrary(xf86_hw,xf86_hwga968,$(XF98LINKKITDIR)/lib98) - #ifndef DontInstallPC98Version - InstallLinkKitNonExecFile(xf86_HWlib.h,$(XF98LINKKITDIR)/include) - InstallLinkKitNonExecFile(xf86_PCI.h,$(XF98LINKKITDIR)/include) - #endif - - DependTarget() - - --- 1,12 ---- ! XCOMM $TOG: Imakefile /main/5 1998/03/06 14:13:44 kaleb $ + XCOMM $XFree86: xc/programs/Xserver/hw/xfree98/common_hw/ga968/Imakefile,v 3.3.2.2 1998/02/01 22:08:13 robin Exp $ ! #define CHWDEFINES -DPC98_GA968 + #include "../Imakefile.chw" InstallLinkKitNamedLibrary(xf86_hw,xf86_hwga968,$(XF98LINKKITDIR)/lib98) *** ./programs/Xserver/hw/xfree98/common_hw/generic/Imakefile@@/PUBLIC-LATEST Sun Jul 20 13:50:32 1997 --- xc/programs/Xserver/hw/xfree98/common_hw/generic/Imakefile Fri Mar 6 14:12:10 1998 *************** *** 1,83 **** ! XCOMM $TOG: Imakefile /main/8 1997/07/20 13:50:33 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree98/common_hw/generic/Imakefile,v 3.5 1996/12/23 07:06:41 dawes Exp $ ! #include <Server.tmpl> ! #if defined(LinuxArchitecture) && defined(AlphaArchitecture) ! XSRCS = BUSmemcpy.c IODelay.c SlowBcopy.c ! XOBJS = BUSmemcpy.o IODelay.o SlowBcopy.o ! #else ! XSRCS = BUSmemcpy.s IODelay.s SlowBcopy.s ! XOBJS = BUSmemcpy.o IODelay.o SlowBcopy.o ! #endif - SRCS = I2061Acal.c I2061Aset.c I2061Aalt.c xf86_ClkPr.c \ - SC11412.c ATTDac.c S3gendac.c Ti3025clk.c \ - ICS2595.c CirrusClk.c Ch8391clk.c xf86_PCI.c Ti3026clk.c IBMRGB.c \ - STG1703clk.c $(XSRCS) - - OBJS = I2061Acal.o I2061Aset.o I2061Aalt.o xf86_ClkPr.o \ - SC11412.o ATTDac.o S3gendac.o Ti3025clk.o \ - ICS2595.o CirrusClk.o Ch8391clk.o xf86_PCI.o Ti3026clk.o IBMRGB.o \ - STG1703clk.o $(XOBJS) - - INCLUDES = -I. -I$(XF86COMSRC) -I$(XF86OSSRC) \ - -I$(SERVERSRC)/include -I$(XINCLUDESRC) -I$(XF86SRC)/accel/s3 - - DEFINES = -DPC98 - - NormalLibraryObjectRule() - NormalAsmObjectRule() - - NormalLibraryTarget(xf86_hw,$(OBJS)) - - #if !(defined(LinuxArchitecture) && defined(AlphaArchitecture)) - ObjectFromAsmSource(BUSmemcpy,NullParameter) - ObjectFromAsmSource(IODelay,NullParameter) - ObjectFromAsmSource(SlowBcopy,NullParameter) - #endif - - LinkSourceFile(ATTDac.c,$(XF86SRC)/common_hw) - LinkSourceFile(BUSmemcpy.c,$(XF86SRC)/common_hw) - LinkSourceFile(BUSmemcpy.s,$(XF86SRC)/common_hw) - LinkSourceFile(Ch8391clk.c,$(XF86SRC)/common_hw) - LinkSourceFile(CirrusClk.c,$(XF86SRC)/common_hw) - LinkSourceFile(CirrusClk.h,$(XF86SRC)/common_hw) - LinkSourceFile(I2061Aalt.c,$(XF86SRC)/common_hw) - LinkSourceFile(I2061Acal.c,$(XF86SRC)/common_hw) - LinkSourceFile(I2061Aset.c,$(XF86SRC)/common_hw) - LinkSourceFile(IBMRGB.c,$(XF86SRC)/common_hw) - LinkSourceFile(IBMRGB.h,$(XF86SRC)/common_hw) - LinkSourceFile(ICD2061A.h,$(XF86SRC)/common_hw) - LinkSourceFile(ICS2595.c,$(XF86SRC)/common_hw) - LinkSourceFile(ICS2595.h,$(XF86SRC)/common_hw) - LinkSourceFile(IODelay.c,$(XF86SRC)/common_hw) - LinkSourceFile(IODelay.s,$(XF86SRC)/common_hw) - LinkSourceFile(S3gendac.c,$(XF86SRC)/common_hw) - LinkSourceFile(S3gendac.h,$(XF86SRC)/common_hw) - LinkSourceFile(SC11412.c,$(XF86SRC)/common_hw) - LinkSourceFile(SC11412.h,$(XF86SRC)/common_hw) - LinkSourceFile(STG1703clk.c,$(XF86SRC)/common_hw) - LinkSourceFile(SlowBcopy.c,$(XF86SRC)/common_hw) - LinkSourceFile(SlowBcopy.s,$(XF86SRC)/common_hw) - LinkSourceFile(Ti3025clk.c,$(XF86SRC)/common_hw) - LinkSourceFile(Ti3026clk.c,$(XF86SRC)/common_hw) - LinkSourceFile(Ti302X.h,$(XF86SRC)/common_hw) - LinkSourceFile(xf86_ClkPr.c,$(XF86SRC)/common_hw) - LinkSourceFile(xf86_HWlib.h,$(XF86SRC)/common_hw) - LinkSourceFile(xf86_PCI.c,$(XF86SRC)/common_hw) - LinkSourceFile(xf86_PCI.h,$(XF86SRC)/common_hw) - InstallLinkKitNamedLibrary(xf86_hw,xf86_hwgen,$(XF98LINKKITDIR)/lib98) - #ifndef DontInstallPC98Version - InstallLinkKitNonExecFile(xf86_HWlib.h,$(XF98LINKKITDIR)/include) - InstallLinkKitNonExecFile(xf86_PCI.h,$(XF98LINKKITDIR)/include) - #endif - - DependTarget() - - --- 1,13 ---- ! XCOMM $TOG: Imakefile /main/9 1998/03/06 14:13:48 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree98/common_hw/generic/Imakefile,v 3.5.2.2 1998/02/01 22:08:14 robin Exp $ ! #define CHWDEFINES ! CHWLIBNAME = xf86_hwgen ! #include "../Imakefile.chw" InstallLinkKitNamedLibrary(xf86_hw,xf86_hwgen,$(XF98LINKKITDIR)/lib98) *** ./programs/Xserver/hw/xfree98/common_hw/nec/Imakefile@@/PUBLIC-LATEST Sun Jul 20 13:50:36 1997 --- xc/programs/Xserver/hw/xfree98/common_hw/nec/Imakefile Fri Mar 6 14:12:14 1998 *************** *** 1,83 **** ! XCOMM $TOG: Imakefile /main/8 1997/07/20 13:50:37 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree98/common_hw/nec/Imakefile,v 3.5 1996/12/23 07:06:51 dawes Exp $ ! #include <Server.tmpl> ! #if defined(LinuxArchitecture) && defined(AlphaArchitecture) ! XSRCS = BUSmemcpy.c IODelay.c SlowBcopy.c ! XOBJS = BUSmemcpy.o IODelay.o SlowBcopy.o ! #else ! XSRCS = BUSmemcpy.s IODelay.s SlowBcopy.s ! XOBJS = BUSmemcpy.o IODelay.o SlowBcopy.o ! #endif - SRCS = I2061Acal.c I2061Aset.c I2061Aalt.c xf86_ClkPr.c \ - SC11412.c ATTDac.c S3gendac.c Ti3025clk.c \ - ICS2595.c CirrusClk.c Ch8391clk.c xf86_PCI.c Ti3026clk.c IBMRGB.c \ - STG1703clk.c $(XSRCS) - - OBJS = I2061Acal.o I2061Aset.o I2061Aalt.o xf86_ClkPr.o \ - SC11412.o ATTDac.o S3gendac.o Ti3025clk.o \ - ICS2595.o CirrusClk.o Ch8391clk.o xf86_PCI.o Ti3026clk.o IBMRGB.o \ - STG1703clk.o $(XOBJS) - - INCLUDES = -I. -I$(XF86COMSRC) -I$(XF86OSSRC) \ - -I$(SERVERSRC)/include -I$(XINCLUDESRC) -I$(XF86SRC)/accel/s3 - - DEFINES = -DPC98 -DPC98_NEC - - NormalLibraryObjectRule() - NormalAsmObjectRule() - - NormalLibraryTarget(xf86_hw,$(OBJS)) - - #if !(defined(LinuxArchitecture) && defined(AlphaArchitecture)) - ObjectFromAsmSource(BUSmemcpy,NullParameter) - ObjectFromAsmSource(IODelay,NullParameter) - ObjectFromAsmSource(SlowBcopy,NullParameter) - #endif - - LinkSourceFile(ATTDac.c,$(XF86SRC)/common_hw) - LinkSourceFile(BUSmemcpy.c,$(XF86SRC)/common_hw) - LinkSourceFile(BUSmemcpy.s,$(XF86SRC)/common_hw) - LinkSourceFile(Ch8391clk.c,$(XF86SRC)/common_hw) - LinkSourceFile(CirrusClk.c,$(XF86SRC)/common_hw) - LinkSourceFile(CirrusClk.h,$(XF86SRC)/common_hw) - LinkSourceFile(I2061Aalt.c,$(XF86SRC)/common_hw) - LinkSourceFile(I2061Acal.c,$(XF86SRC)/common_hw) - LinkSourceFile(I2061Aset.c,$(XF86SRC)/common_hw) - LinkSourceFile(IBMRGB.c,$(XF86SRC)/common_hw) - LinkSourceFile(IBMRGB.h,$(XF86SRC)/common_hw) - LinkSourceFile(ICD2061A.h,$(XF86SRC)/common_hw) - LinkSourceFile(ICS2595.c,$(XF86SRC)/common_hw) - LinkSourceFile(ICS2595.h,$(XF86SRC)/common_hw) - LinkSourceFile(IODelay.c,$(XF86SRC)/common_hw) - LinkSourceFile(IODelay.s,$(XF86SRC)/common_hw) - LinkSourceFile(S3gendac.c,$(XF86SRC)/common_hw) - LinkSourceFile(S3gendac.h,$(XF86SRC)/common_hw) - LinkSourceFile(SC11412.c,$(XF86SRC)/common_hw) - LinkSourceFile(SC11412.h,$(XF86SRC)/common_hw) - LinkSourceFile(STG1703clk.c,$(XF86SRC)/common_hw) - LinkSourceFile(SlowBcopy.c,$(XF86SRC)/common_hw) - LinkSourceFile(SlowBcopy.s,$(XF86SRC)/common_hw) - LinkSourceFile(Ti3025clk.c,$(XF86SRC)/common_hw) - LinkSourceFile(Ti3026clk.c,$(XF86SRC)/common_hw) - LinkSourceFile(Ti302X.h,$(XF86SRC)/common_hw) - LinkSourceFile(xf86_ClkPr.c,$(XF86SRC)/common_hw) - LinkSourceFile(xf86_HWlib.h,$(XF86SRC)/common_hw) - LinkSourceFile(xf86_PCI.c,$(XF86SRC)/common_hw) - LinkSourceFile(xf86_PCI.h,$(XF86SRC)/common_hw) - InstallLinkKitNamedLibrary(xf86_hw,xf86_hwnec,$(XF98LINKKITDIR)/lib98) - #ifndef DontInstallPC98Version - InstallLinkKitNonExecFile(xf86_HWlib.h,$(XF98LINKKITDIR)/include) - InstallLinkKitNonExecFile(xf86_PCI.h,$(XF98LINKKITDIR)/include) - #endif - - DependTarget() - - --- 1,12 ---- ! XCOMM $TOG: Imakefile /main/9 1998/03/06 14:13:52 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree98/common_hw/nec/Imakefile,v 3.5.2.2 1998/02/01 22:08:14 robin Exp $ ! #define CHWDEFINES -DPC98_NEC ! #include "../Imakefile.chw" InstallLinkKitNamedLibrary(xf86_hw,xf86_hwnec,$(XF98LINKKITDIR)/lib98) *** ./programs/Xserver/hw/xfree98/common_hw/pwlb/Imakefile@@/PUBLIC-LATEST Sun Jul 20 13:50:40 1997 --- xc/programs/Xserver/hw/xfree98/common_hw/pwlb/Imakefile Fri Mar 6 14:12:19 1998 *************** *** 1,83 **** ! XCOMM $TOG: Imakefile /main/8 1997/07/20 13:50:41 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree98/common_hw/pwlb/Imakefile,v 3.5 1996/12/23 07:06:56 dawes Exp $ ! #include <Server.tmpl> ! #if defined(LinuxArchitecture) && defined(AlphaArchitecture) ! XSRCS = BUSmemcpy.c IODelay.c SlowBcopy.c ! XOBJS = BUSmemcpy.o IODelay.o SlowBcopy.o ! #else ! XSRCS = BUSmemcpy.s IODelay.s SlowBcopy.s ! XOBJS = BUSmemcpy.o IODelay.o SlowBcopy.o ! #endif - SRCS = I2061Acal.c I2061Aset.c I2061Aalt.c xf86_ClkPr.c \ - SC11412.c ATTDac.c S3gendac.c Ti3025clk.c \ - ICS2595.c CirrusClk.c Ch8391clk.c xf86_PCI.c Ti3026clk.c IBMRGB.c \ - STG1703clk.c $(XSRCS) - - OBJS = I2061Acal.o I2061Aset.o I2061Aalt.o xf86_ClkPr.o \ - SC11412.o ATTDac.o S3gendac.o Ti3025clk.o \ - ICS2595.o CirrusClk.o Ch8391clk.o xf86_PCI.o Ti3026clk.o IBMRGB.o \ - STG1703clk.o $(XOBJS) - - INCLUDES = -I. -I$(XF86COMSRC) -I$(XF86OSSRC) \ - -I$(SERVERSRC)/include -I$(XINCLUDESRC) -I$(XF86SRC)/accel/s3 - - DEFINES = -DPC98 -DPC98_PWLB - - NormalLibraryObjectRule() - NormalAsmObjectRule() - - NormalLibraryTarget(xf86_hw,$(OBJS)) - - #if !(defined(LinuxArchitecture) && defined(AlphaArchitecture)) - ObjectFromAsmSource(BUSmemcpy,NullParameter) - ObjectFromAsmSource(IODelay,NullParameter) - ObjectFromAsmSource(SlowBcopy,NullParameter) - #endif - - LinkSourceFile(ATTDac.c,$(XF86SRC)/common_hw) - LinkSourceFile(BUSmemcpy.c,$(XF86SRC)/common_hw) - LinkSourceFile(BUSmemcpy.s,$(XF86SRC)/common_hw) - LinkSourceFile(Ch8391clk.c,$(XF86SRC)/common_hw) - LinkSourceFile(CirrusClk.c,$(XF86SRC)/common_hw) - LinkSourceFile(CirrusClk.h,$(XF86SRC)/common_hw) - LinkSourceFile(I2061Aalt.c,$(XF86SRC)/common_hw) - LinkSourceFile(I2061Acal.c,$(XF86SRC)/common_hw) - LinkSourceFile(I2061Aset.c,$(XF86SRC)/common_hw) - LinkSourceFile(IBMRGB.c,$(XF86SRC)/common_hw) - LinkSourceFile(IBMRGB.h,$(XF86SRC)/common_hw) - LinkSourceFile(ICD2061A.h,$(XF86SRC)/common_hw) - LinkSourceFile(ICS2595.c,$(XF86SRC)/common_hw) - LinkSourceFile(ICS2595.h,$(XF86SRC)/common_hw) - LinkSourceFile(IODelay.c,$(XF86SRC)/common_hw) - LinkSourceFile(IODelay.s,$(XF86SRC)/common_hw) - LinkSourceFile(S3gendac.c,$(XF86SRC)/common_hw) - LinkSourceFile(S3gendac.h,$(XF86SRC)/common_hw) - LinkSourceFile(SC11412.c,$(XF86SRC)/common_hw) - LinkSourceFile(SC11412.h,$(XF86SRC)/common_hw) - LinkSourceFile(STG1703clk.c,$(XF86SRC)/common_hw) - LinkSourceFile(SlowBcopy.c,$(XF86SRC)/common_hw) - LinkSourceFile(SlowBcopy.s,$(XF86SRC)/common_hw) - LinkSourceFile(Ti3025clk.c,$(XF86SRC)/common_hw) - LinkSourceFile(Ti3026clk.c,$(XF86SRC)/common_hw) - LinkSourceFile(Ti302X.h,$(XF86SRC)/common_hw) - LinkSourceFile(xf86_ClkPr.c,$(XF86SRC)/common_hw) - LinkSourceFile(xf86_HWlib.h,$(XF86SRC)/common_hw) - LinkSourceFile(xf86_PCI.c,$(XF86SRC)/common_hw) - LinkSourceFile(xf86_PCI.h,$(XF86SRC)/common_hw) - InstallLinkKitNamedLibrary(xf86_hw,xf86_hwpwlb,$(XF98LINKKITDIR)/lib98) - #ifndef DontInstallPC98Version - InstallLinkKitNonExecFile(xf86_HWlib.h,$(XF98LINKKITDIR)/include) - InstallLinkKitNonExecFile(xf86_PCI.h,$(XF98LINKKITDIR)/include) - #endif - - DependTarget() - - --- 1,12 ---- ! XCOMM $TOG: Imakefile /main/9 1998/03/06 14:13:56 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree98/common_hw/pwlb/Imakefile,v 3.5.2.2 1998/02/01 22:08:15 robin Exp $ ! #define CHWDEFINES -DPC98_PWLB ! #include "../Imakefile.chw" InstallLinkKitNamedLibrary(xf86_hw,xf86_hwpwlb,$(XF98LINKKITDIR)/lib98) *** ./programs/Xserver/hw/xfree98/common_hw/pwskb/Imakefile@@/PUBLIC-LATEST Sun Jul 20 13:50:44 1997 --- xc/programs/Xserver/hw/xfree98/common_hw/pwskb/Imakefile Fri Mar 6 14:12:22 1998 *************** *** 1,83 **** ! XCOMM $TOG: Imakefile /main/8 1997/07/20 13:50:45 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree98/common_hw/pwskb/Imakefile,v 3.5 1996/12/23 07:06:58 dawes Exp $ ! #include <Server.tmpl> ! #if defined(LinuxArchitecture) && defined(AlphaArchitecture) ! XSRCS = BUSmemcpy.c IODelay.c SlowBcopy.c ! XOBJS = BUSmemcpy.o IODelay.o SlowBcopy.o ! #else ! XSRCS = BUSmemcpy.s IODelay.s SlowBcopy.s ! XOBJS = BUSmemcpy.o IODelay.o SlowBcopy.o ! #endif - SRCS = I2061Acal.c I2061Aset.c I2061Aalt.c xf86_ClkPr.c \ - SC11412.c ATTDac.c S3gendac.c Ti3025clk.c \ - ICS2595.c CirrusClk.c Ch8391clk.c xf86_PCI.c Ti3026clk.c IBMRGB.c \ - STG1703clk.c $(XSRCS) - - OBJS = I2061Acal.o I2061Aset.o I2061Aalt.o xf86_ClkPr.o \ - SC11412.o ATTDac.o S3gendac.o Ti3025clk.o \ - ICS2595.o CirrusClk.o Ch8391clk.o xf86_PCI.o Ti3026clk.o IBMRGB.o \ - STG1703clk.o $(XOBJS) - - INCLUDES = -I. -I$(XF86COMSRC) -I$(XF86OSSRC) \ - -I$(SERVERSRC)/include -I$(XINCLUDESRC) -I$(XF86SRC)/accel/s3 - - DEFINES = -DPC98 -DPC98_PW -DPC98_XKB - - NormalLibraryObjectRule() - NormalAsmObjectRule() - - NormalLibraryTarget(xf86_hw,$(OBJS)) - - #if !(defined(LinuxArchitecture) && defined(AlphaArchitecture)) - ObjectFromAsmSource(BUSmemcpy,NullParameter) - ObjectFromAsmSource(IODelay,NullParameter) - ObjectFromAsmSource(SlowBcopy,NullParameter) - #endif - - LinkSourceFile(ATTDac.c,$(XF86SRC)/common_hw) - LinkSourceFile(BUSmemcpy.c,$(XF86SRC)/common_hw) - LinkSourceFile(BUSmemcpy.s,$(XF86SRC)/common_hw) - LinkSourceFile(Ch8391clk.c,$(XF86SRC)/common_hw) - LinkSourceFile(CirrusClk.c,$(XF86SRC)/common_hw) - LinkSourceFile(CirrusClk.h,$(XF86SRC)/common_hw) - LinkSourceFile(I2061Aalt.c,$(XF86SRC)/common_hw) - LinkSourceFile(I2061Acal.c,$(XF86SRC)/common_hw) - LinkSourceFile(I2061Aset.c,$(XF86SRC)/common_hw) - LinkSourceFile(IBMRGB.c,$(XF86SRC)/common_hw) - LinkSourceFile(IBMRGB.h,$(XF86SRC)/common_hw) - LinkSourceFile(ICD2061A.h,$(XF86SRC)/common_hw) - LinkSourceFile(ICS2595.c,$(XF86SRC)/common_hw) - LinkSourceFile(ICS2595.h,$(XF86SRC)/common_hw) - LinkSourceFile(IODelay.c,$(XF86SRC)/common_hw) - LinkSourceFile(IODelay.s,$(XF86SRC)/common_hw) - LinkSourceFile(S3gendac.c,$(XF86SRC)/common_hw) - LinkSourceFile(S3gendac.h,$(XF86SRC)/common_hw) - LinkSourceFile(SC11412.c,$(XF86SRC)/common_hw) - LinkSourceFile(SC11412.h,$(XF86SRC)/common_hw) - LinkSourceFile(STG1703clk.c,$(XF86SRC)/common_hw) - LinkSourceFile(SlowBcopy.c,$(XF86SRC)/common_hw) - LinkSourceFile(SlowBcopy.s,$(XF86SRC)/common_hw) - LinkSourceFile(Ti3025clk.c,$(XF86SRC)/common_hw) - LinkSourceFile(Ti3026clk.c,$(XF86SRC)/common_hw) - LinkSourceFile(Ti302X.h,$(XF86SRC)/common_hw) - LinkSourceFile(xf86_ClkPr.c,$(XF86SRC)/common_hw) - LinkSourceFile(xf86_HWlib.h,$(XF86SRC)/common_hw) - LinkSourceFile(xf86_PCI.c,$(XF86SRC)/common_hw) - LinkSourceFile(xf86_PCI.h,$(XF86SRC)/common_hw) - InstallLinkKitNamedLibrary(xf86_hw,xf86_hwpwskb,$(XF98LINKKITDIR)/lib98) - #ifndef DontInstallPC98Version - InstallLinkKitNonExecFile(xf86_HWlib.h,$(XF98LINKKITDIR)/include) - InstallLinkKitNonExecFile(xf86_PCI.h,$(XF98LINKKITDIR)/include) - #endif - - DependTarget() - - --- 1,12 ---- ! XCOMM $TOG: Imakefile /main/9 1998/03/06 14:14:00 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree98/common_hw/pwskb/Imakefile,v 3.5.2.2 1998/02/01 22:08:15 robin Exp $ ! #define CHWDEFINES -DPC98_PW -DPC98_XKB ! #include "../Imakefile.chw" InstallLinkKitNamedLibrary(xf86_hw,xf86_hwpwskb,$(XF98LINKKITDIR)/lib98) *** /dev/null Tue Jun 30 11:51:17 1998 --- xc/programs/Xserver/hw/xfree98/os-support/linux/Imakefile Fri Mar 6 14:12:51 1998 *************** *** 0 **** --- 1,63 ---- + XCOMM $TOG: Imakefile /main/1 1998/03/06 14:14:29 kaleb $ + + + + + + XCOMM $XFree86: xc/programs/Xserver/hw/xfree98/os-support/linux/Imakefile,v 1.1.2.1 1998/02/01 16:42:16 robin Exp $ + + #include <Server.tmpl> + + #if BuildXInputExt + # if JoystickSupport + JOYSTICK_SRC = lnx_jstk.c + # endif + # if BuildDynamicLoading + SHARED_CFLAGS = PositionIndependentCFlags + # else + # if JoystickSupport + JOYSTICK_OBJ = lnx_jstk.o + # endif + # endif + #endif + + SRCS = lnx_init.c lnx_video.c IO_utils.c lnx_io.c bios_devmem.c mapVT_noop.c \ + VTsw_usl.c std_kbdEv.c posix_tty.c std_mouse.c std_mseEv.c $(JOYSTICK_SRC) + + OBJS = lnx_init.o lnx_video.o IO_utils.o lnx_io.o bios_devmem.o mapVT_noop.o \ + VTsw_usl.o std_kbdEv.o posix_tty.o std_mouse.o std_mseEv.o $(JOYSTICK_OBJ) + + INCLUDES = -I$(XF86COMSRC) -I$(XF86OSSRC) -I. -I$(SERVERSRC)/include \ + -I$(XINCLUDESRC) + + DEFINES = $(CONSDEFINES) $(APDEFINES) $(IOPERMDEFINES) -DPC98 + + SubdirLibraryRule($(OBJS)) + NormalLibraryObjectRule() + + #if BuildXInputExt + # if BuildDynamicLoading + # if JoystickSupport + AllTarget(lnx_jstk.o) + # ifndef DontInstallPC98Version + SpecialObjectRule(lnx_jstk.o,lnx_jstk.c,$(SHARED_CFLAGS)) + # endif + # endif + # endif + #endif + + LinkSourceFile(lnx_init.c,$(XF86OSSRC)/linux) + LinkSourceFile(lnx_io.c,$(XF86OSSRC)/linux) + LinkSourceFile(lnx_jstk.c,$(XF86OSSRC)/linux) + LinkSourceFile(lnx_video.c,$(XF86OSSRC)/linux) + + ObjectFromSpecialSource(bios_devmem,$(XF86OSSRC)/shared/bios_devmem,/**/) + ObjectFromSpecialSource(IO_utils,$(XF86OSSRC)/shared/IO_utils,/**/) + ObjectFromSpecialSource(mapVT_noop,$(XF86OSSRC)/shared/mapVT_noop,/**/) + ObjectFromSpecialSource(VTsw_usl,$(XF86OSSRC)/shared/VTsw_usl,/**/) + ObjectFromSpecialSource(std_kbdEv,$(XF86OSSRC)/shared/std_kbdEv,/**/) + ObjectFromSpecialSource(posix_tty,$(XF86OSSRC)/shared/posix_tty,/**/) + ObjectFromSpecialSource(std_mouse,$(XF86OSSRC)/shared/std_mouse,/**/) + ObjectFromSpecialSource(std_mseEv,$(XF86OSSRC)/shared/std_mseEv,/**/) + + DependTarget() *** ./programs/Xserver/hw/xfree98/doc/Japanese/README98@@/PUBLIC-LATEST Sun Jul 20 13:51:02 1997 --- xc/programs/Xserver/hw/xfree98/doc/Japanese/README98 Fri Mar 6 14:12:32 1998 *************** *** 1,57 **** XFree86 PC98 Dependent Information ! The XFree86 Project Inc. and X98 CORE TEAMÃø ! 1997ǯ 1·î 23Æü ! ¤³¤Î¥É¥­¥å¥á¥ó¥È¤Ç¤Ï¡¢PC98¥µ¡¼¥Ð¸ÇÍ­¤Î»ö¹à¤Ë¤Ä¤¤¤Æ²òÀ⤷¤Þ¤¹¡£ PC-AT¤È ! ¶¦Ä̤λö¹à¤Ë¤Ä¤¤¤Æ¤Ï¡¢¶¦Ä̤Υɥ­¥å¥á¥ó¥È¤ò»²¾È¤·¤Æ¤¯¤À¤µ¤¤¡£¤³¤Î¥É¥­¥å ! ¥á¥ó¥È¤Ç¤â¡¢³Æ¥µ¡¼¥Ð¤´¤È¤Ë»²¾È¤¹¤Ù¤­¥É¥­¥å¥á¥ó¥È¤ò¼¨¤·¤Æ¤¤¤Þ¤¹¤Î¤Ç»²¹Í ! ¤Ë¤·¤Æ¤¯¤À¤µ¤¤¡£ ! 1.¥µ¥Ý¡¼¥È¥µ¡¼¥ÐµÚ¤Ó¹½À® ! PC98ÍÑ¥µ¡¼¥Ð¤Ï¡¢°Ê²¼¤Î³ÈÄ¥¥Ó¥Ç¥ª¥Ü¡¼¥É¡¢Æ⢥ӥǥª¥·¥¹¥Æ¥à¤ËÂбþ¤·¤Æ¤¤ ! ¤Þ¤¹¡£¸Ä¡¹¤ÎÂбþ¡¢Æ°ºî¾õ¶·¤Ë¤Ä¤¤¤Æ¤ÏVideoBoard98¤ò»²¾È¤·¤Æ¤¯¤À¤µ¤¤¡£ ! 1.1.¥µ¥Ý¡¼¥È¥«¡¼¥É°ìÍ÷ ! ! ¥Ù¥ó¥À¡¼ ¥«¡¼¥É̾¾Î ¥µ¡¼¥Ð ! ------------- --------------------------------------- ---------------- ! MELCO WAB-S, WAB-1000, WAB-2000, WSR-E, WSR-G XF98_WABS ! MELCO WAP-2000, WAP-4000 XF98_GANBWAP ! MELCO WAB-EP XF98_WABEP ! MELCO WSN-A2F XF98_WSNA ! IO Data GA-98NB I/C,GA-98NB II, GA-98NB IV XF98_GANBWAP ! GA-968V2/PCI, GA-968V4/PCI XF98_GA968 ! GA-DRV2/98, GA-DRV4/98 XF98_TGUI ! NEC ¥¦¥£¥ó¥É¥¦¥¢¥¯¥»¥é¥ì¡¼¥¿¥Ü¡¼¥É A/B XF98_NECS3 ! Canopus PowerWindow 801, 801+, 928, 928G, 801G, XF98_PWSKB 928II, 805i ! Canopus PowerWindow 928IILB, 928GLB, 964LB XF98_PWLB ! EPSON PCSKB, PCSKB2, PCSKB3,PCSKB4,PCPKB4 XF98_PWSKB ! 1.2.¥µ¥Ý¡¼¥ÈÆ⢥ӥǥª¥·¥¹¥Æ¥à°ìÍ÷ - - ¥Ù¥ó¥À¡¼ ¥Á¥Ã¥×¥»¥Ã¥È ¥µ¡¼¥Ð - ------------- --------------------------------------- ---------------- - NEC/EPSON EGC(640x400x16) XF98_EGC - NEC PEGC(640x400x256,640x480x256) XF98_NEC480 - NEC S3 928(As2Åù), S3 864(As3Åù) XF98_NECS3 - NEC Cirrus CLGD5428/5430(B-Mate,Xe,CanBeÅù) XF98_NKVNEC - NEC Trident TGUI9680XGi(X-Mate,ValueStarÅù) XF98_TGUI - EPSON NKV(486MR,MS,MV,586MVÅù) XF98_NKVNEC - - - - 2.¶¦ÄÌ»ö¹à - - xf86config ! PC98ÍѤ˰ܿ¢¤µ¤ì¤Æ¤¤¤Þ¤»¤ó¡£/usr/X11R6/lib/X11/XF86Config.98¤ò ! XF86Config¤È¥ê¥Í¡¼¥à¤·¤Æ»ÈÍѤ·¤Æ¤¯¤À¤µ¤¤¡£ xvidtune ¸·³Ê¤ÊÆ°ºî³Îǧ¤ò¹Ô¤Ã¤Æ¤¤¤Þ¤»¤ó¤¬¡¢Æ°ºî¤¹¤ë¤è¤¦¤Ç¤¹¡£ --- 1,57 ---- XFree86 PC98 Dependent Information ! The XFree86 Project Inc. and X98 CORE TEAM Ãø ! 1998 ǯ 2 ·î 27 Æü ! ¤³¤Î¥É¥­¥å¥á¥ó¥È¤Ç¤Ï¡¢PC98 ¥µ¡¼¥Ð¸ÇÍ­¤Î»ö¹à¤Ë¤Ä¤¤¤Æ²òÀ⤷¤Þ¤¹¡£PC-AT ! ¤È¶¦Ä̤λö¹à¤Ë¤Ä¤¤¤Æ¤Ï¡¢¶¦Ä̤Υɥ­¥å¥á¥ó¥È¤ò»²¾È¤·¤Æ¤¯¤À¤µ¤¤¡£¤³¤Î¥É ! ¥­¥å¥á¥ó¥È¤Ç¤â¡¢³Æ¥µ¡¼¥Ð¤´¤È¤Ë»²¾È¤¹¤Ù¤­¥É¥­¥å¥á¥ó¥È¤ò¼¨¤·¤Æ¤¤¤Þ¤¹¤Î¤Ç ! »²¹Í¤Ë¤·¤Æ¤¯¤À¤µ¤¤¡£ ! 1. ¥µ¥Ý¡¼¥È¥µ¡¼¥ÐµÚ¤Ó¹½À® ! PC98 ÍÑ¥µ¡¼¥Ð¤Ï¡¢°Ê²¼¤Î³ÈÄ¥¥Ó¥Ç¥ª¥Ü¡¼¥É¡¢Æ⢥ӥǥª¥·¥¹¥Æ¥à¤ËÂбþ¤·¤Æ ! ¤¤¤Þ¤¹¡£¸Ä¡¹¤ÎÂбþ¡¢Æ°ºî¾õ¶·¤Ë¤Ä¤¤¤Æ¤Ï VideoBoard98 ¤ò»²¾È¤·¤Æ¤¯¤À¤µ ! ¤¤¡£ ! 1.1. ¥µ¥Ý¡¼¥È¥«¡¼¥É°ìÍ÷ ! ¥Ù¥ó¥À¡¼ ¥«¡¼¥É̾¾Î ¥µ¡¼¥Ð ! ------------- ----------------------------------------------- ------------- ! MELCO WAB-S, WAB-1000, WAB-2000, WSR-E, WSR-G XF98_WABS ! MELCO WAP-2000, WAP-4000 XF98_GANBWAP ! MELCO WAB-EP XF98_WABEP ! MELCO WSN-A2F XF98_WSNA ! IO Data GA-98NB I/C,GA-98NB II, GA-98NB IV XF98_GANBWAP ! GA-968V2/PCI, GA-968V4/PCI XF98_GA968 ! GA-DRV2/98, GA-DRV4/98 XF98_TGUI ! ICM GI-5434-2M, GI-5434-4M XF98_GANBWAP ! NEC ¥¦¥£¥ó¥É¥¦¥¢¥¯¥»¥é¥ì¡¼¥¿¥Ü¡¼¥É A/B XF98_NECS3 ! NEC ¥Õ¥ë¥«¥é¡¼¥¦¥£¥ó¥É¥¦¥¢¥¯¥»¥é¥ì¡¼¥¿¥Ü¡¼¥É A/B XF98_NECS3 ! NEC ¥Õ¥ë¥«¥é¡¼¥¦¥£¥ó¥É¥¦¥¢¥¯¥»¥é¥ì¡¼¥¿¥Ü¡¼¥É X2 XF98_MGA ! Canopus PowerWindow 801, 801+, 928, 928G, 801G, XF98_PWSKB 928II, 805i ! Canopus PowerWindow 928IILB, 928GLB, 964LB XF98_PWLB ! EPSON PCSKB, PCSKB2, PCSKB3, PCSKB4, PCPKB4 XF98_PWSKB ! Matrox MGA Millennium(PC/AT ¸ß´¹µ¡ÍÑ) XF98_MGA + 1.2. ¥µ¥Ý¡¼¥ÈÆ⢥ӥǥª¥·¥¹¥Æ¥à°ìÍ÷ + ¥Ù¥ó¥À¡¼ ¥Á¥Ã¥×¥»¥Ã¥È ¥µ¡¼¥Ð + ------------- ----------------------------------------------- ------------- + NEC/EPSON EGC(640x400, 4bpp) XF98_EGC + NEC PEGC(640x400/640x480, 8bpp) XF98_NEC480 + NEC S3 928(As2 Åù), S3 864(As3 Åù) XF98_NECS3 + NEC Cirrus CLGD5428/543x/544x(B-Mate,Xe,CanBe Åù) XF98_NKVNEC + NEC Trident TGUI968xXGi(X-Mate,ValueStar Åù) XF98_TGUI + NEC MGA Millennium/Mystique XF98_MGA + NEC Cirrus CLGD755x(Aile) XF98_SVGA + EPSON NKV(486MR,MS,MV,586MV Åù) XF98_NKVNEC ! 2. ¶¦ÄÌ»ö¹à xf86config ! PC98 ÍѤ˰ܿ¢¤µ¤ì¤Æ¤¤¤Þ¤»¤ó¡£XF98Setup ¤ò»È¤¦¤«¡¢/usr/X11R6/lib/ ! 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EPSON PCSKB3/PCSKB4/PCPKB4¤Ç»ÈÍѤ¹¤ë¾ì¹ç¡¢É¬¤º»ØÄꤷ¤Æ¤¯¤À¤µ¤¤¡£ Option ``pchkb'' ! EPSON PCHKBÍѤËͽÌ󤵤ì¤Æ¤¤¤Þ¤¹¡£¤ª¤½¤é¤¯Æ°ºî¤·¤Þ¤»¤ó¡£ Option ``pw805i'' ! PowerWindow805i¤Ç»ÈÍѤ¹¤ë»þ¤Ë»ØÄꤷ¤Þ¤¹¡£¤¿¤À¤·¡¢»ØÄꤷ¤Ê¤¤¾õÂÖ ¤Î¤Û¤¦¤¬°ÂÄêÆ°ºî¤¹¤ëÎã¤âÊó¹ð¤µ¤ì¤Æ¤¤¤Þ¤¹¡£ Option ``pw_mux'' ! PW928II¤ÇRAMDAC¤ÎMUX¥â¡¼¥É¤ò»È¤¤¡¢85MHz°Ê¾å¤òÆ°ºî²Äǽ¤Ë¤·¤Þ¤¹¡£ ! ¥á¡¼¥«¤«¤é¡¢¾ðÊóÄ󶡤ò¼õ¤Æ¤¤¤Ê¤¤¤Î¤Ç¡¢°ÂÁ´¤ËÆ°ºî¤·¤Æ¤¤¤ë¤«ÉÔÌÀ¤Ç ! ¤¢¤ê¥ê¥¹¥¯¤òȼ¤¤¤Þ¤¹¡£ºÇ°­¤Î¾ì¹ç¡¢¥Ó¥Ç¥ª¥Ü¡¼¥É¤òÇË»¤¹¤ë²ÄǽÀ­¤¬ ! ¤¢¤ê¤Þ¤¹¡£ Option ``nomemaccess'' ! VRAM¤Î¥á¥â¥ê¶õ´Ö¤Ø¤Î¥Þ¥Ã¥Ô¥ó¥°¤ò¹Ô¤¤¤Þ¤»¤ó¡£Èó¾ï¤ËÆ°ºî¤¬ÃÙ¤¯¤Ê¤ê ! ¤Þ¤¹¡£PCSKB4/PCPKB4¡¢¤Þ¤¿¤Ï¡¢NOTE+³ÈÄ¥BOX¤Î¾ì¹çɬÍפǤ¹¡£ Option ``epsonmemwin'' ! ESPON PC486GR¥·¥ê¡¼¥º°ÊÁ°¤Îµ¡¼ï¤Ç¡¢0xf00000¤ØVRAM¤ò¥Þ¥Ã¥Ô¥ó¥°²Ä ! ǽ¤Ë¤·¤Þ¤¹¡£FreeBSD(98)¤Ç¤Ï¥«¡¼¥Í¥ëconfig»þ¤Ë»ØÄꤹ¤ë»ö¤Ç¡¢¥«¡¼ ! ¥Í¥ë¦¤ÇƱÅù¤Îµ¡Ç½¤ò¼Â¸½¤·¤Æ¤¤¤Þ¤¹¡£Ä̾ï¤Ï¥«¡¼¥Í¥ë¦¤Ç»ØÄꤷ¡¢ ! XF86Config¤Ç¤Ï¤³¤Î¥ª¥×¥·¥ç¥ó¤ò»ØÄꤷ¤Þ¤»¤ó¡£NetBSD/pc98(based on ! NetBSD 1.2)¤Ç¤Ï¡¢É¬¤º¤³¤Î¥ª¥×¥·¥ç¥ó¤ò»ØÄꤷ¤Æ¤¯¤À¤µ¤¤¡£¤Þ¤¿¡¢NEC ! µ¡¤äGR¥·¥ê¡¼¥º¤è¤ê¿·¤·¤¤EPSONµ¡¤Ç¤Ï¥½¥Õ¥È¥¦¥¨¥¢DIP¥¹¥¤¥Ã¥Á¤ÇƱÅù ! ¤Îµ¡Ç½¤ò¼Â¸½¤·¤Þ¤¹¤Î¤Ç¡¢¤³¤Î¥ª¥×¥·¥ç¥ó¤Ï»ØÄꤷ¤Ê¤¤¤Ç¤¯¤À¤µ¤¤¡£ ! Option ``nomemaccess''¤ò»ØÄꤷ¤Æ¤¤¤ë¾ì¹ç¤Ë¤Ï°ÕÌ£¤ò»ý¤Á¤Þ¤»¤ó¡£ Option ``dac_8_bit'' ! Ramdac ``sc15025''¤ò»ØÄꤷ¤Æ¤¤¤ë¾ì¹ç¡¢É¬¤ºÉ¬ÍפǤ¹¡£Ramdac ! ``bt485''¤Î¾ì¹ç¤â»ØÄê²Äǽ¤Ç¤¹¡£ Option ``bt485_curs'' ! Ramdac ``bt485''¤Î¾ì¹ç¡¢»ØÄê²Äǽ¤Ç¤¹¡£Bt485¤Î¥Ï¡¼¥É¥¦¥¨¥¢¥«¡¼¥½ ! ¥ëµ¡Ç½¤ò»ÈÍѤ·¤Þ¤¹¡£ - - 3.8.2.Êó¹ð¤µ¤ì¤Æ¤¤¤ëÌäÂê - - o PW928 + memaccess ¤ÇÆ°ºî¤·¤Ê¤¤¾ì¹ç¤¬¤¢¤ê¤Þ¤¹¡£ËÜÂΤȤÎÁêÀ­¤Ë¤è¤ë¤è ¤¦¤Ç¤¹¡£ o mmio_928 + nomemaccess ¤òƱ»þ¤Ë»ØÄꤹ¤ë¤È¥Ï¥ó¥°¥¢¥Ã¥×¤·¤Þ¤¹¡£ ! o PW805i¤Ç¤Ï15/16/32bpp¤Ï»ÈÍѤǤ­¤Þ¤»¤ó¡£ ! o µìÈǤǤÏÆ°ºî¤·¤Æ¤¤¤¿¤â¤Î¤Î¡¢¸½ºß¡¢PW801¤Ç15/16Bpp¤¬Æ°ºî¤·¤Ê¤¤¤È¤¤¤¦ ! Êó¹ð¤¬¤¢¤ê¤Þ¤·¤¿¡£ ! o PCSKB3/PCSKB4/PCPKB4¤Ç¤Ïmemaccess¤Ï»ÈÍѤǤ­¤Þ¤»¤ó¡£ ! o PW805i¤Ç¤Ï½é´ü²½¤Ë¼ºÇÔ¤¹¤ë¤Ê¤É¡¢Æ°ºî¤¬ÉÔ°ÂÄê¤Ê¤è¤¦¤Ç¤¹¡£ o Option ``pcskb'',``pcskb4''»ØÄê»þ¤Ë¡¢-probeonly¤Çµ¯Æ°¤¹¤ë¤È¡¢¿®¹æÀÚ ÂØÍÑ¥ê¥ì¡¼¤¬Éüµ¢¤»¤º¡¢¥Ö¥é¥Ã¥¯¥¢¥¦¥È¤·¤Þ¤¹¡£-probeonly¤Ï¡¢»ÈÍѤ·¤Ê --- 61,438 ---- ¤ÇÀäÂФ˻ÈÍѤ·¤Ê¤¤¤Ç¤¯¤À¤µ¤¤¡£ XF86Setup ! PC98 ÍѤ˰ܿ¢¤µ¤ì¤Æ¤¤¤Þ¤¹¡£XF98Setup ¤ò»ÈÍѤ·¤Æ²¼¤µ¤¤¡£¥Ç¥Õ¥©¥ë ! ¥È¤Ç¤Ï¡¢XF98_NEC480 ¤ò»ÈÍѤ·¤Þ¤¹¤¬¡¢-egc ¥ª¥×¥·¥ç¥ó¤Ç XF98_EGC ! ¤â»ÈÍѤǤ­¤Þ¤¹¡£´Ä¶­ÊÑ¿ô LANG ¤Ë¡¢ja¡¢ja_JP¡¢ja_JP.*¡¢japan¡¢ ! japanese Åù¤ò»ØÄꤹ¤ë¤È¡¢ÆüËܸì¤Î²èÌ̤ˤʤê¤Þ¤¹¡£¤Ê¤ª¡¢ÆüËܸì²è ! ÌÌ¤Ï PC/AT ¸ß´¹µ¡¾å¤Î XF86Setup ¤Ç¤âÍøÍѤǤ­¤Þ¤¹¡£XF98Setup ¤Ç ! ¤Ï¡¢¥­¡¼¥Ü¡¼¥É¤ÎÁªÂò²èÌ̤ÏÉÔÍפʤΤǾÊά¤·¤Æ¤¤¤Þ¤¹¡£¥Þ¥¦¥¹¤Î¼ïÎà ! ¤Ï¡¢³Æ OS Ëè¤Ë¥µ¥Ý¡¼¥È¤µ¤ì¤ë¤â¤Î¤Î¤ßÁªÂò¤Ç¤­¤Þ¤¹¡£ scanpci ¸·³Ê¤ÊÆ°ºî³Îǧ¤ò¹Ô¤Ã¤Æ¤¤¤Þ¤»¤ó¤¬¡¢Æ°ºî¤¹¤ë¤è¤¦¤Ç¤¹¡£ ¥Ç¥Õ¥©¥ë¥È¤Î¥³¥ó¥Ñ¥¤¥ë»þ¤ÎÀßÄê ! °ÊÁ°¤Î PC98 ÍÑ¥µ¡¼¥Ð¤È°Û¤Ê¤ê¡¢XFree86 ¤Ï¡¢GetValuesBC ! NO,BuildPexExt YES,BuildXIE YES ¤ÈÄêµÁ¤µ¤ì¤Æ¤¤¤Þ¤¹¡£¤´Ãí°Õ¤¯¤À¤µ ! ¤¤¡£xengine Åù¤Ç¤Ï GetValues ¤Ë¤Ä¤¤¤Æ¥½¡¼¥¹¤Î½¤Àµ¤¬É¬ÍפǤ¹¡£ ! 16MB ¥·¥¹¥Æ¥à¶õ´Ö¤ÎÀßÄê ! ¥µ¡¼¥Ð¡¼¤Ë¤è¤Ã¤Æ¤Ï¡¢15M-16M ¤ÎÎΰè¤ò»ÈÍѤ¹¤ëʪ¤¬¤¢¤ê¤Þ¤¹¡£¥·¥¹¥Æ ! ¥à¥»¥Ã¥È¥¢¥Ã¥×¥á¥Ë¥å¡¼¤Ç¡¢16MB ¥·¥¹¥Æ¥à¶õ´Ö¤ò¡ÖÀÚ¤êÎ¥¤¹¡×¤Ë¤·¤Æ ! ¥µ¡¼¥Ð¡¼¤òµ¯Æ°¤¹¤ë¤È¡¢¥Ï¥ó¥°¥¢¥Ã¥×Åù¤ò°ú¤­µ¯¤³¤¹²ÄǽÀ­¤¬¤¢¤ë¤¿ ! ¤á¡¢¤«¤Ê¤é¤º¡Ö»ÈÍѤ¹¤ë¡×¤Ë¤·¤Æ¤¯¤À¤µ¤¤¡£ + 3. ³Æ¥µ¡¼¥Ð¤Ë¤Ä¤¤¤Æ 3.1. XF98_WABS + MELCO ¤Î WAB-S,1000/2000,WSR-E/G ¤ÇÆ°ºî¤¹¤ë VGA256 ¥Ù¡¼¥¹¤Î¥µ¡¼¥Ð¤Ç + ¤¹¡£ ! 3.1.1. XF86Config ¤ÎÀßÄê ! README.cirrus Æâ¤Ë²òÀ⤵¤ì¤Æ¤¤¤ë¥ª¥×¥·¥ç¥ó¤ò»ØÄê¤Ç¤­¤Þ¤¹¡£ ! 3.1.2. Êó¹ð¤µ¤ì¤Æ¤¤¤ëÌäÂê ! 3.1.3. ¤½¤Î¾ + o WAB-2000 ¤Ç VRAM 2M ¤Ç¤ÎÆ°ºî¤Ï̤Âбþ¤Ç¤¹¡£ ! o WAB-S/1000/2000 ¤Ë¤ª¤±¤ë IO port ¤Î SW ¤Ï default ¤Î 0 ¤Ç¤¹¡£ + o 15/16/24/32bpp ¤ÏÆ°ºî¤·¤Þ¤»¤ó¡£ ! 3.1.4. ´ØÏ¢ ! XF86_SVGA manpage,README.cirrus »²¾È¡£ 3.2. XF98_WABEP ! MELCO ¤Î WAB-EP (EPSON ¥í¡¼¥«¥ë¥Ð¥¹ÍÑ) ¤ÇÆ°ºî¤¹¤ë VGA256 ¥Ù¡¼¥¹¤Î¥µ¡¼ ! ¥Ð¤Ç¤¹¡£ + 3.2.1. XF86Config ¤ÎÀßÄê ! README.cirrus Æâ¤Ë²òÀ⤵¤ì¤Æ¤¤¤ë¥ª¥×¥·¥ç¥ó¤ò»ØÄê¤Ç¤­¤Þ¤¹¡£ ! 3.2.2. Êó¹ð¤µ¤ì¤Æ¤¤¤ëÌäÂê ! 3.2.3. ¤½¤Î¾ o ¤Þ¤À½½Ê¬¤Ê¥Æ¥¹¥È¤¬¹Ô¤ï¤ì¤Æ¤¤¤Ê¤¤¤Î¤ÇÆ°ºî¥ì¥Ý¡¼¥È¤ò¤ª´ê¤¤¤·¤Þ¤¹¡£ ! 3.2.4. ´ØÏ¢ ! XF86_SVGA manpage,README.cirrus »²¾È¡£ 3.3. XF98_GANBWAP ! MELCO ¤Î WAP2000/4000, IO Data ¤Î GA-98NB I/C,II,IV ¤ÇÆ°ºî¤¹¤ë VGA256 ! ¥Ù¡¼¥¹¤Î¥µ¡¼¥Ð¤Ç¤¹¡£ICM GI-5434-2M/4M ¤Ç¤âÆ°ºî¤·¤Þ¤¹¡£ + 3.3.1. XF86Config ¤ÎÀßÄê ! °Ê²¼¤Î Option ¤¬ PC98 ÍѤ˻ØÄê¤Ç¤­¤Þ¤¹¡£¤³¤ì°Ê³°¤Ë¡¢README.cirrus Æâ¤Ë ! ²òÀ⤵¤ì¤Æ¤¤¤ë¥ª¥×¥·¥ç¥ó¤ò»ØÄê¤Ç¤­¤Þ¤¹¡£ Option ``ga98nb1'' GA-98NB I/C »ÈÍÑ»þ¤Ëɬ¤º»ØÄꤷ¤Þ¤¹¡£ Option ``ga98nb2'' ! GA-98NB II ¤ä GI-5434-2M ¤ò»ÈÍÑ»þ¤Ëɬ¤º»ØÄꤷ¤Þ¤¹¡£ Option ``ga98nb4'' ! GA-98NB IV ¤ä GI-5434-4M ¤ò»ÈÍÑ»þ¤Ëɬ¤º»ØÄꤷ¤Þ¤¹¡£ ! Option ``wap'' ! WAP-2000/4000 »ÈÍÑ»þ¤Ëɬ¤º»ØÄꤷ¤Þ¤¹¡£ + Option ``no_mmio'' + PC98 ÍѤΠCLGD543x/544x ·Ï¤Ç¤Ïɬ¤º»ØÄꤷ¤Æ²¼¤µ¤¤¡£GANBWAP ¥µ¡¼¥Ð + ¤Î¾ì¹ç¤Ïɬ¿Ü¤È¤Ê¤ê¤Þ¤¹¡£ + Option ``epsonmemwin'' ! ESPON PC486GR ¥·¥ê¡¼¥º°ÊÁ°¤Îµ¡¼ï¤Ç¡¢0xf00000 ¤Ø VRAM ¤ò¥Þ¥Ã¥Ô¥ó ! ¥°²Äǽ¤Ë¤·¤Þ¤¹¡£FreeBSD(98) ¤Ç¤Ï¥«¡¼¥Í¥ë config »þ¤Ë»ØÄꤹ¤ë»ö ! ¤Ç¡¢¥«¡¼¥Í¥ë¦¤ÇƱÅù¤Îµ¡Ç½¤ò¼Â¸½¤·¤Æ¤¤¤Þ¤¹¡£Ä̾ï¤Ï¥«¡¼¥Í¥ë¦¤Ç»Ø ! Äꤷ¡¢XF86Config ¤Ç¤Ï¤³¤Î¥ª¥×¥·¥ç¥ó¤ò»ØÄꤷ¤Þ¤»¤ó¡£ ! NetBSD/pc98(based on NetBSD 1.2) ¤Ç¤Ï¡¢É¬¤º¤³¤Î¥ª¥×¥·¥ç¥ó¤ò»ØÄê ! ¤·¤Æ¤¯¤À¤µ¤¤¡£¤Þ¤¿¡¢NEC µ¡¤ä GR ¥·¥ê¡¼¥º¤è¤ê¿·¤·¤¤ EPSON µ¡¤Ç¤Ï ! ¥½¥Õ¥È¥¦¥¨¥¢ DIP ¥¹¥¤¥Ã¥Á¤ÇƱÅù¤Îµ¡Ç½¤ò¼Â¸½¤·¤Þ¤¹¤Î¤Ç¡¢¤³¤Î¥ª¥× ! ¥·¥ç¥ó¤Ï»ØÄꤷ¤Ê¤¤¤Ç¤¯¤À¤µ¤¤¡£ + 3.3.2. Êó¹ð¤µ¤ì¤Æ¤¤¤ëÌäÂê ! o MMIO ¤ò»ÈÍѤ¹¤ë¤ÈÉÁ²è¤Ë¼ºÇÔ¤¹¤ë»ö¤¬¤¢¤ê¤Þ¤¹¡£ + o 1280x1024 ¤Ç¤Ï¡¢ÉÁ²è»þ¤Ë¥Î¥¤¥º¤¬½Ð¤Þ¤¹¡£ ! 3.3.3. ¤½¤Î¾ ! o GA-98NB, WAP ¶¦¤Ë IO port ¤Î SW ¤Ï default ¤Î 0 ¤Ç¤¹¡£ ! o 15/16/24/32bpp ¤ÏÆ°ºî¤·¤Þ¤»¤ó¡£ + o ¥É¥Ã¥È¥¯¥í¥Ã¥¯ 85MHz °Ê¾å¤Ç¤Ï¡¢¥Ï¡¼¥É¥¦¥§¥¢¥«¡¼¥½¥ë¤Ï»ÈÍѤǤ­¤Þ¤» + ¤ó¡£Option ``sw_cursor'' ¤ò»ØÄꤷ¤Æ¤¯¤À¤µ¤¤¡£ o WGN-A2 ¤Ë¤Ä¤¤¤Æ¤Ï¡¢¿ô·ïÆ°ºî¤¹¤ë»Ý¤ÎÊó¹ð¤ò¼õ¤±¤Æ¤¤¤Þ¤¹¤¬¡¢Æ°ºî¤·¤Ê¤¤ ¤È¸À¤¦Êó¹ð¤â¤¢¤ê¤Þ¤·¤¿¡£¤è¤ê¾Ü¤·¤¤¾ðÊó¤ò¤ª´ê¤¤¤·¤Þ¤¹¡£ + 3.3.4. ´ØÏ¢ ! XF86_SVGA manpage,README.cirrus »²¾È¡£ 3.4. XF98_WSNA ! MELCO ¤Î WSN-A2F,A4F ¤ÇÆ°ºî¤¹¤ë VGA256 ¥Ù¡¼¥¹¤Î¥µ¡¼¥Ð¤Ç¤¹¡£ + 3.4.1. XF86Config ¤ÎÀßÄê ! °Ê²¼¤Î Option ¤¬ PC98 ÍѤ˻ØÄê¤Ç¤­¤Þ¤¹¡£¤³¤ì°Ê³°¤Ë¡¢README.cirrus Æâ¤Ë ! ²òÀ⤵¤ì¤Æ¤¤¤ë¥ª¥×¥·¥ç¥ó¤ò»ØÄê¤Ç¤­¤Þ¤¹¡£ ! Option ``no_mmio'' ! PC98 ÍѤΠCLGD543x/544x ·Ï¤Ç¤Ïɬ¤º»ØÄꤷ¤Æ²¼¤µ¤¤¡£WSNA ¥µ¡¼¥Ð¤Î ! ¾ì¹ç¤Ïɬ¿Ü¤È¤Ê¤ê¤Þ¤¹¡£ Option ``epsonmemwin'' ! ESPON PC486GR ¥·¥ê¡¼¥º°ÊÁ°¤Îµ¡¼ï¤Ç¡¢0xf00000 ¤Ø VRAM ¤ò¥Þ¥Ã¥Ô¥ó ! ¥°²Äǽ¤Ë¤·¤Þ¤¹¡£FreeBSD(98) ¤Ç¤Ï¥«¡¼¥Í¥ë config »þ¤Ë»ØÄꤹ¤ë»ö ! ¤Ç¡¢¥«¡¼¥Í¥ë¦¤ÇƱÅù¤Îµ¡Ç½¤ò¼Â¸½¤·¤Æ¤¤¤Þ¤¹¡£Ä̾ï¤Ï¥«¡¼¥Í¥ë¦¤Ç»Ø ! Äꤷ¡¢XF86Config ¤Ç¤Ï¤³¤Î¥ª¥×¥·¥ç¥ó¤ò»ØÄꤷ¤Þ¤»¤ó¡£ ! NetBSD/pc98(based on NetBSD 1.2) ¤Ç¤Ï¡¢É¬¤º¤³¤Î¥ª¥×¥·¥ç¥ó¤ò»ØÄê ! ¤·¤Æ¤¯¤À¤µ¤¤¡£¤Þ¤¿¡¢NEC µ¡¤ä GR ¥·¥ê¡¼¥º¤è¤ê¿·¤·¤¤ EPSON µ¡¤Ç¤Ï ! ¥½¥Õ¥È¥¦¥¨¥¢ DIP ¥¹¥¤¥Ã¥Á¤ÇƱÅù¤Îµ¡Ç½¤ò¼Â¸½¤·¤Þ¤¹¤Î¤Ç¡¢¤³¤Î¥ª¥× ! ¥·¥ç¥ó¤Ï»ØÄꤷ¤Ê¤¤¤Ç¤¯¤À¤µ¤¤¡£ + 3.4.2. Êó¹ð¤µ¤ì¤Æ¤¤¤ëÌäÂê o ³«È¯¸å½½Ê¬¤Ê¥Æ¥¹¥È¤¬¹Ô¤ï¤ì¤Æ¤¤¤Ê¤¤¤Î¤ÇÆ°ºî¥ì¥Ý¡¼¥È¤ò¤ª´ê¤¤¤·¤Þ¤¹¡£ + 3.4.3. ¤½¤Î¾ + o GA-98NB, WAP ¶¦¤Ë IO port ¤Î SW ¤Ï default ¤Î 0 ¤Ç¤¹¡£ + o 15/16/24/32bpp ¤ÏÆ°ºî¤·¤Þ¤»¤ó¡£ ! o ¥É¥Ã¥È¥¯¥í¥Ã¥¯ 85MHz °Ê¾å¤Ç¤Ï¡¢¥Ï¡¼¥É¥¦¥§¥¢¥«¡¼¥½¥ë¤Ï»ÈÍѤǤ­¤Þ¤» ! ¤ó¡£Option ``sw_cursor'' ¤ò»ØÄꤷ¤Æ¤¯¤À¤µ¤¤¡£ + 3.4.4. ´ØÏ¢ ! XF86_SVGA manpage,README.cirrus »²¾È¡£ 3.5. XF98_NKVNEC ! NEC,EPSON ¤ÎÆ⢥¢¥¯¥»¥é¥ì¡¼¥¿ (Cirrus Logic CL-GD5428,5429,5430,5434) ! ¤ÇÆ°ºî¤¹¤ë VGA256 ¥Ù¡¼¥¹¤Î¥µ¡¼¥Ð¤Ç¤¹¡£ + 3.5.1. XF86Config ¤ÎÀßÄê ! °Ê²¼¤Î Option ¤¬ PC98 ÍѤ˻ØÄê¤Ç¤­¤Þ¤¹¡£¤³¤ì°Ê³°¤Ë¡¢README.cirrus Æâ¤Ë ! ²òÀ⤵¤ì¤Æ¤¤¤ë¥ª¥×¥·¥ç¥ó¤ò»ØÄê¤Ç¤­¤Þ¤¹¡£ Option ``nec_cirrus'' ! NEC µ¡Æ⢠crrus ¥Á¥Ã¥×»ÈÍѤΥӥǥª¥·¥¹¥Æ¥à»ÈÍÑ»þ¤Ëɬ¤º»ØÄꤷ¤Þ ! ¤¹¡£ + Option ``no_mmio'' + CLGD543x/544x »ÈÍѤΥӥǥª¥·¥¹¥Æ¥à»ÈÍÑ»þ¤Ëɬ¤º»ØÄꤷ¤Þ¤¹¡£¼ÂºÝ¤Ë + ¤Ï¡¢Xe/BX4/Xe10/Xa7e/Xb/Xc/Cf °Ê¹ß¤Î Canbe/ValueStar ¤Î + CirrusLogic ºÎÍѵ¡¼ïÅù¤¬³ºÅö¤¹¤ë¤È»×¤ï¤ì¤Þ¤¹¡£ ! 3.5.2. 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PseudoColor ¤Î visual ¤ò¥µ¥Ý¡¼¥È¤·¤¿¤¿¤á¡¢XF86Config ¤Î Screen ¥»¥¯ ! ¥·¥ç¥ó¤Ë¡¢Visual ``PseudoColor'' ¤Îµ­½Ò¤ò¤·¤Ê¤¤¤È¡¢µìÈǤÈƱ¤¸¿§ ! ¤Ë¤Ê¤ê¤Þ¤»¤ó¡£ËÜÇÛÉÛʪ¤Ë´Þ¤Þ¤ì¤ë XF86Config.98 ¤Ë¤Ï¤¢¤é¤«¤¸¤áµ­½Ò¤µ ! ¤ì¤Æ¤¤¤Þ¤¹¡£ ! 3.6.2. Êó¹ð¤µ¤ì¤Æ¤¤¤ëÌäÂê o XF86Config ¤Ç¤Î Section "Monitor" ¤Î¿ô»ú¤ÏÍѤ¤¤Æ¤¤¤Ê¤¤¤Ë¤â¤«¤«¤ï¤é ¤ºÃͤò¥Á¥§¥Ã¥¯¤·¤Þ¤¹¡£ ! o EPSON NOTE ¤Ç¤Ï¡¢twm ¤Ê¤É¤Î¥×¥ë¥À¥¦¥ó¥á¥Ë¥å¡¼¤Ç¥«¡¼¥½¥ë°ÌÃ֤˥´¥ß¤¬ ! À¸¤¸¤Þ¤¹¡£xrefresh ¤Ê¤É¤Ç½üµî¤Ç¤­¤Þ¤¹¤¬¡¢²ò·èÊýË¡¤ÏÉÔÌÀ¤Ç¤¹¡£ ! o PANIX Ver.5.0 for 98¡¢Linux/98 ¤Ç¤ÏÆ°ºî¤·¤Þ¤»¤ó¡£ ! 3.6.3. ¤½¤Î¾ + o ²¾ÁÛ¥¹¥¯¥ê¡¼¥ó¤Îµ¡Ç½¤Ï¤¢¤ê¤Þ¤»¤ó¡£640x400 ¸ÇÄê¤Ç¤¹¡£Virtual ¤ÎÀßÄê + ¤Ï¹Ô¤ï¤Ê¤¤¤Ç¤¯¤À¤µ¤¤¡£ ! 3.6.4. ´ØÏ¢ + XF86_VGA16 manpage,README.Config »²¾È¡£ 3.7. XF98_NEC480 ! PEGC ¤òÍѤ¤¤¿¡¢640x400, 640x480 ¥É¥Ã¥È 256 ¿§¤Î¥µ¡¼¥Ð¤Ç¤¹¡£PC-9821 ¥· ! ¥ê¡¼¥º¤Î³ÈÄ¥¥°¥é¥Õ¥£¥Ã¥¯¥¢¡¼¥­¥Æ¥¯¥Á¥ãÅëºÜµ¡¤ÇÆ°ºî¤·¤Þ¤¹¡£ ! 3.7.1. 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XF86Config ¤ÎÀßÄê + °Ê²¼¤Î Option Åù¤¬ PC98 ÍѤ˻ØÄê¤Ç¤­¤Þ¤¹¡£¤³¤ì°Ê³°¤Ë¡¢README.s3¡¢ + XF86_Accel man page ¤Ç²òÀ⤵¤ì¤Æ¤¤¤ë¥ª¥×¥·¥ç¥óÅù¤ò»ØÄê¤Ç¤­¤Þ¤¹¡£PC98 + ¸ÇÍ­°Ê³°¤Î Option Åù¤Ë¤Ä¤¤¤Æ¤Ï XF86_Accel man page ¤ò»²¾È¤·¤Æ¤¯¤À¤µ¤¤ + Chipset ``mmio_928'' ! chip ¤¬ 928 ¤Î¾ì¹ç¤Î¤ß»ÈÍѤǤ­¤Þ¤¹¡£Æ°ºî¤¬¹â®¤Ë¤Ê¤ê¤Þ¤¹¤¬¡¢ÉÔ°Â ! Äê¤Ê¾ì¹ç¤Ê¤É¤Ï¡¢``s3_generic'' ¤ò»ØÄꤷ¤Æ¤¯¤À¤µ¤¤¡£ Chipset ``s3_generic'' ! ``s3_mmio'' ¤ò»ØÄꤷ¤Ê¤¤¾ì¹ç¤Ë»ÈÍѤ·¤Þ¤¹¡£¤¹¤Ê¤ï¤Á¡¢Ä̾ï¤ÎÀßÄê¤Ç ¤Ïɬ¤º»ØÄꤷ¤Þ¤¹¡£ Ramdac ``sc15025'' PowerWindow801/801+/928/928G/801G¡¢PCSKB/PCSKB2/PCSKB4(1M RAM)/ ! PCPKB4(1M RAM) ¤Ç¤Ïɬ¤ºÉ¬ÍפǤ¹¡£ Ramdac ``bt485'' ! PowerWindow928II,PCSKB4(2,4M RAM),PCPKB4(2,4M RAM) ¤Ç¤Ïɬ¤ºÉ¬Í× ! ¤Ç¤¹¡£``att20c505'' ¤Ç¤âƱÅù¤ÎÆ°ºî¤ò¤·¤Þ¤¹¡£ Ramdac ``s3_gendac'' ! PowerWindow805i ¤Ç¤Ï¡¢É¬¤ºÉ¬ÍפǤ¹¡£ Clockchip ``icd2061a'' ! PowerWindow801/801+/928/928G/801G/928II ¤Çɬ¤º»ØÄꤷ¤Þ¤¹¡£ Clockchip ``s3_gendac'' ! PW805i ¤Ç¤Ï¡¢É¬¤ºÉ¬ÍפǤ¹¡£ VideoRam 1024 ! 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Êó¹ð¤µ¤ì¤Æ¤¤¤ëÌäÂê + o PC9821Xn(864) ¤Ç¤Ï¡¢Æ°ºî¤¬ÉÔ°ÂÄê¤Ç¤¹¡£WAIT ¤¬Â­¤ê¤Ê¤¤¤³¤È¤¬¹Í¤¨¤é¤ì + ¤Þ¤¹¡£ + o X-MATE,A-MATE(864) ¤Ç¤Ï¡¢16bpp,32bpp ¤¬ÉÔ°ÂÄê¤Ê¤è¤¦¤Ç¤¹¡£Æäˡ¢ + 32bpp ¤Ï¥Ï¥ó¥°¥¢¥Ã¥×¤¹¤ë¤³¤È¤¬Â¿¤¤¤è¤¦¤Ç¤¹¡£ ! o X-MATE,A-MATE(864) ¤Ç¡¢¥µ¡¼¥Ðµ¯Æ°»þ¤Ë²èÌ̤¬Íð¤ì¤ë¾ì¹ç¤¬¤¢¤ê¤Þ¤¹¡£¤½ ! ¤Î¾ì¹ç¡¢²òÁüÅÙ¤òÀÚÂؤ¨¤ë¤È²óÉü¤·¤Þ¤¹¡£(CTRL+GRPH+ +/-) + o ¥¦¥£¥ó¥É¥¦¥¢¥¯¥»¥é¥ì¡¼¥¿¥Ü¡¼¥É A,B ¤Ç 65MHz ¤Î Dot Clock ¤¬»ÈÍѤǤ­ + ¤Ê¤¤¤³¤È¤¬¤¢¤ê¤Þ¤¹¡£¤³¤Î»þ¤Ï¡¢XF86Config.98 ¤Î 1024x768H ¤Î Monitor + Section ¤ò»ÈÍѤ·¤Æ¤¯¤À¤µ¤¤¡£ ! 3.10.3. ¤½¤Î¾ ! o 16M Byte °Ê¾å RAM ¤ò¼ÂÁõ¤·¤Æ¤¤¤ë¾ì¹ç¡¢µ¡¼ï¤Ë¤è¤ê¥«¡¼¥Í¥ë¦¤ÎÀßÄ꤬ ! ɬÍפǤ¹¡£ ! o IO port ¤Ï default ¤Î DIP ¥¹¥¤¥Ã¥Á¤È¤·¤Þ¤¹¡£ ! 3.10.4. ´ØÏ¢ ! README.s3¡¢XF86_Accel man page + 3.11. XF98_GA968 ! GA-968V2/PCI, GA-968V4/PCI ¤ÇÆ°ºî¤¹¤ë¥µ¡¼¥Ð¤Ç¤¹¡£ ! 3.11.1. XF86Config ¤ÎÀßÄê ! °Ê²¼¤Î Option Åù¤¬ PC98 ÍѤ˻ØÄê¤Ç¤­¤Þ¤¹¡£¤³¤ì°Ê³°¤Ë¡¢README.S3¡¢ ! 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XFree86 3.2 ¤ò»ÈÍѤ¹¤ë¾ì¹ç¡¢¥¢¥¯¥»¥é¥ì¡¼¥·¥ç¥ó¤ÏÍøÍѤǤ­¤Þ¤»¤ó¡£ + o ¤Þ¤À½½Ê¬¤Ê¥Æ¥¹¥È¤¬¹Ô¤ï¤ì¤Æ¤¤¤Ê¤¤¤Î¤ÇÆ°ºî¥ì¥Ý¡¼¥È¤ò¤ª´ê¤¤¤·¤Þ¤¹¡£ ! 3.12.3. ¤½¤Î¾ ! o GA-DRV/98 ¤Ç¤Ï 8bpp °Ê³°¤ÏÆ°ºî¤·¤Þ¤»¤ó¡£ + 3.12.4. ´ØÏ¢ ! README.trident¡¢XF86_SVGA man page ! 3.13. XF98_MGA ! NEC ¤ÎÆ⢥¢¥¯¥»¥é¥ì¡¼¥¿ (Matrox Millennium/Mystique), PC/AT ¸ß´¹µ¡ÍÑ ! Millennium ¤ÇÆ°ºî¤¹¤ë VGA256 ¥Ù¡¼¥¹¤Î¥µ¡¼¥Ð¤Ç¤¹¡£ ! 3.13.1. XF86Config ¤ÎÀßÄê ! README.MGA Æâ¤Ë²òÀ⤵¤ì¤Æ¤¤¤ë¥ª¥×¥·¥ç¥ó¤ò»ØÄê¤Ç¤­¤Þ¤¹¡£Ä̾ï¤ÏÆä˲¿¤â ! »ØÄꤹ¤ëɬÍ×̵¤¤È¦¤Ç¤¹¡£ ! 3.13.2. Êó¹ð¤µ¤ì¤Æ¤¤¤ëÌäÂê + o Millennium ¤Ç¤Ï¡¢Modeline ¤ÎÀßÄê¤Ë¤è¤Ã¤Æ¤Ï 24bpp ¤Ç½Ä¤ËÀþ¤¢¤ë¤¤¤Ï¼Ê + ÌÏÍͤΥΥ¤¥º¤¬½Ð¤ë¤³¤È¤¬¤¢¤ê¤Þ¤¹¡£ ! o Mystique ¤Ç¤Ï¡¢»ÈÍÑÁ°¤Ë Windows(3.1/95/NT) ¤ò»ÈÍѤ¹¤ë¿§¿ô¤Ë¹ç¤ï¤»¤Æ ! µ¯Æ°¤·¤Æ¤ª¤¯É¬Íפ¬¤¢¤ê¤Þ¤¹¡£°ìöµ¯Æ°¤¹¤ì¤ÐÅŸ»¤ò OFF ¤Ë¤¹¤ë¤Þ¤Ç¤ÏÀµ ! ¾ï¤ËÆ°ºî¤·¤Þ¤¹¡£¤¿¤À¤· 8bpp ¤Ï¿§¤¬¤ª¤«¤·¤¯¤Ê¤ê¤Þ¤¹¡£ + 3.13.3. ¤½¤Î¾ ! o PC/AT ¸ß´¹µ¡ÍѤΠMillennium ¤ò»ÈÍѤ¹¤ë¾ì¹ç¤Ï¡¢VGA ¤ò disable ¤·¤Æ²¼ ! ¤µ¤¤¡£ + o PC/AT ¸ß´¹µ¡ÍѤΠMillennium II, Mystique ¤Ï¡¢VGA ¤ò disable ¤Ç¤­¤Ê + ¤¤¤Î¤Ç¡¢»ÈÍѤǤ­¤Þ¤»¤ó¡£ ! o ¤Þ¤À½½Ê¬¤Ê¥Æ¥¹¥È¤¬¹Ô¤ï¤ì¤Æ¤¤¤Ê¤¤¤Î¤ÇÆ°ºî¥ì¥Ý¡¼¥È¤ò¤ª´ê¤¤¤·¤Þ¤¹¡£ ! 3.13.4. ´ØÏ¢ + README.MGA¡¢XF86_SVGA man page + + 3.14. XF98_SVGA + + NEC ¤ÎÆ⢥¢¥¯¥»¥é¥ì¡¼¥¿ (Cirrus Logic CL-GD7555,7556) ¤ÇÆ°ºî¤¹¤ë + VGA256 ¥Ù¡¼¥¹¤Î¥µ¡¼¥Ð¤Ç¤¹¡£ + + 3.14.1. XF86Config ¤ÎÀßÄê + + README.cirrus Æâ¤Ë²òÀ⤵¤ì¤Æ¤¤¤ë¥ª¥×¥·¥ç¥ó¤ò»ØÄê¤Ç¤­¤Þ¤¹¡£ + + 3.14.2. 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<ITEM>¿ÀÊÝ Æ»É×<it/<karl@spnet.ne.jp>/ ! <ITEM>ÎëÌÚ ¹§°ìϺ<it/<s-koichi@nims.nec.co.jp>/ ! <ITEM>ÎëÌÚ Ãθ«<it/<suzuki@grelot.elec.ryukoku.ac.jp>/ <ITEM>ÎëÌÚ ¹¯»Ê<it/<suz@d2.bs1.fc.nec.co.jp>/ + <ITEM>Âì¾å ÉÙÀ²<it/<takigami@elsd.mt.nec.co.jp>/ <ITEM>ÄÍÅÄ ¹äʸ<it/<tsuka@linkt.imasy.or.jp>/ <ITEM>±ÊÈø Ä÷·¼<it/<nagao@cs.titech.ac.jp>/ <ITEM>ÌîÅÄ Ì­<it/<mnoda@cv.tottori-u.ac.jp>/ ! <ITEM>Ìî¼ ¹âÌÀ<it/<amadeus@yk.rim.or.jp>/ <ITEM>Æ£±º Ë­ÆÁ<it/<toyo@ibbsal.or.jp>/ <ITEM>ËÜ¿ ¾°Ê¸<it/<honda@Kururu.math.hokudai.ac.jp>/ + <ITEM>¿¹ÅÄ ¾¼É×<it/<amorita@bird.scphys.kyoto-u.ac.jp>/ <ITEM>Ȭ¿§ ¿­°ì<it/<QZR00522@niftyserve.or.jp>/ + <ITEM>ȬÌÚ ½Óɧ<it/<j2297222@ed.kagu.sut.ac.jp>/ <ITEM>°ÂÅÄ À»<it/<yasuda@cc.hit-u.ac.jp>/ </itemize> <p>¤½¤Î¾¤Î¶¨ÎÏ¼Ô <itemize> ! <ITEM>»³ËÜ ¹À(x98MLµì´ÉÍý¼Ô) ! <ITEM>ÃæÅç µá(x98ML´ÉÍý¼Ô) <ITEM>µÈÅÄ Àµ¿Í(PowerWindow805iÂбþ¥³¡¼¥ÉÄó¶¡) <ITEM>»°±º ÆØ»Ê(PW928IIÂßÍ¿) ! <ITEM>PC-VAN(JUNIX, JSPUNIX), NIFTY-SERVE(FUNIX, FEPSONX, SAISAP), ! fj, x98 ML, FreeBSD-users-jp ML, FreeBSD kit ML¤ÇÆ°ºîÊó¹ð ¤ò¤¯¤À¤µ¤Ã¤¿Êý¡¹ + <ITEM>µþÂç¥Þ¥¤¥³¥ó¥¯¥é¥Ö <ITEM>FreeBSD PC98°Ü¿¢¥Á¡¼¥à <ITEM>NetBSD/pc98 Core Team <ITEM>¥¨¡¼¡¦¥¢¥¤¡¦¥½¥Õ¥È³ô¼°²ñ¼Ò *** ./programs/Xserver/hw/xfree98/doc/Japanese/sgml/read98.sgml@@/PUBLIC-LATEST Sun Jul 20 13:51:21 1997 --- xc/programs/Xserver/hw/xfree98/doc/Japanese/sgml/read98.sgml Fri Mar 6 14:12:45 1998 *************** *** 5,11 **** <!-- Title information --> <title> XFree86 PC98 Dependent Information <author> The XFree86 Project Inc. and X98 CORE TEAM ! <date> 1997ǯ 1·î 23Æü <abstract> ¤³¤Î¥É¥­¥å¥á¥ó¥È¤Ç¤Ï¡¢PC98¥µ¡¼¥Ð¸ÇÍ­¤Î»ö¹à¤Ë¤Ä¤¤¤Æ²òÀ⤷¤Þ¤¹¡£ PC-AT¤È¶¦Ä̤λö¹à¤Ë¤Ä¤¤¤Æ¤Ï¡¢¶¦Ä̤Υɥ­¥å¥á¥ó¥È¤ò»²¾È¤·¤Æ¤¯¤À¤µ¤¤¡£¤³¤Î --- 5,11 ---- <!-- Title information --> <title> XFree86 PC98 Dependent Information <author> The XFree86 Project Inc. and X98 CORE TEAM ! <date> 1998ǯ 2·î 27Æü <abstract> ¤³¤Î¥É¥­¥å¥á¥ó¥È¤Ç¤Ï¡¢PC98¥µ¡¼¥Ð¸ÇÍ­¤Î»ö¹à¤Ë¤Ä¤¤¤Æ²òÀ⤷¤Þ¤¹¡£ PC-AT¤È¶¦Ä̤λö¹à¤Ë¤Ä¤¤¤Æ¤Ï¡¢¶¦Ä̤Υɥ­¥å¥á¥ó¥È¤ò»²¾È¤·¤Æ¤¯¤À¤µ¤¤¡£¤³¤Î *************** *** 12,18 **** ¥É¥­¥å¥á¥ó¥È¤Ç¤â¡¢³Æ¥µ¡¼¥Ð¤´¤È¤Ë»²¾È¤¹¤Ù¤­¥É¥­¥å¥á¥ó¥È¤ò¼¨¤·¤Æ¤¤¤Þ¤¹¤Î ¤Ç»²¹Í¤Ë¤·¤Æ¤¯¤À¤µ¤¤¡£ </abstract> ! <toc> <sect>¥µ¥Ý¡¼¥È¥µ¡¼¥ÐµÚ¤Ó¹½À®<p> PC98ÍÑ¥µ¡¼¥Ð¤Ï¡¢°Ê²¼¤Î³ÈÄ¥¥Ó¥Ç¥ª¥Ü¡¼¥É¡¢Æ⢥ӥǥª¥·¥¹¥Æ¥à¤ËÂбþ¤·¤Æ¤¤ ¤Þ¤¹¡£¸Ä¡¹¤ÎÂбþ¡¢Æ°ºî¾õ¶·¤Ë¤Ä¤¤¤Æ¤ÏVideoBoard98¤ò»²¾È¤·¤Æ¤¯¤À¤µ¤¤¡£ --- 12,18 ---- ¥É¥­¥å¥á¥ó¥È¤Ç¤â¡¢³Æ¥µ¡¼¥Ð¤´¤È¤Ë»²¾È¤¹¤Ù¤­¥É¥­¥å¥á¥ó¥È¤ò¼¨¤·¤Æ¤¤¤Þ¤¹¤Î ¤Ç»²¹Í¤Ë¤·¤Æ¤¯¤À¤µ¤¤¡£ </abstract> ! <sect>¥µ¥Ý¡¼¥È¥µ¡¼¥ÐµÚ¤Ó¹½À®<p> PC98ÍÑ¥µ¡¼¥Ð¤Ï¡¢°Ê²¼¤Î³ÈÄ¥¥Ó¥Ç¥ª¥Ü¡¼¥É¡¢Æ⢥ӥǥª¥·¥¹¥Æ¥à¤ËÂбþ¤·¤Æ¤¤ ¤Þ¤¹¡£¸Ä¡¹¤ÎÂбþ¡¢Æ°ºî¾õ¶·¤Ë¤Ä¤¤¤Æ¤ÏVideoBoard98¤ò»²¾È¤·¤Æ¤¯¤À¤µ¤¤¡£ *************** *** 19,57 **** </p> <sect1>¥µ¥Ý¡¼¥È¥«¡¼¥É°ìÍ÷ <p> <verb> ! ¥Ù¥ó¥À¡¼ ¥«¡¼¥É̾¾Î ¥µ¡¼¥Ð ! ------------- --------------------------------------- ---------------- ! MELCO WAB-S, WAB-1000, WAB-2000, WSR-E, WSR-G XF98_WABS ! MELCO WAP-2000, WAP-4000 XF98_GANBWAP ! MELCO WAB-EP XF98_WABEP ! MELCO WSN-A2F XF98_WSNA ! IO Data GA-98NB I/C,GA-98NB II, GA-98NB IV XF98_GANBWAP ! GA-968V2/PCI, GA-968V4/PCI XF98_GA968 ! GA-DRV2/98, GA-DRV4/98 XF98_TGUI ! NEC ¥¦¥£¥ó¥É¥¦¥¢¥¯¥»¥é¥ì¡¼¥¿¥Ü¡¼¥É A/B XF98_NECS3 ! Canopus PowerWindow 801, 801+, 928, 928G, 801G, XF98_PWSKB ! 928II, 805i ! Canopus PowerWindow 928IILB, 928GLB, 964LB XF98_PWLB ! EPSON PCSKB, PCSKB2, PCSKB3,PCSKB4,PCPKB4 XF98_PWSKB </verb></p></sect1> <sect1>¥µ¥Ý¡¼¥ÈÆ⢥ӥǥª¥·¥¹¥Æ¥à°ìÍ÷<p> <verb> ! ¥Ù¥ó¥À¡¼ ¥Á¥Ã¥×¥»¥Ã¥È ¥µ¡¼¥Ð ! ------------- --------------------------------------- ---------------- ! NEC/EPSON EGC(640x400x16) XF98_EGC ! NEC PEGC(640x400x256,640x480x256) XF98_NEC480 ! NEC S3 928(As2Åù), S3 864(As3Åù) XF98_NECS3 ! NEC Cirrus CLGD5428/5430(B-Mate,Xe,CanBeÅù) XF98_NKVNEC ! NEC Trident TGUI9680XGi(X-Mate,ValueStarÅù) XF98_TGUI ! EPSON NKV(486MR,MS,MV,586MVÅù) XF98_NKVNEC </verb></p> <sect>¶¦ÄÌ»ö¹à<p> <descrip> <tag>xf86config</tag> ! PC98ÍѤ˰ܿ¢¤µ¤ì¤Æ¤¤¤Þ¤»¤ó¡£/usr/X11R6/lib/X11/XF86Config.98¤ò ! XF86Config¤È¥ê¥Í¡¼¥à¤·¤Æ»ÈÍѤ·¤Æ¤¯¤À¤µ¤¤¡£ <tag>xvidtune</tag> ¸·³Ê¤ÊÆ°ºî³Îǧ¤ò¹Ô¤Ã¤Æ¤¤¤Þ¤»¤ó¤¬¡¢Æ°ºî¤¹¤ë¤è¤¦¤Ç¤¹¡£ <tag>SuperProbe</tag> --- 19,63 ---- </p> <sect1>¥µ¥Ý¡¼¥È¥«¡¼¥É°ìÍ÷ <p> <verb> ! ¥Ù¥ó¥À¡¼ ¥«¡¼¥É̾¾Î ¥µ¡¼¥Ð ! ------------- ----------------------------------------------- ------------- ! MELCO WAB-S, WAB-1000, WAB-2000, WSR-E, WSR-G XF98_WABS ! MELCO WAP-2000, WAP-4000 XF98_GANBWAP ! MELCO WAB-EP XF98_WABEP ! MELCO WSN-A2F XF98_WSNA ! IO Data GA-98NB I/C,GA-98NB II, GA-98NB IV XF98_GANBWAP ! GA-968V2/PCI, GA-968V4/PCI XF98_GA968 ! GA-DRV2/98, GA-DRV4/98 XF98_TGUI ! ICM GI-5434-2M, GI-5434-4M XF98_GANBWAP ! NEC ¥¦¥£¥ó¥É¥¦¥¢¥¯¥»¥é¥ì¡¼¥¿¥Ü¡¼¥É A/B XF98_NECS3 ! NEC ¥Õ¥ë¥«¥é¡¼¥¦¥£¥ó¥É¥¦¥¢¥¯¥»¥é¥ì¡¼¥¿¥Ü¡¼¥É A/B XF98_NECS3 ! NEC ¥Õ¥ë¥«¥é¡¼¥¦¥£¥ó¥É¥¦¥¢¥¯¥»¥é¥ì¡¼¥¿¥Ü¡¼¥É X2 XF98_MGA ! Canopus PowerWindow 801, 801+, 928, 928G, 801G, XF98_PWSKB ! 928II, 805i ! Canopus PowerWindow 928IILB, 928GLB, 964LB XF98_PWLB ! EPSON PCSKB, PCSKB2, PCSKB3, PCSKB4, PCPKB4 XF98_PWSKB ! Matrox MGA Millennium(PC/AT ¸ß´¹µ¡ÍÑ) XF98_MGA </verb></p></sect1> <sect1>¥µ¥Ý¡¼¥ÈÆ⢥ӥǥª¥·¥¹¥Æ¥à°ìÍ÷<p> <verb> ! ¥Ù¥ó¥À¡¼ ¥Á¥Ã¥×¥»¥Ã¥È ¥µ¡¼¥Ð ! ------------- ----------------------------------------------- ------------- ! NEC/EPSON EGC(640x400, 4bpp) XF98_EGC ! NEC PEGC(640x400/640x480, 8bpp) XF98_NEC480 ! NEC S3 928(As2Åù), S3 864(As3Åù) XF98_NECS3 ! NEC Cirrus CLGD5428/543x/544x(B-Mate,Xe,CanBe Åù) XF98_NKVNEC ! NEC Trident TGUI968xXGi(X-Mate,ValueStarÅù) XF98_TGUI ! NEC MGA Millennium/Mystique XF98_MGA ! NEC Cirrus CLGD755x(Aile) XF98_SVGA ! EPSON NKV(486MR,MS,MV,586MVÅù) XF98_NKVNEC </verb></p> <sect>¶¦ÄÌ»ö¹à<p> <descrip> <tag>xf86config</tag> ! PC98ÍѤ˰ܿ¢¤µ¤ì¤Æ¤¤¤Þ¤»¤ó¡£XF98Setup ¤ò»È¤¦¤«¡¢/usr/X11R6/lib/ ! X11/XF86Config.98¤òXF86Config¤È¥ê¥Í¡¼¥à¤·¤Æ»ÈÍѤ·¤Æ¤¯¤À¤µ¤¤¡£ <tag>xvidtune</tag> ¸·³Ê¤ÊÆ°ºî³Îǧ¤ò¹Ô¤Ã¤Æ¤¤¤Þ¤»¤ó¤¬¡¢Æ°ºî¤¹¤ë¤è¤¦¤Ç¤¹¡£ <tag>SuperProbe</tag> *************** *** 58,68 **** °Ü¿¢¤µ¤ì¤Æ¤¤¤Þ¤»¤ó¡£¥Ï¥ó¥°¥¢¥Ã¥×¤ä¥Ó¥Ç¥ª¥Ü¡¼¥É¤ò²õ¤¹¶²¤ì¤¬¤¢¤ë ¤Î¤ÇÀäÂФ˻ÈÍѤ·¤Ê¤¤¤Ç¤¯¤À¤µ¤¤¡£ <tag>XF86Setup</tag> ! PC98ÍѤ˰ܿ¢¤µ¤ì¤Æ¤¤¤Þ¤»¤ó¡£ <tag>scanpci</tag> ¸·³Ê¤ÊÆ°ºî³Îǧ¤ò¹Ô¤Ã¤Æ¤¤¤Þ¤»¤ó¤¬¡¢Æ°ºî¤¹¤ë¤è¤¦¤Ç¤¹¡£ <tag>¥Ç¥Õ¥©¥ë¥È¤Î¥³¥ó¥Ñ¥¤¥ë»þ¤ÎÀßÄê</tag> ! °ÊÁ°¤ÎPC98ÍÑ¥µ¡¼¥Ð¤È°Û¤Ê¤ê¡¢XFree86¤Ï¡¢GetValesBC NO,BuildPexExt YES,BuildXIE YES¤ÈÄêµÁ¤µ¤ì¤Æ¤¤¤Þ¤¹¡£¤´Ãí°Õ¤¯¤À¤µ¤¤¡£xengineÅù¤Ç ¤ÏGetValues¤Ë¤Ä¤¤¤Æ¥½¡¼¥¹¤Î½¤Àµ¤¬É¬ÍפǤ¹¡£ <tag>16MB¥·¥¹¥Æ¥à¶õ´Ö¤ÎÀßÄê</tag> --- 64,80 ---- °Ü¿¢¤µ¤ì¤Æ¤¤¤Þ¤»¤ó¡£¥Ï¥ó¥°¥¢¥Ã¥×¤ä¥Ó¥Ç¥ª¥Ü¡¼¥É¤ò²õ¤¹¶²¤ì¤¬¤¢¤ë ¤Î¤ÇÀäÂФ˻ÈÍѤ·¤Ê¤¤¤Ç¤¯¤À¤µ¤¤¡£ <tag>XF86Setup</tag> ! PC98ÍѤ˰ܿ¢¤µ¤ì¤Æ¤¤¤Þ¤¹¡£XF98Setup ¤ò»ÈÍѤ·¤Æ²¼¤µ¤¤¡£¥Ç¥Õ¥©¥ë¥È ! ¤Ç¤Ï¡¢XF98_NEC480 ¤ò»ÈÍѤ·¤Þ¤¹¤¬¡¢-egc ¥ª¥×¥·¥ç¥ó¤Ç XF98_EGC ¤â ! »ÈÍѤǤ­¤Þ¤¹¡£´Ä¶­ÊÑ¿ô LANG ¤Ë¡¢ja¡¢ja_JP¡¢ja_JP.*¡¢japan¡¢japanese ! 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GA-98NB II »ÈÍÑ»þ¤Ëɬ¤º»ØÄꤷ¤Þ¤¹¡£ <tag>Option ``ga98nb4''</tag> ! GA-98NB IV »ÈÍÑ»þ¤Ëɬ¤º»ØÄꤷ¤Þ¤¹¡£ <tag>Option ``wap''</tag> WAP-2000/4000»ÈÍÑ»þ¤Ëɬ¤º»ØÄꤷ¤Þ¤¹¡£ <tag>Option ``epsonmemwin''</tag> ESPON PC486GR¥·¥ê¡¼¥º°ÊÁ°¤Îµ¡¼ï¤Ç¡¢0xf00000¤ØVRAM¤ò¥Þ¥Ã¥Ô¥ó¥°²Äǽ ¤Ë¤·¤Þ¤¹¡£FreeBSD(98)¤Ç¤Ï¥«¡¼¥Í¥ëconfig»þ¤Ë»ØÄꤹ¤ë»ö¤Ç¡¢¥«¡¼¥Í¥ë --- 125,138 ---- <tag>Option ``ga98nb1''</tag> GA-98NB I/C »ÈÍÑ»þ¤Ëɬ¤º»ØÄꤷ¤Þ¤¹¡£ <tag>Option ``ga98nb2''</tag> ! GA-98NB II ¤ä GI-5434-2M ¤ò»ÈÍÑ»þ¤Ëɬ¤º»ØÄꤷ¤Þ¤¹¡£ <tag>Option ``ga98nb4''</tag> ! GA-98NB IV ¤ä GI-5434-4M ¤ò»ÈÍÑ»þ¤Ëɬ¤º»ØÄꤷ¤Þ¤¹¡£ <tag>Option ``wap''</tag> WAP-2000/4000»ÈÍÑ»þ¤Ëɬ¤º»ØÄꤷ¤Þ¤¹¡£ + <tag>Option ``no_mmio''</tag> + PC98ÍѤÎCLGD543x/544x·Ï¤Ç¤Ïɬ¤º»ØÄꤷ¤Æ²¼¤µ¤¤¡£GANBWAP¥µ¡¼¥Ð¤Î + ¾ì¹ç¤Ïɬ¿Ü¤È¤Ê¤ê¤Þ¤¹¡£ <tag>Option ``epsonmemwin''</tag> ESPON PC486GR¥·¥ê¡¼¥º°ÊÁ°¤Îµ¡¼ï¤Ç¡¢0xf00000¤ØVRAM¤ò¥Þ¥Ã¥Ô¥ó¥°²Äǽ ¤Ë¤·¤Þ¤¹¡£FreeBSD(98)¤Ç¤Ï¥«¡¼¥Í¥ëconfig»þ¤Ë»ØÄꤹ¤ë»ö¤Ç¡¢¥«¡¼¥Í¥ë *************** *** 135,141 **** <sect2>¤½¤Î¾<p> <itemize> <ITEM>GA-98NB, WAP¶¦¤ËIO port ¤Î SW ¤Ï default ¤Î 0 ¤Ç¤¹¡£ ! <ITEM>15/16/32bpp¤ÏÆ°ºî¤·¤Þ¤»¤ó¡£ <ITEM>¥É¥Ã¥È¥¯¥í¥Ã¥¯85MHz°Ê¾å¤Ç¤Ï¡¢¥Ï¡¼¥É¥¦¥§¥¢¥«¡¼¥½¥ë¤Ï»ÈÍѤǤ­ ¤Þ¤»¤ó¡£Option ``sw_cursor''¤ò»ØÄꤷ¤Æ¤¯¤À¤µ¤¤¡£ <ITEM>WGN-A2 ¤Ë¤Ä¤¤¤Æ¤Ï¡¢¿ô·ïÆ°ºî¤¹¤ë»Ý¤ÎÊó¹ð¤ò¼õ¤±¤Æ¤¤¤Þ¤¹¤¬¡¢ --- 151,157 ---- <sect2>¤½¤Î¾<p> <itemize> <ITEM>GA-98NB, WAP¶¦¤ËIO port ¤Î SW ¤Ï default ¤Î 0 ¤Ç¤¹¡£ ! <ITEM>15/16/24/32bpp¤ÏÆ°ºî¤·¤Þ¤»¤ó¡£ <ITEM>¥É¥Ã¥È¥¯¥í¥Ã¥¯85MHz°Ê¾å¤Ç¤Ï¡¢¥Ï¡¼¥É¥¦¥§¥¢¥«¡¼¥½¥ë¤Ï»ÈÍѤǤ­ ¤Þ¤»¤ó¡£Option ``sw_cursor''¤ò»ØÄꤷ¤Æ¤¯¤À¤µ¤¤¡£ <ITEM>WGN-A2 ¤Ë¤Ä¤¤¤Æ¤Ï¡¢¿ô·ïÆ°ºî¤¹¤ë»Ý¤ÎÊó¹ð¤ò¼õ¤±¤Æ¤¤¤Þ¤¹¤¬¡¢ *************** *** 152,157 **** --- 168,176 ---- °Ê²¼¤ÎOption¤¬PC98ÍѤ˻ØÄê¤Ç¤­¤Þ¤¹¡£¤³¤ì°Ê³°¤Ë¡¢README.cirrusÆâ¤Ë ²òÀ⤵¤ì¤Æ¤¤¤ë¥ª¥×¥·¥ç¥ó¤ò»ØÄê¤Ç¤­¤Þ¤¹¡£ <descrip> + <tag>Option ``no_mmio''</tag> + PC98ÍѤÎCLGD543x/544x·Ï¤Ç¤Ïɬ¤º»ØÄꤷ¤Æ²¼¤µ¤¤¡£WSNA¥µ¡¼¥Ð¤Î¾ì¹ç + ¤Ïɬ¿Ü¤È¤Ê¤ê¤Þ¤¹¡£ <tag>Option ``epsonmemwin''</tag> ESPON PC486GR¥·¥ê¡¼¥º°ÊÁ°¤Îµ¡¼ï¤Ç¡¢0xf00000¤ØVRAM¤ò¥Þ¥Ã¥Ô¥ó¥°²Äǽ ¤Ë¤·¤Þ¤¹¡£FreeBSD(98)¤Ç¤Ï¥«¡¼¥Í¥ëconfig»þ¤Ë»ØÄꤹ¤ë»ö¤Ç¡¢¥«¡¼¥Í¥ë *************** *** 170,176 **** <sect2>¤½¤Î¾<p> <itemize> <ITEM>GA-98NB, WAP¶¦¤ËIO port ¤Î SW ¤Ï default ¤Î 0 ¤Ç¤¹¡£ ! <ITEM>15/16/32bpp¤ÏÆ°ºî¤·¤Þ¤»¤ó¡£ <ITEM>¥É¥Ã¥È¥¯¥í¥Ã¥¯85MHz°Ê¾å¤Ç¤Ï¡¢¥Ï¡¼¥É¥¦¥§¥¢¥«¡¼¥½¥ë¤Ï»ÈÍѤǤ­ ¤Þ¤»¤ó¡£Option ``sw_cursor''¤ò»ØÄꤷ¤Æ¤¯¤À¤µ¤¤¡£ </itemize> --- 189,195 ---- <sect2>¤½¤Î¾<p> <itemize> <ITEM>GA-98NB, WAP¶¦¤ËIO port ¤Î SW ¤Ï default ¤Î 0 ¤Ç¤¹¡£ ! <ITEM>15/16/24/32bpp¤ÏÆ°ºî¤·¤Þ¤»¤ó¡£ <ITEM>¥É¥Ã¥È¥¯¥í¥Ã¥¯85MHz°Ê¾å¤Ç¤Ï¡¢¥Ï¡¼¥É¥¦¥§¥¢¥«¡¼¥½¥ë¤Ï»ÈÍѤǤ­ ¤Þ¤»¤ó¡£Option ``sw_cursor''¤ò»ØÄꤷ¤Æ¤¯¤À¤µ¤¤¡£ </itemize> *************** *** 180,186 **** <sect1>XF98_NKVNEC<p> ! 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XF86_Accel man page¤Ç²òÀ⤵¤ì¤Æ¤¤¤ë¥ª¥×¥·¥ç¥óÅù¤ò»ØÄê¤Ç¤­¤Þ¤¹¡£ PC98¸ÇÍ­°Ê³°¤ÎOptionÅù¤Ë¤Ä¤¤¤Æ¤ÏXF86_Accel man page¤ò»²¾È¤·¤Æ ¤¯¤À¤µ¤¤ <descrip> *************** *** 478,485 **** <itemize> <ITEM>PC9821Xn(864)¤Ç¤Ï¡¢Æ°ºî¤¬ÉÔ°ÂÄê¤Ç¤¹¡£WAIT¤¬Â­¤ê¤Ê¤¤ ¤³¤È¤¬¹Í¤¨¤é¤ì¤Þ¤¹¡£ ! <ITEM>X-MATE,A-MATE(864)¤Ç¤Ï¡¢16Bpp,32Bpp¤¬ÉÔ°ÂÄê¤Ê¤è¤¦¤Ç¤¹¡£ ! Æäˡ¢32Bpp¤Ï¥Ï¥ó¥°¥¢¥Ã¥×¤¹¤ë¤³¤È¤¬Â¿¤¤¤è¤¦¤Ç¤¹¡£ <ITEM>X-MATE,A-MATE(864)¤Ç¡¢¥µ¡¼¥Ðµ¯Æ°»þ¤Ë²èÌ̤¬Íð¤ì¤ë¾ì¹ç¤¬ ¤¢¤ê¤Þ¤¹¡£¤½¤Î¾ì¹ç¡¢²òÁüÅÙ¤òÀÚÂؤ¨¤ë¤È²óÉü¤·¤Þ¤¹¡£ (CTRL+GRPH+ +/-) --- 504,511 ---- <itemize> <ITEM>PC9821Xn(864)¤Ç¤Ï¡¢Æ°ºî¤¬ÉÔ°ÂÄê¤Ç¤¹¡£WAIT¤¬Â­¤ê¤Ê¤¤ ¤³¤È¤¬¹Í¤¨¤é¤ì¤Þ¤¹¡£ ! <ITEM>X-MATE,A-MATE(864)¤Ç¤Ï¡¢16bpp,32bpp¤¬ÉÔ°ÂÄê¤Ê¤è¤¦¤Ç¤¹¡£ ! Æäˡ¢32bpp¤Ï¥Ï¥ó¥°¥¢¥Ã¥×¤¹¤ë¤³¤È¤¬Â¿¤¤¤è¤¦¤Ç¤¹¡£ <ITEM>X-MATE,A-MATE(864)¤Ç¡¢¥µ¡¼¥Ðµ¯Æ°»þ¤Ë²èÌ̤¬Íð¤ì¤ë¾ì¹ç¤¬ ¤¢¤ê¤Þ¤¹¡£¤½¤Î¾ì¹ç¡¢²òÁüÅÙ¤òÀÚÂؤ¨¤ë¤È²óÉü¤·¤Þ¤¹¡£ (CTRL+GRPH+ +/-) *************** *** 493,500 **** ÀßÄ꤬ɬÍפǤ¹¡£ <ITEM>IO port ¤Ï default ¤ÎDIP¥¹¥¤¥Ã¥Á¤È¤·¤Þ¤¹¡£ </itemize> ! <sect2>»²¾È<p> ! README.s3¡¢XF86_Accell man page <sect1>XF98_GA968<p> --- 519,526 ---- ÀßÄ꤬ɬÍפǤ¹¡£ <ITEM>IO port ¤Ï default ¤ÎDIP¥¹¥¤¥Ã¥Á¤È¤·¤Þ¤¹¡£ </itemize> ! <sect2>´ØÏ¢<p> ! README.s3¡¢XF86_Accel man page <sect1>XF98_GA968<p> *************** *** 502,543 **** <sect2>XF86Config¤ÎÀßÄê<p> °Ê²¼¤ÎOptionÅù¤¬PC98ÍѤ˻ØÄê¤Ç¤­¤Þ¤¹¡£¤³¤ì°Ê³°¤Ë¡¢README.S3¡¢ ! XF86_Accell man page¤Ç²òÀ⤵¤ì¤Æ¤¤¤ë¥ª¥×¥·¥ç¥óÅù¤ò»ØÄê¤Ç¤­¤Þ¤¹¡£ PC98¸ÇÍ­°Ê³°¤ÎOptionÅù¤Ë¤Ä¤¤¤Æ¤ÏXF86_Accel man page¤ò»²¾È¤·¤Æ ¤¯¤À¤µ¤¤ <descrip> ! <tag>Chipset ``s3_generic''</tag> ! ¾ï¤Ë»ØÄꤷ¤Æ¤¯¤À¤µ¤¤¡£ </descrip> - <sect2> Êó¹ð¤µ¤ì¤Æ¤¤¤ëÌäÂê<p> - <itemize> - <ITEM>³«È¯¸å½½Ê¬¤Ê¥Æ¥¹¥È¤¬¹Ô¤ï¤ì¤Æ¤¤¤Ê¤¤¤Î¤ÇÆ°ºî¥ì¥Ý¡¼¥È¤ò - ¤ª´ê¤¤¤·¤Þ¤¹¡£ - </itemize> - <sect2>»²¾È<p> - README.s3¡¢XF86_Accell man page - <sect1>XF98_TGUI<p> ! NEC¤ÎÆ⢥¢¥¯¥»¥é¥ì¡¼¥¿(Trident TGUi9680XGi), IO Data¤ÎGA-DRV/98 ¤Ç Æ°ºî¤¹¤ë VGA256¥Ù¡¼¥¹¤Î¥µ¡¼¥Ð¤Ç¤¹¡£</p> <sect2>XF86Config¤ÎÀßÄê<p> ! README.tridentÆâ¤Ë²òÀ⤵¤ì¤Æ¤¤¤ë¥ª¥×¥·¥ç¥ó¤ò»ØÄê¤Ç¤­¤Þ¤¹¡£ ! ¥¢¥¯¥»¥é¥ì¡¼¥·¥ç¥óµ¡Ç½¤Ë¤ÏºÇ°­¤Î¾ì¹ç¥·¥¹¥Æ¥à¤Î¥Ï¥ó¥°¥¢¥Ã¥×¤òȼ¤¦ ! ÉÔ¶ñ¹ç¤¬¸«ÉÕ¤«¤Ã¤Æ¤¤¤Þ¤¹¤Î¤Ç¡¢Option ``noaccel''¤ò»ØÄꤷ¤Æ ! ¥¢¥¯¥»¥é¥ì¡¼¥·¥ç¥óµ¡Ç½¤òÀÚ¤êÎ¥¤·¤Æ¤¯¤À¤µ¤¤¡£</p> <sect2>Êó¹ð¤µ¤ì¤Æ¤¤¤ëÌäÂê<p> <itemize> ! <ITEM>GA-DRV/98¤Ç¡¢1024x768¤¬Àµ¾ï¤Ëɽ¼¨¤µ¤ì¤Ê¤¤¡£ </itemize> <sect2>¤½¤Î¾<p> <itemize> ! <ITEM>GA-DRV/98¤Ç¤Ï16bpp¤ÏÆ°ºî¤·¤Þ¤»¤ó¡£ ! <ITEM>15/24/32bpp¤ÏÆ°ºî¤·¤Þ¤»¤ó¡£ ! <ITEM>¤Þ¤À½½Ê¬¤Ê¥Æ¥¹¥È¤¬¹Ô¤ï¤ì¤Æ¤¤¤Ê¤¤¤Î¤ÇÆ°ºî¥ì¥Ý¡¼¥È¤ò¤ª´ê¤¤¤·¤Þ¤¹¡£ </itemize> <sect2>´ØÏ¢<p> README.trident¡¢XF86_SVGA man page</p> </article> --- 528,615 ---- <sect2>XF86Config¤ÎÀßÄê<p> °Ê²¼¤ÎOptionÅù¤¬PC98ÍѤ˻ØÄê¤Ç¤­¤Þ¤¹¡£¤³¤ì°Ê³°¤Ë¡¢README.S3¡¢ ! XF86_Accel man page¤Ç²òÀ⤵¤ì¤Æ¤¤¤ë¥ª¥×¥·¥ç¥óÅù¤ò»ØÄê¤Ç¤­¤Þ¤¹¡£ PC98¸ÇÍ­°Ê³°¤ÎOptionÅù¤Ë¤Ä¤¤¤Æ¤ÏXF86_Accel man page¤ò»²¾È¤·¤Æ ¤¯¤À¤µ¤¤ <descrip> ! <tag>VideoRam 4096</tag> ! GA-968V4/PCI¤Ç»ØÄꤷ¤Æ²¼¤µ¤¤¡£ ! <tag>VideoRam 2048</tag> ! GA-968V2/PCI¤Ç»ØÄꤷ¤Æ²¼¤µ¤¤¡£ </descrip> + <sect2>´ØÏ¢<p> + README.s3¡¢XF86_Accel man page <sect1>XF98_TGUI<p> ! NEC¤ÎÆ⢥¢¥¯¥»¥é¥ì¡¼¥¿(Trident TGUI9680/9682), IO Data¤ÎGA-DRV/98 ¤Ç Æ°ºî¤¹¤ë VGA256¥Ù¡¼¥¹¤Î¥µ¡¼¥Ð¤Ç¤¹¡£</p> <sect2>XF86Config¤ÎÀßÄê<p> ! °Ê²¼¤ÎOptionÅù¤¬PC98ÍѤ˻ØÄê¤Ç¤­¤Þ¤¹¡£¤³¤ì°Ê³°¤Ë¡¢README.tridentÆâ ! ¤Ë²òÀ⤵¤ì¤Æ¤¤¤ë¥ª¥×¥·¥ç¥ó¤ò»ØÄê¤Ç¤­¤Þ¤¹¡£ ! <descrip> ! <tag>Option ``xaa_no_color_exp''</tag> ! ¥¢¥¯¥»¥é¥ì¡¼¥·¥ç¥ó¤òÍ­¸ú¤Ë¤¹¤ë¾ì¹ç¡¢»ØÄꤷ¤Æ²¼¤µ¤¤¡£ ! <tag>Option ``noaccel''</tag> ! ¥¢¥¯¥»¥é¥ì¡¼¥·¥ç¥ó¤ò̵¸ú¤Ë¤¹¤ë¾ì¹ç¡¢»ØÄꤷ¤Æ²¼¤µ¤¤¡£ ¥¢¥¯¥»¥é¥ì¡¼¥·¥ç¥óµ¡Ç½¤Ë¤ÏºÇ°­¤Î¾ì¹ç¥·¥¹¥Æ¥à¤Î¥Ï¥ó¥°¥¢¥Ã¥×¤òȼ¤¦ ! ÉÔ¶ñ¹ç¤¬¸«ÉÕ¤«¤Ã¤Æ¤¤¤Þ¤¹¡£ ! </descrip> <sect2>Êó¹ð¤µ¤ì¤Æ¤¤¤ëÌäÂê<p> <itemize> ! <ITEM>XFree86 3.2A °Ê¹ß¤Ç¤Ï¡¢GA-DRV/98 ¤Ï»ÈÍѤǤ­¤Ê¤¯¤Ê¤Ã¤Æ¤¤¤Þ¤¹¡£ ! XFree86 3.2 ¤ò»ÈÍѤ¹¤ë¾ì¹ç¡¢¥¢¥¯¥»¥é¥ì¡¼¥·¥ç¥ó¤ÏÍøÍѤǤ­¤Þ¤»¤ó¡£ ! <ITEM>¤Þ¤À½½Ê¬¤Ê¥Æ¥¹¥È¤¬¹Ô¤ï¤ì¤Æ¤¤¤Ê¤¤¤Î¤ÇÆ°ºî¥ì¥Ý¡¼¥È¤ò¤ª´ê¤¤¤· ! ¤Þ¤¹¡£ </itemize> <sect2>¤½¤Î¾<p> <itemize> ! <ITEM>GA-DRV/98¤Ç¤Ï8bpp°Ê³°¤ÏÆ°ºî¤·¤Þ¤»¤ó¡£ </itemize> <sect2>´ØÏ¢<p> README.trident¡¢XF86_SVGA man page</p> + <sect1>XF98_MGA<p> + NEC¤ÎÆ⢥¢¥¯¥»¥é¥ì¡¼¥¿(Matrox Millennium/Mystique), PC/AT ¸ß´¹µ¡ÍÑ + Millennium ¤ÇÆ°ºî¤¹¤ë VGA256¥Ù¡¼¥¹¤Î¥µ¡¼¥Ð¤Ç¤¹¡£</p> + <sect2>XF86Config¤ÎÀßÄê<p> + README.MGAÆâ¤Ë²òÀ⤵¤ì¤Æ¤¤¤ë¥ª¥×¥·¥ç¥ó¤ò»ØÄê¤Ç¤­¤Þ¤¹¡£Ä̾ï¤ÏÆÃ¤Ë + ²¿¤â»ØÄꤹ¤ëɬÍ×̵¤¤È¦¤Ç¤¹¡£ + <sect2>Êó¹ð¤µ¤ì¤Æ¤¤¤ëÌäÂê<p> + <itemize> + <ITEM>Millennium ¤Ç¤Ï¡¢Modeline ¤ÎÀßÄê¤Ë¤è¤Ã¤Æ¤Ï 24bpp ¤Ç½Ä¤ËÀþ + ¤¢¤ë¤¤¤Ï¼ÊÌÏÍͤΥΥ¤¥º¤¬½Ð¤ë¤³¤È¤¬¤¢¤ê¤Þ¤¹¡£ + <ITEM>Mystique ¤Ç¤Ï¡¢»ÈÍÑÁ°¤Ë Windows(3.1/95/NT) ¤ò»ÈÍѤ¹¤ë¿§¿ô¤Ë + ¹ç¤ï¤»¤Æµ¯Æ°¤·¤Æ¤ª¤¯É¬Íפ¬¤¢¤ê¤Þ¤¹¡£°ìöµ¯Æ°¤¹¤ì¤ÐÅŸ»¤òOFF¤Ë¤¹¤ë + ¤Þ¤Ç¤ÏÀµ¾ï¤ËÆ°ºî¤·¤Þ¤¹¡£¤¿¤À¤· 8bpp ¤Ï¿§¤¬¤ª¤«¤·¤¯¤Ê¤ê¤Þ¤¹¡£ + </itemize> + <sect2>¤½¤Î¾<p> + <itemize> + <ITEM>PC/AT ¸ß´¹µ¡ÍѤΠMillennium ¤ò»ÈÍѤ¹¤ë¾ì¹ç¤Ï¡¢VGA ¤ò disable + ¤·¤Æ²¼¤µ¤¤¡£ + <ITEM>PC/AT ¸ß´¹µ¡ÍѤΠMillennium II, Mystique ¤Ï¡¢VGA ¤ò disable + ¤Ç¤­¤Ê¤¤¤Î¤Ç¡¢»ÈÍѤǤ­¤Þ¤»¤ó¡£ + <ITEM>¤Þ¤À½½Ê¬¤Ê¥Æ¥¹¥È¤¬¹Ô¤ï¤ì¤Æ¤¤¤Ê¤¤¤Î¤ÇÆ°ºî¥ì¥Ý¡¼¥È¤ò¤ª´ê¤¤¤· + ¤Þ¤¹¡£ + </itemize> + <sect2>´ØÏ¢<p> + README.MGA¡¢XF86_SVGA man page</p> + + <sect1>XF98_SVGA<p> + NEC¤ÎÆ⢥¢¥¯¥»¥é¥ì¡¼¥¿(Cirrus Logic CL-GD7555,7556)¤ÇÆ°ºî¤¹¤ë + VGA256¥Ù¡¼¥¹¤Î¥µ¡¼¥Ð¤Ç¤¹¡£</p> + <sect2>XF86Config¤ÎÀßÄê<p> + README.cirrusÆâ¤Ë²òÀ⤵¤ì¤Æ¤¤¤ë¥ª¥×¥·¥ç¥ó¤ò»ØÄê¤Ç¤­¤Þ¤¹¡£ + <sect2>Êó¹ð¤µ¤ì¤Æ¤¤¤ëÌäÂê<p> + <itemize> + <ITEM>¥³¥ó¥½¡¼¥ë¤Ø¤ÎÉüµ¢¸å¤ÎÉÁ²è¤¬½ÐÍè¤Ê¤«¤Ã¤¿¤ê¡¢µ¯Æ°»þ¤Ë640x400Éôʬ¤¬ + ɽ¼¨¤µ¤ì¤Ê¤¤¾õÂ֤ˤʤ俤ꤷ¤Þ¤¹¡£ + <ITEM>Option ``noaccel''¤ò»ØÄꤷ¤Ê¤¤¾ì¹ç¡¢²èÌ̤˥´¥ß¤¬¤Ç¤ë»ö¤¬¤¢¤ê¤Þ¤¹¡£ + </itemize> + <sect2>¤½¤Î¾<p> + <itemize> + <ITEM>¤Þ¤À½½Ê¬¤Ê¥Æ¥¹¥È¤¬¹Ô¤ï¤ì¤Æ¤¤¤Ê¤¤¤Î¤ÇÆ°ºî¥ì¥Ý¡¼¥È¤ò¤ª´ê¤¤¤· + ¤Þ¤¹¡£ + </itemize> + <sect2>´ØÏ¢<p> + README.cirrus¡¢XF86_SVGA man page</p> </article> *** ./programs/Xserver/hw/xfree98/doc/VideoBoard98@@/PUBLIC-LATEST Sun Aug 10 13:08:17 1997 --- xc/programs/Xserver/hw/xfree98/doc/VideoBoard98 Fri Mar 6 14:12:26 1998 *************** *** 1,4 **** ! DATE:970730 XFree86 PC98 Server Video System List --- 1,4 ---- ! DATE:980213 XFree86 PC98 Server Video System List *************** *** 10,16 **** X : Not Working/Not supported 2 : 2MB o? : Probably work 3 : 3MB x? : Probably NOT work 4 : 4MB ! D : Developping ? : Unknown --- 10,16 ---- X : Not Working/Not supported 2 : 2MB o? : Probably work 3 : 3MB x? : Probably NOT work 4 : 4MB ! D : Developping 8 : 8MB ? : Unknown *************** *** 24,46 **** |PEGC |PEGC | B/I | B/I | | O |X| +------------------------+---------------+-------+--------+-+-------+-+ |WAB-A (PC-9821A-E01) |S3-928 |Bt481 |ICS2494 |1| O | | ! |WAB-A2 (PC-9821A-E11) |MGA2 | | |2| X | | |WAB-B (PC-9801-85) |S3-928 |Bt481 |ICS2494 |1| O | | |WAB-B3 (PC-9801-96) |CLGD5428 | B/I | B/I |1| X |X| |FC-WAB-A (PC-9821A-E09) |S3-928 |Bt485 |ICS2494 |2| o | | |FC-WAB-B (PC-9801-91) |S3-928 |Bt485 |ICS2494 |2| o? | | ! |FC-WAB-X (PC-9821X-B01) |MGA2 | | |2| X | | ! |FC-WAB-X2(PC-9821X-B03) |MGA2064W |Ti3026 |Ti3026 |2| D |O| |MSWIN KIT(PC-9801B3-E02)|CLGD5428 | B/I | B/I |1| X |X| +------------------------+---------------+-------+--------+-+-------+-+ |PC9821As2/U7W/U8W |S3-928E | | |1| o? | | |PC9821As3 |S3-864 |S3-SDAC|S3-SDAC |2| o |O| |PC9821Ap2/U8W/C9W |S3-928E | | |1| O | | ! |PC9821Ap2/C9T |MGA2 | | |2| X | | |PC9821Ap3 |S3-864 |S3-SDAC|S3-SDAC |2| o? |O| |PC9821Af/M9W/U9W |S3-928 |Bt485 |ICS2494 |2| o? | | |PC9821An/U8W |S3-928 |Bt485 |ICS2494 |2| o? | | ! |PC9821An/C9T |MGA2 | | |2| X | | +------------------------+---------------+-------+--------+-+-------+-+ |PC9821Bf/U8W |CLGD5428 | B/I | B/I |1| o |X| |PC9821Bp/U8W/U7W |CLGD5428 | B/I | B/I |1| o? |X| --- 24,46 ---- |PEGC |PEGC | B/I | B/I | | O |X| +------------------------+---------------+-------+--------+-+-------+-+ |WAB-A (PC-9821A-E01) |S3-928 |Bt481 |ICS2494 |1| O | | ! |WAB-A2 (PC-9821A-E11) |MGA II | | |2| X | | |WAB-B (PC-9801-85) |S3-928 |Bt481 |ICS2494 |1| O | | |WAB-B3 (PC-9801-96) |CLGD5428 | B/I | B/I |1| X |X| |FC-WAB-A (PC-9821A-E09) |S3-928 |Bt485 |ICS2494 |2| o | | |FC-WAB-B (PC-9801-91) |S3-928 |Bt485 |ICS2494 |2| o? | | ! |FC-WAB-X (PC-9821X-B01) |MGA II | | |2| X | | ! |FC-WAB-X2(PC-9821X-B03) |MGA2064W |Ti3026 |Ti3026 |2| o? |O| |MSWIN KIT(PC-9801B3-E02)|CLGD5428 | B/I | B/I |1| X |X| +------------------------+---------------+-------+--------+-+-------+-+ |PC9821As2/U7W/U8W |S3-928E | | |1| o? | | |PC9821As3 |S3-864 |S3-SDAC|S3-SDAC |2| o |O| |PC9821Ap2/U8W/C9W |S3-928E | | |1| O | | ! |PC9821Ap2/C9T |MGA II | | |2| X | | |PC9821Ap3 |S3-864 |S3-SDAC|S3-SDAC |2| o? |O| |PC9821Af/M9W/U9W |S3-928 |Bt485 |ICS2494 |2| o? | | |PC9821An/U8W |S3-928 |Bt485 |ICS2494 |2| o? | | ! |PC9821An/C9T |MGA II | | |2| X | | +------------------------+---------------+-------+--------+-+-------+-+ |PC9821Bf/U8W |CLGD5428 | B/I | B/I |1| o |X| |PC9821Bp/U8W/U7W |CLGD5428 | B/I | B/I |1| o? |X| *************** *** 51,86 **** |PC9801BX3/U2/W |CLGD5428 | B/I | B/I |1| X |X| |PC9801BX4/U2 |CLGD5430 | B/I | B/I |1| o? |X| +------------------------+---------------+-------+--------+-+-------+-+ ! |PC9821Xt |MGA2 | | |4| X | | ! |PC9821Xt13 |MGA2064W |Ti3026 |Ti3026 |4| D |O| ! |PC9821Xt16 |MGA2064W |Ti3026 |Ti3026 |4| D |O| ! |PC9821St15 |MGA2064W |Ti3026 |Ti3026 |4| D |O| ! |PC9821St20 |MGA2064W |Ti3026 |Ti3026 |4| D |O| ! |PC9821Xa |MGA2 | | |2| X | | ! |PC9821Xa7/C,K |TGUI9680 | B/I | B/I |2| o | | ! |PC9821Xa9/C,K |TGUI9680 | B/I | B/I |2| o? | | ! |PC9821Xa10/C,K |TGUI9680 | B/I | B/I |2| o? | | ! |PC9821Xa12/C,K |TGUI9680 | B/I | B/I |2| o? | | ! |PC9821Xa13/C,K |TGUI9680 | B/I | B/I |2| o? | | ! |PC9821Xa13/W |TGUI9682 | B/I | B/I |2| o? | | ! |PC9821Xa16/R |TGUI9680 | B/I | B/I |2| o? | | ! |PC9821Xa16/W |TGUI9682 | B/I | B/I |2| o? | | ! |PC9821Xa20/W |TGUI9682 | B/I | B/I |2| o? | | |PC9821Xb10 |CLGD5440 | B/I | B/I |1| o? |X| ! |PC9821Xc13/M,S |TGUI9680 | B/I | B/I |2| o? | | |PC9821Xc13/S5 |CLGD5446 | B/I | B/I |1| o? |X| |PC9821Xc16/M,S |CLGD5446 | B/I | B/I |2| o? |X| |PC9821Xc200/M,S |CLGD5446 | B/I | B/I |2| o? |X| |PC9821Xa7e |CLGD5440 | B/I | B/I |1| o? |X| |PC9821Xn |S3-864 |S3-SDAC|S3-SDAC |2| U | | ! |PC9821Xf |MGA2 | | |2| X | | |PC9821Xp |S3-864 |S3-SDAC|S3-SDAC |2| o |O| |PC9821Xs |S3-864 |S3-SDAC|S3-SDAC |2| o |O| |PC9821Xe |CLGD5430 | B/I | B/I |1| o? |X| |PC9821Xe10 |CLGD5430 | B/I | B/I |1| O |X| ! |PC9821Xv13/R |TGUI9680 | B/I | B/I |2| o? | | ! |PC9821Xv13/W |MGA2064W |Ti3026 |Ti3026 |4| D |O| ! |PC9821Xv20/W |MGA2064W |Ti3026 |Ti3026 |4| D |O| +------------------------+---------------+-------+--------+-+-------+-+ |PC9821V7/C |CLGD5440 | B/I | B/I |1| o? |X| |PC9821V10/C,S |CLGD5440 | B/I | B/I |1| o? |X| --- 51,87 ---- |PC9801BX3/U2/W |CLGD5428 | B/I | B/I |1| X |X| |PC9801BX4/U2 |CLGD5430 | B/I | B/I |1| o? |X| +------------------------+---------------+-------+--------+-+-------+-+ ! |PC9821Xt |MGA II | | |4| X | | ! |PC9821Xt13 |MGA2064W |Ti3026 |Ti3026 |4| o? |O| ! |PC9821Xt16 |MGA2064W |Ti3026 |Ti3026 |4| o? |O| ! |PC9821St15 |MGA2064W |Ti3026 |Ti3026 |4| o? |O| ! |PC9821St20 |MGA2064W |Ti3026 |Ti3026 |4| o? |O| ! |PC9821Xa |MGA II | | |2| X | | ! |PC9821Xa7/C,K |TGUI9680 | B/I | B/I |2| o |O| ! |PC9821Xa9/C,K |TGUI9680 | B/I | B/I |2| o? |O| ! |PC9821Xa10/C,K |TGUI9680 | B/I | B/I |2| o? |O| ! |PC9821Xa12/C,K |TGUI9680 | B/I | B/I |2| o? |O| ! |PC9821Xa13/C,K |TGUI9680 | B/I | B/I |2| o? |O| ! |PC9821Xa13/W |TGUI9682 | B/I | B/I |2| o? |O| ! |PC9821Xa16/R |TGUI9680 | B/I | B/I |2| o? |O| ! |PC9821Xa16/W |TGUI9682 | B/I | B/I |2| o? |O| ! |PC9821Xa20/D,W |TGUI9682 | B/I | B/I |2| o? |O| ! |PC9821Xa200/D,W |TGUI9682 | B/I | B/I |2| o? |O| |PC9821Xb10 |CLGD5440 | B/I | B/I |1| o? |X| ! |PC9821Xc13/M,S |TGUI9680 | B/I | B/I |2| o? |O| |PC9821Xc13/S5 |CLGD5446 | B/I | B/I |1| o? |X| |PC9821Xc16/M,S |CLGD5446 | B/I | B/I |2| o? |X| |PC9821Xc200/M,S |CLGD5446 | B/I | B/I |2| o? |X| |PC9821Xa7e |CLGD5440 | B/I | B/I |1| o? |X| |PC9821Xn |S3-864 |S3-SDAC|S3-SDAC |2| U | | ! |PC9821Xf |MGA II | | |2| X | | |PC9821Xp |S3-864 |S3-SDAC|S3-SDAC |2| o |O| |PC9821Xs |S3-864 |S3-SDAC|S3-SDAC |2| o |O| |PC9821Xe |CLGD5430 | B/I | B/I |1| o? |X| |PC9821Xe10 |CLGD5430 | B/I | B/I |1| O |X| ! |PC9821Xv13/R |TGUI9680 | B/I | B/I |2| o? |O| ! |PC9821Xv13/W |MGA2064W |Ti3026 |Ti3026 |4| o? |O| ! |PC9821Xv20/W |MGA2064W |Ti3026 |Ti3026 |4| o? |O| +------------------------+---------------+-------+--------+-+-------+-+ |PC9821V7/C |CLGD5440 | B/I | B/I |1| o? |X| |PC9821V10/C,S |CLGD5440 | B/I | B/I |1| o? |X| *************** *** 89,102 **** |PC9821V16/S |CLGD5440 | B/I | B/I |1| o? |X| |PC9821V16/S5V,P |CLGD5446 | B/I | B/I |2| o? |X| |PC9821V20/S7 |CLGD5440 | B/I | B/I |1| o? |X| ! |PC9821V13/M7 |TGUI9680 | B/I | B/I |2| o? | | ! |PC9821V16/M7 |TGUI9680 | B/I | B/I |2| o? | | ! |PC9821V20/M7 |TGUI9680 | B/I | B/I |2| o? | | ! |PC9821V166/S |MGA1064SG | B/I | B/I |2| X | | ! |PC9821V200/S |MGA1064SG | B/I | B/I |2| X | | ! |PC9821V200/M |MGA1064SG | B/I | B/I |4| X | | ! |PC9821V233/M7 |MGA1064SG | B/I | B/I |2| X | | ! |PC9821V233/M7V |MGA1064SG | B/I | B/I |4| X | | +------------------------+---------------+-------+--------+-+-------+-+ |PC9821Ce |CLGD5428 | B/I | B/I |1| o? |X| |PC9821Ce2 |CLGD5428 | B/I | B/I |1| o? |X| --- 90,103 ---- |PC9821V16/S |CLGD5440 | B/I | B/I |1| o? |X| |PC9821V16/S5V,P |CLGD5446 | B/I | B/I |2| o? |X| |PC9821V20/S7 |CLGD5440 | B/I | B/I |1| o? |X| ! |PC9821V13/M7 |TGUI9680 | B/I | B/I |2| o? |O| ! |PC9821V16/M7 |TGUI9680 | B/I | B/I |2| o? |O| ! |PC9821V20/M7 |TGUI9680 | B/I | B/I |2| o? |O| ! |PC9821V166/S |MGA1064SG | B/I | B/I |2| D |O| ! |PC9821V200/S |MGA1064SG | B/I | B/I |2| D |O| ! |PC9821V200/M |MGA1064SG | B/I | B/I |4| D |O| ! |PC9821V233/M7 |MGA1064SG | B/I | B/I |2| D |O| ! |PC9821V233/M7V |MGA1064SG | B/I | B/I |4| D |O| +------------------------+---------------+-------+--------+-+-------+-+ |PC9821Ce |CLGD5428 | B/I | B/I |1| o? |X| |PC9821Ce2 |CLGD5428 | B/I | B/I |1| o? |X| *************** *** 117,129 **** |PC9821Cu16/H |ProVidia9685 | B/I | B/I |2| ? |X| |PC9821Ct20/A |ProVidia9685 | B/I | B/I |2| ? |X| +------------------------+---------------+-------+--------+-+-------+-+ ! |PC9821Ra20/N |TGUI9682 | B/I | B/I |2| o | | +------------------------+---------------+-------+--------+-+-------+-+ ! |PC9821RaII23/N,W |TGUI9682 | B/I | B/I |2| o? | | ! |PC9821RvII26/N20 |MGA2064W |Ti3026 |Ti3026 |4| D |O| +------------------------+---------------+-------+--------+-+-------+-+ ! |PC9821Rs20/B20 |TGUI9682 | B/I | B/I |2| o? | | ! |PC9821RsII26/B40 |TGUI9682 | B/I | B/I |2| o? | | +------------------------+---------------+-------+--------+-+-------+-+ |PC9821C166/C |3Dimage975 | | |4| X | | |PC9821C166/D |ProVidia9685 | B/I | B/I |2| ? | | --- 118,133 ---- |PC9821Cu16/H |ProVidia9685 | B/I | B/I |2| ? |X| |PC9821Ct20/A |ProVidia9685 | B/I | B/I |2| ? |X| +------------------------+---------------+-------+--------+-+-------+-+ ! |PC9821Ra18/N |TGUI9682 | B/I | B/I |2| o? |O| ! |PC9821Ra20/N |TGUI9682 | B/I | B/I |2| o |O| ! |PC9821Ra266/D,N,W |TGUI9682 | B/I | B/I |2| o |O| ! |PC9821Rv20/N20 |MGA2064W |Ti3026 |Ti3026 |4| o? |O| +------------------------+---------------+-------+--------+-+-------+-+ ! |PC9821RaII23/N,W |TGUI9682 | B/I | B/I |2| o? |O| ! |PC9821RvII26/N20 |MGA2064W |Ti3026 |Ti3026 |4| o |O| +------------------------+---------------+-------+--------+-+-------+-+ ! |PC9821Rs20/B20 |TGUI9682 | B/I | B/I |2| o? |O| ! |PC9821RsII26/B40 |TGUI9682 | B/I | B/I |2| o? |O| +------------------------+---------------+-------+--------+-+-------+-+ |PC9821C166/C |3Dimage975 | | |4| X | | |PC9821C166/D |ProVidia9685 | B/I | B/I |2| ? | | *************** *** 133,143 **** |PC9821Es |CLGD5428 | B/I | B/I |1| o? |X| |PC9821F200/X20 |ProVidia9685 | B/I | B/I |2| ? | | +------------------------+---------------+-------+--------+-+-------+-+ ! |PC9821Ne2 |CLGD5428 | B/I | B/I |1| X |X| ! |PC9821Np |CLGD5428 | B/I | B/I |1| o? |X| ! |PC9821Nf |CLGD5428 | B/I | B/I |1| o? |X| ! |PC9821Ns |CLGD5428 | B/I | B/I |1| o? |X| ! |PC9821Nd |CLGD5428 | B/I | B/I |1| X |X| |PC9821Ne3 |Cyber9320 | B/I | B/I |1| X | | |PC9821Nd2 |Cyber9320 | B/I | B/I |1| X | | |PC9821Na7/HC,H |Cyber9320 | B/I | B/I |1| X | | --- 137,147 ---- |PC9821Es |CLGD5428 | B/I | B/I |1| o? |X| |PC9821F200/X20 |ProVidia9685 | B/I | B/I |2| ? | | +------------------------+---------------+-------+--------+-+-------+-+ ! |PC9821Ne2 |CLGD5428 | B/I | B/I |1| U | | ! |PC9821Np |CLGD5428 | B/I | B/I |1| U | | ! |PC9821Nf |CLGD5428 | B/I | B/I |1| U | | ! |PC9821Ns |CLGD5428 | B/I | B/I |1| U | | ! |PC9821Nd |CLGD5428 | B/I | B/I |1| U | | |PC9821Ne3 |Cyber9320 | B/I | B/I |1| X | | |PC9821Nd2 |Cyber9320 | B/I | B/I |1| X | | |PC9821Na7/HC,H |Cyber9320 | B/I | B/I |1| X | | *************** *** 151,170 **** |PC9821Nb10 |CLGD7548 | B/I | B/I |1| X | | |PC9821Nx/3,C7 |Cyber9320 | B/I | B/I |1| X | | |PC9821Nr12 |CLGD7555 | B/I | B/I |2| D | | ! |PC9821Nr13 |CLGD7555 | B/I | B/I |2| D | | |PC9821Nr15 |Cyber9385 | B/I | B/I |2| X | | |PC9821Nr150 |Cyber9385 | B/I | B/I |2| X | | |PC9821Nr166 |Cyber9385 | B/I | B/I |2| X | | ! |PC9821Nw133 |Cyber9385 | B/I | B/I |2| X | | ! |PC9821Nw150 |Cyber9385 | B/I | B/I |2| X | | +------------------------+---------------+-------+--------+-+-------+-+ |PC9821Lt2 |Cyber9320 | B/I | B/I |1| X | | |PC9821La7 |Cyber9320 | B/I | B/I |1| X | | |PC9821La10 |Cyber9320 | B/I | B/I |1| X | | ! |PC9821La13 | | B/I | B/I |2| X | | +------------------------+---------------+-------+--------+-+-------+-+ |PC9821Ls12 |CLGD7555 | B/I | B/I |2| D | | |PC9821Ls13 |CLGD7555 | B/I | B/I |2| D | | |PC9821Ls150 |CLGD7555 | B/I | B/I |2| D | | +------------------------+---------------+-------+--------+-+-------+-+ --- 155,177 ---- |PC9821Nb10 |CLGD7548 | B/I | B/I |1| X | | |PC9821Nx/3,C7 |Cyber9320 | B/I | B/I |1| X | | |PC9821Nr12 |CLGD7555 | B/I | B/I |2| D | | ! |PC9821Nr13/D10 |CLGD7555 | B/I | B/I |2| D | | ! |PC9821Nr13/D14,S14 |CLGD7556 | B/I | B/I |2| D | | |PC9821Nr15 |Cyber9385 | B/I | B/I |2| X | | |PC9821Nr150 |Cyber9385 | B/I | B/I |2| X | | + |PC9821Nr150/S20 |Cyber9385-1 | B/I | B/I |2| X | | |PC9821Nr166 |Cyber9385 | B/I | B/I |2| X | | ! |PC9821Nw133 |Cyber9385-1 | B/I | B/I |2| X | | ! |PC9821Nw150 |Cyber9385-1 | B/I | B/I |2| X | | +------------------------+---------------+-------+--------+-+-------+-+ |PC9821Lt2 |Cyber9320 | B/I | B/I |1| X | | |PC9821La7 |Cyber9320 | B/I | B/I |1| X | | |PC9821La10 |Cyber9320 | B/I | B/I |1| X | | ! |PC9821La13 |CLGD7555 | B/I | B/I |2| X | | +------------------------+---------------+-------+--------+-+-------+-+ |PC9821Ls12 |CLGD7555 | B/I | B/I |2| D | | |PC9821Ls13 |CLGD7555 | B/I | B/I |2| D | | + |PC9821Ls13 |CLGD7556 | B/I | B/I |2| D | | |PC9821Ls150 |CLGD7555 | B/I | B/I |2| D | | +------------------------+---------------+-------+--------+-+-------+-+ *************** *** 184,190 **** |PCPKB4 |S3-928 |20c491 | |1| U | | |PCPKB4 |S3-928 |Bt485 | |2| o? | | |PCPKB4 |S3-928 |Bt485 | |4| o? | | ! |PCPKB5 | | | | | x? | | |PCHKB |S3-911 |Bt478 | |h| X | | |PCHKB |S3-911 |Bt478 | |1| X | | |PCHKB |S3-924 |Bt478 | |h| X | | --- 191,197 ---- |PCPKB4 |S3-928 |20c491 | |1| U | | |PCPKB4 |S3-928 |Bt485 | |2| o? | | |PCPKB4 |S3-928 |Bt485 | |4| o? | | ! |PCPKB5 |S3-964 | | |2| x? | | |PCHKB |S3-911 |Bt478 | |h| X | | |PCHKB |S3-911 |Bt478 | |1| X | | |PCHKB |S3-924 |Bt478 | |h| X | | *************** *** 202,218 **** |PC586RJ |S3-964 | | |1| x? | | |PC586RV |CLGD5429 | B/I | B/I |1| O |X| |PC586MV |CLGD5428 | B/I | B/I |1| o? |X| ! |PC486MU |CLGD5428 | B/I | B/I |1| o? |X| |PC486MS |CLGD5428 | B/I | B/I |1| o? |X| |PC486MR |CLGD5428 | B/I | B/I |1| o? |X| |PC486MV |CLGD5428 | B/I | B/I |1| O |X| |PC486ME |TGUI9660 | B/I | B/I |1| X | | ! |PC486HA3/JW |S3-964 | | |1| x? | | +------------------------+---------------+-------+--------+-+-------+-+ |PC486NAT |CLGD7543 | B/I | B/I |1| x? | | |PC586NAT |CLGD7543 | B/I | B/I |1| x? | | +------------------------+---------------+-------+--------+-+-------+-+ Canopus +------------------------+---------------+-------+--------+-+-------+-+ --- 209,230 ---- |PC586RJ |S3-964 | | |1| x? | | |PC586RV |CLGD5429 | B/I | B/I |1| O |X| |PC586MV |CLGD5428 | B/I | B/I |1| o? |X| ! |PC486MU |CLGD5429 | B/I | B/I |1| o? |X| |PC486MS |CLGD5428 | B/I | B/I |1| o? |X| |PC486MR |CLGD5428 | B/I | B/I |1| o? |X| |PC486MV |CLGD5428 | B/I | B/I |1| O |X| |PC486ME |TGUI9660 | B/I | B/I |1| X | | ! |PC486HA3/JW |S3-964 | | |2| x? | | +------------------------+---------------+-------+--------+-+-------+-+ |PC486NAT |CLGD7543 | B/I | B/I |1| x? | | |PC586NAT |CLGD7543 | B/I | B/I |1| x? | | +------------------------+---------------+-------+--------+-+-------+-+ + Frontier Kojiro + +------------------------+---------------+-------+--------+-+-------+-+ + |PC9821As2 HYPER |S3-928E | | |1| o? | | + |PC9821Bs HYPER |CLGD5428 | B/I | B/I |1| o? |X| + +------------------------+---------------+-------+--------+-+-------+-+ Canopus +------------------------+---------------+-------+--------+-+-------+-+ *************** *** 226,242 **** |Power Window928 |S3-928D |SC15026|ICD2051A|2| O |O| |Power Window928G |S3-928G |SC15026|ICD2051A|1| O |O| |Power Window928G |S3-928G |SC15026|ICD2051A|2| O |O| |Power Window928II |S3-928D |20c505 |ICD2051A|2| o |O| |Power Window928GLB |S3-928G |SC15026|ICD2051A|1| O |O| ! |Power Window928GLB |S3-928G |SC15026|ICD2051A|2| O | | |Power Window928IILB |S3-928 |20c505 |ICD2051A|2| o | | |Power Window964LB |S3-964 |Ti3025 | |2| o |O| |Power Window964LB |S3-964 |Ti3025 | |4| o |O| |Power Window968 |S3-968 | | |2| ? | | |Power Window968 |S3-968 | | |4| ? | | ! |Power Window9100PCI |P9100 |Bt485 | |2| X | | ! |Power Window9100PCI |P9100 |RGB525 | |4| X | | ! |Power Window9130C-PCI |P9100 | | |4| X | | |Power WindowT64EL |S3-Trio64 | B/I | B/I | | X | | |Power WindowT64S |S3-Trio64 | B/I | B/I |2| X | | |Power WindowT64V Card |S3-Trio64V+ | B/I | B/I |2| X | | --- 238,256 ---- |Power Window928 |S3-928D |SC15026|ICD2051A|2| O |O| |Power Window928G |S3-928G |SC15026|ICD2051A|1| O |O| |Power Window928G |S3-928G |SC15026|ICD2051A|2| O |O| + |Power Window928II |S3-928G |Bt485 |ICD2051A|2| o |O| |Power Window928II |S3-928D |20c505 |ICD2051A|2| o |O| |Power Window928GLB |S3-928G |SC15026|ICD2051A|1| O |O| ! |Power Window928GLB |S3-928G |SC15026|ICD2051A|2| O |O| ! |Power Window928IILB |S3-928G |Bt485 |ICD2051A|2| o | | |Power Window928IILB |S3-928 |20c505 |ICD2051A|2| o | | |Power Window964LB |S3-964 |Ti3025 | |2| o |O| |Power Window964LB |S3-964 |Ti3025 | |4| o |O| |Power Window968 |S3-968 | | |2| ? | | |Power Window968 |S3-968 | | |4| ? | | ! |Power Window9100PCI |Powe9100 |20c505 |ICD2061A|2| X | | ! |Power Window9100PCI |Powe9100 |RGB525 |RGB525 |4| X | | ! |Power Window9130C-PCI |Powe9100 | | |4| X | | |Power WindowT64EL |S3-Trio64 | B/I | B/I | | X | | |Power WindowT64S |S3-Trio64 | B/I | B/I |2| X | | |Power WindowT64V Card |S3-Trio64V+ | B/I | B/I |2| X | | *************** *** 260,266 **** |NMB-S |CLGD5428 | B/I | B/I |1| o? |X| |NMG-G (note) |CLGD5428 | B/I | B/I |1| o? |X| |NMG-S4F(note) |CLGD5428 | B/I | B/I |1| o? |X| ! |WSP-L |P9000 | | | | X | | |WAP-2000 |CLGD5434 | B/I | B/I |2| O |X| |WAP-4000 |CLGD5434 | B/I | B/I |4| O |X| |WSN-A2F |CLGD5434 | B/I | B/I |2| O |X| --- 274,280 ---- |NMB-S |CLGD5428 | B/I | B/I |1| o? |X| |NMG-G (note) |CLGD5428 | B/I | B/I |1| o? |X| |NMG-S4F(note) |CLGD5428 | B/I | B/I |1| o? |X| ! |WSP-L |Power9000 | | | | X | | |WAP-2000 |CLGD5434 | B/I | B/I |2| O |X| |WAP-4000 |CLGD5434 | B/I | B/I |4| O |X| |WSN-A2F |CLGD5434 | B/I | B/I |2| O |X| *************** *** 278,284 **** |WGP-VG4 |S3-ViRGE | B/I | B/I |4| X | | |WGP-VG2DX |S3-ViRGE/DX | B/I | B/I |2| X | | |WGP-VG4DX |S3-ViRGE/DX | B/I | B/I |4| X | | ! |WGP-VX8 |S3-ViRGE/VX | | |8| X | | +------------------------+---------------+-------+--------+-+-------+-+ --- 292,300 ---- |WGP-VG4 |S3-ViRGE | B/I | B/I |4| X | | |WGP-VG2DX |S3-ViRGE/DX | B/I | B/I |2| X | | |WGP-VG4DX |S3-ViRGE/DX | B/I | B/I |4| X | | ! |WGP-VX8 |S3-ViRGE/VX | B/I | B/I |8| X | | ! |WHP-PS8 |PERMEDIA2 | | |8| X | | ! |WHP-PS4 |PERMEDIA2 | | |4| X | | +------------------------+---------------+-------+--------+-+-------+-+ *************** *** 289,300 **** |GA-98NBI/C,SB16-GA98 |CLGD5434 | B/I | B/I |1| O |X| |GA-98NB II |CLGD5434 | B/I | B/I |2| O |X| |GA-98NB IV |CLGD5434 | B/I | B/I |4| O |X| ! |GA-DR2/98 |TGUI9660 | B/I | B/I |2| o |X| ! |GA-DR4/98 |TGUI9660 | B/I | B/I |4| o? |X| |GA-DR2/PCI |TGUI9660 | B/I | B/I |2| X | | |GA-DR4/PCI |TGUI9660 | B/I | B/I |4| X | | ! |GA-DRV2/98 |TGUI9680 | B/I | B/I |2| o? |X| ! |GA-DRV4/98 |TGUI9680 | B/I | B/I |4| o |X| |GA-DRV2/PCI |TGUI9680 | B/I | B/I |2| X | | |GA-DRV4/PCI |TGUI9680 | B/I | B/I |4| X | | |GA-DRTV2/98PCI |TGUI9682 | B/I | B/I |2| X | | --- 305,316 ---- |GA-98NBI/C,SB16-GA98 |CLGD5434 | B/I | B/I |1| O |X| |GA-98NB II |CLGD5434 | B/I | B/I |2| O |X| |GA-98NB IV |CLGD5434 | B/I | B/I |4| O |X| ! |GA-DR2/98 |TGUI9660 | B/I | B/I |2| X? |X| ! |GA-DR4/98 |TGUI9660 | B/I | B/I |4| X? |X| |GA-DR2/PCI |TGUI9660 | B/I | B/I |2| X | | |GA-DR4/PCI |TGUI9660 | B/I | B/I |4| X | | ! |GA-DRV2/98 |TGUI9680 | B/I | B/I |2| X? |X| ! |GA-DRV4/98 |TGUI9680 | B/I | B/I |4| X |X| |GA-DRV2/PCI |TGUI9680 | B/I | B/I |2| X | | |GA-DRV4/PCI |TGUI9680 | B/I | B/I |4| X | | |GA-DRTV2/98PCI |TGUI9682 | B/I | B/I |2| X | | *************** *** 305,312 **** |GA-PGDX4/98PCI |S3-ViRGE/DX | B/I | B/I |4| X | | |GA-PG3D2/98PCI |S3-ViRGE | B/I | B/I |2| X | | |GA-PG3D4/98PCI |S3-ViRGE | B/I | B/I |4| X | | ! |GA-PG3DVX4/98PCI |S3-ViRGE/VX | | |4| X | | ! |GA-PG3DVX8/98PCI |S3-ViRGE/VX | | |8| X | | +------------------------+---------------+-------+--------+-+-------+-+ --- 321,331 ---- |GA-PGDX4/98PCI |S3-ViRGE/DX | B/I | B/I |4| X | | |GA-PG3D2/98PCI |S3-ViRGE | B/I | B/I |2| X | | |GA-PG3D4/98PCI |S3-ViRGE | B/I | B/I |4| X | | ! |GA-PG3DVX4/98PCI |S3-ViRGE/VX | B/I | B/I |4| X | | ! |GA-PG3DVX8/98PCI |S3-ViRGE/VX | B/I | B/I |8| X | | ! |GA-PII8/PCI |PERMEDIA2 | | |8| X | | ! |GA-RUSH6/PCI |Promotion AT25 | | |4| X | | ! | |Voodoo RUSH | | |2| | | +------------------------+---------------+-------+--------+-+-------+-+ *************** *** 319,324 **** --- 338,344 ---- MIDORI +------------------------+---------------+-------+--------+-+-------+-+ + |GAB-981 |CLGD5428 | B/I | B/I |1| ? |X| |GAB-982-00 |CLGD5428 | B/I | B/I |1| ? |X| |GAB-983-00 |CLGD5428 | B/I | B/I |1| ? |X| +------------------------+---------------+-------+--------+-+-------+-+ *************** *** 338,344 **** +------------------------+---------------+-------+--------+-+-------+-+ ! Hachinohe +------------------------+---------------+-------+--------+-+-------+-+ |HighResoStation(note) | | | | | ? | | +------------------------+---------------+-------+--------+-+-------+-+ --- 358,364 ---- +------------------------+---------------+-------+--------+-+-------+-+ ! Hachinohe Firmware System(HFS) +------------------------+---------------+-------+--------+-+-------+-+ |HighResoStation(note) | | | | | ? | | +------------------------+---------------+-------+--------+-+-------+-+ *************** *** 346,353 **** Sumitomo Kinzoku +------------------------+---------------+-------+--------+-+-------+-+ ! |MGA98-PCI/2 |MGA2 | | |2| X | | ! |MGA98-PCI/4 |MGA2 | | |4| X | | +------------------------+---------------+-------+--------+-+-------+-+ ! /* $XFree86: xc/programs/Xserver/hw/xfree98/doc/VideoBoard98,v 3.3.4.4 1997/07/31 09:18:09 dawes Exp $ */ --- 366,382 ---- Sumitomo Kinzoku +------------------------+---------------+-------+--------+-+-------+-+ ! |MGA98 W2 |MGA II | | |2| X | | ! |MGA98 W3 |MGA II | | |3| X | | ! |MGA98 3D,3DH |MGA II | | | | X | | ! |MGA98-PCI/2 |MGA II | | |2| X | | ! |MGA98-PCI/4 |MGA II | | |4| X | | +------------------------+---------------+-------+--------+-+-------+-+ ! Force ! +------------------------+---------------+-------+--------+-+-------+-+ ! |WinFrame |TMS34020 | | | | X | | ! |WinFrame928 |S3-928 | | |2| ? | | ! +------------------------+---------------+-------+--------+-+-------+-+ ! ! /* $XFree86: xc/programs/Xserver/hw/xfree98/doc/VideoBoard98,v 3.3.4.6 1998/02/21 06:07:12 robin Exp $ */ *** ./programs/Xserver/hw/xfree98/vga256/Imakefile@@/PUBLIC-LATEST Sun Jul 20 14:19:06 1997 --- xc/programs/Xserver/hw/xfree98/vga256/Imakefile Fri Mar 6 14:12:55 1998 *************** *** 1,10 **** ! XCOMM $TOG: Imakefile /main/11 1997/07/20 14:19:08 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree98/vga256/Imakefile,v 3.10.2.1 1997/05/03 09:50:37 dawes Exp $ #include <Server.tmpl> #define IHaveSubdirs --- 1,10 ---- ! XCOMM $TOG: Imakefile /main/12 1998/03/06 14:14:32 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree98/vga256/Imakefile,v 3.10.2.3 1998/02/15 16:09:47 hohndel Exp $ #include <Server.tmpl> #define IHaveSubdirs *************** *** 58,72 **** TGUIDONES = trident/DONE #endif SUBDIRS = $(GANBWAPSUBDIRS) $(NEC480SUBDIRS) $(NKVNECSUBDIRS) \ $(WABSSUBDIRS) $(WABEPSUBDIRS) $(WSNASUBDIRS) $(TGUISUBDIRS) \ ! drivers SRCS = $(GANBWAPSRCS) $(NEC480SRCS) $(NKVNECSRCS) $(WABSSRCS) \ ! $(WABEPSRCS) $(WSNASRCS) $(TGUISRCS) OBJS = $(GANBWAPOBJS) $(NEC480OBJS) $(NKVNECOBJS) $(WABSOBJS) \ ! $(WABEPOBJS) $(WSNAOBJS) $(TGUIOBJS) DONES = $(GANBWAPDONES) $(NEC480DONES) $(NKVNECDONES) $(WABSDONES) \ ! $(WABEPDONES) $(WSNADONES) $(TGUIDONES) INCLUDES = -I$(XF86SRC)/vga256/vga -I$(XF86COMSRC) -I$(XF86OSSRC) \ -I$(SERVERSRC)/include -I$(XINCLUDESRC) --- 58,86 ---- TGUIDONES = trident/DONE #endif + #if XF98MGAServer + MGASUBDIRS = mga + MGASRCS = mga/?*.c + MGAOBJS = mga/?*.o + MGADONES = mga/DONE + #endif + + #if XF98SVGAServer + SVGASUBDIRS = svga + SVGASRCS = svga/?*.c + SVGAOBJS = svga/?*.o + SVGADONES = svga/DONE + #endif + SUBDIRS = $(GANBWAPSUBDIRS) $(NEC480SUBDIRS) $(NKVNECSUBDIRS) \ $(WABSSUBDIRS) $(WABEPSUBDIRS) $(WSNASUBDIRS) $(TGUISUBDIRS) \ ! $(MGASUBDIRS) $(SVGASUBDIRS) drivers SRCS = $(GANBWAPSRCS) $(NEC480SRCS) $(NKVNECSRCS) $(WABSSRCS) \ ! $(WABEPSRCS) $(WSNASRCS) $(TGUISRCS) $(MGASRCS) $(SVGASRCS) OBJS = $(GANBWAPOBJS) $(NEC480OBJS) $(NKVNECOBJS) $(WABSOBJS) \ ! $(WABEPOBJS) $(WSNAOBJS) $(TGUIOBJS) $(MGAOBJS) $(SVGAOBJS) DONES = $(GANBWAPDONES) $(NEC480DONES) $(NKVNECDONES) $(WABSDONES) \ ! $(WABEPDONES) $(WSNADONES) $(TGUIDONES) $(MGADONES) $(SVGADONES) INCLUDES = -I$(XF86SRC)/vga256/vga -I$(XF86COMSRC) -I$(XF86OSSRC) \ -I$(SERVERSRC)/include -I$(XINCLUDESRC) *************** *** 81,107 **** $(DONES): $(SUBDIRS) #endif ! #if XF98GANBWAPServer ! ConfigTargetNoDepend(vga256Conf,$(ICONFIGFILES),cvga256.sh,cirrus) #endif - #if XF98WSNAServer - ConfigTargetNoDepend(vga256Conf,$(ICONFIGFILES),cvga256.sh,cirrus) - #endif #if XF98NEC480Server ! ConfigTargetNoDepend(nec480Conf,$(ICONFIGFILES),cnec480.sh,nec480) #endif - #if XF98NKVNECServer - ConfigTargetNoDepend(vga256Conf,$(ICONFIGFILES),cvga256.sh,cirrus) - #endif - #if XF98WABSServer - ConfigTargetNoDepend(vga256Conf,$(ICONFIGFILES),cvga256.sh,cirrus) - #endif - #if XF98WABEPServer - ConfigTargetNoDepend(vga256Conf,$(ICONFIGFILES),cvga256.sh,cirrus) - #endif #if XF98TGUIServer ! ConfigTargetNoDepend(tguiConf,$(ICONFIGFILES),ctgui.sh,tvga8900) #endif #ifdef OS2Architecture all:: DONE --- 95,113 ---- $(DONES): $(SUBDIRS) #endif ! #if XF98GANBWAPServer || XF98WSNAServer || XF98NKVNECServer || \ ! XF98WABSServer || XF98WABEPServer || XF98SVGAServer ! ConfigTargetNoDepend(vga256Conf,$(ICONFIGFILES),cvga256.SHsuf,cirrus) #endif #if XF98NEC480Server ! ConfigTargetNoDepend(nec480Conf,$(ICONFIGFILES),cnec480.SHsuf,nec480) #endif #if XF98TGUIServer ! ConfigTargetNoDepend(tguiConf,$(ICONFIGFILES),ctgui.SHsuf,tvga8900) #endif + #if XF98MGAServer + ConfigTargetNoDepend(mgaConf,$(ICONFIGFILES),cmga.SHsuf,mga) + #endif #ifdef OS2Architecture all:: DONE *************** *** 128,133 **** --- 134,145 ---- #if XF98TGUIServer NormalDepLibraryTarget(trident,$(TGUISUBDIRS) drivers $(TGUIDONES),?*.o) #endif + #if XF98MGAServer + NormalDepLibraryTarget(mga,$(MGASUBDIRS) drivers $(MGADONES),?*.o) + #endif + #if XF98SVGAServer + NormalDepLibraryTarget(vga256,$(SVGASUBDIRS) drivers $(SVGADONES),?*.o) + #endif #else #if XF98GANBWAPServer NormalDepLibraryTarget(ganbwap,$(GANBWAPSUBDIRS) drivers $(GANBWAPDONES),$(GANBWAPOBJS)) *************** *** 150,156 **** --- 162,174 ---- #if XF98TGUIServer NormalDepLibraryTarget(trident,$(TGUISUBDIRS) drivers $(TGUIDONES),$(TGUIOBJS)) #endif + #if XF98MGAServer + NormalDepLibraryTarget(mga,$(MGASUBDIRS) drivers $(MGADONES),$(MGAOBJS)) #endif + #if XF98SVGAServer + NormalDepLibraryTarget(vga256,$(SVGASUBDIRS) drivers $(SVGADONES),$(SVGAOBJS)) + #endif + #endif NormalLibraryObjectRule() *************** *** 160,172 **** InstallLinkKitLibrary(nec480,$(XF98LINKKITDIR)/drivers98) InstallLinkKitLibrary(nkvnec,$(XF98LINKKITDIR)/drivers98) InstallLinkKitLibrary(trident,$(XF98LINKKITDIR)/drivers98) InstallLinkKitLibrary(wabep,$(XF98LINKKITDIR)/drivers98) InstallLinkKitLibrary(wabs,$(XF98LINKKITDIR)/drivers98) InstallLinkKitLibrary(wsna,$(XF98LINKKITDIR)/drivers98) #ifndef DontInstallPC98Version ! InstallLinkKitNonExecFile(cvga256.sh,$(XF98LINKKITDIR)) #endif ! InstallLinkKitNonExecFile(cnec480.sh,$(XF98LINKKITDIR)) ! InstallLinkKitNonExecFile(ctgui.sh,$(XF98LINKKITDIR)) DependSubdirs($(SUBDIRS)) --- 178,193 ---- InstallLinkKitLibrary(nec480,$(XF98LINKKITDIR)/drivers98) InstallLinkKitLibrary(nkvnec,$(XF98LINKKITDIR)/drivers98) InstallLinkKitLibrary(trident,$(XF98LINKKITDIR)/drivers98) + InstallLinkKitLibrary(mga,$(XF98LINKKITDIR)/drivers98) + InstallLinkKitLibrary(vga256,$(XF98LINKKITDIR)/drivers98) InstallLinkKitLibrary(wabep,$(XF98LINKKITDIR)/drivers98) InstallLinkKitLibrary(wabs,$(XF98LINKKITDIR)/drivers98) InstallLinkKitLibrary(wsna,$(XF98LINKKITDIR)/drivers98) #ifndef DontInstallPC98Version ! InstallLinkKitNonExecFile(cvga256.SHsuf,$(XF98LINKKITDIR)) #endif ! InstallLinkKitNonExecFile(cnec480.SHsuf,$(XF98LINKKITDIR)) ! InstallLinkKitNonExecFile(ctgui.SHsuf,$(XF98LINKKITDIR)) ! InstallLinkKitNonExecFile(cmga.SHsuf,$(XF98LINKKITDIR)) DependSubdirs($(SUBDIRS)) *** /dev/null Tue Jun 30 11:51:28 1998 --- xc/programs/Xserver/hw/xfree98/vga256/cmga.cmd Fri Mar 6 14:13:04 1998 *************** *** 0 **** --- 1,39 ---- + /* $TOG: cmga.cmd /main/1 1998/03/06 14:14:41 kaleb $ */ + /* This is OS/2 Rexx, written for OS/2 to avoid need for secondary shell */ + /* $XFree86: xc/programs/Xserver/hw/xfree98/vga256/cmga.cmd,v 1.1.2.1 1998/02/01 16:42:17 robin Exp $ */ + /* + * This script generates vga256Conf.c + * + * usage: confvga256 driver1 driver2 ... + */ + '@echo off' + PARSE UPPER ARG all + + vgaconf = 'mgaConf.c' + + CALL LineOut vgaconf, '/*' + CALL LineOut vgaconf, ' * This file is generated automatically -- DO NOT EDIT' + CALL LineOut vgaconf, ' */' + CALL LineOut vgaconf, ' ' + CALL LineOut vgaconf, '#include "xf86.h"' + CALL LineOut vgaconf, '#include "vga.h"' + CALL LineOut vgaconf, ' ' + CALL LineOut vgaconf, 'extern vgaVideoChipRec' + + DO i=1 TO WORDS(all) + arg = WORD(all,i) + IF i = WORDS(all) THEN + CALL LineOut vgaconf, ' 'arg';' + ELSE + CALL LineOut vgaconf, ' 'arg',' + END + CALL LineOut vgaconf, 'vgaVideoChipPtr vgaDrivers[] =' + CALL LineOut vgaconf, '{' + DO i=1 TO WORDS(all) + arg = WORD(all,i) + CALL LineOut vgaconf, ' &'arg',' + END + CALL LineOut vgaconf, ' NULL' + CALL LineOut vgaconf, '};' + CALL LineOut vgaconf + EXIT *** /dev/null Tue Jun 30 11:51:29 1998 --- xc/programs/Xserver/hw/xfree98/vga256/cmga.sh Fri Mar 6 14:13:07 1998 *************** *** 0 **** --- 1,43 ---- + #!/bin/sh + # $TOG: cmga.sh /main/1 1998/03/06 14:14:45 kaleb $ + + + + + # $XFree86: xc/programs/Xserver/hw/xfree98/vga256/cmga.sh,v 1.1.2.1 1998/02/01 16:42:18 robin Exp $ + # + # This script generates vga256Conf.c + # + # usage: confvga256.sh driver1 driver2 ... + # + # $TOG: cmga.sh /main/1 1998/03/06 14:14:45 kaleb $ + + VGACONF=./mgaConf.c + + cat > $VGACONF <<EOF + /* + * This file is generated automatically -- DO NOT EDIT + */ + + #include "xf86.h" + #include "vga.h" + + extern vgaVideoChipRec + EOF + Args="`echo $* | tr '[a-z]' '[A-Z]'`" + set - $Args + while [ $# -gt 1 ]; do + echo " $1," >> $VGACONF + shift + done + echo " $1;" >> $VGACONF + cat >> $VGACONF <<EOF + + vgaVideoChipPtr vgaDrivers[] = + { + EOF + for i in $Args; do + echo " &$i," >> $VGACONF + done + echo " NULL" >> $VGACONF + echo "};" >> $VGACONF *** ./programs/Xserver/hw/xfree98/vga256/drivers/Imakefile@@/PUBLIC-LATEST Sun Jul 20 13:53:14 1997 --- xc/programs/Xserver/hw/xfree98/vga256/drivers/Imakefile Fri Mar 6 14:13:16 1998 *************** *** 1,9 **** ! XCOMM $TOG: Imakefile /main/8 1997/07/20 13:53:16 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree98/vga256/drivers/Imakefile,v 3.8 1996/12/23 07:08:31 dawes Exp $ #include <Server.tmpl> #define IHaveSubdirs --- 1,9 ---- ! XCOMM $TOG: Imakefile /main/9 1998/03/06 14:14:54 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree98/vga256/drivers/Imakefile,v 3.8.2.1 1998/02/01 16:05:34 robin Exp $ #include <Server.tmpl> #define IHaveSubdirs *************** *** 49,56 **** TGUIOBJS = trident/tvga89_drv.o #endif SUBDIRS = $(GANBWAPDIR) $(NEC480DIR) $(NKVNECDIR) $(WABSDIR) $(WABEPDIR) \ ! $(WSNADIR) $(TGUIDIR) #if XF98GANBWAPServer NormalDepLibraryTarget(driverganbwap,$(GANBWAPDIR) $(GANBWAPOBJS),$(GANBWAPOBJS)) --- 49,68 ---- TGUIOBJS = trident/tvga89_drv.o #endif + #if XF98MGAServer + MGADIR = mga + MGASRCS = mga/?*.c + MGAOBJS = mga/mga_drv.o + #endif + + #if XF98SVGAServer + SVGADIR = svga + SVGASRCS = svga/?*.c + SVGAOBJS = svga/cir_drv.o + #endif + SUBDIRS = $(GANBWAPDIR) $(NEC480DIR) $(NKVNECDIR) $(WABSDIR) $(WABEPDIR) \ ! $(WSNADIR) $(TGUIDIR) $(MGADIR) $(SVGADIR) #if XF98GANBWAPServer NormalDepLibraryTarget(driverganbwap,$(GANBWAPDIR) $(GANBWAPOBJS),$(GANBWAPOBJS)) *************** *** 72,77 **** --- 84,95 ---- #endif #if XF98TGUIServer NormalDepLibraryTarget(drivertrident,$(TGUIDIR) $(TGUIOBJS),$(TGUIOBJS)) + #endif + #if XF98MGAServer + NormalDepLibraryTarget(drivermga,$(MGADIR) $(MGAOBJS),$(MGAOBJS)) + #endif + #if XF98SVGAServer + NormalDepLibraryTarget(driversvga,$(SVGADIR) $(SVGAOBJS),$(SVGAOBJS)) #endif NormalLibraryObjectRule() *** ./programs/Xserver/hw/xfree98/vga256/drivers/cir_pc98.c@@/PUBLIC-LATEST Sat Oct 19 18:30:59 1996 --- xc/programs/Xserver/hw/xfree98/vga256/drivers/cir_pc98.c Fri Mar 6 14:13:21 1998 *************** *** 1,4 **** ! /* $XFree86: xc/programs/Xserver/hw/xfree98/vga256/drivers/cir_pc98.c,v 3.6 1996/06/29 09:09:54 dawes Exp $ */ #include "X.h" #include "input.h" --- 1,4 ---- ! /* $XFree86: xc/programs/Xserver/hw/xfree98/vga256/drivers/cir_pc98.c,v 3.6.4.3 1998/02/24 13:54:34 hohndel Exp $ */ #include "X.h" #include "input.h" *************** *** 38,43 **** --- 38,443 ---- #endif #endif + #ifdef PC98_SVGA + static void init_aile( void ); + static void enter_aile( void ); + static void leave_aile( void ); + + static unsigned short s1735; + static char c1737; + static char c1728; + static int hsync31=0; + + static void init_aile( void ) + { + char c; + unsigned short s; + int i; + #if 0 + static unsigned short x[28]={0x0001,0x0038,0x0039,0x0030,0x002c, + 0x002d,0x002e,0x0020,0x0021,0x0022, + 0x0023,0x0032,0x0026,0x0026,0x0024, + 0x0025,0x0034,0x0035,0x0001,0x0011, + 0x0013,0x0000,0x0010,0x0012,0x0028, + 0x0029,0x002a,0x8031 + }; + #endif + + static unsigned char regs[0x100] = { + 0x7f, 0x63, 0x64, 0x82, 0x6b, 0x1b, 0x72, 0xf0, /* 00-07 */ + 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x0e, 0x10, /* 08-0f */ + 0x58, 0xac, 0x57, 0x64, 0x00, 0x58, 0x72, 0xe3, /* 10-17 */ + 0xff, 0x00, 0x00, 0x22, 0x04, 0x00, 0xe1, 0xe0, /* 18-1f */ + 0xdf, 0xde, 0x03, 0x00, 0x80, 0x66, 0x20, 0x40, /* 20-27 */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 28-2f */ + 0x00, 0x00, 0x00, 0x00, 0x50, 0x00, 0x24, 0x3c, /* 30-37 */ + 0xdf, 0x00, 0x20, 0x60, 0x71, 0x3f, 0x00, 0x00, /* 38-3f */ + 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, /* 40-47 */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 48-4f */ + 0x51, 0xa9, 0x00, 0x00, 0x30, 0x80, 0x27, 0xdf, /* 50-57 */ + 0x28, 0x40, 0x45, 0x00, 0x02, 0x00, 0x00, 0x00, /* 58-5f */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 60-67 */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 68-6f */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 70-77 */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 78-7f */ + 0x01, 0x11, 0x11, 0x29, 0x21, 0xc0, 0xc1, 0x70, /* 80-87 */ + 0x66, 0x60, 0x00, 0x00, 0x77, 0x85, 0x04, 0x00, /* 88-8f */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 90-97 */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 98-9f */ + 0x7b, 0x73, 0x3f, 0x43, 0x73, 0x73, 0x37, 0x3e, /* a0-a7 */ + 0x67, 0x67, 0x31, 0x0f, 0x09, 0xc7, 0xfe, 0x94, /* a8-af */ + 0x6f, 0x12, 0x59, 0x0a, 0x00, 0x00, 0x00, 0x00, /* b0-b7 */ + 0x00, 0x00, 0x00, 0x56, 0x00, 0x00, 0x10, 0x00, /* b8-bf */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* c0-c7 */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* c8-cf */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* d0-d7 */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* d8-df */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* e0-e7 */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* e8-ef */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* f0-f7 */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* f8-ff */ + }; + + ErrorF("\n*** called init_aile\n"); + + #if 1 + outb(0x3C4, 0x22); + outb(0x3C5, 0xFF); + + + c=inb(0x3cc); + outb(0x3c2, c & 0xfd); + outw(0x3C4, 0x1206); /* unlock cirrus special */ + for (i=0;i<0x100;i++) { + outb(vgaIOBase + 4,i); + outb(vgaIOBase + 5,regs[i]); + } + outb(0x3c4,0x07); + outb(0x3c5,0xc1); + outw(0x3ce,0x0010); + outw(0x3ce,0x0012); + outw(0x3ce,0x4014); + outw(0x3ce,0x0616); + outw(0x3ce,0x0217); + outw(0x3ce,0x002c); + outw(0x3ce,0xd22d); + outw(0x3ce,0x8031); + outw(0x3ce,0x0d32); + outw(0x3ce,0x0433); + #endif + + + /* + c=inb(0x3cc); + outb(0x3c2, c | 0x01); + */ + + /* hsync31 = inb(0x9a8) & 0x01; */ + vgaIOBase = (inb(0x3CC) & 0x01) ? 0x3D0 : 0x3B0; + + #if 1 + outw(0x3C4, 0x1206); /* unlock cirrus special */ + + /* unlock LED */ + outb(0x3C4, 0x2d); + c=inb(0x3c5); + outb(0x3c5, c | 0x80); + + #if 1 + for (i=0;i<0x100;i++) { + outb(vgaIOBase + 4,i); + outb(vgaIOBase + 5,regs[i]); + } + outb(0x3c4,0x07); + outb(0x3c5,0xc1); + outw(0x3ce,0x0010); + outw(0x3ce,0x0012); + outw(0x3ce,0x4014); + outw(0x3ce,0x0616); + outw(0x3ce,0x0217); + outw(0x3ce,0x002c); + outw(0x3ce,0xd22d); + outw(0x3ce,0x8031); + outw(0x3ce,0x0d32); + outw(0x3ce,0x0433); + #endif + #endif + + ErrorF("3B4"); + for(i=0;i<0x100;i++) { + outb(0x3b4,i); + if ( i%8 == 0 ) + ErrorF("\n0x%03x:%04x",i,inb(0x3b5)); + else + ErrorF(" %04x",inb(0x3b5)); + } + ErrorF("\n"); + + ErrorF("3BA:%04x\n",inb(0x3ba)); + + ErrorF("3C0"); + for(i=0;i<0x15;i++) { + outb(0x3c0,i); + if ( i%8 == 0 ) + ErrorF("\n0x%03x:%04x",i,inb(0x3c1)); + else + ErrorF(" %04x",inb(0x3c1)); + } + ErrorF("\n"); + + ErrorF("3C2:%04x\n",inb(0x3c2)); + ErrorF("3C3:%04x\n",inb(0x3c3)); + + ErrorF("3C4"); + for(i=0;i<0x40;i++) { + outb(0x3c4,i); + if ( i%8 == 0 ) + ErrorF("\n0x%03x:%04x",i,inb(0x3c5)); + else + ErrorF(" %04x",inb(0x3c5)); + } + ErrorF("\n"); + + ErrorF("3C6:%04x\n",inb(0x3c6)); + ErrorF("3C7:%04x\n",inb(0x3c7)); + ErrorF("3C8:%04x\n",inb(0x3c8)); + ErrorF("3C9:%04x\n",inb(0x3c9)); + ErrorF("3CA:%04x\n",inb(0x3ca)); + ErrorF("3CC:%04x\n",inb(0x3cc)); + ErrorF("3CD:%04x\n",inb(0x3cd)); + + ErrorF("3CE"); + for(i=0;i<0x40;i++) { + outb(0x3ce,i); + if ( i%8 == 0 ) + ErrorF("\n0x%03x:%04x",i,inb(0x3cf)); + else + ErrorF(" %04x",inb(0x3cf)); + } + ErrorF("\n"); + + ErrorF("3D4"); + for(i=0;i<0x100;i++) { + outb(0x3d4,i); + if ( i%8 == 0 ) + ErrorF("\n0x%03x:%04x",i,inb(0x3d5)); + else + ErrorF(" %04x",inb(0x3d5)); + } + ErrorF("\n"); + + ErrorF("3DA:%04x\n",inb(0x3da)); + + /* unlock LED */ + outb(0x3C4, 0x2d); + c=inb(0x3c5); + outb(0x3c5, c & 0x7f); + + outw(0x3C4, 0x0006); /* lock cirrus special */ + + #if 0 + for(i=0;i<28;i++) outw(0x3ce,x[i]); + #endif + + #if 0 + outw(0x3c4, 0x1206); + outb(0x3ce, 0x09); + c1728 = inb(0x3cf); + outb(0x3cf, 0xf0); + outw(0x3c4, 0x3d13); + outw(0x3ce, (c1728 << 8) | 0x09); + outb(0x3c4, 0x12); + c = inb(0x3c5); + c |= 0x02; + outb(0x3c5, c); + outb(0x3c4, 0x12); + c = inb(0x3c5); + c &= 0xfe; + outb(0x3c5, c); + outb(0x3c8, 0x00); + outb(0x3c9, 0x00); + outb(0x3c9, 0x00); + outb(0x3c9, 0x00); + outb(0x3c8, 0xff); + outb(0x3c9, 0x3f); + outb(0x3c9, 0x3f); + outb(0x3c9, 0x3f); + outb(0x3c4, 0x12); + c = inb(0x3c5); + c &= 0xfd; + outb(0x3c5, c); + #endif + } + + static void enter_aile( void ) + { + + char c; + ErrorF("\n*** called enter_aile\n"); + + outb(0x3d4, 0x24); + c = inb(0x3d5); + if(c == 0x80){ + c = inb(0x3c1); + outb(0x3c0, c); + } + + outb(0xfac, 0x02); + + c=inb(0x3cc); + outb(0x3c2, c & 0xfd); + + outb(0x68, 0x0e); + outb(0x6a,0x07); + outb(0x6a,0x8f); + outb(0x6a,0x06); + + /* outb(0x9a8, 0x00); */ + + outb(0x6a, 0x07); + + c=inb(0x3cc); + outb(0x3c2, c | 0x02); + + /* ueno UENO*/ + outb(0x6a, 0xef); + outb(0x6a, 0x01); + outb(0x6a, 0x04); + outb(0x6a, 0x40); + outb(0x6a, 0x20); + outb(0x6a, 0x68); + outb(0x6a, 0x06); + outb(0x5f, 0x00); + outb(0x5f, 0x00); + outb(0x5f, 0x00); + + outb(0x7c, 0x00); + outb(0xa4, 0x00); + outb(0xa6, 0x00); + outb(0x5f, 0x00); + outb(0x5f, 0x00); + outb(0x5f, 0x00); + + + outw(0x3C4, 0x1206); /* unlock cirrus special */ + outb(0x3ce, 0x09); + c1728 = inb(0x3cf); + outb(0x3cf, 0xf0); + outw(0x3c4, 0x3d13); + outw(0x3ce, (c1728 << 8) | 0x09); + outb(0x3c4, 0x12); + c = inb(0x3c5); + c |= 0x02; + outb(0x3c5, c); + outb(0x3c4, 0x12); + c = inb(0x3c5); + c &= 0xfe; + outb(0x3c5, c); + outb(0x3c8, 0x00); + outb(0x3c9, 0x00); + outb(0x3c9, 0x00); + outb(0x3c9, 0x00); + outb(0x3c8, 0xff); + outb(0x3c9, 0x3f); + outb(0x3c9, 0x3f); + outb(0x3c9, 0x3f); + outb(0x3c4, 0x12); + c = inb(0x3c5); + c &= 0xfd; + outb(0x3c5, c); + + outb(0x3b4, 0x3c); + outb(0x3b5, inb(0x3b5) & 0xef); + outb(0x3b4, 0x1a); + outb(0x3b5, inb(0x3b5) & 0xf3); + #if 0 + + ErrorF("called enter_aile\n"); + while((inb(0x60) & 0x04) == 0) ; /* FIFO empty */ + outb(0x62, 0x00); /* RESET */ + while((inb(0xa0) & 0x04) == 0) ; /* FIFO empty */ + outb(0xa2, 0x00); /* RESET */ + + outb(0x6A,0x00); /* Do 8 colors mode */ + outb(0x7C,0x00); /* GRCG OFF */ + + + while (!(inb(0x60) & 0x20)) ; /* V-SYNC wait */ + outb(0x62, 0xc); /* text off */ + outb(0xA2, 0xc); /* graphics off */ + + outb(0x68, 0x0e); + outb(0x6a, 0x07); + outb(0x6a, 0x8f); + outb(0x6a, 0x20); + outb(0x6a, 0x68); + outb(0x6a, 0x06); + outb(0x9a8, 0x00); + + outw(0x08f0, 0x0052); + outb(0x5f, 0x00); + s1735 = inw(0x8f2); + outw(0x08f2, (s1735 | 0x0080)); + outb(0x3b4, 0x80); + c1737 = inb(0x3b5); + outb(0x3b5, (c1737 & 0xfe)); + outb(0x3ce, 0x0e); + c = inb(0x3cf); + outb(0x3cf, (c & 0x04)); /* 0x06 */ + + outw(0x8f0, 0x0052); + outb(0x5f, 0x00); + outw(0x8f2, s1735); + #endif + } + static void leave_aile( void ) + { + char c; + ErrorF("\n*** called leave_aile\n"); + + c=inb(0x3cc); + outb(0x3c2, c | 0x02); + + outb(0xfac, 0x00); + + outb(0x68, 0x0f); + + outb(0x6a, 0x07); + outb(0x6a, 0x8e); + outb(0x6a, 0x06); + + /*if(hsync31) outb(0x9a8, 0x01);*/ + outb(0x68, 0x0f); + + c=inb(0x3cc); + outb(0x3c2, c & 0xfd); + + outb(0x6a, 0x07); + outb(0x6a, 0x8e); + outb(0x6a, 0x06); + + ErrorF("called leave_aile\n"); + outb(0x68, 0x0f); + outb(0x6a, 0x07); + outb(0x6a, 0x8e); + outb(0x6a, 0x21); + outb(0x6a, 0x69); + outb(0x6a, 0x06); + outb(0x9a8, 0x01); + + _outw(0x8f0, 0x0052); + _outb(0x5f, 0x0); + _outw(0x8f2, s1735); + + outb(0x3ce, 0x0e); + c = inb(0x3cf); + outb(0x3cf, c & 0xf9); + outw(0x08f0,0x0052); + outb(0x5f,0x0); + outw(0x08f2, s1735); + } + #endif + #ifdef PC98_WSNA static void init_wsna( void ); static void enter_wsna( void ); *************** *** 531,537 **** --- 931,939 ---- _outb(0xfaa, 0x03); _outb(0xfab, 0x03); _outb(0x5f, 0); + #if 0 while(_inw(0x0c42) & 0x0400) ; + #endif _outb(0x904 , 0x01); _outb(0x102, 0x01); outb(0x3c2, 0x01); *************** *** 586,591 **** --- 988,996 ---- #if defined(PC98_GANB_WAP) || defined(PC98_WAB) init_wabs_ganbwap(); #endif + #ifdef PC98_SVGA + init_aile(); + #endif #ifdef PC98_WSNA init_wsna(); #endif *************** *** 599,610 **** --- 1004,1020 ---- init = 1; } + #ifndef PC98_SVGA vgaIOBase = 0x3d0; + #endif /* switch normal -> X */ #ifdef PC98_GANB_WAP enter_ganbwap(); #endif + #ifdef PC98_SVGA + enter_aile(); + #endif #ifdef PC98_WSNA enter_wsna(); #endif *************** *** 632,637 **** --- 1042,1050 ---- #endif #ifdef PC98_WSNA _outb(0x40E3,0xFA); /* WSN-A2F -> normal */ + #endif + #ifdef PC98_SVGA + leave_aile(); #endif #ifdef PC98_NKVNEC leave_nkvnec(); *** /dev/null Tue Jun 30 11:51:34 1998 --- xc/programs/Xserver/hw/xfree98/vga256/drivers/mga/Imakefile Fri Mar 6 14:13:33 1998 *************** *** 0 **** --- 1,69 ---- + XCOMM $TOG: Imakefile /main/1 1998/03/06 14:15:11 kaleb $ + + + + + XCOMM $XFree86: xc/programs/Xserver/hw/xfree98/vga256/drivers/mga/Imakefile,v 1.1.2.3 1998/02/15 16:09:47 hohndel Exp $ + XCOMM + XCOMM This is an Imakefile for the MGA driver. + XCOMM + + #include <Server.tmpl> + + SRCS = mga_driver.c mga_hwcurs.c mga_dac3026.c mga_dac1064.c \ + mga_storm8.c mga_storm16.c mga_storm24.c mga_storm32.c mga_xaarepl.c + OBJS = mga_driver.o mga_hwcurs.o mga_dac3026.o mga_dac1064.o \ + mga_storm8.o mga_storm16.o mga_storm24.o mga_storm32.o mga_xaarepl.o + + #if XF86LinkKit + INCLUDES = -I. -I../../../include -I../../../include/X11 -I../.. + #else + INCLUDES = -I. -I$(XF86COMSRC) -I$(XF86HWSRC) -I$(XF86OSSRC) \ + -I$(SERVERSRC)/mfb -I$(SERVERSRC)/mi \ + -I$(SERVERSRC)/cfb -I$(XF86SRC)/vga256/vga -I$(XF86SRC)/xaa \ + -I$(FONTINCSRC) -I$(SERVERSRC)/include -I$(XINCLUDESRC) \ + -I$(XF86SRC)/vga256/enhanced + #endif + + DEFINES = -DPC98 -DPC98_MGA + #if MakeHasPosixVariableSubstitutions + SubdirLibraryRule($(OBJS)) + #endif + NormalLibraryObjectRule() + NormalAsmObjectRule() + NormalRelocatableTarget(mga_drv, $(OBJS)) + + ObjectFromSpecialSource(mga_storm8, mga_storm, -DPSZ=8) + ObjectFromSpecialSource(mga_storm16, mga_storm, -DPSZ=16) + ObjectFromSpecialSource(mga_storm24, mga_storm, -DPSZ=24) + ObjectFromSpecialSource(mga_storm32, mga_storm, -DPSZ=32) + + #if !XF86LinkKit + LinkSourceFile(README,$(XF86SRC)/vga256/drivers/mga) + LinkSourceFile(mga.h,$(XF86SRC)/vga256/drivers/mga) + LinkSourceFile(mga_bios.h,$(XF86SRC)/vga256/drivers/mga) + LinkSourceFile(mga_reg.h,$(XF86SRC)/vga256/drivers/mga) + LinkSourceFile(mga_driver.c,$(XF86SRC)/vga256/drivers/mga) + LinkSourceFile(mga_hwcurs.c,$(XF86SRC)/vga256/drivers/mga) + LinkSourceFile(mga_storm.c,$(XF86SRC)/vga256/drivers/mga) + LinkSourceFile(mga_macros.h,$(XF86SRC)/vga256/drivers/mga) + LinkSourceFile(mga_map.h,$(XF86SRC)/vga256/drivers/mga) + LinkSourceFile(mga_dac3026.c,$(XF86SRC)/vga256/drivers/mga) + LinkSourceFile(mga_dac1064.c,$(XF86SRC)/vga256/drivers/mga) + LinkSourceFile(mga_xaarepl.c,$(XF86SRC)/vga256/drivers/mga) + #endif + + InstallLinkKitNonExecFile(mga.h,$(XF98LINKKITDIR)/drivers98/vga256/mga) + InstallLinkKitNonExecFile(mga_bios.h,$(XF98LINKKITDIR)/drivers98/vga256/mga) + InstallLinkKitNonExecFile(mga_reg.h,$(XF98LINKKITDIR)/drivers98/vga256/mga) + InstallLinkKitNonExecFile(mga_driver.c,$(XF98LINKKITDIR)/drivers98/vga256/mga) + InstallLinkKitNonExecFile(mga_hwcurs.c,$(XF98LINKKITDIR)/drivers98/vga256/mga) + InstallLinkKitNonExecFile(mga_storm.c,$(XF98LINKKITDIR)/drivers98/vga256/mga) + InstallLinkKitNonExecFile(mga_map.h,$(XF98LINKKITDIR)/drivers98/vga256/mga) + InstallLinkKitNonExecFile(mga_macros.h,$(XF98LINKKITDIR)/drivers98/vga256/mga) + InstallLinkKitNonExecFile(mga_dac3026.c,$(XF98LINKKITDIR)/drivers98/vga256/mga) + InstallLinkKitNonExecFile(mga_dac1064.c,$(XF98LINKKITDIR)/drivers98/vga256/mga) + InstallLinkKitNonExecFile(mga_xaarepl.c,$(XF98LINKKITDIR)/drivers98/vga256/mga) + InstallLinkKitNonExecFile(Imakefile,$(XF98LINKKITDIR)/drivers98/vga256/mga) + + DependTarget() *** /dev/null Tue Jun 30 11:51:35 1998 --- xc/programs/Xserver/hw/xfree98/vga256/drivers/svga/Imakefile Fri Mar 6 14:13:38 1998 *************** *** 0 **** --- 1,129 ---- + XCOMM $TOG: Imakefile /main/1 1998/03/06 14:15:16 kaleb $ + + + + + + XCOMM $XFree86: xc/programs/Xserver/hw/xfree98/vga256/drivers/svga/Imakefile,v 1.1.2.1 1998/02/01 16:42:19 robin Exp $ + #include <Server.tmpl> + + SRCS = cir_driver.c cir_fill.c cir_blt.c cir_bltC.c cir_im.c cir_bank.s \ + cir_imblt.s cir_colexp.c cirFillSt.c cir_teblt8.c \ + cirFillRct.c cir_blitter.c cir_textblt.s cir_cursor.c \ + cir_blitmm.c cir_immm.c cir_tebltmm.c cir_span.s cir_alloc.c \ + /* cir_blt16.c */ cir_solid.c /* cir_line.c cir_seg.c cir_orect.c */ \ + /* cir_orect16.c cir_orect32.c linearline.c cir_fillLG.c cir_blitLG.c */ \ + cirrus_acl.c cirrus_aclm.c laguna_acl.c \ + cir_pc98.c + + OBJS = cir_driver.o cir_fill.o cir_blt.o cir_bltC.o cir_im.o cir_bank.o \ + cir_imblt.o cir_colexp.o cirFillSt.o cir_teblt8.o \ + cirFillRct.o cir_blitter.o cir_textblt.o cir_cursor.o \ + cir_blitmm.o cir_immm.o cir_tebltmm.o cir_span.o cir_alloc.o \ + /* cir_blt16.o */ cir_solid.o /* cir_line.o cir_seg.o cir_orect.o */ \ + /* cir_orect16.o cir_orect32.o linearline.o cir_fillLG.o cir_blitLG.o */ \ + cirrus_acl.o cirrus_aclm.o laguna_acl.o \ + cir_pc98.o + + DEFINES = -DPSZ=8 -DPC98 -DPC98_SVGA + + #if XF86LinkKit + INCLUDES = -I. -I../../../include -I../../../include/X11 -I../.. + #else + INCLUDES = -I. -I$(XF86COMSRC) -I$(XF86HWSRC) -I$(XF86OSSRC) \ + -I$(SERVERSRC)/mfb -I$(SERVERSRC)/mi \ + -I$(SERVERSRC)/cfb -I$(XF86SRC)/vga256/vga -I$(XF86SRC)/xaa \ + -I$(FONTINCSRC) -I$(SERVERSRC)/include -I$(XINCLUDESRC) \ + -I../../svga + #endif + + #if MakeHasPosixVariableSubstitutions + SubdirLibraryRule($(OBJS)) + #endif + NormalLibraryObjectRule() + NormalAsmObjectRule() + + NormalRelocatableTarget(cir_drv, $(OBJS)) + + #if !XF86LinkKit + LinkSourceFile(cirBlitMM.h,$(XF86SRC)/vga256/drivers/cirrus) + LinkSourceFile(cirBlitter.h,$(XF86SRC)/vga256/drivers/cirrus) + LinkSourceFile(cirFillRct.c,$(XF86SRC)/vga256/drivers/cirrus) + LinkSourceFile(cirFillSt.c,$(XF86SRC)/vga256/drivers/cirrus) + LinkSourceFile(cir_alloc.c,$(XF86SRC)/vga256/drivers/cirrus) + LinkSourceFile(cir_alloc.h,$(XF86SRC)/vga256/drivers/cirrus) + LinkSourceFile(cir_bank.s,$(XF86SRC)/vga256/drivers/cirrus) + LinkSourceFile(cir_blitLG.c,$(XF86SRC)/vga256/drivers/cirrus) + LinkSourceFile(cir_blitLG.h,$(XF86SRC)/vga256/drivers/cirrus) + LinkSourceFile(cir_blitter.c,$(XF86SRC)/vga256/drivers/cirrus) + LinkSourceFile(cir_blt.c,$(XF86SRC)/vga256/drivers/cirrus) + LinkSourceFile(cir_blt16.c,$(XF86SRC)/vga256/drivers/cirrus) + LinkSourceFile(cir_bltC.c,$(XF86SRC)/vga256/drivers/cirrus) + LinkSourceFile(cir_colexp.c,$(XF86SRC)/vga256/drivers/cirrus) + LinkSourceFile(cir_cursor.c,$(XF86SRC)/vga256/drivers/cirrus) + LinkSourceFile(cir_driver.c,$(XF86SRC)/vga256/drivers/cirrus) + LinkSourceFile(cir_driver.h,$(XF86SRC)/vga256/drivers/cirrus) + LinkSourceFile(cir_fill.c,$(XF86SRC)/vga256/drivers/cirrus) + LinkSourceFile(cir_fillLG.c,$(XF86SRC)/vga256/drivers/cirrus) + LinkSourceFile(cir_im.c,$(XF86SRC)/vga256/drivers/cirrus) + LinkSourceFile(cir_imblt.s,$(XF86SRC)/vga256/drivers/cirrus) + LinkSourceFile(cir_inline.h,$(XF86SRC)/vga256/drivers/cirrus) + LinkSourceFile(cir_line.c,$(XF86SRC)/vga256/drivers/cirrus) + LinkSourceFile(cir_orect.c,$(XF86SRC)/vga256/drivers/cirrus) + LinkSourceFile(cir_solid.c,$(XF86SRC)/vga256/drivers/cirrus) + LinkSourceFile(cir_span.h,$(XF86SRC)/vga256/drivers/cirrus) + LinkSourceFile(cir_span.s,$(XF86SRC)/vga256/drivers/cirrus) + LinkSourceFile(cir_teblt8.c,$(XF86SRC)/vga256/drivers/cirrus) + LinkSourceFile(cir_textblt.s,$(XF86SRC)/vga256/drivers/cirrus) + LinkSourceFile(cirrus_acl.c,$(XF86SRC)/vga256/drivers/cirrus) + LinkSourceFile(laguna_acl.c,$(XF86SRC)/vga256/drivers/cirrus) + LinkSourceFile(linearline.c,$(XF86SRC)/vga256/drivers/cirrus) + LinkSourceFile(linearline.h,$(XF86SRC)/vga256/drivers/cirrus) + LinkSourceFile(cir_pc98.c,..) + #endif + + ObjectFromSpecialSource(cir_blitmm, cir_blitter, -DCIRRUS_MMIO) + ObjectFromSpecialSource(cir_immm, cir_im, -DCIRRUS_MMIO) + ObjectFromSpecialSource(cir_tebltmm, cir_teblt8, -DCIRRUS_MMIO) + ObjectFromSpecialSource(cir_seg, cir_line, -DPOLYSEGMENT) + ObjectFromSpecialSource(cir_orect16, cir_orect, -DPSZ=16) + ObjectFromSpecialSource(cir_orect32, cir_orect, -DPSZ=32) + ObjectFromSpecialSource(cirrus_aclm, cirrus_acl, -DMMIO) + + InstallLinkKitNonExecFile(cir_driver.c,$(XF98LINKKITDIR)/drivers98/vga256/svga) + InstallLinkKitNonExecFile(cir_driver.h,$(XF98LINKKITDIR)/drivers98/vga256/svga) + InstallLinkKitNonExecFile(cir_bank.s,$(XF98LINKKITDIR)/drivers98/vga256/svga) + InstallLinkKitNonExecFile(cir_fill.c,$(XF98LINKKITDIR)/drivers98/vga256/svga) + InstallLinkKitNonExecFile(cir_im.c,$(XF98LINKKITDIR)/drivers98/vga256/svga) + InstallLinkKitNonExecFile(cir_blt.c,$(XF98LINKKITDIR)/drivers98/vga256/svga) + InstallLinkKitNonExecFile(cir_bltC.c,$(XF98LINKKITDIR)/drivers98/vga256/svga) + InstallLinkKitNonExecFile(cir_imblt.s,$(XF98LINKKITDIR)/drivers98/vga256/svga) + InstallLinkKitNonExecFile(cir_textblt.s,$(XF98LINKKITDIR)/drivers98/vga256/svga) + InstallLinkKitNonExecFile(cir_span.s,$(XF98LINKKITDIR)/drivers98/vga256/svga) + InstallLinkKitNonExecFile(cir_colexp.c,$(XF98LINKKITDIR)/drivers98/vga256/svga) + InstallLinkKitNonExecFile(cirFillSt.c,$(XF98LINKKITDIR)/drivers98/vga256/svga) + InstallLinkKitNonExecFile(cir_solid.c,$(XF98LINKKITDIR)/drivers98/vga256/svga) + InstallLinkKitNonExecFile(cir_teblt8.c,$(XF98LINKKITDIR)/drivers98/vga256/svga) + InstallLinkKitNonExecFile(cirFillRct.c,$(XF98LINKKITDIR)/drivers98/vga256/svga) + InstallLinkKitNonExecFile(cir_cursor.c,$(XF98LINKKITDIR)/drivers98/vga256/svga) + InstallLinkKitNonExecFile(cir_blitter.c,$(XF98LINKKITDIR)/drivers98/vga256/svga) + InstallLinkKitNonExecFile(cir_blitLG.c,$(XF98LINKKITDIR)/drivers98/vga256/svga) + InstallLinkKitNonExecFile(cir_fillLG.c,$(XF98LINKKITDIR)/drivers98/vga256/svga) + InstallLinkKitNonExecFile(cir_alloc.c,$(XF98LINKKITDIR)/drivers98/vga256/svga) + InstallLinkKitNonExecFile(cir_blt16.c,$(XF98LINKKITDIR)/drivers98/vga256/svga) + InstallLinkKitNonExecFile(cir_line.c,$(XF98LINKKITDIR)/drivers98/vga256/svga) + InstallLinkKitNonExecFile(cir_orect.c,$(XF98LINKKITDIR)/drivers98/vga256/svga) + InstallLinkKitNonExecFile(cirBlitter.h,$(XF98LINKKITDIR)/drivers98/vga256/svga) + InstallLinkKitNonExecFile(cir_span.h,$(XF98LINKKITDIR)/drivers98/vga256/svga) + InstallLinkKitNonExecFile(cir_alloc.h,$(XF98LINKKITDIR)/drivers98/vga256/svga) + InstallLinkKitNonExecFile(cirBlitMM.h,$(XF98LINKKITDIR)/drivers98/vga256/svga) + InstallLinkKitNonExecFile(cir_blitLG.h,$(XF98LINKKITDIR)/drivers98/vga256/svga) + InstallLinkKitNonExecFile(cir_inline.h,$(XF98LINKKITDIR)/drivers98/vga256/svga) + InstallLinkKitNonExecFile(cirrus_acl.c,$(XF98LINKKITDIR)/drivers98/vga256/svga) + InstallLinkKitNonExecFile(laguna_acl.c,$(XF98LINKKITDIR)/drivers98/vga256/svga) + InstallLinkKitNonExecFile(Imakefile,$(XF98LINKKITDIR)/drivers98/vga256/svga) + InstallLinkKitNonExecFile(linearline.c,$(XF98LINKKITDIR)/drivers98/vga256/svga) + InstallLinkKitNonExecFile(linearline.h,$(XF98LINKKITDIR)/drivers98/vga256/svga) + InstallLinkKitNonExecFile(cir_pc98.c,$(XF98LINKKITDIR)/drivers98/vga256/svga) + + DependTarget() *** ./programs/Xserver/hw/xfree98/vga256/drivers/trident/pc98_tgui.c@@/PUBLIC-LATEST Sun Jul 20 13:53:51 1997 --- xc/programs/Xserver/hw/xfree98/vga256/drivers/trident/pc98_tgui.c Fri Mar 6 14:13:44 1998 *************** *** 1,9 **** ! /* $TOG: pc98_tgui.c /main/6 1997/07/20 13:53:52 kaleb $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree98/vga256/drivers/trident/pc98_tgui.c,v 3.7.2.1 1997/05/16 11:35:24 hohndel Exp $ */ #include "X.h" #include "input.h" --- 1,9 ---- ! /* $TOG: pc98_tgui.c /main/7 1998/03/06 14:15:22 kaleb $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree98/vga256/drivers/trident/pc98_tgui.c,v 3.7.2.2 1998/02/01 16:05:35 robin Exp $ */ #include "X.h" #include "input.h" *************** *** 59,93 **** void crtswTGUiGen(short); void crtswNEC96xx(short); void crtswNEC9320(short); ! void crtswDRV96xx(short); Bool testTRUE(); ! Bool testDRV(); ! static PC98TGUiTable pc98TGUiTab[]={ {"NEC Trident TGUi96xx(PCI Bus Type)", ! PC98NEC96xx, PC98PCIBus, PC98LINEAR, ! 0x20000000, 0, 0x20400000, ! 45, 0x00af, {108000, 58500, 0, 31500}, crtswNEC96xx, testTRUE, ChipInit} - ,{"NEC Trident TGUi96xx(PCI Bus Type)", - PC98NEC96xx, PC98PCIBus, PC98LINEAR, - 0x21000000, 0, 0x21400000, - 45, 0x00af, {108000, 58500, 0, 31500}, - crtswNEC96xx, testTRUE, ChipInit} ,{"NEC Trident Cyber9320(PCI Bus Type)", ! PC98NEC9320, PC98PCIBus, PC98LINEAR, ! 0xffc00000, 0, 0xffe00000, ! 45, 0x00af, {108000, 58500, 0, 25175}, crtswNEC9320, testTRUE, ChipInit} ,{"I/O-Data GA-DRV/98,GA-DR/98(C Bus Type)", ! PC98DRV96xx, PC98CBus, PC98PAGE, ! 0, 0x00f20000, 0x00f00000, ! 45, 0x00af, {108000, 58500, 0, 25175}, ! crtswDRV96xx, testDRV, ChipInit} ,{"End of Data Base", ! PC98NoExist, PC98Unknown, PC98PAGE, ! 0, 0, 0, ! 0, 0, {0, 0, 0, 0}, NULL, NULL, NULL}}; static unsigned char seqreg_data[ 0x05 ] = { --- 59,110 ---- void crtswTGUiGen(short); void crtswNEC96xx(short); void crtswNEC9320(short); ! void crtswGA96xx(short); Bool testTRUE(); ! Bool testGA(); ! unsigned long GetMCLK(int); ! static PC98TGUiTable pc98TGUiRunTime={ ! PC98NoExist, PC98Unknown, PC98PAGE, ! 0, 0, 0, 0, 0, {0, 0, 0, 0}, ! NULL}; ! ! static PC98TGUiIOMap ioMapNEC96xx[]={ ! {0x20000000, 0, 0x20400000} ! ,{0x21000000, 0, 0x21400000} ! ,{0, 0 ,0} ! }; ! ! static PC98TGUiIOMap ioMapNEC9320[]={ ! {0xffc00000, 0, 0xffe00000} ! ,{0, 0, 0} ! }; ! ! static PC98TGUiIOMap ioMapGA96xx[]={ ! {0, 0x00f20000, 0x00f00000} ! ,{0, 0, 0} ! }; ! ! static PC98TGUiIOMap ioMapDummy[]={ ! {0, 0, 0} ! }; ! ! static PC98TGUiDataBase pc98TGUidb[]={ {"NEC Trident TGUi96xx(PCI Bus Type)", ! PC98NEC96xx, PC98PCIBus, PC98LINEAR, ioMapNEC96xx, ! 80000, {135000, 58500, 0, 40000}, crtswNEC96xx, testTRUE, ChipInit} ,{"NEC Trident Cyber9320(PCI Bus Type)", ! PC98NEC9320, PC98PCIBus, PC98LINEAR, ioMapNEC9320, ! 80000, {108000, 58500, 0, 25175}, crtswNEC9320, testTRUE, ChipInit} ,{"I/O-Data GA-DRV/98,GA-DR/98(C Bus Type)", ! PC98GA96xx, PC98CBus, PC98PAGE, ioMapGA96xx, ! 80000, {135000, 58500, 0, 40000}, ! crtswGA96xx, testGA, ChipInit} ,{"End of Data Base", ! PC98NoExist, PC98Unknown, PC98PAGE, ioMapDummy, ! 0, {0, 0, 0, 0}, NULL, NULL, NULL}}; static unsigned char seqreg_data[ 0x05 ] = { *************** *** 122,163 **** Bool BoardInit(void) { ! int i; /* Save current horizontal sync, 1: 31.5KHz */ hsync31 = _inb(0x9a8) & 0x01; ! for(i=0;pc98TGUiTab[i].TGUiType != PC98NoExist;i++){ ! switch(pc98TGUiTab[i].BusType){ ! case PC98PCIBus: /* Serach mmioBase on PCI Bus */ ! if(vgaPCIInfo && vgaPCIInfo->Vendor == PCI_VENDOR_TRIDENT ! && vgaPCIInfo->MemBase == pc98TGUiTab[i].pciBase){ ! mmioBase = xf86MapVidMem(0, VGA_REGION, ! (pointer)(pc98TGUiTab[i].mmioBase), 0x10000); ! if(!pc98TGUiTab[i].test()){ ! xf86UnMapVidMem(0, VGA_REGION, mmioBase, 0x10000); ! mmioBase = NULL; } - } break; ! case PC98CBus: /* Serach mmioBase on C Bus */ ! mmioBase = xf86MapVidMem(0, VGA_REGION, ! (pointer)(pc98TGUiTab[i].mmioBase), 0x10000); ! if(!pc98TGUiTab[i].test()){ ! xf86UnMapVidMem(0, VGA_REGION, mmioBase, 0x10000); ! mmioBase = NULL; ! } break; default: ! FatalError("PC98: Server DataBase Error\n"); break; } ! if(mmioBase != NULL)break; ! } ! ! pc98TGUi = &pc98TGUiTab[i]; ! ! if(pc98TGUi->TGUiType != PC98NoExist){ ! switch(pc98TGUi->VramType){ case PC98LINEAR: pc98PvramBase = (pointer)(NULL); break; --- 139,189 ---- Bool BoardInit(void) { ! unsigned long mclk; ! PC98TGUiIOMap *iomap; ! PC98TGUiDataBase *tguidb; ! /* Save current horizontal sync, 1: 31.5KHz */ hsync31 = _inb(0x9a8) & 0x01; ! mmioBase = NULL; ! for(tguidb = pc98TGUidb; tguidb->TGUiType != PC98NoExist; tguidb++){ ! switch(tguidb->BusType){ ! case PC98PCIBus: /* Search mmioBase on PCI Bus */ ! if(vgaPCIInfo && vgaPCIInfo->Vendor == PCI_VENDOR_TRIDENT) ! for(iomap = tguidb->ioMap; iomap->mmioBase != 0; iomap++){ ! if(vgaPCIInfo->MemBase == iomap->pciBase){ ! mmioBase = xf86MapVidMem(0, VGA_REGION, ! (pointer)(iomap->mmioBase), 0x10000); ! if(!tguidb->test()){ ! xf86UnMapVidMem(0, VGA_REGION, mmioBase, 0x10000); ! mmioBase = NULL; ! } ! } ! if(mmioBase != NULL)break; /* break IO search loop if mmio Found */ } break; ! ! case PC98CBus: /* Search mmioBase on C Bus */ ! for(iomap = tguidb->ioMap; iomap->mmioBase != 0; iomap++){ ! mmioBase = xf86MapVidMem(0, VGA_REGION, ! (pointer)(iomap->mmioBase), 0x10000); ! if(!tguidb->test()){ ! xf86UnMapVidMem(0, VGA_REGION, mmioBase, 0x10000); ! mmioBase = NULL; ! } ! if(mmioBase != NULL)break; /* break IO search loop if mmio Found */ ! } break; + default: ! FatalError("Server Internal DataBase Error\n"); break; } ! if(mmioBase != NULL)break; /* break board search loop if mmio Found */ ! } ! if(tguidb->TGUiType != PC98NoExist){ ! switch(tguidb->VramType){ case PC98LINEAR: pc98PvramBase = (pointer)(NULL); break; *************** *** 164,193 **** case PC98PAGE: case PC98BOTH: ! pc98PvramBase = (pointer)(pc98TGUi->vgaBase); break; default: ! FatalError("PC98: Server DataBase Error\n"); break; } - ErrorF("%s %s: Config for %s MMIO @ 0x%08X\n", - XCONFIG_PROBED, vga256InfoRec.name, pc98TGUi->info, - pc98TGUi->mmioBase); - pc98TGUi->init(); } else { FatalError("No Data Base Entry for this Trident Chip\n"); } return TRUE; } Bool testTRUE() { return TRUE; } ! Bool testDRV() { _outw(0x52e8,0x00ff); _outw(0x56e8,0x6fa1); --- 190,274 ---- case PC98PAGE: case PC98BOTH: ! pc98PvramBase = (pointer)(iomap->vgaBase); break; default: ! FatalError("Server Internal DataBase Error\n"); break; } } else { FatalError("No Data Base Entry for this Trident Chip\n"); } + mclk = GetMCLK(tguidb->MCLK); + + /* making runtime database */ + pc98TGUi = &pc98TGUiRunTime; + + pc98TGUi->TGUiType = tguidb->TGUiType; + pc98TGUi->BusType = tguidb->BusType; + pc98TGUi->VramType = tguidb->VramType; + pc98TGUi->mmioBase = iomap->mmioBase; + pc98TGUi->pciBase = iomap->pciBase; + pc98TGUi->vgaBase = iomap->vgaBase; + pc98TGUi->crtsw = tguidb->crtsw; + + pc98TGUi->Bpp_Clocks[0] = tguidb->Bpp_Clocks[0]; + pc98TGUi->Bpp_Clocks[1] = tguidb->Bpp_Clocks[1]; + pc98TGUi->Bpp_Clocks[2] = tguidb->Bpp_Clocks[2]; + pc98TGUi->Bpp_Clocks[3] = tguidb->Bpp_Clocks[3]; + + pc98TGUi->MCLK_A = (mclk & 0x00ff); + pc98TGUi->MCLK_B = (mclk & 0x0300) >> 8; + + ErrorF("%s %s: Config for %s MMIO @ 0x%08X\n", + XCONFIG_PROBED, vga256InfoRec.name, tguidb->info, + iomap->mmioBase); + ErrorF("%s %s: Set MCLK %8.3fMHz (0x%02X%02X)\n", + XCONFIG_PROBED, vga256InfoRec.name, tguidb->MCLK / 1000.0, + pc98TGUi->MCLK_B, pc98TGUi->MCLK_A); + tguidb->init(); + return TRUE; } + unsigned long GetMCLK(int freq){ + int clock_diff=750; + int ffreq; + unsigned int m, n, k ,s; + unsigned long mclk; + + s = 0; + + for(k=0;k<2;k++) + for(n=0; n<64; n++) + for(m=0; m<8; m++) + { + ffreq = (( (n + 4) * (2-k) * 14318.18 ) / (m + 2)); + if((ffreq > freq - clock_diff) && (ffreq < freq + clock_diff)) + { + if((n+4)*100/(m+2) < 500 && (n+4)*100/(m+2) > 170){ + clock_diff = (freq > ffreq) ? freq - ffreq : ffreq - freq; + mclk = (k << 9) | (n << 3) | m; + s = ffreq; + } + } + } + + if(s == 0)FatalError("MCLK %d is not a valid clock.\n" + "Server Inner DataBase Error.\n", + freq); + + return(mclk); + } + Bool testTRUE() { return TRUE; } ! Bool testGA() { _outw(0x52e8,0x00ff); _outw(0x56e8,0x6fa1); *************** *** 278,284 **** return; } ! void crtswDRV96xx(short crtmod) { if(crtmod != 0){ crtswNECGen(crtmod); --- 359,365 ---- return; } ! void crtswGA96xx(short crtmod) { if(crtmod != 0){ crtswNECGen(crtmod); *************** *** 313,319 **** /* Bus & DRAM Setup */ CRTCwrite(0x2a, CRTCread(0x2a) | 0x40); /* Local Bus / DRAM Select */ ! CRTCwrite(0x20, 0x30); /* Command FIFO Register */ CRTCwrite(0x23, 0xe8); /* DRAM Timing Control */ CRTCwrite(0x25, 0x0a); /* RAMDAC R/W Timing Control */ CRTCwrite(0x2f, 0x27); /* Performance Tuning */ --- 394,400 ---- /* Bus & DRAM Setup */ CRTCwrite(0x2a, CRTCread(0x2a) | 0x40); /* Local Bus / DRAM Select */ ! CRTCwrite(0x20, 0x38); /* Command FIFO Register */ CRTCwrite(0x23, 0xe8); /* DRAM Timing Control */ CRTCwrite(0x25, 0x0a); /* RAMDAC R/W Timing Control */ CRTCwrite(0x2f, 0x27); /* Performance Tuning */ *************** *** 322,329 **** CRTCwrite(0x3b, 0x21); /* Clock and Tuning */ CRTCwrite(0x3c, 0x00); /* Miscellaneous Control */ ! outb(0x43C6, pc98TGUi->MCLK & 0x00ff); ! outb(0x43C7, (pc98TGUi->MCLK & 0xff00) >> 8); /* Enable Graphic Engine */ CRTCwrite(0x34, ((pc98TGUi->mmioBase & 0x00ff0000L) >> 16)); --- 403,410 ---- CRTCwrite(0x3b, 0x21); /* Clock and Tuning */ CRTCwrite(0x3c, 0x00); /* Miscellaneous Control */ ! outb(0x43C6, pc98TGUi->MCLK_A); ! outb(0x43C7, pc98TGUi->MCLK_B); /* Enable Graphic Engine */ CRTCwrite(0x34, ((pc98TGUi->mmioBase & 0x00ff0000L) >> 16)); *** ./programs/Xserver/hw/xfree98/vga256/drivers/trident/pc98_tgui.h@@/PUBLIC-LATEST Sun Jul 20 13:53:55 1997 --- xc/programs/Xserver/hw/xfree98/vga256/drivers/trident/pc98_tgui.h Fri Mar 6 14:13:49 1998 *************** *** 1,17 **** ! /* $TOG: pc98_tgui.h /main/3 1997/07/20 13:53:57 kaleb $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree98/vga256/drivers/trident/pc98_tgui.h,v 3.3 1996/12/28 08:20:02 dawes Exp $ */ typedef enum { PC98Unknown , PC98PCIBus , PC98CBus } PC98BusType; typedef enum { PC98PAGE , PC98LINEAR , PC98BOTH } PC98VramType; typedef enum { PC98NoExist , PC98NEC96xx , PC98NEC9320 ! , PC98DRV96xx } PC98TGUiType; typedef struct { - char info[80]; PC98TGUiType TGUiType; PC98BusType BusType; PC98VramType VramType; --- 1,16 ---- ! /* $TOG: pc98_tgui.h /main/4 1998/03/06 14:15:27 kaleb $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree98/vga256/drivers/trident/pc98_tgui.h,v 3.3.2.1 1998/02/01 16:05:35 robin Exp $ */ typedef enum { PC98Unknown , PC98PCIBus , PC98CBus } PC98BusType; typedef enum { PC98PAGE , PC98LINEAR , PC98BOTH } PC98VramType; typedef enum { PC98NoExist , PC98NEC96xx , PC98NEC9320 ! , PC98GA96xx } PC98TGUiType; typedef struct { PC98TGUiType TGUiType; PC98BusType BusType; PC98VramType VramType; *************** *** 18,27 **** unsigned long pciBase; unsigned long vgaBase; unsigned long mmioBase; ! unsigned char DRAMspeed; int MCLK; int Bpp_Clocks[4]; void (*crtsw)(short); Bool (*test)(void); Bool (*init)(void); ! } PC98TGUiTable; --- 17,43 ---- unsigned long pciBase; unsigned long vgaBase; unsigned long mmioBase; ! unsigned char MCLK_A; ! unsigned char MCLK_B; ! int Bpp_Clocks[4]; ! void (*crtsw)(short); ! } PC98TGUiTable; ! ! typedef struct { ! unsigned long pciBase; ! unsigned long vgaBase; ! unsigned long mmioBase; ! } PC98TGUiIOMap; ! ! typedef struct { ! char info[80]; ! PC98TGUiType TGUiType; ! PC98BusType BusType; ! PC98VramType VramType; ! PC98TGUiIOMap *ioMap; int MCLK; int Bpp_Clocks[4]; void (*crtsw)(short); Bool (*test)(void); Bool (*init)(void); ! } PC98TGUiDataBase; *** ./programs/Xserver/hw/xfree98/vga256/ganbwap/Imakefile@@/PUBLIC-LATEST Sun Jul 20 13:54:14 1997 --- xc/programs/Xserver/hw/xfree98/vga256/ganbwap/Imakefile Fri Mar 6 14:13:55 1998 *************** *** 1,220 **** ! XCOMM $TOG: Imakefile /main/10 1997/07/20 13:54:15 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree98/vga256/ganbwap/Imakefile,v 3.10 1996/12/23 07:08:47 dawes Exp $ ! #include <Server.tmpl> ! ! #ifdef i386Architecture ! FSRCS = fBitBlt.s fFillCopy.s fFillOr.s fFillAnd.s \ ! fFillXor.s fFillSet.s vgabres.s vgalineH.s vgalineV.s ! BSRCS = BitBlt.s BitBlt2.s Box.s Line.s VHLine.s vgaBank.s ! ! FOBJS = fBitBlt.o fFillCopy.o fFillOr.o fFillAnd.o \ ! fFillXor.o fFillSet.o vgabres.o vgalineH.o vgalineV.o ! BOBJS = BitBlt.o BitBlt2.o Box.o Line.o VHLine.o vgaBank.o ! #else ! FSRCS = vgaBltFillc.c vgaLinec.c ! BSRCS = vgaBankc.c ! ! FOBJS = vgaBltFillc.o vgaLinec.o ! BOBJS = vgaBankc.o ! #endif ! ! SRCS = vgagc.c vgawindow.c vgascrinit.c \ ! vgapntwin.c vgapwinS.c vgabitblt.c \ ! vgafillsp.c vgasetsp.c vgaimage.c \ ! vgagetsp.c vgafillrct.c vgaBitBlt1.c \ ! vgasolidC.c vgasolidCS.c vgasolidX.c \ ! vgasolidO.c vgasolidA.c vgasolidG.c \ ! vgatile32C.c vgatile32G.c \ ! vgatileoddC.c vgatileoddG.c \ ! vgazerarcC.c vgazerarcX.c vgazerarcG.c \ ! vgafillarcC.c vgafillarcG.c \ ! vgategblt.c vgabstore.c vga8cppl.c \ ! vgabltC.c vgabltCS.c vgabltX.c vgabltO.c vgabltG.c \ ! vgateblt8.c vgateblt8S.c vgaglblt8.c vgaglrop8.c \ ! vgapush8.c vgarctstp8.c vgarctstp8S.c vgapolypnt.c \ ! vgaline.c vgalineS.c vgabresd.c \ ! vgalined.c vgasegd.c vgaseg.c vgasegS.c \ ! vgaply1rctC.c vgaply1rctG.c vgafuncs.c \ ! SpeedUpBlt.c $(BSRCS) \ ! vgaBanks.c $(FSRCS) vgaHW.c vga.c vgaCmap.c \ ! vgaPCI.c vgatables.c ! ! FOBJS = fBitBlt.o fFillCopy.o fFillXor.o fFillOr.o fFillAnd.o \ ! fFillSet.o vgabres.o vgalineH.o vgalineV.o ! ! OBJS = vgagc.o vgawindow.o vgascrinit.o \ ! vgagetsp.o vgafillrct.o vgaimage.o \ ! vgasolidC.o vgasolidCS.o vgasolidX.o \ ! vgasolidO.o vgasolidA.o vgasolidG.o \ ! vgatile32C.o vgatile32G.o \ ! vgatileoddC.o vgatileoddG.o \ ! vgafillsp.o vgasetsp.o \ ! vgapntwin.o vgapwinS.o vgaBitBlt1.o \ ! vgazerarcC.o vgazerarcX.o vgazerarcG.o \ ! vgafillarcC.o vgafillarcG.o \ ! vgategblt.o vgabstore.o vga8cppl.o \ ! vgateblt8.o vgateblt8S.o vgaglblt8.o vgaglrop8.o \ ! vgarctstp8.o vgarctstp8S.o vgapolypnt.o \ ! vgaline.o vgalineS.o vgabresd.o \ ! vgalined.o vgasegd.o vgaseg.o vgasegS.o \ ! vgabitblt.o vgabltC.o vgabltCS.o vgabltX.o \ ! vgabltO.o vgabltG.o \ ! vgapush8.o vgaply1rctC.o vgaply1rctG.o $(STIPPLEOBJ) vgafuncs.o \ ! SpeedUpBlt.o $(BOBJS) \ ! vgaBanks.o $(FOBJS) vgaHW.o vga.o vgaCmap.o \ ! vgaPCI.o vgatables.o ! ! INCLUDES = -I. -I$(XF98COMSRC) -I$(XF86OSSRC) -I$(XF86HWSRC) \ ! -I$(SERVERSRC)/cfb -I$(SERVERSRC)/mfb -I$(SERVERSRC)/mi \ ! -I$(SERVERSRC)/include -I$(XINCLUDESRC) -I$(FONTINCSRC) \ ! -I$(XF86SRC)/xaa ! LINTLIBS = ../../../dix/llib-ldix.ln ../../../os/llib-los.ln \ ! ../../mfb/llib-lmfb.ln ../../mi/llib-lmi.ln ! ! #if DirtyStartup ! STARTUPDEFINES = -DDIRTY_STARTUP ! #endif ! ! DEFINES = $(SPEEDUPDEFINES) $(STARTUPDEFINES) -DPSZ=8 -DPC98 -DPC98_GANB_WAP ! ! #ifdef i386Architecture ! SUDEFINE = -DSPEEDUP ! #endif ! ! SubdirLibraryRule($(OBJS)) ! NormalLibraryObjectRule() ! NormalAsmObjectRule() ! ! NormalLintTarget($(SRCS)) ! ! LinkSourceFile(Design,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vga.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vga.h,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vga256.h,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vga8cppl.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaAsm.h,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaBank.h,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaBank.s,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaCmap.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaHW.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaPCI.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaPCI.h,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgabitblt.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgablt.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgabltC.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgabresd.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgabstore.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgafillarc.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgafillrct.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgafillsp.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgafuncs.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgagc.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgagetsp.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaglblt8.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaimage.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaline.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgalined.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaply1rct.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgapntwin.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgapolypnt.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgapush8.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgapwinS.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgarctstp8.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgascrinit.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgasetsp.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgasolid.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgatables.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgateblt8.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgategblt.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgatile32.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgatileodd.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgawindow.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgazerarc.c,$(XF86SRC)/vga256/vga) ! ! #define EnhancedDir $(XF86SRC)/vga256/enhanced ! ! ObjectFromSpecialSource(vgaBanks,EnhancedDir/gBanks,NullParameter) ! #ifdef i386Architecture ! ObjectFromSpecialAsmSource(BitBlt,EnhancedDir/suBitBlt,NullParameter) ! ObjectFromSpecialAsmSource(BitBlt2,EnhancedDir/suBBlt2,NullParameter) ! ObjectFromSpecialAsmSource(Box,EnhancedDir/suBox,NullParameter) ! ObjectFromSpecialAsmSource(Line,EnhancedDir/suLine,NullParameter) ! ObjectFromSpecialAsmSource(VHLine,EnhancedDir/suVHLine,NullParameter) ! ObjectFromSpecialAsmSource(vgabres,EnhancedDir/fLineBres,NullParameter) ! ObjectFromSpecialAsmSource(vgalineH,EnhancedDir/fLineH,NullParameter) ! ObjectFromSpecialAsmSource(vgalineV,EnhancedDir/fLineV,NullParameter) ! LinkSourceFile(fBitBlt.s,EnhancedDir) ! LinkSourceFile(fFill.s,EnhancedDir) ! LinkSourceFile(fFillSet.s,EnhancedDir) ! #else ! LinkSourceFile(vgaBltFillc.c,EnhancedDir) ! LinkSourceFile(vgaLinec.c,EnhancedDir) ! #endif ! LinkFile(vgaBitBlt1.c,EnhancedDir/vgaBitBlt.c) ! LinkSourceFile(SpeedUpBlt.c,EnhancedDir) ! LinkSourceFile(vgaFasm.h,EnhancedDir) ! ! ObjectFromSpecialSource(vgaseg,vgaline,-DPOLYSEGMENT) ! ObjectFromSpecialSource(vgasegd,vgalined,-DPOLYSEGMENT) ! ObjectFromSpecialSource(vgaglrop8,vgaglblt8,-DGLYPHROP) ! SpecialObjectRule(vgaglblt8.o,vgaglblt8.c,$(STIPPLEDEF)) ! ! ObjectFromSpecialSource(vgalineS,vgaline,$(SUDEFINE)) ! ObjectFromSpecialSource(vgasegS,vgaline,$(SUDEFINE) -DPOLYSEGMENT) ! ObjectFromSpecialSource(vgateblt8S,vgateblt8,$(SUDEFINE)) ! ObjectFromSpecialSource(vgarctstp8S,vgarctstp8,$(SUDEFINE)) ! ! ObjectFromSpecialSource(vgafillarcC,vgafillarc,-DRROP=GXcopy) ! ObjectFromSpecialSource(vgafillarcG,vgafillarc,-DRROP=GXset) ! ! ObjectFromSpecialSource(vgazerarcC,vgazerarc,-DRROP=GXcopy) ! ObjectFromSpecialSource(vgazerarcX,vgazerarc,-DRROP=GXxor) ! ObjectFromSpecialSource(vgazerarcG,vgazerarc,-DRROP=GXset) ! ! ObjectFromSpecialSource(vgabltCS,vgablt,-DMROP=Mcopy $(SUDEFINE)) ! ObjectFromSpecialSource(vgabltX,vgablt,-DMROP=Mxor) ! ObjectFromSpecialSource(vgabltO,vgablt,-DMROP=Mor) ! ObjectFromSpecialSource(vgabltG,vgablt,-DMROP=0) ! ! ObjectFromSpecialSource(vgasolidC,vgasolid,-DRROP=GXcopy) ! ObjectFromSpecialSource(vgasolidCS,vgasolid,-DRROP=GXcopy $(SUDEFINE)) ! ObjectFromSpecialSource(vgasolidX,vgasolid,-DRROP=GXxor) ! ObjectFromSpecialSource(vgasolidO,vgasolid,-DRROP=GXor) ! ObjectFromSpecialSource(vgasolidA,vgasolid,-DRROP=GXand) ! ObjectFromSpecialSource(vgasolidG,vgasolid,-DRROP=GXset) ! ! ObjectFromSpecialSource(vgatile32C,vgatile32,-DMROP=Mcopy) ! ObjectFromSpecialSource(vgatile32G,vgatile32,-DMROP=0) ! ! ObjectFromSpecialSource(vgatileoddC,vgatileodd,-DMROP=Mcopy) ! ObjectFromSpecialSource(vgatileoddG,vgatileodd,-DMROP=0) ! ! ObjectFromSpecialSource(vgaply1rctC,vgaply1rct,-DRROP=GXcopy) ! ObjectFromSpecialSource(vgaply1rctG,vgaply1rct,-DRROP=GXset) ! ! #ifdef i386Architecture ! ObjectFromSpecialAsmSource(fFillAnd,fFill,-DRROP=GXAnd) ! ObjectFromSpecialAsmSource(fFillCopy,fFill,-DRROP=GXCopy) ! ObjectFromSpecialAsmSource(fFillOr,fFill,-DRROP=GXOr) ! ObjectFromSpecialAsmSource(fFillXor,fFill,-DRROP=GXXor) ! #endif ! ! InstallLinkKitNonExecFile(vga.h,$(XF98LINKKITDIR)/drivers98) ! InstallLinkKitNonExecFile(vgaBank.h,$(XF98LINKKITDIR)/drivers98) ! #ifndef DontInstallPC98Version ! InstallLinkKitNonExecFile(vga.h,$(XF98LINKKITDIR)/include) ! InstallLinkKitNonExecFile(vga256.h,$(XF98LINKKITDIR)/include) ! InstallLinkKitNonExecFile(vgaFasm.h,$(XF98LINKKITDIR)/include) ! InstallLinkKitNonExecFile(vgaHW.c,$(XF98LINKKITDIR)/VGADriverDoc) ! InstallLinkKitNonExecFile(vgaPCI.h,$(XF98LINKKITDIR)/include) ! #endif ! ! #ifndef OS2Architecture ! DependTarget() ! #endif --- 1,10 ---- ! XCOMM $TOG: Imakefile /main/11 1998/03/06 14:15:33 kaleb $ + XCOMM $XFree86: xc/programs/Xserver/hw/xfree98/vga256/ganbwap/Imakefile,v 3.10.2.2 1998/02/01 22:08:17 robin Exp $ + #define VGADEFINES -DPC98_GANB_WAP ! #include "../Imakefile.vga" *** /dev/null Tue Jun 30 11:51:40 1998 --- xc/programs/Xserver/hw/xfree98/vga256/mga/Imakefile Fri Mar 6 14:14:00 1998 *************** *** 0 **** --- 1,10 ---- + XCOMM $TOG: Imakefile /main/1 1998/03/06 14:15:39 kaleb $ + + + + + XCOMM $XFree86: xc/programs/Xserver/hw/xfree98/vga256/mga/Imakefile,v 1.2.2.2 1998/02/01 22:08:17 robin Exp $ + + #define VGADEFINES -DPC98_MGA + + #include "../Imakefile.vga" *** ./programs/Xserver/hw/xfree98/vga256/nec480/Imakefile@@/PUBLIC-LATEST Sun Jul 20 13:54:18 1997 --- xc/programs/Xserver/hw/xfree98/vga256/nec480/Imakefile Fri Mar 6 14:14:05 1998 *************** *** 1,220 **** ! XCOMM $TOG: Imakefile /main/10 1997/07/20 13:54:19 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree98/vga256/nec480/Imakefile,v 3.9 1996/12/23 07:08:51 dawes Exp $ ! #include <Server.tmpl> ! ! #ifdef i386Architecture ! FSRCS = fBitBlt.s fFillCopy.s fFillOr.s fFillAnd.s \ ! fFillXor.s fFillSet.s vgabres.s vgalineH.s vgalineV.s ! BSRCS = BitBlt.s BitBlt2.s Box.s Line.s VHLine.s vgaBank.s ! ! FOBJS = fBitBlt.o fFillCopy.o fFillOr.o fFillAnd.o \ ! fFillXor.o fFillSet.o vgabres.o vgalineH.o vgalineV.o ! BOBJS = BitBlt.o BitBlt2.o Box.o Line.o VHLine.o vgaBank.o ! #else ! FSRCS = vgaBltFillc.c vgaLinec.c ! BSRCS = vgaBankc.c ! ! FOBJS = vgaBltFillc.o vgaLinec.o ! BOBJS = vgaBankc.o ! #endif ! ! SRCS = vgagc.c vgawindow.c vgascrinit.c \ ! vgapntwin.c vgapwinS.c vgabitblt.c \ ! vgafillsp.c vgasetsp.c vgaimage.c \ ! vgagetsp.c vgafillrct.c vgaBitBlt1.c \ ! vgasolidC.c vgasolidCS.c vgasolidX.c \ ! vgasolidO.c vgasolidA.c vgasolidG.c \ ! vgatile32C.c vgatile32G.c \ ! vgatileoddC.c vgatileoddG.c \ ! vgazerarcC.c vgazerarcX.c vgazerarcG.c \ ! vgafillarcC.c vgafillarcG.c \ ! vgategblt.c vgabstore.c vga8cppl.c \ ! vgabltC.c vgabltCS.c vgabltX.c vgabltO.c vgabltG.c \ ! vgateblt8.c vgateblt8S.c vgaglblt8.c vgaglrop8.c \ ! vgapush8.c vgarctstp8.c vgarctstp8S.c vgapolypnt.c \ ! vgaline.c vgalineS.c vgabresd.c \ ! vgalined.c vgasegd.c vgaseg.c vgasegS.c \ ! vgaply1rctC.c vgaply1rctG.c vgafuncs.c \ ! SpeedUpBlt.c $(BSRCS) \ ! vgaBanks.c $(FSRCS) vgaHW.c vga.c vgaCmap.c \ ! vgaPCI.c vgatables.c ! ! FOBJS = fBitBlt.o fFillCopy.o fFillXor.o fFillOr.o fFillAnd.o \ ! fFillSet.o vgabres.o vgalineH.o vgalineV.o ! ! OBJS = vgagc.o vgawindow.o vgascrinit.o \ ! vgagetsp.o vgafillrct.o vgaimage.o \ ! vgasolidC.o vgasolidCS.o vgasolidX.o \ ! vgasolidO.o vgasolidA.o vgasolidG.o \ ! vgatile32C.o vgatile32G.o \ ! vgatileoddC.o vgatileoddG.o \ ! vgafillsp.o vgasetsp.o \ ! vgapntwin.o vgapwinS.o vgaBitBlt1.o \ ! vgazerarcC.o vgazerarcX.o vgazerarcG.o \ ! vgafillarcC.o vgafillarcG.o \ ! vgategblt.o vgabstore.o vga8cppl.o \ ! vgateblt8.o vgateblt8S.o vgaglblt8.o vgaglrop8.o \ ! vgarctstp8.o vgarctstp8S.o vgapolypnt.o \ ! vgaline.o vgalineS.o vgabresd.o \ ! vgalined.o vgasegd.o vgaseg.o vgasegS.o \ ! vgabitblt.o vgabltC.o vgabltCS.o vgabltX.o \ ! vgabltO.o vgabltG.o \ ! vgapush8.o vgaply1rctC.o vgaply1rctG.o $(STIPPLEOBJ) vgafuncs.o \ ! SpeedUpBlt.o $(BOBJS) \ ! vgaBanks.o $(FOBJS) vgaHW.o vga.o vgaCmap.o \ ! vgaPCI.o vgatables.o ! ! INCLUDES = -I. -I$(XF98COMSRC) -I$(XF86OSSRC) -I$(XF86HWSRC) \ ! -I$(SERVERSRC)/cfb -I$(SERVERSRC)/mfb -I$(SERVERSRC)/mi \ ! -I$(SERVERSRC)/include -I$(XINCLUDESRC) -I$(FONTINCSRC) \ ! -I$(XF86SRC)/xaa ! LINTLIBS = ../../../dix/llib-ldix.ln ../../../os/llib-los.ln \ ! ../../mfb/llib-lmfb.ln ../../mi/llib-lmi.ln ! ! #if DirtyStartup ! STARTUPDEFINES = -DDIRTY_STARTUP ! #endif ! ! DEFINES = $(SPEEDUPDEFINES) $(STARTUPDEFINES) -DPSZ=8 -DPC98 -DPC98_NEC480 ! ! #ifdef i386Architecture ! SUDEFINE = -DSPEEDUP ! #endif ! ! SubdirLibraryRule($(OBJS)) ! NormalLibraryObjectRule() ! NormalAsmObjectRule() ! ! NormalLintTarget($(SRCS)) ! ! LinkSourceFile(Design,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vga.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vga.h,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vga256.h,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vga8cppl.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaAsm.h,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaBank.h,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaBank.s,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaCmap.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaHW.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaPCI.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaPCI.h,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgabitblt.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgablt.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgabltC.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgabresd.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgabstore.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgafillarc.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgafillrct.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgafillsp.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgafuncs.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgagc.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgagetsp.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaglblt8.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaimage.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaline.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgalined.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaply1rct.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgapntwin.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgapolypnt.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgapush8.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgapwinS.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgarctstp8.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgascrinit.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgasetsp.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgasolid.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgatables.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgateblt8.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgategblt.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgatile32.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgatileodd.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgawindow.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgazerarc.c,$(XF86SRC)/vga256/vga) ! ! #define EnhancedDir $(XF86SRC)/vga256/enhanced ! ! ObjectFromSpecialSource(vgaBanks,EnhancedDir/gBanks,NullParameter) ! #ifdef i386Architecture ! ObjectFromSpecialAsmSource(BitBlt,EnhancedDir/suBitBlt,NullParameter) ! ObjectFromSpecialAsmSource(BitBlt2,EnhancedDir/suBBlt2,NullParameter) ! ObjectFromSpecialAsmSource(Box,EnhancedDir/suBox,NullParameter) ! ObjectFromSpecialAsmSource(Line,EnhancedDir/suLine,NullParameter) ! ObjectFromSpecialAsmSource(VHLine,EnhancedDir/suVHLine,NullParameter) ! ObjectFromSpecialAsmSource(vgabres,EnhancedDir/fLineBres,NullParameter) ! ObjectFromSpecialAsmSource(vgalineH,EnhancedDir/fLineH,NullParameter) ! ObjectFromSpecialAsmSource(vgalineV,EnhancedDir/fLineV,NullParameter) ! LinkSourceFile(fBitBlt.s,EnhancedDir) ! LinkSourceFile(fFill.s,EnhancedDir) ! LinkSourceFile(fFillSet.s,EnhancedDir) ! #else ! LinkSourceFile(vgaBltFillc.c,EnhancedDir) ! LinkSourceFile(vgaLinec.c,EnhancedDir) ! #endif ! LinkFile(vgaBitBlt1.c,EnhancedDir/vgaBitBlt.c) ! LinkSourceFile(SpeedUpBlt.c,EnhancedDir) ! LinkSourceFile(vgaFasm.h,EnhancedDir) ! ! ObjectFromSpecialSource(vgaseg,vgaline,-DPOLYSEGMENT) ! ObjectFromSpecialSource(vgasegd,vgalined,-DPOLYSEGMENT) ! ObjectFromSpecialSource(vgaglrop8,vgaglblt8,-DGLYPHROP) ! SpecialObjectRule(vgaglblt8.o,vgaglblt8.c,$(STIPPLEDEF)) ! ! ObjectFromSpecialSource(vgalineS,vgaline,$(SUDEFINE)) ! ObjectFromSpecialSource(vgasegS,vgaline,$(SUDEFINE) -DPOLYSEGMENT) ! ObjectFromSpecialSource(vgateblt8S,vgateblt8,$(SUDEFINE)) ! ObjectFromSpecialSource(vgarctstp8S,vgarctstp8,$(SUDEFINE)) ! ! ObjectFromSpecialSource(vgafillarcC,vgafillarc,-DRROP=GXcopy) ! ObjectFromSpecialSource(vgafillarcG,vgafillarc,-DRROP=GXset) ! ! ObjectFromSpecialSource(vgazerarcC,vgazerarc,-DRROP=GXcopy) ! ObjectFromSpecialSource(vgazerarcX,vgazerarc,-DRROP=GXxor) ! ObjectFromSpecialSource(vgazerarcG,vgazerarc,-DRROP=GXset) ! ! ObjectFromSpecialSource(vgabltCS,vgablt,-DMROP=Mcopy $(SUDEFINE)) ! ObjectFromSpecialSource(vgabltX,vgablt,-DMROP=Mxor) ! ObjectFromSpecialSource(vgabltO,vgablt,-DMROP=Mor) ! ObjectFromSpecialSource(vgabltG,vgablt,-DMROP=0) ! ! ObjectFromSpecialSource(vgasolidC,vgasolid,-DRROP=GXcopy) ! ObjectFromSpecialSource(vgasolidCS,vgasolid,-DRROP=GXcopy $(SUDEFINE)) ! ObjectFromSpecialSource(vgasolidX,vgasolid,-DRROP=GXxor) ! ObjectFromSpecialSource(vgasolidO,vgasolid,-DRROP=GXor) ! ObjectFromSpecialSource(vgasolidA,vgasolid,-DRROP=GXand) ! ObjectFromSpecialSource(vgasolidG,vgasolid,-DRROP=GXset) ! ! ObjectFromSpecialSource(vgatile32C,vgatile32,-DMROP=Mcopy) ! ObjectFromSpecialSource(vgatile32G,vgatile32,-DMROP=0) ! ! ObjectFromSpecialSource(vgatileoddC,vgatileodd,-DMROP=Mcopy) ! ObjectFromSpecialSource(vgatileoddG,vgatileodd,-DMROP=0) ! ! ObjectFromSpecialSource(vgaply1rctC,vgaply1rct,-DRROP=GXcopy) ! ObjectFromSpecialSource(vgaply1rctG,vgaply1rct,-DRROP=GXset) ! ! #ifdef i386Architecture ! ObjectFromSpecialAsmSource(fFillAnd,fFill,-DRROP=GXAnd) ! ObjectFromSpecialAsmSource(fFillCopy,fFill,-DRROP=GXCopy) ! ObjectFromSpecialAsmSource(fFillOr,fFill,-DRROP=GXOr) ! ObjectFromSpecialAsmSource(fFillXor,fFill,-DRROP=GXXor) ! #endif ! ! InstallLinkKitNonExecFile(vga.h,$(XF98LINKKITDIR)/drivers98) ! InstallLinkKitNonExecFile(vgaBank.h,$(XF98LINKKITDIR)/drivers98) ! #ifndef DontInstallPC98Version ! InstallLinkKitNonExecFile(vga.h,$(XF98LINKKITDIR)/include) ! InstallLinkKitNonExecFile(vga256.h,$(XF98LINKKITDIR)/include) ! InstallLinkKitNonExecFile(vgaFasm.h,$(XF98LINKKITDIR)/include) ! InstallLinkKitNonExecFile(vgaHW.c,$(XF98LINKKITDIR)/VGADriverDoc) ! InstallLinkKitNonExecFile(vgaPCI.h,$(XF98LINKKITDIR)/include) ! #endif ! ! #ifndef OS2Architecture ! DependTarget() ! #endif --- 1,10 ---- ! XCOMM $TOG: Imakefile /main/11 1998/03/06 14:15:43 kaleb $ + XCOMM $XFree86: xc/programs/Xserver/hw/xfree98/vga256/nec480/Imakefile,v 3.9.2.2 1998/02/01 22:08:18 robin Exp $ + #define VGADEFINES -DPC98_NEC480 ! #include "../Imakefile.vga" *** ./programs/Xserver/hw/xfree98/vga256/nkvnec/Imakefile@@/PUBLIC-LATEST Sun Jul 20 13:54:23 1997 --- xc/programs/Xserver/hw/xfree98/vga256/nkvnec/Imakefile Fri Mar 6 14:14:11 1998 *************** *** 1,220 **** ! XCOMM $TOG: Imakefile /main/11 1997/07/20 13:54:24 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree98/vga256/nkvnec/Imakefile,v 3.11 1996/12/23 07:08:55 dawes Exp $ ! #include <Server.tmpl> ! ! #ifdef i386Architecture ! FSRCS = fBitBlt.s fFillCopy.s fFillOr.s fFillAnd.s \ ! fFillXor.s fFillSet.s vgabres.s vgalineH.s vgalineV.s ! BSRCS = BitBlt.s BitBlt2.s Box.s Line.s VHLine.s vgaBank.s ! ! FOBJS = fBitBlt.o fFillCopy.o fFillOr.o fFillAnd.o \ ! fFillXor.o fFillSet.o vgabres.o vgalineH.o vgalineV.o ! BOBJS = BitBlt.o BitBlt2.o Box.o Line.o VHLine.o vgaBank.o ! #else ! FSRCS = vgaBltFillc.c vgaLinec.c ! BSRCS = vgaBankc.c ! ! FOBJS = vgaBltFillc.o vgaLinec.o ! BOBJS = vgaBankc.o ! #endif ! ! SRCS = vgagc.c vgawindow.c vgascrinit.c \ ! vgapntwin.c vgapwinS.c vgabitblt.c \ ! vgafillsp.c vgasetsp.c vgaimage.c \ ! vgagetsp.c vgafillrct.c vgaBitBlt1.c \ ! vgasolidC.c vgasolidCS.c vgasolidX.c \ ! vgasolidO.c vgasolidA.c vgasolidG.c \ ! vgatile32C.c vgatile32G.c \ ! vgatileoddC.c vgatileoddG.c \ ! vgazerarcC.c vgazerarcX.c vgazerarcG.c \ ! vgafillarcC.c vgafillarcG.c \ ! vgategblt.c vgabstore.c vga8cppl.c \ ! vgabltC.c vgabltCS.c vgabltX.c vgabltO.c vgabltG.c \ ! vgateblt8.c vgateblt8S.c vgaglblt8.c vgaglrop8.c \ ! vgapush8.c vgarctstp8.c vgarctstp8S.c vgapolypnt.c \ ! vgaline.c vgalineS.c vgabresd.c \ ! vgalined.c vgasegd.c vgaseg.c vgasegS.c \ ! vgaply1rctC.c vgaply1rctG.c vgafuncs.c \ ! SpeedUpBlt.c $(BSRCS) \ ! vgaBanks.c $(FSRCS) vgaHW.c vga.c vgaCmap.c \ ! vgaPCI.c vgatables.c ! ! FOBJS = fBitBlt.o fFillCopy.o fFillXor.o fFillOr.o fFillAnd.o \ ! fFillSet.o vgabres.o vgalineH.o vgalineV.o ! ! OBJS = vgagc.o vgawindow.o vgascrinit.o \ ! vgagetsp.o vgafillrct.o vgaimage.o \ ! vgasolidC.o vgasolidCS.o vgasolidX.o \ ! vgasolidO.o vgasolidA.o vgasolidG.o \ ! vgatile32C.o vgatile32G.o \ ! vgatileoddC.o vgatileoddG.o \ ! vgafillsp.o vgasetsp.o \ ! vgapntwin.o vgapwinS.o vgaBitBlt1.o \ ! vgazerarcC.o vgazerarcX.o vgazerarcG.o \ ! vgafillarcC.o vgafillarcG.o \ ! vgategblt.o vgabstore.o vga8cppl.o \ ! vgateblt8.o vgateblt8S.o vgaglblt8.o vgaglrop8.o \ ! vgarctstp8.o vgarctstp8S.o vgapolypnt.o \ ! vgaline.o vgalineS.o vgabresd.o \ ! vgalined.o vgasegd.o vgaseg.o vgasegS.o \ ! vgabitblt.o vgabltC.o vgabltCS.o vgabltX.o \ ! vgabltO.o vgabltG.o \ ! vgapush8.o vgaply1rctC.o vgaply1rctG.o $(STIPPLEOBJ) vgafuncs.o \ ! SpeedUpBlt.o $(BOBJS) \ ! vgaBanks.o $(FOBJS) vgaHW.o vga.o vgaCmap.o \ ! vgaPCI.o vgatables.o ! ! INCLUDES = -I. -I$(XF98COMSRC) -I$(XF86OSSRC) -I$(XF86HWSRC) \ ! -I$(SERVERSRC)/cfb -I$(SERVERSRC)/mfb -I$(SERVERSRC)/mi \ ! -I$(SERVERSRC)/include -I$(XINCLUDESRC) -I$(FONTINCSRC) \ ! -I$(XF86SRC)/xaa ! LINTLIBS = ../../../dix/llib-ldix.ln ../../../os/llib-los.ln \ ! ../../mfb/llib-lmfb.ln ../../mi/llib-lmi.ln ! ! #if DirtyStartup ! STARTUPDEFINES = -DDIRTY_STARTUP ! #endif ! ! DEFINES = $(SPEEDUPDEFINES) $(STARTUPDEFINES) -DPSZ=8 -DPC98 -DPC98_NKVNEC ! ! #ifdef i386Architecture ! SUDEFINE = -DSPEEDUP ! #endif ! ! SubdirLibraryRule($(OBJS)) ! NormalLibraryObjectRule() ! NormalAsmObjectRule() ! ! NormalLintTarget($(SRCS)) ! ! LinkSourceFile(Design,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vga.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vga.h,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vga256.h,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vga8cppl.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaAsm.h,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaBank.h,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaBank.s,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaCmap.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaHW.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaPCI.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaPCI.h,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgabitblt.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgablt.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgabltC.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgabresd.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgabstore.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgafillarc.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgafillrct.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgafillsp.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgafuncs.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgagc.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgagetsp.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaglblt8.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaimage.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaline.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgalined.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaply1rct.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgapntwin.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgapolypnt.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgapush8.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgapwinS.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgarctstp8.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgascrinit.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgasetsp.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgasolid.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgatables.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgateblt8.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgategblt.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgatile32.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgatileodd.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgawindow.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgazerarc.c,$(XF86SRC)/vga256/vga) ! ! #define EnhancedDir $(XF86SRC)/vga256/enhanced ! ! ObjectFromSpecialSource(vgaBanks,EnhancedDir/gBanks,NullParameter) ! #ifdef i386Architecture ! ObjectFromSpecialAsmSource(BitBlt,EnhancedDir/suBitBlt,NullParameter) ! ObjectFromSpecialAsmSource(BitBlt2,EnhancedDir/suBBlt2,NullParameter) ! ObjectFromSpecialAsmSource(Box,EnhancedDir/suBox,NullParameter) ! ObjectFromSpecialAsmSource(Line,EnhancedDir/suLine,NullParameter) ! ObjectFromSpecialAsmSource(VHLine,EnhancedDir/suVHLine,NullParameter) ! ObjectFromSpecialAsmSource(vgabres,EnhancedDir/fLineBres,NullParameter) ! ObjectFromSpecialAsmSource(vgalineH,EnhancedDir/fLineH,NullParameter) ! ObjectFromSpecialAsmSource(vgalineV,EnhancedDir/fLineV,NullParameter) ! LinkSourceFile(fBitBlt.s,EnhancedDir) ! LinkSourceFile(fFill.s,EnhancedDir) ! LinkSourceFile(fFillSet.s,EnhancedDir) ! #else ! LinkSourceFile(vgaBltFillc.c,EnhancedDir) ! LinkSourceFile(vgaLinec.c,EnhancedDir) ! #endif ! LinkFile(vgaBitBlt1.c,EnhancedDir/vgaBitBlt.c) ! LinkSourceFile(SpeedUpBlt.c,EnhancedDir) ! LinkSourceFile(vgaFasm.h,EnhancedDir) ! ! ObjectFromSpecialSource(vgaseg,vgaline,-DPOLYSEGMENT) ! ObjectFromSpecialSource(vgasegd,vgalined,-DPOLYSEGMENT) ! ObjectFromSpecialSource(vgaglrop8,vgaglblt8,-DGLYPHROP) ! SpecialObjectRule(vgaglblt8.o,vgaglblt8.c,$(STIPPLEDEF)) ! ! ObjectFromSpecialSource(vgalineS,vgaline,$(SUDEFINE)) ! ObjectFromSpecialSource(vgasegS,vgaline,$(SUDEFINE) -DPOLYSEGMENT) ! ObjectFromSpecialSource(vgateblt8S,vgateblt8,$(SUDEFINE)) ! ObjectFromSpecialSource(vgarctstp8S,vgarctstp8,$(SUDEFINE)) ! ! ObjectFromSpecialSource(vgafillarcC,vgafillarc,-DRROP=GXcopy) ! ObjectFromSpecialSource(vgafillarcG,vgafillarc,-DRROP=GXset) ! ! ObjectFromSpecialSource(vgazerarcC,vgazerarc,-DRROP=GXcopy) ! ObjectFromSpecialSource(vgazerarcX,vgazerarc,-DRROP=GXxor) ! ObjectFromSpecialSource(vgazerarcG,vgazerarc,-DRROP=GXset) ! ! ObjectFromSpecialSource(vgabltCS,vgablt,-DMROP=Mcopy $(SUDEFINE)) ! ObjectFromSpecialSource(vgabltX,vgablt,-DMROP=Mxor) ! ObjectFromSpecialSource(vgabltO,vgablt,-DMROP=Mor) ! ObjectFromSpecialSource(vgabltG,vgablt,-DMROP=0) ! ! ObjectFromSpecialSource(vgasolidC,vgasolid,-DRROP=GXcopy) ! ObjectFromSpecialSource(vgasolidCS,vgasolid,-DRROP=GXcopy $(SUDEFINE)) ! ObjectFromSpecialSource(vgasolidX,vgasolid,-DRROP=GXxor) ! ObjectFromSpecialSource(vgasolidO,vgasolid,-DRROP=GXor) ! ObjectFromSpecialSource(vgasolidA,vgasolid,-DRROP=GXand) ! ObjectFromSpecialSource(vgasolidG,vgasolid,-DRROP=GXset) ! ! ObjectFromSpecialSource(vgatile32C,vgatile32,-DMROP=Mcopy) ! ObjectFromSpecialSource(vgatile32G,vgatile32,-DMROP=0) ! ! ObjectFromSpecialSource(vgatileoddC,vgatileodd,-DMROP=Mcopy) ! ObjectFromSpecialSource(vgatileoddG,vgatileodd,-DMROP=0) ! ! ObjectFromSpecialSource(vgaply1rctC,vgaply1rct,-DRROP=GXcopy) ! ObjectFromSpecialSource(vgaply1rctG,vgaply1rct,-DRROP=GXset) ! ! #ifdef i386Architecture ! ObjectFromSpecialAsmSource(fFillAnd,fFill,-DRROP=GXAnd) ! ObjectFromSpecialAsmSource(fFillCopy,fFill,-DRROP=GXCopy) ! ObjectFromSpecialAsmSource(fFillOr,fFill,-DRROP=GXOr) ! ObjectFromSpecialAsmSource(fFillXor,fFill,-DRROP=GXXor) ! #endif ! ! InstallLinkKitNonExecFile(vga.h,$(XF98LINKKITDIR)/drivers98) ! InstallLinkKitNonExecFile(vgaBank.h,$(XF98LINKKITDIR)/drivers98) ! #ifndef DontInstallPC98Version ! InstallLinkKitNonExecFile(vga.h,$(XF98LINKKITDIR)/include) ! InstallLinkKitNonExecFile(vga256.h,$(XF98LINKKITDIR)/include) ! InstallLinkKitNonExecFile(vgaFasm.h,$(XF98LINKKITDIR)/include) ! InstallLinkKitNonExecFile(vgaHW.c,$(XF98LINKKITDIR)/VGADriverDoc) ! InstallLinkKitNonExecFile(vgaPCI.h,$(XF98LINKKITDIR)/include) ! #endif ! ! #ifndef OS2Architecture ! DependTarget() ! #endif --- 1,10 ---- ! XCOMM $TOG: Imakefile /main/12 1998/03/06 14:15:48 kaleb $ + XCOMM $XFree86: xc/programs/Xserver/hw/xfree98/vga256/nkvnec/Imakefile,v 3.11.2.2 1998/02/01 22:08:19 robin Exp $ + #define VGADEFINES -DPC98_NKVNEC ! #include "../Imakefile.vga" *** /dev/null Tue Jun 30 11:51:45 1998 --- xc/programs/Xserver/hw/xfree98/vga256/svga/Imakefile Fri Mar 6 14:14:15 1998 *************** *** 0 **** --- 1,10 ---- + XCOMM $TOG: Imakefile /main/1 1998/03/06 14:15:53 kaleb $ + + + + + XCOMM $XFree86: xc/programs/Xserver/hw/xfree98/vga256/svga/Imakefile,v 1.2.2.2 1998/02/01 22:08:19 robin Exp $ + + #define VGADEFINES -DPC98_SVGA + + #include "../Imakefile.vga" *** ./programs/Xserver/hw/xfree98/vga256/trident/Imakefile@@/PUBLIC-LATEST Sun Jul 20 13:54:28 1997 --- xc/programs/Xserver/hw/xfree98/vga256/trident/Imakefile Fri Mar 6 14:14:20 1998 *************** *** 1,214 **** ! XCOMM $TOG: Imakefile /main/6 1997/07/20 13:54:29 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree98/vga256/trident/Imakefile,v 3.6 1996/12/24 02:27:05 dawes Exp $ ! #include <Server.tmpl> - #ifdef i386Architecture - FSRCS = fBitBlt.s fFillCopy.s fFillOr.s fFillAnd.s \ - fFillXor.s fFillSet.s vgabres.s vgalineH.s vgalineV.s - BSRCS = BitBlt.s BitBlt2.s Box.s Line.s VHLine.s vgaBank.s - FOBJS = fBitBlt.o fFillCopy.o fFillOr.o fFillAnd.o \ - fFillXor.o fFillSet.o vgabres.o vgalineH.o vgalineV.o - BOBJS = BitBlt.o BitBlt2.o Box.o Line.o VHLine.o vgaBank.o - #else - FSRCS = vgaBltFillc.c vgaLinec.c - BSRCS = vgaBankc.c - FOBJS = vgaBltFillc.o vgaLinec.o - BOBJS = vgaBankc.o - #endif ! SRCS = vgagc.c vgawindow.c vgascrinit.c \ ! vgapntwin.c vgapwinS.c vgabitblt.c \ ! vgafillsp.c vgasetsp.c vgaimage.c \ ! vgagetsp.c vgafillrct.c vgaBitBlt1.c \ ! vgasolidC.c vgasolidCS.c vgasolidX.c \ ! vgasolidO.c vgasolidA.c vgasolidG.c \ ! vgatile32C.c vgatile32G.c \ ! vgatileoddC.c vgatileoddG.c \ ! vgazerarcC.c vgazerarcX.c vgazerarcG.c \ ! vgafillarcC.c vgafillarcG.c \ ! vgategblt.c vgabstore.c vga8cppl.c \ ! vgabltC.c vgabltCS.c vgabltX.c vgabltO.c vgabltG.c \ ! vgateblt8.c vgateblt8S.c vgaglblt8.c vgaglrop8.c \ ! vgapush8.c vgarctstp8.c vgarctstp8S.c vgapolypnt.c \ ! vgaline.c vgalineS.c vgabresd.c \ ! vgalined.c vgasegd.c vgaseg.c vgasegS.c \ ! vgaply1rctC.c vgaply1rctG.c vgafuncs.c \ ! SpeedUpBlt.c $(BSRCS) \ ! vgaBanks.c $(FSRCS) vgaHW.c vga.c vgaCmap.c \ ! vgaPCI.c vgatables.c ! FOBJS = fBitBlt.o fFillCopy.o fFillXor.o fFillOr.o fFillAnd.o \ ! fFillSet.o vgabres.o vgalineH.o vgalineV.o ! OBJS = vgagc.o vgawindow.o vgascrinit.o \ ! vgagetsp.o vgafillrct.o vgaimage.o \ ! vgasolidC.o vgasolidCS.o vgasolidX.o \ ! vgasolidO.o vgasolidA.o vgasolidG.o \ ! vgatile32C.o vgatile32G.o \ ! vgatileoddC.o vgatileoddG.o \ ! vgafillsp.o vgasetsp.o \ ! vgapntwin.o vgapwinS.o vgaBitBlt1.o \ ! vgazerarcC.o vgazerarcX.o vgazerarcG.o \ ! vgafillarcC.o vgafillarcG.o \ ! vgategblt.o vgabstore.o vga8cppl.o \ ! vgateblt8.o vgateblt8S.o vgaglblt8.o vgaglrop8.o \ ! vgarctstp8.o vgarctstp8S.o vgapolypnt.o \ ! vgaline.o vgalineS.o vgabresd.o \ ! vgalined.o vgasegd.o vgaseg.o vgasegS.o \ ! vgabitblt.o vgabltC.o vgabltCS.o vgabltX.o \ ! vgabltO.o vgabltG.o \ ! vgapush8.o vgaply1rctC.o vgaply1rctG.o $(STIPPLEOBJ) vgafuncs.o \ ! SpeedUpBlt.o $(BOBJS) \ ! vgaBanks.o $(FOBJS) vgaHW.o vga.o vgaCmap.o \ ! vgaPCI.o vgatables.o ! ! INCLUDES = -I. -I$(XF98COMSRC) -I$(XF86OSSRC) -I$(XF86HWSRC) \ ! -I$(SERVERSRC)/cfb -I$(SERVERSRC)/mfb -I$(SERVERSRC)/mi \ ! -I$(SERVERSRC)/include -I$(XINCLUDESRC) -I$(FONTINCSRC) \ ! -I$(XF86SRC)/xaa ! LINTLIBS = ../../../dix/llib-ldix.ln ../../../os/llib-los.ln \ ! ../../mfb/llib-lmfb.ln ../../mi/llib-lmi.ln ! ! #if DirtyStartup ! STARTUPDEFINES = -DDIRTY_STARTUP ! #endif ! ! DEFINES = $(SPEEDUPDEFINES) $(STARTUPDEFINES) -DPSZ=8 -DPC98 -DPC98_TGUI ! ! #ifdef i386Architecture ! SUDEFINE = -DSPEEDUP ! #endif ! ! SubdirLibraryRule($(OBJS)) ! NormalLibraryObjectRule() ! NormalAsmObjectRule() ! ! NormalLintTarget($(SRCS)) ! ! LinkSourceFile(Design,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vga.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vga.h,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vga256.h,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vga8cppl.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaAsm.h,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaBank.h,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaBank.s,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaCmap.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaHW.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaPCI.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaPCI.h,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgabitblt.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgablt.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgabltC.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgabresd.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgabstore.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgafillarc.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgafillrct.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgafillsp.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgafuncs.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgagc.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgagetsp.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaglblt8.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaimage.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaline.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgalined.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaply1rct.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgapntwin.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgapolypnt.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgapush8.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgapwinS.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgarctstp8.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgascrinit.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgasetsp.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgasolid.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgatables.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgateblt8.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgategblt.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgatile32.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgatileodd.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgawindow.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgazerarc.c,$(XF86SRC)/vga256/vga) ! ! #define EnhancedDir $(XF86SRC)/vga256/enhanced ! ! ObjectFromSpecialSource(vgaBanks,EnhancedDir/gBanks,NullParameter) ! #ifdef i386Architecture ! ObjectFromSpecialAsmSource(BitBlt,EnhancedDir/suBitBlt,NullParameter) ! ObjectFromSpecialAsmSource(BitBlt2,EnhancedDir/suBBlt2,NullParameter) ! ObjectFromSpecialAsmSource(Box,EnhancedDir/suBox,NullParameter) ! ObjectFromSpecialAsmSource(Line,EnhancedDir/suLine,NullParameter) ! ObjectFromSpecialAsmSource(VHLine,EnhancedDir/suVHLine,NullParameter) ! ObjectFromSpecialAsmSource(vgabres,EnhancedDir/fLineBres,NullParameter) ! ObjectFromSpecialAsmSource(vgalineH,EnhancedDir/fLineH,NullParameter) ! ObjectFromSpecialAsmSource(vgalineV,EnhancedDir/fLineV,NullParameter) ! LinkSourceFile(fBitBlt.s,EnhancedDir) ! LinkSourceFile(fFill.s,EnhancedDir) ! LinkSourceFile(fFillSet.s,EnhancedDir) ! #else ! LinkSourceFile(vgaBltFillc.c,EnhancedDir) ! LinkSourceFile(vgaLinec.c,EnhancedDir) ! #endif ! LinkFile(vgaBitBlt1.c,EnhancedDir/vgaBitBlt.c) ! LinkSourceFile(SpeedUpBlt.c,EnhancedDir) ! LinkSourceFile(vgaFasm.h,EnhancedDir) ! ! ObjectFromSpecialSource(vgaseg,vgaline,-DPOLYSEGMENT) ! ObjectFromSpecialSource(vgasegd,vgalined,-DPOLYSEGMENT) ! ObjectFromSpecialSource(vgaglrop8,vgaglblt8,-DGLYPHROP) ! SpecialObjectRule(vgaglblt8.o,vgaglblt8.c,$(STIPPLEDEF)) ! ! ObjectFromSpecialSource(vgalineS,vgaline,$(SUDEFINE)) ! ObjectFromSpecialSource(vgasegS,vgaline,$(SUDEFINE) -DPOLYSEGMENT) ! ObjectFromSpecialSource(vgateblt8S,vgateblt8,$(SUDEFINE)) ! ObjectFromSpecialSource(vgarctstp8S,vgarctstp8,$(SUDEFINE)) ! ! ObjectFromSpecialSource(vgafillarcC,vgafillarc,-DRROP=GXcopy) ! ObjectFromSpecialSource(vgafillarcG,vgafillarc,-DRROP=GXset) ! ! ObjectFromSpecialSource(vgazerarcC,vgazerarc,-DRROP=GXcopy) ! ObjectFromSpecialSource(vgazerarcX,vgazerarc,-DRROP=GXxor) ! ObjectFromSpecialSource(vgazerarcG,vgazerarc,-DRROP=GXset) ! ! ObjectFromSpecialSource(vgabltCS,vgablt,-DMROP=Mcopy $(SUDEFINE)) ! ObjectFromSpecialSource(vgabltX,vgablt,-DMROP=Mxor) ! ObjectFromSpecialSource(vgabltO,vgablt,-DMROP=Mor) ! ObjectFromSpecialSource(vgabltG,vgablt,-DMROP=0) ! ! ObjectFromSpecialSource(vgasolidC,vgasolid,-DRROP=GXcopy) ! ObjectFromSpecialSource(vgasolidCS,vgasolid,-DRROP=GXcopy $(SUDEFINE)) ! ObjectFromSpecialSource(vgasolidX,vgasolid,-DRROP=GXxor) ! ObjectFromSpecialSource(vgasolidO,vgasolid,-DRROP=GXor) ! ObjectFromSpecialSource(vgasolidA,vgasolid,-DRROP=GXand) ! ObjectFromSpecialSource(vgasolidG,vgasolid,-DRROP=GXset) ! ! ObjectFromSpecialSource(vgatile32C,vgatile32,-DMROP=Mcopy) ! ObjectFromSpecialSource(vgatile32G,vgatile32,-DMROP=0) ! ! ObjectFromSpecialSource(vgatileoddC,vgatileodd,-DMROP=Mcopy) ! ObjectFromSpecialSource(vgatileoddG,vgatileodd,-DMROP=0) ! ! ObjectFromSpecialSource(vgaply1rctC,vgaply1rct,-DRROP=GXcopy) ! ObjectFromSpecialSource(vgaply1rctG,vgaply1rct,-DRROP=GXset) ! ! #ifdef i386Architecture ! ObjectFromSpecialAsmSource(fFillAnd,fFill,-DRROP=GXAnd) ! ObjectFromSpecialAsmSource(fFillCopy,fFill,-DRROP=GXCopy) ! ObjectFromSpecialAsmSource(fFillOr,fFill,-DRROP=GXOr) ! ObjectFromSpecialAsmSource(fFillXor,fFill,-DRROP=GXXor) ! #endif ! ! InstallLinkKitNonExecFile(vga.h,$(XF98LINKKITDIR)/drivers98) ! InstallLinkKitNonExecFile(vgaBank.h,$(XF98LINKKITDIR)/drivers98) ! #ifndef DontInstallPC98Version ! InstallLinkKitNonExecFile(vga.h,$(XF98LINKKITDIR)/include) ! InstallLinkKitNonExecFile(vga256.h,$(XF98LINKKITDIR)/include) ! InstallLinkKitNonExecFile(vgaFasm.h,$(XF98LINKKITDIR)/include) ! InstallLinkKitNonExecFile(vgaHW.c,$(XF98LINKKITDIR)/VGADriverDoc) ! InstallLinkKitNonExecFile(vgaPCI.h,$(XF98LINKKITDIR)/include) ! #endif ! ! #ifndef OS2Architecture ! DependTarget() ! #endif --- 1,10 ---- ! XCOMM $TOG: Imakefile /main/7 1998/03/06 14:15:59 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree98/vga256/trident/Imakefile,v 3.6.2.2 1998/02/01 22:08:20 robin Exp $ ! #define VGADEFINES -DPC98_TGUI ! #include "../Imakefile.vga" *** ./programs/Xserver/hw/xfree98/vga256/wabep/Imakefile@@/PUBLIC-LATEST Sun Jul 20 13:54:37 1997 --- xc/programs/Xserver/hw/xfree98/vga256/wabep/Imakefile Fri Mar 6 14:14:26 1998 *************** *** 1,213 **** ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree98/vga256/wabep/Imakefile,v 3.6 1996/12/24 02:27:09 dawes Exp $ ! #include <Server.tmpl> ! #ifdef i386Architecture ! FSRCS = fBitBlt.s fFillCopy.s fFillOr.s fFillAnd.s \ ! fFillXor.s fFillSet.s vgabres.s vgalineH.s vgalineV.s ! BSRCS = BitBlt.s BitBlt2.s Box.s Line.s VHLine.s vgaBank.s ! FOBJS = fBitBlt.o fFillCopy.o fFillOr.o fFillAnd.o \ ! fFillXor.o fFillSet.o vgabres.o vgalineH.o vgalineV.o ! BOBJS = BitBlt.o BitBlt2.o Box.o Line.o VHLine.o vgaBank.o ! #else ! FSRCS = vgaBltFillc.c vgaLinec.c ! BSRCS = vgaBankc.c ! ! FOBJS = vgaBltFillc.o vgaLinec.o ! BOBJS = vgaBankc.o ! #endif ! ! SRCS = vgagc.c vgawindow.c vgascrinit.c \ ! vgapntwin.c vgapwinS.c vgabitblt.c \ ! vgafillsp.c vgasetsp.c vgaimage.c \ ! vgagetsp.c vgafillrct.c vgaBitBlt1.c \ ! vgasolidC.c vgasolidCS.c vgasolidX.c \ ! vgasolidO.c vgasolidA.c vgasolidG.c \ ! vgatile32C.c vgatile32G.c \ ! vgatileoddC.c vgatileoddG.c \ ! vgazerarcC.c vgazerarcX.c vgazerarcG.c \ ! vgafillarcC.c vgafillarcG.c \ ! vgategblt.c vgabstore.c vga8cppl.c \ ! vgabltC.c vgabltCS.c vgabltX.c vgabltO.c vgabltG.c \ ! vgateblt8.c vgateblt8S.c vgaglblt8.c vgaglrop8.c \ ! vgapush8.c vgarctstp8.c vgarctstp8S.c vgapolypnt.c \ ! vgaline.c vgalineS.c vgabresd.c \ ! vgalined.c vgasegd.c vgaseg.c vgasegS.c \ ! vgaply1rctC.c vgaply1rctG.c vgafuncs.c \ ! SpeedUpBlt.c $(BSRCS) \ ! vgaBanks.c $(FSRCS) vgaHW.c vga.c vgaCmap.c \ ! vgaPCI.c vgatables.c ! ! FOBJS = fBitBlt.o fFillCopy.o fFillXor.o fFillOr.o fFillAnd.o \ ! fFillSet.o vgabres.o vgalineH.o vgalineV.o ! ! OBJS = vgagc.o vgawindow.o vgascrinit.o \ ! vgagetsp.o vgafillrct.o vgaimage.o \ ! vgasolidC.o vgasolidCS.o vgasolidX.o \ ! vgasolidO.o vgasolidA.o vgasolidG.o \ ! vgatile32C.o vgatile32G.o \ ! vgatileoddC.o vgatileoddG.o \ ! vgafillsp.o vgasetsp.o \ ! vgapntwin.o vgapwinS.o vgaBitBlt1.o \ ! vgazerarcC.o vgazerarcX.o vgazerarcG.o \ ! vgafillarcC.o vgafillarcG.o \ ! vgategblt.o vgabstore.o vga8cppl.o \ ! vgateblt8.o vgateblt8S.o vgaglblt8.o vgaglrop8.o \ ! vgarctstp8.o vgarctstp8S.o vgapolypnt.o \ ! vgaline.o vgalineS.o vgabresd.o \ ! vgalined.o vgasegd.o vgaseg.o vgasegS.o \ ! vgabitblt.o vgabltC.o vgabltCS.o vgabltX.o \ ! vgabltO.o vgabltG.o \ ! vgapush8.o vgaply1rctC.o vgaply1rctG.o $(STIPPLEOBJ) vgafuncs.o \ ! SpeedUpBlt.o $(BOBJS) \ ! vgaBanks.o $(FOBJS) vgaHW.o vga.o vgaCmap.o \ ! vgaPCI.o vgatables.o ! ! INCLUDES = -I. -I$(XF98COMSRC) -I$(XF86OSSRC) -I$(XF86HWSRC) \ ! -I$(SERVERSRC)/cfb -I$(SERVERSRC)/mfb -I$(SERVERSRC)/mi \ ! -I$(SERVERSRC)/include -I$(XINCLUDESRC) -I$(FONTINCSRC) \ ! -I$(XF86SRC)/xaa ! LINTLIBS = ../../../dix/llib-ldix.ln ../../../os/llib-los.ln \ ! ../../mfb/llib-lmfb.ln ../../mi/llib-lmi.ln ! ! #if DirtyStartup ! STARTUPDEFINES = -DDIRTY_STARTUP ! #endif ! ! DEFINES = $(SPEEDUPDEFINES) $(STARTUPDEFINES) -DPSZ=8 -DPC98 -DPC98_WABEP ! ! #ifdef i386Architecture ! SUDEFINE = -DSPEEDUP ! #endif ! ! SubdirLibraryRule($(OBJS)) ! NormalLibraryObjectRule() ! NormalAsmObjectRule() ! ! NormalLintTarget($(SRCS)) ! ! LinkSourceFile(Design,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vga.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vga.h,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vga256.h,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vga8cppl.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaAsm.h,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaBank.h,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaBank.s,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaCmap.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaHW.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaPCI.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaPCI.h,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgabitblt.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgablt.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgabltC.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgabresd.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgabstore.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgafillarc.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgafillrct.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgafillsp.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgafuncs.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgagc.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgagetsp.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaglblt8.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaimage.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaline.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgalined.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaply1rct.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgapntwin.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgapolypnt.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgapush8.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgapwinS.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgarctstp8.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgascrinit.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgasetsp.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgasolid.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgatables.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgateblt8.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgategblt.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgatile32.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgatileodd.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgawindow.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgazerarc.c,$(XF86SRC)/vga256/vga) ! ! #define EnhancedDir $(XF86SRC)/vga256/enhanced ! ! ObjectFromSpecialSource(vgaBanks,EnhancedDir/gBanks,NullParameter) ! #ifdef i386Architecture ! ObjectFromSpecialAsmSource(BitBlt,EnhancedDir/suBitBlt,NullParameter) ! ObjectFromSpecialAsmSource(BitBlt2,EnhancedDir/suBBlt2,NullParameter) ! ObjectFromSpecialAsmSource(Box,EnhancedDir/suBox,NullParameter) ! ObjectFromSpecialAsmSource(Line,EnhancedDir/suLine,NullParameter) ! ObjectFromSpecialAsmSource(VHLine,EnhancedDir/suVHLine,NullParameter) ! ObjectFromSpecialAsmSource(vgabres,EnhancedDir/fLineBres,NullParameter) ! ObjectFromSpecialAsmSource(vgalineH,EnhancedDir/fLineH,NullParameter) ! ObjectFromSpecialAsmSource(vgalineV,EnhancedDir/fLineV,NullParameter) ! LinkSourceFile(fBitBlt.s,EnhancedDir) ! LinkSourceFile(fFill.s,EnhancedDir) ! LinkSourceFile(fFillSet.s,EnhancedDir) ! #else ! LinkSourceFile(vgaBltFillc.c,EnhancedDir) ! LinkSourceFile(vgaLinec.c,EnhancedDir) ! #endif ! LinkFile(vgaBitBlt1.c,EnhancedDir/vgaBitBlt.c) ! LinkSourceFile(SpeedUpBlt.c,EnhancedDir) ! LinkSourceFile(vgaFasm.h,EnhancedDir) ! ! ObjectFromSpecialSource(vgaseg,vgaline,-DPOLYSEGMENT) ! ObjectFromSpecialSource(vgasegd,vgalined,-DPOLYSEGMENT) ! ObjectFromSpecialSource(vgaglrop8,vgaglblt8,-DGLYPHROP) ! SpecialObjectRule(vgaglblt8.o,vgaglblt8.c,$(STIPPLEDEF)) ! ! ObjectFromSpecialSource(vgalineS,vgaline,$(SUDEFINE)) ! ObjectFromSpecialSource(vgasegS,vgaline,$(SUDEFINE) -DPOLYSEGMENT) ! ObjectFromSpecialSource(vgateblt8S,vgateblt8,$(SUDEFINE)) ! ObjectFromSpecialSource(vgarctstp8S,vgarctstp8,$(SUDEFINE)) ! ! ObjectFromSpecialSource(vgafillarcC,vgafillarc,-DRROP=GXcopy) ! ObjectFromSpecialSource(vgafillarcG,vgafillarc,-DRROP=GXset) ! ! ObjectFromSpecialSource(vgazerarcC,vgazerarc,-DRROP=GXcopy) ! ObjectFromSpecialSource(vgazerarcX,vgazerarc,-DRROP=GXxor) ! ObjectFromSpecialSource(vgazerarcG,vgazerarc,-DRROP=GXset) ! ! ObjectFromSpecialSource(vgabltCS,vgablt,-DMROP=Mcopy $(SUDEFINE)) ! ObjectFromSpecialSource(vgabltX,vgablt,-DMROP=Mxor) ! ObjectFromSpecialSource(vgabltO,vgablt,-DMROP=Mor) ! ObjectFromSpecialSource(vgabltG,vgablt,-DMROP=0) ! ! ObjectFromSpecialSource(vgasolidC,vgasolid,-DRROP=GXcopy) ! ObjectFromSpecialSource(vgasolidCS,vgasolid,-DRROP=GXcopy $(SUDEFINE)) ! ObjectFromSpecialSource(vgasolidX,vgasolid,-DRROP=GXxor) ! ObjectFromSpecialSource(vgasolidO,vgasolid,-DRROP=GXor) ! ObjectFromSpecialSource(vgasolidA,vgasolid,-DRROP=GXand) ! ObjectFromSpecialSource(vgasolidG,vgasolid,-DRROP=GXset) ! ! ObjectFromSpecialSource(vgatile32C,vgatile32,-DMROP=Mcopy) ! ObjectFromSpecialSource(vgatile32G,vgatile32,-DMROP=0) ! ! ObjectFromSpecialSource(vgatileoddC,vgatileodd,-DMROP=Mcopy) ! ObjectFromSpecialSource(vgatileoddG,vgatileodd,-DMROP=0) ! ! ObjectFromSpecialSource(vgaply1rctC,vgaply1rct,-DRROP=GXcopy) ! ObjectFromSpecialSource(vgaply1rctG,vgaply1rct,-DRROP=GXset) ! ! #ifdef i386Architecture ! ObjectFromSpecialAsmSource(fFillAnd,fFill,-DRROP=GXAnd) ! ObjectFromSpecialAsmSource(fFillCopy,fFill,-DRROP=GXCopy) ! ObjectFromSpecialAsmSource(fFillOr,fFill,-DRROP=GXOr) ! ObjectFromSpecialAsmSource(fFillXor,fFill,-DRROP=GXXor) ! #endif ! ! InstallLinkKitNonExecFile(vga.h,$(XF98LINKKITDIR)/drivers98) ! InstallLinkKitNonExecFile(vgaBank.h,$(XF98LINKKITDIR)/drivers98) ! #ifndef DontInstallPC98Version ! InstallLinkKitNonExecFile(vga.h,$(XF98LINKKITDIR)/include) ! InstallLinkKitNonExecFile(vga256.h,$(XF98LINKKITDIR)/include) ! InstallLinkKitNonExecFile(vgaFasm.h,$(XF98LINKKITDIR)/include) ! InstallLinkKitNonExecFile(vgaHW.c,$(XF98LINKKITDIR)/VGADriverDoc) ! InstallLinkKitNonExecFile(vgaPCI.h,$(XF98LINKKITDIR)/include) ! #endif ! ! #ifndef OS2Architecture ! DependTarget() ! #endif --- 1,5 ---- ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree98/vga256/wabep/Imakefile,v 3.6.2.2 1998/02/01 22:08:20 robin Exp $ ! #define VGADEFINES -DPC98_WAP ! #include "../Imakefile.vga" *** ./programs/Xserver/hw/xfree98/vga256/wabs/Imakefile@@/PUBLIC-LATEST Sun Jul 20 13:54:41 1997 --- xc/programs/Xserver/hw/xfree98/vga256/wabs/Imakefile Fri Mar 6 14:14:32 1998 *************** *** 1,219 **** ! XCOMM $TOG: Imakefile /main/10 1997/07/20 13:54:43 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree98/vga256/wabs/Imakefile,v 3.10 1996/12/23 07:09:02 dawes Exp $ ! #include <Server.tmpl> ! #ifdef i386Architecture ! FSRCS = fBitBlt.s fFillCopy.s fFillOr.s fFillAnd.s \ ! fFillXor.s fFillSet.s vgabres.s vgalineH.s vgalineV.s ! BSRCS = BitBlt.s BitBlt2.s Box.s Line.s VHLine.s vgaBank.s ! ! FOBJS = fBitBlt.o fFillCopy.o fFillOr.o fFillAnd.o \ ! fFillXor.o fFillSet.o vgabres.o vgalineH.o vgalineV.o ! BOBJS = BitBlt.o BitBlt2.o Box.o Line.o VHLine.o vgaBank.o ! #else ! FSRCS = vgaBltFillc.c vgaLinec.c ! BSRCS = vgaBankc.c ! ! FOBJS = vgaBltFillc.o vgaLinec.o ! BOBJS = vgaBankc.o ! #endif ! ! SRCS = vgagc.c vgawindow.c vgascrinit.c \ ! vgapntwin.c vgapwinS.c vgabitblt.c \ ! vgafillsp.c vgasetsp.c vgaimage.c \ ! vgagetsp.c vgafillrct.c vgaBitBlt1.c \ ! vgasolidC.c vgasolidCS.c vgasolidX.c \ ! vgasolidO.c vgasolidA.c vgasolidG.c \ ! vgatile32C.c vgatile32G.c \ ! vgatileoddC.c vgatileoddG.c \ ! vgazerarcC.c vgazerarcX.c vgazerarcG.c \ ! vgafillarcC.c vgafillarcG.c \ ! vgategblt.c vgabstore.c vga8cppl.c \ ! vgabltC.c vgabltCS.c vgabltX.c vgabltO.c vgabltG.c \ ! vgateblt8.c vgateblt8S.c vgaglblt8.c vgaglrop8.c \ ! vgapush8.c vgarctstp8.c vgarctstp8S.c vgapolypnt.c \ ! vgaline.c vgalineS.c vgabresd.c \ ! vgalined.c vgasegd.c vgaseg.c vgasegS.c \ ! vgaply1rctC.c vgaply1rctG.c vgafuncs.c \ ! SpeedUpBlt.c $(BSRCS) \ ! vgaBanks.c $(FSRCS) vgaHW.c vga.c vgaCmap.c \ ! vgaPCI.c vgatables.c ! ! FOBJS = fBitBlt.o fFillCopy.o fFillXor.o fFillOr.o fFillAnd.o \ ! fFillSet.o vgabres.o vgalineH.o vgalineV.o ! ! OBJS = vgagc.o vgawindow.o vgascrinit.o \ ! vgagetsp.o vgafillrct.o vgaimage.o \ ! vgasolidC.o vgasolidCS.o vgasolidX.o \ ! vgasolidO.o vgasolidA.o vgasolidG.o \ ! vgatile32C.o vgatile32G.o \ ! vgatileoddC.o vgatileoddG.o \ ! vgafillsp.o vgasetsp.o \ ! vgapntwin.o vgapwinS.o vgaBitBlt1.o \ ! vgazerarcC.o vgazerarcX.o vgazerarcG.o \ ! vgafillarcC.o vgafillarcG.o \ ! vgategblt.o vgabstore.o vga8cppl.o \ ! vgateblt8.o vgateblt8S.o vgaglblt8.o vgaglrop8.o \ ! vgarctstp8.o vgarctstp8S.o vgapolypnt.o \ ! vgaline.o vgalineS.o vgabresd.o \ ! vgalined.o vgasegd.o vgaseg.o vgasegS.o \ ! vgabitblt.o vgabltC.o vgabltCS.o vgabltX.o \ ! vgabltO.o vgabltG.o \ ! vgapush8.o vgaply1rctC.o vgaply1rctG.o $(STIPPLEOBJ) vgafuncs.o \ ! SpeedUpBlt.o $(BOBJS) \ ! vgaBanks.o $(FOBJS) vgaHW.o vga.o vgaCmap.o \ ! vgaPCI.o vgatables.o ! ! INCLUDES = -I. -I$(XF98COMSRC) -I$(XF86OSSRC) -I$(XF86HWSRC) \ ! -I$(SERVERSRC)/cfb -I$(SERVERSRC)/mfb -I$(SERVERSRC)/mi \ ! -I$(SERVERSRC)/include -I$(XINCLUDESRC) -I$(FONTINCSRC) \ ! -I$(XF86SRC)/xaa ! LINTLIBS = ../../../dix/llib-ldix.ln ../../../os/llib-los.ln \ ! ../../mfb/llib-lmfb.ln ../../mi/llib-lmi.ln ! ! #if DirtyStartup ! STARTUPDEFINES = -DDIRTY_STARTUP ! #endif ! ! DEFINES = $(SPEEDUPDEFINES) $(STARTUPDEFINES) -DPSZ=8 -DPC98 -DPC98_WAB ! ! #ifdef i386Architecture ! SUDEFINE = -DSPEEDUP ! #endif ! ! SubdirLibraryRule($(OBJS)) ! NormalLibraryObjectRule() ! NormalAsmObjectRule() ! ! NormalLintTarget($(SRCS)) ! ! LinkSourceFile(Design,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vga.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vga.h,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vga256.h,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vga8cppl.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaAsm.h,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaBank.h,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaBank.s,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaCmap.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaHW.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaPCI.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaPCI.h,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgabitblt.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgablt.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgabltC.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgabresd.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgabstore.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgafillarc.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgafillrct.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgafillsp.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgafuncs.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgagc.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgagetsp.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaglblt8.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaimage.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaline.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgalined.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaply1rct.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgapntwin.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgapolypnt.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgapush8.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgapwinS.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgarctstp8.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgascrinit.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgasetsp.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgasolid.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgatables.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgateblt8.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgategblt.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgatile32.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgatileodd.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgawindow.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgazerarc.c,$(XF86SRC)/vga256/vga) ! ! #define EnhancedDir $(XF86SRC)/vga256/enhanced ! ! ObjectFromSpecialSource(vgaBanks,EnhancedDir/gBanks,NullParameter) ! #ifdef i386Architecture ! ObjectFromSpecialAsmSource(BitBlt,EnhancedDir/suBitBlt,NullParameter) ! ObjectFromSpecialAsmSource(BitBlt2,EnhancedDir/suBBlt2,NullParameter) ! ObjectFromSpecialAsmSource(Box,EnhancedDir/suBox,NullParameter) ! ObjectFromSpecialAsmSource(Line,EnhancedDir/suLine,NullParameter) ! ObjectFromSpecialAsmSource(VHLine,EnhancedDir/suVHLine,NullParameter) ! ObjectFromSpecialAsmSource(vgabres,EnhancedDir/fLineBres,NullParameter) ! ObjectFromSpecialAsmSource(vgalineH,EnhancedDir/fLineH,NullParameter) ! ObjectFromSpecialAsmSource(vgalineV,EnhancedDir/fLineV,NullParameter) ! LinkSourceFile(fBitBlt.s,EnhancedDir) ! LinkSourceFile(fFill.s,EnhancedDir) ! LinkSourceFile(fFillSet.s,EnhancedDir) ! #else ! LinkSourceFile(vgaBltFillc.c,EnhancedDir) ! LinkSourceFile(vgaLinec.c,EnhancedDir) ! #endif ! LinkFile(vgaBitBlt1.c,EnhancedDir/vgaBitBlt.c) ! LinkSourceFile(SpeedUpBlt.c,EnhancedDir) ! LinkSourceFile(vgaFasm.h,EnhancedDir) ! ! ObjectFromSpecialSource(vgaseg,vgaline,-DPOLYSEGMENT) ! ObjectFromSpecialSource(vgasegd,vgalined,-DPOLYSEGMENT) ! ObjectFromSpecialSource(vgaglrop8,vgaglblt8,-DGLYPHROP) ! SpecialObjectRule(vgaglblt8.o,vgaglblt8.c,$(STIPPLEDEF)) ! ! ObjectFromSpecialSource(vgalineS,vgaline,$(SUDEFINE)) ! ObjectFromSpecialSource(vgasegS,vgaline,$(SUDEFINE) -DPOLYSEGMENT) ! ObjectFromSpecialSource(vgateblt8S,vgateblt8,$(SUDEFINE)) ! ObjectFromSpecialSource(vgarctstp8S,vgarctstp8,$(SUDEFINE)) ! ! ObjectFromSpecialSource(vgafillarcC,vgafillarc,-DRROP=GXcopy) ! ObjectFromSpecialSource(vgafillarcG,vgafillarc,-DRROP=GXset) ! ! ObjectFromSpecialSource(vgazerarcC,vgazerarc,-DRROP=GXcopy) ! ObjectFromSpecialSource(vgazerarcX,vgazerarc,-DRROP=GXxor) ! ObjectFromSpecialSource(vgazerarcG,vgazerarc,-DRROP=GXset) ! ! ObjectFromSpecialSource(vgabltCS,vgablt,-DMROP=Mcopy $(SUDEFINE)) ! ObjectFromSpecialSource(vgabltX,vgablt,-DMROP=Mxor) ! ObjectFromSpecialSource(vgabltO,vgablt,-DMROP=Mor) ! ObjectFromSpecialSource(vgabltG,vgablt,-DMROP=0) ! ! ObjectFromSpecialSource(vgasolidC,vgasolid,-DRROP=GXcopy) ! ObjectFromSpecialSource(vgasolidCS,vgasolid,-DRROP=GXcopy $(SUDEFINE)) ! ObjectFromSpecialSource(vgasolidX,vgasolid,-DRROP=GXxor) ! ObjectFromSpecialSource(vgasolidO,vgasolid,-DRROP=GXor) ! ObjectFromSpecialSource(vgasolidA,vgasolid,-DRROP=GXand) ! ObjectFromSpecialSource(vgasolidG,vgasolid,-DRROP=GXset) ! ! ObjectFromSpecialSource(vgatile32C,vgatile32,-DMROP=Mcopy) ! ObjectFromSpecialSource(vgatile32G,vgatile32,-DMROP=0) ! ! ObjectFromSpecialSource(vgatileoddC,vgatileodd,-DMROP=Mcopy) ! ObjectFromSpecialSource(vgatileoddG,vgatileodd,-DMROP=0) ! ! ObjectFromSpecialSource(vgaply1rctC,vgaply1rct,-DRROP=GXcopy) ! ObjectFromSpecialSource(vgaply1rctG,vgaply1rct,-DRROP=GXset) ! ! #ifdef i386Architecture ! ObjectFromSpecialAsmSource(fFillAnd,fFill,-DRROP=GXAnd) ! ObjectFromSpecialAsmSource(fFillCopy,fFill,-DRROP=GXCopy) ! ObjectFromSpecialAsmSource(fFillOr,fFill,-DRROP=GXOr) ! ObjectFromSpecialAsmSource(fFillXor,fFill,-DRROP=GXXor) ! #endif ! ! InstallLinkKitNonExecFile(vga.h,$(XF98LINKKITDIR)/drivers98) ! InstallLinkKitNonExecFile(vgaBank.h,$(XF98LINKKITDIR)/drivers98) ! #ifndef DontInstallPC98Version ! InstallLinkKitNonExecFile(vga.h,$(XF98LINKKITDIR)/include) ! InstallLinkKitNonExecFile(vga256.h,$(XF98LINKKITDIR)/include) ! InstallLinkKitNonExecFile(vgaFasm.h,$(XF98LINKKITDIR)/include) ! InstallLinkKitNonExecFile(vgaHW.c,$(XF98LINKKITDIR)/VGADriverDoc) ! InstallLinkKitNonExecFile(vgaPCI.h,$(XF98LINKKITDIR)/include) ! #endif ! ! #ifndef OS2Architecture ! DependTarget() ! #endif --- 1,10 ---- ! XCOMM $TOG: Imakefile /main/11 1998/03/06 14:16:10 kaleb $ + XCOMM $XFree86: xc/programs/Xserver/hw/xfree98/vga256/wabs/Imakefile,v 3.10.2.2 1998/02/01 22:08:21 robin Exp $ ! #define VGADEFINES -DPC98_WABS ! #include "../Imakefile.vga" *** ./programs/Xserver/hw/xfree98/vga256/wsna/Imakefile@@/PUBLIC-LATEST Sun Jul 20 13:54:47 1997 --- xc/programs/Xserver/hw/xfree98/vga256/wsna/Imakefile Fri Mar 6 14:14:37 1998 *************** *** 1,213 **** ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree98/vga256/wsna/Imakefile,v 3.6 1996/12/24 02:27:14 dawes Exp $ ! #include <Server.tmpl> ! #ifdef i386Architecture ! FSRCS = fBitBlt.s fFillCopy.s fFillOr.s fFillAnd.s \ ! fFillXor.s fFillSet.s vgabres.s vgalineH.s vgalineV.s ! BSRCS = BitBlt.s BitBlt2.s Box.s Line.s VHLine.s vgaBank.s ! FOBJS = fBitBlt.o fFillCopy.o fFillOr.o fFillAnd.o \ ! fFillXor.o fFillSet.o vgabres.o vgalineH.o vgalineV.o ! BOBJS = BitBlt.o BitBlt2.o Box.o Line.o VHLine.o vgaBank.o ! #else ! FSRCS = vgaBltFillc.c vgaLinec.c ! BSRCS = vgaBankc.c ! ! FOBJS = vgaBltFillc.o vgaLinec.o ! BOBJS = vgaBankc.o ! #endif ! ! SRCS = vgagc.c vgawindow.c vgascrinit.c \ ! vgapntwin.c vgapwinS.c vgabitblt.c \ ! vgafillsp.c vgasetsp.c vgaimage.c \ ! vgagetsp.c vgafillrct.c vgaBitBlt1.c \ ! vgasolidC.c vgasolidCS.c vgasolidX.c \ ! vgasolidO.c vgasolidA.c vgasolidG.c \ ! vgatile32C.c vgatile32G.c \ ! vgatileoddC.c vgatileoddG.c \ ! vgazerarcC.c vgazerarcX.c vgazerarcG.c \ ! vgafillarcC.c vgafillarcG.c \ ! vgategblt.c vgabstore.c vga8cppl.c \ ! vgabltC.c vgabltCS.c vgabltX.c vgabltO.c vgabltG.c \ ! vgateblt8.c vgateblt8S.c vgaglblt8.c vgaglrop8.c \ ! vgapush8.c vgarctstp8.c vgarctstp8S.c vgapolypnt.c \ ! vgaline.c vgalineS.c vgabresd.c \ ! vgalined.c vgasegd.c vgaseg.c vgasegS.c \ ! vgaply1rctC.c vgaply1rctG.c vgafuncs.c \ ! SpeedUpBlt.c $(BSRCS) \ ! vgaBanks.c $(FSRCS) vgaHW.c vga.c vgaCmap.c \ ! vgaPCI.c vgatables.c ! ! FOBJS = fBitBlt.o fFillCopy.o fFillXor.o fFillOr.o fFillAnd.o \ ! fFillSet.o vgabres.o vgalineH.o vgalineV.o ! ! OBJS = vgagc.o vgawindow.o vgascrinit.o \ ! vgagetsp.o vgafillrct.o vgaimage.o \ ! vgasolidC.o vgasolidCS.o vgasolidX.o \ ! vgasolidO.o vgasolidA.o vgasolidG.o \ ! vgatile32C.o vgatile32G.o \ ! vgatileoddC.o vgatileoddG.o \ ! vgafillsp.o vgasetsp.o \ ! vgapntwin.o vgapwinS.o vgaBitBlt1.o \ ! vgazerarcC.o vgazerarcX.o vgazerarcG.o \ ! vgafillarcC.o vgafillarcG.o \ ! vgategblt.o vgabstore.o vga8cppl.o \ ! vgateblt8.o vgateblt8S.o vgaglblt8.o vgaglrop8.o \ ! vgarctstp8.o vgarctstp8S.o vgapolypnt.o \ ! vgaline.o vgalineS.o vgabresd.o \ ! vgalined.o vgasegd.o vgaseg.o vgasegS.o \ ! vgabitblt.o vgabltC.o vgabltCS.o vgabltX.o \ ! vgabltO.o vgabltG.o \ ! vgapush8.o vgaply1rctC.o vgaply1rctG.o $(STIPPLEOBJ) vgafuncs.o \ ! SpeedUpBlt.o $(BOBJS) \ ! vgaBanks.o $(FOBJS) vgaHW.o vga.o vgaCmap.o \ ! vgaPCI.o vgatables.o ! ! INCLUDES = -I. -I$(XF98COMSRC) -I$(XF86OSSRC) -I$(XF86HWSRC) \ ! -I$(SERVERSRC)/cfb -I$(SERVERSRC)/mfb -I$(SERVERSRC)/mi \ ! -I$(SERVERSRC)/include -I$(XINCLUDESRC) -I$(FONTINCSRC) \ ! -I$(XF86SRC)/xaa ! LINTLIBS = ../../../dix/llib-ldix.ln ../../../os/llib-los.ln \ ! ../../mfb/llib-lmfb.ln ../../mi/llib-lmi.ln ! ! #if DirtyStartup ! STARTUPDEFINES = -DDIRTY_STARTUP ! #endif ! ! DEFINES = $(SPEEDUPDEFINES) $(STARTUPDEFINES) -DPSZ=8 -DPC98 -DPC98_WSNA ! ! #ifdef i386Architecture ! SUDEFINE = -DSPEEDUP ! #endif ! ! SubdirLibraryRule($(OBJS)) ! NormalLibraryObjectRule() ! NormalAsmObjectRule() ! ! NormalLintTarget($(SRCS)) ! ! LinkSourceFile(Design,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vga.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vga.h,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vga256.h,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vga8cppl.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaAsm.h,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaBank.h,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaBank.s,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaCmap.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaHW.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaPCI.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaPCI.h,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgabitblt.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgablt.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgabltC.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgabresd.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgabstore.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgafillarc.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgafillrct.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgafillsp.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgafuncs.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgagc.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgagetsp.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaglblt8.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaimage.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaline.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgalined.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgaply1rct.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgapntwin.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgapolypnt.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgapush8.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgapwinS.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgarctstp8.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgascrinit.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgasetsp.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgasolid.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgatables.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgateblt8.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgategblt.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgatile32.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgatileodd.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgawindow.c,$(XF86SRC)/vga256/vga) ! LinkSourceFile(vgazerarc.c,$(XF86SRC)/vga256/vga) ! ! #define EnhancedDir $(XF86SRC)/vga256/enhanced ! ! ObjectFromSpecialSource(vgaBanks,EnhancedDir/gBanks,NullParameter) ! #ifdef i386Architecture ! ObjectFromSpecialAsmSource(BitBlt,EnhancedDir/suBitBlt,NullParameter) ! ObjectFromSpecialAsmSource(BitBlt2,EnhancedDir/suBBlt2,NullParameter) ! ObjectFromSpecialAsmSource(Box,EnhancedDir/suBox,NullParameter) ! ObjectFromSpecialAsmSource(Line,EnhancedDir/suLine,NullParameter) ! ObjectFromSpecialAsmSource(VHLine,EnhancedDir/suVHLine,NullParameter) ! ObjectFromSpecialAsmSource(vgabres,EnhancedDir/fLineBres,NullParameter) ! ObjectFromSpecialAsmSource(vgalineH,EnhancedDir/fLineH,NullParameter) ! ObjectFromSpecialAsmSource(vgalineV,EnhancedDir/fLineV,NullParameter) ! LinkSourceFile(fBitBlt.s,EnhancedDir) ! LinkSourceFile(fFill.s,EnhancedDir) ! LinkSourceFile(fFillSet.s,EnhancedDir) ! #else ! LinkSourceFile(vgaBltFillc.c,EnhancedDir) ! LinkSourceFile(vgaLinec.c,EnhancedDir) ! #endif ! LinkFile(vgaBitBlt1.c,EnhancedDir/vgaBitBlt.c) ! LinkSourceFile(SpeedUpBlt.c,EnhancedDir) ! LinkSourceFile(vgaFasm.h,EnhancedDir) ! ! ObjectFromSpecialSource(vgaseg,vgaline,-DPOLYSEGMENT) ! ObjectFromSpecialSource(vgasegd,vgalined,-DPOLYSEGMENT) ! ObjectFromSpecialSource(vgaglrop8,vgaglblt8,-DGLYPHROP) ! SpecialObjectRule(vgaglblt8.o,vgaglblt8.c,$(STIPPLEDEF)) ! ! ObjectFromSpecialSource(vgalineS,vgaline,$(SUDEFINE)) ! ObjectFromSpecialSource(vgasegS,vgaline,$(SUDEFINE) -DPOLYSEGMENT) ! ObjectFromSpecialSource(vgateblt8S,vgateblt8,$(SUDEFINE)) ! ObjectFromSpecialSource(vgarctstp8S,vgarctstp8,$(SUDEFINE)) ! ! ObjectFromSpecialSource(vgafillarcC,vgafillarc,-DRROP=GXcopy) ! ObjectFromSpecialSource(vgafillarcG,vgafillarc,-DRROP=GXset) ! ! ObjectFromSpecialSource(vgazerarcC,vgazerarc,-DRROP=GXcopy) ! ObjectFromSpecialSource(vgazerarcX,vgazerarc,-DRROP=GXxor) ! ObjectFromSpecialSource(vgazerarcG,vgazerarc,-DRROP=GXset) ! ! ObjectFromSpecialSource(vgabltCS,vgablt,-DMROP=Mcopy $(SUDEFINE)) ! ObjectFromSpecialSource(vgabltX,vgablt,-DMROP=Mxor) ! ObjectFromSpecialSource(vgabltO,vgablt,-DMROP=Mor) ! ObjectFromSpecialSource(vgabltG,vgablt,-DMROP=0) ! ! ObjectFromSpecialSource(vgasolidC,vgasolid,-DRROP=GXcopy) ! ObjectFromSpecialSource(vgasolidCS,vgasolid,-DRROP=GXcopy $(SUDEFINE)) ! ObjectFromSpecialSource(vgasolidX,vgasolid,-DRROP=GXxor) ! ObjectFromSpecialSource(vgasolidO,vgasolid,-DRROP=GXor) ! ObjectFromSpecialSource(vgasolidA,vgasolid,-DRROP=GXand) ! ObjectFromSpecialSource(vgasolidG,vgasolid,-DRROP=GXset) ! ! ObjectFromSpecialSource(vgatile32C,vgatile32,-DMROP=Mcopy) ! ObjectFromSpecialSource(vgatile32G,vgatile32,-DMROP=0) ! ! ObjectFromSpecialSource(vgatileoddC,vgatileodd,-DMROP=Mcopy) ! ObjectFromSpecialSource(vgatileoddG,vgatileodd,-DMROP=0) ! ! ObjectFromSpecialSource(vgaply1rctC,vgaply1rct,-DRROP=GXcopy) ! ObjectFromSpecialSource(vgaply1rctG,vgaply1rct,-DRROP=GXset) ! ! #ifdef i386Architecture ! ObjectFromSpecialAsmSource(fFillAnd,fFill,-DRROP=GXAnd) ! ObjectFromSpecialAsmSource(fFillCopy,fFill,-DRROP=GXCopy) ! ObjectFromSpecialAsmSource(fFillOr,fFill,-DRROP=GXOr) ! ObjectFromSpecialAsmSource(fFillXor,fFill,-DRROP=GXXor) ! #endif ! ! InstallLinkKitNonExecFile(vga.h,$(XF98LINKKITDIR)/drivers98) ! InstallLinkKitNonExecFile(vgaBank.h,$(XF98LINKKITDIR)/drivers98) ! #ifndef DontInstallPC98Version ! InstallLinkKitNonExecFile(vga.h,$(XF98LINKKITDIR)/include) ! InstallLinkKitNonExecFile(vga256.h,$(XF98LINKKITDIR)/include) ! InstallLinkKitNonExecFile(vgaFasm.h,$(XF98LINKKITDIR)/include) ! InstallLinkKitNonExecFile(vgaHW.c,$(XF98LINKKITDIR)/VGADriverDoc) ! InstallLinkKitNonExecFile(vgaPCI.h,$(XF98LINKKITDIR)/include) ! #endif ! ! #ifndef OS2Architecture ! DependTarget() ! #endif --- 1,5 ---- ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree98/vga256/wsna/Imakefile,v 3.6.2.2 1998/02/01 22:08:22 robin Exp $ ! #define VGADEFINES -DPC98_WSNA ! #include "../Imakefile.vga" *** ./programs/Xserver/hw/xfree98/xf86config/Imakefile@@/PUBLIC-LATEST Sun Jul 20 13:55:30 1997 --- xc/programs/Xserver/hw/xfree98/xf86config/Imakefile Fri Mar 6 14:14:53 1998 *************** *** 4,21 **** ! XCOMM $TOG: Imakefile /main/5 1997/07/20 13:55:31 kaleb $ SRCS = xf86config.c cards.c OBJS = xf86config.o cards.o LOCAL_LIBRARIES = DEPLIBS = ! CARDDBFILE = $(LIBDIR)/Cards DEFINES = -DCARD_DATABASE_FILE='"$(CARDDBFILE)"' -DXFREE98_XKB AllTarget(ProgramTargetName(xf98config)) - LinkSourceFile(Cards,$(XF86SRC)/xf86config) LinkSourceFile(cards.c,$(XF86SRC)/xf86config) LinkSourceFile(cards.h,$(XF86SRC)/xf86config) LinkSourceFile(xf86conf.man,$(XF86SRC)/xf86config) --- 4,20 ---- ! XCOMM $TOG: Imakefile /main/6 1998/03/06 14:16:31 kaleb $ SRCS = xf86config.c cards.c OBJS = xf86config.o cards.o LOCAL_LIBRARIES = DEPLIBS = ! CARDDBFILE = $(LIBDIR)/Cards98 DEFINES = -DCARD_DATABASE_FILE='"$(CARDDBFILE)"' -DXFREE98_XKB AllTarget(ProgramTargetName(xf98config)) LinkSourceFile(cards.c,$(XF86SRC)/xf86config) LinkSourceFile(cards.h,$(XF86SRC)/xf86config) LinkSourceFile(xf86conf.man,$(XF86SRC)/xf86config) *************** *** 25,31 **** InstallProgram(xf98config,$(BINDIR)) DependTarget() ! #ifndef DontInstallPC98Version ! InstallNonExecFile(Cards,$(LIBDIR)) ! #endif InstallManPageLong(xf86conf,$(MANDIR),xf98config) --- 24,28 ---- InstallProgram(xf98config,$(BINDIR)) DependTarget() ! InstallNonExecFile(Cards98,$(LIBDIR)) InstallManPageLong(xf86conf,$(MANDIR),xf98config) *** /dev/null Tue Jun 30 11:51:54 1998 --- xc/programs/Xserver/hw/xfree98/xf86config/Cards98 Fri Mar 6 14:14:49 1998 *************** *** 0 **** --- 1,509 ---- + # $XFree86: xc/programs/Xserver/hw/xfree98/xf86config/Cards98,v 1.3.2.2 1998/02/21 06:07:15 robin Exp $ + # + # + # + # $TOG: Cards98 /main/1 1998/03/06 14:16:27 kaleb $ + # This is the database of card definitions used by xf86config. + # Each definition should have a NAME entry, CHIPSET (descriptive) and + # SERVER (one of EGC, GANBWAP, PEGC, NKVNEC, WABS, WABEP, WSNA, TGUI, + # MGA, NECS3, PWSKB, PWLB, GA968). + # A reference to another definition is made with SEE (already defined + # entries are not overridden). + # Optional entries are RAMDAC (identifier), CLOCKCHIP (identifier), + # DACSPEED, NOCLOCKPROBE (advises never to probe clocks), UNSUPPORTED + # (indicates card that is not yet properly supported by a dedicated + # server). A LINE entry adds a line of text to be included in the + # Device section (can include options or comments). + # There's no CLOCKS option (although a Clocks line can be included + # with LINE), as it is very undesirable to have a Clocks line that + # is incorrect. The idea is that the Clocks are probed for to be + # sure (a commented suggested Clocks line can be included). + # + # The majority of entries are just a binding of a model name to a + # chipset/server and untested. + # + + # EGC + + NAME EGC16 + CHIPSET EGC + SERVER EGC + LINE Chipset "vga" + + # PEGC + + NAME PEGC + CHIPSET PEGC + SERVER NEC480 + LINE VideoRam 512 + LINE Clocks 31.5 + LINE # Virtual resolution for 640x400 + LINE # Clocks 28.322 + + # GANBWAP + + NAME GA-98NBI + CHIPSET CL-GD5434 + SERVER GANBWAP + LINE ClockChip "cirrus" + LINE Option "ga98nb1" + LINE # Option "mmio" + LINE # Option "sw_cursor" + + NAME GA-98NBII + CHIPSET CL-GD5434 + SERVER GANBWAP + LINE ClockChip "cirrus" + LINE Option "ga98nb2" + LINE # Option "mmio" + LINE # Option "sw_cursor" + + NAME GA-98NBIV + CHIPSET CL-GD5434 + SERVER GANBWAP + LINE ClockChip "cirrus" + LINE Option "ga98nb4" + LINE # Option "mmio" + LINE # Option "sw_cursor" + + NAME WAP-2000/4000 + CHIPSET CL-GD5434 + SERVER GANBWAP + LINE Option "wap" + LINE # Option "epsonmemwin" + + # NKVNEC + + NAME PCNKV/PCNKV2/NEC_CIRRUS + CHIPSET CL-GD5428/5429/5430 + SERVER NKVNEC + LINE # Option "fast_dram" + LINE VideoRam 1024 + + NAME PC9821Bf/U8W + LINE Option "nec_cirrus" + SEE PCNKV/PCNKV2/NEC_CIRRUS + + NAME PC9821Bp/U8W/U7W + LINE Option "nec_cirrus" + SEE PCNKV/PCNKV2/NEC_CIRRUS + + NAME PC9821Bs/U7W + LINE Option "nec_cirrus" + SEE PCNKV/PCNKV2/NEC_CIRRUS + + NAME PC9821Be/U7W + LINE Option "nec_cirrus" + SEE PCNKV/PCNKV2/NEC_CIRRUS + + NAME PC9821BA3/U2/W + LINE Option "nec_cirrus" + SEE PCNKV/PCNKV2/NEC_CIRRUS + + NAME PC9821BX3/U2/W + LINE Option "nec_cirrus" + SEE PCNKV/PCNKV2/NEC_CIRRUS + + NAME PC9821BX4/U2 + LINE Option "nec_cirrus" + SEE PCNKV/PCNKV2/NEC_CIRRUS + + NAME PC9821Cb + LINE Option "nec_cirrus" + SEE PCNKV/PCNKV2/NEC_CIRRUS + + NAME PC9821Ce + LINE Option "nec_cirrus" + SEE PCNKV/PCNKV2/NEC_CIRRUS + + NAME PC9821Cf + LINE Option "nec_cirrus" + SEE PCNKV/PCNKV2/NEC_CIRRUS + + NAME PC9821Ce2 + LINE Option "nec_cirrus" + SEE PCNKV/PCNKV2/NEC_CIRRUS + + NAME PC9821Cs + LINE Option "nec_cirrus" + SEE PCNKV/PCNKV2/NEC_CIRRUS + + NAME PC9821Cs2 + LINE Option "nec_cirrus" + SEE PCNKV/PCNKV2/NEC_CIRRUS + + NAME PC9821Cx + LINE Option "nec_cirrus" + SEE PCNKV/PCNKV2/NEC_CIRRUS + + NAME PC9821Cx2 + LINE Option "nec_cirrus" + SEE PCNKV/PCNKV2/NEC_CIRRUS + + NAME PC9821Nd + LINE Option "nec_cirrus" + SEE PCNKV/PCNKV2/NEC_CIRRUS + + NAME PC9821Ne2 + LINE Option "nec_cirrus" + SEE PCNKV/PCNKV2/NEC_CIRRUS + + NAME PC9821Nf + LINE Option "nec_cirrus" + SEE PCNKV/PCNKV2/NEC_CIRRUS + + NAME PC9821Np + LINE Option "nec_cirrus" + SEE PCNKV/PCNKV2/NEC_CIRRUS + + NAME PC9821Ns + LINE Option "nec_cirrus" + SEE PCNKV/PCNKV2/NEC_CIRRUS + + NAME PC486MR + SEE PCNKV/PCNKV2/NEC_CIRRUS + + NAME PC486MS + SEE PCNKV/PCNKV2/NEC_CIRRUS + + NAME PC486MU + SEE PCNKV/PCNKV2/NEC_CIRRUS + + NAME PC486MV + SEE PCNKV/PCNKV2/NEC_CIRRUS + + NAME PC586MV + SEE PCNKV/PCNKV2/NEC_CIRRUS + + NAME PC586RV + SEE PCNKV/PCNKV2/NEC_CIRRUS + + # WABS + + NAME WAB-S + CHIPSET CL-GD5426/5428 + SERVER WABS + LINE VideoRam 1024 + LINE # VideoRam 2048 + + NAME WAB-1000/2000 + CHIPSET CL-GD5428 + SERVER WABS + LINE VideoRam 1024 + LINE # VideoRam 2048 + + NAME WSR-E/G + SEE WAB-1000/2000 + + # WABEP + + NAME WAB-EP + CHIPSET CL-GD5428 + SERVER WABEP + LINE Option "med_dram" + + # WSNA + + NAME WSN-A2F + CHIPSET CL-GD5434 + SERVER WSNA + LINE Option "med_dram" + + # TGUI + + NAME NEC Trident + CHIPSET TGUI9680/9682 + SERVER TGUI + LINE Option "xaa_no_color_exp" + LINE # Option "noaccel" + LINE # Option "Linear" + LINE # Option "med_dram" + LINE # Option "hw_cursor" + + NAME PC9821Ra20/N + SEE NEC Trident + + NAME PC9821RaII23/N,W + SEE NEC Trident + + NAME PC9821Ra266/N,W + SEE NEC Trident + + NAME PC9821Rs20/B20 + SEE NEC Trident + + NAME PC9821RsII26/B40 + SEE NEC Trident + + NAME PC9821V13/M7 + SEE NEC Trident + + NAME PC9821V16/M7 + SEE NEC Trident + + NAME PC9821V20/M7 + SEE NEC Trident + + NAME PC9821Xa7/C,K + SEE NEC Trident + + NAME PC9821Xa9/C,K + SEE NEC Trident + + NAME PC9821Xa10/C,K + SEE NEC Trident + + NAME PC9821Xa12/C,K + SEE NEC Trident + + NAME PC9821Xa13/C,K,W + SEE NEC Trident + + NAME PC9821Xa16/R,W + SEE NEC Trident + + NAME PC9821Xa20/W + SEE NEC Trident + + NAME PC9821Xc13/M,S + SEE NEC Trident + + NAME PC9821Xv13/R + SEE NEC Trident + + NAME GA-DRV/98 + CHIPSET TGUI9680 + SERVER TGUI + LINE Option "noaccel" + LINE # Option "med_dram" + LINE # Option "hw_cursor" + + # MGA + + NAME MGA Millennium + CHIPSET MGA2064W + SERVER MGA + + NAME PC9821Xt13 + SEE MGA Millennium + + NAME PC9821Xt16 + SEE MGA Millennium + + NAME PC9821Xv13/W + SEE MGA Millennium + + NAME PC9821Xv20/W + SEE MGA Millennium + + NAME PC9821St15 + SEE MGA Millennium + + NAME PC9821St20 + SEE MGA Millennium + + NAME PC9821RvII26/N20 + SEE MGA Millennium + + NAME NEC FC-WAB-X2 + SEE MGA Millennium + + NAME MGA Mystique + CHIPSET MGA1064SG + SERVER MGA + + NAME PC9821V166/S + SEE MGA Mystique + + NAME PC9821V200/M,S + SEE MGA Mystique + + NAME PC9821V233/M7,M7V + SEE MGA Mystique + + # NECS3 + + NAME NEC WAB-A/B + CHIPSET S3 928 + SERVER NECS3 + LINE Chipset "s3_generic" + LINE Dacspeed 110 + LINE Ramdac "sc15025" + LINE Option "dac_8_bit" + LINE # Option "necwab" + LINE # Option "nomemaccess" + LINE Clocks 25.0 28.0 40.0 0.0 50.0 77.0 36.0 45.0 + LINE Clocks 130.0 120.0 80.0 31.0 110.0 65.0 75.0 94.0 + + NAME NEC FC-WAB-A/B + CHIPSET S3 928 + SERVER NECS3 + LINE Chipset "s3_generic" + LINE Dacspeed 110 + LINE Ramdac "bt485" + LINE Option "necwab" + LINE Option "nomemaccess" + LINE Option "noinit" + LINE Option "nolinear" + LINE Clocks 25.0 28.0 40.0 0.0 50.0 77.0 36.0 45.0 + LINE Clocks 130.0 120.0 80.0 31.0 110.0 65.0 75.0 94.0 + + NAME PC9821Af/U9W E09? + SEE NEC WAB-A/B + + NAME PC9821An/U8W + SEE NEC WAB-A/B + + NAME PC9821Ap2/U8W/C9W + SEE NEC WAB-A/B + + NAME PC9821As2/U7W/U8W + SEE NEC WAB-A/B + + NAME NEC 864 + CHIPSET S3 864 + SERVER NECS3 + LINE Chipset "s3_generic" + LINE Option "necwab" + LINE Ramdac "s3_sdac" + LINE ClockChip "s3_sdac" + + NAME PC9821Ap3 + SEE NEC 864 + + NAME PC9821As3 + SEE NEC 864 + + NAME PC9821Xp + SEE NEC 864 + + NAME PC9821Xs + SEE NEC 864 + + # PWSKB + + NAME PowerWindow 928/801 + CHIPSET S3 928 + SERVER PWSKB + LINE Chipset "s3_generic" + LINE # Chipset "mmio_928" + LINE Ramdac "sc15025" + LINE Dacspeed 110 + LINE Option "dac_8_bit" + LINE # Option "epsonmemwin" + LINE # Option "nomemaccess" + LINE ClockChip "icd2061a" + + NAME PowerWindow 928II + CHIPSET S3 928 + SERVER PWSKB + LINE Chipset "s3_generic" + LINE # Chipset "mmio_928" + LINE Ramdac "att20c505" + LINE # Ramdac "bt485" + LINE Dacspeed 110 + LINE Option "dac_8_bit" + LINE # Option "pw_mux" + LINE Option "bt485_curs" + LINE # Option "epsonmemwin" + LINE # Option "nomemaccess" + LINE ClockChip "icd2061a" + + NAME PowerWindow 805i + CHIPSET S3 805 + SERVER PWSKB + LINE Chipset "s3_generic" + LINE Ramdac "s3gendac" + LINE Dacspeed 110 + LINE Option "dac_8_bit" + LINE # Option "pw805i" + LINE # Option "epsonmemwin" + LINE # Option "nomemaccess" + LINE ClockChip "s3_sdac" + + NAME PowerWindow 928G + CHIPSET S3 928 + SERVER PWSKB + LINE Chipset "s3_generic" + LINE # Chipset "mmio_928" + LINE Ramdac "sc15025" + LINE Dacspeed 110 + LINE Option "dac_8_bit" + LINE # Option "nomemaccess" + LINE # Option "nolinear" + LINE ClockChip "icd2061a" + + NAME PCSKB/PCSKB2 + CHIPSET S3 911/924 + SERVER PWSKB + LINE Chipset "s3_generic" + LINE Ramdac "sc15025" + LINE Dacspeed 110 + LINE Option "dac_8_bit" + LINE # Option "nomemaccess" + LINE Option "pcskb" + LINE Clocks 25.0 28.0 40.0 0.0 50.0 77.0 36.0 45.0 + LINE Clocks 130.0 120.0 80.0 31.0 110.0 65.0 75.0 94.0 + + NAME PCSKB3/PCSKB4/PCPKB4 + CHIPSET S3 928 + SERVER PWSKB + LINE Chipset "s3_generic" + LINE Ramdac "sc15025" + LINE # Ramdac "att20c498" + LINE Dacspeed 110 + LINE Option "dac_8_bit" + LINE Option "nomemaccess" + LINE Option "pcskb4" + LINE Clocks 25.0 28.0 40.0 0.0 50.0 77.0 36.0 45.0 + LINE Clocks 130.0 120.0 80.0 31.0 110.0 65.0 75.0 94.0 + + # PWLB + + NAME PowerWindow 928GLB + CHIPSET S3 928 + SERVER PWLB + LINE Chipset "s3_generic" + LINE # Chipset "mmio_928" + LINE Ramdac "sc15025" + LINE Dacspeed 110 + LINE Option "dac_8_bit" + LINE # Option "pw_localbus" + LINE # Option "nomemaccess" + LINE # Option "nolinear" + LINE ClockChip "icd2061a" + + NAME PowerWindow 928IILB + CHIPSET S3 928 + SERVER PWLB + LINE Chipset "s3_generic" + LINE # Chipset "mmio_928" + LINE Ramdac "att20c505" + LINE # Ramdac "bt485" + LINE Dacspeed 110 + LINE Option "dac_8_bit" + LINE Option "bt485_curs" + LINE Option "pw_localbus" + LINE # Option "pw_mux" + LINE # Option "nomemaccess" + LINE # Option "nolinear" + LINE ClockChip "icd2061a" + + NAME PowerWindow 964LB + CHIPSET S3 964 + SERVER PWLB + LINE Chipset "s3_generic" + LINE Option "pw_localbus" + LINE Option "number_nine" + LINE Ramdac "ti3025" + LINE ClockChip "ti3025" + LINE VideoRam 4096 + + # GA968 + + NAME GA-968V4/PCI + CHIPSET S3 968 + SERVER GA968 + LINE Chipset "s3_generic" + LINE # Chipset "mmio_928" + LINE VideoRam 4096 *** ./xfree68/doc/README.fbdev@@/PUBLIC-LATEST Sun Aug 10 12:55:43 1997 --- xc/programs/Xserver/hw/xfree68/doc/README.fbdev Fri Mar 6 13:38:17 1998 *************** *** 440,446 **** (in picoseconds, 1E-12 s), and vertical timings in number of scanlines. ! 7. Converting XFree86 timing values info frame buffer device timings An XFree86 mode line consists of the following fields: --- 440,446 ---- (in picoseconds, 1E-12 s), and vertical timings in number of scanlines. ! 7. Converting XFree86 timing values into frame buffer device timings An XFree86 mode line consists of the following fields: *************** *** 558,569 **** This readme was written by Geert Uytterhoeven, partly based on the original X- framebuffer.README by Roman Hodek and Martin Schaller. Section `Converting ! XFree86 timing values info frame buffer device timings' was provided by Frank Neumann. The frame buffer device abstraction was designed by Martin Schaller. ! Generated from XFree86: xc/programs/Xserver/hw/xfree68/doc/sgml/fbdev.sgml,v 1.1.2.4 1997/08/02 13:54:10 dawes Exp $ --- 558,569 ---- This readme was written by Geert Uytterhoeven, partly based on the original X- framebuffer.README by Roman Hodek and Martin Schaller. Section `Converting ! XFree86 timing values into frame buffer device timings' was provided by Frank Neumann. The frame buffer device abstraction was designed by Martin Schaller. ! Generated from XFree86: xc/programs/Xserver/hw/xfree68/doc/sgml/fbdev.sgml,v 1.1.2.5 1997/08/08 03:09:07 dawes Exp $ *************** *** 681,687 **** 6. Video Mode Timings ...................................................... 5 ! 7. Converting XFree86 timing values info frame buffer device timings ....... 7 8. References .............................................................. 8 --- 681,687 ---- 6. Video Mode Timings ...................................................... 5 ! 7. Converting XFree86 timing values into frame buffer device timings ....... 7 8. References .............................................................. 8 *************** *** 725,732 **** ! $XFree86: xc/programs/Xserver/hw/xfree68/doc/README.fbdev,v 1.1.2.4 1997/08/02 13:54:44 dawes Exp $ ! ! ! ! $TOG: README.fbdev /main/2 1997/08/10 12:54:19 kaleb $ --- 725,729 ---- ! $XFree86: xc/programs/Xserver/hw/xfree68/doc/README.fbdev,v 1.1.2.5 1997/08/08 03:34:18 dawes Exp $ ! $TOG: README.fbdev /main/3 1998/03/06 13:39:54 kaleb $ *** ./xfree68/doc/sgml/fbdev.sgml@@/PUBLIC-LATEST Sun Aug 10 12:55:54 1997 --- xc/programs/Xserver/hw/xfree68/doc/sgml/fbdev.sgml Fri Mar 6 13:38:21 1998 *************** *** 334,340 **** (in picoseconds, 1E-12 s), and vertical timings in number of scanlines. ! <sect>Converting XFree86 timing values info frame buffer device timings <p> An XFree86 mode line consists of the following fields: --- 334,340 ---- (in picoseconds, 1E-12 s), and vertical timings in number of scanlines. ! <sect>Converting XFree86 timing values into frame buffer device timings <p> An XFree86 mode line consists of the following fields: *************** *** 416,422 **** <p> This readme was written by Geert Uytterhoeven, partly based on the original <tt>X-framebuffer.README</tt> by Roman Hodek and Martin Schaller. Section ! `Converting XFree86 timing values info frame buffer device timings' was provided by Frank Neumann. The frame buffer device abstraction was designed by Martin Schaller. --- 416,422 ---- <p> This readme was written by Geert Uytterhoeven, partly based on the original <tt>X-framebuffer.README</tt> by Roman Hodek and Martin Schaller. Section ! `Converting XFree86 timing values into frame buffer device timings' was provided by Frank Neumann. The frame buffer device abstraction was designed by Martin Schaller. *************** *** 423,433 **** <verb> ! $XFree86: xc/programs/Xserver/hw/xfree68/doc/sgml/fbdev.sgml,v 1.1.2.4 1997/08/02 13:54:10 dawes Exp $ ! $TOG: fbdev.sgml /main/2 1997/08/10 12:54:29 kaleb $ </verb> </article> --- 423,433 ---- <verb> ! $XFree86: xc/programs/Xserver/hw/xfree68/doc/sgml/fbdev.sgml,v 1.1.2.5 1997/08/08 03:09:07 dawes Exp $ ! $TOG: fbdev.sgml /main/3 1998/03/06 13:39:59 kaleb $ </verb> </article> *** ./xfree86/accel/i128/i128accel.c@@/PUBLIC-LATEST Sun Aug 10 12:58:08 1997 --- xc/programs/Xserver/hw/xfree86/accel/i128/i128accel.c Fri Mar 6 16:31:11 1998 *************** *** 1,8 **** ! /* $TOG: i128accel.c /main/2 1997/08/10 12:56:43 kaleb $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/accel/i128/i128accel.c,v 3.4.2.4 1997/07/31 06:05:46 dawes Exp $ */ /* * Copyright 1997 by Robin Cutshaw <robin@XFree86.Org> --- 1,8 ---- ! /* $TOG: i128accel.c /main/3 1998/03/06 16:32:49 kaleb $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/accel/i128/i128accel.c,v 3.4.2.8 1998/02/20 14:27:55 robin Exp $ */ /* * Copyright 1997 by Robin Cutshaw <robin@XFree86.Org> *************** *** 33,69 **** #include "xf86.h" #include "xf86xaa.h" #include "i128.h" #include "i128reg.h" extern struct i128io i128io; extern struct i128mem i128mem; extern int i128DisplayWidth; extern int i128DisplayOffset; extern int i128DeviceType; static volatile CARD32 *eng_a; static volatile CARD32 *eng_b; ! static int i128blitdir, i128rop; ! short i128alu[16] = { ! CR_CLEAR, ! CR_NOR, ! CR_AND_INV, ! CR_COPY_INV, ! CR_AND_REV, ! CR_INVERT, ! CR_XOR, ! CR_NAND, ! CR_AND, ! CR_EQUIV, ! CR_NOOP, ! CR_OR_INV, ! CR_COPY, ! CR_OR_REV, ! CR_OR, ! CR_SET }; /* 8bpp 16bpp 32bpp unused */ static int min_size[] = { 0x62, 0x32, 0x1A, 0x00 }; --- 33,80 ---- #include "xf86.h" #include "xf86xaa.h" + #include "xf86local.h" #include "i128.h" #include "i128reg.h" + #define ENG_PIPELINE_READY() { while (eng_cur[BUSY] & BUSY_BUSY) ; } + #define ENG_DONE() { while (eng_cur[FLOW] & (FLOW_DEB | FLOW_MCB | FLOW_PRV)) ;} + extern struct i128io i128io; extern struct i128mem i128mem; extern int i128DisplayWidth; extern int i128DisplayOffset; extern int i128DeviceType; + extern int i128MemoryType; static volatile CARD32 *eng_a; static volatile CARD32 *eng_b; ! static volatile CARD32 *eng_cur; ! static volatile i128dlpu *i128dl1p, *i128dl2p; ! static CARD32 i128dl1o, i128dl2o; ! static CARD32 i128blitdir, i128cmd, i128rop, i128clptl, i128clpbr; ! static i128dlpu dlpb[256]; ! /* pre-shift rops and just or in as needed */ ! ! CARD32 i128alu[16] = { ! CR_CLEAR<<8, ! CR_AND<<8, ! CR_AND_REV<<8, ! CR_COPY<<8, ! CR_AND_INV<<8, ! CR_NOOP<<8, ! CR_XOR<<8, ! CR_OR<<8, ! CR_NOR<<8, ! CR_EQUIV<<8, ! CR_INVERT<<8, ! CR_OR_REV<<8, ! CR_COPY_INV<<8, ! CR_OR_INV<<8, ! CR_NAND<<8, ! CR_SET<<8 }; /* 8bpp 16bpp 32bpp unused */ static int min_size[] = { 0x62, 0x32, 0x1A, 0x00 }; *************** *** 110,206 **** void i128EngineDone() { ! int flow; ! ! do { ! flow = eng_a[FLOW]; ! } while (flow & (FLOW_DEB | FLOW_MCB | FLOW_PRV)); } - void - i128EngineReady() - { - int busy; - do { - busy = eng_a[BUSY]; - } while (busy & BUSY_BUSY) ; - } - void ! i128SetupForScreenToScreenCopy(int xdir, int ydir, int rop, unsigned planemask, ! int transparency_color) { ! i128EngineReady(); ! switch (xf86bpp) { ! case 8: ! eng_a[BUF_CTRL] = BC_PSIZ_8B; ! break; ! case 16: ! eng_a[BUF_CTRL] = BC_PSIZ_16B; ! break; ! case 24: ! case 32: ! eng_a[BUF_CTRL] = BC_PSIZ_32B; ! break; ! default: ! /* programming error */ ! return; ! } - eng_a[DE_PGE] = 0x00; - eng_a[DE_SORG] = i128DisplayOffset; - eng_a[DE_DORG] = i128DisplayOffset; - eng_a[DE_MSRC] = 0x00; - eng_a[DE_WKEY] = 0x00; - eng_a[DE_SPTCH] = i128mem.rbase_g[DB_PTCH]; - eng_a[DE_DPTCH] = i128mem.rbase_g[DB_PTCH]; - eng_a[MASK] = planemask; - eng_a[RMSK] = planemask; - eng_a[CLPTL] = 0x00000000; - eng_a[CLPBR] = 0xffffffff; - - - if (xdir == -1) { - if (ydir == -1) - i128blitdir = DIR_RL_BT; - else - i128blitdir = DIR_RL_TB; - } else { - if (ydir == -1) - i128blitdir = DIR_LR_BT; - else - i128blitdir = DIR_LR_TB; - } - - i128rop = i128alu[rop]; - } - - void - i128SubsequentScreenToScreenCopy(int x1, int y1, int x2, int y2, int w,int h) - { - int origx2 = x2; - int origy2 = y2; - - i128EngineReady(); - - eng_a[CMD] = CMD_BLIT; - eng_a[XY3_DIR] = i128blitdir; - eng_a[XY4_ZM] = ZOOM_NONE; - if (i128blitdir & DIR_RL_TB) { ! x1 += w - 1; ! x2 += w - 1; } if (i128blitdir & DIR_LR_BT) { ! y1 += h - 1; ! y2 += h - 1; } if (i128DeviceType == I128_DEVICE_ID1) { int bppi; static int first_time_through = 1; /* The I128-1 has a nasty bitblit bug --- 121,154 ---- void i128EngineDone() { ! ENG_DONE(); } void ! i128BitBlit(int x1, int y1, int x2, int y2, int w, int h) { ! ENG_PIPELINE_READY(); ! eng_cur[CMD] = i128cmd; ! /*eng_cur[XY3_DIR] = i128blitdir;*/ if (i128blitdir & DIR_RL_TB) { ! x1 += w; x1--; ! x2 += w; x2--; } if (i128blitdir & DIR_LR_BT) { ! y1 += h; y1--; ! y2 += h; y2--; } + if (i128DeviceType == I128_DEVICE_ID1) { int bppi; + int origx2 = x2; + int origy2 = y2; + static int first_time_through = 1; /* The I128-1 has a nasty bitblit bug *************** *** 207,213 **** * that occurs when dest is exactly 8 pages wide */ ! bppi = (eng_a[BUF_CTRL] & BC_PSIZ_MSK) >> 24; if ((w >= min_size[bppi]) && (w <= max_size[bppi])) { if (first_time_through) { --- 155,161 ---- * that occurs when dest is exactly 8 pages wide */ ! bppi = (eng_cur[BUF_CTRL] & BC_PSIZ_MSK) >> 24; if ((w >= min_size[bppi]) && (w <= max_size[bppi])) { if (first_time_through) { *************** *** 220,230 **** #if 1 /* split method */ ! eng_a[XY2_WH] = (bppi<<16) | h; ! eng_a[XY0_SRC] = (x1<<16) | y1; ! eng_a[XY1_DST] = (x2<<16) | y2; ! i128EngineDone(); w -= bppi; --- 168,178 ---- #if 1 /* split method */ ! eng_cur[XY2_WH] = (bppi<<16) | h; ! eng_cur[XY0_SRC] = (x1<<16) | y1; MB; ! eng_cur[XY1_DST] = (x2<<16) | y2; MB; ! ENG_PIPELINE_READY(); w -= bppi; *************** *** 239,261 **** } #else /* clip method */ ! eng_a[CLPTL] = (origx2<<16) | origy2; ! eng_a[CLPBR] = ((origx2+w)<<16) | (origy2+h); w += bppi; #endif } } ! eng_a[XY2_WH] = (w<<16) | h; ! eng_a[XY0_SRC] = (x1<<16) | y1; ! eng_a[XY1_DST] = (x2<<16) | y2; } void i128AccelInit() { ! xf86AccelInfoRec.Flags = BACKGROUND_OPERATIONS | PIXMAP_CACHE; xf86AccelInfoRec.ServerInfoRec = &i128InfoRec; xf86AccelInfoRec.Sync = i128EngineDone; --- 187,590 ---- } #else /* clip method */ ! eng_cur[CLPTL] = (origx2<<16) | origy2; ! eng_cur[CLPBR] = ((origx2+w)<<16) | (origy2+h); w += bppi; #endif } } ! eng_cur[XY2_WH] = (w<<16) | h; ! eng_cur[XY0_SRC] = (x1<<16) | y1; MB; ! eng_cur[XY1_DST] = (x2<<16) | y2; MB; } void + i128SetupForScreenToScreenCopy(int xdir, int ydir, int rop, unsigned planemask, + int transparency_color) + { + + ENG_PIPELINE_READY(); + + eng_cur[MASK] = planemask; + + eng_cur[CLPTL] = 0x00000000; + eng_cur[CLPBR] = (4095<<16) | 2047; + + if (transparency_color != -1) + eng_cur[BACK] = transparency_color; + + + if (xdir == -1) { + if (ydir == -1) i128blitdir = DIR_RL_BT; + else i128blitdir = DIR_RL_TB; + } else { + if (ydir == -1) i128blitdir = DIR_LR_BT; + else i128blitdir = DIR_LR_TB; + } + eng_cur[XY3_DIR] = i128blitdir; + + i128rop = i128alu[rop]; + i128cmd = (transparency_color != -1 ? (CS_TRNSP<<16) : 0) | + i128rop | CO_BITBLT; + eng_cur[CMD] = i128cmd; + } + + void + i128SubsequentScreenToScreenCopy(int x1, int y1, int x2, int y2, int w, int h) + { + i128BitBlit(x1, y1, x2, y2, w, h); + } + + void + i128SetupForFillRectSolid(int color, int rop, unsigned planemask) + { + + ENG_PIPELINE_READY(); + #if 0 + ErrorF("SFFRS color 0x%x rop 0x%x (i128rop 0x%x) pmask 0x%x\n", color, rop, i128alu[rop]>>8, planemask); + #endif + + if (planemask == -1) + eng_cur[MASK] = -1; + else switch (xf86bpp) { + case 8: + eng_cur[MASK] = planemask | + (planemask<<8) | + (planemask<<16) | + (planemask<<24); + break; + case 16: + eng_cur[MASK] = planemask | (planemask<<16); + break; + case 24: + case 32: + default: + eng_cur[MASK] = planemask; + break; + } + + eng_cur[FORE] = color; + + i128clptl = eng_cur[CLPTL] = 0x00000000; + i128clpbr = eng_cur[CLPBR] = (4095<<16) | 2047 ; + + eng_cur[XY3_DIR] = i128blitdir = DIR_LR_TB; + + i128rop = i128alu[rop]; + i128cmd = (CS_SOLID<<16) | i128rop | CO_BITBLT; + eng_cur[CMD] = i128cmd; + } + + void + i128SubsequentFillRectSolid(int x, int y, int w, int h) + { + #if 0 + ErrorF("SFRS %d,%d %d,%d\n", x, y, w, h); + #endif + i128BitBlit(0, 0, x, y, w, h); + } + + void + i128SubsequentTwoPointLine(int x1, int y1, int x2, int y2, int bias) + { + ENG_PIPELINE_READY(); + #if 0 + ErrorF("STPL i128rop 0x%x %d,%d %d,%d clip %d,%d %d,%d\n", i128rop, x1, y1, x2, y2, i128clptl>>16, i128clptl&0xffff, (i128clpbr>>16)&0xffff, i128clpbr&0xffff); + #endif + + eng_cur[CMD] = + ((bias&0x0100) ? (CP_NLST<<24) : 0) | + (CC_CLPRECI<<21) | + (CS_SOLID<<16) | + i128rop | + CO_LINE; + + eng_cur[CLPTL] = i128clptl; + eng_cur[CLPBR] = i128clpbr; + + eng_cur[XY0_SRC] = (x1<<16) | y1; MB; + eng_cur[XY1_DST] = (x2<<16) | y2; MB; + + } + + void + i128SetClippingRectangle(int x1, int y1, int x2, int y2) + { + int tmp; + #if 0 + ErrorF("SCR %d,%d %d,%d\n", x1, y1, x2, y2); + #endif + + if (x1 > x2) { tmp = x2; x2 = x1; x1 = tmp; } + if (y1 > y2) { tmp = y2; y2 = y1; y1 = tmp; } + + i128clptl = (x1<<16) | y1; + i128clpbr = (x2<<16) | y2; + } + + + void + i128FillRectSolid(DrawablePtr pDraw, GCPtr pGC, int nBox, register BoxPtr pBoxI) + { + register int w, h, planemask; + + ENG_PIPELINE_READY(); + #if 0 + ErrorF("FRS color 0x%x rop 0x%x (i128rop 0x%x) pmask 0x%x\n", pGC->fgPixel, pGC->alu, i128alu[pGC->alu]>>8, pGC->planemask); + #endif + + planemask = pGC->planemask; + + if (planemask != -1) { + if (xf86bpp == 8) { + planemask |= (planemask<<8) | + (planemask<<16) | + (planemask<<24); + } else if (xf86bpp == 16) + planemask |= planemask<<16; + } + + eng_cur[MASK] = planemask; + eng_cur[FORE] = pGC->fgPixel; + eng_cur[CMD] = (CS_SOLID<<16) | i128alu[pGC->alu] | CO_BITBLT; + eng_cur[CLPTL] = 0x00000000; + eng_cur[CLPBR] = (4095<<16) | 2047; + + eng_cur[XY3_DIR] = DIR_LR_TB; + eng_cur[XY0_SRC] = 0x00000000; + + while (nBox > 0) { + w = pBoxI->x2 - pBoxI->x1; + h = pBoxI->y2 - pBoxI->y1; + if (w > 0 && h > 0) { + eng_cur[XY2_WH] = (w<<16) | h; MB; + eng_cur[XY1_DST] = (pBoxI->x1<<16) | pBoxI->y1; MB; + ENG_PIPELINE_READY(); + } + pBoxI++; + nBox--; + } + + ENG_DONE(); + } + + + void + i128T2RFillRectSolid(DrawablePtr pDraw, GCPtr pGC, int nBox, BoxPtr pBoxI) + { + register int planemask; + register CARD32 *idp, *sdp; + register i128dlpu *dp; + static i128dlpu staticdp[2] = { + { + (MASK*4)&0xff, /* aad */ + (FORE*4)&0xff, /* bad */ + (CMD*4)&0xff, /* cad */ + 0x0c | + (((MASK*4)&0x100)>>4) | + (((FORE*4)&0x100)>>3) | + (((CMD*4)&0x100)>>2), /* control */ + 0x00000000, /* rad */ + 0x00000000, /* rbd */ + 0x00000000, /* rcd */ + }, + { + (CLPTL*4)&0xff, /* aad */ + (CLPBR*4)&0xff, /* bad */ + 0x00, /* cad */ + 0x08 | + (((CLPTL*4)&0x100)>>4) | + (((CLPBR*4)&0x100)>>3), /* control */ + 0x00000000, /* rad */ + (4095<<16) | 2047, /* rbd */ + 0x00000000, /* rcd */ + } + }; + + ENG_PIPELINE_READY(); + + planemask = pGC->planemask; + + if (planemask != -1) { + if (xf86bpp == 8) { + planemask |= (planemask<<8) | + (planemask<<16) | + (planemask<<24); + } else if (xf86bpp == 16) + planemask |= planemask<<16; + } + + if (nBox == 1) { + register int w, h; + + eng_cur[MASK] = planemask; + eng_cur[FORE] = pGC->fgPixel; + eng_cur[CMD] = (CS_SOLID<<16) | i128alu[pGC->alu] | CO_BITBLT; + eng_cur[CLPTL] = 0x00000000; + eng_cur[CLPBR] = (4095<<16) | 2047; + + eng_cur[XY3_DIR] = DIR_LR_TB; + eng_cur[XY0_SRC] = 0x00000000; + + w = pBoxI->x2 - pBoxI->x1; + h = pBoxI->y2 - pBoxI->y1; + if (w > 0 && h > 0) { + eng_cur[XY2_WH] = (w<<16) | h; MB; + eng_cur[XY1_DST] = (pBoxI->x1<<16) | pBoxI->y1; MB; + } + ENG_DONE(); + return; + } + + staticdp[0].f0.rad = planemask; + staticdp[0].f0.rbd = pGC->fgPixel; + staticdp[0].f0.rcd = (CS_SOLID<<16) | i128alu[pGC->alu] | CO_BITBLT; + + /* copy and trigger the transfer */ + + idp = (CARD32 *)i128dl2p; + sdp = (CARD32 *)staticdp; + *idp++ = *sdp++; + *idp++ = *sdp++; + *idp++ = *sdp++; + *idp++ = *sdp++; + *idp++ = *sdp++; + *idp++ = *sdp++; + *idp++ = *sdp++; + *idp++ = *sdp++; + + while (eng_cur[DL_ADR] & 0x40000000) ; + + eng_cur[DL_ADR] = i128dl2o; MB; + eng_cur[DL_CNTRL] = i128dl2o + 32; MB; + + while (nBox > 0) { + register int w, h, n, ndp, dlpslotsleft; + + dp = dlpb; + ndp = 0; + + /* fill in up to 16 slots in the dlp1 buffer */ + + dlpslotsleft = 16; + while ((nBox > 0) && (dlpslotsleft > 0)) { + w = pBoxI->x2 - pBoxI->x1; + h = pBoxI->y2 - pBoxI->y1; + if (w > 0 && h > 0) { + dp->f1.xy0 = 0x0000000; + dp->f1.xy2 = (w<<16) | h; + dp->f1.xy3 = DIR_LR_TB; /* == 0 */ + dp->f1.xy1 = (pBoxI->x1<<16) | pBoxI->y1; + dp++; ndp++; dlpslotsleft--; + } + pBoxI++; + nBox--; + } + if (ndp == 0) /* no valid rects, we're done */ + break; + + /* copy the words into the frame buffer dlp1 cache */ + + idp = (CARD32 *)i128dl1p; + sdp = (CARD32 *)dlpb; + n = ndp; + + while (n-- > 0) { + *idp++ = *sdp++; + *idp++ = *sdp++; + *idp++ = *sdp++; + *idp++ = *sdp++; + } + + /* trigger the dlp op */ + + while (eng_cur[DL_ADR] & 0x40000000) ; + + eng_cur[DL_ADR] = i128dl1o; MB; + eng_cur[DL_CNTRL] = (i128dl1o + 16*ndp) | 0x20000000; MB; + + /* we do our own multi-threading here */ + + dp = dlpb; + ndp = 0; + + /* fill in up to 128 slots in the dlp2 buffer */ + + dlpslotsleft = 128; + while ((nBox > 0) && (dlpslotsleft > 0)) { + w = pBoxI->x2 - pBoxI->x1; + h = pBoxI->y2 - pBoxI->y1; + if (w > 0 && h > 0) { + dp->f1.xy0 = 0x0000000; + dp->f1.xy2 = (w<<16) | h; + dp->f1.xy3 = DIR_LR_TB; /* == 0 */ + dp->f1.xy1 = (pBoxI->x1<<16) | pBoxI->y1; + dp++; ndp++; dlpslotsleft--; + } + pBoxI++; + nBox--; + } + if (ndp == 0) /* no valid rects, we're done */ + break; + + /* copy the words into the frame buffer dlp2 cache */ + + idp = (CARD32 *)i128dl2p; + sdp = (CARD32 *)dlpb; + n = ndp; + + while (n-- > 0) { + *idp++ = *sdp++; + *idp++ = *sdp++; + *idp++ = *sdp++; + *idp++ = *sdp++; + } + + /* trigger the dlp op */ + + while (eng_cur[DL_ADR] & 0x40000000) ; + + eng_cur[DL_ADR] = i128dl2o; MB; + eng_cur[DL_CNTRL] = (i128dl2o + 16*ndp) | 0x20000000; MB; + } + + while (!(eng_cur[DL_CNTRL] & 0x00000400)) ; + + ENG_DONE(); + } + + + void + i128ScreenToScreenBitBlt(int nbox, DDXPointPtr pptSrc, BoxPtr pbox, + int xdir, int ydir, int alu, unsigned planemask) + { + i128SetupForScreenToScreenCopy(xdir, ydir, alu, planemask, -1); + for (; nbox; pbox++, pptSrc++, nbox--) + i128SubsequentScreenToScreenCopy(pptSrc->x, pptSrc->y, + pbox->x1, pbox->y1, pbox->x2 - pbox->x1, pbox->y2 - pbox->y1); + ENG_DONE(); + } + + + void i128AccelInit() { ! CARD32 buf_ctrl; + xf86AccelInfoRec.Flags = BACKGROUND_OPERATIONS | + HARDWARE_CLIP_LINE | + USE_TWO_POINT_LINE | + TWO_POINT_LINE_NOT_LAST | + PIXMAP_CACHE + #ifdef DELAYED_SYNC + | DELAYED_SYNC + #endif + ; + + if (i128DeviceType == I128_DEVICE_ID3) + xf86AccelInfoRec.Flags |= ONLY_LEFT_TO_RIGHT_BITBLT; + xf86AccelInfoRec.ServerInfoRec = &i128InfoRec; xf86AccelInfoRec.Sync = i128EngineDone; *************** *** 265,281 **** xf86AccelInfoRec.SubsequentScreenToScreenCopy = i128SubsequentScreenToScreenCopy; ! xf86GCInfoRec.CopyAreaFlags = ! GXCOPY_ONLY | NO_PLANEMASK | NO_TRANSPARENCY; xf86AccelInfoRec.PixmapCacheMemoryStart = i128InfoRec.virtualY * i128DisplayWidth * i128InfoRec.bitsPerPixel / 8; xf86AccelInfoRec.PixmapCacheMemoryEnd = ! i128InfoRec.videoRam * 1024-1024; i128InfoRec.displayWidth = i128DisplayWidth; ! eng_a = i128mem.rbase_a; eng_b = i128mem.rbase_b; } --- 594,676 ---- xf86AccelInfoRec.SubsequentScreenToScreenCopy = i128SubsequentScreenToScreenCopy; ! xf86GCInfoRec.CopyAreaFlags = 0; + xf86AccelInfoRec.SetupForFillRectSolid = + i128SetupForFillRectSolid; + xf86AccelInfoRec.SubsequentFillRectSolid = + i128SubsequentFillRectSolid; + + xf86AccelInfoRec.SubsequentTwoPointLine = + i128SubsequentTwoPointLine; + + xf86AccelInfoRec.SetClippingRectangle = + i128SetClippingRectangle; + + xf86GCInfoRec.PolyFillRectSolidFlags = 0; + xf86AccelInfoRec.PixmapCacheMemoryStart = i128InfoRec.virtualY * i128DisplayWidth * i128InfoRec.bitsPerPixel / 8; xf86AccelInfoRec.PixmapCacheMemoryEnd = ! (i128InfoRec.videoRam * 1024) - 1024; + /*/ + * If there is sufficient memory, we create two blocks of + * 128 diplay list instruction words (16 bytes each). + /*/ + + if ((xf86AccelInfoRec.PixmapCacheMemoryEnd - + xf86AccelInfoRec.PixmapCacheMemoryStart) > 16*256) { + xf86AccelInfoRec.PixmapCacheMemoryEnd -= 16*256; + i128dl1o = xf86AccelInfoRec.PixmapCacheMemoryEnd; + i128dl1p = (i128dlpu *)&i128mem.mw0_ad[i128dl1o]; + i128dl2o = i128dl1o + 16*128; + i128dl2p = (i128dlpu *)&i128mem.mw0_ad[i128dl2o]; + } else { + i128dl1o = i128dl2o = 0; + i128dl1p = i128dl2p = (i128dlpu *)0; + } + + xf86GCInfoRec.PolyFillRectSolid = xf86PolyFillRect; + if ((i128DeviceType == I128_DEVICE_ID3) && (i128dl1o != 0)) + xf86AccelInfoRec.FillRectSolid = i128T2RFillRectSolid; + else + xf86AccelInfoRec.FillRectSolid = i128FillRectSolid; + + i128InfoRec.displayWidth = i128DisplayWidth; ! eng_a = i128mem.rbase_a; eng_b = i128mem.rbase_b; + eng_cur = eng_a; + + switch (xf86bpp) { + case 8: buf_ctrl = BC_PSIZ_8B; break; + case 16: buf_ctrl = BC_PSIZ_16B; break; + case 24: + case 32: buf_ctrl = BC_PSIZ_32B; break; + default: buf_ctrl = 0; break; /* error */ + } + if (i128DeviceType == I128_DEVICE_ID3) { + if (i128MemoryType == I128_MEMORY_SGRAM) + buf_ctrl |= BC_MDM_PLN; + else + buf_ctrl |= BC_BLK_ENA; + } + eng_cur[BUF_CTRL] = buf_ctrl; + + eng_cur[DE_PGE] = 0x00; + eng_cur[DE_SORG] = i128DisplayOffset; + eng_cur[DE_DORG] = i128DisplayOffset; + eng_cur[DE_MSRC] = 0x00; + eng_cur[DE_WKEY] = 0x00; + eng_cur[DE_SPTCH] = i128mem.rbase_g[DB_PTCH]; + eng_cur[DE_DPTCH] = i128mem.rbase_g[DB_PTCH]; + eng_cur[RMSK] = 0x00000000; + eng_cur[XY4_ZM] = ZOOM_NONE; + eng_cur[LPAT] = 0xffffffff; /* for lines */ + eng_cur[PCTRL] = 0x00000000; /* for lines */ + eng_cur[CLPTL] = 0x00000000; + eng_cur[CLPBR] = (4095<<16) | 2047 ; } *** ./xfree86/accel/s3/s3ramdacs.c@@/PUBLIC-LATEST Sun Aug 10 12:59:21 1997 --- xc/programs/Xserver/hw/xfree86/accel/s3/s3ramdacs.c Fri Mar 6 16:33:26 1998 *************** *** 1,8 **** ! /* $TOG: s3ramdacs.c /main/2 1997/08/10 12:57:57 kaleb $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/accel/s3/s3ramdacs.c,v 3.10.2.5 1997/07/19 04:59:26 dawes Exp $ */ /* * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany. * --- 1,8 ---- ! /* $TOG: s3ramdacs.c /main/3 1998/03/06 16:35:04 kaleb $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/accel/s3/s3ramdacs.c,v 3.10.2.8 1998/02/15 16:09:01 hohndel Exp $ */ /* * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany. * *************** *** 1099,1105 **** } else { /* set s3 reg65 for some unknown reason */ if (s3InfoRec.bitsPerPixel == 32) ! outb(vgaCRReg, 0x80); else if (s3InfoRec.bitsPerPixel == 16) outb(vgaCRReg, 0x40); else --- 1099,1109 ---- } else { /* set s3 reg65 for some unknown reason */ if (s3InfoRec.bitsPerPixel == 32) ! if (OFLG_ISSET(OPTION_ELSA_W2000PRO,&s3InfoRec.options)) { ! outb(vgaCRReg, 0x40); ! } else { ! outb(vgaCRReg, 0x80); ! } else if (s3InfoRec.bitsPerPixel == 16) outb(vgaCRReg, 0x40); else *************** *** 1870,1875 **** --- 1874,1880 ---- if((xf86bpp <= 8) && (S3_x64_SERIES(s3ChipId) || S3_805_I_SERIES(s3ChipId))) { s3ATT498PixMux = TRUE; + pixMuxPossible = TRUE; nonMuxMaxClock = 67500; pixMuxMinClock = 67500; allowPixMuxInterlace = TRUE; *************** *** 2532,2537 **** --- 2537,2543 ---- { unsigned char sr8, sr27, sr28; int m,n,n1,n2, mclk; + int h_lcd, v_lcd, lcdclk; /* Verify that depth is supported by ramdac */ /* all are supported */ *************** *** 2602,2607 **** --- 2608,2635 ---- outb(0x3c4, 0x28); sr28 = inb(0x3c5); mclk /= ((sr27 >> 2) & 0x03) + 1; + if (OFLG_ISSET(XCONFIG_LCDCLOCK, &s3InfoRec.xconfigFlag)) { + lcdclk = s3InfoRec.LCDClk; + } else { + int sr12, sr13; + outb(0x3c4, 0x12); + sr12 = inb(0x3c5); + outb(0x3c4, 0x13); + sr13 = inb(0x3c5); + n1 = sr12 & 0x3f; + n2 = (sr12>>6) & 0x03; + lcdclk = ((1431818 * (sr13+2)) / (n1+2) / (1 << n2) + 50) / 100; + } + outb(0x3c4, 0x61); + h_lcd = inb(0x3c5); + outb(0x3c4, 0x66); + h_lcd |= ((inb(0x3c5) & 0x02) << 7); + h_lcd = (h_lcd+1) * 8; + outb(0x3c4, 0x69); + v_lcd = inb(0x3c5); + outb(0x3c4, 0x6e); + v_lcd |= ((inb(0x3c5) & 0x70) << 4); + v_lcd++; } outb(0x3c4, 0x08); *************** *** 2608,2617 **** outb(0x3c5, sr8); if (xf86Verbose) ! if (OFLG_ISSET(CLOCK_OPTION_S3AURORA, &s3InfoRec.clockOptions)) ErrorF("%s %s: Using Aurora64 programmable clock (MCLK %1.3f MHz, SR27=%02x, SR28=%02x)\n" ,clockchip_probed, s3InfoRec.name ,mclk / 1000.0, sr27, sr28); else if (OFLG_ISSET(CLOCK_OPTION_S3TRIO64V2, &s3InfoRec.clockOptions)) ErrorF("%s %s: Using Trio64V2 programmable clock (MCLK %1.3f MHz)\n" ,clockchip_probed, s3InfoRec.name --- 2636,2651 ---- outb(0x3c5, sr8); if (xf86Verbose) ! if (OFLG_ISSET(CLOCK_OPTION_S3AURORA, &s3InfoRec.clockOptions)) { ErrorF("%s %s: Using Aurora64 programmable clock (MCLK %1.3f MHz, SR27=%02x, SR28=%02x)\n" ,clockchip_probed, s3InfoRec.name ,mclk / 1000.0, sr27, sr28); + ErrorF("%s %s: LCD size %dx%d, clock %1.3f MHz\n" + , OFLG_ISSET(XCONFIG_LCDCLOCK, &s3InfoRec.xconfigFlag) ? XCONFIG_GIVEN : XCONFIG_PROBED + , s3InfoRec.name + , h_lcd, v_lcd + , lcdclk / 1000.0); + } else if (OFLG_ISSET(CLOCK_OPTION_S3TRIO64V2, &s3InfoRec.clockOptions)) ErrorF("%s %s: Using Trio64V2 programmable clock (MCLK %1.3f MHz)\n" ,clockchip_probed, s3InfoRec.name *************** *** 4446,4453 **** #else if (S3_TRIOxx_SERIES(s3ChipId)) { ! if (OFLG_ISSET(CLOCK_OPTION_S3AURORA, &s3InfoRec.clockOptions)) ! (void) S3AuroraSetClock(freq, 2); /* can't fail */ else if (OFLG_ISSET(CLOCK_OPTION_S3TRIO64V2, &s3InfoRec.clockOptions)) (void) S3Trio64V2SetClock(freq, 2); /* can't fail */ else --- 4480,4522 ---- #else if (S3_TRIOxx_SERIES(s3ChipId)) { ! if (OFLG_ISSET(CLOCK_OPTION_S3AURORA, &s3InfoRec.clockOptions)) { ! outb(0x3c4, 0x08); /* unlock extended SEQ regs */ ! outb(0x3c5, 0x06); ! outb(0x3c4, 0x31); ! if (inb(0x3c5) & 0x10) { /* LCD on */ ! if (!s3InfoRec.LCDClk) { /* entered only once for first mode */ ! int h_lcd, v_lcd; ! outb(0x3c4, 0x61); ! h_lcd = inb(0x3c5); ! outb(0x3c4, 0x66); ! h_lcd |= ((inb(0x3c5) & 0x02) << 7); ! h_lcd = (h_lcd+1) * 8; ! outb(0x3c4, 0x69); ! v_lcd = inb(0x3c5); ! outb(0x3c4, 0x6e); ! v_lcd |= ((inb(0x3c5) & 0x70) << 4); ! v_lcd++; ! ! /* check if first mode has physical LCD resolution */ ! if (s3InfoRec.modes->HDisplay == h_lcd && s3InfoRec.modes->VDisplay == v_lcd) ! s3InfoRec.LCDClk = s3InfoRec.clock[s3InfoRec.modes->Clock]; ! else { ! int n1, n2, sr12, sr13; ! outb(0x3c4, 0x12); ! sr12 = inb(0x3c5); ! outb(0x3c4, 0x13); ! sr13 = inb(0x3c5); ! n1 = sr12 & 0x3f; ! n2 = (sr12>>6) & 0x03; ! s3InfoRec.LCDClk = ((1431818 * (sr13+2)) / (n1+2) / (1 << n2) + 50) / 100; ! } ! } ! (void) S3AuroraSetClock(s3InfoRec.LCDClk, 2); /* can't fail */ ! } ! else ! (void) S3AuroraSetClock(freq, 2); /* can't fail */ ! } else if (OFLG_ISSET(CLOCK_OPTION_S3TRIO64V2, &s3InfoRec.clockOptions)) (void) S3Trio64V2SetClock(freq, 2); /* can't fail */ else *** ./xfree86/common/xf86DCConf.c@@/PUBLIC-LATEST Sat Jul 19 16:04:28 1997 --- xc/programs/Xserver/hw/xfree86/common/xf86DCConf.c Fri Mar 6 16:34:41 1998 *************** *** 1,9 **** ! /* $TOG: xf86DCConf.c /main/1 1997/07/19 16:04:29 kaleb $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86DCConf.c,v 3.2 1997/01/05 11:58:05 dawes Exp $ */ ! #ifndef X_NOT_STDC_ENV #include <stdlib.h> #else --- 1,8 ---- ! /* $TOG: xf86DCConf.c /main/2 1998/03/06 16:36:19 kaleb $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86DCConf.c,v 3.2.2.1 1998/02/26 13:59:03 dawes Exp $ */ #ifndef X_NOT_STDC_ENV #include <stdlib.h> #else *************** *** 89,95 **** if (!c) { currpointer = Pointer + pos; /* locate current position */ if(* currpointer == EOF){ /* handle EOF */ - xfree(Pointer); xfree(configRBuf); pos = 0; return( DCpushToken = EOF ); --- 88,93 ---- *************** *** 287,293 **** configPath,lineno,currpointer); pos += addlen; }; - xfree(Pointer); return(Flag); } --- 285,290 ---- *** ./xfree86/doc/BUILD@@/PUBLIC-LATEST Sat Jul 19 10:54:13 1997 --- xc/programs/Xserver/hw/xfree86/doc/BUILD Fri Mar 6 16:36:03 1998 *************** *** 11,17 **** David Dawes ! 2 June 1997 --- 11,17 ---- David Dawes ! 27 February 1997 *************** *** 36,57 **** failures. (gcc-2 is available from prep.ai.mit.edu and other sites archiving GNU source.) ! 1.1 How to get the XFree86 3.3 source There are a few starting points for getting the XFree86 source. One option is ! to start directly with the XFree86 3.3 source distribution. In this case, the ! procedure is as follows: ! o The XFree86 3.3 source is contained in files X33src-1.tgz, X33src-2.tgz ! and X33src-3.tgz. These can be found at ! ftp://ftp.xfree86.org/pub/XFree86/3.3/source/ and similar locations on ! XFree86 mirror sites. X33src-2.tgz contains the fonts and documentation ! source. X33src-3.tgz contains the hardcopy documentation. X33src-1.tgz contains everything else. If you don't need the docs or fonts you can get ! by with only X33src-1.tgz. o Extract each of these files by running the following from a directory on a ! filesystem containing enough space (the full source requires around 130MB, and a similar amount is required in addition to this for the compiled binaries): --- 36,57 ---- failures. (gcc-2 is available from prep.ai.mit.edu and other sites archiving GNU source.) ! 1.1 How to get the XFree86 3.3.2 source There are a few starting points for getting the XFree86 source. One option is ! to start directly with the XFree86 3.3.2 source distribution. In this case, ! the procedure is as follows: ! o The XFree86 3.3.2 source is contained in files X332src-1.tgz, ! X332src-2.tgz and X332src-3.tgz. These can be found at ! ftp://ftp.xfree86.org/pub/XFree86/3.3.2/source/ and similar locations on ! XFree86 mirror sites. X332src-2.tgz contains the fonts and documentation ! source. X332src-3.tgz contains the hardcopy documentation. X332src-1.tgz contains everything else. If you don't need the docs or fonts you can get ! by with only X332src-1.tgz. o Extract each of these files by running the following from a directory on a ! filesystem containing enough space (the full source requires around 140MB, and a similar amount is required in addition to this for the compiled binaries): *************** *** 71,101 **** ! gzip -d < X33src-1.tgz | tar vxf - ! gzip -d < X33src-2.tgz | tar vxf - ! gzip -d < X33src-3.tgz | tar vxf - Another option is to start with the X11R6.3 source distribution and patch it up ! to XFree86 3.3. In this case you need to do the following: ! o Start with the X Consortium's X11R6.3 distribution with public patch 1 ! applied. This can be obtained by following the links from the X home page ! <URL:http://www.x.org>. ! o Get the files R6.3pl1-3.3.diff1.gz, R6.3pl1-3.3.diff2.gz, ! R6.3pl1-3.3.diff3.gz, R6.3pl1-3.3.diff4.gz, and cfont33.tgz from ! ftp://ftp.xfree86.org/pub/XFree86/3.3/patches/ (or a similar location on ! mirror sites). To upgrade the source to XFree86 3.3, run the following ! from directory containing the xc directory of the X11R6.3 pl1 source tree: ! gzip -d < R6.3pl1-3.3.diff1.gz | patch -p0 -E ! gzip -d < R6.3pl1-3.3.diff2.gz | patch -p0 -E ! gzip -d < R6.3pl1-3.3.diff3.gz | patch -p0 -E ! gzip -d < R6.3pl1-3.3.diff4.gz | patch -p0 -E ! gzip -d < cfont33.tgz | tar vxf - --- 71,101 ---- ! gzip -d < X332src-1.tgz | tar vxf - ! gzip -d < X332src-2.tgz | tar vxf - ! gzip -d < X332src-3.tgz | tar vxf - Another option is to start with the X11R6.3 source distribution and patch it up ! to XFree86 3.3.2. In this case you need to do the following: ! o Start with the X Consortium's X11R6.3 distribution with public patches 1 ! and 2 applied. This can be obtained by following the links from the The ! Open Group's X home page <URL:http://www.opengroup.org/tech/desktop/x/>. ! o Get the files R6.3pl2-3.3.2.diff1.gz, R6.3pl2-3.3.2.diff2.gz, ! R6.3pl2-3.3.2.diff3.gz, R6.3pl2-3.3.2.diff4.gz, and cfont332.tgz from ! ftp://ftp.xfree86.org/pub/XFree86/3.3.2/patches/ (or a similar location on ! mirror sites). To upgrade the source to XFree86 3.3.2, run the following ! from directory containing the xc directory of the X11R6.3 pl2 source tree: ! gzip -d < R6.3pl2-3.3.2.diff1.gz | patch -p0 -E ! gzip -d < R6.3pl2-3.3.2.diff2.gz | patch -p0 -E ! gzip -d < R6.3pl2-3.3.2.diff3.gz | patch -p0 -E ! gzip -d < R6.3pl2-3.3.2.diff4.gz | patch -p0 -E ! gzip -d < cfont332.tgz | tar vxf - *************** *** 102,130 **** Be sure to do this with a clean unmodified source tree. If you don't some patches may fail. ! If you only want to build the XFree86 X servers, you can use a cut-down version ! of the XFree86 source tree called the ``servers only'' distribution. If you ! choose this option, do the following: ! o Get the X33servonly.tgz file from ! ftp://ftp.xfree86.org/pub/XFree86/3.3/source/ (or a similar locations on ! mirror sites. ! o Extract this by running the following: ! gzip -d < X33servonly.tgz | tar vxf - - There is no patch to upgrade from the XFree86 3.2 source to 3.3. The reason - for this is the large number of changes associated with the move from X11R6.1 - to X11R6.3. ! XFree86 supports a small subset of the X Consortium X11R6.1 contrib distribu- ! tion. If you wish to build this, you will need at least the following ! files/directories from that distribution: --- 102,130 ---- Be sure to do this with a clean unmodified source tree. If you don't some patches may fail. ! A further option is to start with the XFree86 3.3.1 source, and patch it up to ! XFree86 3.3.2. In this case you need to do the following: ! o If using this option, you would already have the XFree86 3.3.1 source. ! o Get the files 3.3.1-3.3.2.diff.gz, and cfont332.tgz from ! ftp://ftp.xfree86.org/pub/XFree86/3.3.2/patches/ (or a similar location on ! mirror sites). To upgrade the source to XFree86 3.3.2, run the following ! from directory containing the xc directory of the XFree86 3.3.1 source ! tree: ! gzip -d < 3.3.1-3.3.2.diff1.gz | patch -p0 -E ! rm -fr xc/fonts/bdf/cyrillic ! gzip -d < cfont332.tgz | tar vxf - ! Be sure to do this with a clean unmodified source tree. If you don't some ! patches may fail. + If you only want to build the XFree86 X servers, you can use a cut-down version *************** *** 137,142 **** --- 137,160 ---- + of the XFree86 source tree called the ``servers only'' distribution. If you + choose this option, do the following: + + o Get the X332servonly.tgz file from + ftp://ftp.xfree86.org/pub/XFree86/3.3.2/source/ (or a similar locations on + mirror sites. + + o Extract this by running the following: + + + gzip -d < X332servonly.tgz | tar vxf - + + + + XFree86 supports a small subset of the X Consortium X11R6.1 contrib distribu- + tion. If you wish to build this, you will need at least the following + files/directories from that distribution: + contrib/Imakefile contrib/programs/Imakefile contrib/programs/ico *************** *** 156,171 **** contrib/programs/xmessage ! You will also need the XFree86 patch contrib-3.3.diff.gz. To apply the patch, ! run the following from the directory containing the contrib directory: ! gzip -d < contrib-3.3.diff.gz | patch -p0 -E ! Alternatively, you can just get the file X33contrib.tgz from the XFree86 source ! directory, and extract it by running: ! gzip -d < X33contrib.tgz | tar vxf - If you wish to build the xtest distribution, get the source distribution X33test.tgz from the XFree86 source directory, and extract it by running: --- 174,189 ---- contrib/programs/xmessage ! You will also need the XFree86 patch contrib-3.3.2.diff.gz. To apply the ! patch, run the following from the directory containing the contrib directory: ! gzip -d < contrib-3.3.2.diff.gz | patch -p0 -E ! Alternatively, you can just get the file X332contrib.tgz from the XFree86 ! source directory, and extract it by running: ! gzip -d < X332contrib.tgz | tar vxf - If you wish to build the xtest distribution, get the source distribution X33test.tgz from the XFree86 source directory, and extract it by running: *************** *** 173,178 **** --- 191,208 ---- gzip -d < X33test.tgz | tar vxf - + + + + + + + + + Building XFree86 + + + Note, xtest is no longer part of the core X11 distribution (since X11R6.3). 1.2 Configuring the source before building *************** *** 187,208 **** ous OS*Version parameters, so you shouldn't need to enter those settings explicitly. ! If you are using just the X33src-1.tgz part of the source dist, you will need to define BuildFonts to NO. If you are using the ``servers only'' distribution, you will need to define - - - - - - - - - Building XFree86 - - - BuildServersOnly to YES. 1.3 Building and installing the distribution --- 217,226 ---- ous OS*Version parameters, so you shouldn't need to enter those settings explicitly. ! If you are using just the X332src-1.tgz part of the source dist, you will need to define BuildFonts to NO. If you are using the ``servers only'' distribution, you will need to define BuildServersOnly to YES. 1.3 Building and installing the distribution *************** *** 240,245 **** --- 258,274 ---- To build a different set of servers or servers with a different set of drivers installed: + + + + + + + + Building XFree86 + + + 1. Make sure the source for any new drivers is in the correct place (e.g., driver source for the SVGA server should be in a subdirectory of xc/pro- grams/Xserver/hw/xfree86/vga256/drivers). *************** *** 256,274 **** make - - - - - - - - - - Building XFree86 - - - 3. Reconfiguring the server (binary distribution) If you have installed the server Binary LinkKit, it is possible to reconfigure --- 285,290 ---- *************** *** 275,281 **** the drivers and some of the extensions in the servers. For details of how to do this, please refer to the README.LinkKit file. ! Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/BUILD.sgml,v 3.1.2.4 1997/06/02 03:12:42 dawes Exp $ --- 291,297 ---- the drivers and some of the extensions in the servers. For details of how to do this, please refer to the README.LinkKit file. ! Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/BUILD.sgml,v 3.1.2.7 1998/02/28 13:00:00 dawes Exp $ *************** *** 315,336 **** - - - - - - - - - - - - - - - - Building XFree86 --- 331,336 ---- *************** *** 406,413 **** 1. Building XFree86 From a Source Distribution .............................. 1 ! 1.1 How to get the XFree86 3.3 source .................................... 1 ! 1.2 Configuring the source before building ............................... 3 1.3 Building and installing the distribution ............................. 4 2. Reconfiguring the server (source distribution) ........................... 4 --- 406,413 ---- 1. Building XFree86 From a Source Distribution .............................. 1 ! 1.1 How to get the XFree86 3.3.2 source .................................. 1 ! 1.2 Configuring the source before building ............................... 4 1.3 Building and installing the distribution ............................. 4 2. Reconfiguring the server (source distribution) ........................... 4 *************** *** 461,468 **** ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/BUILD,v 3.1.2.4 1997/06/02 03:18:20 dawes Exp $ ! $TOG: BUILD /main/1 1997/07/19 10:54:14 kaleb $ --- 461,468 ---- ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/BUILD,v 3.1.2.6 1998/02/28 13:05:32 dawes Exp $ ! $TOG: BUILD /main/2 1998/03/06 16:37:41 kaleb $ *** ./xfree86/doc/Japanese/man/XF86Config.man@@/PUBLIC-LATEST Tue Nov 4 21:17:36 1997 --- xc/programs/Xserver/hw/xfree86/doc/Japanese/man/XF86Config.man Fri Mar 6 16:38:37 1998 *************** *** 5,13 **** .\" Translated Tue Dec 10 19:45:00 JST 1996 .\" by Kazuyuki Okamoto <ikko-@pacific.rim.or.jp> .\" Doc Version 3.47 - .\" $TOG: XF86Config.man /main/2 1997/11/04 21:20:30 kaleb $ .\" ! .TH XF86Config 4/5 "Release 6.4 (XFree86 3.3.1)" "X Version 11" .\" .SH NAME .\" XF86Config - Configuration File for XFree86 .SH "̾Á°" --- 5,12 ---- .\" Translated Tue Dec 10 19:45:00 JST 1996 .\" by Kazuyuki Okamoto <ikko-@pacific.rim.or.jp> .\" Doc Version 3.47 .\" ! .TH XF86Config 4/5 "Version 3.2" "XFree86" .\" .SH NAME .\" XF86Config - Configuration File for XFree86 .SH "̾Á°" *************** *** 1509,1513 **** .\" manual page. ¤Î¥ª¥ó¥é¥¤¥ó¥Þ¥Ë¥å¥¢¥ë¤ò»²¾È¤·¤Æ¤¯¤À¤µ¤¤¡£ ! .\" $TOG: XF86Config.man /main/2 1997/11/04 21:20:30 kaleb $ --- 1508,1512 ---- .\" manual page. ¤Î¥ª¥ó¥é¥¤¥ó¥Þ¥Ë¥å¥¢¥ë¤ò»²¾È¤·¤Æ¤¯¤À¤µ¤¤¡£ ! .\" $TOG: XF86Config.man /main/3 1998/03/06 16:40:15 kaleb $ *** ./xfree86/doc/Japanese/man/XFree86.man@@/PUBLIC-LATEST Sun Aug 10 13:15:00 1997 --- xc/programs/Xserver/hw/xfree86/doc/Japanese/man/XFree86.man Fri Mar 6 16:38:43 1998 *************** *** 5,11 **** .\" Translated Tue Dec 11 21:59:36 JST 1996 .\" by Kazuyuki Okamoto <ikko-@pacific.rim.or.jp> .\" Doc Version 3.47 ! .\" $TOG: XFree86.man /main/1 1997/08/10 13:13:36 kaleb $ .\" .TH XFree86 1 "Version 3.3.1" "XFree86" .\" .SH NAME --- 5,11 ---- .\" Translated Tue Dec 11 21:59:36 JST 1996 .\" by Kazuyuki Okamoto <ikko-@pacific.rim.or.jp> .\" Doc Version 3.47 ! .\" $TOG: XFree86.man /main/2 1998/03/06 16:40:21 kaleb $ .\" .TH XFree86 1 "Version 3.3.1" "XFree86" .\" .SH NAME *************** *** 563,569 **** .\" Ported to \fBMinix-386vm\fP. \fBMinix-386vm\fP ¤Ø¤Î°Ü¿¢¡£ .TP 8 ! Thomas Mueller, \fItm@systrix.de\fP .\" Ported to \fBLynxOS\fP. \fBLynxOS\fP ¤Ø¤Î°Ü¿¢¡£ .TP 8 --- 563,569 ---- .\" Ported to \fBMinix-386vm\fP. \fBMinix-386vm\fP ¤Ø¤Î°Ü¿¢¡£ .TP 8 ! Thomas Mueller, \fItmueller@sysgo.de\fP .\" Ported to \fBLynxOS\fP. \fBLynxOS\fP ¤Ø¤Î°Ü¿¢¡£ .TP 8 *************** *** 757,761 **** .\" \fIXFree86@XFree86.org\fP for details. \fIXFree86\fP ¤Î¥½¡¼¥¹¤Ï \fIftp.XFree86.org\fP ¤Î FTP ¥µ¡¼¥Ð¡¢¤½¤Î¾¤Ë ¤¢¤ê¤Þ¤¹¡£¾ÜºÙ¤Ë¤Ä¤¤¤Æ¤Ï \fIXFree86@XFree86.org\fP ¤ØÅŻҥ᡼¥ë¤ò²¼¤µ¤¤¡£ ! .\" $TOG: XFree86.man /main/1 1997/08/10 13:13:36 kaleb $ --- 757,761 ---- .\" \fIXFree86@XFree86.org\fP for details. \fIXFree86\fP ¤Î¥½¡¼¥¹¤Ï \fIftp.XFree86.org\fP ¤Î FTP ¥µ¡¼¥Ð¡¢¤½¤Î¾¤Ë ¤¢¤ê¤Þ¤¹¡£¾ÜºÙ¤Ë¤Ä¤¤¤Æ¤Ï \fIXFree86@XFree86.org\fP ¤ØÅŻҥ᡼¥ë¤ò²¼¤µ¤¤¡£ ! .\" $TOG: XFree86.man /main/2 1998/03/06 16:40:21 kaleb $ *** ./xfree86/doc/README.OpenBSD@@/PUBLIC-LATEST Sun Aug 10 13:08:21 1997 --- xc/programs/Xserver/hw/xfree86/doc/README.OpenBSD Fri Mar 6 16:37:18 1998 *************** *** 7,23 **** ! README for XFree86 3.3.1 on OpenBSD Matthieu Herrb ! Last modified on: 26 July 1997 1. What and Where is XFree86? ! XFree86 3.3.1 is a port of X11R6.3 that supports several versions of Intel- based Unix. It is derived from X386 1.2, which was the X server distributed with X11R5. This release consists of many new features and performance improvements as well as many bug fixes. The release is available as source --- 7,23 ---- ! README for XFree86 3.3.2 on OpenBSD Matthieu Herrb ! Last modified on: 20 February 1998 1. What and Where is XFree86? ! XFree86 3.3.2 is a port of X11R6.3 that supports several versions of Intel- based Unix. It is derived from X386 1.2, which was the X server distributed with X11R5. This release consists of many new features and performance improvements as well as many bug fixes. The release is available as source *************** *** 30,43 **** ftp://ftp.XFree86.org/pub/XFree86/current ! Binaries for OpenBSD 2.1 are available from: ftp://ftp.XFree86.org/pub/XFree86/current/binaries/ A list of mirror sites is provided by ftp://ftp.XFree86.org/pub/XFree86/MIRRORS ! XFree86 3.3.1 also builds on other OpenBSD architectures. See section Building ! on other architectures (section 8.3, page 7) for details. 2. Bug Reports for This Document --- 30,43 ---- ftp://ftp.XFree86.org/pub/XFree86/current ! Binaries for OpenBSD 2.2 are available from: ftp://ftp.XFree86.org/pub/XFree86/current/binaries/ A list of mirror sites is provided by ftp://ftp.XFree86.org/pub/XFree86/MIRRORS ! XFree86 3.3.2 also builds on other OpenBSD architectures. See section Building ! on other architectures (section 9.3, page 7) for details. 2. Bug Reports for This Document *************** *** 48,99 **** 3. New features in this release ! 1. See the Release Notes for non-OS dependent new features in XFree86 3.3.1. 4. Installing the Binaries ! Refer to section 4 of the Release Notes for detailed installation instruc- tions. - 4.1 Installing Xdm, the display manager - The file xc/lib/Xdmcp/WrapHelp.c is not available in France (where the binary - README for XFree86 3.3.1 on OpenBSD - README for XFree86 3.3.1 on OpenBSD - distribution is built) so support for XDM-AUTHORIZATION-1 is not included here. - You'll have to get WrapHelp.c and rebuild xdm after having set HasXdmAuth in - host.def. - The file is available within the US; for details see ftp.x.org:/pub/R6/xdm- - auth/README. - To start the display manager, log in as root on the console and type: ``xdm - -nodaemon''. - - You can start xdm automatically on bootup by disabling the console getty and - adding the following code to /etc/rc.local: - - if [ -x /usr/X11R6/bin/xdm ]; then - echo -n ' xdm'; /usr/X11R6/bin/xdm - fi - - To disable the console getty, change ``on'' to ``off'' in the console entry in - /etc/ttys: - - ttyC0 "/usr/libexec/getty Pc" pc off secure - - 5. Configuring X for Your Hardware The XF86Config file tells the X server what kind of monitor, video card and --- 48,76 ---- 3. New features in this release ! 1. See the Release Notes for non-OS dependent new features in XFree86 3.3.2. 4. Installing the Binaries ! Refer to section 5 of the Release Notes for detailed installation instruc- tions. + README for XFree86 3.3.2 on OpenBSD + README for XFree86 3.3.2 on OpenBSD 5. Configuring X for Your Hardware The XF86Config file tells the X server what kind of monitor, video card and *************** *** 125,142 **** /etc/XF86Config, /usr/X11R6/lib/X11/XF86Config.hostname or /usr/X11R6/lib/X11/XF86Config. - - - - - - - - - README for XFree86 3.3.1 on OpenBSD - - - Once you've set up a XF86Config file, you can fine tune the video modes with the xvidtune utility. --- 102,107 ---- *************** *** 151,159 **** --- 116,142 ---- Mouse translation. By default, the driver runs in "cooked" mode. It can be switched using ioctls or by opening the first minor device which is /dev/psm0. + Only standard PS/2 mice are supported by this driver. Newest PS/2 mice that + send more than three bytes at a time (especially intellimouse, or mouseman+ + with a "3D" roller) are not supported yet. + + See README.mouse for general instruction on mouse configuration in XFree86. + 5.2 Other input devices XFree86 supports the dynamic loading of drivers for external input devices + + + + + + + + + README for XFree86 3.3.2 on OpenBSD + + + using the XInput extension. Currently supported devices are: o Joystick (xf86Jstk.so) *************** *** 190,210 **** load "xie.so" - README for XFree86 3.3.1 on OpenBSD - 6. Running X 8mb of memory is a recommended minimum for running X. The server, window man- ager and an xterm take about 4 Mb of memory themselves. On a 4Mb system that would leave nothing left over for other applications like gcc that expect a few --- 173,232 ---- load "xie.so" + 6. Installing Xdm, the display manager + The file xc/lib/Xdmcp/WrapHelp.c is not available in France (where the binary + distribution is built) so support for XDM-AUTHORIZATION-1 is not included here. + You'll have to get WrapHelp.c and rebuild xdm after having set HasXdmAuth in + host.def. + The file is available within the US; for details see ftp.x.org:/pub/R6/xdm- + auth/README. + To start the display manager, log in as root on the console and type: ``xdm + -nodaemon''. + You can start xdm automatically on bootup un-commenting the following code in + /etc/rc.local: + + + README for XFree86 3.3.2 on OpenBSD + + + + if [ -x /usr/X11R6/bin/xdm ]; then + echo -n ' xdm'; /usr/X11R6/bin/xdm + fi + + On the default OpenBSD 2.2 installation, you will also need to create the vir- + tual console device for the X server: + + cd /dev + ./MAKEDEV ttyC5 + + It's also better to specify explicitly the virtual console to be used by the X + server. If you're experimenting keyboards lockup with xdm, in + /usr/X11R6/lib/X11/xdm/Xservers, replace the line: + + :0 local /usr/X11R6/bin/X + + + by: + + :0 local /usr/X11R6/bin/X vt06 + + + 7. Running X + 8mb of memory is a recommended minimum for running X. The server, window man- ager and an xterm take about 4 Mb of memory themselves. On a 4Mb system that would leave nothing left over for other applications like gcc that expect a few *************** *** 220,231 **** directory as described in the xinit and startx man pages. ! 7. Kernel Support for X To make sure X support is enabled under OpenBSD, the following line must be in your config file in /sys/arch/i386/conf: ! options XSERVER, UCONSOLE The server supports the two standard OpenBSD/i386 console drivers: pccons and pcvt. They are detected at runtime and no configuration of the server itself is --- 242,253 ---- directory as described in the xinit and startx man pages. ! 8. Kernel Support for X To make sure X support is enabled under OpenBSD, the following line must be in your config file in /sys/arch/i386/conf: ! options XSERVER The server supports the two standard OpenBSD/i386 console drivers: pccons and pcvt. They are detected at runtime and no configuration of the server itself is *************** *** 235,240 **** --- 257,274 ---- tual consoles and international keyboard support. When not using XKB, the server can read the actual keymap from the keyboard + + + + + + + + + README for XFree86 3.3.2 on OpenBSD + + + driver and use to build the X keymap. Be sure to use ``RightAlt ModeShift'' in XF86Config to have the right Alt key behave as AltGr. *************** *** 242,250 **** FTP from a number of sites. They are not supported by the XFree86 binary dis- tribution anymore. You can compile support for them by adding -DSYSCONS_SUPPORT or -DCODRV_SUPPORT to XFree86ConsoleDefines in xf86site.def. See the section ! Console drivers (section 8.1, page 6) for details. ! 7.1 Aperture Driver By default OpenBSD includes the BSD 4.4 kernel security feature that disable access to the /dev/mem device when in multi-users mode. But XFree86 servers can --- 276,284 ---- FTP from a number of sites. They are not supported by the XFree86 binary dis- tribution anymore. You can compile support for them by adding -DSYSCONS_SUPPORT or -DCODRV_SUPPORT to XFree86ConsoleDefines in xf86site.def. See the section ! Console drivers (section 9.1, page 7) for details. ! 8.1 Aperture Driver By default OpenBSD includes the BSD 4.4 kernel security feature that disable access to the /dev/mem device when in multi-users mode. But XFree86 servers can *************** *** 256,278 **** There are two ways to allow XFree86 to access linear memory: - - - - - - - - - - README for XFree86 3.3.1 on OpenBSD - - - 1. Disable the kernel security feature by adding `option INSECURE' in the kernel configuration file and build a new kernel. 2. Install the aperture driver: 1. The first step is highly dependent from your exact operating sys- --- 290,302 ---- There are two ways to allow XFree86 to access linear memory: 1. Disable the kernel security feature by adding `option INSECURE' in the kernel configuration file and build a new kernel. + In OpenBSD 2.2 and later, you will also need to comment out the line ini- + tializing securelevel to 1 in /etc/rc.securelevel. + 2. Install the aperture driver: 1. The first step is highly dependent from your exact operating sys- *************** *** 289,300 **** modload -o ${KERNDIR}/ap -e ap -p ${KERNDIR}/apinstall ${KERNDIR}/ap.o fi ! o OpenBSD 2.1 Uncomment the lines loading the aperture driver from /etc/rc.securelevel 2. Reboot your system. XFree86 will auto-detect the aperture driver if available. --- 313,345 ---- modload -o ${KERNDIR}/ap -e ap -p ${KERNDIR}/apinstall ${KERNDIR}/ap.o fi ! o OpenBSD 2.1, 2.2 Uncomment the lines loading the aperture driver from /etc/rc.securelevel + o OpenBSD-current + + In addition to the loadable kernel module, you can now use an + in-kernel aperture driver. Add 'option APERTURE' to your + + + + + + + + + README for XFree86 3.3.2 on OpenBSD + + + + kernel configuration file, build and install the new kernel + and run ./MAKEDEV std in /dev. Edit /etc/sysctl.conf to set + the variable machdep.allowaperture to 1. + + 2. Reboot your system. XFree86 will auto-detect the aperture driver if available. *************** *** 311,317 **** Use 'option INSECURE' if you need more that one X server at a time. ! 7.2 MIT-SHM OpenBSD supports System V shared memory. If XFree86 detects this support in your kernel, it will support the MIT-SHM extension. --- 356,362 ---- Use 'option INSECURE' if you need more that one X server at a time. ! 8.2 MIT-SHM OpenBSD supports System V shared memory. If XFree86 detects this support in your kernel, it will support the MIT-SHM extension. *************** *** 323,340 **** options SYSVSEM options SYSVSHM - - - - - - - - - README for XFree86 3.3.1 on OpenBSD - - - to your kernel config file. Then from /sys/arch/i386/config, type: # rm -f ../compile/<KERNEL-NAME>/* --- 368,373 ---- *************** *** 350,356 **** # reboot ! 8. Rebuilding the XFree86 Distribution The server link kit allow you to rebuild just the X server with a minimum amount of disk space. Just unpack it, make the appropriate changes to the --- 383,389 ---- # reboot ! 9. Rebuilding the XFree86 Distribution The server link kit allow you to rebuild just the X server with a minimum amount of disk space. Just unpack it, make the appropriate changes to the *************** *** 357,362 **** --- 390,406 ---- xf86site.def, type ``./mkmf'' and ``make'' to link the server. See /usr/X11R6/lib/Server/README for more info. + + + + + + + + README for XFree86 3.3.2 on OpenBSD + + + See INSTALL for instructions on unbundling and building the source distribu- tion. *************** *** 364,372 **** before compiling. To compile the sources, invoke ``make World'' in the xc directory. ! 8.1 Console drivers ! XFree86 3.3.1 has a configuration option to select the console drivers to use in xf86site.def: o if you're using pccons put: --- 408,416 ---- before compiling. To compile the sources, invoke ``make World'' in the xc directory. ! 9.1 Console drivers ! XFree86 3.3.2 has a configuration option to select the console drivers to use in xf86site.def: o if you're using pccons put: *************** *** 389,408 **** If you don't define XFree86ConsoleDefines in xf86site.def the pccons and pcvt drivers will be supported. - - - - - - - - README for XFree86 3.3.1 on OpenBSD - - - - 8.2 console.h and ioctl_pc.h files: - If you want to build a server supporting codrv and you don't already have the corresponding header file ioctl_pc.h installed in /usr/include/machine, then install the copy that is supplied in xc/programs/Xserver/hw/xfree86/etc. If --- 433,440 ---- If you don't define XFree86ConsoleDefines in xf86site.def the pccons and pcvt drivers will be supported. + 9.2 console.h and ioctl_pc.h files: If you want to build a server supporting codrv and you don't already have the corresponding header file ioctl_pc.h installed in /usr/include/machine, then install the copy that is supplied in xc/programs/Xserver/hw/xfree86/etc. If *************** *** 416,429 **** The console.h file for syscons isn't distributed with XFree86 anymore. You should get it from the syscons distribution. ! 8.3 Building on other architectures ! XFree86 3.3.1 also compiles on other OpenBSD architectures. The XFree86 servers can also been built on OpenBSD/mips. The S3 server has been tested on an Acer Mips system with a S3/928 board. Contact Per Fogelstrom (pefo@OpenBSD.org) for details. The Xsun server patches from Dennis Ferguson and Matthew Green for NetBSD have been integrated in xc/programs/Xserver/hw/sun. The Xsun server can be built on the sparc and the sun3. --- 448,472 ---- The console.h file for syscons isn't distributed with XFree86 anymore. You should get it from the syscons distribution. ! 9.3 Building on other architectures ! XFree86 3.3.2 also compiles on other OpenBSD architectures. The XFree86 servers can also been built on OpenBSD/mips. The S3 server has been tested on an Acer Mips system with a S3/928 board. Contact Per Fogelstrom (pefo@OpenBSD.org) for details. + + + + + + + + README for XFree86 3.3.2 on OpenBSD + + + The Xsun server patches from Dennis Ferguson and Matthew Green for NetBSD have been integrated in xc/programs/Xserver/hw/sun. The Xsun server can be built on the sparc and the sun3. *************** *** 435,441 **** lists rather than to the xfree86 mailing list. ! 9. Building New X Clients The easiest way to build a new client (X application) is to use xmkmf if an Imakefile is included in the sources. Type ``xmkmf -a'' to create the Make- --- 478,484 ---- lists rather than to the xfree86 mailing list. ! 10. Building New X Clients The easiest way to build a new client (X application) is to use xmkmf if an Imakefile is included in the sources. Type ``xmkmf -a'' to create the Make- *************** *** 448,472 **** ``limit stacksize 16M''). ! 10. Thanks Many thanks to: o Pace Willison for providing the initial port to 386BSD. - - - - - - - - - - README for XFree86 3.3.1 on OpenBSD - - - o Amancio Hasty for fixing cursor restoration, mouse bugs and many others. o Christoph Robitschko for fixing com.c and thus select(). --- 491,502 ---- ``limit stacksize 16M''). ! 11. Thanks Many thanks to: o Pace Willison for providing the initial port to 386BSD. o Amancio Hasty for fixing cursor restoration, mouse bugs and many others. o Christoph Robitschko for fixing com.c and thus select(). *************** *** 476,488 **** o Rod Grimes and Jack Velte of Walnut Creek Cdrom for use of their machines in preparing the FreeBSD binary release. ! Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/OpenBSD.sgml,v 1.1.2.2 1997/08/02 13:48:14 dawes Exp $ ! $TOG: README.OpenBSD /main/1 1997/08/10 13:06:58 kaleb $ --- 506,518 ---- o Rod Grimes and Jack Velte of Walnut Creek Cdrom for use of their machines in preparing the FreeBSD binary release. ! Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/OpenBSD.sgml,v 1.1.2.5 1998/02/26 13:59:07 dawes Exp $ ! $TOG: README.OpenBSD /main/2 1998/03/06 16:38:56 kaleb $ *************** *** 499,504 **** --- 529,535 ---- + README for XFree86 3.3.2 on OpenBSD *************** *** 529,535 **** - README for XFree86 3.3.1 on OpenBSD --- 560,565 ---- *************** *** 569,604 **** - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CONTENTS --- 599,604 ---- *************** *** 610,637 **** 3. New features in this release ............................................ 1 4. Installing the Binaries ................................................. 1 - 4.1 Installing Xdm, the display manager ................................. 1 5. Configuring X for Your Hardware ......................................... 2 ! 5.1 About mouse configuration ........................................... 3 ! 5.2 Other input devices ................................................. 3 5.3 Configuring PEX and XIE extensions .................................. 3 ! 6. Running X ............................................................... 4 ! 7. Kernel Support for X .................................................... 4 ! 7.1 Aperture Driver ..................................................... 4 ! 7.2 MIT-SHM ............................................................. 5 ! 8. Rebuilding the XFree86 Distribution ..................................... 6 ! 8.1 Console drivers ..................................................... 6 ! 8.2 console.h and ioctl_pc.h files: ..................................... 7 ! 8.3 Building on other architectures ..................................... 7 ! 9. Building New X Clients .................................................. 7 ! 10. Thanks .................................................................. 7 --- 610,637 ---- 3. New features in this release ............................................ 1 4. Installing the Binaries ................................................. 1 5. Configuring X for Your Hardware ......................................... 2 ! 5.1 About mouse configuration ........................................... 2 ! 5.2 Other input devices ................................................. 2 5.3 Configuring PEX and XIE extensions .................................. 3 ! 6. Installing Xdm, the display manager ..................................... 3 ! 7. Running X ............................................................... 4 ! 8. Kernel Support for X .................................................... 4 ! 8.1 Aperture Driver ..................................................... 5 ! 8.2 MIT-SHM ............................................................. 6 ! 9. Rebuilding the XFree86 Distribution ..................................... 6 ! 9.1 Console drivers ..................................................... 7 ! 9.2 console.h and ioctl_pc.h files: ..................................... 7 ! 9.3 Building on other architectures ..................................... 7 ! 10. Building New X Clients .................................................. 8 + 11. Thanks .................................................................. 8 *************** *** 659,666 **** ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/README.OpenBSD,v 1.1.2.3 1997/08/02 13:53:32 dawes Exp $ ! $TOG: README.OpenBSD /main/1 1997/08/10 13:06:58 kaleb $ --- 659,666 ---- ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/README.OpenBSD,v 1.1.2.6 1998/02/27 02:55:01 dawes Exp $ ! $TOG: README.OpenBSD /main/2 1998/03/06 16:38:56 kaleb $ *** ./xfree86/doc/README.SiS@@/PUBLIC-LATEST Sat Jul 19 10:54:19 1997 --- xc/programs/Xserver/hw/xfree86/doc/README.SiS Fri Mar 6 16:37:43 1998 *************** *** 11,25 **** Xavier Ducoin (xavier@rd.lectra.fr) ! 16 January 1997 1. Introduction ! The driver was primarily written for the SiS86c201. The driver has almost been ! completed, with many additional features. These include o Linear Addressing o 8/15/16/24 bits per pixel --- 11,29 ---- Xavier Ducoin (xavier@rd.lectra.fr) ! 27 February 1998 1. Introduction ! This driver was primarily written for the SiS86c201. It also works on the 202 ! and the 205 chips. Support for other SiS products is not available in XFree86 ! release 3.3.2. Drivers for the 5597/8 are currently under development and ! should be available in the next release. + The driver supports many advanced features. These include: + o Linear Addressing o 8/15/16/24 bits per pixel *************** *** 56,66 **** This option will disable the use of the XAA and will enable the old BitBlt acceleration operations. (see below). - Option "hw_clocks" - On chips 86c202 and later, the default is to use the programmable - clock for all clocks. It is possible to use the fixed clocks - Information for SiS Users --- 60,66 ---- *************** *** 71,77 **** ! supported by the chip instead of using this option (manufacturer dependent). Option "sw_cursor", "hw_cursor" --- 71,80 ---- ! Option "hw_clocks" ! On chips 86c202 and later, the default is to use the programmable ! clock for all clocks. It is possible to use the fixed clocks sup- ! ported by the chip instead of using this option (manufacturer dependent). Option "sw_cursor", "hw_cursor" *************** *** 118,124 **** problem (It can take one hour, two or more). I can't reproduce this problem in 1024x768 75 MHz or 1280x1024 110 MHz or 1152x900 95 MHz. ! Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/SiS.sgml,v 3.3 1997/01/25 03:22:15 dawes Exp $ --- 121,127 ---- problem (It can take one hour, two or more). I can't reproduce this problem in 1024x768 75 MHz or 1280x1024 110 MHz or 1152x900 95 MHz. ! Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/SiS.sgml,v 3.3.2.1 1998/02/27 02:45:24 dawes Exp $ *************** *** 130,138 **** - - - Information for SiS Users --- 133,138 ---- *************** *** 263,270 **** ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/README.SiS,v 3.5 1997/01/27 22:12:56 dawes Exp $ ! $TOG: README.SiS /main/1 1997/07/19 10:54:20 kaleb $ --- 263,270 ---- ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/README.SiS,v 3.5.2.1 1998/02/27 02:55:02 dawes Exp $ ! $TOG: README.SiS /main/2 1998/03/06 16:39:21 kaleb $ *** ./xfree86/doc/RELNOTES@@/PUBLIC-LATEST Sun Aug 10 13:02:55 1997 --- xc/programs/Xserver/hw/xfree86/doc/RELNOTES Fri Mar 6 16:38:24 1998 *************** *** 1,28 **** ! Release Notes for XFree86[tm] 3.3.1 ! Release Notes for XFree86[tm] 3.3.1 The XFree86 Project, Inc ! 4 August 1997 Abstract ! This document describes the bugs fixed in XFree86 3.3.1 compared with ! the 3.3 release, as well as the new features in XFree86 3.3 compared ! with the previous full release, 3.2. It also includes installation ! instructions for the binary distributions. --- 1,27 ---- ! Release Notes for XFree86[tm] 3.3.2 ! Release Notes for XFree86[tm] 3.3.2 The XFree86 Project, Inc ! 28 February 1998 Abstract ! This document describes the bugs fixed and the features added in ! XFree86 3.3.2 compared with the 3.3.1 release, It also includes ! installation instructions for the binary distributions. *************** *** 51,791 **** Always check the OS specific README files for special requirements or caveats. ! Users running Linux/Elf (on Intel platforms) should note that they will need ! ld.so version 1.7.14 or later. This can be found at ! ftp://tsx-11.mit.edu/pub/linux/packages/GCC. - Note: Elf is now the only binary type supported for Linux OSs. This means that - binaries for ix86/a.out and AXP/ECOFF are not available with this release. - Release Notes for XFree86[tm] 3.3.1 - Release Notes for XFree86[tm] 3.3.1 - 3. What's new in 3.3.1? - 3.1 Bug fixes ! o XFree86 3.3.1 includes The Open Group's public patch 2 for X11R6.3. ! o Build problems that showed up on some OSs have been fixed. ! o Support for SCO Open Server 5 should now be complete. ! o A malloc problem in libXt which showed up on FreeBSD has been fixed. ! o Depth-specific DacSpeeds are now implemented for the ET6000. ! o Depth-specific DacSpeeds are fixed for the S3 server. ! o HW cursor problem with the I128 server has been fixed. ! o I128 Series II rev 2 chips are now supported. ! o Xterm will now startup on Linux if /etc/termcap is missing. ! o Various problems with the S3V server and the SVGA s3v driver have been ! fixed. ! o A problem with the clock limit for some revisions of the Circus 5434 has ! been fixed. ! o The Mach64 server will now correctly recognise some of the newer ATI chip ! revisions, including the Rage II+, Rage Pro and VT3. If you needed the ! ChipId/ChipRev workaround when using 3.3, you should remove those lines ! from your XF86Config file when upgrading to 3.3.1. ! o An initialisation problem in the S3 server that shows up when the ramdac ! type is given in the XF86Config file should be fixed. ! o The MGA driver now defaults to using the software cursor because some peo- ! ple have reported problems when using the hardware cursor with Millennium ! cards. ! o Lockups with the MGA driver that happen on some SVR4 versions have been ! fixed. Lockups when the server crashes and dumps core on some OSs have ! also been fixed where possible. ! o The xterm termcap field for turning off colour has been fixed. ! o A server crash that happens when starting some servers on Solaris has been ! fixed. ! o Some problems with the Trident 9860 and 9685 chips have been fixed. ! o A problem with xterm writing an invalid wtmp entry on Linux has been ! fixed. - Release Notes for XFree86[tm] 3.3.1 - o A PolyPoint bug in the S3V server has been fixed. - o Screen wraparound problems with the S3 server that show up on some old - Number Nine GXE level 10 cards have been fixed. - o A problem with the PCI framebuffer remapping in the S3 server has been - fixed. ! o A problem with XF86Setup not showing the correct chipset-specific README ! file has been fixed. - o A problem with XF86Setup not setting up the link to the Xserver in some - situations has been fixed. - o Some libXt error/warning messages were partially duplicated, and this is - now fixed. ! o Some line drawing problems that show up with the Cirrus 542x chips have ! been fixed. ! o A problem drawing wide fonts with some Cirrus chips has been fixed. ! o Some bugs in some XKB symbols files have been fixed. ! o The Chips and Technologies 65555 and 68554 are now detected by the chips ! driver. ! o `xset dpms' didn't accept some parameters correctly. ! o Some raster op bugs in the SVGA server's s3v driver have been fixed. ! o Problems with the Mach32 server that show up with some AST motherboards ! that have an on-board Mach32 chip have been fixed (see the README.Mach32 ! file for details). ! o A bug in the ET6000 driver which can cause the server to crash on non- ! Linux systems has been fixed. ! o An initialisation problem with the ET6000 driver which can result in a ! black screen has been fixed. ! o The Eraser support in the Wacom driver has been fixed. ! o Support for two relative devices has been fixed in the Wacom driver. ! o The DPMS state is now correctly reset when switching back to the Xserver's ! VT. ! o A bug in the 24bpp framebuffer code which caused a server crash when run- ! ning StarOffice has been fixed. ! o An Xserver bug which could cause a server crash when using lbxproxy has ! been fixed. - Release Notes for XFree86[tm] 3.3.1 - o A conflict between Imake.rules and Motif.rules has been fixed. - o Some problems that show up with some accelerated servers on SVR4 when - using Xqueue have been fixed. - o A problem that can cause a server crash when drawing some arcs has been - fixed. - o The MGA driver now recognises the newer 220MHz Mystique chips. - o The MGA driver has experimental support for the Millennium II. This - really is very new, and is largely untested. There are known problems - (see README.MGA for details). - o The "noaccel" option could cause a lockup with the Cirrus Laguna chips - (546x). This option is now disabled for those chips. ! o Some blitter timeouts that show up with Cirrus 7548 and 7555 chips should ! now be fixed. - o The handling of the PS/2 mouse protocol is fixed for OpenBSD. - o The SiS driver should now correctly determine the MMIO address. ! 3.2 Known Problems ! o There are problems with some Cirrus laptop chipsets (75xx). The driver ! seems to work for some people, but not others. Until someone with the ! appropriate hardware can look into this, these problems are unlikely to be ! fixed. If you wish to work on this, please contact us. We don't need ! testers, we need people willing and able to fix the problems. ! o There are problems with some of the Trident laptop chipsets. The driver ! seems to work in a limited way for some people, but not others. Until ! someone with the appropriate hardware can look into this, these problems ! are unlikely to be fixed. If you wish to work on this, please contact us. ! We don't need testers, we need people willing and able to fix the prob- ! lems. ! o We have had some reports of apparently random lockups with some Mystique ! cards. We have not been able to reproduce this problem, and have no fix ! for it. ! o There is a drawing bug in the MGA driver that shows up when running `view- ! fax'. We have no fix for this problem yet. ! o Some people have reported problems with some newer Rage II cards. We have ! no fix for this problem yet. ! o We've had a report that the SVGA server will cause a lockup on some SVR4 ! versions (UnixWare 1.x) with some Chips and Technologies chips. A ! workaround for this problem is to use the "xaa_no_color_exp" option. ! Release Notes for XFree86[tm] 3.3.1 - 4. New Features in 3.3 - 4.1 General - o XFree86 3.3 includes the X Consortium's X11R6.3. - 4.2 General X server changes - o The X servers include a new DPMS extension, which was donated by Digital - Equipment Corporation. Not all DPMS modes have been implemented by all - servers yet, but this should improve in future releases. See the XF86Con- - fig(4/5) and xset(1) man pages for further details. ! o The LBX extension is included in all the X servers, as part of the update ! to R6.3. - o A print-only server (Xprt) is included as part of the update to R6.3. - o Some bugs in the Type1 font code have been fixed. ! o Some bugs in newer functions in the XFree86 VidMode extension have been ! fixed. - o Support has been added for the Microsoft IntelliMouse. ! 4.3 XF86Setup ! o Some bugs have been fixed, but no major changes have been made to this ! version. ! o More modelines were added. There are now high-refresh versions of most ! common modes available (85 and 100 Hz). 512x384, 1152x864, 1600x1200 and ! 1800x1440 modes were added. ! 4.4 PC98 Support ! ! o The XF98_TGUI server includes XAA support, but there are some problems ! with this at the moment. It can be disabled with the "noaccel" option. ! ! 4.5 Alpha (AXP) platform support ! ! o Support for the S3 ViRGE and ViRGE/VX is now available. ! ! o Support for "newmmio" is now available for the S3 868/968/Trio64V+ and is ! enabled by default (use chipset "mmio_928" to get the old behaviour). ! ! o Support for the Matrox Millennium and Mystique (in the SVGA server) is ! included. ! ! o Support for the Trident driver (in the SVGA server) is included. ! ! o Some problems that showed up with Netscape on some servers have been ! fixed. ! ! ! ! ! ! ! ! ! ! Release Notes for XFree86[tm] 3.3.1 ! ! ! ! o Various alignment problems have been fixed. ! ! o NOTE: A recent Linux kernel version is required for most of these servers ! (essential for the Matrox driver). ! ! o Scanpci now works on Alpha platforms. ! ! 4.6 XInput Extension ! ! o Multiple input devices can share the core pointer. ! ! 4.6.1 Wacom driver ! ! o Multiple devices can be defined for the same tablet to represent different ! active zones. ! ! 4.7 XKEYBOARD Extension ! ! o An improved layout for Russian keyboards is provided. ! ! o A layout for Hungarian keyboards is provided. ! ! 4.8 SVGA server ! ! o A new general graphics acceleration interface (XFree86 Acceleration Archi- ! tecture - XAA) has been implemented. It is used to provide relatively ! complete acceleration, at different colour depths, for several chips in ! the SVGA server. Chips currently making use of this include the Matrox ! Millennium, Mystique, Tseng ET4000/W32p and ET6000, and several chips from ! ARK Logic, Chips and Technologies, Cirrus, Trident, SiS and the S3 ViRGE ! family. ! ! o The SVGA server now includes a driver for the S3 ViRGE family. It supports ! the ViRGE, ViRGE/DX, ViRGE/GX and ViRGE/VX. This driver is a completely ! new implementation, so please send in success/failure reports. ! ! 4.9 S3 server ! ! o Some further S3 968 hardware bugs for lines/text have been worked around. ! ! o Cursor/pointer pixmaps larger than 64x64 are now supported without the ! need to use the "sw_cursor" option. ! ! o Detection/support for the Trio64UV+, Trio64V2 (including the /DX and /GX ! versions), Aurora64V+ (86CM65 used in notebooks), and Plato/PX is now ! included. This support is very new and hasn't had much testing, so please ! send us success/failure reports. ! ! o Support is now included for the ELSA Winner 2000PRO/X-8. Please refer to ! the notes for this card in README.S3. ! ! o Support is now included for the MIRO 80SV. ! ! ! ! ! ! ! ! ! ! ! Release Notes for XFree86[tm] 3.3.1 ! ! ! ! o A bug which prevented DGA apps from setting the ViewPort to the lower part ! of the framebuffer has been fixed (this showed up most commonly with 4MB ! cards). ! ! 4.10 S3V (ViRGE) server ! ! o Support has been added for the ViRGE/DX and ViRGE/GX. ! ! o Problems with the Diamond Stealth 3D 3000 are now fixed. ! ! o The line drawing code has been improved. ! ! o Packed 24bpp support is included, and should be improved over earlier ver- ! sions. ! ! o The S3V server translates between sparse 32bpp pixmaps and packed 24bpp ! for the framebuffer. In some cases this can be slow. ! ! o 32bpp framebuffer format is not supported. ! ! 4.11 Mach64 server ! ! o Support for 3D Rage II based Mach64 cards is included. ! ! o Various problems with support for some revisions of CT, VT and GT chipsets ! have been fixed. ! ! o It is strongly recommended that all users with CT, VT, GT and 3D Rage II ! based Mach64 cards upgrade to the 3.3 release due to the problems that ! were fixed. ! ! 4.12 Mach32 server ! ! o A bug that causes problems when running XF86Setup with cards with less ! than 2MB of video memory has been fixed. ! ! o Minor shifts in maximum clock rate under 16 bpp, and inclusion of explicit ! 15 "bpp" setting. ! ! 4.13 W32 server ! ! o In this version, the separate W32 server (XF86_W32) has not undergone any ! significant changes. In fact, it is not being developed further. Instead, ! the SVGA server (XF86_SVGA) is now the main focus of new developments. See ! the W32 (SVGA) description. ! ! 4.14 P9000 server ! ! o Support for PCI probing has been added. ! ! o DPMS support has been added. ! ! ! ! ! ! ! ! ! ! ! ! Release Notes for XFree86[tm] 3.3.1 ! ! ! ! 4.15 I128 server ! ! o Some preliminary acceleration (for bitblts) is included. This code is ! very new, and hasn't been extensively tested yet. ! ! 4.16 TGA server ! ! o Preliminary acceleration support is included, using XAA. ! ! o Various bugs have been fixed. ! ! 4.17 Trident driver (SVGA server) ! ! o Acceleration support has been added for the 9320, 9440 and 96xx chips. ! ! o Support for the Cyber series of laptop chips has been improved. ! ! o 24/32bpp support has been added for some chips. ! ! o Some clock limits have been fixed. ! ! 4.18 Ark driver (SVGA server) ! ! o More complete acceleration has been implemented using XAA, including line ! draw, fill, and text acceleration, at different colour depths. ! ! 4.19 W32 driver (SVGA server) ! ! o The SVGA server now supports acceleration for the most recent ET4000W32 ! chips. In 3.3, the ET4000W32p chips are now fully accelerated, and also ! support the higher performing linear memory layout (read the tseng README ! file for more information: there are a few problems). ! ! o VESA DPMS (monitor power saving) support was added. ! ! o There is now support for more than 256 colors on most ET4000W32i and ! ET4000W32p chips. This means 15, 16, 24 and/or 32 bits per pixel modes ! (32768, 65536 or 16 million colors) are supported on most common RAMDACs. ! On the W32p, these modes are accelerated. On the W32i, there is no accel- ! eration in any mode. For accelerated support on W32i chips, refer to the ! separate W32 server (XF86_W32). ! ! o A few bugs in XFree86 3.2 and 3.2A have been fixed. Most importantly the ! failure to probe some PCI cards has been resolved. ! ! o Fix interference with ISA-DMA sensitive devices (soundcards, floppy-tape ! drives) ! ! o Support for the Chrontel RAMDAC has been added. ! ! 4.20 ET6000 driver (SVGA server) ! ! o The ET6000 driver in the separate W32 server (XF86_W32) has not changed ! significantly. ! ! ! ! ! ! ! ! ! Release Notes for XFree86[tm] 3.3.1 ! ! ! ! o On the other hand, the ET6000 driver in the SVGA server, which already ! existed in XFree86 3.2 for all color depths, is now fully accelerated for ! all those color depths. It builds upon the new XAA architecture, which is ! the cornerstone of a new acceleration framework within the XFree86 ! servers. It is responsible for the outstanding acceleration performance of ! this release. ! ! o Many small problems which existed in the initial 3.2 release have been ! solved. Screen noise, flicker or instability at higher pixel clocks are ! mostly fixed. Some detection problems are gone. Weird behaviour (jumping ! and screen wrap) when panning through large virtual desktops has been ! fixed. The server now detects the correct amount of memory on ET6000 cards ! with 2.25 MB of MDRAM. More realistic pixel clock rate limits have been ! put in place, to avoid modes that would cause screen problems. ! ! o DPMS support was added. ! ! o The ET6000 hardware cursor is now supported. Read the Tseng documentation ! file for more information (there are a few limitations) ! ! o fix interference with ISA-DMA sensitive devices (soundcards, floppy-tape ! drives) ! ! 4.21 Alliance ProMotion driver (SVGA server) ! ! o The driver now recognises the AT24 chipset, but it is treated the same way ! as the AP6422. ! ! 4.22 Matrox driver (SVGA server) ! ! o More complete acceleration for the Millennium (MGA2064W). ! ! o Support is included for the Mystique (including some acceleration). This ! code is very new. ! ! o 24 bpp mode tiled pattern problems still present. ! ! o Support for DGA, Sync-on-Green, and DPMS. ! ! o The "nolinear" option is no longer available. ! ! o Support for 8 bits per colour component (at 8bpp) has been added. ! ! 4.23 Cirrus driver (SVGA server) ! ! o More complete acceleration for all chips with a BitBLT engine (CL-GD5426, ! 5428, 5429, 5430, 5434, 5436, 5440, 5446, 7541, 7543, and 7548). ! ! o More complete acceleration for Laguna series chips (CL-GD546X). ! ! o The support for the 754x series of laptop controllers has been improved. ! ! o The 24bpp mode on the CL-GD5430/40 has been fixed. ! ! ! ! ! ! ! ! ! ! Release Notes for XFree86[tm] 3.3.1 ! ! ! ! o Support for the CL-GD5480 has been added. ! ! 4.24 SiS driver (SVGA server) ! ! o Significant updates have been made to the SiS driver (see README.SiS for ! further details). ! ! o Acceleration support is included, making use of XAA. ! ! o Linear addressing is supported. ! ! o Support has been added for 15/16/24bpp. ! ! o Support has been added for programmable clocks. ! ! o HW cursor support is included. ! ! 4.25 Chips and Technologies driver (SVGA server) ! ! o Support has been included for the 65525, 65535, 64200 and 64300 ! ! o Problems relating to blank screen at start-up and text mode restoration ! with the 65550 and 65554 should now be fixed ! ! o Acceleration support for all chips has improved due to the new XAA archi- ! tecture. ! ! o Many additional minor fixes and documentation updates (see README.chips ! for further details). ! ! 4.26 S3 ViRGE driver (SVGA server) ! ! o Completely new driver for the ViRGE family. The driver works with linear ! addressing and PCI chipsets. ! ! o Acceleration support uses the XAA architecture. ! ! o The driver supports 8/15/16/24/32 bpp on all cards. ! ! o Acceleration includes bitblits, filled rectangles, color expansion and ! pattern fills (8/15/16/24 bpp). Acceleration at 32 bpp is limited to bit- ! blits and filled rectangles. ! ! o Includes HW cursor support. ! ! o See README.S3V for further details. ! ! 4.27 WD90C24 driver (SVGA server) ! ! o DPMS support is included (only for "off" mode so far). ! ! 4.28 Compaq AVGA driver (SVGA server) ! ! ! ! ! ! ! ! ! ! ! Release Notes for XFree86[tm] 3.3.1 ! ! ! ! o The Compaq AVGA driver has been resurrected. The bugs causing it to not ! work in some previous releases have been fixed. ! ! 4.29 Hercules mono driver ! ! o The problems with the Hercules mono driver in previous releases has now ! been fixed, and the driver is included in this release. ! ! 4.30 Client/Library changes ! ! o The libraries have been updated to R6.3. The shared lib version numbers ! for libXext and libICE have been bumped to 6.3. The others remain the ! same. ! ! o An Xlib problem with non-latin-1 encodings that shows up when using XKB is ! fixed. ! ! o Some Xlib security vulnerabilities have been fixed. ! ! o Xterm's emulation of DECUDK (DEC user-defined keys) now (correctly) inter- ! prets shifted keys only. ! ! o VT52 emulation has been added to xterm. ! ! o Xterm's VT100 emulation generates correct codes for PF1-PF4, as well as ! the keypad "+" and ",". These codes differ from the VT220 emulation. ! ! o Some xterm bugs have been fixed, including coloured background exposure ! while selection is active, and missing state changes in the VT100 emula- ! tion. ! ! o Xterm's memory requirements for colour have been reduced. The colour ! resource file is merged with the regular resource file to reduce installa- ! tion problems. ! ! o Emulation of VT220 soft-reset, and non-DEC REP (repeat) control sequence ! has been added to xterm. ! ! o Xterm now recognizes control sequences for 16 colors (from aixterm). ! ! o xset includes support for the DPMS extension. ! ! o xset's "r rate" flag was broken on some OSs, and is now fixed. ! ! 4.31 xf86config utility ! ! o More modelines were added. There are now high-refresh versions of most ! common modes available (85 and 100 Hz). 512x384, 1152x864, 1600x1200 and ! 1800x1440 modes were added. ! ! 4.32 SuperProbe ! ! o Add detection of Alliance Pro Motion chips. ! ! ! ! ! ! ! ! ! ! Release Notes for XFree86[tm] 3.3.1 ! ! ! ! o Add detection of I128-2. ! ! o Add detection of S3 Trio64UV+ and Aurora64V+, Trio64V2/DX and /GX, S3 ! ViRGE/DX and /GX and Plato/PX. ! ! o Add detection of Matrox chips. ! ! o Add detection of newer Trident chips, including the Cyber series. ! ! o Fix detection of ET4000W32 chips, and their memory probing. ! ! o Add detection of newer ATI chips. ! ! o Add detection of STG170x and CH8398 RAMDACs ! ! o Add detection of Sigma Designs REALMagic ! ! o Add detection of 3DLabs GLINT ! ! 4.33 Fonts ! ! o Gzipped fonts are now supported. ! ! ! 5. Installing the XFree86 3.3.1 Release ! ! The XFree86 3.3.1 binaries are distributed as both a full release and as an ! upgrade to XFree86 3.3. ! ! What follows is a list of the XFree86 3.3.1 components. There may be some variations in this for some OSs. The following are required for all new installations or upgrades from versions ! prior to 3.3: preinst.sh Pre-installation script postinst.sh Post-installation script ! extract.tgz XFree86 extraction utility ! X331bin.tgz Clients, run-time libs, and app-defaults files ! X331doc.tgz Documentation ! X331fnts.tgz 75dpi, misc and PEX fonts ! X331lib.tgz Data files required at run-time ! X331man.tgz Manual pages ! X331set.tgz XF86Setup utility ! X331VG16.tgz 16 colour VGA server (XF86Setup needs this server) ! The following are required for an upgrade from XFree86 3.3: --- 50,326 ---- Always check the OS specific README files for special requirements or caveats. ! Users running Linux should note that Elf is now the only binary type supported ! for Linux OSs. This means that binaries for ix86/a.out and AXP/ECOFF are not ! available with this release. + 3. What's new in 3.3.2? + Release Notes for XFree86[tm] 3.3.2 + Release Notes for XFree86[tm] 3.3.2 ! 3.1 Security fixes ! o Several buffer overrun problem discovered since the release of ! XFree86-3.3.1 have been fixed ! o Several insecure X server command line options have been removed ! o The X servers now run the xkbcomp program under the user's real uid ! o Additionally, a wrapper program for the X servers has been added which ! eliminated the need for the servers to be installed SUID root ! 3.2 Bug fixes ! o A black screen problem in the Tseng driver has been fixed. ! o Several drawing problems in the Tseng driver have been corrected. ! o Timeouts to all routines waiting for the accelerator have been added. ! o DPMS has been fixed in the Tseng driver. ! o The memory clock for the Matrox Millennium II is now set correctly. ! o Several drawing bugs in the MGA driver have been fixed. ! o The problem with some Millennium II cards in higher resolutions and 24bpp ! is fixed. ! o Some problems with 24 and 32bpp in the Trident driver have been fixed. ! o Some problems in the C&T driver with the TMED DSTN dithering scheme for ! the 65555 and 68554 have been fixed. ! o The C&T driver now adheres much more strictly to the clock limits. ! o Allow DacSpeed command to work correctly in more servers. ! o Several small bugs for Cirrus Laguna chipsets have been fixed. ! o Fixes to the Wacom driver. + o The Cyrillic fonts have been updated. + o BSDI is supported again. + o Several XAA problems have been fixed. + o XKB for PC98 has been updated. + o S3 Aurora64V+ now works with 16bpp. + o cursor offset for some S3 cards has been fixed. ! Release Notes for XFree86[tm] 3.3.2 ! o S3 server support for STG 1700 ramdac has been fixed. ! o imake correctly works on Linux glibc-2 systems now. ! 3.3 New Features ! o Support for ET6100 has been added to the Tseng driver. ! o Acceleration has been added for W32 and W32i. ! o Text performance has been improved for the Tseng driver. ! o Support for new RAMDACs, including the ch8398, the ch8391 and the MUSIC ! MU9C4910 has been added to the Tseng driver. ! o Accelerated support for the AT3D and AT25 has been added to the APM ! driver. ! o Support for accelerated NV1 and accelerated Riva128 has been added to the ! NV driver. ! o Support for the Matrox Millennium II AGP has been included into the MGA ! driver. ! o New support for several Trident chips has been added, including Cyber9397, ! 3DImage975 and 3DImage985 (unaccelerated and not completed, yet), ! TGUI9685. ! o CrealTV support has been added for the TGUI9685. ! o Acceleration of all TGUI chipsets has been improved. ! o Support for Rage Pro based PCI and AGP cards has been added. + o Maximum dotclock for newer Mach64 cards has been increased. + o Support for 1600x1200 and 1600x1280 mode has been added for VT and newer + Mach64 chips. + o Support for the auxiliary register aperture for newer Mach64 cards has + been added. + o Support for the I128 Revolution (T2R) has been added. + o Additional acceleration for the I128 server has been added. + o Support for sw cursor, pci_retry, 24bpp HW cursor has been added to cirrus + Laguna chipsets. + o S3 ViRGE/MX and ViRGE/GX2 support has been added (SVGA server only!). + o support for S3 ViRGE hardware cursor added in SVGA server. ! Release Notes for XFree86[tm] 3.3.2 ! o An S3 driver has been added to the SVGA server. ! o S3 server and SVGA/S3 server now recognize some fake S3 chips and print ! out a warning message. ! o XAA has been extended to support hardware cursors and provide accelerated ! support dashed lines and trapezoid fills. ! o Several new mouse protocols have been added to all servers. They should ! now support Kensington ThinkingMouse, ALPS GlidePoint, Genius NetScroll, ! Genius NetMouse, Genius NetMouse, ASCII MieMouse, Logitech MouseMan+, Log- ! itech FirstMouse+. This includes all buttons on these mice as well as the ! wheels. The wheel can be used to either create additional buttons or for ! z-axis indication. ! o login.conf/setusercontext support to xdm for FreeBSD has been added. ! o XF86Setup now supports setting the default color depth and choosing the ! modes the user wants to use. ! o XF86Setup allows to select all the new mouse protocols (depending on the ! OS it is running on). + o Japanization of XF86Setup has been added. + o XF98_MGA server for Millennium and Mystique has been added. This server + is very new and has some problems with Mystique support. + o XF98_SVGA server for CLGD755x has been added. This server also is very new + and has some problems. + o Linux/98 support has been added. Linux/98 is very new and perhaps the + servers also have some problems. + o XF98_TGUI server now works on PANIX98. + o XF98Setup(i.e. XF86Setup for PC98) has been added. + o Many changes to xterm including support for double-size characters (posi- + tioning), blinking characters (render in color), improvements to logging, + transparent printing, delete/backspace toggle, and better support for Sun + and PC keyboards. + 3.4 Known Problems + o There are problems with some Cirrus laptop chipsets (75xx). The driver + seems to work for some people, but not others. Until someone with the + appropriate hardware can look into this, these problems are unlikely to be + fixed. If you wish to work on this, please contact us. We don't need + testers, we need people willing and able to fix the problems. ! o There are problems with some of the Trident laptop chipsets. The driver ! seems to work in a limited way for some people, but not others. Until ! someone with the appropriate hardware can look into this, these problems ! Release Notes for XFree86[tm] 3.3.2 ! are unlikely to be fixed. If you wish to work on this, please contact us. ! We don't need testers, we need people willing and able to fix the prob- ! lems. ! 4. Installing the XFree86 3.3.2 Release ! The XFree86 3.3.2 binaries are distributed as both a full release and as an ! upgrade to XFree86 3.3.1. ! NOTE: the X servers are no longer installed setuid root. If you are starting ! your X servers with startx/xinit, or something similar, you will need a copy of ! the setuid Xwrapper, and an updated xinit. These can be found in X332upd.tgz ! for those upgrading from 3.3.1, and in X332bin.tgz for those doing a full ! install. ! What follows is a list of the XFree86 3.3.2 components. There may be some variations in this for some OSs. The following are required for all new installations or upgrades from versions ! prior to 3.3.1: preinst.sh Pre-installation script postinst.sh Post-installation script ! extract XFree86 extraction utility ! X332bin.tgz Clients, run-time libs, and app-defaults files ! X332doc.tgz Documentation ! X332fnts.tgz 75dpi, misc and PEX fonts ! X332lib.tgz Data files required at run-time ! X332man.tgz Manual pages ! X332set.tgz XF86Setup utility ! X332VG16.tgz 16 colour VGA server (XF86Setup needs this server) ! The following are required for an upgrade from XFree86 3.3.1: + preinst.sh Pre-installation script + postinst.sh Post-installation script + extract XFree86 extraction utility + X332upd.tgz Changes since 3.3.1 (except the servers) + X332doc.tgz Documentation + X332set.tgz XF86Setup utility + X332VG16.tgz 16 colour VGA server (XF86Setup needs this server) + The following is required for new installations, and optional for existing + installations: + X332cfg.tgz sample config files for xinit, xdm *************** *** 793,822 **** - Release Notes for XFree86[tm] 3.3.1 ! preinst.sh Pre-installation script ! postinst.sh Post-installation script ! extract.tgz XFree86 extraction utility ! X331upd.tgz Changes since 3.3 (except the servers) ! X331doc.tgz Documentation ! X331set.tgz XF86Setup utility ! X331VG16.tgz 16 colour VGA server (XF86Setup needs this server) - The following is required for new installations, and optional for existing - installations: ! ! X331cfg.tgz sample config files for xinit, xdm ! ! ! NOTE: Be very careful about installing X331cfg.tgz over an existing installa- tion if you have customised your xinit and/or xdm config files. Installing ! X331cfg.tgz will overwrite any existing files. If you do have customised ! files, there is no need to install X331cfg.tgz. NOTE: The bitmap fonts distributed with this release are compressed using gzip rather than compress. This means that you will probably want to remove the old --- 328,344 ---- ! Release Notes for XFree86[tm] 3.3.2 ! NOTE: Be very careful about installing X332cfg.tgz over an existing installa- tion if you have customised your xinit and/or xdm config files. Installing ! X332cfg.tgz will overwrite any existing files. If you do have customised ! files, there is no need to install X332cfg.tgz. NOTE: The bitmap fonts distributed with this release are compressed using gzip rather than compress. This means that you will probably want to remove the old *************** *** 830,848 **** (XF86Setup). ! X3318514.tgz 8514/A server ! X331AGX.tgz AGX server ! X331I128.tgz I128 server ! X331Ma32.tgz Mach 32 server ! X331Ma64.tgz Mach 64 server ! X331Ma8.tgz Mach 8 server ! X331Mono.tgz Mono server ! X331P9K.tgz P9000 server ! X331S3.tgz S3 server ! X331S3V.tgz S3 ViRGE server ! X331SVGA.tgz SVGA server ! X331VG16.tgz 16 colour VGA server (XF86Setup needs this server) ! X331W32.tgz ET4000/W32, ET6000 server --- 352,370 ---- (XF86Setup). ! X3328514.tgz 8514/A server ! X332AGX.tgz AGX server ! X332I128.tgz I128 server ! X332Ma32.tgz Mach 32 server ! X332Ma64.tgz Mach 64 server ! X332Ma8.tgz Mach 8 server ! X332Mono.tgz Mono server ! X332P9K.tgz P9000 server ! X332S3.tgz S3 server ! X332S3V.tgz old S3 ViRGE server (please use SVGA server) ! X332SVGA.tgz SVGA server ! X332VG16.tgz 16 colour VGA server (XF86Setup needs this server) ! X332W32.tgz ET4000/W32, ET6000 server *************** *** 849,857 **** --- 371,389 ---- The following X servers are available for Alpha hardware: + X332Ma64.tgz Mach 64 server + X332Mono.tgz Mono server (generic driver only) + X332P9K.tgz P9000 server + X332TGA.tgz DEC 21030 (TGA) server + X332S3.tgz S3 server + X332S3V.tgz old S3 ViRGE server (please use SVGA server) + X332SVGA.tgz SVGA server (Matrox Millennium driver only) + The following X servers are for PC98 hardware. If you have a PC98 machine, + choose one which suits your hardware. If you don't know what a PC98 machine + is, you don't need any of these. *************** *** 859,916 **** - Release Notes for XFree86[tm] 3.3.1 - X331Ma64.tgz Mach 64 server - X331Mono.tgz Mono server (generic driver only) - X331P9K.tgz P9000 server - X331TGA.tgz DEC 21030 (TGA) server - X331S3.tgz S3 server - X331S3V.tgz S3 ViRGE server - X331SVGA.tgz SVGA server (Matrox Millennium driver only) ! The following X servers are for PC98 hardware. If you have a PC98 machine, ! choose one which suits your hardware. If you don't know what a PC98 machine ! is, you don't need any of these. - X3319NS3.tgz PC98 NEC(S3) server - X3319SPW.tgz PC98 PCSKB-PowerWindow(S3) server - X3319LPW.tgz PC98 PowerWindowLB(S3) server - X3319EGC.tgz PC98 EGC(generic) server - X3319GA9.tgz PC98 GA-968V4/PCI(S3 968) server - X3319GAN.tgz PC98 GANB-WAP(cirrus) server - X3319480.tgz PC98 PEGC-480(generic) server - X3319NKV.tgz PC98 NKV-NEC(cirrus) server - X3319WS.tgz PC98 WABS(cirrus) server - X3319WEP.tgz PC98 WAB-EP(cirrus) server - X3319WSN.tgz PC98 WSN-A2F(cirrus) server - X3319TGU.tgz PC98 TGUI server The following are optional. ! X331f100.tgz 100dpi fonts ! X331fcyr.tgz Cyrillic fonts ! X331fnon.tgz Other fonts (Chinese, Japanese, Korean, Hebrew) ! X331fscl.tgz Scalable fonts (Speedo and Type1) ! X331fsrv.tgz Font server and config files ! X331prog.tgz X header files, config files and compile-time libs ! X331nest.tgz Nested X server ! X331vfb.tgz Virtual framebuffer X server ! X331prt.tgz X Print server ! X331ps.tgz PostScript version of the documentation ! X331html.tgz HTML version of the documentation ! X331jdoc.tgz Documentation in Japanese (for version 3.2) ! X331jhtm.tgz HTML version of the documentation in Japanese (3.2) ! X331lkit.tgz X server LinkKit ! X331lk98.tgz X server LinkKit for PC98 servers If you already have a version of XFree86 installed, MAKE A BACKUP OF /usr/X11R6 --- 391,442 ---- ! Release Notes for XFree86[tm] 3.3.2 + X3329NS3.tgz PC98 NEC(S3) server + X3329SPW.tgz PC98 PCSKB-PowerWindow(S3) server + X3329LPW.tgz PC98 PowerWindowLB(S3) server + X3329EGC.tgz PC98 EGC(generic) server + X3329GA9.tgz PC98 GA-968V4/PCI(S3 968) server + X3329GAN.tgz PC98 GANB-WAP(cirrus) server + X3329480.tgz PC98 PEGC-480(generic) server + X3329NKV.tgz PC98 NKV-NEC(cirrus) server + X3329WS.tgz PC98 WABS(cirrus) server + X3329WEP.tgz PC98 WAB-EP(cirrus) server + X3329WSN.tgz PC98 WSN-A2F(cirrus) server + X3329TGU.tgz PC98 TGUI server + X3329MGA.tgz PC98 MGA server + X3329SVG.tgz PC98 CLGD755x server + X3329set.tgz PC98 XF98Setup utility + The following are optional. ! X332f100.tgz 100dpi fonts ! X332fcyr.tgz Cyrillic fonts ! X332fnon.tgz Other fonts (Chinese, Japanese, Korean, Hebrew) ! X332fscl.tgz Scalable fonts (Speedo and Type1) ! X332fsrv.tgz Font server and config files ! X332prog.tgz X header files, config files and compile-time libs ! X332nest.tgz Nested X server ! X332vfb.tgz Virtual framebuffer X server ! X332prt.tgz X Print server ! X332ps.tgz PostScript version of the documentation ! X332html.tgz HTML version of the documentation ! X332jdoc.tgz Documentation in Japanese (for version 3.2) ! X332jhtm.tgz HTML version of the documentation in Japanese (3.2) ! X332lkit.tgz X server LinkKit ! X332lk98.tgz X server LinkKit for PC98 servers If you already have a version of XFree86 installed, MAKE A BACKUP OF /usr/X11R6 *************** *** 917,924 **** --- 443,460 ---- BEFORE DOING ANYTHING ELSE. The standard installation procedure will overwrite your existing version of XFree86. + If you are installing from scratch, create a directory called /usr/X11R6, then + extract the required .tgz files. If you don't have enough space in /usr for + this, create a directory elsewhere and create a symbolic link to it. E.g., if + you create a directory in /home: + mkdir /home/X11R6 + ln -s /home/X11R6 /usr + The next step is to run the pre-installation script. This script makes some + preliminary checks of your system. For some OSs, it may tell you to install + new versions of some system components before proceeding with the installation. + This script may also remove some outdated files and symbolic links from a *************** *** 925,947 **** - Release Notes for XFree86[tm] 3.3.1 - If you are installing from scratch, create a directory called /usr/X11R6, then - extract the required .tgz files. If you don't have enough space in /usr for - this, create a directory elsewhere and create a symbolic link to it. E.g., if - you create a directory in /home: - mkdir /home/X11R6 - ln -s /home/X11R6 /usr ! The next step is to run the pre-installation script. This script makes some ! preliminary checks of your system. For some OSs, it may tell you to install ! new versions of some system components before proceeding with the installation. ! This script may also remove some outdated files and symbolic links from a pre- ! vious installation that could cause problems. For the purposes of these installation instructions, it is assumed that you have downloaded all the files to the /var/tmp directory. If you've put them in --- 461,473 ---- + Release Notes for XFree86[tm] 3.3.2 ! previous installation that could cause problems. For the purposes of these installation instructions, it is assumed that you have downloaded all the files to the /var/tmp directory. If you've put them in *************** *** 953,964 **** cd /usr/X11R6 sh /var/tmp/preinst.sh ! The next step is to untar the installation utility. To do this, make sure the ! extract.tgz file is in the same directory as all the X331*.tgz files, and run ! the following from that directory: ! cd /var/tmp ! gzip -d < extract.tgz | tar vxf - The installation utility ``extract'' is used to unpack the .tgz files that make up the XFree86 distribution. The .tgz files are gzipped tar files. However, --- 479,489 ---- cd /usr/X11R6 sh /var/tmp/preinst.sh ! The next step is to make the installation utility executable. To do this, make ! sure the `extract' file is in the same directory as all the X332*.tgz files, ! and run the following from that directory: ! chmod 755 extract The installation utility ``extract'' is used to unpack the .tgz files that make up the XFree86 distribution. The .tgz files are gzipped tar files. However, *************** *** 977,1000 **** To extract the XFree86 binaries, run the following as root: cd /usr/X11R6 ! /var/tmp/extract /var/tmp/X331*.tgz Once the required .tgz files have been extracted, run the post installation script: cd /usr/X11R6 - - - - - - - - - Release Notes for XFree86[tm] 3.3.1 - - - sh /var/tmp/postinst.sh For OSs which use ldconfig, you may need to run ldconfig or reboot to complete --- 502,513 ---- To extract the XFree86 binaries, run the following as root: cd /usr/X11R6 ! /var/tmp/extract /var/tmp/X332*.tgz Once the required .tgz files have been extracted, run the post installation script: cd /usr/X11R6 sh /var/tmp/postinst.sh For OSs which use ldconfig, you may need to run ldconfig or reboot to complete *************** *** 1002,1008 **** if you are using Linux, FreeBSD, NetBSD or OpenBSD. For other OSs that use ldconfig, check how it normally gets run at boot time. ! Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/RELNOTE.sgml,v 3.59.2.21 1997/08/04 02:10:43 dawes Exp $ --- 515,521 ---- if you are using Linux, FreeBSD, NetBSD or OpenBSD. For other OSs that use ldconfig, check how it normally gets run at boot time. ! Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/RELNOTE.sgml,v 3.59.2.37 1998/02/28 13:00:00 dawes Exp $ *************** *** 1016,1021 **** --- 529,535 ---- + Release Notes for XFree86[tm] 3.3.2 *************** *** 1057,1063 **** - Release Notes for XFree86[tm] 3.3.1 --- 571,576 ---- *************** *** 1086,1097 **** --- 599,619 ---- + CONTENTS + 1. XFree86 and X11R6.3 ...................................................... 1 + 2. OS issues ................................................................ 1 + 3. What's new in 3.3.2? ..................................................... 1 + 3.1 Security fixes ....................................................... 2 + 3.2 Bug fixes ............................................................ 2 + 3.3 New Features ......................................................... 3 + 3.4 Known Problems ....................................................... 4 + 4. Installing the XFree86 3.3.2 Release ..................................... 5 *************** *** 1127,1194 **** - CONTENTS - 1. XFree86 and X11R6.3 ...................................................... 1 - 2. OS issues ................................................................ 1 - 3. What's new in 3.3.1? ..................................................... 2 - 3.1 Bug fixes ........................................................... 2 - 3.2 Known Problems ...................................................... 4 - 4. New Features in 3.3 ...................................................... 5 - 4.1 General ............................................................. 5 - 4.2 General X server changes ............................................ 5 - 4.3 XF86Setup ........................................................... 5 - 4.4 PC98 Support ........................................................ 5 - 4.5 Alpha (AXP) platform support ........................................ 5 - 4.6 XInput Extension .................................................... 6 - 4.7 XKEYBOARD Extension ................................................. 6 - 4.8 SVGA server ......................................................... 6 - 4.9 S3 server ........................................................... 6 - 4.10 S3V (ViRGE) server .................................................. 7 - 4.11 Mach64 server ....................................................... 7 - 4.12 Mach32 server ....................................................... 7 - 4.13 W32 server .......................................................... 7 - 4.14 P9000 server ........................................................ 7 - 4.15 I128 server ......................................................... 8 - 4.16 TGA server .......................................................... 8 - 4.17 Trident driver (SVGA server) ........................................ 8 - 4.18 Ark driver (SVGA server) ............................................ 8 - 4.19 W32 driver (SVGA server) ............................................ 8 - 4.20 ET6000 driver (SVGA server) ......................................... 8 - 4.21 Alliance ProMotion driver (SVGA server) ............................. 9 - 4.22 Matrox driver (SVGA server) ......................................... 9 - 4.23 Cirrus driver (SVGA server) ......................................... 9 - 4.24 SiS driver (SVGA server) ........................................... 10 - 4.25 Chips and Technologies driver (SVGA server) ........................ 10 - 4.26 S3 ViRGE driver (SVGA server) ...................................... 10 - 4.27 WD90C24 driver (SVGA server) ....................................... 10 - 4.28 Compaq AVGA driver (SVGA server) ................................... 10 - 4.29 Hercules mono driver ............................................... 11 - 4.30 Client/Library changes ............................................. 11 - 4.31 xf86config utility ................................................. 11 - 4.32 SuperProbe ......................................................... 11 - 4.33 Fonts .............................................................. 12 - - 5. Installing the XFree86 3.3.1 Release .................................... 12 - - - - - - - - i ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/RELNOTES,v 3.52.2.17 1997/08/04 02:12:40 dawes Exp $ ! $TOG: RELNOTES /main/2 1997/08/10 13:01:31 kaleb $ --- 649,666 ---- i ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/RELNOTES,v 3.52.2.22 1998/02/28 13:05:36 dawes Exp $ ! $TOG: RELNOTES /main/3 1998/03/06 16:40:02 kaleb $ *** ./xfree86/doc/sgml/BUILD.sgml@@/PUBLIC-LATEST Sat Jul 19 10:54:58 1997 --- xc/programs/Xserver/hw/xfree86/doc/sgml/BUILD.sgml Fri Mar 6 16:39:07 1998 *************** *** 3,9 **** <article> <title>Building XFree86 <author>David Dawes ! <Date>2 June 1997 <abstract> This document describes how to build XFree86 from the <bf>source</bf> --- 3,9 ---- <article> <title>Building XFree86 <author>David Dawes ! <Date>27 February 1997 <abstract> This document describes how to build XFree86 from the <bf>source</bf> *************** *** 31,105 **** build or execution failures. (gcc-2 is available from prep.ai.mit.edu and other sites archiving GNU source.) ! <sect1>How to get the XFree86 3.3 source <p> There are a few starting points for getting the XFree86 source. One option ! is to start directly with the XFree86 3.3 source distribution. In this case, the procedure is as follows: <itemize> ! <item>The XFree86 3.3 source is contained in files <tt>X33src-1.tgz</tt>, ! <tt>X33src-2.tgz</tt> and <tt>X33src-3.tgz</tt>. These can be found ! at <htmlurl name="ftp://ftp.xfree86.org/pub/XFree86/3.3/source/" ! url="ftp://ftp.xfree86.org/pub/XFree86/3.3/source/"> and similar ! locations on XFree86 mirror sites. <tt>X33src-2.tgz</tt> contains ! the fonts and documentation source. <tt>X33src-3.tgz</tt> contains ! the hardcopy documentation. <tt>X33src-1.tgz</tt> contains everything else. If you don't need the docs or fonts you can get ! by with only <tt>X33src-1.tgz</tt>. <item>Extract each of these files by running the following from a directory on a filesystem containing enough space (the full source requires ! around 130MB, and a similar amount is required in addition to this for the compiled binaries): <quote><verb> ! gzip -d < X33src-1.tgz | tar vxf - ! gzip -d < X33src-2.tgz | tar vxf - ! gzip -d < X33src-3.tgz | tar vxf - </verb></quote> </itemize> Another option is to start with the X11R6.3 source distribution and patch ! it up to XFree86 3.3. In this case you need to do the following: <itemize> <item>Start with the X Consortium's X11R6.3 distribution with public ! patch 1 applied. This can be obtained by following the links ! from the <url name="X home page" url="http://www.x.org">. ! <item>Get the files <tt>R6.3pl1-3.3.diff1.gz</tt>, ! <tt>R6.3pl1-3.3.diff2.gz</tt>, <tt>R6.3pl1-3.3.diff3.gz</tt>, ! <tt>R6.3pl1-3.3.diff4.gz</tt>, and <tt>cfont33.tgz</tt> ! from <htmlurl name="ftp://ftp.xfree86.org/pub/XFree86/3.3/patches/" ! url="ftp://ftp.xfree86.org/pub/XFree86/3.3/patches/"> (or a similar ! location on mirror sites). To upgrade the source to XFree86 3.3, run the following from directory containing the <tt>xc</tt> ! directory of the X11R6.3 pl1 source tree: <quote><verb> ! gzip -d < R6.3pl1-3.3.diff1.gz | patch -p0 -E ! gzip -d < R6.3pl1-3.3.diff2.gz | patch -p0 -E ! gzip -d < R6.3pl1-3.3.diff3.gz | patch -p0 -E ! gzip -d < R6.3pl1-3.3.diff4.gz | patch -p0 -E ! gzip -d < cfont33.tgz | tar vxf - </verb></quote> Be sure to do this with a clean unmodified source tree. If you don't some patches may fail. </itemize> If you only want to build the XFree86 X servers, you can use a cut-down version of the XFree86 source tree called the ``servers only'' distribution. If you choose this option, do the following: <itemize> ! <item>Get the <tt>X33servonly.tgz</tt> file from ! <htmlurl name="ftp://ftp.xfree86.org/pub/XFree86/3.3/source/" ! url="ftp://ftp.xfree86.org/pub/XFree86/3.3/source/"> (or a similar locations on mirror sites. <item>Extract this by running the following: <quote><verb> ! gzip -d < X33servonly.tgz | tar vxf - </verb></quote> </itemize> - There is no patch to upgrade from the XFree86 3.2 source to 3.3. The - reason for this is the large number of changes associated with the - move from X11R6.1 to X11R6.3. - XFree86 supports a small subset of the X Consortium X11R6.1 contrib distribution. If you wish to build this, you will need at least the following files/directories from that distribution: --- 31,123 ---- build or execution failures. (gcc-2 is available from prep.ai.mit.edu and other sites archiving GNU source.) ! <sect1>How to get the XFree86 3.3.2 source <p> There are a few starting points for getting the XFree86 source. One option ! is to start directly with the XFree86 3.3.2 source distribution. In this case, the procedure is as follows: <itemize> ! <item>The XFree86 3.3.2 source is contained in files <tt>X332src-1.tgz</tt>, ! <tt>X332src-2.tgz</tt> and <tt>X332src-3.tgz</tt>. These can be found ! at <htmlurl name="ftp://ftp.xfree86.org/pub/XFree86/3.3.2/source/" ! url="ftp://ftp.xfree86.org/pub/XFree86/3.3.2/source/"> and similar ! locations on XFree86 mirror sites. <tt>X332src-2.tgz</tt> contains ! the fonts and documentation source. <tt>X332src-3.tgz</tt> contains ! the hardcopy documentation. <tt>X332src-1.tgz</tt> contains everything else. If you don't need the docs or fonts you can get ! by with only <tt>X332src-1.tgz</tt>. <item>Extract each of these files by running the following from a directory on a filesystem containing enough space (the full source requires ! around 140MB, and a similar amount is required in addition to this for the compiled binaries): <quote><verb> ! gzip -d < X332src-1.tgz | tar vxf - ! gzip -d < X332src-2.tgz | tar vxf - ! gzip -d < X332src-3.tgz | tar vxf - </verb></quote> </itemize> Another option is to start with the X11R6.3 source distribution and patch ! it up to XFree86 3.3.2. In this case you need to do the following: <itemize> <item>Start with the X Consortium's X11R6.3 distribution with public ! patches 1 and 2 applied. This can be obtained by following the links ! from the <url name="The Open Group's X home page" ! url="http://www.opengroup.org/tech/desktop/x/">. ! <item>Get the files <tt>R6.3pl2-3.3.2.diff1.gz</tt>, ! <tt>R6.3pl2-3.3.2.diff2.gz</tt>, <tt>R6.3pl2-3.3.2.diff3.gz</tt>, ! <tt>R6.3pl2-3.3.2.diff4.gz</tt>, and <tt>cfont332.tgz</tt> ! from <htmlurl name="ftp://ftp.xfree86.org/pub/XFree86/3.3.2/patches/" ! url="ftp://ftp.xfree86.org/pub/XFree86/3.3.2/patches/"> (or a similar ! location on mirror sites). To upgrade the source to XFree86 3.3.2, run the following from directory containing the <tt>xc</tt> ! directory of the X11R6.3 pl2 source tree: <quote><verb> ! gzip -d < R6.3pl2-3.3.2.diff1.gz | patch -p0 -E ! gzip -d < R6.3pl2-3.3.2.diff2.gz | patch -p0 -E ! gzip -d < R6.3pl2-3.3.2.diff3.gz | patch -p0 -E ! gzip -d < R6.3pl2-3.3.2.diff4.gz | patch -p0 -E ! gzip -d < cfont332.tgz | tar vxf - </verb></quote> Be sure to do this with a clean unmodified source tree. If you don't some patches may fail. </itemize> + A further option is to start with the XFree86 3.3.1 source, and patch + it up to XFree86 3.3.2. In this case you need to do the following: + <itemize> + <item>If using this option, you would already have the XFree86 3.3.1 + source. + <item>Get the files <tt>3.3.1-3.3.2.diff.gz</tt>, + and <tt>cfont332.tgz</tt> + from <htmlurl name="ftp://ftp.xfree86.org/pub/XFree86/3.3.2/patches/" + url="ftp://ftp.xfree86.org/pub/XFree86/3.3.2/patches/"> (or a similar + location on mirror sites). To upgrade the source to XFree86 3.3.2, + run the following from directory containing the <tt>xc</tt> + directory of the XFree86 3.3.1 source tree: + <quote><verb> + gzip -d < 3.3.1-3.3.2.diff1.gz | patch -p0 -E + rm -fr xc/fonts/bdf/cyrillic + gzip -d < cfont332.tgz | tar vxf - + </verb></quote> + Be sure to do this with a clean unmodified source tree. If you + don't some patches may fail. + </itemize> + If you only want to build the XFree86 X servers, you can use a cut-down version of the XFree86 source tree called the ``servers only'' distribution. If you choose this option, do the following: <itemize> ! <item>Get the <tt>X332servonly.tgz</tt> file from ! <htmlurl name="ftp://ftp.xfree86.org/pub/XFree86/3.3.2/source/" ! url="ftp://ftp.xfree86.org/pub/XFree86/3.3.2/source/"> (or a similar locations on mirror sites. <item>Extract this by running the following: <quote><verb> ! gzip -d < X332servonly.tgz | tar vxf - </verb></quote> </itemize> XFree86 supports a small subset of the X Consortium X11R6.1 contrib distribution. If you wish to build this, you will need at least the following files/directories from that distribution: *************** *** 122,137 **** contrib/programs/xman contrib/programs/xmessage </verb></tscreen> ! You will also need the XFree86 patch <tt>contrib-3.3.diff.gz</tt>. To apply the patch, run the following from the directory containing the <tt>contrib</tt> directory: <tscreen><verb> ! gzip -d < contrib-3.3.diff.gz | patch -p0 -E </verb></tscreen> ! Alternatively, you can just get the file <tt>X33contrib.tgz</tt> from the XFree86 source directory, and extract it by running: <tscreen><verb> ! gzip -d < X33contrib.tgz | tar vxf - </verb></tscreen> If you wish to build the xtest distribution, get the source distribution --- 140,155 ---- contrib/programs/xman contrib/programs/xmessage </verb></tscreen> ! You will also need the XFree86 patch <tt>contrib-3.3.2.diff.gz</tt>. To apply the patch, run the following from the directory containing the <tt>contrib</tt> directory: <tscreen><verb> ! gzip -d < contrib-3.3.2.diff.gz | patch -p0 -E </verb></tscreen> ! Alternatively, you can just get the file <tt>X332contrib.tgz</tt> from the XFree86 source directory, and extract it by running: <tscreen><verb> ! gzip -d < X332contrib.tgz | tar vxf - </verb></tscreen> If you wish to build the xtest distribution, get the source distribution *************** *** 155,161 **** the various <bf>OS*Version</bf> parameters, so you shouldn't need to enter those settings explicitly. ! If you are using just the <tt>X33src-1.tgz</tt> part of the source dist, you will need to define <bf>BuildFonts</bf> to <bf>NO</bf>. If you are using the ``servers only'' distribution, you will need to --- 173,179 ---- the various <bf>OS*Version</bf> parameters, so you shouldn't need to enter those settings explicitly. ! If you are using just the <tt>X332src-1.tgz</tt> part of the source dist, you will need to define <bf>BuildFonts</bf> to <bf>NO</bf>. If you are using the ``servers only'' distribution, you will need to *************** *** 227,236 **** name="README.LinkKit"> file. <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/BUILD.sgml,v 3.1.2.4 1997/06/02 03:12:42 dawes Exp $ ! ! ! $TOG: BUILD.sgml /main/1 1997/07/19 10:54:59 kaleb $ </verb> </article> --- 245,252 ---- name="README.LinkKit"> file. <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/BUILD.sgml,v 3.1.2.7 1998/02/28 13:00:00 dawes Exp $ ! $TOG: BUILD.sgml /main/2 1998/03/06 16:40:45 kaleb $ </verb> </article> *** ./xfree86/doc/sgml/OpenBSD.sgml@@/PUBLIC-LATEST Sun Aug 10 13:08:29 1997 --- xc/programs/Xserver/hw/xfree86/doc/sgml/OpenBSD.sgml Fri Mar 6 16:40:17 1998 *************** *** 1,10 **** <!DOCTYPE linuxdoc PUBLIC "-//XFree86//DTD linuxdoc//EN"> <article> ! <title>README for XFree86 3.3.1 on OpenBSD <author> Matthieu Herrb ! <Date>Last modified on: 26 July 1997 <toc> --- 1,10 ---- <!DOCTYPE linuxdoc PUBLIC "-//XFree86//DTD linuxdoc//EN"> <article> ! <title>README for XFree86 3.3.2 on OpenBSD <author> Matthieu Herrb ! <Date>Last modified on: 20 February 1998 <toc> *************** *** 12,18 **** <sect>What and Where is XFree86? <p> ! XFree86 3.3.1 is a port of X11R6.3 that supports several versions of Intel-based Unix. It is derived from X386 1.2, which was the X server distributed with X11R5. This release consists of many new features and performance improvements as well as many bug fixes. The release --- 12,18 ---- <sect>What and Where is XFree86? <p> ! XFree86 3.3.2 is a port of X11R6.3 that supports several versions of Intel-based Unix. It is derived from X386 1.2, which was the X server distributed with X11R5. This release consists of many new features and performance improvements as well as many bug fixes. The release *************** *** 26,32 **** <htmlurl name="ftp://ftp.XFree86.org/pub/XFree86/current" url="ftp://ftp.XFree86.org/pub/XFree86/current"> ! Binaries for OpenBSD 2.1 are available from: <htmlurl name="ftp://ftp.XFree86.org/pub/XFree86/current/binaries/" url="ftp://ftp.XFree86.org/pub/XFree86/current/binaries/OpenBSD"> --- 26,32 ---- <htmlurl name="ftp://ftp.XFree86.org/pub/XFree86/current" url="ftp://ftp.XFree86.org/pub/XFree86/current"> ! Binaries for OpenBSD 2.2 are available from: <htmlurl name="ftp://ftp.XFree86.org/pub/XFree86/current/binaries/" url="ftp://ftp.XFree86.org/pub/XFree86/current/binaries/OpenBSD"> *************** *** 37,43 **** <p> ! XFree86 3.3.1 also builds on other OpenBSD architectures. See section <ref id="otherarch" name="Building on other architectures"> for details. --- 37,43 ---- <p> ! XFree86 3.3.2 also builds on other OpenBSD architectures. See section <ref id="otherarch" name="Building on other architectures"> for details. *************** *** 49,101 **** this file and we'll revise it. <sect>New features in this release - <p> <enum> <item>See the <htmlurl url="RELNOTES.html" name="Release Notes"> for ! non-OS dependent new features in XFree86 3.3.1. </enum> <sect>Installing the Binaries <p> ! Refer to section 4 of the <htmlurl url="RELNOTES.html" name="Release Notes"> for detailed installation instructions. - - <sect1>Installing Xdm, the display manager - - <p> - The file <tt>xc/lib/Xdmcp/WrapHelp.c</tt> is not available in - France (where the binary distribution is built) so support for - XDM-AUTHORIZATION-1 is not included here. You'll have to get - WrapHelp.c and rebuild xdm after having set <tt/HasXdmAuth/ in - <tt/host.def/. - - The file is available within the US; for - details see <htmlurl name="ftp.x.org:/pub/R6/xdm-auth/README" - url="ftp://ftp.x.org/pub/R6/xdm-auth/README">. - - To start the display manager, log in as root on the console and type: - ``<tt/xdm -nodaemon/''. - - You can start xdm automatically on bootup by disabling the console getty - and adding the following code to <tt>/etc/rc.local</tt>: - - <tscreen><verb> - if [ -x /usr/X11R6/bin/xdm ]; then - echo -n ' xdm'; /usr/X11R6/bin/xdm - fi - </verb></tscreen> - - To disable the console getty, change ``<bf/on/'' to ``<bf/off/'' in - the console entry in <tt>/etc/ttys</tt>: - - <tscreen><verb> - ttyC0 "/usr/libexec/getty Pc" pc off secure - </verb></tscreen> - - <sect>Configuring X for Your Hardware <p> --- 49,66 ---- this file and we'll revise it. <sect>New features in this release <p> <enum> <item>See the <htmlurl url="RELNOTES.html" name="Release Notes"> for ! non-OS dependent new features in XFree86 3.3.2. </enum> <sect>Installing the Binaries <p> ! Refer to section 5 of the <htmlurl url="RELNOTES.html" name="Release Notes"> for detailed installation instructions. <sect>Configuring X for Your Hardware <p> *************** *** 146,151 **** --- 111,123 ---- in that mode. "cooked" mode is the old BusMouse translation. By default, the driver runs in "cooked" mode. It can be switched using ioctls or by opening the first minor device which is <tt>/dev/psm0</tt>. + <p> + Only standard PS/2 mice are supported by this driver. Newest PS/2 + mice that send more than three bytes at a time (especially + intellimouse, or mouseman+ with a "3D" roller) are not supported yet. + <p> + See <htmlurl url="mouse.html" name="README.mouse"> for general + instruction on mouse configuration in XFree86. <sect1>Other input devices <p> *************** *** 185,191 **** --- 157,205 ---- load "xie.so" </verb></tscreen> + <sect>Installing Xdm, the display manager + <p> + The file <tt>xc/lib/Xdmcp/WrapHelp.c</tt> is not available in + France (where the binary distribution is built) so support for + XDM-AUTHORIZATION-1 is not included here. You'll have to get + WrapHelp.c and rebuild xdm after having set <tt/HasXdmAuth/ in + <tt/host.def/. + + The file is available within the US; for + details see <htmlurl name="ftp.x.org:/pub/R6/xdm-auth/README" + url="ftp://ftp.x.org/pub/R6/xdm-auth/README">. + + To start the display manager, log in as root on the console and type: + ``<tt/xdm -nodaemon/''. + + You can start xdm automatically on bootup un-commenting the following + code in <tt>/etc/rc.local</tt>: + + <tscreen><verb> + if [ -x /usr/X11R6/bin/xdm ]; then + echo -n ' xdm'; /usr/X11R6/bin/xdm + fi + </verb></tscreen> + + On the default OpenBSD 2.2 installation, you will also need to create + the virtual console device for the X server: + <tscreen><verb> + cd /dev + ./MAKEDEV ttyC5 + </verb></tscreen> + + It's also better to specify explicitly the virtual console to be used + by the X server. If you're experimenting keyboards lockup with xdm, in + <tt>/usr/X11R6/lib/X11/xdm/Xservers</tt>, replace the line: + <tscreen><verb> + :0 local /usr/X11R6/bin/X + </verb></tscreen> + by: + <tscreen><verb> + :0 local /usr/X11R6/bin/X vt06 + </verb></tscreen> + <sect>Running X <p> *************** *** 212,218 **** line must be in your config file in <tt>/sys/arch/i386/conf</tt>: <tscreen> ! options XSERVER, UCONSOLE </tscreen> The server supports the two standard OpenBSD/i386 --- 226,232 ---- line must be in your config file in <tt>/sys/arch/i386/conf</tt>: <tscreen> ! options XSERVER </tscreen> The server supports the two standard OpenBSD/i386 *************** *** 258,264 **** --- 272,281 ---- `option INSECURE' in the kernel configuration file and build a new kernel. + In OpenBSD 2.2 and later, you will also need to comment out the line + initializing <tt/securelevel/ to 1 in <tt>/etc/rc.securelevel</tt>. + <item>Install the aperture driver: <enum> <item> The first step is highly dependent from your exact operating *************** *** 276,285 **** fi </verb></tscreen> ! <item> OpenBSD 2.1 <p> Uncomment the lines loading the aperture driver from <tt>/etc/rc.securelevel</tt> </itemize> <item> Reboot your system. XFree86 will auto-detect the aperture --- 293,311 ---- fi </verb></tscreen> ! <item> OpenBSD 2.1, 2.2 <p> Uncomment the lines loading the aperture driver from <tt>/etc/rc.securelevel</tt> + + <item> OpenBSD-current + <p> + In addition to the loadable kernel module, you can now use an + in-kernel aperture driver. Add 'option APERTURE' to your kernel + configuration file, build and install the new kernel and run + <tt>./MAKEDEV std</tt> in <tt>/dev</tt>. Edit + <tt>/etc/sysctl.conf</tt> to set the variable + <bf>machdep.allowaperture</bf> to 1. </itemize> <item> Reboot your system. XFree86 will auto-detect the aperture *************** *** 356,362 **** <sect1>Console drivers<label id="console-drivers"> <p> ! XFree86 3.3.1 has a configuration option to select the console drivers to use in <tt/xf86site.def/: <itemize> <item> if you're using pccons put: --- 382,388 ---- <sect1>Console drivers<label id="console-drivers"> <p> ! XFree86 3.3.2 has a configuration option to select the console drivers to use in <tt/xf86site.def/: <itemize> <item> if you're using pccons put: *************** *** 402,408 **** <sect1>Building on other architectures<label id="otherarch"> <p> ! XFree86 3.3.1 also compiles on other OpenBSD architectures. The XFree86 servers can also been built on OpenBSD/mips. The S3 server has been tested on an Acer Mips system with a S3/928 board. Contact --- 428,434 ---- <sect1>Building on other architectures<label id="otherarch"> <p> ! XFree86 3.3.2 also compiles on other OpenBSD architectures. The XFree86 servers can also been built on OpenBSD/mips. The S3 server has been tested on an Acer Mips system with a S3/928 board. Contact *************** *** 449,461 **** </itemize> <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/OpenBSD.sgml,v 1.1.2.2 1997/08/02 13:48:14 dawes Exp $ ! $TOG: OpenBSD.sgml /main/1 1997/08/10 13:07:05 kaleb $ </verb> </article> --- 475,487 ---- </itemize> <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/OpenBSD.sgml,v 1.1.2.5 1998/02/26 13:59:07 dawes Exp $ ! $TOG: OpenBSD.sgml /main/2 1998/03/06 16:41:54 kaleb $ </verb> </article> *** ./xfree86/doc/sgml/RELNOTE.sgml@@/PUBLIC-LATEST Sun Aug 10 13:03:40 1997 --- xc/programs/Xserver/hw/xfree86/doc/sgml/RELNOTE.sgml Fri Mar 6 16:40:33 1998 *************** *** 2,17 **** <article> ! <title>Release Notes for XFree86&tm; 3.3.1 <author>The XFree86 Project, Inc ! <date>4 August 1997 <abstract> ! This document describes the bugs fixed in XFree86 3.3.1 compared with the ! 3.3 release, as well as the new features in XFree86 3.3 compared with the ! previous full release, 3.2. It also includes installation instructions ! for the binary distributions. </abstract> --- 2,16 ---- <article> ! <title>Release Notes for XFree86&tm; 3.3.2 <author>The XFree86 Project, Inc ! <date>28 February 1998 <abstract> ! This document describes the bugs fixed and the features added in XFree86 3.3.2 ! compared with the 3.3.1 release, ! It also includes installation instructions for the binary distributions. </abstract> *************** *** 44,144 **** <p> Always check the OS specific README files for special requirements or caveats. <p> ! Users running Linux/Elf (on Intel platforms) should note that they will ! need ld.so version 1.7.14 or later. This ! can be found at <htmlurl name="ftp://tsx-11.mit.edu/pub/linux/packages/GCC" ! url="ftp://tsx-11.mit.edu/pub/linux/packages/GCC">. ! <p> ! Note: Elf is now the only binary type supported for Linux OSs. This means that binaries for ix86/a.out and AXP/ECOFF are not available with this release. ! <sect> What's new in 3.3.1? <p> <sect1> Bug fixes <p> <itemize> ! <item>XFree86 3.3.1 includes The Open Group's public patch 2 for X11R6.3. ! <item>Build problems that showed up on some OSs have been fixed. ! <item>Support for SCO Open Server 5 should now be complete. ! <item>A malloc problem in libXt which showed up on FreeBSD has been fixed. ! <item>Depth-specific DacSpeeds are now implemented for the ET6000. ! <item>Depth-specific DacSpeeds are fixed for the S3 server. ! <item>HW cursor problem with the I128 server has been fixed. ! <item>I128 Series II rev 2 chips are now supported. ! <item>Xterm will now startup on Linux if /etc/termcap is missing. ! <item>Various problems with the S3V server and the SVGA s3v driver have been ! fixed. ! <item>A problem with the clock limit for some revisions of the Circus 5434 ! has been fixed. ! <item>The Mach64 server will now correctly recognise some of the newer ! ATI chip revisions, including the Rage II+, Rage Pro and VT3. If ! you needed the ChipId/ChipRev workaround when using 3.3, you should ! remove those lines from your XF86Config file when upgrading to 3.3.1. ! <item>An initialisation problem in the S3 server that shows up when the ! ramdac type is given in the XF86Config file should be fixed. ! <item>The MGA driver now defaults to using the software cursor because ! some people have reported problems when using the hardware cursor ! with Millennium cards. ! <item>Lockups with the MGA driver that happen on some SVR4 versions have ! been fixed. Lockups when the server crashes and dumps core on some ! OSs have also been fixed where possible. ! <item>The xterm termcap field for turning off colour has been fixed. ! <item>A server crash that happens when starting some servers on Solaris ! has been fixed. ! <item>Some problems with the Trident 9860 and 9685 chips have been fixed. ! <item>A problem with xterm writing an invalid wtmp entry on Linux has been ! fixed. ! <item>A PolyPoint bug in the S3V server has been fixed. ! <item>Screen wraparound problems with the S3 server that show up on some ! old Number Nine GXE level 10 cards have been fixed. ! <item>A problem with the PCI framebuffer remapping in the S3 server has been ! fixed. ! <item>A problem with XF86Setup not showing the correct chipset-specific ! README file has been fixed. ! <item>A problem with XF86Setup not setting up the link to the Xserver in ! some situations has been fixed. ! <item>Some libXt error/warning messages were partially duplicated, and this ! is now fixed. ! <item>Some line drawing problems that show up with the Cirrus 542x chips ! have been fixed. ! <item>A problem drawing wide fonts with some Cirrus chips has been fixed. ! <item>Some bugs in some XKB symbols files have been fixed. ! <item>The Chips and Technologies 65555 and 68554 are now detected by ! the chips driver. ! <item>`xset dpms' didn't accept some parameters correctly. ! <item>Some raster op bugs in the SVGA server's s3v driver have been fixed. ! <item>Problems with the Mach32 server that show up with some AST motherboards ! that have an on-board Mach32 chip have been fixed (see the ! <htmlurl url="Mach32.html" name="README.Mach32"> file for details). ! <item>A bug in the ET6000 driver which can cause the server to crash on ! non-Linux systems has been fixed. ! <item>An initialisation problem with the ET6000 driver which can result in ! a black screen has been fixed. ! <item>The Eraser support in the Wacom driver has been fixed. ! <item>Support for two relative devices has been fixed in the Wacom driver. ! <item>The DPMS state is now correctly reset when switching back to the ! Xserver's VT. ! <item>A bug in the 24bpp framebuffer code which caused a server crash ! when running StarOffice has been fixed. ! <item>An Xserver bug which could cause a server crash when using lbxproxy ! has been fixed. ! <item>A conflict between Imake.rules and Motif.rules has been fixed. ! <item>Some problems that show up with some accelerated servers on SVR4 ! when using Xqueue have been fixed. ! <item>A problem that can cause a server crash when drawing some arcs has ! been fixed. ! <item>The MGA driver now recognises the newer 220MHz Mystique chips. ! <item>The MGA driver has experimental support for the Millennium II. ! This really is very new, and is largely untested. There are known ! problems (see <htmlurl name="README.MGA" url="MGA.html"> for details). ! <item>The "noaccel" option could cause a lockup with the Cirrus Laguna ! chips (546x). This option is now disabled for those chips. ! <item>Some blitter timeouts that show up with Cirrus 7548 and 7555 chips ! should now be fixed. ! <item>The handling of the PS/2 mouse protocol is fixed for OpenBSD. ! <item>The SiS driver should now correctly determine the MMIO address. </itemize> <sect1>Known Problems <p> <itemize> --- 43,155 ---- <p> Always check the OS specific README files for special requirements or caveats. <p> ! Users running Linux should note that Elf is now the only binary type ! supported for Linux OSs. This means that binaries for ix86/a.out and AXP/ECOFF are not available with this release. ! <sect> What's new in 3.3.2? <p> + <sect1> Security fixes + <p> + <itemize> + <item>Several buffer overrun problem discovered since the release of + XFree86-3.3.1 have been fixed + <item>Several insecure X server command line options have been removed + <item>The X servers now run the <tt>xkbcomp</tt> program under the + user's real uid + <item>Additionally, a wrapper program for the X servers has been added + which eliminated the need for the servers to be installed SUID root + </itemize> <sect1> Bug fixes <p> <itemize> ! <item>A black screen problem in the Tseng driver has been fixed. ! <item>Several drawing problems in the Tseng driver have been corrected. ! <item>Timeouts to all routines waiting for the accelerator have been added. ! <item>DPMS has been fixed in the Tseng driver. ! <item>The memory clock for the Matrox Millennium II is now set correctly. ! <item>Several drawing bugs in the MGA driver have been fixed. ! <item>The problem with some Millennium II cards in higher resolutions and ! 24bpp is fixed. ! <item>Some problems with 24 and 32bpp in the Trident driver have been fixed. ! <item>Some problems in the C&T driver with the TMED DSTN dithering scheme ! for the 65555 and 68554 have been fixed. ! <item>The C&T driver now adheres much more strictly to the clock limits. ! <item>Allow DacSpeed command to work correctly in more servers. ! <item>Several small bugs for Cirrus Laguna chipsets have been fixed. ! <item>Fixes to the Wacom driver. ! <item>The Cyrillic fonts have been updated. ! <item>BSDI is supported again. ! <item>Several XAA problems have been fixed. ! <item>XKB for PC98 has been updated. ! <item>S3 Aurora64V+ now works with 16bpp. ! <item>cursor offset for some S3 cards has been fixed. ! <item>S3 server support for STG 1700 ramdac has been fixed. ! <item>imake correctly works on Linux glibc-2 systems now. </itemize> + <sect1> New Features + <p> + <itemize> + <item>Support for ET6100 has been added to the Tseng driver. + <item>Acceleration has been added for W32 and W32i. + <item>Text performance has been improved for the Tseng driver. + <item>Support for new RAMDACs, including the ch8398, the + ch8391 and the MUSIC MU9C4910 has been added to the Tseng driver. + <item>Accelerated support for the AT3D and AT25 has been added to the APM + driver. + <item>Support for accelerated NV1 and accelerated Riva128 has been added to + the NV driver. + <item>Support for the Matrox Millennium II AGP has been included into the + MGA driver. + <item>New support for several Trident chips has been added, including + Cyber9397, 3DImage975 and 3DImage985 (unaccelerated and not completed, yet), + TGUI9685. + <item>CrealTV support has been added for the TGUI9685. + <item>Acceleration of all TGUI chipsets has been improved. + <item>Support for Rage Pro based PCI and AGP cards has been added. + <item>Maximum dotclock for newer Mach64 cards has been increased. + <item>Support for 1600x1200 and 1600x1280 mode has been added for VT and + newer Mach64 chips. + <item>Support for the auxiliary register aperture for newer Mach64 cards + has been added. + <item>Support for the I128 Revolution (T2R) has been added. + <item>Additional acceleration for the I128 server has been added. + <item>Support for sw cursor, pci_retry, 24bpp HW cursor has been added to + cirrus Laguna chipsets. + <item>S3 ViRGE/MX and ViRGE/GX2 support has been added (SVGA server only!). + <item>support for S3 ViRGE hardware cursor added in SVGA server. + <item>An S3 driver has been added to the SVGA server. + <item>S3 server and SVGA/S3 server now recognize some fake S3 chips and + print out a warning message. + <item>XAA has been extended to support hardware cursors and provide + accelerated support dashed lines and trapezoid fills. + <item>Several new mouse protocols have been added to all servers. They + should now support Kensington ThinkingMouse, ALPS GlidePoint, + Genius NetScroll, Genius NetMouse, Genius NetMouse, ASCII MieMouse, + Logitech MouseMan+, Logitech FirstMouse+. This includes all buttons on + these mice as well as the wheels. The wheel can be used to either create + additional buttons or for z-axis indication. + <item>login.conf/setusercontext support to xdm for FreeBSD has been added. + <item>XF86Setup now supports setting the default color depth and choosing + the modes the user wants to use. + <item>XF86Setup allows to select all the new mouse protocols (depending + on the OS it is running on). + <item>Japanization of XF86Setup has been added. + <item>XF98_MGA server for Millennium and Mystique has been added. + This server is very new and has some problems with Mystique support. + <item>XF98_SVGA server for CLGD755x has been added. This server also is + very new and has some problems. + <item>Linux/98 support has been added. Linux/98 is very new and perhaps + the servers also have some problems. + <item>XF98_TGUI server now works on PANIX98. + <item>XF98Setup(i.e. XF86Setup for PC98) has been added. + <item>Many changes to xterm including support for double-size + characters (positioning), blinking characters (render in color), + improvements to logging, transparent printing, delete/backspace + toggle, and better support for Sun and PC keyboards. + + </itemize> <sect1>Known Problems <p> <itemize> *************** *** 154,599 **** this, these problems are unlikely to be fixed. If you wish to work on this, please contact us. We don't need testers, we need people willing and able to fix the problems. - <item>We have had some reports of apparently random lockups with some - Mystique cards. We have not been able to reproduce this problem, - and have no fix for it. - <item>There is a drawing bug in the MGA driver that shows up when running - `viewfax'. We have no fix for this problem yet. - <item>Some people have reported problems with some newer Rage II cards. - We have no fix for this problem yet. - <item>We've had a report that the SVGA server will cause a lockup on - some SVR4 versions (UnixWare 1.x) with some Chips and Technologies - chips. A workaround for this problem is to use the "xaa_no_color_exp" - option. </itemize> ! <sect> New Features in 3.3 <p> ! <sect1> General ! <p> ! <itemize> ! <item>XFree86 3.3 includes the X Consortium's X11R6.3. ! </itemize> ! <sect1> General X server changes ! <p> ! <itemize> ! <item>The X servers include a new DPMS extension, which was donated by ! Digital Equipment Corporation. Not all DPMS modes have been ! implemented by all servers yet, but this should improve in future ! releases. See the XF86Config(4/5) and xset(1) man pages ! for further details. ! <item>The LBX extension is included in all the X servers, as part of the ! update to R6.3. ! <item>A print-only server (Xprt) is included as part of the update to R6.3. ! <item>Some bugs in the Type1 font code have been fixed. ! <item>Some bugs in newer functions in the XFree86 VidMode extension ! have been fixed. ! <item>Support has been added for the Microsoft IntelliMouse. ! </itemize> ! <sect1> XF86Setup ! <p> ! <itemize> ! <item>Some bugs have been fixed, but no major changes have been made ! to this version. ! <item>More modelines were added. There are now high-refresh versions of ! most common modes available (85 and 100 Hz). 512x384, 1152x864, ! 1600x1200 and 1800x1440 modes were added. ! </itemize> ! <sect1> PC98 Support ! <p> ! <itemize> ! <item>The XF98_TGUI server includes XAA support, but there are some problems ! with this at the moment. It can be disabled with the "noaccel" ! option. ! </itemize> ! <sect1> Alpha (AXP) platform support ! <p> ! <itemize> ! <item>Support for the S3 ViRGE and ViRGE/VX is now available. ! <item>Support for "newmmio" is now available for the S3 868/968/Trio64V+ ! and is enabled by default (use chipset "mmio_928" to get the old ! behaviour). ! <item>Support for the Matrox Millennium and Mystique (in the SVGA server) ! is included. ! <item>Support for the Trident driver (in the SVGA server) is included. ! <item>Some problems that showed up with Netscape on some servers have ! been fixed. ! <item>Various alignment problems have been fixed. ! <item>NOTE: A recent Linux kernel version is required for most of these ! servers (essential for the Matrox driver). ! <item>Scanpci now works on Alpha platforms. ! </itemize> ! <sect1> XInput Extension ! <p> ! <itemize> ! <item>Multiple input devices can share the core pointer. ! </itemize> ! <sect2> Wacom driver ! <p> ! <itemize> ! <item>Multiple devices can be defined for the same tablet to represent ! different active zones. ! </itemize> ! <sect1> XKEYBOARD Extension ! <p> ! <itemize> ! <item>An improved layout for Russian keyboards is provided. ! <item>A layout for Hungarian keyboards is provided. ! </itemize> ! <sect1> SVGA server ! <p> ! <itemize> ! <item>A new general graphics acceleration interface (XFree86 Acceleration ! Architecture - XAA) has been implemented. It is used to provide ! relatively complete acceleration, at different colour depths, ! for several chips in the SVGA server. Chips currently making use ! of this include the Matrox Millennium, Mystique, Tseng ET4000/W32p ! and ET6000, ! and several chips from ARK Logic, Chips and Technologies, Cirrus, ! Trident, SiS and the S3 ViRGE family. ! <item>The SVGA server now includes a driver for the S3 ViRGE family. It ! supports the ViRGE, ViRGE/DX, ViRGE/GX and ViRGE/VX. This driver is ! a completely new implementation, so please send in success/failure ! reports. ! </itemize> ! <sect1> S3 server ! <p> ! <itemize> ! <item>Some further S3 968 hardware bugs for lines/text have been worked ! around. ! <item>Cursor/pointer pixmaps larger than 64x64 are now supported without ! the need to use the "sw_cursor" option. ! <item>Detection/support for the Trio64UV+, Trio64V2 (including the /DX and ! /GX versions), Aurora64V+ (86CM65 used in notebooks), and Plato/PX ! is now included. This support is ! very new and hasn't had much testing, so please send us ! success/failure reports. ! <item>Support is now included for the ELSA Winner 2000PRO/X-8. Please ! refer to the notes for this card in <htmlurl url="S3.html" ! name="README.S3">. ! <item>Support is now included for the MIRO 80SV. ! <item>A bug which prevented DGA apps from setting the ViewPort to the lower ! part of the framebuffer has been fixed (this showed up most commonly ! with 4MB cards). ! </itemize> ! <sect1> S3V (ViRGE) server ! <p> ! <itemize> ! <item>Support has been added for the ViRGE/DX and ViRGE/GX. ! <item>Problems with the Diamond Stealth 3D 3000 are now fixed. ! <item>The line drawing code has been improved. ! <item>Packed 24bpp support is included, and should be improved ! over earlier versions. ! <item>The S3V server translates between sparse 32bpp pixmaps and packed ! 24bpp for the framebuffer. In some cases this can be slow. ! <item>32bpp framebuffer format is not supported. ! </itemize> ! <sect1> Mach64 server ! <p> ! <itemize> ! <item>Support for 3D Rage II based Mach64 cards is included. ! <item>Various problems with support for some revisions of CT, VT and GT ! chipsets have been fixed. ! <item>It is strongly recommended that all users with CT, VT, GT and ! 3D Rage II based Mach64 cards upgrade to the 3.3 release due ! to the problems that were fixed. ! </itemize> ! <sect1> Mach32 server ! <p> ! <itemize> ! <item>A bug that causes problems when running XF86Setup with cards with ! less than 2MB of video memory has been fixed. ! <item>Minor shifts in maximum clock rate under 16 bpp, and inclusion of ! explicit 15 "bpp" setting. ! </itemize> ! <sect1> W32 server ! <p> ! <itemize> ! <item>In this version, the separate W32 server (XF86_W32) has not ! undergone any significant changes. In fact, it is not being ! developed further. Instead, the SVGA server (XF86_SVGA) is now the ! main focus of new developments. See the W32 (SVGA) description. ! </itemize> ! <!-- ! <sect1> AGX server ! <p> ! <itemize> ! <item>stuff... ! </itemize> ! --> ! <sect1> P9000 server ! <p> ! <itemize> ! <item>Support for PCI probing has been added. ! <item>DPMS support has been added. ! </itemize> ! <sect1> I128 server ! <p> ! <itemize> ! <item>Some preliminary acceleration (for bitblts) is included. ! This code is very new, and hasn't been extensively tested yet. ! </itemize> ! <sect1> TGA server ! <p> ! <itemize> ! <item>Preliminary acceleration support is included, using XAA. ! <item>Various bugs have been fixed. ! </itemize> ! <sect1> Trident driver (SVGA server) ! <p> ! <itemize> ! <item>Acceleration support has been added for the 9320, 9440 and 96xx chips. ! <item>Support for the Cyber series of laptop chips has been improved. ! <item>24/32bpp support has been added for some chips. ! <item>Some clock limits have been fixed. ! </itemize> ! <sect1> Ark driver (SVGA server) ! <p> ! <itemize> ! <item>More complete acceleration has been implemented using XAA, ! including line draw, fill, and text acceleration, at different ! colour depths. ! </itemize> ! <sect1> W32 driver (SVGA server) ! <p> ! <itemize> ! <item>The SVGA server now supports acceleration for the most recent ! ET4000W32 chips. In 3.3, the ET4000W32p chips are now fully ! accelerated, and also support the higher performing linear memory ! layout (read the tseng README file for more information: there are a ! few problems). ! <item>VESA DPMS (monitor power saving) support was added. ! <item>There is now support for more than 256 colors on most ET4000W32i and ! ET4000W32p chips. This means 15, 16, 24 and/or 32 bits per pixel ! modes (32768, 65536 or 16 million colors) are supported on most ! common RAMDACs. On the W32p, these modes are accelerated. On the ! W32i, there is no acceleration in any mode. For accelerated support ! on W32i chips, refer to the separate W32 server (XF86_W32). ! <item>A few bugs in XFree86 3.2 and 3.2A have been fixed. Most importantly ! the failure to probe some PCI cards has been resolved. ! <item>Fix interference with ISA-DMA sensitive devices (soundcards, ! floppy-tape drives) ! <item>Support for the Chrontel RAMDAC has been added. ! </itemize> ! <sect1> ET6000 driver (SVGA server) ! <p> ! <itemize> ! <item>The ET6000 driver in the separate W32 server (XF86_W32) has not ! changed significantly. ! <item>On the other hand, the ET6000 driver in the SVGA server, which ! already existed in XFree86 3.2 for all color depths, is now fully ! accelerated for all those color depths. It builds upon the new XAA ! architecture, which is the cornerstone of a new acceleration ! framework within the XFree86 servers. It is responsible for the ! outstanding acceleration performance of this release. ! <item>Many small problems which existed in the initial 3.2 release have ! been solved. Screen noise, flicker or instability at higher pixel ! clocks are mostly fixed. Some detection problems are gone. Weird ! behaviour (jumping and screen wrap) when panning through large ! virtual desktops has been fixed. The server now detects the correct ! amount of memory on ET6000 cards with 2.25 MB of MDRAM. More ! realistic pixel clock rate limits have been put in place, to avoid ! modes that would cause screen problems. ! <item>DPMS support was added. ! <item>The ET6000 hardware cursor is now supported. Read the Tseng ! documentation file for more information (there are a few ! limitations) ! <item>fix interference with ISA-DMA sensitive devices (soundcards, ! floppy-tape drives) ! </itemize> ! <sect1> Alliance ProMotion driver (SVGA server) ! <p> ! <itemize> ! <item>The driver now recognises the AT24 chipset, but it is treated ! the same way as the AP6422. ! </itemize> ! <!-- ! <sect1> NVidia NV1 / SGS Thomson STG2000 driver (SVGA server) ! <p> ! <itemize> ! <item>stuff... ! </itemize> ! --> ! <sect1> Matrox driver (SVGA server) ! <p> ! <itemize> ! <item>More complete acceleration for the Millennium (MGA2064W). ! <item>Support is included for the Mystique (including some acceleration). ! This code is very new. ! <item>24 bpp mode tiled pattern problems still present. ! <item>Support for DGA, Sync-on-Green, and DPMS. ! <item>The "nolinear" option is no longer available. ! <item>Support for 8 bits per colour component (at 8bpp) has been added. ! </itemize> ! <sect1> Cirrus driver (SVGA server) ! <p> ! <itemize> ! <item>More complete acceleration for all chips with a BitBLT engine ! (CL-GD5426, 5428, 5429, 5430, 5434, 5436, 5440, 5446, 7541, ! 7543, and 7548). ! <item>More complete acceleration for Laguna series chips (CL-GD546X). ! <item>The support for the 754x series of laptop controllers has been ! improved. ! <item>The 24bpp mode on the CL-GD5430/40 has been fixed. ! <item>Support for the CL-GD5480 has been added. ! </itemize> ! <sect1> SiS driver (SVGA server) ! <p> ! <itemize> ! <item>Significant updates have been made to the SiS driver (see ! <htmlurl url="SiS.html" name="README.SiS"> for further details). ! <item>Acceleration support is included, making use of XAA. ! <item>Linear addressing is supported. ! <item>Support has been added for 15/16/24bpp. ! <item>Support has been added for programmable clocks. ! <item>HW cursor support is included. ! </itemize> ! <sect1> Chips and Technologies driver (SVGA server) ! <p> ! <itemize> ! <item>Support has been included for the 65525, 65535, 64200 and 64300 ! <item>Problems relating to blank screen at start-up and text mode ! restoration with the 65550 and 65554 should now be fixed ! <item>Acceleration support for all chips has improved due to the new ! XAA architecture. ! <item>Many additional minor fixes and documentation updates (see ! <htmlurl url="chips.html" name="README.chips"> for further details). ! </itemize> ! <sect1> S3 ViRGE driver (SVGA server) ! <p> ! <itemize> ! <item>Completely new driver for the ViRGE family. The driver works with ! linear addressing and PCI chipsets. ! <item>Acceleration support uses the XAA architecture. ! <item>The driver supports 8/15/16/24/32 bpp on all cards. ! <item>Acceleration includes bitblits, filled rectangles, color expansion ! and pattern fills (8/15/16/24 bpp). Acceleration at 32 bpp is limited ! to bitblits and filled rectangles. ! <item>Includes HW cursor support. ! <item>See <htmlurl url="S3V.html" name="README.S3V"> for further details. ! </itemize> ! <!-- ! <sect1> ALI driver (SVGA server) ! <p> ! <itemize> ! <item>stuff... ! </itemize> ! --> ! <!-- ! <sect1> ATI driver (SVGA server) ! <p> ! <itemize> ! <item>stuff... ! </itemize> ! --> ! <sect1> WD90C24 driver (SVGA server) ! <p> ! <itemize> ! <item>DPMS support is included (only for "off" mode so far). ! </itemize> ! <sect1> Compaq AVGA driver (SVGA server) ! <p> ! <itemize> ! <item>The Compaq AVGA driver has been resurrected. The bugs causing it ! to not work in some previous releases have been fixed. ! </itemize> ! <sect1> Hercules mono driver ! <p> ! <itemize> ! <item>The problems with the Hercules mono driver in previous releases ! has now been fixed, and the driver is included in this release. ! </itemize> ! <sect1> Client/Library changes ! <p> ! <itemize> ! <item>The libraries have been updated to R6.3. The shared lib version ! numbers for libXext and libICE have been bumped to 6.3. The ! others remain the same. ! <item>An Xlib problem with non-latin-1 encodings that shows up when using ! XKB is fixed. ! <item>Some Xlib security vulnerabilities have been fixed. ! <item>Xterm's emulation of DECUDK (DEC user-defined keys) now (correctly) ! interprets shifted keys only. ! <item>VT52 emulation has been added to xterm. ! <item>Xterm's VT100 emulation generates correct codes for PF1-PF4, as well ! as the keypad "+" and ",". These codes differ from the VT220 ! emulation. ! <item>Some xterm bugs have been fixed, including coloured background ! exposure while selection is active, and missing state changes ! in the VT100 emulation. ! <item>Xterm's memory requirements for colour have been reduced. The colour ! resource file is merged with the regular resource file to reduce ! installation problems. ! <item>Emulation of VT220 soft-reset, and non-DEC REP (repeat) control ! sequence has been added to xterm. ! <item>Xterm now recognizes control sequences for 16 colors (from aixterm). ! <item>xset includes support for the DPMS extension. ! <item>xset's "r rate" flag was broken on some OSs, and is now fixed. ! </itemize> ! <p> ! <sect1> xf86config utility ! <p> ! <itemize> ! <item>More modelines were added. There are now high-refresh versions of ! most common modes available (85 and 100 Hz). 512x384, 1152x864, ! 1600x1200 and 1800x1440 modes were added. ! </itemize> ! <sect1> SuperProbe ! <p> ! <itemize> ! <item>Add detection of Alliance Pro Motion chips. ! <item>Add detection of I128-2. ! <item>Add detection of S3 Trio64UV+ and Aurora64V+, Trio64V2/DX and /GX, ! S3 ViRGE/DX and /GX and Plato/PX. ! <item>Add detection of Matrox chips. ! <item>Add detection of newer Trident chips, including the Cyber series. ! <item>Fix detection of ET4000W32 chips, and their memory probing. ! <item>Add detection of newer ATI chips. ! <item>Add detection of STG170x and CH8398 RAMDACs ! <item>Add detection of Sigma Designs REALMagic ! <item>Add detection of 3DLabs GLINT ! </itemize> ! <sect1> Fonts ! <p> ! <itemize> ! <item>Gzipped fonts are now supported. ! </itemize> ! <sect>Installing the XFree86 3.3.1 Release ! <p> ! The XFree86 3.3.1 binaries are distributed as both a full release ! and as an upgrade to XFree86 3.3. ! What follows is a list of the XFree86 3.3.1 components. There may be some variations in this for some OSs. The following are required for all new installations or upgrades from ! versions prior to 3.3: <quote> <verb> preinst.sh Pre-installation script postinst.sh Post-installation script ! extract.tgz XFree86 extraction utility ! X331bin.tgz Clients, run-time libs, and app-defaults files ! X331doc.tgz Documentation ! X331fnts.tgz 75dpi, misc and PEX fonts ! X331lib.tgz Data files required at run-time ! X331man.tgz Manual pages ! X331set.tgz XF86Setup utility ! X331VG16.tgz 16 colour VGA server (XF86Setup needs this server) </verb> </quote> ! The following are required for an upgrade from XFree86 3.3: <quote> <verb> preinst.sh Pre-installation script postinst.sh Post-installation script ! extract.tgz XFree86 extraction utility ! X331upd.tgz Changes since 3.3 (except the servers) ! X331doc.tgz Documentation ! X331set.tgz XF86Setup utility ! X331VG16.tgz 16 colour VGA server (XF86Setup needs this server) </verb> </quote> --- 165,213 ---- this, these problems are unlikely to be fixed. If you wish to work on this, please contact us. We don't need testers, we need people willing and able to fix the problems. </itemize> ! <sect>Installing the XFree86 3.3.2 Release <p> ! The XFree86 3.3.2 binaries are distributed as both a full release ! and as an upgrade to XFree86 3.3.1. ! NOTE: the X servers are no longer installed setuid root. If you are ! starting your X servers with startx/xinit, or something similar, you ! will need a copy of the setuid Xwrapper, and an updated xinit. These ! can be found in X332upd.tgz for those upgrading from 3.3.1, and in ! X332bin.tgz for those doing a full install. ! What follows is a list of the XFree86 3.3.2 components. There may be some variations in this for some OSs. The following are required for all new installations or upgrades from ! versions prior to 3.3.1: <quote> <verb> preinst.sh Pre-installation script postinst.sh Post-installation script ! extract XFree86 extraction utility ! X332bin.tgz Clients, run-time libs, and app-defaults files ! X332doc.tgz Documentation ! X332fnts.tgz 75dpi, misc and PEX fonts ! X332lib.tgz Data files required at run-time ! X332man.tgz Manual pages ! X332set.tgz XF86Setup utility ! X332VG16.tgz 16 colour VGA server (XF86Setup needs this server) </verb> </quote> ! The following are required for an upgrade from XFree86 3.3.1: <quote> <verb> preinst.sh Pre-installation script postinst.sh Post-installation script ! extract XFree86 extraction utility ! X332upd.tgz Changes since 3.3.1 (except the servers) ! X332doc.tgz Documentation ! X332set.tgz XF86Setup utility ! X332VG16.tgz 16 colour VGA server (XF86Setup needs this server) </verb> </quote> *************** *** 601,614 **** installations: <quote> <verb> ! X331cfg.tgz sample config files for xinit, xdm </verb> </quote> ! NOTE: Be very careful about installing X331cfg.tgz over an existing installation if you have customised your xinit and/or xdm config files. ! Installing X331cfg.tgz will overwrite any existing files. If you do have ! customised files, there is no need to install X331cfg.tgz. NOTE: The bitmap fonts distributed with this release are compressed using gzip rather than compress. This means that you will probably want to --- 215,228 ---- installations: <quote> <verb> ! X332cfg.tgz sample config files for xinit, xdm </verb> </quote> ! NOTE: Be very careful about installing X332cfg.tgz over an existing installation if you have customised your xinit and/or xdm config files. ! Installing X332cfg.tgz will overwrite any existing files. If you do have ! customised files, there is no need to install X332cfg.tgz. NOTE: The bitmap fonts distributed with this release are compressed using gzip rather than compress. This means that you will probably want to *************** *** 622,652 **** required by the new configuration utility (XF86Setup). <quote> <verb> ! X3318514.tgz 8514/A server ! X331AGX.tgz AGX server ! X331I128.tgz I128 server ! X331Ma32.tgz Mach 32 server ! X331Ma64.tgz Mach 64 server ! X331Ma8.tgz Mach 8 server ! X331Mono.tgz Mono server ! X331P9K.tgz P9000 server ! X331S3.tgz S3 server ! X331S3V.tgz S3 ViRGE server ! X331SVGA.tgz SVGA server ! X331VG16.tgz 16 colour VGA server (XF86Setup needs this server) ! X331W32.tgz ET4000/W32, ET6000 server </verb> </quote> The following X servers are available for Alpha hardware: <quote> <verb> ! X331Ma64.tgz Mach 64 server ! X331Mono.tgz Mono server (generic driver only) ! X331P9K.tgz P9000 server ! X331TGA.tgz DEC 21030 (TGA) server ! X331S3.tgz S3 server ! X331S3V.tgz S3 ViRGE server ! X331SVGA.tgz SVGA server (Matrox Millennium driver only) </verb> </quote> The following X servers are for PC98 hardware. If you have a PC98 machine, --- 236,266 ---- required by the new configuration utility (XF86Setup). <quote> <verb> ! X3328514.tgz 8514/A server ! X332AGX.tgz AGX server ! X332I128.tgz I128 server ! X332Ma32.tgz Mach 32 server ! X332Ma64.tgz Mach 64 server ! X332Ma8.tgz Mach 8 server ! X332Mono.tgz Mono server ! X332P9K.tgz P9000 server ! X332S3.tgz S3 server ! X332S3V.tgz old S3 ViRGE server (please use SVGA server) ! X332SVGA.tgz SVGA server ! X332VG16.tgz 16 colour VGA server (XF86Setup needs this server) ! X332W32.tgz ET4000/W32, ET6000 server </verb> </quote> The following X servers are available for Alpha hardware: <quote> <verb> ! X332Ma64.tgz Mach 64 server ! X332Mono.tgz Mono server (generic driver only) ! X332P9K.tgz P9000 server ! X332TGA.tgz DEC 21030 (TGA) server ! X332S3.tgz S3 server ! X332S3V.tgz old S3 ViRGE server (please use SVGA server) ! X332SVGA.tgz SVGA server (Matrox Millennium driver only) </verb> </quote> The following X servers are for PC98 hardware. If you have a PC98 machine, *************** *** 654,691 **** is, you don't need any of these. <quote> <verb> ! X3319NS3.tgz PC98 NEC(S3) server ! X3319SPW.tgz PC98 PCSKB-PowerWindow(S3) server ! X3319LPW.tgz PC98 PowerWindowLB(S3) server ! X3319EGC.tgz PC98 EGC(generic) server ! X3319GA9.tgz PC98 GA-968V4/PCI(S3 968) server ! X3319GAN.tgz PC98 GANB-WAP(cirrus) server ! X3319480.tgz PC98 PEGC-480(generic) server ! X3319NKV.tgz PC98 NKV-NEC(cirrus) server ! X3319WS.tgz PC98 WABS(cirrus) server ! X3319WEP.tgz PC98 WAB-EP(cirrus) server ! X3319WSN.tgz PC98 WSN-A2F(cirrus) server ! X3319TGU.tgz PC98 TGUI server </verb> </quote> The following are optional. <quote> <verb> ! X331f100.tgz 100dpi fonts ! X331fcyr.tgz Cyrillic fonts ! X331fnon.tgz Other fonts (Chinese, Japanese, Korean, Hebrew) ! X331fscl.tgz Scalable fonts (Speedo and Type1) ! X331fsrv.tgz Font server and config files ! X331prog.tgz X header files, config files and compile-time libs ! X331nest.tgz Nested X server ! X331vfb.tgz Virtual framebuffer X server ! X331prt.tgz X Print server ! X331ps.tgz PostScript version of the documentation ! X331html.tgz HTML version of the documentation ! X331jdoc.tgz Documentation in Japanese (for version 3.2) ! X331jhtm.tgz HTML version of the documentation in Japanese (3.2) ! X331lkit.tgz X server LinkKit ! X331lk98.tgz X server LinkKit for PC98 servers </verb> </quote> --- 268,308 ---- is, you don't need any of these. <quote> <verb> ! X3329NS3.tgz PC98 NEC(S3) server ! X3329SPW.tgz PC98 PCSKB-PowerWindow(S3) server ! X3329LPW.tgz PC98 PowerWindowLB(S3) server ! X3329EGC.tgz PC98 EGC(generic) server ! X3329GA9.tgz PC98 GA-968V4/PCI(S3 968) server ! X3329GAN.tgz PC98 GANB-WAP(cirrus) server ! X3329480.tgz PC98 PEGC-480(generic) server ! X3329NKV.tgz PC98 NKV-NEC(cirrus) server ! X3329WS.tgz PC98 WABS(cirrus) server ! X3329WEP.tgz PC98 WAB-EP(cirrus) server ! X3329WSN.tgz PC98 WSN-A2F(cirrus) server ! X3329TGU.tgz PC98 TGUI server ! X3329MGA.tgz PC98 MGA server ! X3329SVG.tgz PC98 CLGD755x server ! X3329set.tgz PC98 XF98Setup utility </verb> </quote> The following are optional. <quote> <verb> ! X332f100.tgz 100dpi fonts ! X332fcyr.tgz Cyrillic fonts ! X332fnon.tgz Other fonts (Chinese, Japanese, Korean, Hebrew) ! X332fscl.tgz Scalable fonts (Speedo and Type1) ! X332fsrv.tgz Font server and config files ! X332prog.tgz X header files, config files and compile-time libs ! X332nest.tgz Nested X server ! X332vfb.tgz Virtual framebuffer X server ! X332prt.tgz X Print server ! X332ps.tgz PostScript version of the documentation ! X332html.tgz HTML version of the documentation ! X332jdoc.tgz Documentation in Japanese (for version 3.2) ! X332jhtm.tgz HTML version of the documentation in Japanese (3.2) ! X332lkit.tgz X server LinkKit ! X332lk98.tgz X server LinkKit for PC98 servers </verb> </quote> *************** *** 720,732 **** sh /var/tmp/preinst.sh </verb></tscreen> ! The next step is to untar the installation utility. To do this, make ! sure the extract.tgz file is in the same directory as all the X331*.tgz files, and run the following from that directory: <tscreen><verb> ! cd /var/tmp ! gzip -d < extract.tgz | tar vxf - </verb></tscreen> The installation utility ``extract'' is used to unpack the .tgz files --- 337,348 ---- sh /var/tmp/preinst.sh </verb></tscreen> ! The next step is to make the installation utility executable. To do this, ! make sure the `extract' file is in the same directory as all the X332*.tgz files, and run the following from that directory: <tscreen><verb> ! chmod 755 extract </verb></tscreen> The installation utility ``extract'' is used to unpack the .tgz files *************** *** 746,752 **** To extract the XFree86 binaries, run the following as <bf>root</bf>: <tscreen><verb> cd /usr/X11R6 ! /var/tmp/extract /var/tmp/X331*.tgz </verb></tscreen> Once the required <tt>.tgz</tt> files have been extracted, run the post --- 362,368 ---- To extract the XFree86 binaries, run the following as <bf>root</bf>: <tscreen><verb> cd /usr/X11R6 ! /var/tmp/extract /var/tmp/X332*.tgz </verb></tscreen> Once the required <tt>.tgz</tt> files have been extracted, run the post *************** *** 763,769 **** <p> <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/RELNOTE.sgml,v 3.59.2.21 1997/08/04 02:10:43 dawes Exp $ </verb> </article> --- 379,385 ---- <p> <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/RELNOTE.sgml,v 3.59.2.37 1998/02/28 13:00:00 dawes Exp $ </verb> </article> *** ./xfree86/doc/sgml/SiS.sgml@@/PUBLIC-LATEST Sat Jul 19 10:55:06 1997 --- xc/programs/Xserver/hw/xfree86/doc/sgml/SiS.sgml Fri Mar 6 16:40:55 1998 *************** *** 5,11 **** <!-- Title information --> <title> Information for SiS Users <author> Xavier Ducoin (<it>xavier@rd.lectra.fr</it>) ! <date> 16 January 1997 <!-- Table of contents --> <toc> --- 5,11 ---- <!-- Title information --> <title> Information for SiS Users <author> Xavier Ducoin (<it>xavier@rd.lectra.fr</it>) ! <date> 27 February 1998 <!-- Table of contents --> <toc> *************** *** 12,20 **** <sect> Introduction <p> ! The driver was primarily written for the SiS86c201. ! The driver has almost been completed, with many additional features. ! These include <itemize> <item>Linear Addressing <item>8/15/16/24 bits per pixel --- 12,23 ---- <sect> Introduction <p> ! This driver was primarily written for the SiS86c201. It also works ! on the 202 and the 205 chips. Support for other SiS products is ! not available in XFree86 release 3.3.2. Drivers for the 5597/8 are ! currently under development and should be available in the next release. ! ! The driver supports many advanced features. These include: <itemize> <item>Linear Addressing <item>8/15/16/24 bits per pixel *************** *** 103,113 **** or 1152x900 95 MHz. <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/SiS.sgml,v 3.3 1997/01/25 03:22:15 dawes Exp $ ! $TOG: SiS.sgml /main/1 1997/07/19 10:55:07 kaleb $ </verb> </article> --- 106,116 ---- or 1152x900 95 MHz. <verb> ! $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/SiS.sgml,v 3.3.2.1 1998/02/27 02:45:24 dawes Exp $ ! $TOG: SiS.sgml /main/2 1998/03/06 16:42:33 kaleb $ </verb> </article> *** ./xfree86/os-support/xf86_OSproc.h@@/PUBLIC-LATEST Sat Jul 19 16:04:40 1997 --- xc/programs/Xserver/hw/xfree86/os-support/xf86_OSproc.h Fri Mar 6 16:42:32 1998 *************** *** 1,4 **** ! /* $TOG: xf86_OSproc.h /main/1 1997/07/19 16:04:41 kaleb $ */ /* * Copyright 1990, 1991 by Thomas Roell, Dinkelscherben, Germany * Copyright 1992 by David Dawes <dawes@XFree86.org> --- 1,4 ---- ! /* $TOG: xf86_OSproc.h /main/2 1998/03/06 16:44:09 kaleb $ */ /* * Copyright 1990, 1991 by Thomas Roell, Dinkelscherben, Germany * Copyright 1992 by David Dawes <dawes@XFree86.org> *************** *** 32,38 **** * */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/xf86_OSproc.h,v 3.0 1996/12/19 10:02:15 dawes Exp $ */ #ifndef _XF86_OSPROC_H #define _XF86_OSPROC_H --- 32,38 ---- * */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/xf86_OSproc.h,v 3.0.2.1 1998/02/07 14:27:24 dawes Exp $ */ #ifndef _XF86_OSPROC_H #define _XF86_OSPROC_H *************** *** 325,330 **** --- 325,335 ---- extern void xf86MouseEvents( #if NeedFunctionPrototypes MouseDevPtr + #endif + ); + extern int xf86FlushInput( + #if NeedFunctionPrototypes + int #endif ); extern int xf86XqueKbdProc( *** ./xfree86/vga256/drivers/cirrus/laguna_acl.c@@/PUBLIC-LATEST Sat Jul 19 16:05:14 1997 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/cirrus/laguna_acl.c Fri Mar 6 16:49:19 1998 *************** *** 1,9 **** ! /* $TOG: laguna_acl.c /main/1 1997/07/19 16:05:16 kaleb $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/cirrus/laguna_acl.c,v 3.4.2.2 1997/05/10 11:23:17 hohndel Exp $ */ ! /* * New-style acceleration for the Laguna-family (CL-GD5462/5464). */ --- 1,8 ---- ! /* $TOG: laguna_acl.c /main/2 1998/03/06 16:50:57 kaleb $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/cirrus/laguna_acl.c,v 3.4.2.3 1998/02/15 16:09:36 hohndel Exp $ */ /* * New-style acceleration for the Laguna-family (CL-GD5462/5464). */ *************** *** 29,38 **** is safe. The PCI bus never locked during a large number of screen-screen copies, colexp fills, etc. For now, we'll stick with this setting. (3.2p) */ ! #define ALWAYS_CHECK_FIFO 0 - void LagunaSync(); void LagunaWaitQAvail(); void LagunaSetupForFillRectSolid(); --- 28,43 ---- is safe. The PCI bus never locked during a large number of screen-screen copies, colexp fills, etc. For now, we'll stick with this setting. (3.2p) + + Update (3.3.1a): Some folks have been complaining about mysterious + lockups on AGP machines with 5465's. While I don't have such a + card and can't test the hypothesis, I suspect that the issue is that + the PCI bus is being flooded or something. The solution is to make + the PCI retry thing (ALWAYS_CHECK_FIFO from earlier) to be default + to FALSE, and user-setable to TRUE (with option "pci_retry"). */ ! static Bool lgUsePCIRetry = FALSE; void LagunaSync(); void LagunaWaitQAvail(); void LagunaSetupForFillRectSolid(); *************** *** 109,114 **** --- 114,124 ---- xf86AccelInfoRec.Flags |= NO_TRANSPARENCY; xf86AccelInfoRec.Sync = LagunaSync; + /* Let the PCI bus handle the retry of missed transactions + should the command FIFO fill up. Usually safe, but sometimes + hangs machine. */ + if (OFLG_ISSET(OPTION_PCI_RETRY, &vga256InfoRec.options)) + lgUsePCIRetry = TRUE; /* Solid Color fills */ xf86AccelInfoRec.SetupForFillRectSolid = LagunaSetupForFillRectSolid; *************** *** 202,216 **** } void LagunaWaitQAvail(int n) { ! #if ALWAYS_CHECK_FIFO ! /* Wait until n entries are open in the command queue */ ! volatile unsigned char qfree; ! ! do ! qfree = *(unsigned char *)(cirrusMMIOBase + QFREE); ! while (qfree < n); ! #endif } --- 212,225 ---- } void LagunaWaitQAvail(int n) { ! if (!lgUsePCIRetry) { ! volatile unsigned char qfree; ! /* Wait until n entries are open in the command queue */ ! do ! qfree = *(unsigned char *)(cirrusMMIOBase + QFREE); ! while (qfree < n); ! } } *** ./xfree86/vga256/drivers/et4000/et4_accel.c@@/PUBLIC-LATEST Sat Jul 19 16:05:19 1997 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/et4000/et4_accel.c Fri Mar 6 16:49:28 1998 *************** *** 1,4 **** ! /* $TOG: et4_accel.c /main/1 1997/07/19 16:05:21 kaleb $ */ /* * ET4/6K acceleration interface. * --- 1,4 ---- ! /* $TOG: et4_accel.c /main/2 1998/03/06 16:51:05 kaleb $ */ /* * ET4/6K acceleration interface. * *************** *** 11,17 **** * */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/et4000/et4_accel.c,v 3.11.2.5 1997/05/21 15:02:47 dawes Exp $ */ /* --- 11,17 ---- * */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/et4000/et4_accel.c,v 3.11.2.9 1998/02/01 19:44:23 robin Exp $ */ /* *************** *** 24,44 **** #undef NO_OPTIMIZE #include "vga256.h" #include "xf86.h" #include "vga.h" #include "tseng.h" #include "tseng_acl.h" - #include "compiler.h" #include "xf86xaa.h" #include "miline.h" void TsengSync(); void TsengSetupForFillRectSolid(); ! void Tseng4SubsequentFillRectSolid(); ! void Tseng6SubsequentFillRectSolid(); void TsengSubsequentFillTrapezoidSolid(); --- 24,64 ---- #undef NO_OPTIMIZE + /* + * if ET6K_TRANSPARENCY is set, ScreentoScreenCopy operations (and pattern + * fills) will support transparency. But then the planemask support has to + * be dropped. The default here is to support planemasks, because all Tseng + * chips can do this. Only the ET6000 supports a transparency compare. The + * code could be easily changed to support transparency on the ET6000 and + * planemasks on the others, but that's only useful when transparency is + * more important than planemasks. + */ + + #undef ET6K_TRANSPARENCY + #include "vga256.h" #include "xf86.h" #include "vga.h" #include "tseng.h" #include "tseng_acl.h" #include "xf86xaa.h" + #include "tseng_colexp.h" + #include "tseng_inline.h" #include "miline.h" + /* + * This is just for the messages. + */ + #include "xf86_Config.h" + + void TsengSync(); void TsengSetupForFillRectSolid(); ! void TsengW32iSubsequentFillRectSolid(); ! void TsengW32pSubsequentFillRectSolid(); ! void Tseng6KSubsequentFillRectSolid(); void TsengSubsequentFillTrapezoidSolid(); *************** *** 45,53 **** void TsengSetupForScreenToScreenCopy(); void TsengSubsequentScreenToScreenCopy(); - void TsengSetupForScanlineScreenToScreenColorExpand(); - void TsengSubsequentScanlineScreenToScreenColorExpand(); - void TsengSubsequentBresenhamLine(); void TsengSubsequentTwoPointLine(); --- 65,70 ---- *************** *** 60,87 **** void TsengSetupForFill8x8Pattern(); void TsengSubsequentFill8x8Pattern(); - static int bytesperpixel, powerPerPixel; - static int tseng_line_width; - - /* These will hold the ping-pong registers. - * Note that ping-pong registers might not be needed when using - * BACKGROUND_OPERATIONS (because of the WAIT()-ing involved) - */ - - static LongP MemFg; - static long Fg; - - static LongP MemBg; - static long Bg; - - static LongP MemPat; - static long Pat; - - /* Do we use PCI-retry or busy-waiting */ - extern Bool Use_Pci_Retry; - - /* * The following function sets up the supported acceleration. Call it from * the FbInit() function in the SVGA driver. Do NOT initialize any hardware --- 77,84 ---- void TsengSetupForFill8x8Pattern(); void TsengSubsequentFill8x8Pattern(); + static int planemask_mask; /* will hold the "empty" planemask value */ /* * The following function sets up the supported acceleration. Call it from * the FbInit() function in the SVGA driver. Do NOT initialize any hardware *************** *** 96,148 **** /* * Set up the main acceleration flags. */ ! xf86AccelInfoRec.Flags = BACKGROUND_OPERATIONS | PIXMAP_CACHE ! | HARDWARE_PATTERN_ALIGN_64 | HARDWARE_PATTERN_PROGRAMMED_ORIGIN; ! /* we'll disable COP_FRAMEBUFFER_CONCURRENCY for the public beta ! * release, because it causes font corruption. But THIS NEEDS TO BE ! * INVESTIGATED. */ ! /* | COP_FRAMEBUFFER_CONCURRENCY;*/ - if (et4000_type >= TYPE_ET6000) - { - xf86AccelInfoRec.Flags |= HARDWARE_PATTERN_TRANSPARENCY; - } - /* * The following line installs a "Sync" function, that waits for * all coprocessor operations to complete. */ xf86AccelInfoRec.Sync = TsengSync; /* * We want to set up the FillRectSolid primitive for filling a solid * rectangle. */ - xf86GCInfoRec.PolyFillRectSolidFlags = NO_PLANEMASK; ! xf86AccelInfoRec.SetupForFillRectSolid = TsengSetupForFillRectSolid; ! if (et4000_type >= TYPE_ET6000) { ! xf86AccelInfoRec.SubsequentFillRectSolid = Tseng6SubsequentFillRectSolid; ! #if TRAPEZOIDS_FIXED ! /* disabled for now: not fully compliant yet */ ! xf86AccelInfoRec.SubsequentFillTrapezoidSolid = TsengSubsequentFillTrapezoidSolid; ! #endif } - else - xf86AccelInfoRec.SubsequentFillRectSolid = Tseng4SubsequentFillRectSolid; /* * We also want to set up the ScreenToScreenCopy (BitBLT) primitive for * copying a rectangular area from one location on the screen to ! * another. First we set up the restrictions. In this case, we ! * don't handle transparency color compare nor planemasks. */ xf86GCInfoRec.CopyAreaFlags = NO_PLANEMASK; ! ! if (et4000_type < TYPE_ET6000) xf86GCInfoRec.CopyAreaFlags |= NO_TRANSPARENCY; xf86AccelInfoRec.SetupForScreenToScreenCopy = TsengSetupForScreenToScreenCopy; --- 93,170 ---- /* * Set up the main acceleration flags. */ ! xf86AccelInfoRec.Flags = BACKGROUND_OPERATIONS | PIXMAP_CACHE; ! /* We'll disable COP_FRAMEBUFFER_CONCURRENCY on PCI bus systems, because ! * it causes font corruption. But THIS NEEDS TO BE INVESTIGATED. */ ! if (Tseng_bus != BUS_PCI) ! xf86AccelInfoRec.Flags |= COP_FRAMEBUFFER_CONCURRENCY; ! ! #if 0 ! if (TsengScanlineScreenToScreenFillStippledRect) ! xf86AccelInfoRec.Flags |= DO_NOT_CACHE_STIPPLES; ! #endif /* * The following line installs a "Sync" function, that waits for * all coprocessor operations to complete. */ xf86AccelInfoRec.Sync = TsengSync; + + /* W32 and W32i must wait for ACL before changing registers */ + tseng_need_wait_acl = Is_W32_W32i; + /* we need these shortcuts a lot */ + tseng_line_width = vga256InfoRec.displayWidth * tseng_bytesperpixel; + /* * We want to set up the FillRectSolid primitive for filling a solid * rectangle. + * + * The W32 and W32i chips don't have a register to set the amount of + * bytes per pixel, and hence they don't skip 1 byte in each 4-byte word + * at 24bpp. Therefor, the FG or BG colors would have to be concatenated + * in video memory (R-G-B-R-G-B-... instead of R-G-B-X-R-G-B-X-..., with + * X = dont' care), plus a wrap value that is a multiple of 3 would have + * to be set. There is no such wrap combination available. */ ! if ( !(Is_W32_W32i && (vgaBitsPerPixel == 24)) ) ! { ! xf86AccelInfoRec.SetupForFillRectSolid = TsengSetupForFillRectSolid; ! if (Is_ET6K) { ! xf86AccelInfoRec.SubsequentFillRectSolid = Tseng6KSubsequentFillRectSolid; ! } ! else if (Is_W32p) ! xf86AccelInfoRec.SubsequentFillRectSolid = TsengW32pSubsequentFillRectSolid; ! else /* W32, W32i */ ! xf86AccelInfoRec.SubsequentFillRectSolid = TsengW32iSubsequentFillRectSolid; } + #if TSENG_TRAPEZOIDS + if (Is_ET6K) + { + /* disabled for now: not fully compliant yet */ + xf86AccelInfoRec.SubsequentFillTrapezoidSolid = TsengSubsequentFillTrapezoidSolid; + } + #endif + /* * We also want to set up the ScreenToScreenCopy (BitBLT) primitive for * copying a rectangular area from one location on the screen to ! * another. First we set up the restrictions. We support EITHER a ! * planemask OR TRANSPARENCY, but not both (they use the same Pattern ! * map). */ + #ifdef ET6K_TRANSPARENCY xf86GCInfoRec.CopyAreaFlags = NO_PLANEMASK; ! if (!Is_ET6K) { xf86GCInfoRec.CopyAreaFlags |= NO_TRANSPARENCY; + } + #else + xf86GCInfoRec.CopyAreaFlags = NO_TRANSPARENCY; + #endif xf86AccelInfoRec.SetupForScreenToScreenCopy = TsengSetupForScreenToScreenCopy; *************** *** 149,164 **** xf86AccelInfoRec.SubsequentScreenToScreenCopy = TsengSubsequentScreenToScreenCopy; /* ! * 8x8 pattern tiling not possible on W32 chips in 24bpp mode. * Currently, 24bpp pattern tiling doesn't work at all. */ ! #ifdef BPP24_BUG ! if ( !((et4000_type < TYPE_ET6000) && (vgaBitsPerPixel == 24)) ) ! #else ! if ( !(vgaBitsPerPixel == 24) ) #endif { xf86AccelInfoRec.SetupForFill8x8Pattern = TsengSetupForFill8x8Pattern; --- 171,212 ---- xf86AccelInfoRec.SubsequentScreenToScreenCopy = TsengSubsequentScreenToScreenCopy; + /* overload XAA ImageWrite function */ + if (tsengImageWriteBase) + { + /* Offsets in video memory for line buffers. TsengDoImageWrite assumes + * that each line is the screen width (in bytes) + 3 and rounded up to + * the next dword. + */ + tsengFirstLine = tsengImageWriteBase; + tsengSecondLine = tsengFirstLine + ((tseng_line_width + 6) & ~0x3L); + + if (ET4000.ChipUseLinearAddressing) + tsengFirstLinePntr = (CARD32 *) ((int)vgaLinearBase + tsengFirstLine); + else + tsengFirstLinePntr = (CARD32 *) ( ((int)vgaBase) + 0x1A000L); + + tsengSecondLinePntr = (CARD32 *)((int)tsengFirstLinePntr + ((tseng_line_width + 6) & ~0x3L)); + } + /* ! * 8x8 pattern tiling not possible on W32/i/p chips in 24bpp mode. * Currently, 24bpp pattern tiling doesn't work at all. + * + * On W32 cards, pattern tiling doesn't work as expected. */ + xf86AccelInfoRec.Flags |= HARDWARE_PATTERN_ALIGN_64 + | HARDWARE_PATTERN_PROGRAMMED_ORIGIN; + #ifdef ET6K_TRANSPARENCY + xf86AccelInfoRec.Flags |= HARDWARE_PATTERN_NO_PLANEMASK; ! if (Is_ET6K) ! { ! xf86AccelInfoRec.Flags |= HARDWARE_PATTERN_TRANSPARENCY; ! } #endif + + if ( (vgaBitsPerPixel != 24) && (et4000_type >= TYPE_ET4000W32P) ) { xf86AccelInfoRec.SetupForFill8x8Pattern = TsengSetupForFill8x8Pattern; *************** *** 165,292 **** xf86AccelInfoRec.SubsequentFill8x8Pattern = TsengSubsequentFill8x8Pattern; } ! /* * Setup hardware-line-drawing code. - */ - - if (et4000_type >= TYPE_ET4000W32P) - { - #if 0 - /* -- currently disabled because of major bugs... */ - xf86AccelInfoRec.SubsequentBresenhamLine = - TsengSubsequentBresenhamLine; - xf86AccelInfoRec.ErrorTermBits = 11; - #endif - - xf86AccelInfoRec.SubsequentTwoPointLine = - TsengSubsequentTwoPointLine; - - xf86GCInfoRec.PolyLineSolidZeroWidthFlags = - NO_TRANSPARENCY | NO_PLANEMASK | TWO_POINT_LINE_ERROR_TERM; - xf86GCInfoRec.PolySegmentSolidZeroWidthFlags = - NO_TRANSPARENCY | NO_PLANEMASK | TWO_POINT_LINE_ERROR_TERM; - } - - /* - * Color expansion primitives. - * Since the ET6000 doesn't support CPU-to-screen color expansion, - * we revert to scanline-screen-to-screen color expansion instead. - * This is a less performant solution. - */ - - /* - * ScanlineScreenToScreenColorExpand needs a linear ScratchBufferAddr, - * so there's no point in providing this function when banked adressing - * is used, although it is feasible (through an MMU aperture). XAA needs - * to be modified to accomodate this. Currently it tries to write to - * FrameBufferBase+ScratchBufferAddr, which is only valid in linear mode. * */ ! if ( (et4000_type >= TYPE_ET6000) || (vgaBitsPerPixel == 8) ) { ! xf86AccelInfoRec.ColorExpandFlags = ! BIT_ORDER_IN_BYTE_LSBFIRST | VIDEO_SOURCE_GRANULARITY_PIXEL | NO_PLANEMASK; ! ! #if 1 ! /* new and untested (not used by XAA yet -- needs testing) */ ! ! xf86AccelInfoRec.SetupForScreenToScreenColorExpand = ! TsengSetupForScreenToScreenColorExpand; ! xf86AccelInfoRec.SubsequentScreenToScreenColorExpand = ! TsengSubsequentScreenToScreenColorExpand; #endif ! ! xf86AccelInfoRec.SetupForScanlineScreenToScreenColorExpand = ! TsengSetupForScanlineScreenToScreenColorExpand; ! xf86AccelInfoRec.SubsequentScanlineScreenToScreenColorExpand = ! TsengSubsequentScanlineScreenToScreenColorExpand; ! ! /* triple-buffering is needed to account for double-buffering of Tseng ! * acceleration registers. Increasing this number doesn't help solve the ! * problems with both ET4000 and ET6000 with text rendering. ! */ ! xf86AccelInfoRec.PingPongBuffers = 3; ! ! xf86AccelInfoRec.ScratchBufferSize = scratchVidBase + 1024 - (long) W32Mix; ! xf86AccelInfoRec.ScratchBufferAddr = W32Mix; ! ! if (!OFLG_ISSET(OPTION_LINEAR, &vga256InfoRec.options)) ! { ! /* in banked mode, use aperture #0 */ ! xf86AccelInfoRec.ScratchBufferBase = ! (unsigned char *) ! ( ((int)vgaBase) + 0x18000L + 1024 - xf86AccelInfoRec.ScratchBufferSize ); ! } ! #if 0 ! ErrorF("ColorExpand ScratchBuf: Addr = %d (0x%x); Size = %d (0x%x); Base = %d (0x%x)\n", ! xf86AccelInfoRec.ScratchBufferAddr, xf86AccelInfoRec.ScratchBufferAddr, ! xf86AccelInfoRec.ScratchBufferSize, xf86AccelInfoRec.ScratchBufferSize, ! xf86AccelInfoRec.ScratchBufferBase, xf86AccelInfoRec.ScratchBufferBase); ! #endif } ! #if 0 ! /* ! * CPU-to-screen color expansion doesn't seem to be reliable yet. The ! * W32 needs the correct amount of data sent to it in this mode, or it ! * hangs the machine until is does (?). Currently, the init code in this ! * file or the XAA code that uses this does something wrong, so that ! * occasionally we get accelerator timeouts, and after a few, complete ! * system hangs. ! * ! * What works is this: tell XAA that we have SCANLINE_PAD_DWORD, and then ! * add the following code in TsengSubsequentCPUToScreenColorExpand(): ! * w = (w + 31) & ~31; this code rounds the width up to the nearest ! * multiple of 32, and together with SCANLINE_PAD_DWORD, this makes ! * CPU-to-screen color expansion work. Of course, the display isn't ! * correct (4 chars are "blanked out" when only one is written, for ! * example). But this shows that the principle works. But the code ! * doesn't... ! */ ! if (et4000_type < TYPE_ET6000) ! { ! /* ! * CPU_TRANSFER_PAD_DWORD is implied by XAA, and I'm not sure this is ! * OK, because the W32 might be trying to expand the padding data. ! */ ! xf86AccelInfoRec.ColorExpandFlags |= ! SCANLINE_NO_PAD | CPU_TRANSFER_BASE_FIXED; ! /* "| CPU_TRANSFER_PAD_DWORD" is implied, but should not be needed/allowed */ ! ! xf86AccelInfoRec.SetupForCPUToScreenColorExpand = ! TsengSetupForCPUToScreenColorExpand; ! xf86AccelInfoRec.SubsequentCPUToScreenColorExpand = ! TsengSubsequentCPUToScreenColorExpand; ! ! /* we'll be using MMU aperture 2 */ ! xf86AccelInfoRec.CPUToScreenColorExpandBase = CPU2ACLBase; ! /* ErrorF("CPU2ACLBase = 0x%x\n", CPU2ACLBase);*/ ! /* aperture size is 8kb in banked mode. Larger in linear mode, but 8kb is enough */ ! xf86AccelInfoRec.CPUToScreenColorExpandRange = 8192; ! } ! #endif /* * Finally, we set up the video memory space available to the pixmap --- 213,243 ---- xf86AccelInfoRec.SubsequentFill8x8Pattern = TsengSubsequentFill8x8Pattern; } ! /* * Setup hardware-line-drawing code. * + * We use Bresenham by preference, because it supports hardware clipping + * (using the error term). TwoPointLines() is implemented, but not used, + * because clipped lines are not accelerated (hardware clipping support + * is lacking)... */ ! if (Is_W32p_up) { ! xf86AccelInfoRec.SubsequentBresenhamLine = TsengSubsequentBresenhamLine; ! /* ErrorTermBits = min(errorterm_size, delta_major_size, delta_minor_size) */ ! xf86AccelInfoRec.ErrorTermBits = 11; ! #if TSENG_TWOPOINTLINE ! xf86AccelInfoRec.SubsequentTwoPointLine = TsengSubsequentTwoPointLine; #endif ! xf86GCInfoRec.PolyLineSolidZeroWidthFlags = ! TWO_POINT_LINE_ERROR_TERM; ! xf86GCInfoRec.PolySegmentSolidZeroWidthFlags = ! TWO_POINT_LINE_ERROR_TERM; } ! TsengAccelInit_Colexp(); /* * Finally, we set up the video memory space available to the pixmap *************** *** 296,302 **** */ xf86InitPixmapCache( &vga256InfoRec, ! vga256InfoRec.virtualY * vga256InfoRec.displayWidth * vgaBitsPerPixel / 8, vga256InfoRec.videoRam * 1024 ); --- 247,253 ---- */ xf86InitPixmapCache( &vga256InfoRec, ! vga256InfoRec.virtualY * vga256InfoRec.displayWidth * tseng_bytesperpixel, vga256InfoRec.videoRam * 1024 ); *************** *** 303,594 **** /* * For Tseng, we set up some often-used values */ ! bytesperpixel = vgaBitsPerPixel / 8; ! switch (bytesperpixel) /* for MULBPP optimization */ { ! case 1: powerPerPixel = 0; break; ! case 2: ! case 3: powerPerPixel = 1; break; ! case 4: powerPerPixel = 2; } - tseng_line_width = vga256InfoRec.displayWidth * bytesperpixel; - /* * Init ping-pong registers. * This might be obsoleted by the BACKGROUND_OPERATIONS flag. */ ! MemFg = MemW32ForegroundPing; ! Fg = W32ForegroundPing; ! MemBg = MemW32BackgroundPing; ! Bg = W32BackgroundPing; ! MemPat = MemW32PatternPing; ! Pat = W32PatternPing; } /* - * Some commonly used macro's / inlines - */ - - static __inline__ int COLOR_REPLICATE_DWORD(int color) - { - switch (bytesperpixel) - { - case 1: - color &= 0xFF; - color = (color << 8) | color; - color = (color << 16) | color; - break; - case 2: - color &= 0xFFFF; - color = (color << 16) | color; - break; - } - return color; - } - - /* - * Optimizing note: increasing the wrap size for fixed-color source/pattern - * tiles from 4x1 (as below) to anything bigger doesn't seem to affect - * performance (it might have been better for larger wraps, but it isn't). - */ - - static __inline__ void SET_FG_COLOR(int color) - { - *ACL_SOURCE_ADDRESS = Fg; - *ACL_SOURCE_Y_OFFSET = 3; - color = COLOR_REPLICATE_DWORD(color); - if (et4000_type >= TYPE_ET4000W32P) - { - *ACL_SOURCE_WRAP = 0x02; - *MemFg = color; - } - else - { - *ACL_SOURCE_WRAP = 0x12; - *MemFg = color; - *(MemFg + 1) = color; - } - } - - static __inline__ void SET_BG_COLOR(int color) - { - *ACL_PATTERN_ADDRESS = Pat; - *ACL_PATTERN_Y_OFFSET = 3; - color = COLOR_REPLICATE_DWORD(color); - if (et4000_type >= TYPE_ET4000W32P) - { - *ACL_PATTERN_WRAP = 0x02; - *MemPat = color; - } - else - { - *ACL_PATTERN_WRAP = 0x12; - *MemPat = color; - *(MemPat + 1) = color; - } - } - - /* - * this does the same as SET_FG_COLOR and SET_BG_COLOR together, but is - * faster, because it allows the PCI chipset to chain the requests into a - * burst sequence. The order of the commands is partly linear. - * So far for the theory... - */ - static __inline__ void SET_FG_BG_COLOR(int fgcolor, int bgcolor) - { - *ACL_PATTERN_ADDRESS = Pat; - *ACL_SOURCE_ADDRESS = Fg; - *((LongP) ACL_PATTERN_Y_OFFSET) = 0x00030003; - fgcolor = COLOR_REPLICATE_DWORD(fgcolor); - bgcolor = COLOR_REPLICATE_DWORD(bgcolor); - if (et4000_type >= TYPE_ET4000W32P) - { - *ACL_SOURCE_WRAP = 0x02; - *ACL_PATTERN_WRAP = 0x02; - *MemFg = fgcolor; - *MemPat = bgcolor; - } - else - { - *ACL_SOURCE_WRAP = 0x12; - *ACL_PATTERN_WRAP = 0x12; - *MemFg = fgcolor; - *(MemFg+1) = fgcolor; - *MemPat = bgcolor; - *(MemPat+1) = bgcolor; - } - } - - #define SET_FUNCTION_BLT \ - if (et4000_type>=TYPE_ET6000) \ - *ACL_MIX_CONTROL = 0x33; \ - else \ - *ACL_ROUTING_CONTROL = 0x00; - - #define SET_FUNCTION_BLT_TR \ - *ACL_MIX_CONTROL = 0x13; - - #define SET_FUNCTION_COLOREXPAND \ - if (et4000_type >= TYPE_ET6000) \ - *ACL_MIX_CONTROL = 0x32; \ - else \ - *ACL_ROUTING_CONTROL = 0x08; - - #define SET_FUNCTION_COLOREXPAND_CPU \ - *ACL_ROUTING_CONTROL = 0x02; - - /* - * Real 32-bit multiplications are horribly slow compared to 16-bit (on i386). - * - * FBADDR() could be implemented completely in assembler on i386. - */ - #ifdef NO_OPTIMIZE - #define MULBPP(x) ((x) * bytesperpixel) - #else - static __inline__ int MULBPP(int x) - { - int result = x << powerPerPixel; - if (bytesperpixel != 3) - return result; - else - return result + x; - } - #endif - - #define FBADDR(x,y) ( (y) * tseng_line_width + MULBPP(x) ) - - #define SET_FG_ROP(rop) \ - *ACL_FOREGROUND_RASTER_OPERATION = W32OpTable[rop]; - - #define SET_BG_ROP(rop) \ - *ACL_BACKGROUND_RASTER_OPERATION = W32PatternOpTable[rop]; - - /* faster than separate functions */ - #define SET_FG_BG_ROP(fgrop, bgrop) \ - *((WordP) ACL_BACKGROUND_RASTER_OPERATION) = \ - W32PatternOpTable[bgrop] | W32OpTable[fgrop]; - - #define SET_BG_ROP_TR(rop, bg_color) \ - if ((bg_color) == -1) /* transparent color expansion */ \ - *ACL_BACKGROUND_RASTER_OPERATION = 0xaa; \ - else \ - *ACL_BACKGROUND_RASTER_OPERATION = W32PatternOpTable[rop]; - - - static int old_x = 0, old_y = 0; - - /* generic SET_XY */ - static __inline__ void SET_XY(int x, int y) - { - int new_x; - if (et4000_type >= TYPE_ET6000) - new_x = MULBPP(x)-1; - else - new_x = MULBPP(x-1); - *((LongP) ACL_X_COUNT) = ((y - 1) << 16) + new_x; - old_x = x; old_y = y; - } - - /* - * This is plain and simple "benchmark rigging". - * (no real application does lots of subsequent same-size blits) - * - * The effect of this is amazingly good on e.g large blits: 400x400 rectangle fill - * in 24 and 32 bpp jumps from 276 MB/sec to up to 490 MB/sec... But not always. - * There must be a good reason why this gives such a boost, but I don't know it. - */ - - static __inline__ void SET_XY_4(int x, int y) - { - int new_xy; - - if ( (old_y != y) || (old_x != x) ) - { - new_xy = ((y - 1) << 16) + MULBPP(x-1); - *((LongP) ACL_X_COUNT) = new_xy; - old_x = x; old_y = y; - } - } - - static __inline__ void SET_XY_6(int x, int y) - { - int new_xy; /* using this intermediate variable is faster */ - - if ( (old_y != y) || (old_x != x) ) - { - new_xy = ((y - 1) << 16) + MULBPP(x)-1; - *((LongP) ACL_X_COUNT) = new_xy; - old_x = x; old_y = y; - } - } - - - /* generic SET_XY_RAW */ - static __inline__ void SET_XY_RAW(int x, int y) - { - *((LongP) ACL_X_COUNT) = (y << 16) + x; - old_x = x; old_y = y; - } - - #define SET_DELTA(Min, Maj) \ - *((LongP) ACL_DELTA_MINOR) = ((Maj) << 16) + (Min) - - #define SET_SECONDARY_DELTA(Min, Maj) \ - *((LongP) ACL_SECONDARY_DELTA_MINOR) = ((Maj) << 16) + (Min) - - - /* Must do 0x09 (in one operation) for the W32 */ - #define START_ACL(dst) \ - *(ACL_DESTINATION_ADDRESS) = dst; \ - if (et4000_type < TYPE_ET4000W32P) *ACL_OPERATION_STATE = 0x09; - - /* START_ACL for the ET6000 */ - #define START_ACL_6(dst) \ - *(ACL_DESTINATION_ADDRESS) = dst; - - #define START_ACL_CPU(dst) \ - *(ACL_DESTINATION_ADDRESS) = dst; - - static __inline__ void PINGPONG() - { - if (Fg == W32ForegroundPing) - { - MemFg = MemW32ForegroundPong; Fg = W32ForegroundPong; - MemBg = MemW32BackgroundPong; Bg = W32BackgroundPong; - MemPat = MemW32PatternPong; Pat = W32PatternPong; - } - else - { - MemFg = MemW32ForegroundPing; Fg = W32ForegroundPing; - MemBg = MemW32BackgroundPing; Bg = W32BackgroundPing; - MemPat = MemW32PatternPing; Pat = W32PatternPing; - } - } - - static int old_dir=-1; - - #ifdef NO_OPTIMIZE - #define SET_XYDIR(dir) \ - *ACL_XY_DIRECTION = (dir); - #else - /* - * only changing ACL_XY_DIRECTION when it needs to be changed avoids - * unnecessary PCI bus writes, which are slow. This shows up very well - * on consecutive small fills. - */ - #define SET_XYDIR(dir) \ - if ((dir) != old_dir) \ - *ACL_XY_DIRECTION = old_dir = (dir); - #endif - - #define SET_SECONDARY_XYDIR(dir) \ - *ACL_SECONDARY_EDGE = (dir); - - /* * This is the implementation of the Sync() function. * * To avoid pipeline/cache/buffer flushing in the PCI subsystem and the VGA --- 254,293 ---- /* * For Tseng, we set up some often-used values */ ! switch (tseng_bytesperpixel) /* for MULBPP optimization */ { ! case 1: tseng_powerPerPixel = 0; ! planemask_mask = 0x000000FF; ! tseng_neg_x_pixel_offset = 0; break; ! case 2: tseng_powerPerPixel = 1; ! planemask_mask = 0x0000FFFF; ! tseng_neg_x_pixel_offset = 1; break; ! case 3: tseng_powerPerPixel = 1; ! planemask_mask = 0x00FFFFFF; ! tseng_neg_x_pixel_offset = 2; /* is this correct ??? */ ! break; ! case 4: tseng_powerPerPixel = 2; ! planemask_mask = 0xFFFFFFFF; ! tseng_neg_x_pixel_offset = 3; ! break; } /* * Init ping-pong registers. * This might be obsoleted by the BACKGROUND_OPERATIONS flag. */ ! tsengMemFg = MemW32ForegroundPing; ! tsengFg = W32ForegroundPing; ! tsengMemBg = MemW32BackgroundPing; ! tsengBg = W32BackgroundPing; ! tsengMemPat = MemW32PatternPing; ! tsengPat = W32PatternPing; } /* * This is the implementation of the Sync() function. * * To avoid pipeline/cache/buffer flushing in the PCI subsystem and the VGA *************** *** 618,634 **** /* ErrorF("S");*/ - #ifdef DEBUG_PLANEMASK - if (planemask != -1) - ErrorF("SetupForFillRectSolid: BUG: planemask = 0x%x\n", planemask); - #endif - PINGPONG(); ! /* Avoid PCI-Retry's */ ! if (!Use_Pci_Retry) WAIT_QUEUE; ! SET_FG_ROP(rop); SET_FG_COLOR(color); SET_FUNCTION_BLT; --- 317,340 ---- /* ErrorF("S");*/ PINGPONG(); ! wait_acl_queue(); ! ! /* ! * planemask emulation uses a modified "standard" FG ROP (see ET6000 ! * data book p 66 or W32p databook p 37: "Bit masking"). We only enable ! * the planemask emulation when the planemask is not a no-op, because ! * blitting speed would suffer. ! */ ! if ((planemask & planemask_mask) != planemask_mask) { ! SET_FG_ROP_PLANEMASK(rop); ! SET_BG_COLOR(planemask); ! } ! else { ! SET_FG_ROP(rop); ! } SET_FG_COLOR(color); SET_FUNCTION_BLT; *************** *** 643,656 **** * Splitting it up between ET4000 and ET6000 avoids lots of "if (et4000_type * >= TYPE_ET6000)" -style comparisons. */ ! void Tseng4SubsequentFillRectSolid(x, y, w, h) int x, y, w, h; { int destaddr = FBADDR(x,y); ! /* Avoid PCI-Retry's */ ! if (!Use_Pci_Retry) WAIT_QUEUE; SET_XYDIR(0); SET_XY_4(w, h); --- 349,374 ---- * Splitting it up between ET4000 and ET6000 avoids lots of "if (et4000_type * >= TYPE_ET6000)" -style comparisons. */ ! void TsengW32pSubsequentFillRectSolid(x, y, w, h) int x, y, w, h; { int destaddr = FBADDR(x,y); ! wait_acl_queue(); + /* + * Restoring the ACL_SOURCE_ADDRESS here is needed as long as Bresenham + * lines are enabled for >8bpp. Or until XAA allows us to render + * horizontal lines using the same Bresenham code instead of re-routing + * them to FillRectSolid. For XDECREASING lines, the SubsequentBresenham + * code adjusts the ACL_SOURCE_ADDRESS to make sure XDECREASING lines + * are drawn with the correct colors. But if a batch of subsequent + * operations also holds a few horizontal lines, they will be routed to + * here without calling the SetupFor... code again, and the + * ACL_SOURCE_ADDRESS will be wrong. + */ + *ACL_SOURCE_ADDRESS = tsengFg; + SET_XYDIR(0); SET_XY_4(w, h); *************** *** 657,670 **** START_ACL(destaddr); } ! void Tseng6SubsequentFillRectSolid(x, y, w, h) int x, y, w, h; { int destaddr = FBADDR(x,y); ! /* Avoid PCI-Retry's */ ! if (!Use_Pci_Retry) WAIT_QUEUE; /* if XYDIR is not reset here, drawing a hardware line in between * blitting, with the same ROP, color, etc will not cause a call to * SetupFor... (because linedrawing uses SetupForSolidFill() as its --- 375,403 ---- START_ACL(destaddr); } ! void TsengW32iSubsequentFillRectSolid(x, y, w, h) int x, y, w, h; { int destaddr = FBADDR(x,y); ! wait_acl_queue(); + SET_XYDIR(0); + + SET_XY_6(w, h); + START_ACL(destaddr); + } + + void Tseng6KSubsequentFillRectSolid(x, y, w, h) + int x, y, w, h; + { + int destaddr = FBADDR(x,y); + + wait_acl_queue(); + + /* see comment in TsengW32pSubsequentFillRectSolid */ + *ACL_SOURCE_ADDRESS = tsengFg; + /* if XYDIR is not reset here, drawing a hardware line in between * blitting, with the same ROP, color, etc will not cause a call to * SetupFor... (because linedrawing uses SetupForSolidFill() as its *************** *** 681,689 **** /* * This is the implementation of the SetupForScreenToScreenCopy function * that sets up the coprocessor for a subsequent batch of ! * screen-to-screen copies. Remember, we don't handle transparency, ! * so the transparency color is ignored. */ static int blitxdir, blitydir; void TsengSetupForScreenToScreenCopy(xdir, ydir, rop, planemask, --- 414,453 ---- /* * This is the implementation of the SetupForScreenToScreenCopy function * that sets up the coprocessor for a subsequent batch of ! * screen-to-screen copies. */ + + static __inline__ void Tseng_setup_screencopy(rop, planemask, transparency_color, blit_dir) + int rop; + unsigned planemask; + int transparency_color; + int blit_dir; + { + wait_acl_queue(); + + #ifdef ET6K_TRANSPARENCY + if (Is_ET6K && (transparency_color != -1)) + { + SET_BG_COLOR(transparency_color); + SET_FUNCTION_BLT_TR; + } + else + SET_FUNCTION_BLT; + + SET_FG_ROP(rop); + #else + if ((planemask & planemask_mask) != planemask_mask) { + SET_FG_ROP_PLANEMASK(rop); + SET_BG_COLOR(planemask); + } + else { + SET_FG_ROP(rop); + } + SET_FUNCTION_BLT; + #endif + SET_XYDIR(blit_dir); + } + static int blitxdir, blitydir; void TsengSetupForScreenToScreenCopy(xdir, ydir, rop, planemask, *************** *** 708,728 **** if (xdir == -1) blit_dir |= 0x1; if (ydir == -1) blit_dir |= 0x2; ! /* Avoid PCI-Retry's */ ! if (!Use_Pci_Retry) WAIT_QUEUE; - SET_XYDIR(blit_dir); - - if ((et4000_type >= TYPE_ET6000) && (transparency_color != -1)) - { - SET_BG_COLOR(transparency_color); - SET_FUNCTION_BLT_TR; - } - else - SET_FUNCTION_BLT; - - SET_FG_ROP(rop); - *ACL_SOURCE_WRAP = 0x77; /* no wrap */ *ACL_SOURCE_Y_OFFSET = tseng_line_width-1; } --- 472,479 ---- if (xdir == -1) blit_dir |= 0x1; if (ydir == -1) blit_dir |= 0x2; ! Tseng_setup_screencopy(rop, planemask, transparency_color, blit_dir); *ACL_SOURCE_WRAP = 0x77; /* no wrap */ *ACL_SOURCE_Y_OFFSET = tseng_line_width-1; } *************** *** 783,790 **** destaddr += x2; } ! /* Avoid PCI-Retry's */ ! if (!Use_Pci_Retry) WAIT_QUEUE; SET_XY(w, h); *ACL_SOURCE_ADDRESS = srcaddr; --- 534,540 ---- destaddr += x2; } ! wait_acl_queue(); SET_XY(w, h); *ACL_SOURCE_ADDRESS = srcaddr; *************** *** 803,823 **** /* ErrorF("P");*/ ! /* Avoid PCI-Retry's */ ! if (!Use_Pci_Retry) WAIT_QUEUE; ! SET_FG_ROP(rop); ! ! if ((et4000_type >= TYPE_ET6000) && (transparency_color != -1)) { - SET_BG_COLOR(transparency_color); - SET_FUNCTION_BLT_TR; - } - else - SET_FUNCTION_BLT; - - switch(bytesperpixel) - { case 1: *ACL_SOURCE_WRAP = 0x33; /* 8x8 wrap */ *ACL_SOURCE_Y_OFFSET = 8 - 1; break; --- 553,562 ---- /* ErrorF("P");*/ ! Tseng_setup_screencopy(rop, planemask, transparency_color, 0); ! switch(tseng_bytesperpixel) { case 1: *ACL_SOURCE_WRAP = 0x33; /* 8x8 wrap */ *ACL_SOURCE_Y_OFFSET = 8 - 1; break; *************** *** 830,837 **** case 4: *ACL_SOURCE_WRAP = 0x35; /* 32x8 wrap */ *ACL_SOURCE_Y_OFFSET = 32 - 1; } - - SET_XYDIR(0); } void TsengSubsequentFill8x8Pattern(patternx, patterny, x, y, w, h) --- 569,574 ---- *************** *** 842,849 **** int destaddr = FBADDR(x,y); int srcaddr = pat_src_addr + MULBPP(patterny * 8 + patternx); ! /* Avoid PCI-Retry's */ ! if (!Use_Pci_Retry) WAIT_QUEUE; *ACL_SOURCE_ADDRESS = srcaddr; --- 579,585 ---- int destaddr = FBADDR(x,y); int srcaddr = pat_src_addr + MULBPP(patterny * 8 + patternx); ! wait_acl_queue(); *ACL_SOURCE_ADDRESS = srcaddr; *************** *** 851,1056 **** START_ACL(destaddr); } - - static int ColorExpandDst; - - void TsengSetupForScanlineScreenToScreenColorExpand(x, y, w, h, bg, fg, rop, planemask) - int x, y; - int w, h; - int bg, fg; - int rop; - unsigned int planemask; - { - - /* ErrorF("X");*/ - - PINGPONG(); - - ColorExpandDst = FBADDR(x,y); - - /* Avoid PCI-Retry's */ - if (!Use_Pci_Retry) WAIT_QUEUE; - - SET_FG_ROP(rop); - SET_BG_ROP_TR(rop, bg); - - SET_FG_BG_COLOR(fg, bg); - - SET_FUNCTION_COLOREXPAND; - - *ACL_MIX_Y_OFFSET = 0x0FFF; /* see remark below */ - - SET_XYDIR(0); - - SET_XY(w, 1); - } - - void TsengSubsequentScanlineScreenToScreenColorExpand(srcaddr) - int srcaddr; - { - /* COP_FRAMEBUFFER_CONCURRENCY can cause text corruption !!! - * - * Looks like some scanline data DWORDS are not written to the ping-pong - * framebuffers, so that old data is rendered in some places. Is this - * caused by PCI host bridge queueing? Or is data lost when written - * while the accelerator is accessing the framebuffer (which would be - * the real reason NOT to use COP_FRAMEBUFFER_CONCURRENCY)? - * - * Even with ping-ponging, parts of scanline three (which are supposed - * to be written to the old, already rendered scanline 1 buffer) have - * not yet arrived in the framebuffer, and thus some parts of the new - * scanline are rendered with data from two lines above it. - * - * Extra problem: ET6000 queueing really needs triple buffering for - * this, because XAA can still overwrite scanline 1 when writing data - * for scanline three. Right _after_ that, the accelerator blocks on - * queueing in TsengSubsequentScanlineScreenToScreenColorExpand(), but - * then it's too late: the scanline data is already overwritten. That's - * why we use 3 ping-pong buffers. - * - * "x11perf -fitext" is about 530k chars/sec now, but with - * COP_FRAMEBUFFER_CONCURRENCY, this goes up to >700k (which is similar - * to what Xinside can do). - * - * Needs to be investigated! - * - * Update: this seems to depend upon ACL_MIX_Y_OFFSET, although that - * register should not do anything at all here (only one line done at a - * time, so no Y_OFFSET needed). Setting the offset to 0x0FFF seems to - * remedy this situation most of the time (still an occasional error - * here and there). This _could_ be a bug, but then it would have to be - * in both in the ET6000 _and_ the ET4000W32p. - * - * The more delay added after starting a color-expansion operation, the - * less font corruption we get. But nothing really solves it. - */ - - /* Avoid PCI-Retry's */ - if (!Use_Pci_Retry) WAIT_QUEUE; - - *ACL_MIX_ADDRESS = srcaddr; - START_ACL(ColorExpandDst); - ColorExpandDst += tseng_line_width; - - /* - * If not using triple-buffering, we need to wait for the queued - * register set to be transferred to the working register set here, - * because otherwise an e.g. double-buffering mechanism could overwrite - * the buffer that's currently being worked with with new data too soon. - * - * WAIT_QUEUE; // not needed with triple-buffering - */ - } - - /* - * CPU-to-Screen color expansion. - * This is for ET4000 only (The ET6000 cannot do this) - */ - - void TsengSetupForCPUToScreenColorExpand(bg, fg, rop, planemask) - int bg, fg; - int rop; - unsigned int planemask; - { - /* ErrorF("X");*/ - - PINGPONG(); - - /* Avoid PCI-Retry's */ - if (!Use_Pci_Retry) WAIT_QUEUE; - - SET_FG_ROP(rop); - SET_BG_ROP_TR(rop, bg); - - SET_XYDIR(0); - - SET_FG_BG_COLOR(fg,bg); - - SET_FUNCTION_COLOREXPAND_CPU; - - *ACL_MIX_ADDRESS = 0; - } - - - /* - * TsengSubsequentCPUToScreenColorExpand() is potentially dangerous: - * Not writing enough data to the MMU aperture for CPU-to-screen color - * expansion will eventually cause a system deadlock! - */ - - void TsengSubsequentCPUToScreenColorExpand(x, y, w, h, skipleft) - int x, y; - int w, h; - int skipleft; - { - int destaddr = FBADDR(x,y); - - /* ErrorF("\n %dx%d",w,h); */ - - /* Avoid PCI-Retry's */ - if (!Use_Pci_Retry) WAIT_QUEUE; - - *ACL_MIX_Y_OFFSET = w-1; - SET_XY(w, h); - START_ACL_CPU(destaddr); - } - - - void TsengSetupForScreenToScreenColorExpand(bg, fg, rop, planemask) - int bg, fg; - int rop; - unsigned int planemask; - { - /* ErrorF("SSC ");*/ - - PINGPONG(); - - /* Avoid PCI-Retry's */ - if (!Use_Pci_Retry) WAIT_QUEUE; - - SET_FG_ROP(rop); - SET_BG_ROP_TR(rop, bg); - - SET_FUNCTION_COLOREXPAND; - - SET_FG_BG_COLOR(fg, bg); - - SET_XYDIR(0); - } - - void TsengSubsequentScreenToScreenColorExpand(srcx, srcy, x, y, w, h) - int srcx, srcy; - int x, y; - int w, h; - { - int destaddr = FBADDR(x,y); - - int mixaddr = FBADDR(srcx, srcy * 8); - - /* Avoid PCI-Retry's */ - if (!Use_Pci_Retry) WAIT_QUEUE; - - SET_XY(w, h); - *ACL_MIX_ADDRESS = mixaddr; - *ACL_MIX_Y_OFFSET = w-1; - - START_ACL(destaddr); - } - - - /* * W32p/ET6000 hardware linedraw code. * ! * Actually, the Tseng engines are rather slow line-drawing machines. ! * On 350-pixel long lines, the _raw_ accelerator performance is about ! * 24400 lines per second. And that is "only" about 8.5 Million pixels ! * per second. ! * The break-even point is a Pentium-133, which does line-drawing as fast as ! * the ET6000, including X-overhead. ! * Of course, there's the issue of hardware parallellism that makes a difference. ! * ! * TsengSetupForFillRectSolid() is used as a setup function */ void TsengSubsequentBresenhamLine(x1, y1, octant, err, e1, e2, length) --- 587,596 ---- START_ACL(destaddr); } /* * W32p/ET6000 hardware linedraw code. * ! * TsengSetupForFillRectSolid() is used as a setup function. */ void TsengSubsequentBresenhamLine(x1, y1, octant, err, e1, e2, length) *************** *** 1059,1081 **** int err, e1, e2; int length; { - int algrthm=0, direction=0; int destaddr = FBADDR(x1,y1); direction = W32BresTable[octant]; if (octant & XDECREASING) ! destaddr += bytesperpixel-1; ! if (!(octant & YDECREASING)) ! algrthm = 16; ! ! /* Avoid PCI-Retry's */ ! if (!Use_Pci_Retry) WAIT_QUEUE; if (!(octant & YMAJOR)) { ! SET_XY_RAW(length * bytesperpixel - 1, 0xFFF); } else { --- 599,630 ---- int err, e1, e2; int length; { int destaddr = FBADDR(x1,y1); + /* + * We need to compensate for the automatic biasing in the Tseng Bresenham + * engine. It uses either "MicroSoft" or "XGA" bias. Both are + * incompatible with X. + */ + unsigned int tseng_bias_compensate = 0xd8; + int algrthm; + int direction; + int DeltaMinor = e1 >> 1; + int DeltaMajor = (e1 - e2) >> 1; + int ErrorTerm = e1 - err; + int xydir; direction = W32BresTable[octant]; + algrthm = ((tseng_bias_compensate >> octant) & 1) ^ 1; + xydir = 0xA0 | (algrthm<<4) | direction; if (octant & XDECREASING) ! destaddr += tseng_bytesperpixel-1; ! wait_acl_queue(); if (!(octant & YMAJOR)) { ! SET_X_YRAW(length, 0xFFF); } else { *************** *** 1082,1091 **** SET_XY_RAW(0xFFF, length -1); } ! SET_DELTA(e1>>1, length); - SET_XYDIR(0x80 | algrthm | direction); - START_ACL(destaddr); } --- 631,647 ---- SET_XY_RAW(0xFFF, length -1); } ! SET_DELTA(DeltaMinor, DeltaMajor); ! *ACL_ERROR_TERM = ErrorTerm; ! ! /* make sure colors are rendered correctly if >8bpp */ ! if (octant & XDECREASING) ! *ACL_SOURCE_ADDRESS = tsengFg + tseng_neg_x_pixel_offset; ! else ! *ACL_SOURCE_ADDRESS = tsengFg; ! ! SET_XYDIR(xydir); START_ACL(destaddr); } *************** *** 1112,1117 **** --- 668,674 ---- * causing a complete accelerator hang. */ + #if TSENG_TWOPOINTLINE void TsengSubsequentTwoPointLine(x1, y1, x2, y2, bias) int x1, y1; int x2, y2; /* excl. */ *************** *** 1121,1133 **** int dir_reg = 0x80; int octant=0; ! /* ErrorF("L"); */ /* * Fix drawing "bug" when drawing right-to-left (dx<0). This could also be * fixed by changing the offset in the color "pattern" instead if dx < 0 */ ! if (bytesperpixel > 1) { if (x2 < x1) { --- 678,690 ---- int dir_reg = 0x80; int octant=0; ! /* ErrorF("L"); */ /* * Fix drawing "bug" when drawing right-to-left (dx<0). This could also be * fixed by changing the offset in the color "pattern" instead if dx < 0 */ ! if (tseng_bytesperpixel > 1) { if (x2 < x1) { *************** *** 1150,1156 **** /* destaddr must point to highest addressed byte in the pixel when drawing * right-to-left */ ! destaddr += bytesperpixel-1; } /* compute delta-Y */ --- 707,713 ---- /* destaddr must point to highest addressed byte in the pixel when drawing * right-to-left */ ! destaddr += tseng_bytesperpixel-1; } /* compute delta-Y */ *************** *** 1164,1171 **** dy = -dy; } ! /* Avoid PCI-Retry's */ ! if (!Use_Pci_Retry) WAIT_QUEUE; /* compute axial direction and load registers */ if (dx >= dy) /* X is major axis */ --- 721,727 ---- dy = -dy; } ! wait_acl_queue(); /* compute axial direction and load registers */ if (dx >= dy) /* X is major axis */ *************** *** 1189,1194 **** --- 745,751 ---- START_ACL(destaddr); } + #endif /* * Trapezoid filling code. *************** *** 1196,1204 **** * TsengSetupForFillRectSolid() is used as a setup function */ - #undef USE_ERROR_TERM #undef DEBUG_TRAP void TsengSubsequentFillTrapezoidSolid(ytop, height, left, dxL, dyL, eL, right, dxR, dyR, eR) int ytop; int height; --- 753,761 ---- * TsengSetupForFillRectSolid() is used as a setup function */ #undef DEBUG_TRAP + #if TSENG_TRAPEZOIDS void TsengSubsequentFillTrapezoidSolid(ytop, height, left, dxL, dyL, eL, right, dxR, dyR, eR) int ytop; int height; *************** *** 1209,1225 **** int dxR, dyR; int eR; { int destaddr, algrthm; ! int xcount = right - left + 1; ! #ifdef USE_ERROR_TERM ! int dir_reg = 0x60; ! int sec_dir_reg = 0x20; ! #else ! int dir_reg = 0x40; ! int sec_dir_reg = 0x00; ! #endif int octant=0; - int bias = 0x00; /* FIXME !!! */ /* ErrorF("#");*/ --- 766,777 ---- int dxR, dyR; int eR; { + unsigned int tseng_bias_compensate = 0xd8; int destaddr, algrthm; ! int xcount = right - left + 1; /* both edges included */ ! int dir_reg = 0x60; /* trapezoid drawing; use error term for primary edge */ ! int sec_dir_reg = 0x20; /* use error term for secondary edge */ int octant=0; /* ErrorF("#");*/ *************** *** 1242,1251 **** /* Y direction is always positive (top-to-bottom drawing) */ ! /* Avoid PCI-Retry's */ ! if (!Use_Pci_Retry) WAIT_QUEUE; - /* left edge */ /* compute axial direction and load registers */ if (dxL >= dyL) /* X is major axis */ --- 794,801 ---- /* Y direction is always positive (top-to-bottom drawing) */ ! wait_acl_queue(); /* left edge */ /* compute axial direction and load registers */ if (dxL >= dyL) /* X is major axis */ *************** *** 1253,1259 **** dir_reg |= 4; SET_DELTA(dyL, dxL); if (dir_reg & 1) { /* edge coherency: draw left edge */ ! destaddr += bytesperpixel; sec_dir_reg |= 0x80; xcount--; } --- 803,809 ---- dir_reg |= 4; SET_DELTA(dyL, dxL); if (dir_reg & 1) { /* edge coherency: draw left edge */ ! destaddr += tseng_bytesperpixel; sec_dir_reg |= 0x80; xcount--; } *************** *** 1263,1275 **** SetYMajorOctant(octant); SET_DELTA(dxL, dyL); } ! #ifdef USE_ERROR_TERM ! *ACL_ERROR_TERM = eL-1; ! #endif /* select "linedraw algorithm" (=bias) and load direction register */ /* ErrorF(" o=%d ", octant);*/ ! algrthm = ((bias >> octant) & 1) ^ 1; dir_reg |= algrthm << 4; SET_XYDIR(dir_reg); --- 813,823 ---- SetYMajorOctant(octant); SET_DELTA(dxL, dyL); } ! *ACL_ERROR_TERM = eL; /* select "linedraw algorithm" (=bias) and load direction register */ /* ErrorF(" o=%d ", octant);*/ ! algrthm = ((tseng_bias_compensate >> octant) & 1) ^ 1; dir_reg |= algrthm << 4; SET_XYDIR(dir_reg); *************** *** 1295,1303 **** { SET_SECONDARY_DELTA(dxR, dyR); } - #ifdef USE_ERROR_TERM *ACL_SECONDARY_ERROR_TERM = eR; - #endif /* ErrorF("%02x", sec_dir_reg);*/ SET_SECONDARY_XYDIR(sec_dir_reg); --- 843,849 ---- *************** *** 1310,1313 **** --- 856,861 ---- START_ACL_6(destaddr); } + #endif + *** ./xfree86/vga256/drivers/et4000/tseng.h@@/PUBLIC-LATEST Sat Jul 19 16:05:24 1997 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/et4000/tseng.h Fri Mar 6 16:49:40 1998 *************** *** 1,9 **** ! /* $TOG: tseng.h /main/1 1997/07/19 16:05:26 kaleb $ */ - /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/et4000/tseng.h,v 3.0.2.4 1997/05/25 05:06:49 dawes Exp $ */ #ifndef _TSENG_H #define _TSENG_H --- 1,10 ---- ! /* $TOG: tseng.h /main/2 1998/03/06 16:51:18 kaleb $ */ + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/et4000/tseng.h,v 3.0.2.7 1998/02/27 01:29:28 dawes Exp $ */ + #ifndef _TSENG_H #define _TSENG_H *************** *** 15,21 **** #define MAX_TSENG_CLOCK 86000 - #ifdef W32_SUPPORT typedef struct { unsigned char cmd_reg; unsigned char PLL_f2_M; --- 16,21 ---- *************** *** 23,61 **** unsigned char PLL_ctrl; unsigned char PLL_w_idx; unsigned char PLL_r_idx; } GenDACstate; - #endif typedef struct { ! vgaHWRec std; /* good old IBM VGA */ ! unsigned char ExtStart; /* Tseng ET4000 specials CRTC 0x33/0x34/0x35 */ ! unsigned char Compatibility; ! unsigned char OverflowHigh; ! unsigned char StateControl; /* TS 6 & 7 */ ! unsigned char AuxillaryMode; ! unsigned char Misc; /* ATC 0x16 */ ! unsigned char SegSel1, SegSel2; ! unsigned char HorOverflow; ! unsigned char ET6KMMAPCtrl; /* ET6000 -- used for linear memory mapping */ ! unsigned char ET6KVidCtrl1; /* ET6000 -- used for 15/16 bpp modes */ ! unsigned char ET6KMemBase; /* ET6000 -- linear memory mapped address */ ! unsigned char ET6KPerfContr; /* ET6000 -- system performance control */ ! unsigned char ET6KDispFeat; /* ET6000 -- display feature register (0x46) */ ! unsigned char ET6KMclkM, ET6KMclkN; /* memory clock values */ ! #ifdef W32_SUPPORT ! unsigned char SegMapComp; /* CRTC 0x30 */ ! unsigned char GenPurp; /* CRTC 0x31 */ ! unsigned char VSConf1; /* CRTC 0x36 */ ! unsigned char VSConf2; /* CRTC 0x37 */ ! unsigned char IMAPortCtrl; /* IMA port control register (0x217B index 0xF7) */ GenDACstate gendac; ! Bool Gr_Mode; /* kludge: true if we're dealing with a graphics mode */ ! unsigned char ATTdac_cmd; /* command register for ATT 49x DACs */ ! #endif ! #ifndef MONOVGA ! unsigned char RCConf; /* CRTC 0x32 */ ! #endif } vgaET4000Rec, *vgaET4000Ptr; extern vgaVideoChipRec ET4000; --- 23,57 ---- unsigned char PLL_ctrl; unsigned char PLL_w_idx; unsigned char PLL_r_idx; + unsigned char timingctrl; /* for STG170x */ } GenDACstate; typedef struct { ! vgaHWRec std; /* good old IBM VGA */ ! unsigned char SegMapComp; /* CRTC 0x30 */ ! unsigned char GenPurp; /* CRTC 0x31 */ ! unsigned char RCConf; /* CRTC 0x32 */ ! unsigned char ExtStart; /* CRTC 0x33 */ ! unsigned char Compatibility; /* CRTC 0x34 */ ! unsigned char OverflowHigh; /* CRTC 0x35 */ ! unsigned char VSConf1; /* CRTC 0x36 */ ! unsigned char VSConf2; /* CRTC 0x37 */ ! unsigned char HorOverflow; /* CRTC 0x3F */ ! unsigned char StateControl; /* TS 0x06 */ ! unsigned char AuxillaryMode; /* TS 0x07 */ ! unsigned char Misc; /* ATC 0x16 */ ! unsigned char SegSel1, SegSel2; /* 0x3CD, 0x3CB */ ! unsigned char ET6KMemBase; /* ET6000 0x13 -- linear memory mapped address */ ! unsigned char ET6KMMAPCtrl; /* ET6000 0x40 -- used for linear memory mapping */ ! unsigned char ET6KPerfContr; /* ET6000 0x41 -- system performance control */ ! unsigned char ET6KRasCas; /* ET6000 0x44 -- ram delays configuration */ ! unsigned char ET6KDispFeat; /* ET6000 0x46 -- display feature register */ ! unsigned char ET6KVidCtrl1; /* ET6000 0x58 -- used for 15/16 bpp modes */ ! unsigned char MClkM, MClkN; /* memory clock values */ ! unsigned char IMAPortCtrl; /* IMA port control register (0x217B index 0xF7) */ GenDACstate gendac; ! unsigned char ATTdac_cmd; /* command register for ATT 49x DACs */ } vgaET4000Rec, *vgaET4000Ptr; extern vgaVideoChipRec ET4000; *************** *** 73,85 **** --- 69,94 ---- TYPE_ET4000W32Pc, TYPE_ET4000W32Pd, TYPE_ET6000, + TYPE_ET6100, TYPE_ET6300 } t_tseng_type; + #define Is_W32_any ( (et4000_type >= TYPE_ET4000W32) && (et4000_type < TYPE_ET6000) ) + #define Is_ET6K ( et4000_type >= TYPE_ET6000 ) + #define Is_W32 ( (et4000_type >= TYPE_ET4000W32) && (et4000_type < TYPE_ET4000W32I) ) + #define Is_W32i ( (et4000_type >= TYPE_ET4000W32I) && (et4000_type < TYPE_ET4000W32P) ) + #define Is_W32_W32i ( (et4000_type >= TYPE_ET4000W32) && (et4000_type < TYPE_ET4000W32P) ) + #define Is_W32p ( (et4000_type >= TYPE_ET4000W32P) && (et4000_type < TYPE_ET6000) ) + #define Is_W32p_ab ( (et4000_type >= TYPE_ET4000W32P) && (et4000_type <= TYPE_ET4000W32Pb) ) + #define Is_W32p_cd ( (et4000_type >= TYPE_ET4000W32Pc) && (et4000_type <= TYPE_ET4000W32Pd) ) + #define Is_W32p_up ( et4000_type >= TYPE_ET4000W32P ) + + extern t_tseng_type et4000_type; extern unsigned char tseng_save_divide; /* saves state of hibit */ extern unsigned long ET6Kbase; + extern int tseng_bytesperpixel; extern SymTabRec TsengDacTable[]; *************** *** 94,118 **** ATT20C491_DAC, ATT20C492_DAC, ICS5341_DAC, ! GENDAC_DAC, STG1700_DAC, STG1702_DAC, STG1703_DAC, ET6000_DAC, CH8398_DAC, ! ET6300_DAC } t_ramdactype; extern t_ramdactype TsengRamdacType; ! extern void Check_Tseng_Ramdac(); #define DAC_IS_ATT49x ( (TsengRamdacType == ATT20C490_DAC) \ || (TsengRamdacType == ATT20C491_DAC) \ || (TsengRamdacType == ATT20C492_DAC) \ ! || (TsengRamdacType == ATT20C493_DAC) ) #define CHIP_SUPPORTS_LINEAR (et4000_type >= TYPE_ET4000W32I) #define BUS_ISA 0 #define BUS_MCA 1 #define BUS_VLB 2 --- 103,166 ---- ATT20C491_DAC, ATT20C492_DAC, ICS5341_DAC, ! ICS5301_DAC, STG1700_DAC, STG1702_DAC, STG1703_DAC, ET6000_DAC, CH8398_DAC, ! MUSIC4910_DAC } t_ramdactype; extern t_ramdactype TsengRamdacType; ! void Check_Tseng_Ramdac(void); ! void tseng_init_clockscale(void); ! void TsengHideCursor(void); #define DAC_IS_ATT49x ( (TsengRamdacType == ATT20C490_DAC) \ || (TsengRamdacType == ATT20C491_DAC) \ || (TsengRamdacType == ATT20C492_DAC) \ ! || (TsengRamdacType == ATT20C493_DAC) \ ! || (TsengRamdacType == MUSIC4910_DAC) ) + #define DAC_is_GenDAC ( (TsengRamdacType == ICS5341_DAC) \ + || (TsengRamdacType == ICS5301_DAC) ) + + #define DAC_is_STG170x ( (TsengRamdacType == STG1700_DAC) \ + || (TsengRamdacType == STG1702_DAC) \ + || (TsengRamdacType == STG1703_DAC) ) + #define CHIP_SUPPORTS_LINEAR (et4000_type >= TYPE_ET4000W32I) + #define Gendac_programmable_clock \ + ( (OFLG_ISSET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions)) && \ + ( (OFLG_ISSET(CLOCK_OPTION_ICS5341, &vga256InfoRec.clockOptions)) \ + || (OFLG_ISSET(CLOCK_OPTION_ICS5301, &vga256InfoRec.clockOptions)) \ + ) \ + ) + + #define STG170x_programmable_clock \ + ( (OFLG_ISSET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions)) && \ + (OFLG_ISSET(CLOCK_OPTION_STG1703, &vga256InfoRec.clockOptions)) \ + ) + + #define ICD2061a_programmable_clock \ + ( (OFLG_ISSET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions)) && \ + (OFLG_ISSET(CLOCK_OPTION_ICD2061A, &vga256InfoRec.clockOptions)) \ + ) + + #define CH8398_programmable_clock \ + ( (OFLG_ISSET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions)) && \ + (OFLG_ISSET(CLOCK_OPTION_CH8398, &vga256InfoRec.clockOptions)) \ + ) + + #define ET6000_programmable_clock \ + ( (OFLG_ISSET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions)) && \ + (OFLG_ISSET(CLOCK_OPTION_ET6000, &vga256InfoRec.clockOptions)) \ + ) + + + extern int Tseng_bus; #define BUS_ISA 0 #define BUS_MCA 1 #define BUS_VLB 2 *************** *** 126,142 **** /* pixel multiplexing variables */ extern Bool Tseng_pixMuxPossible; extern int Tseng_nonMuxMaxClock; - extern int Tseng_pixMuxMinClock; extern int Tseng_pixMuxMinWidth; Bool Tseng_ET4000ClockSelect(int no); Bool Tseng_LegendClockSelect(int no); Bool Tseng_ET6000ClockSelect(int freq); ! Bool Tseng_ICS5341ClockSelect(int freq); Bool Tseng_STG1703ClockSelect(int freq); Bool Tseng_ICD2061AClockSelect(int freq); ! void tseng_set_dacspeed(int bytesperpixel); ! void tseng_validate_mode(DisplayModePtr mode, int bytesperpixel, Bool verbose); ! void tseng_set_ramdac_bpp(DisplayModePtr mode, vgaET4000Ptr tseng_regs, int bytesperpixel); ! #endif --- 174,192 ---- /* pixel multiplexing variables */ extern Bool Tseng_pixMuxPossible; extern int Tseng_nonMuxMaxClock; extern int Tseng_pixMuxMinWidth; Bool Tseng_ET4000ClockSelect(int no); Bool Tseng_LegendClockSelect(int no); Bool Tseng_ET6000ClockSelect(int freq); ! Bool Tseng_GenDACClockSelect(int freq); Bool Tseng_STG1703ClockSelect(int freq); Bool Tseng_ICD2061AClockSelect(int freq); ! void tseng_set_dacspeed(void); ! void tseng_validate_mode(DisplayModePtr mode, Bool verbose); ! void tseng_set_ramdac_bpp(DisplayModePtr mode, vgaET4000Ptr tseng_regs); ! #ifdef DPMSExtension ! void TsengCrtcDPMSSet(int Mode); ! void TsengHVSyncDPMSSet(int Mode); ! #endif #endif *** ./xfree86/vga256/drivers/et4000/tseng_acl.c@@/PUBLIC-LATEST Sun Aug 10 13:05:20 1997 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/et4000/tseng_acl.c Fri Mar 6 16:49:44 1998 *************** *** 1,12 **** ! /* $TOG: tseng_acl.c /main/2 1997/08/10 13:03:56 kaleb $ */ - /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/et4000/tseng_acl.c,v 3.6.2.8 1997/07/26 06:30:52 dawes Exp $ */ #include "misc.h" #include "xf86.h" - #include "xf86_OSlib.h" #include "tseng.h" #include "tseng_acl.h" --- 1,12 ---- ! /* $TOG: tseng_acl.c /main/3 1998/03/06 16:51:22 kaleb $ */ + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/et4000/tseng_acl.c,v 3.6.2.11 1998/02/01 19:06:24 robin Exp $ */ + #include "misc.h" #include "xf86.h" #include "tseng.h" #include "tseng_acl.h" *************** *** 20,25 **** --- 20,26 ---- ByteP ACL_SUSPEND_TERMINATE, ACL_OPERATION_STATE, ACL_SYNC_ENABLE, + ACL_WRITE_INTERFACE_VALID, ACL_INTERRUPT_MASK, ACL_INTERRUPT_STATUS, ACL_ACCELERATOR_STATUS; *************** *** 46,51 **** --- 47,53 ---- WordP ACL_X_COUNT, ACL_Y_COUNT; + LongP ACL_XY_COUNT; /* for combined writes to X and Y count registers */ ByteP ACL_ROUTING_CONTROL, ACL_RELOAD_CONTROL, *************** *** 98,103 **** --- 100,124 ---- 0xff /* Xset 1 */ }; + int W32OpTable_planemask[] = { + 0x0a, /* Xclear 0 */ + 0x8a, /* Xand src AND dst */ + 0x4a, /* XandReverse src AND NOT dst */ + 0xca, /* Xcopy src */ + 0x2a, /* XandInverted NOT src AND dst */ + 0xaa, /* Xnoop dst */ + 0x6a, /* Xxor src XOR dst */ + 0xea, /* Xor src OR dst */ + 0x1a, /* Xnor NOT src AND NOT dst */ + 0x9a, /* Xequiv NOT src XOR dst */ + 0x5a, /* Xinvert NOT dst */ + 0xda, /* XorReverse src OR NOT dst */ + 0x3a, /* XcopyInverted NOT src */ + 0xba, /* XorInverted NOT src OR dst */ + 0x7a, /* Xnand NOT src OR NOT dst */ + 0xfa /* Xset 1 */ + }; + int W32PatternOpTable[] = { 0x00, /* Xclear 0 */ 0xa0, /* Xand pat AND dst */ *************** *** 148,158 **** LongP MemW32PatternPong; LongP MemW32Mix; /* ping-ponging the MIX map is done by XAA */ ! LongP CPU2ACLBase; ! long scratchVidBase; /* will be initialized in the Probe */ /**********************************************************************/ void tseng_terminate_acl() --- 169,211 ---- LongP MemW32PatternPong; LongP MemW32Mix; /* ping-ponging the MIX map is done by XAA */ ! LongP tsengCPU2ACLBase; ! long tsengScratchVidBase; /* will be initialized in the Probe */ ! int tsengImageWriteBase=0; /* ImageWritebuffer adress -- initialized in the Probe() */ + int tseng_powerPerPixel, tseng_neg_x_pixel_offset; + int tseng_line_width; + Bool tseng_need_wait_acl = FALSE; + /* scanline buffers for ImageWrite and WriteBitmap (and scanline color expansion in the future) */ + CARD32 *tsengFirstLinePntr, *tsengSecondLinePntr; + CARD32 tsengFirstLine, tsengSecondLine; + + /* + * Avoid re-initializing stuff that should not be when the server is + * restored after a console switch or a server reset (e.g. XAA interface)\ + */ + static int tsengAccelGeneration = -1; + + /* used for optimisation of direction-register writing */ + int tseng_old_dir=-1; + int old_x = 0, old_y = 0; + + /* These will hold the ping-pong registers. + * Note that ping-pong registers might not be needed when using + * BACKGROUND_OPERATIONS (because of the WAIT()-ing involved) + */ + + LongP tsengMemFg; + long tsengFg; + + LongP tsengMemBg; + long tsengBg; + + LongP tsengMemPat; + long tsengPat; + /**********************************************************************/ void tseng_terminate_acl() *************** *** 170,175 **** --- 223,243 ---- } } + void tseng_recover_timeout() + { + if (!Is_ET6K) + { + *tsengCPU2ACLBase = 0L; /* try unlocking the bus when CPU-to-accel gets stuck */ + } + + if (Is_W32p) /* flush the accelerator pipeline */ + { + *ACL_SUSPEND_TERMINATE = 0x00; + *ACL_SUSPEND_TERMINATE = 0x02; + *ACL_SUSPEND_TERMINATE = 0x00; + } + } + void tseng_init_acl() { long MMioBase, scratchMemBase; *************** *** 178,194 **** * prepare some shortcuts for faster access to memory mapped registers */ ! if (OFLG_ISSET(OPTION_LINEAR, &vga256InfoRec.options)) { MMioBase = (long)vgaLinearBase + 0x3FFF00; ! scratchMemBase = (long)vgaLinearBase + scratchVidBase; /* ! * we won't be using CPU2ACLBase in linear memory mode anyway, since * using the MMU apertures restricts the amount of useable video memory * to only 2MB, supposing we ONLY redirect MMU aperture 2 to the CPU. * (see data book W32p, page 207) */ ! CPU2ACLBase = (LongP) ((long)vgaLinearBase + 0x300000); /* MMU aperture 2 */ } else { --- 246,262 ---- * prepare some shortcuts for faster access to memory mapped registers */ ! if (ET4000.ChipUseLinearAddressing) { MMioBase = (long)vgaLinearBase + 0x3FFF00; ! scratchMemBase = (long)vgaLinearBase + tsengScratchVidBase; /* ! * we won't be using tsengCPU2ACLBase in linear memory mode anyway, since * using the MMU apertures restricts the amount of useable video memory * to only 2MB, supposing we ONLY redirect MMU aperture 2 to the CPU. * (see data book W32p, page 207) */ ! tsengCPU2ACLBase = (LongP) ((long)vgaLinearBase + 0x200000); /* MMU aperture 2 */ } else { *************** *** 197,209 **** * for the scratchpad (i.e. colors and scanline-colorexpand buffers) * we'll use the MMU aperture 0, which we'll make point at the last 1 * KB of video memory. */ scratchMemBase = (long)vgaBase + 0x18000L; ! *((LongP) (MMioBase + 0x00)) = scratchVidBase; /* ! * CPU2ACLBase is used for CPUtoSCreen...() operations on < ET6000 devices */ ! CPU2ACLBase = (LongP)((long)vgaBase + 0x1C000L); /* MMU aperture 2 */ } /* ErrorF("MMioBase = 0x%x, scratchMemBase = 0x%x\n", MMioBase, scratchMemBase);*/ --- 265,280 ---- * for the scratchpad (i.e. colors and scanline-colorexpand buffers) * we'll use the MMU aperture 0, which we'll make point at the last 1 * KB of video memory. + * + * MMU 1 is used for the Imagewrite buffer. */ scratchMemBase = (long)vgaBase + 0x18000L; ! *((LongP) (MMioBase + 0x00)) = tsengScratchVidBase; ! *((LongP) (MMioBase + 0x04)) = tsengImageWriteBase; /* ! * tsengCPU2ACLBase is used for CPUtoSCreen...() operations on < ET6000 devices */ ! tsengCPU2ACLBase = (LongP)((long)vgaBase + 0x1C000L); /* MMU aperture 2 */ } /* ErrorF("MMioBase = 0x%x, scratchMemBase = 0x%x\n", MMioBase, scratchMemBase);*/ *************** *** 216,221 **** --- 287,293 ---- ACL_SYNC_ENABLE = (ByteP) (MMioBase + 0x32); /* for ET6000, ACL_SYNC_ENABLE becomes ACL_6K_CONFIG */ + ACL_WRITE_INTERFACE_VALID = (ByteP) (MMioBase + 0x33); ACL_INTERRUPT_MASK = (ByteP) (MMioBase + 0x34); ACL_INTERRUPT_STATUS = (ByteP) (MMioBase + 0x35); ACL_ACCELERATOR_STATUS = (ByteP) (MMioBase + 0x36); *************** *** 247,257 **** ACL_PATTERN_WRAP = (ByteP) (MMioBase + 0x90); ! ACL_TRANSFER_DISABLE = (ByteP) (MMioBase + 0x91); /* ET6000 only */ ACL_SOURCE_WRAP = (ByteP) (MMioBase + 0x92); ACL_X_COUNT = (WordP) (MMioBase + 0x98); ACL_Y_COUNT = (WordP) (MMioBase + 0x9A); ACL_ROUTING_CONTROL = (ByteP) (MMioBase + 0x9C); /* for ET6000, ACL_ROUTING_CONTROL becomes ACL_MIX_CONTROL */ --- 319,330 ---- ACL_PATTERN_WRAP = (ByteP) (MMioBase + 0x90); ! ACL_TRANSFER_DISABLE = (ByteP) (MMioBase + 0x91); /* ET6000 only */ ACL_SOURCE_WRAP = (ByteP) (MMioBase + 0x92); ACL_X_COUNT = (WordP) (MMioBase + 0x98); ACL_Y_COUNT = (WordP) (MMioBase + 0x9A); + ACL_XY_COUNT = (LongP) (ACL_X_COUNT); /* shortcut. not a real register */ ACL_ROUTING_CONTROL = (ByteP) (MMioBase + 0x9C); /* for ET6000, ACL_ROUTING_CONTROL becomes ACL_MIX_CONTROL */ *************** *** 278,293 **** ACL_SECONDARY_DELTA_MAJOR = (WordP) (MMioBase + 0xB6); /* addresses in video memory (i.e. "0" = first byte in video memory) */ ! W32ForegroundPing = scratchVidBase + 0; ! W32ForegroundPong = scratchVidBase + 8; ! W32BackgroundPing = scratchVidBase + 16; ! W32BackgroundPong = scratchVidBase + 24; ! W32PatternPing = scratchVidBase + 32; ! W32PatternPong = scratchVidBase + 40; ! W32Mix = scratchVidBase + 48; /* addresses in the memory map */ MemW32ForegroundPing = (LongP) (scratchMemBase + 0); --- 351,366 ---- ACL_SECONDARY_DELTA_MAJOR = (WordP) (MMioBase + 0xB6); /* addresses in video memory (i.e. "0" = first byte in video memory) */ ! W32ForegroundPing = tsengScratchVidBase + 0; ! W32ForegroundPong = tsengScratchVidBase + 8; ! W32BackgroundPing = tsengScratchVidBase + 16; ! W32BackgroundPong = tsengScratchVidBase + 24; ! W32PatternPing = tsengScratchVidBase + 32; ! W32PatternPong = tsengScratchVidBase + 40; ! W32Mix = tsengScratchVidBase + 48; /* addresses in the memory map */ MemW32ForegroundPing = (LongP) (scratchMemBase + 0); *************** *** 312,331 **** *ACL_INTERRUPT_STATUS = 0x0; *ACL_ACCELERATOR_STATUS = 0x0; ! if (et4000_type >= TYPE_ET6000) { ! *ACL_STEPPING_INHIBIT = 0x0; /* let all maps (Src, Dst, Mix, Pat) step */ ! *ACL_6K_CONFIG = 0x00; /* maximum performance -- what did you think? */ *ACL_POWER_CONTROL = 0x01; /* conserve power when ACL is idle */ *ACL_TRANSFER_DISABLE = 0x00; /* Undefined at power-on, enable all transfers */ } else /* W32i/W32p */ { *ACL_RELOAD_CONTROL = 0x0; ! *ACL_SYNC_ENABLE = 0x1; } ! if (et4000_type < TYPE_ET4000W32P) /* W32i */ { /* X, Y positions set to zero's for w32 and w32i */ *ACL_X_POSITION = 0; --- 385,415 ---- *ACL_INTERRUPT_STATUS = 0x0; *ACL_ACCELERATOR_STATUS = 0x0; ! if (Is_ET6K) { ! *ACL_STEPPING_INHIBIT = 0x0; /* Undefined at power-on, let all maps (Src, Dst, Mix, Pat) step */ ! *ACL_6K_CONFIG = 0x00; /* maximum performance -- what did you think? */ *ACL_POWER_CONTROL = 0x01; /* conserve power when ACL is idle */ + *ACL_MIX_CONTROL = 0x33; *ACL_TRANSFER_DISABLE = 0x00; /* Undefined at power-on, enable all transfers */ } else /* W32i/W32p */ { *ACL_RELOAD_CONTROL = 0x0; ! *ACL_SYNC_ENABLE = 0x1; /* | 0x2 = 0WS ACL read. Yields up to 10% faster operation for small blits */ ! *ACL_ROUTING_CONTROL = 0x00; } ! if (Is_W32p_up) ! { ! /* Enable the W32p startup bit and set use an eight-bit pixel depth */ ! *ACL_NQ_X_POSITION = 0; ! *ACL_NQ_Y_POSITION = 0; ! *ACL_PIXEL_DEPTH = (vgaBitsPerPixel - 8) << 1; ! /* writing destination address will start ACL */ ! *ACL_OPERATION_STATE = 0x10; ! } ! else { /* X, Y positions set to zero's for w32 and w32i */ *ACL_X_POSITION = 0; *************** *** 335,374 **** * this will need to be made dynamic (i.e. moved to Setup() * functions) */ ! *ACL_VIRTUAL_BUS_SIZE = 0x00; } ! else /* w32p and ET6000 */ ! { ! /* Enable the W32p startup bit and set use an eight-bit pixel depth */ ! *ACL_NQ_X_POSITION = 0; ! *ACL_NQ_Y_POSITION = 0; ! *ACL_PIXEL_DEPTH = (vgaBitsPerPixel - 8) << 1; ! /* writing destination address will start ACL */ ! *ACL_OPERATION_STATE = 0x10; ! } ! *ACL_DESTINATION_Y_OFFSET = vga256InfoRec.displayWidth * (vgaBitsPerPixel / 8) - 1; *ACL_XY_DIRECTION = 0; *MMU_CONTROL = 0x74; ! if ((et4000_type < TYPE_ET6000) && (et4000_type > TYPE_ET4000W32I) ! && OFLG_ISSET(OPTION_LINEAR, &vga256InfoRec.options)) /* W32p */ { /* * Since the w32p revs C and D don't have any memory mapped when the * accelerator registers are used it is necessary to use the MMUs to * provide a semblance of linear memory. Fortunately on these chips ! * the MMU appertures are 1 megabyte each. So as long as we are willing ! * to only use 3 megs of video memory we can have some acceleration. ! * If we ever get the CPU-to-screen-color-expansion stuff working then ! * we will only be able to use 2 megs since MMU 2 will be used for ! * that. * ! * MBP2 is hardwired to 0x200000 on when linear memory mode is enabled, ! * except on rev a (where it is programmable). */ ! *((LongP) (MMioBase + 0x00)) = 0x0L; ! *((LongP) (MMioBase + 0x04)) = 0x100000; } /* --- 419,464 ---- * this will need to be made dynamic (i.e. moved to Setup() * functions) */ ! *ACL_VIRTUAL_BUS_SIZE = 0x00; /* VBS = 1 byte is faster than VBS = 4 bytes, since ! the ACL can start processing as ! soon as the first byte arrives */ } ! *ACL_DESTINATION_Y_OFFSET = vga256InfoRec.displayWidth * tseng_bytesperpixel - 1; *ACL_XY_DIRECTION = 0; *MMU_CONTROL = 0x74; ! if (Is_W32p && ET4000.ChipUseLinearAddressing) { /* * Since the w32p revs C and D don't have any memory mapped when the * accelerator registers are used it is necessary to use the MMUs to * provide a semblance of linear memory. Fortunately on these chips ! * the MMU appertures are 1 megabyte each. So as long as we are ! * willing to only use 3 megs of video memory we can have some ! * acceleration. If we ever get the CPU-to-screen-color-expansion ! * stuff working then we will NOT need to sacrifice the extra 1MB ! * provided by MBP2, because we could do dynamic switching of the APT ! * bit in the MMU control register. * ! * On W32p rev c and d MBP2 is hardwired to 0x200000 when linear ! * memory mode is enabled. (On rev a it is programmable). ! * ! * W32p rev a and b have their first 2M mapped in the normal (non-MMU) ! * way, and MMU0 and MMU1, each 512 kb wide, can be used to access ! * another 1MB of memory. This totals to 3MB of mem. available in ! * linear memory when the accelerator is enabled. */ ! if (Is_W32p_ab) ! { ! *((LongP) (MMioBase + 0x00)) = 0x200000L; ! *((LongP) (MMioBase + 0x04)) = 0x280000L; ! } ! else /* rev C & D */ ! { ! *((LongP) (MMioBase + 0x00)) = 0x0L; ! *((LongP) (MMioBase + 0x04)) = 0x100000L; ! } } /* *************** *** 375,382 **** * Initialize the XAA data structures. This should be done in * ET4000FbInit(), but that is called _before_ this tseng_init_acl(), * and it relies on variables that are only setup here. */ ! TsengAccelInit(); } --- 465,493 ---- * Initialize the XAA data structures. This should be done in * ET4000FbInit(), but that is called _before_ this tseng_init_acl(), * and it relies on variables that are only setup here. + * + * This kludge has one major disadvantage: it would result in + * TsengAccelInit() being called upon each and every pass through the + * hardware init. This would cause e.g. the xf86AccelInfoRec.Flags to be + * reset to their initial value each time, and that in turn would + * override any overrides put in place by the XAA init code (which is + * only called once). If XAA decided to disable the PIXMAP_CACHE flag, + * then a server reset or a console switch would cause TsengAccelInit to + * set the flags again, and cause havoc (XAA would start using the + * pixmap cache without it being initialized). + * + * This would not happen if TsengAccelInit were called in the proper + * place (ET4000FbInit). + * + * That's why we need to fiddle with Generations here... */ ! if (tsengAccelGeneration != serverGeneration) { ! TsengAccelInit(); ! } ! tsengAccelGeneration = serverGeneration; } + + + *** ./xfree86/vga256/drivers/et4000/tseng_acl.h@@/PUBLIC-LATEST Sun Aug 10 13:05:25 1997 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/et4000/tseng_acl.h Fri Mar 6 16:49:48 1998 *************** *** 1,16 **** ! /* $TOG: tseng_acl.h /main/2 1997/08/10 13:04:01 kaleb $ */ - /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/et4000/tseng_acl.h,v 3.5.2.4 1997/07/26 06:30:53 dawes Exp $ */ #ifndef _TSENG_ACL_H #define _TSENG_ACL_H typedef volatile unsigned char *ByteP; typedef volatile unsigned short *WordP; typedef volatile unsigned *LongP; /* * Shortcuts to Tseng memory-mapped accelerator-control registers */ --- 1,32 ---- ! /* $TOG: tseng_acl.h /main/3 1998/03/06 16:51:26 kaleb $ */ + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/et4000/tseng_acl.h,v 3.5.2.8 1998/02/01 19:44:24 robin Exp $ */ + #ifndef _TSENG_ACL_H #define _TSENG_ACL_H + #include "compiler.h" + + /* + * if NO_OPTIMIZE is set, some optimizations are disabled. + * + * What it basically tries to do is minimize the amounts of writes to + * accelerator registers, since these are the ones that slow down small + * operations a lot. + */ + + #undef NO_OPTIMIZE + + typedef volatile unsigned char *ByteP; typedef volatile unsigned short *WordP; typedef volatile unsigned *LongP; + void tseng_recover_timeout(); + /* * Shortcuts to Tseng memory-mapped accelerator-control registers */ *************** *** 23,28 **** --- 39,45 ---- ByteP ACL_SUSPEND_TERMINATE, ACL_OPERATION_STATE, ACL_SYNC_ENABLE, + ACL_WRITE_INTERFACE_VALID, ACL_INTERRUPT_MASK, ACL_INTERRUPT_STATUS, ACL_ACCELERATOR_STATUS; *************** *** 64,69 **** --- 81,87 ---- extern WordP ACL_X_COUNT, ACL_Y_COUNT; + LongP ACL_XY_COUNT; /* for combined writes to X and Y count registers */ extern *************** *** 98,111 **** WordP ACL_SECONDARY_ERROR_TERM, ACL_SECONDARY_DELTA_MINOR, ACL_SECONDARY_DELTA_MAJOR; ByteP ACL_TRANSFER_DISABLE; extern int W32OpTable[16]; extern int W32PatternOpTable[16]; - extern int W32BresTable[8]; extern long W32ForegroundPing; extern long W32ForegroundPong; extern long W32BackgroundPing; --- 116,137 ---- WordP ACL_SECONDARY_ERROR_TERM, ACL_SECONDARY_DELTA_MINOR, ACL_SECONDARY_DELTA_MAJOR; + extern ByteP ACL_TRANSFER_DISABLE; + /* + * Some data structures for faster accelerator programming. + */ extern int W32OpTable[16]; + extern int W32OpTable_planemask[16]; extern int W32PatternOpTable[16]; extern int W32BresTable[8]; + /* + * The ping-pong registers. Probably too much hassle for too little gain. "TODO". + */ + extern long W32ForegroundPing; extern long W32ForegroundPong; extern long W32BackgroundPing; *************** *** 122,178 **** extern LongP MemW32PatternPong; extern LongP MemW32Mix; /* ping-ponging the MIX map is done by XAA */ ! extern LongP CPU2ACLBase; ! extern long scratchVidBase; ! extern Bool Use_Pci_Retry; /* Often checked value */ ! /******************************************************************************/ ! #define WAIT_QUEUE \ ! {while (*(volatile unsigned char *)ACL_ACCELERATOR_STATUS & 0x1);} ! #define WAIT_QUEUE_VERBOSE \ ! { int cnt=0; while (*(volatile unsigned char *)ACL_ACCELERATOR_STATUS & 0x1) cnt++; ErrorF("Q%d ",cnt);} ! #define MAX_WAIT_CNT 500000 ! #define WAIT_ACL_VERBOSE DO_WAIT_ACL(ErrorF("W%d ",MAX_WAIT_CNT - cnt)) ! #define WAIT_ACL DO_WAIT_ACL( {} ) ! #define DO_WAIT_ACL(command) \ ! { int cnt = MAX_WAIT_CNT; \ ! while (*(volatile unsigned char *)ACL_ACCELERATOR_STATUS & 0x2) \ ! if (--cnt < 0) \ ! { \ ! if (et4000_type < TYPE_ET6000) \ ! { \ ! *CPU2ACLBase = 0L; /* try unlocking the bus when CPU-to-accel gets stuck */ \ ! FLUSH_ACL \ ! } \ ! ErrorF("WAIT_ACL: timeout.\n"); \ ! break; \ ! } \ ! command; \ ! } ! ! #define WAIT_XY \ ! {while (*(volatile unsigned char *)ACL_ACCELERATOR_STATUS & 0x4);} - #define FLUSH_ACL \ - if (et4000_type > TYPE_ET4000W32I) \ - { \ - *ACL_SUSPEND_TERMINATE = 0x00; \ - *ACL_SUSPEND_TERMINATE = 0x02; \ - *ACL_SUSPEND_TERMINATE = 0x00; \ - } /***********************************************************************/ void tseng_init_acl(); - #endif --- 148,294 ---- extern LongP MemW32PatternPong; extern LongP MemW32Mix; /* ping-ponging the MIX map is done by XAA */ ! /* ! * Some exported variables used by several source files. They are all ! * prepended with "tseng" to avoid name clashes with other modules. ! */ ! extern LongP tsengCPU2ACLBase; ! extern long tsengScratchVidBase; ! extern int tsengImageWriteBase; ! extern int tseng_powerPerPixel; ! extern int tseng_neg_x_pixel_offset; ! extern int tseng_line_width; ! extern Bool tseng_need_wait_acl; ! extern Bool tseng_use_PCI_Retry; /* Do we use PCI-retry or busy-waiting */ ! /* for ImageWrite and WriteBitmap */ ! extern CARD32 *tsengFirstLinePntr, *tsengSecondLinePntr; ! extern CARD32 tsengFirstLine, tsengSecondLine; ! /* ! * These will hold the ping-pong registers. ! */ ! extern LongP tsengMemFg; ! extern long tsengFg; ! extern LongP tsengMemBg; ! extern long tsengBg; ! extern LongP tsengMemPat; ! extern long tsengPat; ! ! /* for register write optimisation */ ! extern int old_x, old_y; ! extern int tseng_old_dir; ! ! ! /* ! * Some shortcuts. ! */ ! ! #define MAX_WAIT_CNT 500000 /* how long we wait before we time out */ ! #undef WAIT_VERBOSE /* if defined: print out how long we waited */ ! ! static __inline__ void tseng_wait(reg,name,mask) ! ByteP reg; ! char* name; ! unsigned char mask; ! { ! int cnt = MAX_WAIT_CNT; ! while (*reg & mask) ! if (--cnt < 0) ! { ! ErrorF("WAIT_%s: timeout.\n",name); ! tseng_recover_timeout(); ! break; ! } ! #ifdef WAIT_VERBOSE ! ErrorF("%s%d ",name,MAX_WAIT_CNT-cnt); ! #endif ! } ! ! #define WAIT_QUEUE tseng_wait(ACL_ACCELERATOR_STATUS, "QUEUE", 0x1) ! ! /* This is only for W32p rev b...d*/ ! #define WAIT_INTERFACE tseng_wait(ACL_WRITE_INTERFACE_VALID, "INTERFACE", 0xf) ! ! #define WAIT_ACL tseng_wait(ACL_ACCELERATOR_STATUS, "ACL", 0x2) ! #define WAIT_XY tseng_wait(ACL_ACCELERATOR_STATUS, "XY", 0x4) + #define SET_FUNCTION_BLT \ + if (Is_ET6K) \ + *ACL_MIX_CONTROL = 0x33; \ + else \ + *ACL_ROUTING_CONTROL = 0x00; + #define SET_FUNCTION_BLT_TR \ + *ACL_MIX_CONTROL = 0x13; + + #define FBADDR(x,y) ( (y) * tseng_line_width + MULBPP(x) ) + + #define SET_FG_ROP(rop) \ + *ACL_FOREGROUND_RASTER_OPERATION = W32OpTable[rop]; + + #define SET_FG_ROP_PLANEMASK(rop) \ + *ACL_FOREGROUND_RASTER_OPERATION = W32OpTable_planemask[rop]; + + #define SET_BG_ROP(rop) \ + *ACL_BACKGROUND_RASTER_OPERATION = W32PatternOpTable[rop]; + + #define SET_BG_ROP_TR(rop, bg_color) \ + if ((bg_color) == -1) /* transparent color expansion */ \ + *ACL_BACKGROUND_RASTER_OPERATION = 0xaa; \ + else \ + *ACL_BACKGROUND_RASTER_OPERATION = W32PatternOpTable[rop]; + + #define SET_DELTA(Min, Maj) \ + *((LongP) ACL_DELTA_MINOR) = ((Maj) << 16) + (Min) + + #define SET_SECONDARY_DELTA(Min, Maj) \ + *((LongP) ACL_SECONDARY_DELTA_MINOR) = ((Maj) << 16) + (Min) + + #ifdef NO_OPTIMIZE + #define SET_XYDIR(dir) \ + *ACL_XY_DIRECTION = (dir); + #else + /* + * only changing ACL_XY_DIRECTION when it needs to be changed avoids + * unnecessary PCI bus writes, which are slow. This shows up very well + * on consecutive small fills. + */ + #define SET_XYDIR(dir) \ + if ((dir) != tseng_old_dir) \ + *ACL_XY_DIRECTION = tseng_old_dir = (dir); + #endif + + #define SET_SECONDARY_XYDIR(dir) \ + *ACL_SECONDARY_EDGE = (dir); + + + /* Must do 0x09 (in one operation) for the W32 */ + #define START_ACL(dst) \ + *(ACL_DESTINATION_ADDRESS) = dst; \ + if (et4000_type < TYPE_ET4000W32P) *ACL_OPERATION_STATE = 0x09; + + /* START_ACL for the ET6000 */ + #define START_ACL_6(dst) \ + *(ACL_DESTINATION_ADDRESS) = dst; + + #define START_ACL_CPU(dst) \ + if (et4000_type < TYPE_ET4000W32P) \ + *tsengCPU2ACLBase = dst; \ + else \ + *(ACL_DESTINATION_ADDRESS) = dst; + + /***********************************************************************/ void tseng_init_acl(); #endif *** ./xfree86/vga256/drivers/et4000/tseng_clock.c@@/PUBLIC-LATEST Sat Jul 19 16:05:37 1997 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/et4000/tseng_clock.c Fri Mar 6 16:49:52 1998 *************** *** 1,9 **** ! /* $TOG: tseng_clock.c /main/1 1997/07/19 16:05:39 kaleb $ */ - /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/et4000/tseng_clock.c,v 3.3.2.2 1997/05/09 13:49:47 hohndel Exp $ */ /* * * Copyright 1993-1997 The XFree86 Project, Inc. --- 1,10 ---- ! /* $TOG: tseng_clock.c /main/2 1998/03/06 16:51:30 kaleb $ */ + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/et4000/tseng_clock.c,v 3.3.2.4 1998/02/01 16:05:07 robin Exp $ */ + /* * * Copyright 1993-1997 The XFree86 Project, Inc. *************** *** 172,178 **** */ Bool ! Tseng_ICS5341ClockSelect(freq) int freq; { Bool result = TRUE; --- 173,179 ---- */ Bool ! Tseng_GenDACClockSelect(freq) int freq; { Bool result = TRUE; *** /dev/null Tue Jun 30 15:22:34 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/et4000/tseng_colexp.c Fri Mar 6 16:49:57 1998 *************** *** 0 **** --- 1,1469 ---- + /* $TOG: tseng_colexp.c /main/1 1998/03/06 16:51:35 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/et4000/tseng_colexp.c,v 1.1.2.3 1998/02/20 15:13:56 robin Exp $ */ + /* + * ET4/6K acceleration interface -- color expansion primitives. + * + * Uses Harm Hanemaayer's generic acceleration interface (XAA). + * + * Author: Koen Gadeyne + * + * Much of the acceleration code is based on the XF86_W32 server code from + * Glenn Lai. + * + * + * Color expansion capabilities of the Tseng chip families: + * + * Chip screen-to-screen CPU-to-screen Supported depths + * + * ET4000W32/W32i No Yes 8bpp only + * ET4000W32p Yes Yes 8bpp only + * ET6000 Yes No 8/16/24/32 bpp + */ + + #include "vga256.h" + #include "xf86.h" + #include "vga.h" + #include "tseng.h" + #include "tseng_acl.h" + #include "compiler.h" + + #include "xf86xaa.h" + + #include "tseng_colexp.h" + #include "tseng_inline.h" + + /* + * This is just for the messages. + */ + #include "xf86_Config.h" + + /* for color expansion via scanline buffer in system memory */ + #define COLEXP_BUF_SIZE 1024 + static CARD32 colexp_buf[COLEXP_BUF_SIZE / 4]; + + static void TsengSubsequentScanlineCPUToScreenColorExpand_1to2to16 (); + static void TsengSubsequentScanlineCPUToScreenColorExpand_1to4to32 (); + + + void + TsengAccelInit_Colexp () + { + + if (OFLG_ISSET(OPTION_XAA_NO_COL_EXP, &vga256InfoRec.options)) return; + if (et4000_type < TYPE_ET4000W32P) return; /* disable accelerated color expansion for W32/W32i until it's fixed */ + if (Is_W32p) return; /* disable for w32p as well, bug in drawing small pcs */ + + /* + * Screen-to-screen color expansion. + * + * Scanline-screen-to-screen color expansion is slower than + * CPU-to-screen color expansion. + */ + + xf86AccelInfoRec.ColorExpandFlags = + BIT_ORDER_IN_BYTE_LSBFIRST | + VIDEO_SOURCE_GRANULARITY_PIXEL | + NO_PLANEMASK; + + if (!Is_ET6K && (vgaBitsPerPixel != 24)) + { + /* fast 8bpp-only XAA replacements for text drawing and Bitmap writing */ + if ((vgaBitsPerPixel == 8) && (et4000_type > TYPE_ET4000W32Pa)) + { + xf86AccelInfoRec.WriteBitmap = W32WriteBitmap; + xf86AccelInfoRec.ImageTextTE = W32ImageTextTECPUToScreenColorExpand; + xf86AccelInfoRec.PolyTextTE = W32PolyTextTECPUToScreenColorExpand; + xf86AccelInfoRec.FillRectOpaqueStippled = TsengScanlineCPUToScreenFillStippledRect; + xf86AccelInfoRec.FillRectStippled = TsengScanlineCPUToScreenFillStippledRect; + ErrorF ("%s %s: XAA/Tseng: Using ET4000W32-specific Color-expansion (WriteBitmap, Image/PolyTextTE, FillRect(Opaque)Stippled).\n", + XCONFIG_PROBED, vga256InfoRec.name); + } + + /* + * We'll use an intermediate memory buffer and fake + * scanline-screen-to-screen color expansion, because the XAA + * CPU-to-screen color expansion causes the accelerator to hang. + * Reason unkown (yet). This also allows us to do 16 and 32 bpp color + * expansion by first doubling the bitmap pattern before + * color-expanding it, because W32s can only do 8bpp color expansion. + * + * XAA doesn't support scanline-CPU-to-SCreen color expansion yet. + */ + + #if 0 + if (vgaBitsPerPixel == 24) + xf86AccelInfoRec.ColorExpandFlags |= TRIPLE_BITS_24BPP; + #endif + + xf86AccelInfoRec.PingPongBuffers = 1; + xf86AccelInfoRec.ScratchBufferSize = COLEXP_BUF_SIZE / tseng_bytesperpixel; + xf86AccelInfoRec.ScratchBufferAddr = 1; /* any non-zero value will do -- not used */ + xf86AccelInfoRec.ScratchBufferBase = (void *) colexp_buf; + + xf86AccelInfoRec.SetupForScanlineScreenToScreenColorExpand = + TsengSetupForScanlineCPUToScreenColorExpand; + + xf86AccelInfoRec.SubsequentScanlineScreenToScreenColorExpand = + TsengSubsequentScanlineCPUToScreenColorExpand; + } + + if (Is_ET6K || (Is_W32p && (vgaBitsPerPixel == 8))) + { + xf86AccelInfoRec.SetupForScreenToScreenColorExpand = + TsengSetupForScreenToScreenColorExpand; + xf86AccelInfoRec.SubsequentScreenToScreenColorExpand = + TsengSubsequentScreenToScreenColorExpand; + } + + if (Is_ET6K) + { + if (tsengImageWriteBase) /* uses the same buffer memory as ImageWrite */ + { + xf86AccelInfoRec.WriteBitmap = ET6KWriteBitmap; + xf86AccelInfoRec.FillRectOpaqueStippled = TsengScanlineScreenToScreenFillStippledRect; + xf86AccelInfoRec.FillRectStippled = TsengScanlineScreenToScreenFillStippledRect; + ErrorF ("%s %s: XAA/Tseng: Using ET6000-specific Color-expansion (WriteBitmap, FillRect(Opaque)Stippled).\n", + XCONFIG_PROBED, vga256InfoRec.name); + } + + xf86AccelInfoRec.SetupForScanlineScreenToScreenColorExpand = + TsengSetupForScanlineScreenToScreenColorExpand; + + xf86AccelInfoRec.SubsequentScanlineScreenToScreenColorExpand = + TsengSubsequentScanlineScreenToScreenColorExpand; + + /* triple-buffering is needed to account for double-buffering of Tseng + * acceleration registers. Increasing this number doesn't help solve the + * problems with both ET4000W32 and ET6000 with text rendering. + */ + xf86AccelInfoRec.PingPongBuffers = 3; + + xf86AccelInfoRec.ScratchBufferSize = tsengScratchVidBase + 1024 - (long) W32Mix; + xf86AccelInfoRec.ScratchBufferAddr = W32Mix; + + if (!ET4000.ChipUseLinearAddressing) + { + /* in banked mode, use aperture #0 */ + xf86AccelInfoRec.ScratchBufferBase = + (unsigned char *) + (((int) vgaBase) + 0x18000L + 1024 - xf86AccelInfoRec.ScratchBufferSize); + } + } + #if 0 + ErrorF ("ColorExpand ScratchBuf: Addr = %d (0x%x); Size = %d (0x%x); Base = %d (0x%x)\n", + xf86AccelInfoRec.ScratchBufferAddr, xf86AccelInfoRec.ScratchBufferAddr, + xf86AccelInfoRec.ScratchBufferSize, xf86AccelInfoRec.ScratchBufferSize, + xf86AccelInfoRec.ScratchBufferBase, xf86AccelInfoRec.ScratchBufferBase); + #endif + + #if TSENG_CPU_TO_SCREEN_COLOREXPAND + /* + * CPU-to-screen color expansion doesn't seem to be reliable yet. The + * W32 needs the correct amount of data sent to it in this mode, or it + * hangs the machine until is does (?). Currently, the init code in this + * file or the XAA code that uses this does something wrong, so that + * occasionally we get accelerator timeouts, and after a few, complete + * system hangs. + * + * The W32 engine requires SCANLINE_NO_PAD, but that doesn't seem to + * work very well (accelerator hangs). + * + * What works is this: tell XAA that we have SCANLINE_PAD_DWORD, and then + * add the following code in TsengSubsequentCPUToScreenColorExpand(): + * w = (w + 31) & ~31; this code rounds the width up to the nearest + * multiple of 32, and together with SCANLINE_PAD_DWORD, this makes + * CPU-to-screen color expansion work. Of course, the display isn't + * correct (4 chars are "blanked out" when only one is written, for + * example). But this shows that the principle works. But the code + * doesn't... + * + * The same thing goes for PAD_BYTE: this also works (with the same + * problems as SCANLINE_PAD_DWORD, although less prominent) + */ + if (Is_W32_any && (vgaBitsPerPixel == 8)) + { + /* + * CPU_TRANSFER_PAD_DWORD is implied by XAA, and I'm not sure this is + * OK, because the W32 might be trying to expand the padding data. + */ + xf86AccelInfoRec.ColorExpandFlags |= + SCANLINE_NO_PAD | CPU_TRANSFER_PAD_DWORD; + + xf86AccelInfoRec.SetupForCPUToScreenColorExpand = + TsengSetupForCPUToScreenColorExpand; + xf86AccelInfoRec.SubsequentCPUToScreenColorExpand = + TsengSubsequentCPUToScreenColorExpand; + + /* we'll be using MMU aperture 2 */ + xf86AccelInfoRec.CPUToScreenColorExpandBase = tsengCPU2ACLBase; + /* ErrorF("tsengCPU2ACLBase = 0x%x\n", tsengCPU2ACLBase); */ + /* aperture size is 8kb in banked mode. Larger in linear mode, but 8kb is enough */ + xf86AccelInfoRec.CPUToScreenColorExpandRange = 8192; + } + #endif + } + + + #define SET_FUNCTION_COLOREXPAND \ + if (Is_ET6K) \ + *ACL_MIX_CONTROL = 0x32; \ + else \ + *ACL_ROUTING_CONTROL = 0x08; + + #define SET_FUNCTION_COLOREXPAND_CPU \ + *ACL_ROUTING_CONTROL = 0x02; + + + + static int ColorExpandDst; + static int colexp_width; + static int colexp_slot = 0; /* slot offset in ping-pong buffers */ + + + void + TsengSetupForScanlineScreenToScreenColorExpand (x, y, w, h, bg, fg, rop, planemask) + int x, y; + int w, h; + int bg, fg; + int rop; + unsigned int planemask; + { + colexp_width = w; /* only needed for 1-to-2-to-16 color expansion */ + + ColorExpandDst = FBADDR (x, y); + + TsengSetupForScreenToScreenColorExpand (bg, fg, rop, planemask); + + *ACL_MIX_Y_OFFSET = 0x0FFF; /* see remark below */ + + SET_XY (w, 1); + } + + void + TsengSubsequentScanlineScreenToScreenColorExpand (srcaddr) + int srcaddr; + { + /* COP_FRAMEBUFFER_CONCURRENCY can cause text corruption !!! + + * Looks like some scanline data DWORDS are not written to the ping-pong + * framebuffers, so that old data is rendered in some places. Is this + * caused by PCI host bridge queueing? Or is data lost when written + * while the accelerator is accessing the framebuffer (which would be + * the real reason NOT to use COP_FRAMEBUFFER_CONCURRENCY)? + * + * Even with ping-ponging, parts of scanline three (which are supposed + * to be written to the old, already rendered scanline 1 buffer) have + * not yet arrived in the framebuffer, and thus some parts of the new + * scanline are rendered with data from two lines above it. + * + * Extra problem: ET6000 queueing really needs triple buffering for + * this, because XAA can still overwrite scanline 1 when writing data + * for scanline three. Right _after_ that, the accelerator blocks on + * queueing in TsengSubsequentScanlineScreenToScreenColorExpand(), but + * then it's too late: the scanline data is already overwritten. That's + * why we use 3 ping-pong buffers. + * + * "x11perf -fitext" is about 530k chars/sec now, but with + * COP_FRAMEBUFFER_CONCURRENCY, this goes up to >700k (which is similar + * to what Xinside can do). + * + * Needs to be investigated! + * + * Update: this seems to depend upon ACL_MIX_Y_OFFSET, although that + * register should not do anything at all here (only one line done at a + * time, so no Y_OFFSET needed). Setting the offset to 0x0FFF seems to + * remedy this situation most of the time (still an occasional error + * here and there). This _could_ be a bug, but then it would have to be + * in both in the ET6000 _and_ the ET4000W32p. + * + * The more delay added after starting a color-expansion operation, the + * less font corruption we get. But nothing really solves it. + */ + + wait_acl_queue (); + + *ACL_MIX_ADDRESS = srcaddr; + START_ACL (ColorExpandDst); + + /* move to next scanline */ + ColorExpandDst += tseng_line_width; + + /* + * If not using triple-buffering, we need to wait for the queued + * register set to be transferred to the working register set here, + * because otherwise an e.g. double-buffering mechanism could overwrite + * the buffer that's currently being worked with with new data too soon. + * + * WAIT_QUEUE; // not needed with triple-buffering + */ + } + + + /* + * We use this intermediate CPU-to-Screen color expansion because the one + * provided by XAA seems to lock up the accelerator engine. + */ + + static int colexp_width_dwords; + + void + TsengSetupForScanlineCPUToScreenColorExpand (x, y, w, h, bg, fg, rop, planemask) + int x, y; + int w, h; + int bg, fg; + int rop; + unsigned int planemask; + { + /* the accelerator needs DWORD padding, and "w" is in PIXELS... */ + colexp_width_dwords = (MULBPP (w) + 31) >> 5; + /* ErrorF("w=%d;d=%d ", w, colexp_width_dwords); */ + + ColorExpandDst = FBADDR (x, y); + + TsengSetupForCPUToScreenColorExpand (bg, fg, rop, planemask); + + /* *ACL_MIX_Y_OFFSET = w-1; */ + + SET_XY (w, 1); + } + + void + TsengSubsequentScanlineCPUToScreenColorExpand (srcaddr) + int srcaddr; + { + int i; + CARD8* src=(CARD8*)colexp_buf; + CARD8* dst=(CARD8*)tsengCPU2ACLBase; + + wait_acl_queue (); + + START_ACL (ColorExpandDst); + + switch (vgaBitsPerPixel) + { + case 8: + case 24: /* assumes TRIPLE_BITS_24BPP */ + /* Copy scanline data to accelerator MMU aperture */ + if (et4000_type < TYPE_ET4000W32P) + for (i=0; i<(colexp_width_dwords*4); i++) + *dst++ = *src++; + else + MoveDWORDS (tsengCPU2ACLBase, colexp_buf, colexp_width_dwords); + break; + case 16: + /* expand the color expand data to 2 bits per pixel before copying it to the MMU aperture */ + TsengSubsequentScanlineCPUToScreenColorExpand_1to2to16 (colexp_buf); + break; + case 32: + TsengSubsequentScanlineCPUToScreenColorExpand_1to4to32 (colexp_buf); + break; + } + + /* move to next scanline */ + ColorExpandDst += tseng_line_width; + } + + /* + * This function does direct memory-to-CPU bit doubling for color-expansion + * at 16bpp on W32 chips. They can only do 8bpp color expansion, so we have + * to expand the incoming data to 2bpp first. + */ + + static void + TsengSubsequentScanlineCPUToScreenColorExpand_1to2to16 (src) + CARD32 *src; + { + CARD32 *dest = (CARD32 *) tsengCPU2ACLBase; + int i; + CARD16 ind, *bufptr; + CARD32 r; + + i = colexp_width_dwords; /* amount of blocks of 16 bits to expand to 32 bits (=1 DWORD) */ + bufptr = (CARD16 *) (src); + + while (i--) + { + r = 0; + ind = *bufptr++; + + if (ind & 0x0001) r |= 0x00000003; + if (ind & 0x0002) r |= 0x0000000C; + if (ind & 0x0004) r |= 0x00000030; + if (ind & 0x0008) r |= 0x000000C0; + if (ind & 0x0010) r |= 0x00000300; + if (ind & 0x0020) r |= 0x00000C00; + if (ind & 0x0040) r |= 0x00003000; + if (ind & 0x0080) r |= 0x0000C000; + + if (ind & 0x0100) r |= 0x00030000; + if (ind & 0x0200) r |= 0x000C0000; + if (ind & 0x0400) r |= 0x00300000; + if (ind & 0x0800) r |= 0x00C00000; + if (ind & 0x1000) r |= 0x03000000; + if (ind & 0x2000) r |= 0x0C000000; + if (ind & 0x4000) r |= 0x30000000; + if (ind & 0x8000) r |= 0xC0000000; + + *dest++ = r; + } + } + + /* + * This function does direct memory-to-CPU bit doubling for color-expansion + * at 32bpp on W32 chips. They can only do 8bpp color expansion, so we have + * to expand the incoming data to 4bpp first. + */ + + static void + TsengSubsequentScanlineCPUToScreenColorExpand_1to4to32 (src) + CARD32 *src; + { + CARD32 *dest = (CARD32 *) tsengCPU2ACLBase; + int i; + CARD8 ind, *bufptr; + CARD32 r; + + i = colexp_width_dwords; /* amount of blocks of 8 bits to expand to 32 bits (=1 DWORD) */ + bufptr = (CARD8 *) (src); + + while (i--) + { + r = 0; + ind = *bufptr++; + + if (ind & 0x0001) r |= 0x0000000F; + if (ind & 0x0002) r |= 0x000000F0; + if (ind & 0x0004) r |= 0x00000F00; + if (ind & 0x0008) r |= 0x0000F000; + if (ind & 0x0010) r |= 0x000F0000; + if (ind & 0x0020) r |= 0x00F00000; + if (ind & 0x0040) r |= 0x0F000000; + if (ind & 0x0080) r |= 0xF0000000; + + *dest++ = r; + } + } + + /* + * CPU-to-Screen color expansion. + * This is for ET4000 only (The ET6000 cannot do this) + */ + + void + TsengSetupForCPUToScreenColorExpand (bg, fg, rop, planemask) + int bg, fg; + int rop; + unsigned int planemask; + { + /* ErrorF("X"); */ + + PINGPONG (); + + wait_acl_queue (); + + SET_FG_ROP (rop); + SET_BG_ROP_TR (rop, bg); + + SET_XYDIR (0); + + SET_FG_BG_COLOR (fg, bg); + + SET_FUNCTION_COLOREXPAND_CPU; + + /* assure correct alignment of MIX address (ACL needs same alignment here as in MMU aperture) */ + *ACL_MIX_ADDRESS = 0; + } + + + /* + * TsengSubsequentCPUToScreenColorExpand() is potentially dangerous: + * Not writing enough data to the MMU aperture for CPU-to-screen color + * expansion will eventually cause a system deadlock! + * + * Note that CPUToScreenColorExpand operations _always_ require a + * WAIT_INTERFACE before starting a new operation (this is empyrical, + * though) + */ + + void + TsengSubsequentCPUToScreenColorExpand (x, y, w, h, skipleft) + int x, y; + int w, h; + int skipleft; + { + int destaddr = FBADDR (x, y); + + /* ErrorF(" %dx%d|%d ",w,h,skipleft); */ + if (skipleft) + ErrorF ("Can't do: Skipleft = %d\n", skipleft); + + /* wait_acl_queue(); */ + WAIT_ACL; + + *ACL_MIX_Y_OFFSET = w - 1; + SET_XY (w, h); + START_ACL (destaddr); + } + + void + TsengSetupForScreenToScreenColorExpand (bg, fg, rop, planemask) + int bg, fg; + int rop; + unsigned int planemask; + { + /* ErrorF("SSC "); */ + + PINGPONG (); + + wait_acl_queue (); + + SET_FG_ROP (rop); + SET_BG_ROP_TR (rop, bg); + + SET_FG_BG_COLOR (fg, bg); + + SET_FUNCTION_COLOREXPAND; + + SET_XYDIR (0); + } + + void + TsengSubsequentScreenToScreenColorExpand (srcx, srcy, x, y, w, h) + int srcx, srcy; + int x, y; + int w, h; + { + int destaddr = FBADDR (x, y); + + int mixaddr = FBADDR (srcx, srcy * 8); + + wait_acl_queue (); + + SET_XY (w, h); + *ACL_MIX_ADDRESS = mixaddr; + *ACL_MIX_Y_OFFSET = w - 1; + + START_ACL (destaddr); + } + + /* + * Below are XAA replacements for some commonly used functions. Some are + * there because XAA doesn't support the Tseng hardware, some are there + * because we think we can do it faster than XAA... + */ + + /* + * WriteBitmap() code. Largely written by Mark Vojkovich. + * + * This should really use triple-buffering as does the standard scanline + * color expansion XAA code. Now the excessive Syncing causes it to drag a + * little. Still, it beats drawing bitmaps through scanline-color expansion: + * copyplane500 : 493 (up from 365) + * copyplane100 : 4440 (up from 2880) + * copyplane10 : 31900 (up from 24600) + * + * The main advantage here is that alignment problems are handled by the + * accelerator instead of the XAA code (= the CPU). + */ + + void + ET6KWriteBitmap (x, y, w, h, src, srcwidth, srcx, srcy, + bg, fg, rop, planemask) + int x, y, w, h; + unsigned char *src; + int srcwidth; + int srcx, srcy; + int bg, fg; + int rop; + unsigned int planemask; + { + unsigned char *srcp; /* pointer to src */ + Bool PlusOne = (h & 0x01); + int dwords; + + TsengSetupForScanlineScreenToScreenColorExpand (x, y, w, h, bg, fg, rop, planemask); + + h >>= 1; /* h now represents line pairs */ + + /* calculate the src pointer to the nearest dword boundary */ + srcp = (srcwidth * srcy) + (srcx >> 5) + src; + srcx &= 31; /* srcx now contains the skipleft parameter */ + + dwords = (w + 31 + srcx) >> 5; + + while (h--) + { + /* WAIT_ACL; */ + /* write the first line */ + MoveDWORDS (tsengFirstLinePntr, (CARD32 *) srcp, dwords); + /* blit it */ + WAIT_QUEUE; + TsengSubsequentScanlineScreenToScreenColorExpand ((tsengFirstLine << 3) + srcx); + srcp += srcwidth; + /* write the second line */ + MoveDWORDS (tsengSecondLinePntr, (CARD32 *) srcp, dwords); + /* blit it */ + WAIT_QUEUE; + TsengSubsequentScanlineScreenToScreenColorExpand ((tsengSecondLine << 3) + srcx); + srcp += srcwidth; + } + + if (PlusOne) + { + /* WAIT_ACL; */ + /* write the first line */ + MoveDWORDS (tsengFirstLinePntr, (CARD32 *) srcp, dwords); + /* blit it */ + WAIT_QUEUE; + TsengSubsequentScanlineScreenToScreenColorExpand ((tsengFirstLine << 3) + srcx); + } + + xf86AccelInfoRec.Sync(); + } + + + + /* when defined, use faster (but less generic) ACL CPU-to-screen Subsequent setup code */ + #define USE_FAST_ACLINIT 1 + + + void + W32WriteBitmap (x, y, w, h, src, srcwidth, srcx, + srcy, bg, fg, rop, planemask) + int x, y, w, h; + unsigned char *src; + int srcwidth; + int srcx, srcy; + int bg, fg; + int rop; + unsigned int planemask; + { + unsigned char *srcp = (srcwidth * srcy) + (srcx >> 3) + src; + int dwords = (w + 31) >> 5; + register int shift = srcx & 0x07; + int destaddr; + + TsengSetupForCPUToScreenColorExpand (bg, fg, rop, planemask); + + #ifdef USE_FAST_ACLINIT + /* + * this is a replacement for the TsengSubsequentCPUToScreenColorExpand() + * function, but optimized for this application. + */ + destaddr = FBADDR (x, y); + + SET_XY (w, 1); + #endif + + if (shift) + { + int count; + register CARD32 *destptr; + register CARD32 *srcptr; + while (h--) + { + count = dwords; + srcptr = (CARD32 *) srcp; + destptr = (CARD32 *) tsengCPU2ACLBase; + #ifdef USE_FAST_ACLINIT + WAIT_ACL; + START_ACL (destaddr); + destaddr += tseng_line_width; + #else + TsengSubsequentCPUToScreenColorExpand (x, y++, w, 1, 0); + #endif + while (count--) + { + *(destptr++) = (srcptr[0] >> shift) | + (srcptr[1] << (32 - shift)); + srcptr++; + } + srcp += srcwidth; + } + } + else + { + while (h--) + { + #ifdef USE_FAST_ACLINIT + WAIT_ACL; + START_ACL (destaddr); + destaddr += tseng_line_width; + #else + TsengSubsequentCPUToScreenColorExpand (x, y++, w, 1, 0); + #endif + MoveDWORDS (tsengCPU2ACLBase, (CARD32 *) srcp, dwords); + srcp += srcwidth; + } + } + + xf86AccelInfoRec.Sync(); + } + + + + /* + * Fast W32 8bpp TE ImageText and PolyText rendering code, using + * CPU-to-screen color expansion. This draws one scanline at a time. + * Author: Mark Vojkovich. + */ + + + #include "xf86expblt.h" + + #define MAX_GLYPHS 1024 /* that's gotta be enough */ + static unsigned int *Glyphs[MAX_GLYPHS]; + + void + W32ImageTextTECPUToScreenColorExpand (pDrawable, pGC, xInit, yInit, + nglyph, ppci, pglyphBase) + DrawablePtr pDrawable; + GC *pGC; + int xInit, yInit; + int nglyph; + CharInfoPtr *ppci; /* array of character info */ + unsigned char *pglyphBase; /* start of array of glyphs */ + { + int w, h, x, y; + int glyphWidth, count; + int destaddr; + + glyphWidth = FONTMAXBOUNDS (pGC->font, characterWidth); + + /* + * Check for non-standard glyphs, glyphs that are too wide. + */ + if ((GLYPHWIDTHBYTESPADDED (*ppci) != 4) || glyphWidth > 32) + { + xf86GCInfoRec.ImageGlyphBltFallBack ( + pDrawable, pGC, xInit, yInit, nglyph, ppci, pglyphBase); + return; + } + + h = FONTASCENT (pGC->font) + FONTDESCENT (pGC->font); + if (!(h && glyphWidth)) + return; + + TsengSetupForCPUToScreenColorExpand ( + pGC->bgPixel, pGC->fgPixel, GXcopy, pGC->planemask); + + x = xInit + FONTMAXBOUNDS (pGC->font, leftSideBearing) + pDrawable->x; + y = yInit - FONTASCENT (pGC->font) + pDrawable->y; + w = nglyph * glyphWidth; + + #ifdef USE_FAST_ACLINIT + /* + * this is a replacement for the TsengSubsequentCPUToScreenColorExpand() + * function, but optimized for this application. + */ + destaddr = FBADDR (x, y); + + SET_XY (w, 1); + #endif + + for (count = 0; count < nglyph; count++) + Glyphs[count] = (unsigned int *) FONTGLYPHBITS (pglyphBase, *ppci++); + + + for (count = 0; count < h; count++, y++) + { + #ifdef USE_FAST_ACLINIT + WAIT_ACL; + START_ACL (destaddr); + destaddr += tseng_line_width; + #else + TsengSubsequentCPUToScreenColorExpand (x, y, w, 1, 0); + #endif + xf86DrawTextScanline ((unsigned int *) tsengCPU2ACLBase, + Glyphs, count, nglyph, glyphWidth); + } + + xf86AccelInfoRec.Sync(); + } + + void + W32PolyTextTECPUToScreenColorExpand (pDrawable, pGC, xInit, yInit, + nglyph, ppci, pglyphBase) + DrawablePtr pDrawable; + GC *pGC; + int xInit, yInit; + int nglyph; + CharInfoPtr *ppci; /* array of character info */ + unsigned char *pglyphBase; /* start of array of glyphs */ + { + int w, h, x, y; + int glyphWidth, count; + int destaddr; + + glyphWidth = FONTMAXBOUNDS (pGC->font, characterWidth); + + /* + * Check for non-standard glyphs, glyphs that are too wide. + */ + if ((GLYPHWIDTHBYTESPADDED (*ppci) != 4) || glyphWidth > 32) + { + xf86GCInfoRec.PolyGlyphBltFallBack ( + pDrawable, pGC, xInit, yInit, nglyph, ppci, pglyphBase); + return; + } + + h = FONTASCENT (pGC->font) + FONTDESCENT (pGC->font); + if (!(h && glyphWidth)) + return; + + TsengSetupForCPUToScreenColorExpand ( + -1, pGC->fgPixel, pGC->alu, pGC->planemask); + + x = xInit + FONTMAXBOUNDS (pGC->font, leftSideBearing) + pDrawable->x; + y = yInit - FONTASCENT (pGC->font) + pDrawable->y; + w = nglyph * glyphWidth; + + #ifdef USE_FAST_ACLINIT + /* + * this is a replacement for the TsengSubsequentCPUToScreenColorExpand() + * function, but optimized for this application. + */ + destaddr = FBADDR (x, y); + + SET_XY (w, 1); + #endif + + for (count = 0; count < nglyph; count++) + Glyphs[count] = (unsigned int *) FONTGLYPHBITS (pglyphBase, *ppci++); + + for (count = 0; count < h; count++, y++) + { + #ifdef USE_FAST_ACLINIT + WAIT_ACL; + START_ACL (destaddr); + destaddr += tseng_line_width; + #else + TsengSubsequentCPUToScreenColorExpand (x, y, w, 1, 0); + #endif + xf86DrawTextScanline ((unsigned int *) tsengCPU2ACLBase, + Glyphs, count, nglyph, glyphWidth); + } + + xf86AccelInfoRec.Sync(); + } + + + /* + * Stipple acceleration code. + */ + + /* shiftmasks for stipple acceleration */ + static CARD32 ShiftMasks[32] = + { + 0x00000000, 0x00000001, 0x00000003, 0x00000007, + 0x0000000f, 0x0000001f, 0x0000003f, 0x0000007f, + 0x000000ff, 0x000001ff, 0x000003ff, 0x000007ff, + 0x00000fff, 0x00001fff, 0x00003fff, 0x00007fff, + 0x0000ffff, 0x0001ffff, 0x0003ffff, 0x0007ffff, + 0x000fffff, 0x001fffff, 0x003fffff, 0x007fffff, + 0x00ffffff, 0x01ffffff, 0x03ffffff, 0x07ffffff, + 0x0fffffff, 0x1fffffff, 0x3fffffff, 0x7fffffff}; + + + + /* + The TsengFillStippledRect function can replace: + + xf86AccelInfoRec.FillRectOpaqueStippled + & + xf86AccelInfoRec.FillRectStippled + + + This function will probably be less satisfying since it will + rarely be used. In general, scanline expansions are only used + when a bitmap won't fit in the cache, either because it's just + too big or because video memory is low. For the most part, + the other options are preferred to the scanline expansion + (blit from pixmap cache, 8x8 pattern fills). + + This code is based on stuff I wrote for the S3. I was + unhappy with the performance of the XAA stipple fallbacks in + cases where the pixmap cache couldn't be used. It DOESN'T + use a skipleft parameter. All performance gains over XAA + come from breaking up the code to handle 3 cases of stipple + widths: powers of two <= 32, other less than 32, and larger + stipple widths. + + As for x11perf: + + srect, osrect - + + These guys are 32x32 stipples reduceable to 8x8. It would + be good to establish a hierarchy between the 8x8 pattern fills, + blitting from the pixmap cache, and the expansion routines. + This function would only be used if there isn't enough room + for the pixmap cache (or it's turned off), or if you specify + DO_NOT_CACHE_STIPPLES. + + oddsrect, oddosrect - + + A 17x15 stipple. Will only use this function if there's + not enough room (need 15 lines) in the pixmap cache or with + DO_NOT_CACHE_STIPPLES. + + bigsrect, bigosrect - + + This function will always be used, since the pixmap cache + is never large enough to hold these stipples. Conceivably + I could make a skipleft version for the bigger stipples, but I + haven't yet. + + + In general the ones that are used the least is where my + version of this code has the biggest advantage over XAA, + so I generally only think of this as a way to keep performance + from sucking when there's not enough room for the pixmap cache. + + [ kmg ] + Do we really need those shiftmasks? + + ShiftMasks[i] = (1 << i) - 1; + + This is really a very simple operation, probably even faster than indexing + in an array -- and certainly a lot more cache-friendly (it's in-place) + + */ + + static void + SetDWORDS (dest, value, dwords) + register CARD32 *dest; + register CARD32 value; + register int dwords; + { + while (dwords & ~0x03) + { + dest[0] = dest[1] = dest[2] = dest[3] = value; + dest += 4; + dwords -= 4; + } + switch (dwords) + { + case 1: + dest[0] = value; + break; + case 2: + dest[0] = dest[1] = value; + break; + case 3: + dest[0] = dest[1] = dest[2] = value; + break; + } + } + + + + /* this function attaches to those 2 xf86AccelInfoRec pointers. + This function calls that previous function I posted */ + + void + TsengScanlineScreenToScreenFillStippledRect (pDrawable, pGC, nBoxInit, pBoxInit) + DrawablePtr pDrawable; + GCPtr pGC; + int nBoxInit; /* number of rectangles to fill */ + BoxPtr pBoxInit; /* Pointer to first rectangle to fill */ + { + PixmapPtr pPixmap; /* Pixmap of the area to draw */ + int rectWidth; /* Width of the rect to be drawn */ + int rectHeight; /* Height of the rect to be drawn */ + BoxPtr pBox; /* current rectangle to fill */ + int nBox; /* Number of rectangles to fill */ + int xoffset, yoffset; + Bool AlreadySetup = FALSE; + + pPixmap = pGC->stipple; + + for (nBox = nBoxInit, pBox = pBoxInit; nBox > 0; nBox--, pBox++) + { + + + rectWidth = pBox->x2 - pBox->x1; + rectHeight = pBox->y2 - pBox->y1; + + if ((rectWidth > 0) && (rectHeight > 0)) + { + if (!AlreadySetup) + { + TsengSetupForScreenToScreenColorExpand ( + (pGC->fillStyle == FillStippled) ? -1 : pGC->bgPixel, + pGC->fgPixel, pGC->alu, pGC->planemask); + + AlreadySetup = TRUE; + } + + xoffset = (pBox->x1 - (pGC->patOrg.x + pDrawable->x)) + % pPixmap->drawable.width; + if (xoffset < 0) + xoffset += pPixmap->drawable.width; + yoffset = (pBox->y1 - (pGC->patOrg.y + pDrawable->y)) + % pPixmap->drawable.height; + if (yoffset < 0) + yoffset += pPixmap->drawable.height; + TsengSubsequentScanlineScreenToScreenFillStippledRect ( + pBox->x1, pBox->y1, rectWidth, rectHeight, + pPixmap->devPrivate.ptr, pPixmap->devKind, + pPixmap->drawable.width, pPixmap->drawable.height, + xoffset, yoffset); + } + } /* end for loop through each rectangle to draw */ + xf86AccelInfoRec.Sync(); + } + + + void + TsengSubsequentScanlineScreenToScreenFillStippledRect (x, y, w, h, src, srcwidth, + stipplewidth, stippleheight, srcx, srcy) + int x, y, w, h; + unsigned char *src; + int srcwidth; + int stipplewidth, stippleheight; + int srcx, srcy; + { + unsigned char *srcp; + int dwords = (w + 31) >> 5; + int line = 0; + + /* setup x/y/w in the ACL engine */ + ColorExpandDst = FBADDR (x, y); + *ACL_MIX_Y_OFFSET = 0x0FFF; + SET_XY (w, 1); + + srcp = (srcwidth * srcy) + src; + + if (!((stipplewidth > 32) || (stipplewidth & (stipplewidth - 1)))) + { + CARD32 pattern; + register unsigned char *kludge = (unsigned char *) (&pattern); + + while (h--) + { + switch (stipplewidth) + { + case 32: + pattern = *((CARD32 *) srcp); + break; + case 16: + kludge[0] = kludge[2] = srcp[0]; + kludge[1] = kludge[3] = srcp[1]; + break; + case 8: + kludge[0] = kludge[1] = kludge[2] = kludge[3] = srcp[0]; + break; + case 4: + kludge[0] = kludge[1] = kludge[2] = kludge[3] = + (srcp[0] & 0x0F); + pattern |= (pattern << 4); + break; + case 2: + kludge[0] = kludge[1] = kludge[2] = kludge[3] = + (srcp[0] & 0x03); + pattern |= (pattern << 2); + pattern |= (pattern << 4); + break; + default: /* case 1: */ + if (srcp[0] & 0x01) + pattern = 0xffffffff; + else + pattern = 0x00000000; + break; + } + + if (srcx) + pattern = (pattern >> srcx) | (pattern << (32 - srcx)); + + if (line & 0x01) + { + SetDWORDS (tsengFirstLinePntr, pattern, dwords); + TsengSubsequentScanlineScreenToScreenColorExpand (tsengFirstLine << 3); + } + else + { + WAIT_ACL; + SetDWORDS (tsengSecondLinePntr, pattern, dwords); + TsengSubsequentScanlineScreenToScreenColorExpand (tsengSecondLine << 3); + } + line++; + srcy++; + srcp += srcwidth; + if (srcy >= stippleheight) + { + srcy = 0; + srcp = src; + } + } + } + else if (stipplewidth < 32) + { + register int width, offset; + int count; + register CARD32 pattern; + register CARD32 *DestPntr; + + while (h--) + { + width = stipplewidth; + pattern = *((CARD32 *) srcp) & ShiftMasks[width]; + while (!(width & ~15)) + { + pattern |= (pattern << width); + width <<= 1; + } + pattern |= (pattern << width); + + offset = srcx; + count = dwords; + + if (line & 0x01) + { + DestPntr = tsengSecondLinePntr; + while (count--) + { + *DestPntr = (pattern >> offset) | + (pattern << (width - offset)); + DestPntr++; + offset += 32; + while (offset >= width) + offset -= width; + } + TsengSubsequentScanlineScreenToScreenColorExpand (tsengSecondLine << 3); + } + else + { + DestPntr = tsengFirstLinePntr; + WAIT_ACL; + while (count--) + { + *DestPntr = (pattern >> offset) | + (pattern << (width - offset)); + DestPntr++; + offset += 32; + while (offset >= width) + offset -= width; + } + TsengSubsequentScanlineScreenToScreenColorExpand (tsengFirstLine << 3); + } + line++; + + srcy++; + srcp += srcwidth; + if (srcy >= stippleheight) + { + srcy = 0; + srcp = src; + } + } + } + else + { + register CARD32 *scratch; + int shift, offset, scratch2, count; + register CARD32 *DestPntr; + + while (h--) + { + count = dwords; + offset = srcx; + + if (line & 0x01) + DestPntr = tsengSecondLinePntr; + else + { + DestPntr = tsengFirstLinePntr; + WAIT_ACL; + } + while (count--) + { + shift = stipplewidth - offset; + scratch = (CARD32 *) (srcp + (offset >> 3)); + scratch2 = offset & 0x07; + + if (shift & ~31) + { + if (scratch2) + { + *DestPntr = (*scratch >> scratch2) | + (scratch[1] << (32 - scratch2)); + } + else + *DestPntr = *scratch; + } + else + { + *DestPntr = (*((CARD32 *) srcp) << shift) | + ((*scratch >> scratch2) & ShiftMasks[shift]); + } + DestPntr++; + offset += 32; + while (offset >= stipplewidth) + offset -= stipplewidth; + } + if (line & 0x01) + TsengSubsequentScanlineScreenToScreenColorExpand (tsengSecondLine << 3); + else + TsengSubsequentScanlineScreenToScreenColorExpand (tsengFirstLine << 3); + + line++; + srcy++; + srcp += srcwidth; + if (srcy >= stippleheight) + { + srcy = 0; + srcp = src; + } + } + } + xf86AccelInfoRec.Sync(); + } + + + void + TsengScanlineCPUToScreenFillStippledRect (pDrawable, pGC, nBoxInit, pBoxInit) + DrawablePtr pDrawable; + GCPtr pGC; + int nBoxInit; /* number of rectangles to fill */ + BoxPtr pBoxInit; /* Pointer to first rectangle to fill */ + { + PixmapPtr pPixmap; /* Pixmap of the area to draw */ + int rectWidth; /* Width of the rect to be drawn */ + int rectHeight; /* Height of the rect to be drawn */ + BoxPtr pBox; /* current rectangle to fill */ + int nBox; /* Number of rectangles to fill */ + int xoffset, yoffset; + Bool AlreadySetup = FALSE; + + pPixmap = pGC->stipple; + + for (nBox = nBoxInit, pBox = pBoxInit; nBox > 0; nBox--, pBox++) + { + + + rectWidth = pBox->x2 - pBox->x1; + rectHeight = pBox->y2 - pBox->y1; + + if ((rectWidth > 0) && (rectHeight > 0)) + { + if (!AlreadySetup) + { + TsengSetupForCPUToScreenColorExpand ( + (pGC->fillStyle == FillStippled) ? -1 : pGC->bgPixel, + pGC->fgPixel, pGC->alu, pGC->planemask); + + AlreadySetup = TRUE; + } + + xoffset = (pBox->x1 - (pGC->patOrg.x + pDrawable->x)) + % pPixmap->drawable.width; + if (xoffset < 0) + xoffset += pPixmap->drawable.width; + yoffset = (pBox->y1 - (pGC->patOrg.y + pDrawable->y)) + % pPixmap->drawable.height; + if (yoffset < 0) + yoffset += pPixmap->drawable.height; + TsengSubsequentScanlineCPUToScreenFillStippledRect ( + pBox->x1, pBox->y1, rectWidth, rectHeight, + pPixmap->devPrivate.ptr, pPixmap->devKind, + pPixmap->drawable.width, pPixmap->drawable.height, + xoffset, yoffset); + } + } /* end for loop through each rectangle to draw */ + xf86AccelInfoRec.Sync(); + } + + + void + TsengSubsequentScanlineCPUToScreenFillStippledRect (x, y, w, h, src, srcwidth, + stipplewidth, stippleheight, srcx, srcy) + int x, y, w, h; + unsigned char *src; + int srcwidth; + int stipplewidth, stippleheight; + int srcx, srcy; + { + unsigned char *srcp; + int dwords = (w + 31) >> 5; + int destaddr; + + #ifdef USE_FAST_ACLINIT + /* + * this is a replacement for the TsengSubsequentCPUToScreenColorExpand() + * function, but optimized for this application. + */ + destaddr = FBADDR (x, y); + + SET_XY (w, 1); + #endif + + srcp = (srcwidth * srcy) + src; + + if (!((stipplewidth > 32) || (stipplewidth & (stipplewidth - 1)))) + { + CARD32 pattern; + register unsigned char *kludge = (unsigned char *) (&pattern); + + while (h--) + { + switch (stipplewidth) + { + case 32: + pattern = *((CARD32 *) srcp); + break; + case 16: + kludge[0] = kludge[2] = srcp[0]; + kludge[1] = kludge[3] = srcp[1]; + break; + case 8: + kludge[0] = kludge[1] = kludge[2] = kludge[3] = srcp[0]; + break; + case 4: + kludge[0] = kludge[1] = kludge[2] = kludge[3] = + (srcp[0] & 0x0F); + pattern |= (pattern << 4); + break; + case 2: + kludge[0] = kludge[1] = kludge[2] = kludge[3] = + (srcp[0] & 0x03); + pattern |= (pattern << 2); + pattern |= (pattern << 4); + break; + default: /* case 1: */ + if (srcp[0] & 0x01) + pattern = 0xffffffff; + else + pattern = 0x00000000; + break; + } + + if (srcx) + pattern = (pattern >> srcx) | (pattern << (32 - srcx)); + + #ifdef USE_FAST_ACLINIT + WAIT_ACL; + START_ACL (destaddr); + destaddr += tseng_line_width; + #else + TsengSubsequentCPUToScreenColorExpand (x, y++, w, 1, 0); + #endif + SetDWORDS (tsengCPU2ACLBase, pattern, dwords); + + srcy++; + srcp += srcwidth; + if (srcy >= stippleheight) + { + srcy = 0; + srcp = src; + } + } + } + else if (stipplewidth < 32) + { + register int width, offset; + int count; + register CARD32 pattern; + register CARD32 *DestPntr; + + while (h--) + { + width = stipplewidth; + pattern = *((CARD32 *) srcp) & ShiftMasks[width]; + while (!(width & ~15)) + { + pattern |= (pattern << width); + width <<= 1; + } + pattern |= (pattern << width); + + offset = srcx; + count = dwords; + + #ifdef USE_FAST_ACLINIT + WAIT_ACL; + START_ACL (destaddr); + destaddr += tseng_line_width; + #else + TsengSubsequentCPUToScreenColorExpand (x, y++, w, 1, 0); + #endif + DestPntr = (CARD32 *) tsengCPU2ACLBase; + while (count--) + { + *DestPntr = (pattern >> offset) | + (pattern << (width - offset)); + DestPntr++; + offset += 32; + while (offset >= width) + offset -= width; + } + + srcy++; + srcp += srcwidth; + if (srcy >= stippleheight) + { + srcy = 0; + srcp = src; + } + } + } + else + { + register CARD32 *scratch; + int shift, offset, scratch2, count; + register CARD32 *DestPntr; + + while (h--) + { + count = dwords; + offset = srcx; + + DestPntr = (CARD32 *) tsengCPU2ACLBase; + + #ifdef USE_FAST_ACLINIT + WAIT_ACL; + START_ACL (destaddr); + destaddr += tseng_line_width; + #else + TsengSubsequentCPUToScreenColorExpand (x, y++, w, 1, 0); + #endif + while (count--) + { + shift = stipplewidth - offset; + scratch = (CARD32 *) (srcp + (offset >> 3)); + scratch2 = offset & 0x07; + + if (shift & ~31) + { + if (scratch2) + { + *DestPntr = (*scratch >> scratch2) | + (scratch[1] << (32 - scratch2)); + } + else + *DestPntr = *scratch; + } + else + { + *DestPntr = (*((CARD32 *) srcp) << shift) | + ((*scratch >> scratch2) & ShiftMasks[shift]); + } + DestPntr++; + offset += 32; + while (offset >= stipplewidth) + offset -= stipplewidth; + } + + srcy++; + srcp += srcwidth; + if (srcy >= stippleheight) + { + srcy = 0; + srcp = src; + } + } + } + xf86AccelInfoRec.Sync(); + } *** /dev/null Tue Jun 30 15:22:36 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/et4000/tseng_colexp.h Fri Mar 6 16:50:03 1998 *************** *** 0 **** --- 1,109 ---- + /* $TOG: tseng_colexp.h /main/1 1998/03/06 16:51:40 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/et4000/tseng_colexp.h,v 1.1.2.1 1998/02/01 16:42:12 robin Exp $ */ + /* + * Tseng acceleration interface -- color expansion primitives. + */ + + #ifndef _TSENG_COLEXP_H + #define _TSENG_COLEXP_H + + extern void TsengSetupForScanlineScreenToScreenColorExpand( + int x, int y, + int w, int h, + int bg, int fg, + int rop, + unsigned int planemask); + + extern void TsengSubsequentScanlineScreenToScreenColorExpand( + int srcaddr); + + extern void TsengSetupForScanlineCPUToScreenColorExpand( + int x, int y, + int w, int h, + int bg, int fg, + int rop, + unsigned int planemask); + + extern void TsengSubsequentScanlineCPUToScreenColorExpand( + int srcaddr); + + extern void TsengSetupForCPUToScreenColorExpand( + int bg, int fg, + int rop, + unsigned int planemask); + + extern void TsengSubsequentCPUToScreenColorExpand( + int x, int y, + int w, int h, + int skipleft); + + extern void TsengSetupForScreenToScreenColorExpand( + int bg, int fg, + int rop, + unsigned int planemask); + + extern void TsengSubsequentScreenToScreenColorExpand( + int srcx, int srcy, + int x, int y, + int w, int h); + + extern void ET6KWriteBitmap( + int x, int y, int w, int h, + unsigned char *src, int srcwidth, + int srcx, int srcy, + int bg, int fg, int rop, + unsigned int planemask); + + extern void W32WriteBitmap( + int x, int y, int w, int h, + unsigned char *src, int srcwidth, + int srcx, int srcy, + int bg, int fg, int rop, + unsigned int planemask); + + extern void W32ImageTextTECPUToScreenColorExpand( + DrawablePtr pDrawable, + GC *pGC, + int xInit, int yInit, + int nglyph, + CharInfoPtr *ppci, + unsigned char *pglyphBase); + + extern void W32PolyTextTECPUToScreenColorExpand( + DrawablePtr pDrawable, + GC *pGC, + int xInit, int yInit, + int nglyph, + CharInfoPtr *ppci, + unsigned char *pglyphBase); + + extern void TsengScanlineScreenToScreenFillStippledRect( + DrawablePtr pDrawable, + GCPtr pGC, + int nBoxInit, + BoxPtr pBoxInit); + + extern void TsengSubsequentScanlineScreenToScreenFillStippledRect( + int x, int y, int w, int h, + unsigned char *src, + int srcwidth, + int stipplewidth, int stippleheight, + int srcx, int srcy); + + extern void TsengScanlineCPUToScreenFillStippledRect( + DrawablePtr pDrawable, + GCPtr pGC, + int nBoxInit, + BoxPtr pBoxInit); + + extern void TsengSubsequentScanlineCPUToScreenFillStippledRect( + int x, int y, int w, int h, + unsigned char *src, + int srcwidth, + int stipplewidth, int stippleheight, + int srcx, int srcy); + + #endif *** ./xfree86/vga256/drivers/et4000/tseng_cursor.c@@/PUBLIC-LATEST Sat Jul 19 16:05:42 1997 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/et4000/tseng_cursor.c Fri Mar 6 16:50:06 1998 *************** *** 1,9 **** ! /* $TOG: tseng_cursor.c /main/1 1997/07/19 16:05:43 kaleb $ */ - /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/et4000/tseng_cursor.c,v 1.6.2.4 1997/05/31 13:34:43 dawes Exp $ */ /* * Hardware cursor handling. Adapted mainly from apm/apm_cursor.c * and whatever piece of code in XFree86 that could provide me with --- 1,10 ---- ! /* $TOG: tseng_cursor.c /main/2 1998/03/06 16:51:44 kaleb $ */ + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/et4000/tseng_cursor.c,v 1.6.2.5 1998/02/01 16:05:07 robin Exp $ */ + /* * Hardware cursor handling. Adapted mainly from apm/apm_cursor.c * and whatever piece of code in XFree86 that could provide me with *************** *** 21,26 **** --- 22,29 ---- #include "scrnintstr.h" #include "servermd.h" #include "windowstr.h" + #include "mfb.h" + #include "compiler.h" #include "xf86.h" #include "mipointer.h" #include "xf86Priv.h" *************** *** 70,79 **** static CursorPtr tsengCursorpCurs; /* ! * This is a high-level init function, called once at ! * startup and once every time the server VC is reentered; ! * it passes a local miPointerSpriteFuncRec with ! * additional functions that we need to provide. * It is called by the SVGA server. */ --- 73,80 ---- static CursorPtr tsengCursorpCurs; /* ! * This is a high-level init function, called once; it passes a local ! * miPointerSpriteFuncRec with additional functions that we need to provide. * It is called by the SVGA server. */ *************** *** 108,114 **** unsigned char tmp; /* Enable the hardware cursor. */ ! if (et4000_type >= TYPE_ET6000) { tmp = inb(ET6Kbase+0x46); outb(ET6Kbase+0x46, (tmp | 0x01)); } --- 109,115 ---- unsigned char tmp; /* Enable the hardware cursor. */ ! if (Is_ET6K) { tmp = inb(ET6Kbase+0x46); outb(ET6Kbase+0x46, (tmp | 0x01)); } *************** *** 128,134 **** unsigned char tmp; /* Disable the hardware cursor. */ ! if (et4000_type >= TYPE_ET6000) { tmp = inb(ET6Kbase+0x46); outb(ET6Kbase+0x46, (tmp & 0xfe));; } --- 129,135 ---- unsigned char tmp; /* Disable the hardware cursor. */ ! if (Is_ET6K) { tmp = inb(ET6Kbase+0x46); outb(ET6Kbase+0x46, (tmp & 0xfe));; } *************** *** 367,373 **** /* Program the cursor image address in video memory. */ /* The adress is given in doublewords */ ! if (et4000_type >= TYPE_ET6000) { /* bits 19:16 */ outb(vgaIOBase + 0x04, 0x0E); tmp = inb(vgaIOBase + 0x05) & 0xF0; --- 368,374 ---- /* Program the cursor image address in video memory. */ /* The adress is given in doublewords */ ! if (Is_ET6K) { /* bits 19:16 */ outb(vgaIOBase + 0x04, 0x0E); tmp = inb(vgaIOBase + 0x05) & 0xF0; *************** *** 483,489 **** /* Program the cursor origin (offset into the cursor bitmap). */ /* Program the new cursor position. */ ! if (et4000_type >= TYPE_ET6000) { outb (ET6Kbase + 0x82, xorigin); outb (ET6Kbase + 0x83, yorigin); --- 484,490 ---- /* Program the cursor origin (offset into the cursor bitmap). */ /* Program the new cursor position. */ ! if (Is_ET6K) { outb (ET6Kbase + 0x82, xorigin); outb (ET6Kbase + 0x83, yorigin); *************** *** 579,585 **** badColour = 0; fgColour = 0; bgColour = 0; ! if (et4000_type >= TYPE_ET6000) { /* Extract foreground Cursor Colour, put in position bits 5 and 4 */ fgColour = get_et6000_color_bits(pCurs->foreRed, &badColour) << 4 | get_et6000_color_bits(pCurs->foreGreen, &badColour) << 2 --- 580,586 ---- badColour = 0; fgColour = 0; bgColour = 0; ! if (Is_ET6K) { /* Extract foreground Cursor Colour, put in position bits 5 and 4 */ fgColour = get_et6000_color_bits(pCurs->foreRed, &badColour) << 4 | get_et6000_color_bits(pCurs->foreGreen, &badColour) << 2 *** /dev/null Tue Jun 30 15:22:38 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/et4000/tseng_dpms.c Fri Mar 6 16:50:11 1998 *************** *** 0 **** --- 1,259 ---- + /* $TOG: tseng_dpms.c /main/1 1998/03/06 16:51:49 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/et4000/tseng_dpms.c,v 1.1.2.2 1998/02/27 01:29:28 dawes Exp $ */ + + #ifdef DPMSExtension + + #include "compiler.h" + + #include "xf86.h" + + #include "vga.h" + #include "tseng.h" + + /* + * TsengCrtcDPMSSet -- + * + * Sets VESA Display Power Management Signaling (DPMS) Mode. + * This routine is for the ET4000W32P rev. c and later, which can + * use CRTC indexed register 34 to turn off H/V Sync signals. + * + * '97 Harald Nordgård Hansen + */ + void + TsengCrtcDPMSSet(int Mode) + { + unsigned char seq1, crtc34; + if (!xf86VTSema) return; + switch (Mode) + { + case DPMSModeOn: + default: + /* Screen: On; HSync: On, VSync: On */ + seq1 = 0x00; + crtc34 = 0x00; + break; + case DPMSModeStandby: + /* Screen: Off; HSync: Off, VSync: On */ + seq1 = 0x20; + crtc34 = 0x01; + break; + case DPMSModeSuspend: + /* Screen: Off; HSync: On, VSync: Off */ + seq1 = 0x20; + crtc34 = 0x20; + break; + case DPMSModeOff: + /* Screen: Off; HSync: Off, VSync: Off */ + seq1 = 0x20; + crtc34 = 0x21; + break; + } + outb(0x3C4, 0x01); /* Select SEQ1 */ + seq1 |= inb(0x3C5) & ~0x20; + outb(0x3C5, seq1); + outb(vgaIOBase+4, 0x34); /* Select CRTC34 */ + crtc34 |= inb(vgaIOBase+5) & ~0x21; + outb(vgaIOBase+5, crtc34); + } + + + /* + * TsengHVSyncDPMSSet -- + * + * Sets VESA Display Power Management Signaling (DPMS) Mode. + * This routine is for Tseng et4000 chips that do not have any + * registers to disable sync output. + * + * The "classic" (standard VGA compatible) method; disabling all syncs, + * causes video memory corruption on Tseng cards, according to "Tseng + * ET4000/W32 family tech note #20": + * + * "Setting CRTC Indexed Register 17 bit 7 = 0 will disable the video + * syncs (=VESA DPMS power down), but will also disable DRAM refresh cycles" + * + * The method used here is derived from the same tech note, which describes + * a method to disable specific sync signals on chips that do not have + * direct support for it: + * + * To get vsync off, program VSYNC_START > VTOTAL + * (approximately). In particular, the formula used is: + * + * VSYNC.ADJ = (VTOT - VSYNC.NORM) + VTOT + 4 + * + * To test for this state, test if VTOT + 1 < VSYNC + * + * + * To get hsync off, program HSYNC_START > HTOTAL + * (approximately). In particular, the following formula is used: + * + * HSYNC.ADJ = (HTOT - HSYNC.NORM) + HTOT + 7 + * + * To test for this state, test if HTOT + 3 < HSYNC + * + * The advantage of these formulas is that the ON state can be restored by + * reversing the formula. The original state need not be stored anywhere... + * + * The trick in the above approach is obviously to put the start of the sync + * _beyond_ the total H or V counter range, which causes the sync to never + * toggle. + */ + void + TsengHVSyncDPMSSet(int Mode) + { + unsigned char seq1, tmpb; + unsigned int HSync, VSync, HTot, VTot, tmp; + Bool chgHSync, chgVSync; + + if (!xf86VTSema) return; + + /* Code here to read the current values of HSync through VTot: + * HSYNC: + * bits 0..7 : CRTC index 0x04 + * bit 8 : CRTC index 0x3F, bit 4 + */ + outb(vgaIOBase+4, 0x04); + HSync = inb(vgaIOBase+5); + outb(vgaIOBase+4, 0x3F); + HSync += (inb(vgaIOBase+5) & 0x10) << 4; + /* VSYNC: + * bits 0..7 : CRTC index 0x10 + * bits 8..9 : CRTC index 0x07 bits 2 (VSYNC bit 8) and 7 (VSYNC bit 9) + * bit 10 : CRTC index 0x35 bit 3 + */ + outb(vgaIOBase+4, 0x10); + VSync = inb(vgaIOBase+5); + outb(vgaIOBase+4, 0x07); + tmp = inb(vgaIOBase+5); + VSync += ((tmp & 0x04) << 6) + ((tmp & 0x80) << 2); + outb(vgaIOBase+4, 0x35); + VSync += (inb(vgaIOBase+5) & 0x08) << 7; + /* HTOT: + * bits 0..7 : CRTC index 0x00. + * bit 8 : CRTC index 0x3F, bit 0 + */ + outb(vgaIOBase+4, 0x00); + HTot = inb(vgaIOBase+5); + outb(vgaIOBase+4, 0x3F); + HTot += (inb(vgaIOBase+5) & 0x01) << 8; + /* VTOT: + * bits 0..7 : CRTC index 0x06 + * bits 8..9 : CRTC index 0x07 bits 0 (VTOT bit 8) and 5 (VTOT bit 9) + * bit 10 : CRTC index 0x35 bit 1 + */ + outb(vgaIOBase+4, 0x06); + VTot = inb(vgaIOBase+5); + outb(vgaIOBase+4, 0x07); + tmp = inb(vgaIOBase+5); + VTot += ((tmp & 0x01) << 8) + ((tmp & 0x20) << 4); + outb(vgaIOBase+4, 0x35); + VTot += (inb(vgaIOBase+5) & 0x02) << 9; + + /* Don't write these unless we have to. */ + chgHSync = chgVSync = FALSE; + + switch (Mode) + { + case DPMSModeOn: + default: + /* Screen: On; HSync: On, VSync: On */ + seq1 = 0x00; + if(HSync > HTot +3) { /* Sync is off now, turn it on. */ + HSync = (HTot - HSync) + HTot + 7; + chgHSync = TRUE; + } + if(VSync > VTot +1) { /* Sync is off now, turn it on. */ + VSync = (VTot - VSync) + VTot + 4; + chgVSync = TRUE; + } + break; + case DPMSModeStandby: + /* Screen: Off; HSync: Off, VSync: On */ + seq1 = 0x20; + if(HSync <= HTot +3) { /* Sync is on now, turn it off. */ + HSync = (HTot - HSync) + HTot + 7; + chgHSync = TRUE; + } + if(VSync > VTot +1) { /* Sync is off now, turn it on. */ + VSync = (VTot - VSync) + VTot + 4; + chgVSync = TRUE; + } + break; + case DPMSModeSuspend: + /* Screen: Off; HSync: On, VSync: Off */ + seq1 = 0x20; + if(HSync > HTot +3) { /* Sync is off now, turn it on. */ + HSync = (HTot - HSync) + HTot + 7; + chgHSync = TRUE; + } + if(VSync <= VTot +1) { /* Sync is on now, turn it off. */ + VSync = (VTot - VSync) + VTot + 4; + chgVSync = TRUE; + } + break; + case DPMSModeOff: + /* Screen: Off; HSync: Off, VSync: Off */ + seq1 = 0x20; + if(HSync <= HTot +3) { /* Sync is on now, turn it off. */ + HSync = (HTot - HSync) + HTot + 7; + chgHSync = TRUE; + } + if(VSync <= VTot +1) { /* Sync is on now, turn it off. */ + VSync = (VTot - VSync) + VTot + 4; + chgVSync = TRUE; + } + break; + } + + /* If the new hsync or vsync overflows, don't change anything. */ + if (HSync >= 1 << 9 || VSync >= 1 << 11) { + ErrorF("tseng: warning: Cannot go into DPMS from this resolution.\n"); + chgVSync = chgHSync = FALSE; + } + + /* The code to turn on and off video output is equal for all. */ + if (chgHSync || chgVSync) { + outb(0x3C4, 0x01); /* Select SEQ1 */ + seq1 |= inb(0x3C5) & ~0x20; + outb(0x3C5, seq1); + } + + /* Then the code to write VSync and HSync to the card. + * HSYNC: + * bits 0..7 : CRTC index 0x04 + * bit 8 : CRTC index 0x3F, bit 4 + */ + if(chgHSync) { + outb(vgaIOBase+4, 0x04); + tmpb = HSync & 0xFF; + outb(vgaIOBase+5, tmpb); + outb(vgaIOBase+4, 0x3F); + tmpb = (HSync & 0x100) >>4; + tmpb |= inb(vgaIOBase+5) & ~0x10; + outb(vgaIOBase+5, tmpb); + } + /* VSYNC: + * bits 0..7 : CRTC index 0x10 + * bits 8..9 : CRTC index 0x07 bits 2 (VSYNC bit 8) and 7 (VSYNC bit 9) + * bit 10 : CRTC index 0x35 bit 3 + */ + if(chgVSync) { + outb(vgaIOBase+4, 0x10); + tmpb = VSync & 0xFF; + outb(vgaIOBase+5, tmpb); + outb(vgaIOBase+4, 0x07); + tmpb = (VSync & 0x100) >> 6; + tmpb |= (VSync & 0x200) >> 2; + tmpb |= inb(vgaIOBase+5) & ~0x84; + outb(vgaIOBase+5, tmpb); + outb(vgaIOBase+4, 0x35); + tmpb = (VSync & 0x400) >> 7; + tmpb |= inb(vgaIOBase+5) & ~0x08; + outb(vgaIOBase+5, tmpb); + } + } + #else + static int nodpms; + #endif *** /dev/null Tue Jun 30 15:22:39 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/et4000/tseng_inline.h Fri Mar 6 16:50:15 1998 *************** *** 0 **** --- 1,294 ---- + /* $TOG: tseng_inline.h /main/1 1998/03/06 16:51:53 kaleb $ */ + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/et4000/tseng_inline.h,v 1.1.2.1 1998/02/01 16:42:13 robin Exp $ */ + + #include "compiler.h" + + /* + * Some commonly used inline functions and utility functions. + */ + + + static __inline__ int + COLOR_REPLICATE_DWORD (int color) + { + switch (tseng_bytesperpixel) + { + case 1: + color &= 0xFF; + color = (color << 8) | color; + color = (color << 16) | color; + break; + case 2: + color &= 0xFFFF; + color = (color << 16) | color; + break; + } + return color; + } + + /* + * Optimizing note: increasing the wrap size for fixed-color source/pattern + * tiles from 4x1 (as below) to anything bigger doesn't seem to affect + * performance (it might have been better for larger wraps, but it isn't). + */ + + static __inline__ void + SET_FG_COLOR (int color) + { + *ACL_SOURCE_ADDRESS = tsengFg; + *ACL_SOURCE_Y_OFFSET = 3; + color = COLOR_REPLICATE_DWORD (color); + *tsengMemFg = color; + if (Is_W32p_up) + { + *ACL_SOURCE_WRAP = 0x02; + } + else + { + *(tsengMemFg + 1) = color; + *ACL_SOURCE_WRAP = 0x12; + } + } + + static __inline__ void + SET_BG_COLOR (int color) + { + *ACL_PATTERN_ADDRESS = tsengPat; + *ACL_PATTERN_Y_OFFSET = 3; + color = COLOR_REPLICATE_DWORD (color); + *tsengMemPat = color; + if (Is_W32p_up) + { + *ACL_PATTERN_WRAP = 0x02; + } + else + { + *(tsengMemPat + 1) = color; + *ACL_PATTERN_WRAP = 0x12; + } + } + + /* + * this does the same as SET_FG_COLOR and SET_BG_COLOR together, but is + * faster, because it allows the PCI chipset to chain the requests into a + * burst sequence. The order of the commands is partly linear. + * So far for the theory... + */ + static __inline__ void + SET_FG_BG_COLOR (int fgcolor, int bgcolor) + { + *ACL_PATTERN_ADDRESS = tsengPat; + *ACL_SOURCE_ADDRESS = tsengFg; + *((LongP) ACL_PATTERN_Y_OFFSET) = 0x00030003; + fgcolor = COLOR_REPLICATE_DWORD (fgcolor); + bgcolor = COLOR_REPLICATE_DWORD (bgcolor); + *tsengMemFg = fgcolor; + *tsengMemPat = bgcolor; + if (Is_W32p_up) + { + *((LongP) ACL_PATTERN_WRAP) = 0x00020002; + } + else + { + *(tsengMemFg + 1) = fgcolor; + *(tsengMemPat + 1) = bgcolor; + *((LongP) ACL_PATTERN_WRAP) = 0x00120012; + } + } + + /* + * Real 32-bit multiplications are horribly slow compared to 16-bit (on i386). + * + * FBADDR() could be implemented completely in assembler on i386. + */ + #ifdef NO_OPTIMIZE + static __inline__ int + MULBPP (int x) + { + return (x * tseng_bytesperpixel); + } + #else + static __inline__ int + MULBPP (int x) + { + int result = x << tseng_powerPerPixel; + if (tseng_bytesperpixel != 3) + return result; + else + return result + x; + } + #endif + + static __inline__ int + CALC_XY (int x, int y) + { + int new_x, xy; + + if ((old_y == y) && (old_x == x)) + return -1; + + if (Is_W32p) + new_x = MULBPP (x - 1); + else + new_x = MULBPP (x) - 1; + xy = ((y - 1) << 16) + new_x; + old_x = x; + old_y = y; + return xy; + } + + /* generic SET_XY */ + static __inline__ void + SET_XY (int x, int y) + { + int new_x; + if (Is_W32p) + new_x = MULBPP (x - 1); + else + new_x = MULBPP (x) - 1; + *ACL_XY_COUNT = ((y - 1) << 16) + new_x; + old_x = x; + old_y = y; + } + + static __inline__ void + SET_X_YRAW (int x, int y) + { + int new_x; + if (Is_W32p) + new_x = MULBPP (x - 1); + else + new_x = MULBPP (x) - 1; + *ACL_XY_COUNT = (y << 16) + new_x; + old_x = x; + old_y = y - 1; /* old_y is invalid (raw transfer) */ + } + + /* + * This is plain and simple "benchmark rigging". + * (no real application does lots of subsequent same-size blits) + * + * The effect of this is amazingly good on e.g large blits: 400x400 + * rectangle fill in 24 and 32 bpp on ET6000 jumps from 276 MB/sec to up to + * 490 MB/sec... But not always. There must be a good reason why this gives + * such a boost, but I don't know it. + */ + + static __inline__ void + SET_XY_4 (int x, int y) + { + int new_xy; + + if ((old_y != y) || (old_x != x)) + { + new_xy = ((y - 1) << 16) + MULBPP (x - 1); + *ACL_XY_COUNT = new_xy; + old_x = x; + old_y = y; + } + } + + static __inline__ void + SET_XY_6 (int x, int y) + { + int new_xy; /* using this intermediate variable is faster */ + + if ((old_y != y) || (old_x != x)) + { + new_xy = ((y - 1) << 16) + MULBPP (x) - 1; + *ACL_XY_COUNT = new_xy; + old_x = x; + old_y = y; + } + } + + + /* generic SET_XY_RAW */ + static __inline__ void + SET_XY_RAW (int x, int y) + { + *ACL_XY_COUNT = (y << 16) + x; + old_x = old_y = -1; /* invalidate old_x/old_y (raw transfers) */ + } + + static __inline__ void + PINGPONG () + { + if (tsengFg == W32ForegroundPing) + { + tsengMemFg = MemW32ForegroundPong; + tsengFg = W32ForegroundPong; + tsengMemBg = MemW32BackgroundPong; + tsengBg = W32BackgroundPong; + tsengMemPat = MemW32PatternPong; + tsengPat = W32PatternPong; + } + else + { + tsengMemFg = MemW32ForegroundPing; + tsengFg = W32ForegroundPing; + tsengMemBg = MemW32BackgroundPing; + tsengBg = W32BackgroundPing; + tsengMemPat = MemW32PatternPing; + tsengPat = W32PatternPing; + } + } + + + /* + * This is called in each ACL function just before the first ACL register is + * written to. It waits for a the accelerator to finish on cards that don't + * support hardware-wait-state locking, and waits for a free queue entry on + * others, if hardware-wait-states are not enabled. + */ + static __inline__ void + wait_acl_queue () + { + if (!tseng_use_PCI_Retry) + WAIT_QUEUE; + if (tseng_need_wait_acl) + WAIT_ACL; + } + + /* + * The functions below need "MoveDWORDS()". This is an optimized C-only (no + * assembler), but fast "memcpy()"-like function. Author: Harm Hanemaayer (?) + */ + + static __inline__ void + MoveDWORDS (dest, src, dwords) + register CARD32 *dest; + register CARD32 *src; + register int dwords; + { + while (dwords & ~0x03) + { + *dest = *src; + *(dest + 1) = *(src + 1); + *(dest + 2) = *(src + 2); + *(dest + 3) = *(src + 3); + src += 4; + dest += 4; + dwords -= 4; + } + switch (dwords) + { + case 0: + return; + case 1: + *dest = *src; + return; + case 2: + *dest = *src; + *(dest + 1) = *(src + 1); + return; + case 3: + *dest = *src; + *(dest + 1) = *(src + 1); + *(dest + 2) = *(src + 2); + return; + } + } *** ./xfree86/vga256/drivers/et4000/tseng_ramdac.c@@/PUBLIC-LATEST Sun Aug 10 13:05:30 1997 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/et4000/tseng_ramdac.c Fri Mar 6 16:50:19 1998 *************** *** 1,8 **** ! /* $TOG: tseng_ramdac.c /main/2 1997/08/10 13:04:06 kaleb $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/et4000/tseng_ramdac.c,v 3.3.2.12 1997/07/28 15:06:53 dawes Exp $ */ /* * --- 1,8 ---- ! /* $TOG: tseng_ramdac.c /main/3 1998/03/06 16:51:56 kaleb $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/et4000/tseng_ramdac.c,v 3.3.2.14 1998/02/01 16:05:08 robin Exp $ */ /* * *************** *** 22,31 **** #include "compiler.h" #include "xf86.h" #include "xf86Procs.h" #include "xf86Priv.h" - #include "xf86.h" #define XCONFIG_FLAGS_ONLY #include "xf86_Config.h" --- 22,31 ---- #include "compiler.h" #include "xf86.h" + #include "xf86_HWlib.h" #include "xf86Procs.h" #include "xf86Priv.h" #define XCONFIG_FLAGS_ONLY #include "xf86_Config.h" *************** *** 42,53 **** { ATT20C491_DAC, "att20c491" }, { ATT20C492_DAC, "att20c492" }, { ICS5341_DAC, "ics5341" }, ! { GENDAC_DAC, "gendac" }, { STG1700_DAC, "stg1700" }, { STG1702_DAC, "stg1702" }, { STG1703_DAC, "stg1703" }, { ET6000_DAC, "et6000" }, { CH8398_DAC, "ch8398" }, { UNKNOWN_DAC, "unknown" }, }; --- 42,54 ---- { ATT20C491_DAC, "att20c491" }, { ATT20C492_DAC, "att20c492" }, { ICS5341_DAC, "ics5341" }, ! { ICS5301_DAC, "ics5301" }, { STG1700_DAC, "stg1700" }, { STG1702_DAC, "stg1702" }, { STG1703_DAC, "stg1703" }, { ET6000_DAC, "et6000" }, { CH8398_DAC, "ch8398" }, + { MUSIC4910_DAC, "music4910" }, { UNKNOWN_DAC, "unknown" }, }; *************** *** 56,62 **** /* pixel multiplexing variables */ Bool Tseng_pixMuxPossible = FALSE; int Tseng_nonMuxMaxClock = 0; - int Tseng_pixMuxMinClock = 0; int Tseng_pixMuxMinWidth = 1024; --- 57,62 ---- *************** *** 209,222 **** ErrorF("%s %s: Ramdac: ICS 5301 GENDAC and programmable clock (MClk = %1.2f MHz)\n", XCONFIG_PROBED, vga256InfoRec.name, mclk); } ! TsengRamdacType = GENDAC_DAC; break; default: if (!quiet) { ! ErrorF("%s %s: Ramdac: unknown GENDAC and programmable clock (ID code = 0x%02x)\n", XCONFIG_PROBED, vga256InfoRec.name, dbyte); } ! TsengRamdacType = GENDAC_DAC; } xf86dactopel(); } --- 209,222 ---- ErrorF("%s %s: Ramdac: ICS 5301 GENDAC and programmable clock (MClk = %1.2f MHz)\n", XCONFIG_PROBED, vga256InfoRec.name, mclk); } ! TsengRamdacType = ICS5301_DAC; break; default: if (!quiet) { ! ErrorF("%s %s: Ramdac: unknown GENDAC and programmable clock (ID code = 0x%02x). Please report. (we'll treat it as a standard ICS5301 for now).\n", XCONFIG_PROBED, vga256InfoRec.name, dbyte); } ! TsengRamdacType = ICS5301_DAC; } xf86dactopel(); } *************** *** 223,230 **** return found; } static Bool ! ProbeCH8398(Bool quiet) { unsigned char cid; Bool Found = FALSE; --- 223,232 ---- return found; } + + /* probe for RAMDAC using the chip-ID method */ static Bool ! ProbeRamdacID(Bool quiet) { unsigned char cid; Bool Found = FALSE; *************** *** 234,242 **** cid = inb(RAMDAC_RMR); cid = inb(RAMDAC_RMR); cid = inb(RAMDAC_RMR); /* this returns chip ID */ ! if (cid == 0xc0) { ! Found = TRUE; ! TsengRamdacType = CH8398_DAC; } xf86dactopel(); --- 236,253 ---- cid = inb(RAMDAC_RMR); cid = inb(RAMDAC_RMR); cid = inb(RAMDAC_RMR); /* this returns chip ID */ ! switch(cid) ! { ! case 0xc0: ! Found = TRUE; ! TsengRamdacType = CH8398_DAC; ! break; ! case 0x82: ! Found = TRUE; ! TsengRamdacType = MUSIC4910_DAC; ! break; ! default: ! Found = FALSE; } xf86dactopel(); *************** *** 308,315 **** GlennsIODelay(); } ! void Check_Tseng_Ramdac() { unsigned char cmap[3], save_cmap[3]; --- 319,343 ---- GlennsIODelay(); } ! static void ! check_mclk(min, max) ! int min, max; ! { ! if (vga256InfoRec.MemClk <= 0) return; + if (vga256InfoRec.MemClk < min || vga256InfoRec.MemClk > max) { + ErrorF("%s %s: MCLK %1.3f MHz out of range (=%1.3f..%1.3f), not changed!\n", + OFLG_ISSET(XCONFIG_MEMCLOCK, &vga256InfoRec.xconfigFlag) ? + XCONFIG_GIVEN : XCONFIG_PROBED, vga256InfoRec.name, + vga256InfoRec.MemClk / 1000.0, min / 1000.0, max / 1000.0); + vga256InfoRec.MemClk = 0; + } + else if (xf86Verbose) + ErrorF("%s %s: set MCLK to %1.3f MHz\n", + XCONFIG_GIVEN, vga256InfoRec.name, vga256InfoRec.MemClk / 1000.0); + } + + void Check_Tseng_Ramdac() { unsigned char cmap[3], save_cmap[3]; *************** *** 327,340 **** if (TsengRamdacType < 0) { ErrorF("%s %s: Unknown RAMDAC type \"%s\"\n", XCONFIG_GIVEN, vga256InfoRec.name, vga256InfoRec.ramdac); ! return ; } } else /* autoprobe for the RAMDAC */ { ! /* is it an ICS GenDAC ? */ ! if (ProbeGenDAC(FALSE)) { /* It is. Nothing to do here */ } else if (ProbeSTG1703(FALSE)) --- 355,371 ---- if (TsengRamdacType < 0) { ErrorF("%s %s: Unknown RAMDAC type \"%s\"\n", XCONFIG_GIVEN, vga256InfoRec.name, vga256InfoRec.ramdac); ! return; } } else /* autoprobe for the RAMDAC */ { ! if (Is_ET6K) { + TsengRamdacType = ET6000_DAC; + } + else if (ProbeGenDAC(FALSE)) + { /* It is. Nothing to do here */ } else if (ProbeSTG1703(FALSE)) *************** *** 341,352 **** { /* it's a STG170x */ } ! else if (ProbeCH8398(FALSE)) { ! /* it's a CH8398 */ } else ! /* if none of the above: start probing for other DAC's */ { outb(RAMDAC_RMR, 0xff); GlennsIODelay(); inb(RAMDAC_RMR); GlennsIODelay(); --- 372,383 ---- { /* it's a STG170x */ } ! else if (ProbeRamdacID(FALSE)) { ! /* found one using RAMDAC ID code */ } else ! /* if none of the above: start probing for other DACs */ { outb(RAMDAC_RMR, 0xff); GlennsIODelay(); inb(RAMDAC_RMR); GlennsIODelay(); *************** *** 398,404 **** } dac_found: - /* defaults: 8-bit wide DAC port, 6-bit color lookup-tables */ RamdacShift = 10; vgaRamdacMask = 0x3f; --- 429,434 ---- *************** *** 423,434 **** --- 453,470 ---- OFLG_SET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions); OFLG_SET(CLOCK_OPTION_ET6000, &vga256InfoRec.clockOptions); generic_ramdac = TRUE; /* avoids treatment as ATT compatible DAC */ + check_mclk(80000,110000); break; case ICS5341_DAC: OFLG_SET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions); OFLG_SET(CLOCK_OPTION_ICS5341, &vga256InfoRec.clockOptions); + check_mclk(40000,60000); dac_is_16bit = TRUE; break; + case ICS5301_DAC: + OFLG_SET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions); + OFLG_SET(CLOCK_OPTION_ICS5301, &vga256InfoRec.clockOptions); + break; case STG1702_DAC: case STG1700_DAC: dac_is_16bit = TRUE; *************** *** 453,467 **** } ! void tseng_init_clockscale(int bytesperpixel) { /* nothing to do for 1:1 modes */ ! if (bytesperpixel <= 1) return; ! if (et4000_type >= TYPE_ET6000) return; /* 16-bit ET4000W32p RAMDACs need different treatment than 8-bitters */ if (dac_is_16bit) { ! switch (bytesperpixel) { case 3: ET4000.ChipClockDivFactor = 2; ET4000.ChipClockMulFactor = 3; break; --- 489,503 ---- } ! void tseng_init_clockscale() { /* nothing to do for 1:1 modes */ ! if (tseng_bytesperpixel <= 1) return; ! if (Is_ET6K) return; /* 16-bit ET4000W32p RAMDACs need different treatment than 8-bitters */ if (dac_is_16bit) { ! switch (tseng_bytesperpixel) { case 3: ET4000.ChipClockDivFactor = 2; ET4000.ChipClockMulFactor = 3; break; *************** *** 472,483 **** } /* 8-bit RAMDACs */ ! ET4000.ChipClockMulFactor = bytesperpixel; /* 8-bit RAMDAC */ return; } ! ! void tseng_set_dacspeed(int bytesperpixel) { /* * Memory bandwidth is important in > 8bpp modes, especially on ET4000 --- 508,518 ---- } /* 8-bit RAMDACs */ ! ET4000.ChipClockMulFactor = tseng_bytesperpixel; /* 8-bit RAMDAC */ return; } ! void tseng_set_dacspeed() { /* * Memory bandwidth is important in > 8bpp modes, especially on ET4000 *************** *** 496,506 **** */ int mem_bw; /* memory bandwidth */ ! #ifndef USE_OFFICIAL_TSENG_LIMITS ! unsigned char bw_reg; ! #endif ! if (bytesperpixel < 1) bytesperpixel = 1; /* for MONO/VGA16 */ /* * First, determine if we can use pixel multiplexing. This will have --- 531,540 ---- */ int mem_bw; /* memory bandwidth */ ! int local_bytesperpixel = tseng_bytesperpixel; ! /* kludge for 1 and 4bpp modes */ ! if (tseng_bytesperpixel < 1) local_bytesperpixel = 1; /* * First, determine if we can use pixel multiplexing. This will have *************** *** 507,555 **** * impact on the max allowed pixelclock. */ ! if (OFLG_ISSET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions)) { ! if (OFLG_ISSET(CLOCK_OPTION_ICS5341, &vga256InfoRec.clockOptions)) ! { ! ErrorF("%s %s: Using W32p programmable clock chip ICS5341\n", ! OFLG_ISSET(CLOCK_OPTION_ICS5341, &vga256InfoRec.clockOptions) ? ! XCONFIG_GIVEN : XCONFIG_PROBED, vga256InfoRec.name); if (vgaBitsPerPixel == 8) { Tseng_pixMuxPossible = TRUE; Tseng_nonMuxMaxClock = MAX_TSENG_CLOCK; /* or 75000 ? */ - Tseng_pixMuxMinClock = 67500; Tseng_pixMuxMinWidth = 1024; /* seems to be this way: 1024x768 is wrong with pixmux */ } - } - else if (OFLG_ISSET(CLOCK_OPTION_STG1703, &vga256InfoRec.clockOptions)) - { - ErrorF("%s %s: Using W32p programmable clock chip STG1703\n", - OFLG_ISSET(CLOCK_OPTION_STG1703, &vga256InfoRec.clockOptions) ? - XCONFIG_GIVEN : XCONFIG_PROBED, vga256InfoRec.name); - if (vgaBitsPerPixel == 8) { - Tseng_pixMuxPossible = TRUE; - Tseng_nonMuxMaxClock = MAX_TSENG_CLOCK; /* or 75000 ? */ - Tseng_pixMuxMinClock = 67500; - Tseng_pixMuxMinWidth = 1024; /* seems to be this way: 1024x768 is wrong with pixmux */ - } - } - else if (OFLG_ISSET(CLOCK_OPTION_ICD2061A, &vga256InfoRec.clockOptions)) - { - ErrorF("%s %s: Using W32 programmable clock chip ICD2061a\n", - OFLG_ISSET(CLOCK_OPTION_ICD2061A, &vga256InfoRec.clockOptions) ? - XCONFIG_GIVEN : XCONFIG_PROBED, vga256InfoRec.name); - } - else if (OFLG_ISSET(CLOCK_OPTION_ET6000, &vga256InfoRec.clockOptions)) - { - ErrorF("%s %s: Using ET6000 built-in programmable clock\n", - OFLG_ISSET(CLOCK_OPTION_ET6000, &vga256InfoRec.clockOptions) ? - XCONFIG_GIVEN : XCONFIG_PROBED, vga256InfoRec.name); - } - else - { - ErrorF("%s %s: Unsupported clock chip given for ET4000 W32\n", - XCONFIG_GIVEN, vga256InfoRec.name); - /* return(FALSE); */ - } } /* if not set in the XF86Config file, use defaults */ --- 541,557 ---- * impact on the max allowed pixelclock. */ ! switch (TsengRamdacType) ! { ! case ICS5341_DAC: ! case STG1703_DAC: ! case STG1702_DAC: ! case STG1700_DAC: if (vgaBitsPerPixel == 8) { Tseng_pixMuxPossible = TRUE; Tseng_nonMuxMaxClock = MAX_TSENG_CLOCK; /* or 75000 ? */ Tseng_pixMuxMinWidth = 1024; /* seems to be this way: 1024x768 is wrong with pixmux */ } } /* if not set in the XF86Config file, use defaults */ *************** *** 556,562 **** if (vga256InfoRec.dacSpeeds[0] <= 0) { switch(TsengRamdacType) { case CH8398_DAC: - case GENDAC_DAC: case ICS5341_DAC: case STG1700_DAC: case STG1702_DAC: --- 558,563 ---- *************** *** 567,577 **** vga256InfoRec.dacSpeeds[0] = MAX_TSENG_CLOCK; break; case ET6000_DAC: ! vga256InfoRec.dacSpeeds[0] = 135000; break; - case ET6300_DAC: - vga256InfoRec.dacSpeeds[0] = 175000; - break; default: vga256InfoRec.dacSpeeds[0] = MAX_TSENG_CLOCK; } --- 568,578 ---- vga256InfoRec.dacSpeeds[0] = MAX_TSENG_CLOCK; break; case ET6000_DAC: ! if (et4000_type == TYPE_ET6000) ! vga256InfoRec.dacSpeeds[0] = 135000; ! else ! vga256InfoRec.dacSpeeds[0] = 175000; break; default: vga256InfoRec.dacSpeeds[0] = MAX_TSENG_CLOCK; } *************** *** 588,599 **** */ vga256InfoRec.maxClock = min(vga256InfoRec.dacSpeeds[0], ! ((mem_bw/bytesperpixel)*ET4000.ChipClockMulFactor)/ET4000.ChipClockDivFactor); } else { ! #define USE_OFFICIAL_TSENG_LIMITS ! /* According to Tseng: * "Besides the 135 MHz maximum pixel clock frequency, the other limit has to * do with where you get FIFO breakdown (usually appears as stray horizontal * lines on the screen). Assuming the accelerator is running steadily doing a --- 589,599 ---- */ vga256InfoRec.maxClock = min(vga256InfoRec.dacSpeeds[0], ! ((mem_bw/local_bytesperpixel)*ET4000.ChipClockMulFactor)/ET4000.ChipClockDivFactor); } else { ! /* According to Tseng (about the ET6000): * "Besides the 135 MHz maximum pixel clock frequency, the other limit has to * do with where you get FIFO breakdown (usually appears as stray horizontal * lines on the screen). Assuming the accelerator is running steadily doing a *************** *** 608,639 **** * for q3, the ET6300] will raise the pixel clock limit to 175 MHz and * the pixel_clock*(bytes/pixel) FIFO breakdown limit to about 275 MHz." */ ! #ifdef USE_OFFICIAL_TSENG_LIMITS ! if (et4000_type > TYPE_ET6000) /* ET6300 */ ! mem_bw = 275000; else /* ET6000 */ mem_bw = 225000; ! #else ! mem_bw = 90000 * 2 * 5/6; /* 1 MDRAM bandwidth at 90 MHz, with 80% efficiency */ ! bw_reg = inb(ET6Kbase + 0x45); ! if (bw_reg & 0x04) mem_bw *=2; /* 2 MDRAM channels (2 chips) */ ! if (bw_reg & 0x03) mem_bw *=2; /* interleaved MDRAM (4 chips) */ ! #endif ! vga256InfoRec.maxClock = min(vga256InfoRec.dacSpeeds[0], mem_bw/bytesperpixel); } - - #ifndef USE_OFFICIAL_TSENG_LIMITS - if (xf86Verbose) { - ErrorF("%s %s: Estimated video memory bandwidth: %d MB/s.\n", - XCONFIG_PROBED, vga256InfoRec.name, mem_bw/1000); - } - #endif ! if (vga256InfoRec.dacSpeeds[bytesperpixel-1] > 0) ! vga256InfoRec.maxClock = vga256InfoRec.dacSpeeds[bytesperpixel-1]; ! ! #ifndef MONOVGA /* cosmetic: vgaBitsPerPixel is "0" in VGA16 and MONO mode */ ! #ifndef XF86VGA16 if (xf86Verbose) { ErrorF("%s %s: Ramdac speed at %dbpp: %3.3f MHz\n", OFLG_ISSET(XCONFIG_DACSPEED, &vga256InfoRec.xconfigFlag) ? --- 608,624 ---- * for q3, the ET6300] will raise the pixel clock limit to 175 MHz and * the pixel_clock*(bytes/pixel) FIFO breakdown limit to about 275 MHz." */ ! if (et4000_type > TYPE_ET6000) /* ET6100/6300 */ ! mem_bw = 280000; /* 275000 is _just_ not enough for 1152x864x24 @ 70Hz */ else /* ET6000 */ mem_bw = 225000; ! vga256InfoRec.maxClock = min(vga256InfoRec.dacSpeeds[0], mem_bw/local_bytesperpixel); } ! if (vga256InfoRec.dacSpeeds[local_bytesperpixel-1] > 0) ! vga256InfoRec.maxClock = vga256InfoRec.dacSpeeds[local_bytesperpixel-1]; ! ! #ifdef SUPERFLUOUS if (xf86Verbose) { ErrorF("%s %s: Ramdac speed at %dbpp: %3.3f MHz\n", OFLG_ISSET(XCONFIG_DACSPEED, &vga256InfoRec.xconfigFlag) ? *************** *** 641,647 **** vgaBitsPerPixel, vga256InfoRec.dacSpeeds[0] / 1000.0); } #endif - #endif /* Check that maxClock is not higher than dacSpeed */ if (vga256InfoRec.maxClock > vga256InfoRec.dacSpeeds[0]) --- 626,631 ---- *************** *** 650,658 **** } ! void tseng_validate_mode(DisplayModePtr mode, int bytesperpixel, Bool verbose) { int pixel_clock; int hdiv=1, hmul=1; /* --- 634,643 ---- } ! void tseng_validate_mode(DisplayModePtr mode, Bool verbose) { int pixel_clock; + int data_clock; int hdiv=1, hmul=1; /* *************** *** 664,669 **** --- 649,655 ---- * in ET4000Validate(), mode->Clock is enough. */ pixel_clock = vga256InfoRec.clock[mode->Clock]; + data_clock = (pixel_clock * ET4000.ChipClockMulFactor) / ET4000.ChipClockDivFactor; /* * For programmable clocks, fill in the SynthClock value *************** *** 671,735 **** */ if (OFLG_ISSET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions)) { ! mode->SynthClock = (pixel_clock * ET4000.ChipClockMulFactor) / ET4000.ChipClockDivFactor; } ! /* nothing more to do for MONO/VGA16 (pixmux doesn't work anyway) */ ! if (bytesperpixel < 1) return; /* - * Check what impact each mode has on pixel multiplexing, - * and mark those modes for which pixmux must be used. - * PixMux is only possible in 8bpp. - * Pixmux SHOULD work in interlaced mode, but I don't know how to do it :-( - */ - - if ( (Tseng_pixMuxPossible) && - ((pixel_clock / 1000) > (Tseng_nonMuxMaxClock / 1000)) && - (mode->HDisplay >= Tseng_pixMuxMinWidth) && - (!(mode->Flags & V_INTERLACE)) ) { - mode->Flags |= V_PIXMUX; - switch(TsengRamdacType) { - case ICS5341_DAC: - case STG1700_DAC: - case STG1702_DAC: - case STG1703_DAC: - if (mode->SynthClock > Tseng_nonMuxMaxClock) { - mode->SynthClock /= 2; - mode->Flags |= V_DBLCLK; - } - break; - default: - /* Do nothing */ - break; - } - if (verbose) - ErrorF("%s %s: Mode \"%s\" will use pixel multiplexing.\n", - XCONFIG_PROBED, vga256InfoRec.name, mode->name); - } - - /* * define hdiv and hmul depending on mode, pixel multiplexing and ramdac type */ ! if (mode->Flags & V_PIXMUX) ! { ! if ((OFLG_ISSET(CLOCK_OPTION_ICS5341, &vga256InfoRec.clockOptions)) ! && (TsengRamdacType==ICS5341_DAC)) ! { ! if (mode->Flags & V_DBLCLK) ! hdiv = 2; ! } ! if ((OFLG_ISSET(CLOCK_OPTION_STG1703, &vga256InfoRec.clockOptions)) ! && (TsengRamdacType==STG1703_DAC)) ! { ! if (mode->Flags & V_DBLCLK) ! hdiv = 2; ! } } hmul *= ET4000.ChipClockMulFactor; hdiv *= ET4000.ChipClockDivFactor; ! /* * Modify mode timings accordingly */ --- 657,678 ---- */ if (OFLG_ISSET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions)) { ! mode->SynthClock = data_clock; } ! /* nothing more to do for 1 or 4 bpp (pixmux doesn't work anyway) */ ! if (tseng_bytesperpixel < 1) return; /* * define hdiv and hmul depending on mode, pixel multiplexing and ramdac type */ ! if (mode->Flags & V_PIXMUX) { ! hdiv *= 2; } hmul *= ET4000.ChipClockMulFactor; hdiv *= ET4000.ChipClockDivFactor; ! /* * Modify mode timings accordingly */ *************** *** 740,757 **** mode->CrtcHSyncStart = (mode->CrtcHSyncStart * hmul) / hdiv; mode->CrtcHSyncEnd = (mode->CrtcHSyncEnd * hmul) / hdiv; mode->CrtcHSkew = (mode->CrtcHSkew * hmul) / hdiv; ! if (bytesperpixel == 3) { int rgb_skew; ! /* in 24bpp, the position of the BLANK signal determines the * phase of the R,G and B values. XFree86 sets blanking equal to * the Sync, so setting the Sync correctly will also set the ! * BLANK corectly, and thus also the RGB phase */ rgb_skew = (mode->CrtcHTotal/8 - mode->CrtcHSyncEnd/8 - 1) % 3; mode->CrtcHSyncEnd += rgb_skew * 8 + 24; /* HSyncEnd must come BEFORE HTotal */ if (mode->CrtcHSyncEnd > mode->CrtcHTotal) mode->CrtcHSyncEnd -= 24; ! /* HSyncEnd could now have been moved BEFORE HSyncStart, * but if that happens, it means you had a sync of only 8 * clocks long. This should not happen */ --- 683,703 ---- mode->CrtcHSyncStart = (mode->CrtcHSyncStart * hmul) / hdiv; mode->CrtcHSyncEnd = (mode->CrtcHSyncEnd * hmul) / hdiv; mode->CrtcHSkew = (mode->CrtcHSkew * hmul) / hdiv; ! if (tseng_bytesperpixel == 3) { int rgb_skew; ! /* ! * in 24bpp, the position of the BLANK signal determines the * phase of the R,G and B values. XFree86 sets blanking equal to * the Sync, so setting the Sync correctly will also set the ! * BLANK corectly, and thus also the RGB phase ! */ rgb_skew = (mode->CrtcHTotal/8 - mode->CrtcHSyncEnd/8 - 1) % 3; mode->CrtcHSyncEnd += rgb_skew * 8 + 24; /* HSyncEnd must come BEFORE HTotal */ if (mode->CrtcHSyncEnd > mode->CrtcHTotal) mode->CrtcHSyncEnd -= 24; ! /* ! * HSyncEnd could now have been moved BEFORE HSyncStart, * but if that happens, it means you had a sync of only 8 * clocks long. This should not happen */ *************** *** 772,781 **** * "0xFF" is used as a "not-supported" flag. Assuming no RAMDAC uses this * value for some real configuration... */ ! static unsigned char CMD_ICS5341[] = { 0x00, 0x20, 0x60, 0x40, 0xFF, ! 0x10, 0x30, 0x50, 0x90, 0x70 }; ! static unsigned char CMD_STG1703[] = { 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x05, 0x02, 0x03, 0x09, 0x04 }; static unsigned char CMD_CH8398[] = { 0x04, 0xC4, 0x64, 0x74, 0xFF, --- 718,727 ---- * "0xFF" is used as a "not-supported" flag. Assuming no RAMDAC uses this * value for some real configuration... */ ! static unsigned char CMD_GENDAC[] = { 0x00, 0x20, 0x60, 0x40, 0xFF, ! /* gendac and ICS53x1 */ 0x10, 0x30, 0x50, 0x90, 0x70 }; ! static unsigned char CMD_STG170x[] = { 0x00, 0x08, 0xFF, 0xFF, 0xFF, 0x05, 0x02, 0x03, 0x09, 0x04 }; static unsigned char CMD_CH8398[] = { 0x04, 0xC4, 0x64, 0x74, 0xFF, *************** *** 784,801 **** static unsigned char CMD_ATT49x[] = { 0x00, 0xa0, 0xc0, 0xe0, 0xe0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; /* * This sets up the RAMDAC registers for the correct BPP and pixmux values. * (also set VGA controller registers for pixmux and BPP) */ ! void tseng_set_ramdac_bpp(DisplayModePtr mode, vgaET4000Ptr tseng_regs, int bytesperpixel) { Bool rgb555, rgb565, dac16bit; unsigned char* cmd_array = NULL; unsigned char* cmd_dest = NULL; ! int index; ! if (bytesperpixel < 1) bytesperpixel = 1; /* for MONO/VGA16 */ rgb555 = (xf86weight.red == 5 && xf86weight.green == 5 && xf86weight.blue == 5); rgb565 = (xf86weight.red == 5 && xf86weight.green == 6 && xf86weight.blue == 5); --- 730,755 ---- static unsigned char CMD_ATT49x[] = { 0x00, 0xa0, 0xc0, 0xe0, 0xe0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; + static unsigned char CMD_SC15025[] = { 0x00, 0xa0, 0xe0, 0x60, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; + + static unsigned char CMD_MU4910[] = { 0x1C, 0xBC, 0xDC, 0xFC, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; + + /* * This sets up the RAMDAC registers for the correct BPP and pixmux values. * (also set VGA controller registers for pixmux and BPP) */ ! void tseng_set_ramdac_bpp(DisplayModePtr mode, vgaET4000Ptr tseng_regs) { Bool rgb555, rgb565, dac16bit; unsigned char* cmd_array = NULL; unsigned char* cmd_dest = NULL; ! int index, dataclock; ! int local_bytesperpixel = tseng_bytesperpixel; ! if (tseng_bytesperpixel < 1) local_bytesperpixel = 1; /* for 1 and 4bpp */ rgb555 = (xf86weight.red == 5 && xf86weight.green == 5 && xf86weight.blue == 5); rgb565 = (xf86weight.red == 5 && xf86weight.green == 6 && xf86weight.blue == 5); *************** *** 804,814 **** * mode It should rather be passed on from the tseng_validate_mode() code. * Right now it'd better agree with what tseng_validate_mode() proposed. */ ! dac16bit = (dac_is_16bit) && ((bytesperpixel > 1) || (mode->Flags & V_PIXMUX)); tseng_regs->Misc &= 0xCF; /* ATC index 0x16 -- bits-per-PCLK */ ! if (et4000_type >= TYPE_ET6000) ! tseng_regs->Misc |= (bytesperpixel-1) << 4; else if (dac16bit) tseng_regs->Misc |= 0x20; --- 758,768 ---- * mode It should rather be passed on from the tseng_validate_mode() code. * Right now it'd better agree with what tseng_validate_mode() proposed. */ ! dac16bit = (dac_is_16bit) && ((local_bytesperpixel > 1) || (mode->Flags & V_PIXMUX)); tseng_regs->Misc &= 0xCF; /* ATC index 0x16 -- bits-per-PCLK */ ! if (Is_ET6K) ! tseng_regs->Misc |= (local_bytesperpixel-1) << 4; else if (dac16bit) tseng_regs->Misc |= 0x20; *************** *** 824,836 **** case STG1700_DAC: case STG1702_DAC: case STG1703_DAC: ! tseng_regs->gendac.cmd_reg |= 8; ! cmd_array = CMD_STG1703; cmd_dest = &(tseng_regs->gendac.PLL_ctrl); break; case ICS5341_DAC: ! case GENDAC_DAC: ! cmd_array = CMD_ICS5341; tseng_regs->gendac.PLL_ctrl = 0; cmd_dest = &(tseng_regs->gendac.cmd_reg); break; --- 778,809 ---- case STG1700_DAC: case STG1702_DAC: case STG1703_DAC: ! tseng_regs->gendac.cmd_reg &= 0x04; /* keep 7.5 IRE setup setting */ ! tseng_regs->gendac.cmd_reg |= 0x18; /* enable ext regs and pixel modes */ ! switch (local_bytesperpixel) { ! case 2: if (rgb555) tseng_regs->gendac.cmd_reg |= 0xA0; ! if (rgb565) tseng_regs->gendac.cmd_reg |= 0xC0; ! break; ! case 3: ! case 4: ! tseng_regs->gendac.cmd_reg |= 0xE0; ! break; ! } ! cmd_array = CMD_STG170x; cmd_dest = &(tseng_regs->gendac.PLL_ctrl); + /* set PLL (input) range */ + dataclock = (vga256InfoRec.clock[mode->Clock] * ET4000.ChipClockMulFactor) / ET4000.ChipClockDivFactor; + if (dataclock <= 16000) + tseng_regs->gendac.timingctrl = 0; + else if (dataclock <= 32000) + tseng_regs->gendac.timingctrl = 1; + else if (dataclock <= 67500) + tseng_regs->gendac.timingctrl = 2; + else tseng_regs->gendac.timingctrl = 3; break; case ICS5341_DAC: ! case ICS5301_DAC: ! cmd_array = CMD_GENDAC; tseng_regs->gendac.PLL_ctrl = 0; cmd_dest = &(tseng_regs->gendac.cmd_reg); break; *************** *** 846,855 **** tseng_regs->ET6KVidCtrl1 |= 0x02; /* 5-6-5 RGB mode */ } break; } if (cmd_array != NULL) { ! switch (bytesperpixel) { case 1: index = 0; break; case 2: index = rgb555 ? 1 : 2; break; case 3: index = 3; break; --- 819,832 ---- tseng_regs->ET6KVidCtrl1 |= 0x02; /* 5-6-5 RGB mode */ } break; + case MUSIC4910_DAC: + cmd_array = CMD_MU4910; + cmd_dest = &(tseng_regs->ATTdac_cmd); + break; } if (cmd_array != NULL) { ! switch (local_bytesperpixel) { case 1: index = 0; break; case 2: index = rgb555 ? 1 : 2; break; case 3: index = 3; break; *************** *** 867,873 **** else { tseng_regs->gendac.cmd_reg = 0; ErrorF("%s %s: %dbpp not supported in %d-bit DAC mode on this RAMDAC -- Please report.\n", ! XCONFIG_PROBED, vga256InfoRec.name, bytesperpixel*8, dac16bit ? 16 : 8); } } --- 844,850 ---- else { tseng_regs->gendac.cmd_reg = 0; ErrorF("%s %s: %dbpp not supported in %d-bit DAC mode on this RAMDAC -- Please report.\n", ! XCONFIG_PROBED, vga256InfoRec.name, vgaBitsPerPixel, dac16bit ? 16 : 8); } } *** ./xfree86/vga256/drivers/mga/mga_bios.h@@/PUBLIC-LATEST Sat Jul 19 16:05:56 1997 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/mga/mga_bios.h Fri Mar 6 16:50:37 1998 *************** *** 1,11 **** ! /* $TOG: mga_bios.h /main/1 1997/07/19 16:05:58 kaleb $ */ #ifndef MGA_BIOS_H #define MGA_BIOS_H ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/mga/mga_bios.h,v 1.1.2.1 1997/05/09 09:09:07 hohndel Exp $ */ /* * MGABiosInfo - This struct describes the video BIOS info block. * * DESCRIPTION * Do not mess with this, unless you know what you are doing. --- 1,12 ---- ! /* $TOG: mga_bios.h /main/2 1998/03/06 16:52:15 kaleb $ */ #ifndef MGA_BIOS_H #define MGA_BIOS_H ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/mga/mga_bios.h,v 1.1.2.2 1998/02/01 16:05:11 robin Exp $ */ /* * MGABiosInfo - This struct describes the video BIOS info block. + * MGABios2Info - This struct describes the Myst, Mill II, and poss Mill 1 rev 3 * * DESCRIPTION * Do not mess with this, unless you know what you are doing. *************** *** 12,23 **** * The data lengths and types are critical. * * HISTORY * October 7, 1996 - [aem] Andrew E. Mileski * This struct was shamelessly stolen from the MGA DDK. * It has been reformatted, and the data types changed. */ typedef struct { ! /* Length of this structure in bytes */ CARD16 StructLen; /* --- 13,28 ---- * The data lengths and types are critical. * * HISTORY + * August 31, 1997 - [ajv] Andrew van der Stock + * Updated to reflected PINS 2.06 information from Matrox + * * October 7, 1996 - [aem] Andrew E. Mileski * This struct was shamelessly stolen from the MGA DDK. * It has been reformatted, and the data types changed. */ + typedef struct { ! /* Length of this structure in bytes */ CARD16 StructLen; /* *************** *** 108,113 **** CARD16 Reserved[ 3 ]; } MGABiosInfo; ! extern MGABiosInfo MGABios; #endif --- 113,151 ---- CARD16 Reserved[ 3 ]; } MGABiosInfo; ! /* from the PINS structure, refer pins info from MGA */ ! typedef struct tagParamMGA { ! CARD16 PinID; /* 0 */ ! CARD8 StructLen; /* 2 */ ! CARD8 Rsvd1; /* 3 */ ! CARD16 StructRev; /* 4 */ ! CARD16 ProgramDate; /* 6 */ ! CARD16 ProgramCnt; /* 8 */ ! CARD16 ProductID; /* 10 */ ! CARD8 SerNo[16]; /* 12 */ ! CARD8 PLInfo[6]; /* 28 */ ! CARD16 PCBInfo; /* 34 */ ! CARD32 FeatFlag; /* 36 */ ! CARD8 RamdacType; /* 40 */ ! CARD8 RamdacSpeed; /* 41 */ ! CARD8 PclkMax; /* 42 */ ! CARD8 ClkGE; /* 43 */ ! CARD8 ClkMem; /* 44 */ ! CARD8 Clk4MB; /* 45 */ ! CARD8 Clk8MB; /* 46 */ ! CARD8 ClkMod; /* 47 */ ! CARD8 TestClk; /* 48 */ ! CARD8 VGAFreq1; /* 49 */ ! CARD8 VGAFreq2; /* 50 */ ! CARD8 MCTLWTST; /* 51 */ ! CARD8 VidCtrl; /* 52 */ ! CARD8 Clk12MB; /* 53 */ ! CARD8 Clk16MB; /* 54 */ ! CARD8 Reserved[8]; /* 55-62 */ ! CARD8 PinCheck; /* 63 */ ! } MGABios2Info; ! ! extern MGABiosInfo MGABios; ! extern MGABios2Info MGABios2; #endif *** ./xfree86/vga256/drivers/mga/mga_dac1064.c@@/PUBLIC-LATEST Sun Aug 10 13:05:50 1997 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/mga/mga_dac1064.c Fri Mar 6 16:50:41 1998 *************** *** 1,12 **** ! /* $TOG: mga_dac1064.c /main/2 1997/08/10 13:04:26 kaleb $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/mga/mga_dac1064.c,v 1.1.2.8 1997/07/26 06:30:54 dawes Exp $ */ /* ! * Mystique RAMDAC driver v1.2 * * Author: Andrew van der Stock * ajv@greebo.svhm.org.au --- 1,12 ---- ! /* $TOG: mga_dac1064.c /main/3 1998/03/06 16:52:19 kaleb $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/mga/mga_dac1064.c,v 1.1.2.10 1998/02/07 10:05:26 hohndel Exp $ */ /* ! * Mystique RAMDAC driver v1.3 * * Author: Andrew van der Stock * ajv@greebo.svhm.org.au *************** *** 37,44 **** --- 37,48 ---- * g.desbief@aix.pacwan.net * RAMDAC timing, for MGA 1064SG integrated RAMDAC * + * Andrew van der Stock, andrew.van.der.Stock@member.sage-au.org.au + * MGA BIOS stuff + * */ + #include "compiler.h" #include "xf86.h" #include "xf86Priv.h" #include "xf86_OSlib.h" *************** *** 47,52 **** --- 51,57 ---- #include "vgaPCI.h" #include "mga_reg.h" + #include "mga_bios.h" #include "mga.h" /* *************** *** 102,107 **** --- 107,135 ---- 0x00, 0x00, 0x0D, 0xCA, 0x33, 0x58, 0xC2 }; + #ifdef PC98_MGA + static unsigned char PC98_MGADACbpp8[] = { + 0xFE, 0x03, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, + 0x3F, 0x43, 0x50, 0x00, 0x05, 0x09, 0x20, 0x19, + 0x10, 0x3f, 0x40, 0x00, 0x07, + 0x00, 0x00, 0x1C, 0xEE, 0x9A, 0x82, 0x5B + }; + + static unsigned char PC98_MGADACbpp16[] = { + 0xFE, 0x07, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, + 0x3F, 0x43, 0x50, 0x00, 0x02, 0x09, 0x20, 0x19, + 0x10, 0x3f, 0x40, 0x00, 0x07, + 0x00, 0x00, 0x1C, 0xEE, 0x9A, 0x82, 0x5B + }; + + static unsigned char PC98_MGADACbpp32[] = { + 0xFE, 0x07, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, + 0x2A, 0x02, 0x10, 0x00, 0x07, 0x09, 0x20, 0x19, + 0x10, 0x3f, 0x40, 0x00, 0x07, + 0x00, 0x00, 0x00, 0x0E, 0x9A, 0x80, 0x5A + }; + #endif /* PC98_MGA */ + /* * This is a convenience macro, so that entries in the driver structure * can simply be dereferenced with 'newVS->xxx'. *************** *** 121,130 **** * Read/write to the DAC via MMIO */ - /* - * Read/write to the DAC via MMIO - */ - void outMGA1064(reg, val) unsigned char reg, val; { --- 149,154 ---- *************** *** 174,181 **** --- 198,279 ---- OUTREG8(RAMDAC_OFFSET + reg, val); } + #ifdef PC98_MGA + /* + * MGA-1064SG for PC98 + * + * written by Isao OHISHI(X98 core team) + */ + static void MGA1064PC98Init() + { + int i; + long option_reg; + + outb(MGAREG_FIFOSTATUS, 0x6); + outb(MGAREG_VCOUNT, 0x6); + outb(MGAREG_Reset, 0x6); + + switch(vgaBitsPerPixel) + { + case 8: + outb(MGAREG_IEN,0xe5); + outb(0x1e3c,0xe5); + outb(0x1fff,0x02); + pciWriteLong( MGAPciTag, PCI_OPTION_REG, 0x1f094e21 ); + outMGA1064( MGA1064_SYS_PLL_M, 0x09 ); + outMGA1064( MGA1064_SYS_PLL_N, 0x73 ); + outMGA1064( MGA1064_SYS_PLL_P, 0x10 ); + for(i=0; i<sizeof(MGADACregs); i++) { + outMGA1064( MGADACregs[i], PC98_MGADACbpp8[i] ); + } + break; + case 16: + outb(MGAREG_IEN,0xd8); + outb(0x1e3c,0xd8); + outb(0x1fff,0x02); + pciWriteLong( MGAPciTag, PCI_OPTION_REG, 0x1f094e21 ); + outMGA1064( MGA1064_SYS_PLL_M, 0x09 ); + outMGA1064( MGA1064_SYS_PLL_N, 0x73 ); + outMGA1064( MGA1064_SYS_PLL_P, 0x10 ); + for(i=0; i<sizeof(MGADACregs); i++) { + outMGA1064( MGADACregs[i], PC98_MGADACbpp16[i] ); + } + break; + case 24: + /* not yet at all*/ /* + option_reg = pciReadLong(MGAPciTag, PCI_OPTION_REG); + ErrorF("pciReadLong = %x\n",option_reg); + ErrorF("MGA1064_SYS_PLL_M = %x\n",inMGA1064( MGA1064_SYS_PLL_M )); + ErrorF("MGA1064_SYS_PLL_N = %x\n",inMGA1064( MGA1064_SYS_PLL_N )); + ErrorF("MGA1064_SYS_PLL_P = %x\n",inMGA1064( MGA1064_SYS_PLL_P )); + for(i=0; i<sizeof(MGADACregs); i++) { + ErrorF("inMGA1064( %x ) = %x\n", MGADACregs[i], inMGA1064( MGADACregs[i] )); + } + */ + break; + case 32: + outb(MGAREG_IEN,0x75); + outb(0x1e3c,0x75); + outb(0x1fff,0x01); + pciWriteLong( MGAPciTag, PCI_OPTION_REG, 0x1f094e21 ); + outMGA1064( MGA1064_SYS_PLL_M, 0x09 ); + outMGA1064( MGA1064_SYS_PLL_N, 0x73 ); + outMGA1064( MGA1064_SYS_PLL_P, 0x10 ); + for(i=0; i<sizeof(MGADACregs); i++) { + outMGA1064( MGADACregs[i], PC98_MGADACbpp32[i] ); + } + break; + default: + FatalError("MGA: unsupported depth\n"); + } + + outb(MGAREG_MISC_WRITE, 0xd); + } + #endif /* PC98_MGA */ + + /* * MGA1064SGCalcClock - Calculate the PLL settings (m, n, p, s). * * DESCRIPTION *************** *** 354,363 **** /* The actual frequency output by the clock */ double f_pll; ! /* Get the maximum pixel clock frequency */ ! long f_max = MGA1064_MAX_PCLK_FREQ ; ! if ( vga256InfoRec.maxClock < MGA1064_MAX_PCLK_FREQ ) f_max = vga256InfoRec.maxClock; /* Do the calculations for m, n, and p */ --- 452,468 ---- /* The actual frequency output by the clock */ double f_pll; + long f_max; ! /* Get the maximum pixel clock frequency from the BIOS, ! * or from a reasonable default ! */ ! if ( MGABios2.PinID && MGABios2.PclkMax != 0xff ) ! f_max = (MGABios2.PclkMax+100) * 1000; /* [ajv - scale it] */ ! else ! f_max = MGA1064_MAX_PCLK_FREQ; ! ! if ( vga256InfoRec.maxClock < f_max ) f_max = vga256InfoRec.maxClock; /* Do the calculations for m, n, and p */ *************** *** 435,443 **** int pclk_m, pclk_n, pclk_p,pclk_s; int mclk_ctl, rfhcnt; long option_reg; f_pll = MGA1064SGCalcClock( ! f_out, MGA1064_MAX_MCLK_FREQ, & mclk_m, & mclk_n, & mclk_p ,& mclk_s ); --- 540,556 ---- int pclk_m, pclk_n, pclk_p,pclk_s; int mclk_ctl, rfhcnt; long option_reg; + long f_max; + /* ajv - get it from the bios, if it exists */ + + if (MGABios2.PinID) + f_max = MGABios2.ClkMem * 1000; + else + f_max = MGA1064_MAX_MCLK_FREQ; + f_pll = MGA1064SGCalcClock( ! f_out, f_max, & mclk_m, & mclk_n, & mclk_p ,& mclk_s ); *************** *** 498,506 **** rfhcnt = ( 332.0 * f_pll / 1280000.0 ); if ( rfhcnt > 15 ) rfhcnt = 0; - pciWriteLong( MGAPciTag, PCI_OPTION_REG, ( rfhcnt << 16 ) | - ( pciReadLong( MGAPciTag, PCI_OPTION_REG ) & ~0xf0000 )); #ifdef DEBUG ErrorF( "MGA1064SGSetMCLK: syspll_m=%x syspll_n=%x syspll_p=%x, option_reg=%x\n" ,inMGA1064( MGA1064_SYS_PLL_M ) --- 611,625 ---- rfhcnt = ( 332.0 * f_pll / 1280000.0 ); if ( rfhcnt > 15 ) rfhcnt = 0; + rfhcnt <<= 16; + + if(!OFLG_ISSET(OPTION_PCI_RETRY, &vga256InfoRec.options)) + rfhcnt |= (1 << 29); + + pciWriteLong( MGAPciTag, PCI_OPTION_REG, rfhcnt | + ( pciReadLong( MGAPciTag, PCI_OPTION_REG ) & ~0x200f0000 )); + #ifdef DEBUG ErrorF( "MGA1064SGSetMCLK: syspll_m=%x syspll_n=%x syspll_p=%x, option_reg=%x\n" ,inMGA1064( MGA1064_SYS_PLL_M ) *************** *** 574,579 **** --- 693,705 ---- vs = mode->CrtcVSyncStart - 1; ve = mode->CrtcVSyncEnd - 1; vt = mode->CrtcVTotal - 2; + + /* HTOTAL & 0xF equal to 0xE in 8bpp or 0x4 in 24bpp causes strange + * vertical stripes + */ + if((ht & 0x0F) == 0x0E || (ht & 0x0F) == 0x04) + ht++; + if (vgaBitsPerPixel == 24) wd = (vga256InfoRec.displayWidth * 3) >> (4 - MGABppShft); else *************** *** 607,612 **** --- 733,740 ---- else newVS->ExtVga[3] = ((1 << MGABppShft) - 1) | 0x80; + newVS->ExtVga[3] &= 0xE7; /* ajv - bits 4-5 MUST be 0 or bad karma happens */ + newVS->ExtVga[4] = 0; newVS->std.CRTC[0] = ht - 4; *************** *** 684,689 **** --- 812,821 ---- } newVS->DAClong = 0x5F094F21; + #ifdef PC98_MGA + MGA1064PC98Init(); + #endif + MGA1064SGSetPCLK( vga256InfoRec.clock[newVS->std.NoClock], 1 << MGABppShft ); *************** *** 873,881 **** MGA1064RamdacInit() { MGAdac.isHwCursor = FALSE; ! ! if (MGArev < 3) ! MGAdac.maxPixelClock = 170000; else ! MGAdac.maxPixelClock = 220000; } --- 1005,1021 ---- MGA1064RamdacInit() { MGAdac.isHwCursor = FALSE; ! ! if ( MGABios2.PinID ) ! { ! MGAdac.maxPixelClock = (MGABios2.RamdacSpeed+100) * 1000; ! ErrorF("Using BIOS value for maxPixelClock: %d kHz\n", MGAdac.maxPixelClock); ! } else ! { ! if ( MGArev < 3 ) ! MGAdac.maxPixelClock = 170000; ! else ! MGAdac.maxPixelClock = 220000; ! } } *** ./xfree86/vga256/drivers/mga/mga_dac3026.c@@/PUBLIC-LATEST Sun Aug 10 13:05:56 1997 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/mga/mga_dac3026.c Fri Mar 6 16:50:46 1998 *************** *** 1,8 **** ! /* $TOG: mga_dac3026.c /main/2 1997/08/10 13:04:32 kaleb $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/mga/mga_dac3026.c,v 1.1.2.3 1997/08/02 13:48:22 dawes Exp $ */ /* * Copyright 1994 by Robin Cutshaw <robin@XFree86.org> * --- 1,8 ---- ! /* $TOG: mga_dac3026.c /main/3 1998/03/06 16:52:23 kaleb $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/mga/mga_dac3026.c,v 1.1.2.10 1998/02/26 20:11:32 hohndel Exp $ */ /* * Copyright 1994 by Robin Cutshaw <robin@XFree86.org> * *************** *** 32,50 **** */ #include "xf86.h" #include "xf86Priv.h" #include "xf86_OSlib.h" #include "xf86_HWlib.h" #include "vga.h" #include "vgaPCI.h" #include "mga_bios.h" #include "mga_reg.h" #include "mga.h" /* Set to 1 if you want to set MCLK from XF86Config - AT YOUR OWN RISK! */ ! #define MCLK_FROM_XCONFIG 0 /* * exported functions --- 32,61 ---- */ + #include "compiler.h" #include "xf86.h" #include "xf86Priv.h" #include "xf86_OSlib.h" #include "xf86_HWlib.h" + #include "xf86cursor.h" #include "vga.h" #include "vgaPCI.h" + #ifdef PC98_MGA + #ifdef XFreeXDGA + #include "scrnintstr.h" + #include "servermd.h" + #define _XF86DGA_SERVER_ + #include "extensions/xf86dgastr.h" + #endif + #endif + #include "mga_bios.h" #include "mga_reg.h" #include "mga.h" /* Set to 1 if you want to set MCLK from XF86Config - AT YOUR OWN RISK! */ ! #define MCLK_FROM_XCONFIG 1 /* * exported functions *************** *** 53,58 **** --- 64,72 ---- Bool MGA3026Init(); void MGA3026Restore(); void* MGA3026Save(); + #ifdef PC98_MGA + void MGA3026Reset(); + #endif /* * implementation *************** *** 150,155 **** --- 164,290 ---- outTi3026dreg(TVP3026_DATA, tmp | val); } + #ifdef PC98_MGA + /* taken from vgaCmap.c */ + void + MGATi3026StoreColors(pmap, ndef, pdefs) + ColormapPtr pmap; + int ndef; + xColorItem *pdefs; + { + int i; + unsigned char *cmap, *tmp; + xColorItem directDefs[256]; + Bool new_overscan = FALSE; + unsigned char overscan = ((vgaHWPtr)vgaNewVideoState)->Attribute[OVERSCAN]; + unsigned char tmp_overscan; + + if (vgaCheckColorMap(pmap)) + return; + + if ((pmap->pVisual->class | DynamicClass) == DirectColor) + { + ndef = cfbExpandDirectColors (pmap, ndef, pdefs, directDefs); + pdefs = directDefs; + } + + for(i = 0; i < ndef; i++) + { + if (pdefs[i].pixel == overscan) + { + new_overscan = TRUE; + } + cmap = &((vgaHWPtr)vgaNewVideoState)->DAC[pdefs[i].pixel*3]; + if (vgaDAC8BitComponents) { + cmap[0] = pdefs[i].red >> 8; + cmap[1] = pdefs[i].green >> 8; + cmap[2] = pdefs[i].blue >> 8; + } + else { + cmap[0] = pdefs[i].red >> 10; + cmap[1] = pdefs[i].green >> 10; + cmap[2] = pdefs[i].blue >> 10; + } + + if (xf86VTSema + #ifdef XFreeXDGA + || ((vga256InfoRec.directMode & XF86DGADirectGraphics) + && !(vga256InfoRec.directMode & XF86DGADirectColormap)) + || (vga256InfoRec.directMode & XF86DGAHasColormap) + #endif + ) + { + outTi3026dreg(TVP3026_WADR_PAL, pdefs[i].pixel); + outTi3026dreg(TVP3026_COL_PAL, cmap[0]); + outTi3026dreg(TVP3026_COL_PAL, cmap[1]); + outTi3026dreg(TVP3026_COL_PAL, cmap[2]); + } + } + if (new_overscan) + { + new_overscan = FALSE; + for(i = 0; i < ndef; i++) + { + if (pdefs[i].pixel == overscan) + { + if ((pdefs[i].red != 0) || + (pdefs[i].green != 0) || + (pdefs[i].blue != 0)) + { + new_overscan = TRUE; + tmp_overscan = overscan; + tmp = &((vgaHWPtr)vgaNewVideoState)->DAC[pdefs[i].pixel*3]; + } + break; + } + } + if (new_overscan) + { + /* + * Find a black pixel, or the nearest match. + */ + for (i=255; i >= 0; i--) + { + cmap = &((vgaHWPtr)vgaNewVideoState)->DAC[i*3]; + if ((cmap[0] == 0) && (cmap[1] == 0) && (cmap[2] == 0)) + { + overscan = i; + break; + } + else + { + if ((cmap[0] < tmp[0]) && + (cmap[1] < tmp[1]) && (cmap[2] < tmp[2])) + { + tmp = cmap; + tmp_overscan = i; + } + } + } + if (i < 0) + { + overscan = tmp_overscan; + } + ((vgaHWPtr)vgaNewVideoState)->Attribute[OVERSCAN] = overscan; + if (xf86VTSema + #ifdef XFreeXDGA + || ((vga256InfoRec.directMode & XF86DGADirectGraphics) + && !(vga256InfoRec.directMode & XF86DGADirectColormap)) + || (vga256InfoRec.directMode&XF86DGAHasColormap) + #endif + ) + { + (void)inb(vgaIOBase + 0x0A); + outb(0x3C0, OVERSCAN); + outb(0x3C0, overscan); + (void)inb(vgaIOBase + 0x0A); + outb(0x3C0, 0x20); + } + } + } + } + #endif + /* * MGATi3026CalcClock - Calculate the PLL settings (m, n, p). * *************** *** 168,173 **** --- 303,311 ---- * p OUT Value of PLL 'p' register. * * HISTORY + * February 7, 1998 - Sebastien Marineau + * Minor improvement to the optimizer algorithm + * * January 11, 1997 - [aem] Andrew E. Mileski * Split off from MGATi3026SetClock. */ *************** *** 234,239 **** --- 372,383 ---- best_m = ( int ) calc_m; best_n = *n; } + if ((( - calc_m + 1.0 + ( int ) calc_m) < m_err ) && + ((int) calc_m < 64)) { + m_err = -calc_m + ( int ) calc_m + 1; + best_m = ( int ) calc_m + 1; + best_n = *n; + } } /* 65 - ( 65 - x ) = x */ *************** *** 315,332 **** while (( inTi3026( TVP3026_MEM_CLK_DATA ) & 0x40 ) == 0 ) { ; } ! /* Set the WRAM refresh divider */ ! rfhcnt = ( 332.0 * f_pll / 1280000.0 ); ! if ( rfhcnt > 15 ) rfhcnt = 0; ! pciWriteLong( MGAPciTag, PCI_OPTION_REG, ( rfhcnt << 16 ) | ! ( pciReadLong( MGAPciTag, PCI_OPTION_REG ) & ~0xf0000 )); #ifdef DEBUG ErrorF( "rfhcnt=%d\n", rfhcnt ); ! #endif /* Output MCLK PLL on MCLK pin */ outTi3026( TVP3026_MCLK_CTL, 0, ( mclk_ctl & 0xe7 ) | 0x10 ); outTi3026( TVP3026_MCLK_CTL, 0, ( mclk_ctl & 0xe7 ) | 0x18 ); --- 459,536 ---- while (( inTi3026( TVP3026_MEM_CLK_DATA ) & 0x40 ) == 0 ) { ; } ! /* Set the WRAM refresh divider */ ! /* these formulas assume nogscale=1; RTFM if gscale=0, esp. if ! * you are slowing the clocks for power-saving ! * Also note that the 1064SG seems to treat rfhcnt differently, ! * but it doesn't use this dac. ! */ ! if (MGAchipset == PCI_CHIP_MGA2064 ) ! { ! /* this one is from the 2064W manual. */ ! /* rfhcnt = (( (33.2 * f_pll) / 1000.0 ) / 128) - 1; */ ! /* changing to -.5 to get round-to-nearest approximation */ ! rfhcnt = (((33.2 * f_pll) / 1000.0 ) / 128.0) - .5; ! if ( rfhcnt > 15 ) ! { ! #ifdef DEBUG ! ErrorF( "error: rfhcnt=%d, setting to 0\n", rfhcnt ); ! #endif ! /* the 2064W manual implies that zero is OK (?) ! * "minimum frequency" is supposedly set to 4MHz ! * when rfhcnt=0 and nogscale=1 ! */ ! rfhcnt = 0; ! } ! } ! else /* 2164W PCI or AGP and default */ ! { ! /* this is calculated from the 2164W manual. It seems OK with ! * both the 2164W-AGP and a PCI 2064W. Barring algebra errors, ! * with expected rounding, this should be guaranteed to conform ! * to the formula from p.3-18 of the 2164W manual. ! */ ! rfhcnt = (( (33.2 * f_pll) / 1000.0 ) - 1) / 256; ! if ( rfhcnt > 15 ) ! { ! #ifdef DEBUG ! ErrorF( "error: rfhcnt=%d, setting to 15\n", rfhcnt ); ! #endif ! rfhcnt = 15; ! } ! #ifdef DEBUG /* paranoia check, neither should ever happen */ ! /* check formula from p. 3-18 of MGA-2164W manual ! * 33.2 >= (rfhcnt<3:1>*512 + rfhcnt<0>*64 + 1) * ! * gclk_period * gscaling_factor ! */ ! { ! double refresh_period = ((rfhcnt & 0xE)*256 + ! (rfhcnt & 1)*64 + 1) * ( 1000.0 / f_pll); ! if (! ( 33.2 >= refresh_period )) ! { ! ErrorF( "warning: rfhcnt=%d -> %lf usec > 33.2 usec\n", ! rfhcnt, refresh_period ); ! } ! } ! if ( rfhcnt == 0 ) ! ErrorF( "warning: 2164W memory refresh disabled!\n"); ! #endif ! } /* MGAchipset choice */ #ifdef DEBUG ErrorF( "rfhcnt=%d\n", rfhcnt ); ! #endif + rfhcnt <<= 16; + + if(!OFLG_ISSET(OPTION_PCI_RETRY, &vga256InfoRec.options)) + rfhcnt |= (1 << 29); + + pciWriteLong( MGAPciTag, PCI_OPTION_REG, rfhcnt | + ( pciReadLong( MGAPciTag, PCI_OPTION_REG ) & ~0x200f0000 )); + /* Output MCLK PLL on MCLK pin */ outTi3026( TVP3026_MCLK_CTL, 0, ( mclk_ctl & 0xe7 ) | 0x10 ); outTi3026( TVP3026_MCLK_CTL, 0, ( mclk_ctl & 0xe7 ) | 0x18 ); *************** *** 359,364 **** --- 563,571 ---- * vgaBitsPerPixel IN Bits per pixel. * * HISTORY + * February 7, 1998 - Sebastien Marineau + * Changes to 24 bpp PLL setup and changes for revision B Ramdacs + * * January 11, 1997 - [aem] Andrew E. Mileski * Split to simplify code for MCLK (=GCLK) setting. * *************** *** 393,403 **** --- 600,618 ---- /* The actual frequency output by the clock */ double f_pll; + /* The silicon revision of the 3026 */ + int s_rev; + /* Get the maximum pixel clock frequency */ long f_max = TI_MAX_VCO_FREQ; if ( vga256InfoRec.maxClock > TI_MAX_VCO_FREQ ) f_max = vga256InfoRec.maxClock; + /* Get the silicon revision */ + s_rev = inTi3026 (TVP3026_SILICON_REV); + #ifdef DEBUG + ErrorF("Found TVP3026 Rev. %c\n", ( s_rev > 0x20 ) ? 'B' : 'A' ); + #endif /* Do the calculations for m, n, and p */ f_pll = MGATi3026CalcClock( f_out, f_max, & m, & n, & p ); *************** *** 464,475 **** lq = ( int )( z / 1600.0 ); } ! /* Values for the loop clock PLL registers */ if ( vgaBitsPerPixel == 24 ) { /* Packed pixel mode values */ newVS->DACclk[ 3 ] = ( ln & 0x3f ) | 0x80; ! newVS->DACclk[ 4 ] = ( lm & 0x3f ) | 0x80; ! newVS->DACclk[ 5 ] = ( lp & 0x03 ) | 0xf8; } else { /* Non-packed pixel mode values */ newVS->DACclk[ 3 ] = ( ln & 0x3f ) | 0xc0; --- 679,722 ---- lq = ( int )( z / 1600.0 ); } ! /* ! * Values for the loop clock PLL registers ! * ! * [SM] We have changes for 24bpp modes ! * for 3026B in 4:3 multiplex modes (see updated ! * TI document). Also, the corruption problem seen ! * for high pixel rates at 8:3 multiplex ratios is fixed ! * by clearing bit 6 of the loop clock p register. ! */ if ( vgaBitsPerPixel == 24 ) { + int setbits; /* Packed pixel mode values */ newVS->DACclk[ 3 ] = ( ln & 0x3f ) | 0x80; ! /* Set m-value depending on silicon rev. and multiplex */ ! if (( bpp == 2 ) && ( s_rev > 0x20 )) ! newVS->DACclk[ 4 ] = ( lm & 0x3f ) | 0x00; ! else ! newVS->DACclk[ 4 ] = ( lm & 0x3f ) | 0x80; ! /* Clear bit 6 of p if high dot clock at 8:3 ratio ! * this seems to be necessary for 8MB or below, but ! * wrong for 16MB cards; to be on the save side we ! * have an option to flip the bit [SM,DHH] ! */ ! if ((MGAchipset == PCI_CHIP_MGA2164 ) && ! ( vga256InfoRec.videoRam <= 8192 )) ! setbits = 0xb8; ! else ! setbits = 0xf8; ! if (OFLG_ISSET(OPTION_MGA_24BPP_FIX, &vga256InfoRec.options)) ! setbits ^= 0x40; ! #ifdef DEBUG ! ErrorF("PLL bits set to 0x%2x\n",setbits); ! #endif ! if (( bpp == 1) && ( f_pll > 100000 )) ! newVS->DACclk[ 5 ] = ( lp & 0x03 ) | setbits; ! else ! newVS->DACclk[ 5 ] = ( lp & 0x03 ) | 0xf8; ! } else { /* Non-packed pixel mode values */ newVS->DACclk[ 3 ] = ( ln & 0x3f ) | 0xc0; *************** *** 478,483 **** --- 725,734 ---- } newVS->DACreg[ 18 ] = lq | 0x38; + /* Finally, adjust latch-control register for 24bpp, 4:3, rev. B */ + if (( vgaBitsPerPixel == 24 ) && ( bpp == 2 ) && ( s_rev > 0x20 )) + newVS->DACreg[ 0 ] = 0x08; + #ifdef DEBUG ErrorF( "bpp=%d z=%.1f ln=%d lm=%d lp=%d lq=%d\n", bpp, z, ln, lm, lp, lq ); *************** *** 543,548 **** --- 794,806 ---- vs = mode->CrtcVSyncStart - 1; ve = mode->CrtcVSyncEnd - 1; vt = mode->CrtcVTotal - 2; + + /* HTOTAL & 0xF equal to 0xE in 8bpp or 0x4 in 24bpp causes strange + * vertical stripes + */ + if((ht & 0x0F) == 0x0E || (ht & 0x0F) == 0x04) + ht++; + if (vgaBitsPerPixel == 24) wd = (vga256InfoRec.displayWidth * 3) >> (4 - MGABppShft); else *************** *** 581,587 **** newVS->ExtVga[3] = ((1 << MGABppShft) - 1) | 0x80; /* Set viddelay (CRTCEXT3 Bits 3-4). */ ! newVS->ExtVga[3] |= (vga256InfoRec.videoRam == 8192 ? 0x10 : vga256InfoRec.videoRam == 2048 ? 0x08 : 0x00); newVS->ExtVga[4] = 0; --- 839,845 ---- newVS->ExtVga[3] = ((1 << MGABppShft) - 1) | 0x80; /* Set viddelay (CRTCEXT3 Bits 3-4). */ ! newVS->ExtVga[3] |= (vga256InfoRec.videoRam >= 8192 ? 0x10 : vga256InfoRec.videoRam == 2048 ? 0x08 : 0x00); newVS->ExtVga[4] = 0; *************** *** 707,712 **** --- 965,975 ---- * goes here. */ + /* + * this is needed to properly restore start address for 2164W-AGP + */ + outw(0x3DE, (restore->ExtVga[0] << 8) | 0); + /* program pixel clock PLL */ outTi3026(TVP3026_PLL_ADDR, 0, 0x00); for (i = 0; i < 3; i++) *************** *** 816,900 **** * (plane 0) maps to cursor colors 0 and 1 */ - #define MAX_CURS_HEIGHT 64 /* 64 scan lines */ - #define MAX_CURS_WIDTH 64 /* 64 pixels */ - static pointer - MGA3026RealizeCursor(pSource, pMask, w, h) - unsigned char *pSource, *pMask; - int w, h; - { - register int i, j; - unsigned char *ram, *plane0, *plane1; - - ram = (unsigned char *)xalloc(1024); - plane0 = ram; - plane1 = ram+512; - - if (!ram) - return NULL; - - for (i = 0; i < MAX_CURS_HEIGHT; i++) { - for (j = 0; j < MAX_CURS_WIDTH / 8; j++) { - unsigned char mask, source; - - if (i < h && j < w) { - source = byte_reversed[*pSource++]; - mask = byte_reversed[*pMask++]; - *plane0++ = source & mask; - *plane1++ = mask; - } else { - *plane0++ = 0x00; - *plane1++ = 0x00; - } - } - /* - * if we still have more bytes on this line (j < w), - * we have to ignore the rest of the line. - */ - while (j++ < w) pSource++,pMask++; - } - return ram; - } - - /* - * LoadCursor(src) - * src - pointer returned by RealizeCursor - */ static void ! MGA3026LoadCursor(src) ! unsigned char *src; { register int i; ! outTi3026(TVP3026_CURSOR_CTL, 0xf3, 0x00); /* reset A9,A8 */ /* reset cursor RAM load address A7..A0 */ outTi3026dreg(TVP3026_WADR_PAL, 0x00); ! /* ! * Output the cursor data. The realize function has put the planes into ! * their correct order, so we can just blast this out. ! */ ! for (i = 0; i < 1024; i++) ! outTi3026dreg(TVP3026_CUR_RAM, (*src++)); } - static void - MGA3026QueryCursorSize(pwidth, pheight) - unsigned short *pwidth, *pheight; - { - *pwidth = MAX_CURS_WIDTH; - *pheight = MAX_CURS_HEIGHT; - } - - static Bool - MGA3026CursorState() - { - return (inTi3026(TVP3026_CURSOR_CTL) & 0x03); - } - static void ! MGA3026CursorOn() { /* Enable cursor - X11 mode */ outTi3026(TVP3026_CURSOR_CTL, 0x6c, 0x13); --- 1079,1105 ---- * (plane 0) maps to cursor colors 0 and 1 */ static void ! MGA3026LoadCursorImage(src, xorigin, yorigin) ! register unsigned char *src; ! int xorigin, yorigin; { register int i; ! register unsigned char *mask = src + 1; ! outTi3026(TVP3026_CURSOR_CTL, 0xf3, 0x00); /* reset A9,A8 */ /* reset cursor RAM load address A7..A0 */ outTi3026dreg(TVP3026_WADR_PAL, 0x00); ! for (i = 0; i < 512; i++, mask+=2) ! outTi3026dreg(TVP3026_CUR_RAM, *mask); ! for (i = 0; i < 512; i++, src+=2) ! outTi3026dreg(TVP3026_CUR_RAM, *src); } static void ! MGA3026ShowCursor() { /* Enable cursor - X11 mode */ outTi3026(TVP3026_CURSOR_CTL, 0x6c, 0x13); *************** *** 901,907 **** } static void ! MGA3026CursorOff() { /* Disable cursor */ outTi3026(TVP3026_CURSOR_CTL, 0xfc, 0x00); --- 1106,1112 ---- } static void ! MGA3026HideCursor() { /* Disable cursor */ outTi3026(TVP3026_CURSOR_CTL, 0xfc, 0x00); *************** *** 908,921 **** } static void ! MGA3026MoveCursor(x, y) int x, y; { ! x += 64; ! y += 64; ! if (x < 0 || y < 0) ! return; ! /* Output position - "only" 12 bits of location documented */ outTi3026dreg(TVP3026_CUR_XLOW, x & 0xFF); --- 1113,1127 ---- } static void ! MGA3026SetCursorPosition(x, y, xorigin, yorigin) int x, y; { ! if(vga256InfoRec.modes->Flags & V_DBLSCAN) ! y *= 2; ! ! x += 64 - xorigin; ! y += 64 - yorigin; ! /* Output position - "only" 12 bits of location documented */ outTi3026dreg(TVP3026_CUR_XLOW, x & 0xFF); *************** *** 925,996 **** } static void ! MGA3026RecolorCursor(red0, green0, blue0, red1, green1, blue1) ! int red0, green0, blue0, red1, green1, blue1; { /* The TI 3026 cursor is always 8 bits so shift 8, not 10 */ /* Background color */ outTi3026dreg(TVP3026_CUR_COL_ADDR, 1); ! outTi3026dreg(TVP3026_CUR_COL_DATA, (red0 >> 8) & 0xFF); ! outTi3026dreg(TVP3026_CUR_COL_DATA, (green0 >> 8) &0xFF); ! outTi3026dreg(TVP3026_CUR_COL_DATA, (blue0 >> 8) & 0xFF); /* Foreground color */ outTi3026dreg(TVP3026_CUR_COL_ADDR, 2); ! outTi3026dreg(TVP3026_CUR_COL_DATA, (red1 >> 8) & 0xFF); ! outTi3026dreg(TVP3026_CUR_COL_DATA, (green1 >> 8) &0xFF); ! outTi3026dreg(TVP3026_CUR_COL_DATA, (blue1 >> 8) & 0xFF); } void MGA3026RamdacInit() { ! MGAdac.isHwCursor = TRUE; ! MGAdac.RealizeCursor = MGA3026RealizeCursor; ! MGAdac.LoadCursor = MGA3026LoadCursor; ! MGAdac.QueryCursorSize = MGA3026QueryCursorSize; ! MGAdac.CursorState = MGA3026CursorState; ! MGAdac.CursorOn = MGA3026CursorOn; ! MGAdac.CursorOff = MGA3026CursorOff; ! MGAdac.MoveCursor = MGA3026MoveCursor; ! MGAdac.RecolorCursor = MGA3026RecolorCursor; ! switch( MGABios.RamdacType & 0xff ) { ! case 1: MGAdac.maxPixelClock = 220000; ! break; ! case 2: MGAdac.maxPixelClock = 250000; ! break; ! default: ! MGAdac.maxPixelClock = 175000; ! break; } - - /* Set MCLK based on amount of memory */ - if ( vga256InfoRec.videoRam < 4096 ) - MGAdac.MemoryClock = MGABios.ClkBase * 10; - else if ( vga256InfoRec.videoRam < 8192 ) - MGAdac.MemoryClock = MGABios.Clk4MB * 10; else ! MGAdac.MemoryClock = MGABios.Clk8MB * 10; ! /* XXX ajv need to have more details about Mill II */ ! /* this catches the case where the ROM is being probed and the ROM's layout ! is new (ie overridden) and we don't have a clue. It's just a safe value, ! and should be taken out asap we get documentation */ ! /* Actually, having some save range here isn't all that a bad idea; ! between 40 and 100 MHz sounds reasonable (dhh) */ ! if ( (MGAdac.MemoryClock < 40000.0) || ! (MGAdac.MemoryClock >100000.0) ) ! MGAdac.MemoryClock = 50000.0; /* XXX hack hack hack */ #if MCLK_FROM_XCONFIG /* or get it from XF86Config */ ! if (vga256InfoRec.MemClk) MGAdac.MemoryClock = vga256InfoRec.MemClk; #endif ! MGATi3026SetMCLK( MGAdac.MemoryClock ); } --- 1131,1373 ---- } static void ! MGA3026SetCursorColors(bg, fg) ! int bg, fg; { /* The TI 3026 cursor is always 8 bits so shift 8, not 10 */ /* Background color */ outTi3026dreg(TVP3026_CUR_COL_ADDR, 1); ! outTi3026dreg(TVP3026_CUR_COL_DATA, (bg & 0x00FF0000) >> 16); ! outTi3026dreg(TVP3026_CUR_COL_DATA, (bg & 0x0000FF00) >> 8); ! outTi3026dreg(TVP3026_CUR_COL_DATA, (bg & 0x000000FF)); /* Foreground color */ outTi3026dreg(TVP3026_CUR_COL_ADDR, 2); ! outTi3026dreg(TVP3026_CUR_COL_DATA, (fg & 0x00FF0000) >> 16); ! outTi3026dreg(TVP3026_CUR_COL_DATA, (fg & 0x0000FF00) >> 8); ! outTi3026dreg(TVP3026_CUR_COL_DATA, (fg & 0x000000FF)); } + void MGA3026RamdacInit() { ! MGAdac.isHwCursor = TRUE; ! MGAdac.CursorMaxWidth = 64; ! MGAdac.CursorMaxHeight = 64; ! MGAdac.SetCursorColors = MGA3026SetCursorColors; ! MGAdac.SetCursorPosition = MGA3026SetCursorPosition; ! MGAdac.LoadCursorImage = MGA3026LoadCursorImage; ! MGAdac.HideCursor = MGA3026HideCursor; ! MGAdac.ShowCursor = MGA3026ShowCursor; ! MGAdac.CursorFlags = USE_HARDWARE_CURSOR | ! HARDWARE_CURSOR_BIT_ORDER_MSBFIRST | ! HARDWARE_CURSOR_TRUECOLOR_AT_8BPP | ! HARDWARE_CURSOR_PROGRAMMED_ORIGIN | ! HARDWARE_CURSOR_AND_SOURCE_WITH_MASK | ! HARDWARE_CURSOR_CHAR_BIT_FORMAT | ! HARDWARE_CURSOR_PROGRAMMED_BITS; ! ! if ( MGAchipset == PCI_CHIP_MGA2064 && MGABios2.PinID == 0 ) { ! switch( MGABios.RamdacType & 0xff ) ! { ! case 1: MGAdac.maxPixelClock = 220000; ! break; ! case 2: MGAdac.maxPixelClock = 250000; ! break; ! default: ! MGAdac.maxPixelClock = 175000; ! break; ! } ! /* Set MCLK based on amount of memory */ ! if ( vga256InfoRec.videoRam < 4096 ) ! MGAdac.MemoryClock = MGABios.ClkBase * 10; ! else if ( vga256InfoRec.videoRam < 8192 ) ! MGAdac.MemoryClock = MGABios.Clk4MB * 10; ! else ! MGAdac.MemoryClock = MGABios.Clk8MB * 10; } else ! { ! if ( MGABios2.PinID ) /* make sure BIOS is available */ ! { ! if ( MGABios2.PclkMax != 0xff ) ! { ! MGAdac.maxPixelClock = (MGABios2.PclkMax + 100) * 1000; ! } ! else ! MGAdac.maxPixelClock = 220000; ! /* make sure we are not overdriving the GE for the amount of WRAM */ ! switch ( vga256InfoRec.videoRam ) ! { ! case 4096: ! if (MGABios2.Clk4MB != 0xff) ! MGABios2.ClkGE = MGABios2.Clk4MB; ! break; ! case 8192: ! if (MGABios2.Clk8MB != 0xff) ! MGABios2.ClkGE = MGABios2.Clk8MB; ! break; ! case 12288: ! if (MGABios2.Clk12MB != 0xff) ! MGABios2.ClkGE = MGABios2.Clk12MB; ! break; ! case 16384: ! if (MGABios2.Clk16MB != 0xff) ! MGABios2.ClkGE = MGABios2.Clk16MB; ! break; ! default: ! break; ! } ! #if DEBUG ! ErrorF("ClkGE %d ClkMem %d\n",MGABios2.ClkGE,MGABios2.ClkMem); ! #endif ! if ( MGABios2.ClkGE != 0xff && MGABios2.ClkMem == 0xff ) ! MGABios2.ClkMem = MGABios2.ClkGE; ! else if ( MGABios2.ClkGE == 0xff && MGABios2.ClkMem != 0xff ) ! ; /* don't need to do anything */ ! else if ( MGABios2.ClkGE == MGABios2.ClkMem && MGABios2.ClkGE != 0xff ) ! MGABios2.ClkMem = MGABios2.ClkGE; ! else ! MGABios2.ClkMem = 60; + MGAdac.MemoryClock = MGABios2.ClkMem * 1000; + + } /* BIOS enabled initialization */ + else + { + /* bios is not available, initialize to rational figures */ + MGAdac.MemoryClock = 60000; /* 60 MHz WRAM */ + MGAdac.maxPixelClock = 220000; /* 220 MHz */ + } + } /* 2164 specific initialization */ + #if MCLK_FROM_XCONFIG /* or get it from XF86Config */ ! if (vga256InfoRec.MemClk) { MGAdac.MemoryClock = vga256InfoRec.MemClk; + #if DEBUG + ErrorF("From XF86Config MemoryClock %d\n",MGAdac.MemoryClock); #endif ! } ! #endif ! ! /* safety check. Too slow = corruption, too fast = smoking chips */ ! /* 40 MHz (=40000) is a little slower, 50 MHz is safe (and the default */ ! /* 60 MHz is pushing it (YMMV), and > 65 is in Danger Will Robinson territory */ ! ! if ( (MGAdac.MemoryClock < 40000) || ! (MGAdac.MemoryClock > 70000) ) ! MGAdac.MemoryClock = 50000; ! ! #if DEBUG ! ErrorF("Setting MemoryClock %d\n",MGAdac.MemoryClock); ! #endif MGATi3026SetMCLK( MGAdac.MemoryClock ); } + + #ifdef PC98_MGA + void + MGA3026Reset() + { + static unsigned char initcrtc[] = { + 0x60, 0x4f, 0x50, 0x83, 0x55, 0x81, 0xbf, 0x1f, + 0x00, 0x4f, 0x0e, 0x2f, 0x00, 0x00, 0xff, 0xff, + 0x9c, 0x0e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, + 0xff + }; + static unsigned char initcrtcext[] = { + 0x00, 0x00, 0x00, 0x80, 0x00, 0x00 + }; + + unsigned char tmp; + int i; + + /* select CLK0 as clock source */ + outTi3026(TVP3026_CLK_SEL, 0, 0x77); + + /* select VGA mode */ + outTi3026(TVP3026_TRUE_COLOR_CTL, 0, 0x80); + outTi3026(TVP3026_MUX_CTL, 0, 0x98); + + /* set loop and pixel clock PLL PLLEN bits to 0 */ + outTi3026(TVP3026_PLL_ADDR, 0, 0x2A); + outTi3026(TVP3026_LOAD_CLK_DATA, 0, 0); + outTi3026(TVP3026_PIX_CLK_DATA, 0, 0); + + /* select 28MHz fixed clock */ + outb(0x3C2, 0x6D); /* once select PLL */ + outb(0x3C2, 0x65); /* then select 28MHz */ + + /* Pixel clock PLL routed to RCLK */ + outTi3026(TVP3026_MCLK_CTL, 0, 0x18); + + /* set MCLK */ + MGA3026RamdacInit(); + + /* nogscale=1 */ + pciWriteLong(MGAPciTag, PCI_OPTION_REG, 0x002C0000); + + /* mgamode=1 */ + outb(0x3DE, 0x03); /* Select CRTCEXT3 */ + tmp = inb(0x3DF); + outb(0x3DF, tmp | 0x80); + + /* screen off */ + outb(0x3C4, 0x01); /* Select SEQ1 */ + tmp = inb(0x3C5); + outb(0x3C5, tmp | 0x20); + + /* unprotect CRTC registers 0-7 */ + outb(0x3D4, 0x11); + outb(0x3D5, 0x2f); + + /* set initial CRTC regs value */ + for (i = 0; i <= 24; i++) { + outb(0x3D4, i); + outb(0x3D5, initcrtc[i]); + } + + /* set initial CRTCEXT regs value */ + for (i=0; i<=5; i++) { + outb(0x3DE, i); + outb(0x3DF, initcrtcext[i]); + } + + /* assert soft reset */ + OUTREG(MGAREG_Reset, 1); + usleep(250); + OUTREG(MGAREG_Reset, 0); + usleep(250); + + /* wait vertical retrace */ + while ((inb(0x3DA) & 0x08) != 0x08); + + /* screen on */ + outb(0x3C4, 0x01); /* Select SEQ1 */ + tmp = inb(0x3C5); + outb(0x3C5, tmp & ~0x20); + + /* wait vertical retrace */ + while ((inb(0x3DA) & 0x08) != 0x08); + + /* set memreset */ + OUTREG(MGAREG_MACCESS, 0x00008000); + usleep(100); + + /* screen off */ + outb(0x3C4, 0x01); /* Select SEQ1 */ + tmp = inb(0x3C5); + outb(0x3C5, tmp | 0x20); + + /* disable HSYNC,VSYNC */ + outb(0x3DE, 0x01); /* Select CRTCEXT1 */ + tmp = inb(0x3DF); + outb(0x3DF, tmp | 0x30); + } + #endif *** ./xfree86/vga256/drivers/mga/mga_driver.c@@/PUBLIC-LATEST Sun Aug 10 13:06:02 1997 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/mga/mga_driver.c Fri Mar 6 16:50:51 1998 *************** *** 1,4 **** ! /* $TOG: mga_driver.c /main/2 1997/08/10 13:04:40 kaleb $ */ /* * MGA Millennium (MGA2064W) with Ti3026 RAMDAC driver v.1.1 * --- 1,4 ---- ! /* $TOG: mga_driver.c /main/3 1998/03/06 16:52:29 kaleb $ */ /* * MGA Millennium (MGA2064W) with Ti3026 RAMDAC driver v.1.1 * *************** *** 17,23 **** * Contributors: * Andrew Vanderstock, Melbourne, Australia * vanderaj@mail2.svhm.org.au ! * additions, corrections, cleanups, Mill II early support * * Dirk Hohndel * hohndel@XFree86.Org --- 17,23 ---- * Contributors: * Andrew Vanderstock, Melbourne, Australia * vanderaj@mail2.svhm.org.au ! * additions, corrections, cleanups, Mill II and BIOS stuff * * Dirk Hohndel * hohndel@XFree86.Org *************** *** 37,43 **** * Support for 8MB boards, RGB Sync-on-Green, and DPMS. */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/mga/mga_driver.c,v 1.1.2.20 1997/08/02 13:48:22 dawes Exp $ */ #include "X.h" #include "input.h" --- 37,43 ---- * Support for 8MB boards, RGB Sync-on-Green, and DPMS. */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/mga/mga_driver.c,v 1.1.2.24 1998/02/24 19:06:00 hohndel Exp $ */ #include "X.h" #include "input.h" *************** *** 70,81 **** extern vgaPCIInformation *vgaPCIInfo; ! #define DEFAULT_SW_CURSOR /* * Driver data structures. */ MGABiosInfo MGABios; pciTagRec MGAPciTag; int MGAchipset; int MGArev; --- 70,87 ---- extern vgaPCIInformation *vgaPCIInfo; ! /* #define DEFAULT_SW_CURSOR */ /* * Driver data structures. */ + #ifdef PC98_MGA + pointer mmioBase = NULL; + #endif + MGABiosInfo MGABios; + MGABios2Info MGABios2; + pciTagRec MGAPciTag; int MGAchipset; int MGArev; *************** *** 105,110 **** --- 111,120 ---- static int MGALinearOffset(); static void MGADisplayPowerManagementSet(); + #ifdef PC98_MGA + extern void MGATi3026StoreColors(); + #endif + /* * This data structure defines the driver itself. */ *************** *** 210,238 **** * to pixel clocks. This is rarely used, and in most cases, set * it to 1. */ ! 1, /* ChipClockMulFactor */ ! 1 /* ChipClockDivFactor */ }; ! /* ! * ramdac info structure initialization ! */ MGARamdacRec MGAdac = { ! FALSE, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ! 90000, /* maxPixelClock */ ! 0 }; - /* - * array of ports - */ - static unsigned mgaExtPorts[] = - { - 0x400 /* This is enough to enable all ports */ - }; - static int Num_mgaExtPorts = - (sizeof(mgaExtPorts)/sizeof(mgaExtPorts[0])); /* * MGAReadBios - Read the video BIOS info block. --- 220,237 ---- * to pixel clocks. This is rarely used, and in most cases, set * it to 1. */ ! 1, /* ClockMulFactor */ ! 1 /* ClockDivFactor */ }; ! MGARamdacRec MGAdac = { ! FALSE, 0, 0, 0, NULL, NULL, NULL, NULL, NULL, ! 90000, /* maxPixelClock */ ! 0 }; /* * MGAReadBios - Read the video BIOS info block. *************** *** 248,253 **** --- 247,255 ---- * MGABios OUT The video BIOS info block. * * HISTORY + * August 31, 1997 - [ajv] Andrew van der Stock + * Fixed to understand Mystique and Millennium II + * * January 11, 1997 - [aem] Andrew E. Mileski * Set default values for GCLK (= MCLK / pre-scale ). * *************** *** 254,274 **** * October 7, 1996 - [aem] Andrew E. Mileski * Written and tested. */ static void MGAReadBios() { ! CARD8 tmp[ 64 ]; ! CARD16 offset; int i; /* Make sure the BIOS is present */ xf86ReadBIOS( vga256InfoRec.BIOSbase, 0, tmp, sizeof( tmp )); ! if ( ! tmp[ 0 ] != 0x55 ! || tmp[ 1 ] != 0xaa ! || strncmp(( char * )( tmp + 45 ), "MATROX", 6 ) ! ) { ! ErrorF( "%s %s: Video BIOS info block not detected!" ); return; } --- 256,279 ---- * October 7, 1996 - [aem] Andrew E. Mileski * Written and tested. */ + static void MGAReadBios() { ! CARD8 tmp[ 64 ]; ! CARD16 offset; ! CARD8 chksum; ! CARD8 *pPINSInfo; int i; /* Make sure the BIOS is present */ xf86ReadBIOS( vga256InfoRec.BIOSbase, 0, tmp, sizeof( tmp )); ! ! if ( tmp[ 0 ] != 0x55 || tmp[ 1 ] != 0xaa ! || strncmp(( char * )( tmp + 45 ), "MATROX", 6 ) ) ! { ! ErrorF( "%s %s: Video BIOS info block not detected!\n", ! XCONFIG_PROBED, vga256InfoRec.name); return; } *************** *** 276,297 **** xf86ReadBIOS( vga256InfoRec.BIOSbase, 0x7ffc, ( CARD8 * ) & offset, sizeof( offset )); - /* Copy the info block */ - xf86ReadBIOS( vga256InfoRec.BIOSbase, offset, - ( CARD8 * ) & MGABios.StructLen, sizeof( MGABios )); - /* Let the world know what we are up to */ ErrorF( "%s %s: Video BIOS info block at 0x%08lx\n", XCONFIG_PROBED, vga256InfoRec.name, vga256InfoRec.BIOSbase + offset ); ! /* Set default MCLK values (scaled by 10 kHz) */ ! if ( MGABios.ClkBase == 0 ) MGABios.ClkBase = 4500; ! if ( MGABios.Clk4MB == 0 ) MGABios.Clk4MB = MGABios.ClkBase; ! if ( MGABios.Clk8MB == 0 ) MGABios.Clk8MB = MGABios.Clk4MB; } /* --- 281,370 ---- xf86ReadBIOS( vga256InfoRec.BIOSbase, 0x7ffc, ( CARD8 * ) & offset, sizeof( offset )); /* Let the world know what we are up to */ ErrorF( "%s %s: Video BIOS info block at 0x%08lx\n", XCONFIG_PROBED, vga256InfoRec.name, vga256InfoRec.BIOSbase + offset ); ! /* Copy the info block */ ! switch (MGAchipset) ! { ! case PCI_CHIP_MGA2064: ! xf86ReadBIOS( vga256InfoRec.BIOSbase, offset, ! ( CARD8 * ) & MGABios.StructLen, sizeof( MGABios )); ! break; ! ! default: ! xf86ReadBIOS( vga256InfoRec.BIOSbase, offset, ! ( CARD8 * ) & MGABios2.PinID, sizeof( MGABios2 )); ! } ! ! /* matrox millennium-2 and mystique pins info */ ! if ( MGABios2.PinID == 0x412e ) ! { ! /* check that the pins info is correct */ ! if ( MGABios2.StructLen != 0x40 ) ! { ! ErrorF( "%s %s: Video BIOS info block not detected!\n", ! XCONFIG_PROBED, vga256InfoRec.name); ! return; ! } ! /* check that the chksum is correct */ ! chksum = 0; ! pPINSInfo = (CARD8 *) &MGABios2.PinID; ! ! for (i=0; i < MGABios2.StructLen; i++) ! { ! chksum += *pPINSInfo; ! pPINSInfo++; ! } ! ! if ( chksum ) ! { ! ErrorF("%s %s: Video BIOS info block did not checksum!\n", ! XCONFIG_PROBED, vga256InfoRec.name); ! MGABios2.PinID = 0; ! return; ! } ! ! /* last check */ ! if ( MGABios2.StructRev == 0 ) ! { ! ErrorF( "%s %s: Video BIOS info block does not have a valid revision!\n", ! XCONFIG_PROBED, vga256InfoRec.name); ! MGABios2.PinID = 0; ! return; ! } ! ErrorF( "%s %s: Found and verified enhanced Video BIOS info block\n", ! XCONFIG_PROBED, vga256InfoRec.name); ! ! #if DEBUG ! ErrorF( "%s %s: MClk %d Clk4MB %d Clk8MB %d\n", ! XCONFIG_PROBED, vga256InfoRec.name, ! MGABios2.ClkMem,MGABios2.Clk4MB,MGABios2.Clk8MB); ! #endif ! /* Set default MCLK values (scaled by 100 kHz) */ ! if ( MGABios2.ClkMem == 0 ) ! MGABios2.ClkMem = 50; ! if ( MGABios2.Clk4MB == 0 ) ! MGABios2.Clk4MB = MGABios.ClkBase; ! if ( MGABios2.Clk8MB == 0 ) ! MGABios2.Clk8MB = MGABios.Clk4MB; ! MGABios.StructLen = 0; /* not in use */ ! return; ! } ! else ! { ! /* Set default MCLK values (scaled by 10 kHz) */ ! if ( MGABios.ClkBase == 0 ) MGABios.ClkBase = 4500; ! if ( MGABios.Clk4MB == 0 ) MGABios.Clk4MB = MGABios.ClkBase; ! if ( MGABios.Clk8MB == 0 ) MGABios.Clk8MB = MGABios.Clk4MB; + MGABios2.PinID = 0; /* not in use */ + return; + } } /* *************** *** 298,315 **** * MGACountRAM -- * * Counts amount of installed RAM */ static int ! MGACountRam() { if(MGA.ChipLinearBase) { volatile unsigned char* base; ! unsigned char tmp, tmp3, tmp5; base = xf86MapVidMem(vga256InfoRec.scrnIndex, LINEAR_REGION, (pointer)((unsigned long)MGA.ChipLinearBase), ! 8192 * 1024); /* turn MGA mode on - enable linear frame buffer (CRTCEXT3) */ outb(0x3DE, 3); --- 371,399 ---- * MGACountRAM -- * * Counts amount of installed RAM + * + * now counts in 2 MB increments, all the way to 16 MB. + * also preserves fb contents, - ajv 970830 + * + * blocks = # of 2 MB blocks to check. = 4 on 8 MB addr, =8 on 16 MB addr */ + static int ! MGACountRam(int blocks) { + int videoMem; + + videoMem = 2048; + if(MGA.ChipLinearBase) { volatile unsigned char* base; ! int i, basePtr; ! unsigned char tmp, seed, oldMem, cacheMem, newMem[8]; base = xf86MapVidMem(vga256InfoRec.scrnIndex, LINEAR_REGION, (pointer)((unsigned long)MGA.ChipLinearBase), ! blocks * 2097152 ); /* turn MGA mode on - enable linear frame buffer (CRTCEXT3) */ outb(0x3DE, 3); *************** *** 317,341 **** outb(0x3DF, tmp | 0x80); /* write, read and compare method */ - base[0x500000] = 0x55; - base[0x300000] = 0x33; - base[0x100000] = 0x11; - tmp5 = base[0x500000]; - tmp3 = base[0x300000]; /* restore CRTCEXT3 state */ outb(0x3DE, 3); outb(0x3DF, tmp); xf86UnMapVidMem(vga256InfoRec.scrnIndex, LINEAR_REGION, ! (pointer)base, 8192 * 1024); ! ! if(tmp5 == 0x55) ! return 8192; ! if(tmp3 == 0x33) ! return 4096; } ! return 2048; } /* --- 401,451 ---- outb(0x3DF, tmp | 0x80); /* write, read and compare method */ + seed = 0x11; + + /* clear out newMem */ + newMem[0] = newMem[1] = newMem[2] = newMem[3] = 0; + newMem[4] = newMem[5] = newMem[6] = newMem[7] = 0; + + basePtr = 0x100000; /* 1 MB */ + cacheMem = base[0x5000]; /* cache flush spot */ + for (i = 0; i < blocks; i++) + { + oldMem = base[basePtr]; /* remember previous contents */ + base[basePtr] = 0; /* clear it */ + base[basePtr] = seed; + if ( MGAchipset != PCI_CHIP_MGA2064 ) + OUTREG8(MGAREG_CACHEFLUSH, 0); /* flush the cache on the mystique */ + else + base[0x5000] = 0x11; /* flush the cache */ + + newMem[i] = base[basePtr]; + base[basePtr] = oldMem; /* restore it to old val */ + seed += 0x11; + basePtr += 0x200000; /* go forward another 2 MB */ + } + base[0x5000] = cacheMem; /* restore the state */ + /* restore CRTCEXT3 state */ outb(0x3DE, 3); outb(0x3DF, tmp); xf86UnMapVidMem(vga256InfoRec.scrnIndex, LINEAR_REGION, ! (pointer)base, blocks * 2097152 ); ! seed = 0x11; ! videoMem = 0; ! ! for ( i=0; i < blocks; i++ ) ! { ! if ( newMem[i] == seed ) ! { ! seed += 0x11; ! videoMem += 2048; ! } ! } } ! return videoMem; } /* *************** *** 347,353 **** MGAIdent(n) int n; { ! static char *chipsets[] = {"mga2064w", "mga1064sg", "mga2164w" }; if (n + 1 > sizeof(chipsets) / sizeof(char *)) return(NULL); --- 457,463 ---- MGAIdent(n) int n; { ! static char *chipsets[] = {"mga2064w", "mga1064sg", "mga2164w", "mga2164w AGP" }; if (n + 1 > sizeof(chipsets) / sizeof(char *)) return(NULL); *************** *** 366,371 **** --- 476,482 ---- { unsigned long MGAMMIOAddr = 0; pciConfigPtr pcr = NULL; + pciConfigPtr mgapcr = NULL; int i; CARD32 save; *************** *** 409,417 **** case PCI_CHIP_MGA2164: MGAchipset = id; vga256InfoRec.chipset = MGAIdent(2); } if (MGAchipset) ! break; } } } else return(FALSE); --- 520,532 ---- case PCI_CHIP_MGA2164: MGAchipset = id; vga256InfoRec.chipset = MGAIdent(2); + break; + case PCI_CHIP_MGA2164_AGP: + MGAchipset = id; + vga256InfoRec.chipset = MGAIdent(3); } if (MGAchipset) ! mgapcr = pcr; } } } else return(FALSE); *************** *** 423,428 **** --- 538,544 ---- return(FALSE); } + pcr = mgapcr; if (vga256InfoRec.chipRev) { ErrorF("%s %s: MGA chipset override, using ChipRev " "0x%02x instead of 0x%02x\n", XCONFIG_GIVEN, *************** *** 432,451 **** MGArev = pcr->_rev_id; } /* - * make it obvious that Millennium II support is experimental - */ - if (MGAchipset == PCI_CHIP_MGA2164) - { - ErrorF("(!!) %s: Support for the Millennium II in this release\n", - vga256InfoRec.name); - - ErrorF("(!!) %s: is HIGHLY EXPERIMENTAL and largely untested\n", - vga256InfoRec.name); - ErrorF("(!!) %s: =================== ================\n", - vga256InfoRec.name); - } - - /* * OK. It's MGA */ --- 548,553 ---- *************** *** 461,473 **** if ( pcr->_base0 ) { /* details: mgabase1 sdk pp 4-11 */ if ( (MGAchipset == PCI_CHIP_MGA1064 && MGArev >= 3) || ! MGAchipset == PCI_CHIP_MGA2164 ) MGA.ChipLinearBase = pcr->_base0 & 0xff800000; else MGAMMIOAddr = pcr->_base0 & 0xffffc000; } else { if ( (MGAchipset == PCI_CHIP_MGA1064 && MGArev >= 3) || ! MGAchipset == PCI_CHIP_MGA2164 ) MGA.ChipLinearBase = 0; else MGAMMIOAddr = 0; --- 563,577 ---- if ( pcr->_base0 ) { /* details: mgabase1 sdk pp 4-11 */ if ( (MGAchipset == PCI_CHIP_MGA1064 && MGArev >= 3) || ! MGAchipset == PCI_CHIP_MGA2164 || ! MGAchipset == PCI_CHIP_MGA2164_AGP) MGA.ChipLinearBase = pcr->_base0 & 0xff800000; else MGAMMIOAddr = pcr->_base0 & 0xffffc000; } else { if ( (MGAchipset == PCI_CHIP_MGA1064 && MGArev >= 3) || ! MGAchipset == PCI_CHIP_MGA2164 || ! MGAchipset == PCI_CHIP_MGA2164_AGP) MGA.ChipLinearBase = 0; else MGAMMIOAddr = 0; *************** *** 475,481 **** if ( pcr->_base1 ) { /* details: mgabase2 sdk pp 4-12 */ if ( (MGAchipset == PCI_CHIP_MGA1064 && MGArev >= 3) || ! MGAchipset == PCI_CHIP_MGA2164 ) MGAMMIOAddr = pcr->_base1 & 0xffffc000; else --- 579,586 ---- if ( pcr->_base1 ) { /* details: mgabase2 sdk pp 4-12 */ if ( (MGAchipset == PCI_CHIP_MGA1064 && MGArev >= 3) || ! MGAchipset == PCI_CHIP_MGA2164 || ! MGAchipset == PCI_CHIP_MGA2164_AGP) MGAMMIOAddr = pcr->_base1 & 0xffffc000; else *************** *** 482,488 **** MGA.ChipLinearBase = pcr->_base1 & 0xff800000; } else { if ( (MGAchipset == PCI_CHIP_MGA1064 && MGArev >= 3) || ! MGAchipset == PCI_CHIP_MGA2164 ) MGAMMIOAddr = 0; else MGA.ChipLinearBase = 0; --- 587,594 ---- MGA.ChipLinearBase = pcr->_base1 & 0xff800000; } else { if ( (MGAchipset == PCI_CHIP_MGA1064 && MGArev >= 3) || ! MGAchipset == PCI_CHIP_MGA2164 || ! MGAchipset == PCI_CHIP_MGA2164_AGP) MGAMMIOAddr = 0; else MGA.ChipLinearBase = 0; *************** *** 515,531 **** vga256InfoRec.name, MGAMMIOAddr); } - /* - * Set up I/O ports to be used by this card. - */ - xf86ClearIOPortList(vga256InfoRec.scrnIndex); - xf86AddIOPorts(vga256InfoRec.scrnIndex, Num_VGA_IOPorts, VGA_IOPorts); - xf86AddIOPorts(vga256InfoRec.scrnIndex, Num_mgaExtPorts, - mgaExtPorts); /* enable IO ports, etc. */ MGAEnterLeave(ENTER); ! /* * Disable memory and I/O before mapping the MMIO area. * This avoids the MMIO area being read during the mapping --- 621,634 ---- vga256InfoRec.name, MGAMMIOAddr); } + #ifndef PC98_MGA /* enable IO ports, etc. */ MGAEnterLeave(ENTER); ! #else ! xf86EnableIOPorts(vga256InfoRec.scrnIndex); ! #endif ! /* * Disable memory and I/O before mapping the MMIO area. * This avoids the MMIO area being read during the mapping *************** *** 579,590 **** --- 682,707 ---- (pointer)(MGAMMIOAddr), 0x4000); #endif /* __alpha__ */ + #ifdef PC98_MGA + /* Re-enable memory (don't enable I/O) */ + pciWriteLong(MGAPciTag, PCI_CMD_STAT_REG, + save | PCI_CMD_MEM_ENABLE); + #else /* Re-enable I/O and memory */ pciWriteLong(MGAPciTag, PCI_CMD_STAT_REG, save | (PCI_CMD_IO_ENABLE | PCI_CMD_MEM_ENABLE)); + #endif if (!MGAMMIOBase) FatalError("MGA: Can't map IO registers\n"); + + #ifdef PC98_MGA + /* overlap BIOS ROM onto frame buffer aperture */ + save = pciReadLong(MGAPciTag, PCI_OPTION_REG); + pciWriteLong(MGAPciTag, PCI_OPTION_REG, save | 0x40000000); + pciWriteLong(MGAPciTag, 0x30, MGA.ChipLinearBase | 0x00000001); + vga256InfoRec.BIOSbase = MGA.ChipLinearBase; + #endif /* * Read the BIOS data struct *************** *** 593,608 **** #ifdef DEBUG ErrorF("MGABios.RamdacType = 0x%x\n",MGABios.RamdacType); #endif /* * If the user has specified the amount of memory in the XF86Config * file, we respect that setting. */ if (!vga256InfoRec.videoRam) ! vga256InfoRec.videoRam = MGACountRam(); ! MGA.ChipLinearSize = vga256InfoRec.videoRam * 1024; /* * fill MGAdac struct * Warning: currently, it should be after RAM counting --- 710,774 ---- #ifdef DEBUG ErrorF("MGABios.RamdacType = 0x%x\n",MGABios.RamdacType); #endif + + #ifdef PC98_MGA + /* disable BIOS ROM */ + pciWriteLong(MGAPciTag, 0x30, 0); + pciWriteLong(MGAPciTag, PCI_OPTION_REG, save); + + /* set VGA I/O to MMIO redirection base */ + mmioBase = MGAMMIOBase + 0x1c00; + + /* enable IO ports, etc. */ + MGAEnterLeave(ENTER); + + switch (MGAchipset) { + case PCI_CHIP_MGA2064: + MGA3026Reset(); + break; + case PCI_CHIP_MGA2164: + break; + case PCI_CHIP_MGA1064: + break; + } + #endif /* PC98_MGA */ /* * If the user has specified the amount of memory in the XF86Config * file, we respect that setting. */ + if (!vga256InfoRec.videoRam) ! if ( MGAchipset == PCI_CHIP_MGA2164 || MGAchipset == PCI_CHIP_MGA2164_AGP ) ! vga256InfoRec.videoRam = MGACountRam(8); /* count to 16 mb */ ! else ! vga256InfoRec.videoRam = MGACountRam(4); /* count to 8 mb */ ! MGA.ChipLinearSize = vga256InfoRec.videoRam; ! ! /* sanity check ChipLinearSize */ ! ! if ( MGAchipset == PCI_CHIP_MGA2164 || MGAchipset == PCI_CHIP_MGA2164_AGP ) ! { ! if ( MGA.ChipLinearSize < 2048 || MGA.ChipLinearSize > 16384 ) ! { ! MGA.ChipLinearSize = 2048; /* nice safe size */ ! ErrorF("(!!) %s: reset VideoRAM to 2 MB for safety!", ! vga256InfoRec.name); ! } ! } ! else ! { ! if ( MGA.ChipLinearSize < 2048 || MGA.ChipLinearSize > 8192 ) ! { ! MGA.ChipLinearSize = 2048; /* nice safe size */ ! ErrorF("(!!) %s: reset VideoRAM to 2 MB for safety!", ! vga256InfoRec.name); ! } ! } + MGA.ChipLinearSize *= 1024; + /* * fill MGAdac struct * Warning: currently, it should be after RAM counting *************** *** 611,616 **** --- 777,783 ---- { case PCI_CHIP_MGA2064: case PCI_CHIP_MGA2164: + case PCI_CHIP_MGA2164_AGP: MGA3026RamdacInit(); break; case PCI_CHIP_MGA1064: *************** *** 641,646 **** --- 808,815 ---- OFLG_SET(OPTION_DAC_8_BIT, &MGA.ChipOptionFlags); OFLG_SET(OPTION_SW_CURSOR, &MGA.ChipOptionFlags); OFLG_SET(OPTION_HW_CURSOR, &MGA.ChipOptionFlags); + OFLG_SET(OPTION_PCI_RETRY, &MGA.ChipOptionFlags); + OFLG_SET(OPTION_MGA_24BPP_FIX, &MGA.ChipOptionFlags); OFLG_SET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions); OFLG_SET(OPTION_DAC_8_BIT, &vga256InfoRec.options); *************** *** 739,773 **** static int MGAPitchAdjust() { ! int pitch = 0; int accel; ! /* XXX ajv - 512, 576, and 1536 may not be supported ! virtual resolutions. see sdk pp 4-59 for more ! details. Why anyone would want less than 640 is ! bizarre. (maybe lots of pixels tall?) */ - #if 0 - int width[] = { 512, 576, 640, 768, 800, 960, - 1024, 1152, 1280, 1536, 1600, 1920, 2048, 0 }; - #else int width[] = { 640, 768, 800, 960, 1024, 1152, 1280, 1600, 1920, 2048, 0 }; ! #endif ! int i; if (!OFLG_ISSET(OPTION_NOACCEL, &vga256InfoRec.options)) { accel = TRUE; ! for (i = 0; width[i]; i++) { ! if (width[i] >= vga256InfoRec.virtualX && ! TestAndSetRounding(width[i]) == width[i]) { ! pitch = width[i]; break; } } } else --- 908,953 ---- static int MGAPitchAdjust() { ! int *pWidth, pitch = 0; int accel; ! /* ajv - See MGA2064 p4-59 for millennium supported pitches ! * See MGA1064 p4-68 for mystique pitch ! * XXX see if MGA2164 has same width types as MGA1064 ! */ int width[] = { 640, 768, 800, 960, 1024, 1152, 1280, 1600, 1920, 2048, 0 }; ! int width2[] = { 512, 640, 768, 800, 832, 960, 1024, 1152, 1280, ! 1600, 1664, 1920, 2048, 0 }; + switch (MGAchipset) + { + case PCI_CHIP_MGA1064: + pWidth = &width2[0]; + break; + + case PCI_CHIP_MGA2064: + case PCI_CHIP_MGA2164: /* XXX - may need to be with 1064 */ + case PCI_CHIP_MGA2164_AGP: + default: + pWidth = &width[0]; + break; + } + if (!OFLG_ISSET(OPTION_NOACCEL, &vga256InfoRec.options)) { accel = TRUE; ! while ( *pWidth ) { ! if (*pWidth >= vga256InfoRec.virtualX && ! TestAndSetRounding(*pWidth) == *pWidth) { ! pitch = *pWidth; break; } + pWidth++; } } else *************** *** 860,865 **** --- 1040,1060 ---- return MGAydstorg * BytesPerPixel; } + #ifdef PC98_MGA + static Bool + MGAScreenInit(ScreenPtr pScreen, pointer pbits, + int xsize, int ysize, int dpix, int dpiy, int width) + { + switch (MGAchipset) { + case PCI_CHIP_MGA2064: + pScreen->StoreColors = MGATi3026StoreColors; + break; + default: + break; + } + return TRUE; + } + #endif /* * MGAFbInit -- *************** *** 870,875 **** --- 1065,1080 ---- static void MGAFbInit() { + #ifdef PC98_MGA + switch (MGAchipset) { + case PCI_CHIP_MGA2064: + vgaSetScreenInitHook(MGAScreenInit); + break; + default: + break; + } + #endif + if (MGAdac.MemoryClock && xf86Verbose) { ErrorF("%s %s: MCLK set to %1.3f MHz\n", *************** *** 930,935 **** --- 1135,1141 ---- { case PCI_CHIP_MGA2064: case PCI_CHIP_MGA2164: + case PCI_CHIP_MGA2164_AGP: return MGA3026Init(mode); case PCI_CHIP_MGA1064: return MGA1064Init(mode); *************** *** 955,960 **** --- 1161,1167 ---- { case PCI_CHIP_MGA2064: case PCI_CHIP_MGA2164: + case PCI_CHIP_MGA2164_AGP: MGA3026Restore(restore); break; case PCI_CHIP_MGA1064: *************** *** 982,987 **** --- 1189,1195 ---- { case PCI_CHIP_MGA2064: case PCI_CHIP_MGA2164: + case PCI_CHIP_MGA2164_AGP: return (void *)MGA3026Save(save); case PCI_CHIP_MGA1064: return (void *)MGA1064Save(save); *************** *** 1008,1014 **** #ifdef XFreeXDGA if (vga256InfoRec.directMode&XF86DGADirectGraphics && !enter) { if (MGAdac.isHwCursor) { ! MGAdac.CursorOff(); } return; } --- 1216,1222 ---- #ifdef XFreeXDGA if (vga256InfoRec.directMode&XF86DGADirectGraphics && !enter) { if (MGAdac.isHwCursor) { ! MGAdac.HideCursor(); } return; } *************** *** 1016,1022 **** --- 1224,1232 ---- if (enter) { + #ifndef PC98_MGA xf86EnableIOPorts(vga256InfoRec.scrnIndex); + #endif if (MGAMMIOBase) { xf86MapDisplay(vga256InfoRec.scrnIndex, *************** *** 1029,1037 **** --- 1239,1256 ---- /* Unprotect CRTC[0-7] */ outb(vgaIOBase + 4, 0x11); temp = inb(vgaIOBase + 5); outb(vgaIOBase + 5, temp & 0x7F); + #ifdef PC98_MGA + if (MGAchipset == PCI_CHIP_MGA1064) + _outb(0xfac, 0x02); + else + _outb(0xfac, 0x01); + #endif } else { + #ifdef PC98_MGA + _outb(0xfac, 0x00); + #endif /* Protect CRTC[0-7] */ outb(vgaIOBase + 4, 0x11); temp = inb(vgaIOBase + 5); outb(vgaIOBase + 5, (temp & 0x7F) | 0x80); *************** *** 1071,1096 **** int Base = (y * vga256InfoRec.displayWidth + x + MGAydstorg) >> (3 - MGABppShft); int tmp; if (vgaBitsPerPixel == 24) Base *= 3; ! /* Wait for vertical retrace */ ! while (!(inb(vgaIOBase + 0xA) & 0x08)); ! outw(vgaIOBase + 4, (Base & 0x00FF00) | 0x0C); outw(vgaIOBase + 4, ((Base & 0x0000FF) << 8) | 0x0D); outb(0x3DE, 0x00); tmp = inb(0x3DF); outb(0x3DF, (tmp & 0xF0) | ((Base & 0x0F0000) >> 16)); - - #ifdef XFreeXDGA - if (vga256InfoRec.directMode & XF86DGADirectGraphics) { - /* Wait for vertical retrace end */ - while (!(inb(vgaIOBase + 0xA) & 0x08)); - while (inb(vgaIOBase + 0xA) & 0x08); - } - #endif } /* --- 1290,1313 ---- int Base = (y * vga256InfoRec.displayWidth + x + MGAydstorg) >> (3 - MGABppShft); int tmp; + CARD32 count; if (vgaBitsPerPixel == 24) Base *= 3; ! /* find start of retrace */ ! while (inb(vgaIOBase + 0x0A) & 0x08); ! while (!(inb(vgaIOBase + 0xA) & 0x08)); ! /* wait until we're past the start (fixseg.c in the DDK) */ ! count = INREG(MGAREG_VCOUNT) + 2; ! while(INREG(MGAREG_VCOUNT) < count); ! ! outw(vgaIOBase + 4, (Base & 0x00FF00) | 0x0C); outw(vgaIOBase + 4, ((Base & 0x0000FF) << 8) | 0x0D); outb(0x3DE, 0x00); tmp = inb(0x3DF); outb(0x3DF, (tmp & 0xF0) | ((Base & 0x0F0000) >> 16)); } /* *** ./xfree86/vga256/drivers/mga/mga_hwcurs.c@@/PUBLIC-LATEST Sat Jul 19 16:06:18 1997 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/mga/mga_hwcurs.c Fri Mar 6 16:50:56 1998 *************** *** 1,8 **** ! /* $TOG: mga_hwcurs.c /main/1 1997/07/19 16:06:19 kaleb $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/mga/mga_hwcurs.c,v 1.1.2.2 1997/05/31 13:34:44 dawes Exp $ */ /* * Copyright 1994 by Robin Cutshaw <robin@XFree86.org> * --- 1,8 ---- ! /* $TOG: mga_hwcurs.c /main/2 1998/03/06 16:52:34 kaleb $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/mga/mga_hwcurs.c,v 1.1.2.3 1998/02/01 16:05:12 robin Exp $ */ /* * Copyright 1994 by Robin Cutshaw <robin@XFree86.org> * *************** *** 31,37 **** * */ - #define NEED_EVENTS #include <X.h> #include "Xproto.h" --- 31,36 ---- *************** *** 46,51 **** --- 45,51 ---- #include "inputstr.h" #include "xf86Priv.h" #include "xf86_OSlib.h" + #include "xf86cursor.h" #include "mipointer.h" #include "vga.h" *************** *** 53,294 **** #include "mga.h" ! /* ! * exported functions ! */ ! Bool MGAHwCursorInit(); - /* - * implementation - */ - - static int MGACursorHotX; - static int MGACursorHotY; - static int MGACursorGeneration = -1; - static CursorPtr MGACursorpCurs; - - static Bool MGARealizeCursor(); - static Bool MGAUnrealizeCursor(); - static void MGASetCursor(); - static void MGAMoveCursor(); - static void MGALoadCursor(); - - extern miPointerScreenFuncRec xf86PointerScreenFuncs; - extern xf86InfoRec xf86Info; extern vgaHWCursorRec vgaHWCursor; - static miPointerSpriteFuncRec MGAPointerSpriteFuncs = - { - MGARealizeCursor, - MGAUnrealizeCursor, - MGASetCursor, - MGAMoveCursor, - }; - - static Bool - MGARealizeCursor(pScr, pCurs) - ScreenPtr pScr; - CursorPtr pCurs; - { - register int i, j; - int index = pScr->myNum; - pointer *pPriv = &pCurs->bits->devPriv[index]; - int wsrc, h; - CursorBitsPtr bits = pCurs->bits; - - if (pCurs->bits->refcnt > 1) - return TRUE; - - h = bits->height; - wsrc = PixmapBytePad(bits->width, 1); /* bytes per line */ - - *pPriv = MGAdac.RealizeCursor(bits->source, bits->mask, wsrc, h); - if (!*pPriv) - return FALSE; - - return TRUE; - } - - static Bool - MGAUnrealizeCursor(pScr, pCurs) - ScreenPtr pScr; - CursorPtr pCurs; - { - pointer priv; - - if (pCurs->bits->refcnt <= 1 && - (priv = pCurs->bits->devPriv[pScr->myNum])) - xfree(priv); - return TRUE; - } - /* ! * This function should display a new cursor at a new position. */ ! ! static void ! MGASetCursor(pScr, pCurs, x, y, generateEvent) ! ScreenPtr pScr; ! CursorPtr pCurs; ! int x, y; ! Bool generateEvent; { ! if (!pCurs) ! return; ! ! MGACursorHotX = pCurs->bits->xhot; ! MGACursorHotY = pCurs->bits->yhot; ! ! MGALoadCursor(pScr, pCurs, x, y); ! } ! static void ! MGAMoveCursor(pScr, x, y) ! ScreenPtr pScr; ! int x, y; ! { ! if (!xf86VTSema) ! return; ! ! x -= vga256InfoRec.frameX0 + MGACursorHotX; ! y -= vga256InfoRec.frameY0 + MGACursorHotY; ! ! MGAdac.MoveCursor(x, y); ! } - static void - MGARecolorCursor(pScr, pCurs, displayed) - ScreenPtr pScr; - CursorPtr pCurs; - Bool displayed; - { - if (!displayed) - return; - - MGAdac.RecolorCursor(pCurs->backRed, pCurs->backGreen, pCurs->backBlue, - pCurs->foreRed, pCurs->foreGreen, pCurs->foreBlue); - } - - static void - MGALoadCursor(pScr, pCurs, x, y) - ScreenPtr pScr; - CursorPtr pCurs; - int x, y; - { - int index = pScr->myNum; - register int i; - unsigned char *ram, *p, tmp; - - if (!xf86VTSema) - return; - - if (!pCurs) - return; - - /* Remember the cursor currently loaded into this cursor slot. */ - MGACursorpCurs = pCurs; - - /* turn the cursor off */ - MGAdac.CursorOff(); - - /* output the cursor data */ - MGAdac.LoadCursor(pCurs->bits->devPriv[index]); - - /* load colormap */ - MGARecolorCursor(pScr, pCurs, TRUE); - - /* position cursor */ - MGAMoveCursor(0, x, y); - - /* turn the cursor on */ - MGAdac.CursorOn(); - } - - - /* - * This is a high-level init function, called once; it passes a local - * miPointerSpriteFuncRec with additional functions that we need to provide. - * It is called by the SVGA server. - */ - static Bool - MGACursorInit(pm, pScr) - char *pm; - ScreenPtr pScr; - { - if (MGACursorGeneration != serverGeneration) { - if (!(miPointerInitialize(pScr, &MGAPointerSpriteFuncs, - &xf86PointerScreenFuncs, FALSE))) - return FALSE; - - MGACursorHotX = 0; - MGACursorHotY = 0; - pScr->RecolorCursor = MGARecolorCursor; - MGACursorGeneration = serverGeneration; - } return TRUE; - } - - /* - * This function should redisplay a cursor that has been - * displayed earlier. It is called by the SVGA server. - */ - static void - MGARestoreCursor(pScr) - ScreenPtr pScr; - { - int x, y; - - miPointerPosition(&x, &y); - - MGALoadCursor(pScr, MGACursorpCurs, x, y); - } - - /* - * This doesn't do very much. It just calls the mi routine. It is called - * by the SVGA server. - */ - static void - MGAWarpCursor(pScr, x, y) - ScreenPtr pScr; - int x, y; - { - miPointerWarpCursor(pScr, x, y); - xf86Info.currentScreen = pScr; - } - - /* - * This function is called by the SVGA server. It returns the - * size of the hardware cursor that we support when asked for. - * It is called by the SVGA server. - */ - static void - MGAQueryBestSize(class, pwidth, pheight, pScreen) - int class; - unsigned short *pwidth; - unsigned short *pheight; - ScreenPtr pScreen; - { - if (*pwidth > 0) { - if (class == CursorShape) - MGAdac.QueryCursorSize(pwidth, pheight); - else - (void) mfbQueryBestSize(class, pwidth, pheight, pScreen); - } - } - - /* - * This is top-level initialization funtion called from mga_driver - */ - Bool MGAHwCursorInit() - { - if (MGAdac.isHwCursor) { - vgaHWCursor.Initialized = TRUE; - vgaHWCursor.Init = MGACursorInit; - vgaHWCursor.Restore = MGARestoreCursor; - vgaHWCursor.Warp = MGAWarpCursor; - vgaHWCursor.QueryBestSize = MGAQueryBestSize; - return TRUE; - } - return FALSE; } --- 53,87 ---- #include "mga.h" ! extern Bool XAACursorInit(); ! extern void XAARestoreCursor(); ! extern void XAAWarpCursor(); ! extern void XAAQueryBestSize(); extern vgaHWCursorRec vgaHWCursor; /* ! * This is top-level initialization funtion called from mga_driver */ ! Bool MGAHwCursorInit() { + if (!MGAdac.isHwCursor) + return FALSE; ! XAACursorInfoRec.MaxWidth = MGAdac.CursorMaxWidth; ! XAACursorInfoRec.MaxHeight = MGAdac.CursorMaxHeight; ! XAACursorInfoRec.Flags = MGAdac.CursorFlags; ! XAACursorInfoRec.SetCursorColors = MGAdac.SetCursorColors; ! XAACursorInfoRec.SetCursorPosition = MGAdac.SetCursorPosition; ! XAACursorInfoRec.LoadCursorImage = MGAdac.LoadCursorImage; ! XAACursorInfoRec.HideCursor = MGAdac.HideCursor; ! XAACursorInfoRec.ShowCursor = MGAdac.ShowCursor; ! vgaHWCursor.Init = XAACursorInit; ! vgaHWCursor.Initialized = TRUE; ! vgaHWCursor.Restore = XAARestoreCursor; ! vgaHWCursor.Warp = XAAWarpCursor; ! vgaHWCursor.QueryBestSize = XAAQueryBestSize; return TRUE; } *** ./xfree86/vga256/drivers/mga/mga_reg.h@@/PUBLIC-LATEST Sat Jul 19 16:06:27 1997 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/mga/mga_reg.h Fri Mar 6 16:51:04 1998 *************** *** 1,8 **** ! /* $TOG: mga_reg.h /main/1 1997/07/19 16:06:28 kaleb $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/mga/mga_reg.h,v 1.1.2.1 1997/05/09 09:09:11 hohndel Exp $ */ --- 1,8 ---- ! /* $TOG: mga_reg.h /main/2 1998/03/06 16:52:42 kaleb $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/mga/mga_reg.h,v 1.1.2.2 1998/02/01 16:05:13 robin Exp $ */ *************** *** 115,120 **** --- 115,122 ---- #define MGAREG_OPMODE 0x1e54 + #define MGAREG_CACHEFLUSH 0x1fff /* mystique & poss mistral */ + /* OPMODE register additives */ #define MGAOPM_DMA_GENERAL (0x00 << 2) *************** *** 263,268 **** --- 265,272 ---- #define TVP3026_PIX_CLK_DATA 0x2d #define TVP3026_MEM_CLK_DATA 0x2e #define TVP3026_LOAD_CLK_DATA 0x2f + #define TVP3026_KEY_OVRLY_LOW 0x30 + #define TVP3026_KEY_OVRLY_HI 0x31 #define TVP3026_KEY_RED_LOW 0x32 #define TVP3026_KEY_RED_HI 0x33 #define TVP3026_KEY_GREEN_LOW 0x34 *** ./xfree86/vga256/drivers/mga/mga_storm.c@@/PUBLIC-LATEST Sat Jul 19 21:03:45 1997 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/mga/mga_storm.c Sat Mar 7 17:15:21 1998 *************** *** 1,14 **** ! /* $TOG: mga_storm.c /main/2 1997/07/19 21:03:47 kaleb $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/mga/mga_storm.c,v 1.1.2.2 1997/05/25 05:06:51 dawes Exp $ */ ! /* ! * This is a sample driver implementation template for the new acceleration ! * interface. ! */ ! #include "vga256.h" #include "xf86.h" #include "vga.h" --- 1,10 ---- ! /* $TOG: mga_storm.c /main/4 1998/03/07 17:17:03 kaleb $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/mga/mga_storm.c,v 1.1.2.6 1998/02/26 13:59:11 dawes Exp $ */ ! #include "compiler.h" #include "vga256.h" #include "xf86.h" #include "vga.h" *************** *** 17,241 **** #include "miline.h" #include "xf86xaa.h" #include "mga.h" #include "mga_reg.h" #include "mga_map.h" ! /* ! * forward definitions for once only compiled functions. ! */ ! void MGAStormAccelInit(); ! void MGAStormSync(); ! void MGAStormEngineInit(); ! /* ! * forward definitions for the functions in this file. ! * MGANAME macro gives correct name for current depth ! */ static void MGANAME(SetupForFillRectSolid)(); static void MGANAME(SubsequentFillRectSolid)(); static void MGANAME(SubsequentFillTrapezoidSolid)(); ! static void MGANAME(SetupForScreenToScreenCopy)(); ! static void MGANAME(SubsequentScreenToScreenCopy)(); static void MGANAME(SetupForCPUToScreenColorExpand)(); static void MGANAME(SubsequentCPUToScreenColorExpand)(); static void MGANAME(SetupForScreenToScreenColorExpand)(); static void MGANAME(SubsequentScreenToScreenColorExpand)(); - static void MGANAME(SetupFor8x8PatternColorExpand)(); - static void MGANAME(Subsequent8x8PatternColorExpand)(); - static void MGANAME(SubsequentTwoPointLine)(); static void MGANAME(SetupForDashedLine)(); static void MGANAME(SubsequentDashedBresenhamLine)(); ! static void MGANAME(SetClippingRectangle)(); ! ! static int mga_cmd, mga_lastcmd, mga_linecmd, mga_rop; ! static int mga_sgn, mga_lastsgn, mga_lastcxright, mga_lastshift; ! static int mgablitxdir, mgablitydir; ! static int mga_ClipRect; ! static int mga_useBLKopaqueExpand; ! static CARD32 mgaDashedPatternBuf[4]; /* allocate 128 bits */ ! static CARD32 mgaStylelen; - /* - * The following function sets up the supported acceleration. Call it - * from the FbInit() function in the SVGA driver. - */ void MGANAME(AccelInit)() { ! int tmp; ! ! /* ! * If you to disable acceleration, just don't modify anything ! * in the AccelInfoRec. ! */ ! /* ! * Set up the main flags acceleration. ! * Usually, you will want to use BACKGROUND_OPERATIONS, ! * and if you have ScreenToScreenCopy, use the PIXMAP_CACHE. ! */ ! xf86AccelInfoRec.Flags = BACKGROUND_OPERATIONS | ! PIXMAP_CACHE | ! HARDWARE_CLIP_LINE | ! USE_TWO_POINT_LINE | ! TWO_POINT_LINE_NOT_LAST | ! /* LINE_PATTERN_MSBFIRST_DECREASING | */ ! NO_SYNC_AFTER_CPU_COLOR_EXPAND; ! /* pattern flags */ ! xf86AccelInfoRec.Flags |= HARDWARE_PATTERN_PROGRAMMED_BITS | ! HARDWARE_PATTERN_PROGRAMMED_ORIGIN | ! HARDWARE_PATTERN_SCREEN_ORIGIN | ! HARDWARE_PATTERN_BIT_ORDER_MSBFIRST | ! HARDWARE_PATTERN_MONO_TRANSPARENCY; ! ! /* ! * install hardware lines and clipping ! */ ! ! xf86AccelInfoRec.SubsequentTwoPointLine = MGANAME(SubsequentTwoPointLine); ! xf86AccelInfoRec.SetClippingRectangle = MGANAME(SetClippingRectangle); ! ! #if 0 /* wait for XAA suport */ ! xf86AccelInfoRec.SetupForDashedLine = MGANAME(SetupForDashedLine); ! xf86AccelInfoRec.SubsequentDashedBresenhamLine = MGANAME(SubsequentDashedBresenhamLine); ! xf86AccelInfoRec.LinePatternBuffer = (void *) &mgaDashedPatternBuf[0]; ! xf86AccelInfoRec.LinePatternMaxLength = 128; ! xf86AccelInfoRec.ErrorTermBits = 15; ! #endif ! ! /* ! * The following line installs a "Sync" function, that waits for ! * all coprocessor operations to complete. ! */ xf86AccelInfoRec.Sync = MGAStormSync; ! /* ! * We want to set up the FillRectSolid primitive for filling a solid ! * rectangle. First we set up the flags for the graphics operation. ! * It may include GXCOPY_ONLY, NO_PLANEMASK, and RGB_EQUAL. ! */ ! xf86GCInfoRec.PolyFillRectSolidFlags = 0; ! ! #if PSZ == 24 ! /* ! * In 24 bpp, all three colors must have the same mask ! */ ! xf86GCInfoRec.PolyFillRectSolidFlags |= NO_PLANEMASK; ! #endif ! ! /* ! * Install the low-level functions for drawing solid filled rectangles. ! */ ! xf86AccelInfoRec.SetupForFillRectSolid = ! MGANAME(SetupForFillRectSolid); ! xf86AccelInfoRec.SubsequentFillRectSolid = ! MGANAME(SubsequentFillRectSolid); ! #if 0 /* wait for XAA support */ ! xf86AccelInfoRec.SubsequentFillTrapezoidSolid = ! MGANAME(SubsequentFillTrapezoidSolid); ! #endif ! ! /* ! * We also want to set up the ScreenToScreenCopy (BitBLT) primitive for ! * copying a rectangular area from one location on the screen to ! * another. First we set up the restrictions. In this case, we ! * don't handle transparency color compare. Other allowed flags are ! * GXCOPY_ONLY and NO_PLANEMASK. ! */ xf86GCInfoRec.CopyAreaFlags = NO_TRANSPARENCY; - #if PSZ == 24 - xf86GCInfoRec.CopyAreaFlags |= NO_PLANEMASK; - #endif - - /* - * Install the low-level functions for screen-to-screen copy. - */ xf86AccelInfoRec.SetupForScreenToScreenCopy = MGANAME(SetupForScreenToScreenCopy); xf86AccelInfoRec.SubsequentScreenToScreenCopy = MGANAME(SubsequentScreenToScreenCopy); ! /* ! * color expansion ! */ xf86AccelInfoRec.ColorExpandFlags = SCANLINE_PAD_DWORD | CPU_TRANSFER_PAD_DWORD | BIT_ORDER_IN_BYTE_LSBFIRST | ! LEFT_EDGE_CLIPPING | ! LEFT_EDGE_CLIPPING_NEGATIVE_X | ! VIDEO_SOURCE_GRANULARITY_PIXEL; ! #if PSZ == 24 ! xf86AccelInfoRec.ColorExpandFlags |= NO_PLANEMASK; ! #endif ! ! /* Mystique can't do opaque color expansion in BLOCK access type */ ! mga_useBLKopaqueExpand = (MGAchipset == PCI_CHIP_MGA2064); ! ! xf86AccelInfoRec.SetupForScreenToScreenColorExpand = ! MGANAME(SetupForScreenToScreenColorExpand); ! xf86AccelInfoRec.SubsequentScreenToScreenColorExpand = ! MGANAME(SubsequentScreenToScreenColorExpand); ! ! xf86AccelInfoRec.SetupForCPUToScreenColorExpand = ! MGANAME(SetupForCPUToScreenColorExpand); ! xf86AccelInfoRec.SubsequentCPUToScreenColorExpand = ! MGANAME(SubsequentCPUToScreenColorExpand); ! #ifdef __alpha__ xf86AccelInfoRec.CPUToScreenColorExpandBase = (unsigned*)MGAMMIOBaseDENSE; ! #else /* __alpha__ */ xf86AccelInfoRec.CPUToScreenColorExpandBase = (unsigned*)MGAMMIOBase; #endif /* __alpha__ */ xf86AccelInfoRec.CPUToScreenColorExpandRange = 0x1C00; ! /* ! * 8x8 color expand pattern fill ! */ xf86AccelInfoRec.SetupFor8x8PatternColorExpand = MGANAME(SetupFor8x8PatternColorExpand); xf86AccelInfoRec.Subsequent8x8PatternColorExpand = MGANAME(Subsequent8x8PatternColorExpand); ! ! /* ! * Finally, we set up the video memory space available to the pixmap ! * cache. In this case, all memory from the end of the virtual screen ! * to the end of video memory minus 1K, can be used. ! */ { ! int cacheStart = (vga256InfoRec.virtualY * vga256InfoRec.displayWidth ! + MGAydstorg) * vga256InfoRec.bitsPerPixel / 8; ! int cacheEnd = vga256InfoRec.videoRam * 1024 - 1024; ! /* ! * we can't fast blit between first 4MB and second 4MB for interleave ! * and between first 2MB and other memory for non-interleave ! */ ! int max_fastbitblt_mem = (MGAinterleave ? 4096 : 2048) * 1024; ! ! if( cacheStart > max_fastbitblt_mem - 4096 ) ! MGAusefbitblt = 0; ! else ! if( cacheEnd > max_fastbitblt_mem - 1024 ) ! cacheEnd = max_fastbitblt_mem - 1024; ! ! xf86InitPixmapCache(&vga256InfoRec, cacheStart, cacheEnd); } } #if PSZ == 8 - /* functions specific to this chipset, to be compiled just the once */ - /* ! * The following function sets up the supported acceleration. Call it ! * from the FbInit() function in the SVGA driver. ! */ ! void MGAStormAccelInit() { switch( vgaBitsPerPixel ) { case 8: --- 13,244 ---- #include "miline.h" #include "xf86xaa.h" + #include "xf86local.h" #include "mga.h" #include "mga_reg.h" #include "mga_map.h" + #include "mga_macros.h" ! extern CARD32 MGAAtype[16]; ! extern CARD32 MGAAtypeNoBLK[16]; ! extern void MGAWriteBitmap(); ! extern void MGAFillRectStippled(); ! extern Bool MGAIsClipped; ! extern Bool MGAUsePCIRetry; ! extern Bool MGAUseBLKOpaqueExpansion; ! extern Bool MGAIsMillennium2; ! extern int MGAMaxFastBlitY; ! ! static void MGANAME(SetupForScreenToScreenCopy)(); ! static void MGANAME(SubsequentScreenToScreenCopy)(); ! static void MGANAME(SubsequentScreenToScreenCopy_FastBlit)(); ! static void MGANAME(SubsequentScreenToScreenCopy_FastBlit_Broken)(); static void MGANAME(SetupForFillRectSolid)(); static void MGANAME(SubsequentFillRectSolid)(); static void MGANAME(SubsequentFillTrapezoidSolid)(); ! static void MGANAME(SubsequentBresenhamLine)(); static void MGANAME(SetupForCPUToScreenColorExpand)(); static void MGANAME(SubsequentCPUToScreenColorExpand)(); static void MGANAME(SetupForScreenToScreenColorExpand)(); static void MGANAME(SubsequentScreenToScreenColorExpand)(); static void MGANAME(SetupForDashedLine)(); static void MGANAME(SubsequentDashedBresenhamLine)(); ! static void MGANAME(SetupFor8x8PatternColorExpand)(); ! static void MGANAME(Subsequent8x8PatternColorExpand)(); ! static void MGANAME(Subsequent8x8PatternColorExpand_Additional)(); ! static CARD32 MGADashPattern[4]; void MGANAME(AccelInit)() { ! if(MGAchipset == PCI_CHIP_MGA2164_AGP || MGAchipset == PCI_CHIP_MGA2164) ! MGAIsMillennium2 = TRUE; ! if(OFLG_ISSET(OPTION_PCI_RETRY, &vga256InfoRec.options)) ! MGAUsePCIRetry = TRUE; ! MGAUseBLKOpaqueExpansion = (MGAchipset != PCI_CHIP_MGA1064); + xf86AccelInfoRec.Flags = BACKGROUND_OPERATIONS | + COP_FRAMEBUFFER_CONCURRENCY | + DO_NOT_BLIT_STIPPLES | + LINE_PATTERN_MSBFIRST_LSBJUSTIFIED | + PIXMAP_CACHE | + HARDWARE_PATTERN_PROGRAMMED_BITS | + HARDWARE_PATTERN_PROGRAMMED_ORIGIN | + HARDWARE_PATTERN_SCREEN_ORIGIN | + HARDWARE_PATTERN_BIT_ORDER_MSBFIRST | + HARDWARE_PATTERN_MONO_TRANSPARENCY; ! /* sync */ xf86AccelInfoRec.Sync = MGAStormSync; ! /* screen to screen copy */ xf86GCInfoRec.CopyAreaFlags = NO_TRANSPARENCY; xf86AccelInfoRec.SetupForScreenToScreenCopy = MGANAME(SetupForScreenToScreenCopy); xf86AccelInfoRec.SubsequentScreenToScreenCopy = MGANAME(SubsequentScreenToScreenCopy); ! /* solid filled rectangles */ ! xf86AccelInfoRec.SetupForFillRectSolid = ! MGANAME(SetupForFillRectSolid); ! xf86AccelInfoRec.SubsequentFillRectSolid = ! MGANAME(SubsequentFillRectSolid); ! ! /* solid trapezoids */ ! xf86AccelInfoRec.SubsequentFillTrapezoidSolid = ! MGANAME(SubsequentFillTrapezoidSolid); ! ! /* solid bresenham lines */ ! xf86AccelInfoRec.SubsequentBresenhamLine = ! MGANAME(SubsequentBresenhamLine); ! xf86AccelInfoRec.ErrorTermBits = 15; ! ! /* cpu to screen color expansion */ xf86AccelInfoRec.ColorExpandFlags = SCANLINE_PAD_DWORD | CPU_TRANSFER_PAD_DWORD | BIT_ORDER_IN_BYTE_LSBFIRST | ! LEFT_EDGE_CLIPPING | ! LEFT_EDGE_CLIPPING_NEGATIVE_X; #ifdef __alpha__ xf86AccelInfoRec.CPUToScreenColorExpandBase = (unsigned*)MGAMMIOBaseDENSE; ! #else xf86AccelInfoRec.CPUToScreenColorExpandBase = (unsigned*)MGAMMIOBase; #endif /* __alpha__ */ xf86AccelInfoRec.CPUToScreenColorExpandRange = 0x1C00; ! xf86AccelInfoRec.SetupForCPUToScreenColorExpand = ! MGANAME(SetupForCPUToScreenColorExpand); ! xf86AccelInfoRec.SubsequentCPUToScreenColorExpand = ! MGANAME(SubsequentCPUToScreenColorExpand); ! ! xf86AccelInfoRec.SetupForScreenToScreenColorExpand = ! MGANAME(SetupForScreenToScreenColorExpand); ! xf86AccelInfoRec.SubsequentScreenToScreenColorExpand = ! MGANAME(SubsequentScreenToScreenColorExpand); ! ! /* dashed bresenham lines */ ! xf86AccelInfoRec.SetupForDashedLine = MGANAME(SetupForDashedLine); ! xf86AccelInfoRec.SubsequentDashedBresenhamLine = ! MGANAME(SubsequentDashedBresenhamLine); ! xf86AccelInfoRec.LinePatternBuffer = (void *)MGADashPattern; ! xf86AccelInfoRec.LinePatternMaxLength = 128; ! ! ! /* 8x8 pattern fills */ xf86AccelInfoRec.SetupFor8x8PatternColorExpand = MGANAME(SetupFor8x8PatternColorExpand); xf86AccelInfoRec.Subsequent8x8PatternColorExpand = MGANAME(Subsequent8x8PatternColorExpand); ! ! ! /* replacements */ ! xf86AccelInfoRec.WriteBitmap = MGAWriteBitmap; ! xf86AccelInfoRec.FillRectStippled = MGAFillRectStippled; ! xf86AccelInfoRec.FillRectOpaqueStippled = MGAFillRectStippled; ! ! #if PSZ == 24 ! /* Shotgun approach. XAA should do some of these on it's own ! but it isn't getting all of them */ ! xf86GCInfoRec.CopyAreaFlags |= NO_PLANEMASK; ! xf86GCInfoRec.FillPolygonSolidFlags |= NO_PLANEMASK; ! ! xf86GCInfoRec.PolyRectangleSolidZeroWidthFlags |= NO_PLANEMASK; ! xf86GCInfoRec.PolyLineSolidZeroWidthFlags |= NO_PLANEMASK; ! xf86GCInfoRec.PolySegmentSolidZeroWidthFlags |= NO_PLANEMASK; ! xf86GCInfoRec.PolyLineDashedZeroWidthFlags |= NO_PLANEMASK; ! xf86GCInfoRec.PolySegmentDashedZeroWidthFlags |= NO_PLANEMASK; ! ! xf86GCInfoRec.PolyGlyphBltNonTEFlags |= NO_PLANEMASK; ! xf86GCInfoRec.ImageGlyphBltNonTEFlags |= NO_PLANEMASK; ! xf86GCInfoRec.PolyGlyphBltTEFlags |= NO_PLANEMASK; ! xf86GCInfoRec.ImageGlyphBltTEFlags |= NO_PLANEMASK; ! ! xf86GCInfoRec.FillSpansSolidFlags |= NO_PLANEMASK; ! xf86GCInfoRec.FillSpansTiledFlags |= NO_PLANEMASK; ! xf86GCInfoRec.FillSpansStippledFlags |= NO_PLANEMASK; ! xf86GCInfoRec.FillSpansOpaqueStippledFlags |= NO_PLANEMASK; ! ! xf86GCInfoRec.SecondaryPolyFillRectOpaqueStippledFlags |= NO_PLANEMASK; ! xf86GCInfoRec.SecondaryPolyFillRectStippledFlags |= NO_PLANEMASK; ! ! xf86GCInfoRec.PolyFillRectSolidFlags |= NO_PLANEMASK; ! xf86GCInfoRec.PolyFillRectTiledFlags |= NO_PLANEMASK; ! xf86GCInfoRec.PolyFillRectStippledFlags |= NO_PLANEMASK; ! xf86GCInfoRec.PolyFillRectOpaqueStippledFlags |= NO_PLANEMASK; ! ! xf86GCInfoRec.PolyFillArcSolidFlags |= NO_PLANEMASK; ! ! xf86AccelInfoRec.ColorExpandFlags |= NO_PLANEMASK; ! #endif ! ! /* pixmap cache */ { ! int cacheStart, cacheEnd, maxFastBlitMem; ! ! maxFastBlitMem = (MGAinterleave ? 4096 : 2048) * 1024; ! cacheStart = (vga256InfoRec.virtualY * vga256InfoRec.displayWidth ! + MGAydstorg) * PSZ / 8; ! ! cacheEnd = cacheStart + (128 * vga256InfoRec.displayWidth * PSZ / 8); ! ! if(cacheEnd > (vga256InfoRec.videoRam * 1024)) ! cacheEnd = (vga256InfoRec.videoRam * 1024); ! ! if(cacheEnd > maxFastBlitMem) { ! MGAMaxFastBlitY = maxFastBlitMem / ! (vga256InfoRec.displayWidth * PSZ / 8); ! } ! ! xf86AccelInfoRec.PixmapCacheMemoryStart = cacheStart; ! xf86AccelInfoRec.PixmapCacheMemoryEnd = cacheEnd; } } + #if PSZ == 8 /* ! GXclear, GXand, ! GXandReverse, GXcopy, ! GXandInverted, GXnoop, ! GXxor, GXor, ! GXnor, GXequiv, ! GXinvert, GXorReverse, ! GXcopyInverted, GXorInverted, ! GXnand, GXset ! */ ! ! ! CARD32 MGAAtype[16] = { ! MGADWG_RPL | 0x00000000, MGADWG_RSTR | 0x00080000, ! MGADWG_RSTR | 0x00040000, MGADWG_BLK | 0x000c0000, ! MGADWG_RSTR | 0x00020000, MGADWG_RSTR | 0x000a0000, ! MGADWG_RSTR | 0x00060000, MGADWG_RSTR | 0x000e0000, ! MGADWG_RSTR | 0x00010000, MGADWG_RSTR | 0x00090000, ! MGADWG_RSTR | 0x00050000, MGADWG_RSTR | 0x000d0000, ! MGADWG_RPL | 0x00030000, MGADWG_RSTR | 0x000b0000, ! MGADWG_RSTR | 0x00070000, MGADWG_RPL | 0x000f0000 ! }; ! ! ! CARD32 MGAAtypeNoBLK[16] = { ! MGADWG_RPL | 0x00000000, MGADWG_RSTR | 0x00080000, ! MGADWG_RSTR | 0x00040000, MGADWG_RPL | 0x000c0000, ! MGADWG_RSTR | 0x00020000, MGADWG_RSTR | 0x000a0000, ! MGADWG_RSTR | 0x00060000, MGADWG_RSTR | 0x000e0000, ! MGADWG_RSTR | 0x00010000, MGADWG_RSTR | 0x00090000, ! MGADWG_RSTR | 0x00050000, MGADWG_RSTR | 0x000d0000, ! MGADWG_RPL | 0x00030000, MGADWG_RSTR | 0x000b0000, ! MGADWG_RSTR | 0x00070000, MGADWG_RPL | 0x000f0000 ! }; ! ! void ! MGAStormAccelInit() { switch( vgaBitsPerPixel ) { case 8: *************** *** 255,298 **** } } ! /* ! * This is the implementation of the Sync() function. ! */ ! void MGAStormSync() { ! int i, j; ! ! /* ! * Flush the read cache (SDK 5-2) ! * It doesn't matter which VGA register we write, ! * so we pick one that's not used in "Power" mode. ! */ ! OUTREG8(MGAREG_CRTC_INDEX, 0); ! ! if (!MGAISBUSY()) ! return; ! ! for (j = 8; j > 0; j--) { ! for (i = 10000000; i > 0; i--) ! if (!MGAISBUSY()) ! return; ! OUTREG8(MGAREG_OPMODE, 0); /* terminate DMA sequence */ ! ErrorF("MGA: Drawing Engine time-out.\n"); ! } ! FatalError("MGA: Drawing Engine time-out.\n"); } ! /* ! * Global initialization of drawing engine ! */ ! void MGAStormEngineInit() { ! long maccess; switch( vgaBitsPerPixel ) { case 8: - maccess = 0; break; case 16: /* set 16 bpp, turn off dithering, turn on 5:5:5 pixels */ --- 258,292 ---- } } ! Bool MGAIsClipped = FALSE; ! Bool MGAUsePCIRetry = FALSE; ! Bool MGAUseBLKOpaqueExpansion; ! Bool MGAIsMillennium2 = FALSE; ! int MGAMaxFastBlitY = 0; ! ! void ! MGAStormSync() { ! if(MGAIsClipped) { ! /* we don't need to sync after a cpu->screen color expand. ! we merely need to reset the clipping box */ ! WAITFIFO(1); ! OUTREG(MGAREG_CXBNDRY, 0xFFFF0000); ! MGAIsClipped = FALSE; ! } else while(MGAISBUSY()); ! ! /* flush cache before a read (mga-1064g 5.1.6) */ ! OUTREG8(MGAREG_CRTC_INDEX, 0); } ! void ! MGAStormEngineInit() { ! CARD32 maccess = 0; switch( vgaBitsPerPixel ) { case 8: break; case 16: /* set 16 bpp, turn off dithering, turn on 5:5:5 pixels */ *************** *** 305,1016 **** maccess = 2; break; } ! OUTREG(MGAREG_PITCH, vga256InfoRec.displayWidth); OUTREG(MGAREG_YDSTORG, MGAydstorg); OUTREG(MGAREG_MACCESS, maccess); OUTREG(MGAREG_PLNWT, ~0); ! OUTREG(MGAREG_OPMODE, 0); } - #endif /* PSZ == 8 */ /* once only compilation */ ! ! /* ! * Replicate colors and planemasks ! */ ! #if PSZ == 8 ! #define REPLICATE(pixel) \ ! pixel &= 0xff; pixel |= (pixel << 24) | (pixel << 16) | (pixel << 8); ! #elif PSZ == 16 ! #define REPLICATE(pixel) \ ! pixel &= 0xffff; pixel |= (pixel << 16); ! #else ! #define REPLICATE(pixel) ; ! #endif - #define REPLICATE24(pixel) \ - pixel &= 0xffffff; pixel |= (pixel & 0xff) << 24; - /* - * Disable clipping - */ - #define DISABLECLIPPING() \ - OUTREG(MGAREG_CXBNDRY, 0xFFFF0000); /* (maxX << 16) | minX */ \ - OUTREG(MGAREG_YTOP, 0x00000000); /* minPixelPointer */ \ - OUTREG(MGAREG_YBOT, 0x007FFFFF); /* maxPixelPointer */ \ - mga_ClipRect = 0; /* one time line clipping is off */ - /* - * Use faster access type for certain rop's - * - * SETACCESSNOGXCOPY when rop isn't GXcopy - * SETACCESS1 for any rop and foreground only used - * SETACCESS2 for any rop and both foreground and background used - */ - /* - * when rop != GXcopy we can use RPL or RSTR access type - * (mga2064w pp 5-19, 5-23, 5-24, 5-29, 5-31, 5-33, 5-34, 5-37, 5-39) - */ - #define SETACCESSNOGXCOPY(cmd,rop) \ - if( (rop == GXclear) || (rop == GXcopyInverted) || (rop == GXset) ) \ - cmd |= MGADWG_RPL; \ - else \ - cmd |= MGADWG_RSTR; ! #if PSZ != 24 ! /* ! * when rop == GXcopy and bpp != 24 we can use BLOCK access type ! * (mga2064w pp 5-23, 5-24, 5-33, 5-39) ! */ ! #define SETACCESS1(cmd,rop,fg) \ ! if( rop == GXcopy ) { \ ! cmd |= MGADWG_BLK; \ ! } else { \ ! SETACCESSNOGXCOPY(cmd,rop); \ ! } ! #define SETACCESS2(cmd,rop,bg,fg,transc) \ ! if( rop == GXcopy ) { \ ! if( transc || mga_useBLKopaqueExpand ) \ ! cmd |= MGADWG_BLK; \ ! else \ ! cmd |= MGADWG_RPL; \ ! } else { \ ! SETACCESSNOGXCOPY(cmd,rop); \ ! } ! #else /* PSZ != 24 */ ! ! /* ! * in 24 bpp, when rop == GXcopy, we can use BLOCK atype ! * only if color is gray (R=G=B=A) ! */ ! #define RGBEQUAL(c) ( !(((c >> 16) ^ c) & 0xFF) && !(((c >> 8) ^ c) & 0xFF) ) ! ! /* ! * SETACCESS1 checks only foreground color ! * (mga2064w pp 5-23) ! */ ! #define SETACCESS1(cmd,rop,fg) \ ! if( rop == GXcopy ) { \ ! if( RGBEQUAL(fg) ) \ ! { \ ! REPLICATE24(fg); \ ! mga_cmd |= MGADWG_BLK; \ ! } \ ! else \ ! mga_cmd |= MGADWG_RPL; \ ! } else { \ ! SETACCESSNOGXCOPY(cmd,rop); \ ! } ! ! /* ! * SETACCESS2 checks both foreground and background colors. ! * The background color is checked only if it isn't transparent (transc flag). ! * (mga2064w pp 5-24, 5-33, 5-39) ! */ ! #define SETACCESS2(cmd,rop,bg,fg,transc) \ ! if( rop == GXcopy ) { \ ! if( (transc || mga_useBLKopaqueExpand) && \ ! (transc || RGBEQUAL(bg)) && RGBEQUAL(fg) ) \ ! { \ ! REPLICATE24(bg); \ ! REPLICATE24(fg); \ ! cmd |= MGADWG_BLK; \ ! } \ ! else \ ! cmd |= MGADWG_RPL; \ ! } else { \ ! SETACCESSNOGXCOPY(cmd,rop); \ ! } ! ! #endif /* PSZ != 24 */ ! ! /* ! * This is the implementation of the SetupForFillRectSolid function ! * that sets up the coprocessor for a subsequent batch for solid ! * rectangle fills. ! */ ! void MGANAME(SetupForFillRectSolid)(color, rop, planemask) ! int color, rop; unsigned planemask; { ! mga_cmd = MGADWG_TRAP | MGADWG_NOZCMP | MGADWG_SOLID | MGADWG_ARZERO | ! MGADWG_SGNZERO | MGADWG_SHIFTZERO | MGADWG_BMONOLEF; ! /* set atype - foreground color only used (mga2064w pp 5-23) */ ! SETACCESS1(mga_cmd,rop,color); ! ! REPLICATE(color); ! SETFOREGROUNDCOLOR(color); #if PSZ != 24 ! REPLICATE(planemask); ! SETWRITEPLANEMASK(planemask); #endif ! SETRASTEROP(rop); ! /* mga_lastcmd is used by TwoPointLine() to restore the FillRect state */ ! OUTREG(MGAREG_DWGCTL, mga_lastcmd = mga_cmd); ! DISABLECLIPPING(); ! ! /* now, we construct mga_linecmd by masking the opcod and optimising */ ! /* the use of gxcopy rop. opcod is clear so we can draw lines quickly */ ! ! mga_linecmd = MGADWG_NOZCMP | MGADWG_SOLID | MGADWG_SHIFTZERO | ! MGADWG_BFCOL; ! if ( rop == GXcopy ) ! mga_linecmd |= mga_lastcmd & 0x000F0000; /* same bop, RPL atype */ ! else ! mga_linecmd |= mga_lastcmd & 0x000F0070; /* same bop and atype */ } - /* - * This is the implementation of the SubsequentFillRectSolid function - * that sends commands to the coprocessor to fill a solid rectangle of - * the specified location and size, with the parameters from the SetUp - * call. - */ ! void MGANAME(SubsequentFillRectSolid)(x, y, w, h) ! int x, y, w, h; { ! OUTREG(MGAREG_FXBNDRY, ((x + w) << 16) | x); ! OUTREG(MGAREG_YDSTLEN + MGAREG_EXEC, (y << 16) | h); ! } ! /* ! * This is the implementation of the SubsequentFillTrapezoidSolid ! */ ! void MGANAME(SubsequentFillTrapezoidSolid)(y, h, left, dxL, dyL, eL, ! right, dxR, dyR, eR) ! int y, h, left, dxL, dyL, eL, right, dxR, dyR, eR; ! { ! int sdxl = (dxL < 0); ! int sdxr = (dxR < 0); ! ! /* change command because we are after SetupForFillRectSolid */ ! OUTREG(MGAREG_DWGCTL, mga_cmd & ~(MGADWG_ARZERO | MGADWG_SGNZERO)); ! OUTREG(MGAREG_AR0, dyL); ! OUTREG(MGAREG_AR1, sdxl? (dxL + dyL - 1) : -dxL); ! OUTREG(MGAREG_AR2, sdxl? dxL : -dxL); ! OUTREG(MGAREG_AR4, sdxr? (dxR + dyR - 1) : -dxR); ! OUTREG(MGAREG_AR5, sdxr? dxR : -dxR); ! OUTREG(MGAREG_AR6, dyR); ! OUTREG(MGAREG_SGN, (sdxl << 1) | (sdxr << 5)); ! OUTREG(MGAREG_FXBNDRY, ((right + 1) << 16) | left); ! OUTREG(MGAREG_YDSTLEN + MGAREG_EXEC, (y << 16) | h); ! ! /* restore FillRect state for future rects */ ! OUTREG(MGAREG_DWGCTL, mga_cmd); } ! /* ! * This is the implementation of the SetupForScreenToScreenCopy function ! * that sets up the coprocessor for a subsequent batch for solid ! * screen-to-screen copies. Remember, we don't handle transparency, ! * so the transparency color is ignored. ! */ ! ! void MGANAME(SetupForScreenToScreenCopy)(xdir, ydir, rop, planemask, ! transparency_color) ! int xdir, ydir; ! int rop; ! unsigned planemask; ! int transparency_color; { ! int srcpitch; ! ! mga_rop = rop; ! mga_cmd = MGADWG_BITBLT | MGADWG_NOZCMP | MGADWG_SHIFTZERO | MGADWG_BFCOL; ! /* ! * now use faster access type for certain rop's ! * we can't use BLOCK atype for GXcopy (mga2064w 5-29) ! */ ! if( rop == GXcopy ) ! mga_cmd |= MGADWG_RPL; ! else { ! SETACCESSNOGXCOPY(mga_cmd,rop); ! } ! mgablitxdir = xdir; ! mgablitydir = ydir; ! if( ydir == 1 ) /* top - down */ ! { ! mga_sgn = 0; ! srcpitch = xf86AccelInfoRec.FramebufferWidth; ! } ! else /* bottom - up */ ! { ! mga_sgn = 4; ! srcpitch = -xf86AccelInfoRec.FramebufferWidth; ! } ! #if PSZ != 24 ! REPLICATE(planemask); ! SETWRITEPLANEMASK(planemask); #endif ! SETRASTEROP(rop); ! OUTREG(MGAREG_DWGCTL, mga_lastcmd = mga_cmd); ! OUTREG(MGAREG_AR5, srcpitch); ! DISABLECLIPPING(); ! mga_lastsgn = -1; ! mga_lastcxright = 0xFFFF; /* maxX */ } ! /* ! * This is the implementation of the SubsequentForScreenToScreenCopy ! * that sends commands to the coprocessor to perform a screen-to-screen ! * copy of the specified areas, with the parameters from the SetUp call. ! * In this sample implementation, the direction must be taken into ! * account when calculating the addresses (with coordinates, it might be ! * a little easier). ! */ ! void MGANAME(SubsequentScreenToScreenCopy)(xsrc, ysrc, xdst, ydst, w, h) ! int xsrc, ysrc, xdst, ydst, w, h; { ! long srcStart, srcStop; ! int cmd; ! int fxright = xdst + --w; ! int cxright = 0xFFFF; /* maxX */ ! /* check whether this blit can be converted to left-to-right blit */ ! int left_to_right = ((mgablitxdir == 1) || (ysrc != ydst)); ! ! /* ! * Try to use fast bitblt ! */ ! /* alignment constraints (SDK 5-30) ! */ if( #if PSZ == 32 ! !((xsrc ^ xdst) & 31) #elif PSZ == 16 ! !((xsrc ^ xdst) & 63) #else ! !((xsrc ^ xdst) & 127) #endif ! /* fast bitblt works only with GXcopy and from left to right ! */ ! && (mga_rop == GXcopy) && left_to_right && MGAusefbitblt) ! { ! /* undocumented constraints ! */ #if PSZ == 8 ! if( (xdst & (1 << 6)) && (((fxright >> 6) - (xdst >> 6)) & 7) == 7 ) cxright = fxright, fxright |= 1 << 6; #elif PSZ == 16 ! if( (xdst & (1 << 5)) && (((fxright >> 5) - (xdst >> 5)) & 7) == 7 ) cxright = fxright, fxright |= 1 << 5; #elif PSZ == 24 ! if( ((xdst * 3) & (1 << 6)) && ! ((((fxright * 3 + 2) >> 6) - ((xdst * 3) >> 6)) & 7) == 7 ) cxright = fxright, fxright = ((fxright * 3 + 2) | (1 << 6)) / 3; #elif PSZ == 32 ! if( (xdst & (1 << 4)) && (((fxright >> 4) - (xdst >> 4)) & 7) == 7 ) cxright = fxright, fxright |= 1 << 4; #endif ! /* command for fast blit (mga2064w pp 5-30) */ ! cmd = MGADWG_FBITBLT | MGADWG_RPL | MGADWG_NOZCMP | ! MGADWG_SHIFTZERO | 0x000A0000 | MGADWG_BFCOL; ! } ! else ! /* normal blit */ ! cmd = mga_cmd; ! ! if(mgablitydir != 1) /* bottom to top */ ! { ! ysrc += h - 1; ! ydst += h - 1; ! } ! if(left_to_right) /* left to right */ ! { ! srcStart = ysrc * xf86AccelInfoRec.FramebufferWidth + xsrc + MGAydstorg; ! srcStop = srcStart + w; ! mga_sgn &= ~1; ! } ! else /* right to left */ ! { ! srcStop = ysrc * xf86AccelInfoRec.FramebufferWidth + xsrc + MGAydstorg;; ! srcStart = srcStop + w; ! mga_sgn |= 1; ! } ! ! /* cmd, mga_sgn and cxright are constant in most cases ! */ ! if(cmd != mga_lastcmd) ! OUTREG(MGAREG_DWGCTL, mga_lastcmd = cmd); ! if(mga_sgn != mga_lastsgn) ! OUTREG(MGAREG_SGN, mga_lastsgn = mga_sgn); ! if(cxright != mga_lastcxright) ! OUTREG(MGAREG_CXRIGHT, mga_lastcxright = cxright); ! OUTREG(MGAREG_FXBNDRY, (fxright << 16) | xdst); ! OUTREG(MGAREG_YDSTLEN, (ydst << 16) | h); ! OUTREG(MGAREG_AR3, srcStart); ! OUTREG(MGAREG_AR0 + MGAREG_EXEC, srcStop); } ! /* ! * setup for screen-to-screen color expansion ! */ ! void MGANAME(SetupForScreenToScreenColorExpand)(bg, fg, rop, planemask) ! int bg, fg, rop; unsigned planemask; { ! /* handle transparent background */ ! int transc = ( bg == -1 ); ! ! /* bitblt with expansion (mga2064w pp 5-33) */ ! mga_cmd = MGADWG_BITBLT | MGADWG_NOZCMP | MGADWG_SGNZERO | ! MGADWG_SHIFTZERO | MGADWG_BMONOLEF; ! ! /* set atype, both foreground and background used */ ! SETACCESS2(mga_cmd,rop,bg,fg,transc) ! ! /* ! * check transparency ! */ ! if( transc ) ! mga_cmd |= MGADWG_TRANSC; else ! { ! REPLICATE(bg); ! SETBACKGROUNDCOLOR(bg); ! } ! REPLICATE(fg); ! SETFOREGROUNDCOLOR(fg); ! #if PSZ != 24 REPLICATE(planemask); ! SETWRITEPLANEMASK(planemask); #endif ! SETRASTEROP(rop); ! OUTREG(MGAREG_DWGCTL, mga_cmd); ! DISABLECLIPPING(); } ! /* ! * executing screen-to-screen color expansion ! */ ! void MGANAME(SubsequentScreenToScreenColorExpand)(srcx, srcy, x, y, w, h) ! int srcx, srcy, x, y, w, h; { ! int srcStart = srcy * xf86AccelInfoRec.FramebufferWidth * 8 + srcx ! + MGAydstorg; ! int srcStop = srcStart + w - 1; ! OUTREG(MGAREG_AR3, srcStart); ! OUTREG(MGAREG_AR0, srcStop); ! OUTREG(MGAREG_AR5, (w + 31) & ~31); /* source is DWORD-padded */ ! OUTREG(MGAREG_FXBNDRY, ((x + w - 1) << 16) | x); OUTREG(MGAREG_YDSTLEN + MGAREG_EXEC, (y << 16) | h); } ! /* ! * setup for CPU-to-screen color expansion ! */ ! void MGANAME(SetupForCPUToScreenColorExpand)(bg, fg, rop, planemask) int bg, fg, rop; unsigned planemask; { ! int transc = ( bg == -1 ); ! ! /* ILOAD with expansion (mga2064w pp 5-39) */ ! mga_cmd = MGADWG_ILOAD | MGADWG_LINEAR | MGADWG_NOZCMP | MGADWG_SGNZERO | ! MGADWG_SHIFTZERO | MGADWG_BMONOLEF; ! /* set atype, both foreground and background color used */ ! SETACCESS2(mga_cmd,rop,bg,fg,transc) ! ! /* ! * check transparency ! */ ! if( transc ) ! mga_cmd |= MGADWG_TRANSC; ! else ! { ! REPLICATE(bg); ! SETBACKGROUNDCOLOR(bg); } ! REPLICATE(fg); ! SETFOREGROUNDCOLOR(fg); #if PSZ != 24 ! REPLICATE(planemask); ! SETWRITEPLANEMASK(planemask); #endif ! SETRASTEROP(rop); ! OUTREG(MGAREG_DWGCTL, mga_cmd); ! OUTREG16(MGAREG_OPMODE, MGAOPM_DMA_BLIT); ! OUTREG(MGAREG_YTOP, 0x00000000); /* minPixelPointer */ ! OUTREG(MGAREG_YBOT, 0x007FFFFF); /* maxPixelPointer */ } - /* - * executing CPU-to-screen color expansion - */ void MGANAME(SubsequentCPUToScreenColorExpand)(x, y, w, h, skipleft) int x, y, w, h, skipleft; { ! OUTREG(MGAREG_CXBNDRY, ((x + w - 1) << 16) | ((x + skipleft) & 0xffff)); w = (w + 31) & ~31; /* source is dword padded */ OUTREG(MGAREG_AR0, (w * h) - 1); ! OUTREG(MGAREG_AR3, 0); /* we need it here for stability */ ! OUTREG(MGAREG_FXBNDRY, ((x + w - 1) << 16) | (x & 0xffff)); OUTREG(MGAREG_YDSTLEN + MGAREG_EXEC, (y << 16) | h); } ! /* ! * setup for 8x8 color expand pattern fill ! */ ! void MGANAME(SetupFor8x8PatternColorExpand)(patternx, patterny, bg, fg, ! rop, planemask) ! unsigned patternx, patterny, planemask; int bg, fg, rop; { ! int transc = ( bg == -1 ); ! ! /* patterned rectangle fill (mga2064w pp 5-24) */ ! mga_cmd = MGADWG_TRAP | MGADWG_NOZCMP | MGADWG_ARZERO | MGADWG_SGNZERO | ! MGADWG_BMONOLEF; ! /* set atype, both foreground and background used */ ! SETACCESS2(mga_cmd,rop,bg,fg,transc) ! ! /* ! * check transparency ! */ ! if( transc ) ! mga_cmd |= MGADWG_TRANSC; ! else ! { ! REPLICATE(bg); ! SETBACKGROUNDCOLOR(bg); } ! REPLICATE(fg); ! SETFOREGROUNDCOLOR(fg); #if PSZ != 24 ! REPLICATE(planemask); ! SETWRITEPLANEMASK(planemask); #endif ! SETRASTEROP(rop); ! OUTREG(MGAREG_DWGCTL, mga_cmd); ! OUTREG(MGAREG_PAT0, patternx); /* just store pattern */ ! OUTREG(MGAREG_PAT1, patterny); /* in chip registers */ ! DISABLECLIPPING(); ! mga_lastshift = -1; } ! /* ! * executing 8x8 color expand pattern fill ! */ ! void MGANAME(Subsequent8x8PatternColorExpand)(patternx, patterny, x, y, w, h) ! unsigned patternx, patterny; ! int x, y, w, h; { ! int shift = (patterny << 4) | patternx; ! if( shift != mga_lastshift ) ! OUTREG(MGAREG_SHIFT, mga_lastshift = shift); ! OUTREG(MGAREG_FXBNDRY, ((x + w) << 16) | x); OUTREG(MGAREG_YDSTLEN + MGAREG_EXEC, (y << 16) | h); } - /* - * MgaSubsequentTwoPointLine () - * by ajv 961116 - * - * changelog: - * 961116 - started - * 961118 - merged it with 3.2a, added capstyle, added compatibility with - * SetupForFillRectSolid (which does the setup for lines and - * rectangles) - * 961120 - modified it so that fewer instructions are executed per line - * segment, and moved some code into SetupForFillRect so that - * that code is not constantly being (unnecessarily) reevaluated - * all the time. - * 961121 - added one time only clipping as per Harm's notes. Also worked - * to introduce concurrency by doing more work behind the EXEC. - * Reordered code for register starved CPU's (Intel x86) plus - * it achieves better locality of code for other processors. - */ ! void ! MGANAME(SubsequentTwoPointLine)(x1, y1, x2, y2, bias) ! int x1, y1, x2, y2, bias; ! { ! register int mga_localcmd = mga_linecmd; ! /* draw the last pixel? */ ! if ( bias & 0x0100 ) ! mga_localcmd |= MGADWG_AUTOLINE_OPEN; /* no */ ! else ! mga_localcmd |= MGADWG_AUTOLINE_CLOSE; /* yep */ - OUTREG(MGAREG_DWGCTL, mga_localcmd); - OUTREG(MGAREG_XYSTRT, ( y1 << 16 ) | (x1 & 0xffff)); - OUTREG(MGAREG_XYEND + MGAREG_EXEC, ( y2 << 16 ) | (x2 & 0xffff)); - - /* do some work whilst the chipset is busy */ - - /* if clipping is on, disable it */ - if ( mga_ClipRect ) - { - DISABLECLIPPING(); - } - - /* restore FillRect state for future rects */ - OUTREG(MGAREG_DWGCTL, mga_lastcmd); - } - void ! MGANAME(SetupForDashedLine)(int fg, int bg, int rop, unsigned int planemask, ! int size) { ! /* handle transparent background */ ! int transc = ( bg == -1 ); ! MGAStormSync(); ! /* load the style length part into the SHIFT register */ ! ! mgaStylelen = ( (size - 1) << 16 ) & 0x007f0000; ! OUTREG(MGAREG_SHIFT, mgaStylelen); ! mgaStylelen = size; ! ! /* load the pattern */ ! ! switch ( ((size + 31) >> 5) ) ! { ! case 4: OUTREG(MGAREG_SRC3, mgaDashedPatternBuf[3]); ! case 3: OUTREG(MGAREG_SRC2, mgaDashedPatternBuf[2]); ! case 2: OUTREG(MGAREG_SRC1, mgaDashedPatternBuf[1]); ! default: OUTREG(MGAREG_SRC0, mgaDashedPatternBuf[0]); } ! /* closed Bresenham lines with a linestyle, p5-19 or p5-30 */ ! mga_cmd = MGADWG_LINE_CLOSE | MGADWG_BFCOL; ! ! /* ! * check transparency and set bg/fg colors ! */ ! ! if ( transc ) ! mga_cmd |= MGADWG_TRANSC; ! else ! { REPLICATE(bg); ! SETBACKGROUNDCOLOR(bg); } ! REPLICATE(fg); ! SETFOREGROUNDCOLOR(fg); ! ! /* set planemask (if appropiate) */ ! #if PSZ != 24 ! REPLICATE(planemask); ! SETWRITEPLANEMASK(planemask); #endif ! /* set atype, based upon fastest rules */ ! ! if ( rop == GXcopy ) ! { ! mga_cmd |= MGADWG_RPL; } ! else ! { ! SETACCESSNOGXCOPY(mga_cmd, rop); ! } - /* set rop (bop) */ ! SETRASTEROP(rop); ! /* set up power drawing mode */ - OUTREG(MGAREG_DWGCTL, mga_cmd); ! /* we have to do this to allow the hw clipping to work */ ! DISABLECLIPPING(); ! } void ! MGANAME(SubsequentDashedBresenhamLine)(int x1, int y1, int octant, int err, ! int e1, int e2, int length, int start) { ! unsigned int oct = 0; ! unsigned int startPos = mgaStylelen - start; ! #ifdef DEBUG ! if ( start < 0 ) ! ErrorF("mga dashed lines: -ve start (%d, %d)\n", mgaStylelen, start); ! if ( startPos > mgaStylelen ) ! ErrorF("mga dashed lines: startpos > mgaStylelen (%d, %d)\n", mgaStylelen, start); ! if ( startPos > 127 ) ! ErrorF("mga dashed lines: startPos > 127 (%d, %d)\n", mgaStylelen, start); #endif ! OUTREG16(MGAREG_SHIFT, startPos & 0x7f); ! /* load the xy position. The Mill documentation has an error, xdst not ydst */ ! OUTREG16(MGAREG_XDST, x1); ! OUTREG(MGAREG_YDSTLEN, (y1 << 16) | length); - if ( octant & YDECREASING ) - oct |= 4; - if ( octant & XDECREASING ) - oct |= 2; - if ( !((octant & YMAJOR) == YMAJOR) ) - oct |= 1; - OUTREG16(MGAREG_SGN, oct); - OUTREG(MGAREG_AR0, e1 & 0x3ffff); - OUTREG(MGAREG_AR1, err & 0x0fffffff); - OUTREG(MGAREG_AR2 + MGAREG_EXEC, e2 & 0x3ffff); - /* disable one-time clipping (see XAA notes) */ - if ( mga_ClipRect ) - { - DISABLECLIPPING(); - } - } - void - MGANAME(SetClippingRectangle)(x1, y1, x2, y2) - int x1, y1, x2, y2; - { - int tmp; - - #if 0 /* [rdk] I think we don't need it, see xaa/NOTES */ - if ( x2 < x1 ) - { - tmp = x2; - x2 = x1; - x1 = tmp; - } - if ( y2 < y1 ) - { - tmp = y2; - y2 = y1; - y1 = tmp; - } - #endif - - OUTREG(MGAREG_CXBNDRY, (x2 << 16) | x1); - OUTREG(MGAREG_YTOP, - y1 * xf86AccelInfoRec.FramebufferWidth + MGAydstorg); - OUTREG(MGAREG_YBOT, - y2 * xf86AccelInfoRec.FramebufferWidth + MGAydstorg); - - /* indicate to TwoPoint Line that one time only clipping is on */ - mga_ClipRect = 1; - } --- 299,945 ---- maccess = 2; break; } ! ! WAITFIFO(8); OUTREG(MGAREG_PITCH, vga256InfoRec.displayWidth); OUTREG(MGAREG_YDSTORG, MGAydstorg); OUTREG(MGAREG_MACCESS, maccess); OUTREG(MGAREG_PLNWT, ~0); ! OUTREG(MGAREG_OPMODE, MGAOPM_DMA_BLIT); ! ! /* put clipping in a know state */ ! OUTREG(MGAREG_CXBNDRY, 0xFFFF0000); /* (maxX << 16) | minX */ ! OUTREG(MGAREG_YTOP, 0x00000000); /* minPixelPointer */ ! OUTREG(MGAREG_YBOT, 0x007FFFFF); /* maxPixelPointer */ } ! #endif /* PSZ == 8 */ ! /*********************************************\ ! | Screen-to-Screen Copy | ! \*********************************************/ ! #define BLIT_LEFT 1 ! #define BLIT_UP 4 ! static CARD32 BltScanDirection; ! void ! MGANAME(SetupForScreenToScreenCopy)(xdir, ydir, rop, planemask, trans_color) ! int xdir, ydir; ! int rop; unsigned planemask; + int trans_color; { ! xf86AccelInfoRec.SubsequentScreenToScreenCopy = ! MGANAME(SubsequentScreenToScreenCopy); ! REPLICATE(planemask); ! BltScanDirection = 0; ! if(ydir == -1) BltScanDirection |= BLIT_UP; ! if(xdir == -1) BltScanDirection |= BLIT_LEFT; ! if(BltScanDirection) { ! WAITFIFO(4); ! OUTREG(MGAREG_DWGCTL, MGAAtypeNoBLK[rop] | MGADWG_SHIFTZERO | ! MGADWG_BITBLT | MGADWG_BFCOL); ! OUTREG(MGAREG_SGN, BltScanDirection); ! } else { ! if(MGAusefbitblt && (rop == GXcopy)) { ! if(MGAIsMillennium2) ! xf86AccelInfoRec.SubsequentScreenToScreenCopy = ! MGANAME(SubsequentScreenToScreenCopy_FastBlit); ! else ! xf86AccelInfoRec.SubsequentScreenToScreenCopy = ! MGANAME(SubsequentScreenToScreenCopy_FastBlit_Broken); ! } ! WAITFIFO(3); ! OUTREG(MGAREG_DWGCTL, MGAAtypeNoBLK[rop] | MGADWG_SHIFTZERO | ! MGADWG_BITBLT | MGADWG_SGNZERO | MGADWG_BFCOL); ! } #if PSZ != 24 ! OUTREG(MGAREG_PLNWT, planemask); #endif ! OUTREG(MGAREG_AR5, ydir * xf86AccelInfoRec.FramebufferWidth); } ! void ! MGANAME(SubsequentScreenToScreenCopy)(srcX, srcY, dstX, dstY, w, h) ! int srcX, srcY, dstX, dstY, w, h; { ! register int start, end; ! ! if(BltScanDirection & BLIT_UP) { ! srcY += h - 1; ! dstY += h - 1; ! } ! w--; ! start = end = XYADDRESS(srcX, srcY); ! if(BltScanDirection & BLIT_LEFT) start += w; ! else end += w; ! ! WAITFIFO(4); ! OUTREG(MGAREG_AR0, end); ! OUTREG(MGAREG_AR3, start); ! OUTREG(MGAREG_FXBNDRY, ((dstX + w) << 16) | dstX); ! OUTREG(MGAREG_YDSTLEN + MGAREG_EXEC, (dstY << 16) | h); } ! void ! MGANAME(SubsequentScreenToScreenCopy_FastBlit)(srcX, srcY, dstX, dstY, w, h) ! int srcX, srcY, dstX, dstY, w, h; { ! register int start, end; ! w--; ! start = XYADDRESS(srcX, srcY); ! end = start + w; ! /* we assume the driver asserts screen pitches such that ! we can always use fastblit for scrolling */ ! if( ! #if PSZ == 32 ! !((srcX ^ dstX) & 31) ! #elif PSZ == 16 ! !((srcX ^ dstX) & 63) ! #else ! !((srcX ^ dstX) & 127) #endif ! ) { ! if(MGAMaxFastBlitY) { ! if(((srcY + h) > MGAMaxFastBlitY) || ! ((dstY + h) > MGAMaxFastBlitY)) ! goto FASTBLIT_BAILOUT; ! } ! ! WAITFIFO(6); ! OUTREG(MGAREG_DWGCTL, 0x040A600C); ! OUTREG(MGAREG_AR0, end); ! OUTREG(MGAREG_AR3, start); ! OUTREG(MGAREG_FXBNDRY, ((dstX + w) << 16) | dstX); ! OUTREG(MGAREG_YDSTLEN + MGAREG_EXEC, (dstY << 16) | h); ! OUTREG(MGAREG_DWGCTL, MGAAtypeNoBLK[GXcopy] | MGADWG_SHIFTZERO | ! MGADWG_BITBLT | MGADWG_SGNZERO | MGADWG_BFCOL); ! return; ! } ! ! FASTBLIT_BAILOUT: ! ! WAITFIFO(4); ! OUTREG(MGAREG_AR0, end); ! OUTREG(MGAREG_AR3, start); ! OUTREG(MGAREG_FXBNDRY, ((dstX + w) << 16) | dstX); ! OUTREG(MGAREG_YDSTLEN + MGAREG_EXEC, (dstY << 16) | h); } ! ! /* Workaround for fastblit bug in Millennium 1 */ ! ! void ! MGANAME(SubsequentScreenToScreenCopy_FastBlit_Broken)(srcX, srcY, dstX, dstY, w, h) ! int srcX, srcY, dstX, dstY, w, h; { ! register int start, end; ! ! w--; ! start = XYADDRESS(srcX, srcY); ! end = start + w; ! ! /* we assume the driver asserts screen pitches such that ! we can always use fastblit for scrolling */ if( #if PSZ == 32 ! !((srcX ^ dstX) & 31) #elif PSZ == 16 ! !((srcX ^ dstX) & 63) #else ! !((srcX ^ dstX) & 127) #endif ! ) { ! int cxright, fxright = dstX + w; ! ! if(MGAMaxFastBlitY) { ! if(((srcY + h) > MGAMaxFastBlitY) || ! ((dstY + h) > MGAMaxFastBlitY)) ! goto FASTBLIT_BAILOUT_BROKEN; ! } ! #if PSZ == 8 ! if( (dstX & (1 << 6)) && (((fxright >> 6) - (dstX >> 6)) & 7) == 7 ) { cxright = fxright, fxright |= 1 << 6; #elif PSZ == 16 ! if( (dstX & (1 << 5)) && (((fxright >> 5) - (dstX >> 5)) & 7) == 7 ) { cxright = fxright, fxright |= 1 << 5; #elif PSZ == 24 ! if( ((dstX * 3) & (1 << 6)) && ! ((((fxright * 3 + 2) >> 6) - ((dstX * 3) >> 6)) & 7) == 7 ) { cxright = fxright, fxright = ((fxright * 3 + 2) | (1 << 6)) / 3; #elif PSZ == 32 ! if( (dstX & (1 << 4)) && (((fxright >> 4) - (dstX >> 4)) & 7) == 7 ) { cxright = fxright, fxright |= 1 << 4; #endif ! ! WAITFIFO(8); ! OUTREG(MGAREG_CXRIGHT, cxright); ! OUTREG(MGAREG_DWGCTL, 0x040A600C); ! OUTREG(MGAREG_AR0, end); ! OUTREG(MGAREG_AR3, start); ! OUTREG(MGAREG_FXBNDRY, (fxright << 16) | dstX); ! OUTREG(MGAREG_YDSTLEN + MGAREG_EXEC, (dstY << 16) | h); ! OUTREG(MGAREG_DWGCTL, MGAAtypeNoBLK[GXcopy] | MGADWG_SHIFTZERO | ! MGADWG_BITBLT | MGADWG_SGNZERO | MGADWG_BFCOL); ! OUTREG(MGAREG_CXRIGHT, 0xFFFF); ! } else { ! WAITFIFO(6); ! OUTREG(MGAREG_DWGCTL, 0x040A600C); ! OUTREG(MGAREG_AR0, end); ! OUTREG(MGAREG_AR3, start); ! OUTREG(MGAREG_FXBNDRY, ((dstX + w) << 16) | dstX); ! OUTREG(MGAREG_YDSTLEN + MGAREG_EXEC, (dstY << 16) | h); ! OUTREG(MGAREG_DWGCTL, MGAAtypeNoBLK[GXcopy] | MGADWG_SHIFTZERO | ! MGADWG_BITBLT | MGADWG_SGNZERO | MGADWG_BFCOL); ! } ! return; ! } ! FASTBLIT_BAILOUT_BROKEN: ! ! WAITFIFO(4); ! OUTREG(MGAREG_AR0, end); ! OUTREG(MGAREG_AR3, start); ! OUTREG(MGAREG_FXBNDRY, ((dstX + w) << 16) | dstX); ! OUTREG(MGAREG_YDSTLEN + MGAREG_EXEC, (dstY << 16) | h); } ! ! ! ! ! ! ! /*********************************************\ ! | Solid Filled Rectangles | ! \*********************************************/ ! ! static CARD32 FilledRectCMD; ! static CARD32 SolidLineCMD; ! ! void ! MGANAME(SetupForFillRectSolid)(color, rop, planemask) ! int color, rop; unsigned planemask; { ! #if PSZ == 24 ! if(!RGBEQUAL(color)) ! FilledRectCMD = MGADWG_TRAP | MGADWG_SOLID | MGADWG_ARZERO | ! MGADWG_SGNZERO | MGADWG_SHIFTZERO | ! MGADWG_BMONOLEF | MGAAtypeNoBLK[rop]; else ! #endif ! FilledRectCMD = MGADWG_TRAP | MGADWG_SOLID | MGADWG_ARZERO | ! MGADWG_SGNZERO | MGADWG_SHIFTZERO | ! MGADWG_BMONOLEF | MGAAtype[rop]; ! SolidLineCMD = MGADWG_LINE_OPEN | MGADWG_SOLID | MGADWG_SHIFTZERO | ! MGADWG_BFCOL | MGAAtypeNoBLK[rop]; ! ! if(MGAIsMillennium2) FilledRectCMD |= MGADWG_TRANSC; ! ! REPLICATE24(color); REPLICATE(planemask); ! WAITFIFO(3); ! OUTREG(MGAREG_FCOL, color); ! #if PSZ != 24 ! OUTREG(MGAREG_PLNWT, planemask); #endif ! OUTREG(MGAREG_DWGCTL, FilledRectCMD); } ! ! void ! MGANAME(SubsequentFillRectSolid)(x, y, w, h) ! int x, y, w, h; { ! WAITFIFO(2); ! OUTREG(MGAREG_FXBNDRY, ((x + w) << 16) | x); ! OUTREG(MGAREG_YDSTLEN + MGAREG_EXEC, (y << 16) | h); ! } ! /******************************\ ! | Solid Trapezoids | ! \******************************/ ! ! ! void ! MGANAME(SubsequentFillTrapezoidSolid)(y, h, left, dxL, dyL, eL, ! right, dxR, dyR, eR) ! int y, h, left, dxL, dyL, eL, right, dxR, dyR, eR; ! { ! int sdxl = (dxL < 0); ! int ar2 = sdxl? dxL : -dxL; ! int sdxr = (dxR < 0); ! int ar5 = sdxr? dxR : -dxR; ! ! WAITFIFO(11); ! OUTREG(MGAREG_DWGCTL, FilledRectCMD & ~(MGADWG_ARZERO | MGADWG_SGNZERO)); ! OUTREG(MGAREG_AR0, dyL); ! OUTREG(MGAREG_AR1, ar2 - eL); ! OUTREG(MGAREG_AR2, ar2); ! OUTREG(MGAREG_AR4, ar5 - eR); ! OUTREG(MGAREG_AR5, ar5); ! OUTREG(MGAREG_AR6, dyR); ! OUTREG(MGAREG_SGN, (sdxl << 1) | (sdxr << 5)); ! OUTREG(MGAREG_FXBNDRY, ((right + 1) << 16) | left); OUTREG(MGAREG_YDSTLEN + MGAREG_EXEC, (y << 16) | h); + OUTREG(MGAREG_DWGCTL, FilledRectCMD); } ! /********************************\ ! | Bresenham Lines | ! \********************************/ ! ! static CARD32 MGAOctants[8] = { 1, 0, 5, 4, 3, 2, 7, 6 }; ! ! void ! MGANAME(SubsequentBresenhamLine)(x1, y1, octant, err, e1, e2, length) ! int x1, y1, octant, err, e1, e2, length; ! { ! if(MGAIsMillennium2 && !e1) { ! WAITFIFO(2); ! OUTREG(MGAREG_FXBNDRY, ((x1 + 1) << 16) | x1); ! OUTREG(MGAREG_YDSTLEN + MGAREG_EXEC, (y1 << 16) | length); ! return; ! } ! ! WAITFIFO(8); ! OUTREG(MGAREG_DWGCTL, SolidLineCMD); ! OUTREG(MGAREG_SGN, MGAOctants[octant & 7]); ! OUTREG(MGAREG_AR0, e1); ! OUTREG(MGAREG_AR1, err); ! OUTREG(MGAREG_AR2, e2); ! OUTREG(MGAREG_XDST, x1); ! OUTREG(MGAREG_YDSTLEN + MGAREG_EXEC, (y1 << 16) | length); ! OUTREG(MGAREG_DWGCTL, FilledRectCMD); ! } ! ! ! /********************************************\ ! | CPU to Screen Color Expansion | ! \********************************************/ ! ! void ! MGANAME(SetupForCPUToScreenColorExpand)(bg, fg, rop, planemask) int bg, fg, rop; unsigned planemask; { ! CARD32 mgaCMD = MGADWG_ILOAD | MGADWG_LINEAR | MGADWG_SGNZERO | ! MGADWG_SHIFTZERO | MGADWG_BMONOLEF; ! ! REPLICATE24(fg); ! REPLICATE(planemask); ! if(bg == -1) { ! #if PSZ == 24 ! if(!RGBEQUAL(fg)) ! mgaCMD |= MGADWG_TRANSC | MGAAtypeNoBLK[rop]; ! else ! #endif ! mgaCMD |= MGADWG_TRANSC | MGAAtype[rop]; ! ! WAITFIFO(3); ! } else { ! #if PSZ == 24 ! if(MGAUseBLKOpaqueExpansion && RGBEQUAL(fg) && RGBEQUAL(bg)) ! #else ! if(MGAUseBLKOpaqueExpansion) ! #endif ! mgaCMD |= MGAAtype[rop]; ! else ! mgaCMD |= MGAAtypeNoBLK[rop]; ! REPLICATE24(bg); ! WAITFIFO(4); ! OUTREG(MGAREG_BCOL, bg); } ! OUTREG(MGAREG_FCOL, fg); #if PSZ != 24 ! OUTREG(MGAREG_PLNWT, planemask); #endif ! OUTREG(MGAREG_DWGCTL, mgaCMD); } void MGANAME(SubsequentCPUToScreenColorExpand)(x, y, w, h, skipleft) int x, y, w, h, skipleft; { ! MGAIsClipped = TRUE; ! WAITFIFO(5); ! OUTREG(MGAREG_CXBNDRY, ((x + w - 1) << 16) | ((x + skipleft) & 0xFFFF)); w = (w + 31) & ~31; /* source is dword padded */ OUTREG(MGAREG_AR0, (w * h) - 1); ! OUTREG(MGAREG_AR3, 0); /* crashes occasionally without this */ ! OUTREG(MGAREG_FXBNDRY, ((x + w - 1) << 16) | (x & 0xFFFF)); OUTREG(MGAREG_YDSTLEN + MGAREG_EXEC, (y << 16) | h); } ! /***************************************\ ! | Screen to Screen Color Expansion | ! \***************************************/ ! ! void ! MGANAME(SetupForScreenToScreenColorExpand)(bg, fg, rop, planemask) int bg, fg, rop; + unsigned planemask; { ! CARD32 mgaCMD = MGADWG_BITBLT | MGADWG_SGNZERO | MGADWG_SHIFTZERO; ! ! REPLICATE24(fg); ! REPLICATE(planemask); ! if(bg == -1) { ! #if PSZ == 24 ! if(!RGBEQUAL(fg)) ! mgaCMD |= MGADWG_TRANSC | MGAAtypeNoBLK[rop]; ! else ! #endif ! mgaCMD |= MGADWG_TRANSC | MGAAtype[rop]; ! ! WAITFIFO(4); ! } else { ! #if PSZ == 24 ! if(MGAUseBLKOpaqueExpansion && RGBEQUAL(fg) && RGBEQUAL(bg)) ! #else ! if(MGAUseBLKOpaqueExpansion) ! #endif ! mgaCMD |= MGAAtype[rop]; ! else ! mgaCMD |= MGAAtypeNoBLK[rop]; ! REPLICATE24(bg); ! WAITFIFO(5); ! OUTREG(MGAREG_BCOL, bg); } ! OUTREG(MGAREG_FCOL, fg); #if PSZ != 24 ! OUTREG(MGAREG_PLNWT, planemask); #endif ! OUTREG(MGAREG_AR5, xf86AccelInfoRec.FramebufferWidth * PSZ); ! OUTREG(MGAREG_DWGCTL, mgaCMD); } ! void MGANAME(SubsequentScreenToScreenColorExpand)(srcx, srcy, x, y, w, h) ! int srcx, srcy, x, y, w, h; { ! register int start, end; ! ! start = (XYADDRESS(0, srcy) * PSZ) + srcx; ! end = start + w - 1; ! ! WAITFIFO(4); ! OUTREG(MGAREG_AR3, start); ! OUTREG(MGAREG_AR0, end); ! OUTREG(MGAREG_FXBNDRY, ((x + w - 1) << 16) | x); OUTREG(MGAREG_YDSTLEN + MGAREG_EXEC, (y << 16) | h); } ! /************************************\ ! | Dashed Bresenham Lines | ! \************************************/ ! static CARD32 mgaStylelen; ! static Bool NiceDashPattern; ! static CARD32 NiceDashCMD; ! static CARD32 DashCMD; void ! MGANAME(SetupForDashedLine)(fg, bg, rop, planemask, size) ! int fg, bg, rop; ! unsigned int planemask; ! int size; { ! extern unsigned char byte_reversed[256]; ! int dwords = (size + 31) >> 5; ! DashCMD = MGADWG_LINE_OPEN | MGADWG_BFCOL | MGAAtypeNoBLK[rop]; ! mgaStylelen = size - 1; ! REPLICATE(fg); ! REPLICATE(planemask); ! /* We see if we can draw horizontal lines as 8x8 pattern fills. ! This is worthwhile since the pattern fills can use block mode ! and the default X pattern is 8 pixels long. The forward pattern ! is the top scanline, the backwards pattern is the next one. */ ! switch(size) { ! case 2: MGADashPattern[0] |= MGADashPattern[0] << 2; ! case 4: MGADashPattern[0] |= MGADashPattern[0] << 4; ! case 8: MGADashPattern[0] &= 0xFF; ! MGADashPattern[0] |= byte_reversed[MGADashPattern[0]] << 16; ! MGADashPattern[0] |= MGADashPattern[0] << 8; ! NiceDashCMD = MGADWG_TRAP | MGADWG_ARZERO | MGADWG_SGNZERO | ! MGADWG_BMONOLEF; ! NiceDashPattern = TRUE; ! if(bg == -1) { ! #if PSZ == 24 ! if(!RGBEQUAL(fg)) ! NiceDashCMD |= MGADWG_TRANSC | MGAAtypeNoBLK[rop]; ! else ! #endif ! NiceDashCMD |= MGADWG_TRANSC | MGAAtype[rop]; ! } else { ! #if PSZ == 24 ! if(MGAUseBLKOpaqueExpansion && RGBEQUAL(fg) && RGBEQUAL(bg)) ! #else ! if(MGAUseBLKOpaqueExpansion) ! #endif ! NiceDashCMD |= MGAAtype[rop]; ! else ! NiceDashCMD |= MGAAtypeNoBLK[rop]; ! } ! break; ! default: NiceDashPattern = FALSE; } ! if(bg == -1) { ! DashCMD |= MGADWG_TRANSC; ! WAITFIFO(dwords + 3); ! } else { REPLICATE(bg); ! WAITFIFO(dwords + 4); ! OUTREG(MGAREG_BCOL, bg); } ! OUTREG(MGAREG_DWGCTL, DashCMD); #if PSZ != 24 ! OUTREG(MGAREG_PLNWT, planemask); #endif + OUTREG(MGAREG_FCOL, fg); ! switch (dwords) { ! case 4: OUTREG(MGAREG_SRC3, MGADashPattern[3]); ! case 3: OUTREG(MGAREG_SRC2, MGADashPattern[2]); ! case 2: OUTREG(MGAREG_SRC1, MGADashPattern[1]); ! default: OUTREG(MGAREG_SRC0, MGADashPattern[0]); } ! } ! void ! MGANAME(SubsequentDashedBresenhamLine)(x1, y1, octant, err, e1, e2, len ,start) ! int x1, y1, octant, err, e1, e2, len ,start; ! { ! if(NiceDashPattern && !e1 && !(octant & YMAJOR)) { ! WAITFIFO(5); ! OUTREG(MGAREG_DWGCTL, NiceDashCMD); ! if(octant & XDECREASING) { ! len = x1 - len + 1; ! OUTREG(MGAREG_SHIFT, ((-y1 & 0x07) << 4) | ! ((len - start) & 0x07)); ! OUTREG(MGAREG_FXBNDRY, ((x1 + 1) << 16) | len); ! } else { ! OUTREG(MGAREG_SHIFT, (((1 - y1) & 0x07) << 4) | ! ((start - x1) & 0x07)); ! OUTREG(MGAREG_FXBNDRY, ((x1 + len) << 16) | x1); ! } ! OUTREG(MGAREG_YDSTLEN + MGAREG_EXEC, (y1 << 16) | 1); ! OUTREG(MGAREG_DWGCTL, DashCMD); ! return; ! } ! WAITFIFO(7); ! OUTREG(MGAREG_SHIFT, (mgaStylelen << 16 ) | (mgaStylelen - start)); ! OUTREG(MGAREG_SGN, MGAOctants[octant & 7]); ! OUTREG(MGAREG_AR0, e1); ! OUTREG(MGAREG_AR1, err); ! OUTREG(MGAREG_AR2, e2); ! OUTREG(MGAREG_XDST, x1); ! OUTREG(MGAREG_YDSTLEN + MGAREG_EXEC, (y1 << 16) | len); ! } ! /****************************\ ! | 8x8 Rectangular Fill | ! \****************************/ ! static CARD32 PatternRectCMD; void ! MGANAME(SetupFor8x8PatternColorExpand)(patternx, patterny, bg, fg, ! rop, planemask) ! unsigned patternx, patterny, planemask; ! int bg, fg, rop; { ! PatternRectCMD = MGADWG_TRAP | MGADWG_ARZERO | MGADWG_SGNZERO | ! MGADWG_BMONOLEF; ! xf86AccelInfoRec.Subsequent8x8PatternColorExpand = ! MGANAME(Subsequent8x8PatternColorExpand); ! REPLICATE24(fg); ! REPLICATE(planemask); ! ! if(bg == -1) { ! #if PSZ == 24 ! if(!RGBEQUAL(fg)) ! PatternRectCMD |= MGADWG_TRANSC | MGAAtypeNoBLK[rop]; ! else ! #endif ! PatternRectCMD |= MGADWG_TRANSC | MGAAtype[rop]; ! WAITFIFO(5); ! } else { ! #if PSZ == 24 ! if(MGAUseBLKOpaqueExpansion && RGBEQUAL(fg) && RGBEQUAL(bg)) ! #else ! if(MGAUseBLKOpaqueExpansion) #endif + PatternRectCMD |= MGAAtype[rop]; + else + PatternRectCMD |= MGAAtypeNoBLK[rop]; + REPLICATE24(bg); + WAITFIFO(6); + OUTREG(MGAREG_BCOL, bg); + } ! OUTREG(MGAREG_FCOL, fg); ! #if PSZ != 24 ! OUTREG(MGAREG_PLNWT, planemask); ! #endif ! OUTREG(MGAREG_DWGCTL, PatternRectCMD); ! OUTREG(MGAREG_PAT0, patternx); ! OUTREG(MGAREG_PAT1, patterny); ! } ! void ! MGANAME(Subsequent8x8PatternColorExpand)(patternx, patterny, x, y, w, h) ! unsigned patternx, patterny; ! int x, y, w, h; ! { ! WAITFIFO(3); ! OUTREG(MGAREG_SHIFT, (patterny << 4) | patternx); ! OUTREG(MGAREG_FXBNDRY, ((x + w) << 16) | x); ! OUTREG(MGAREG_YDSTLEN + MGAREG_EXEC, (y << 16) | h); ! xf86AccelInfoRec.Subsequent8x8PatternColorExpand = ! MGANAME(Subsequent8x8PatternColorExpand_Additional); ! } ! void ! MGANAME(Subsequent8x8PatternColorExpand_Additional)(patternx, patterny, x, y, w, h) ! unsigned patternx, patterny; ! int x, y, w, h; ! { ! WAITFIFO(2); ! OUTREG(MGAREG_FXBNDRY, ((x + w) << 16) | x); ! OUTREG(MGAREG_YDSTLEN + MGAREG_EXEC, (y << 16) | h); ! } *** ./xfree86/vga256/drivers/s3v/Imakefile@@/PUBLIC-LATEST Sat Jul 19 10:56:57 1997 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/s3v/Imakefile Fri Mar 6 16:54:23 1998 *************** *** 1,7 **** ! XCOMM $TOG: Imakefile /main/1 1997/07/19 10:56:59 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/s3v/Imakefile,v 1.1.2.1 1997/05/14 07:52:55 dawes Exp $ /* * * Copyright 1995-1997 The XFree86 Project, Inc. --- 1,7 ---- ! XCOMM $TOG: Imakefile /main/2 1998/03/06 16:56:01 kaleb $ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/s3v/Imakefile,v 1.1.2.1 1997/05/14 07:52:55 dawes Exp $ */ /* * * Copyright 1995-1997 The XFree86 Project, Inc. *** ./xfree86/vga256/drivers/s3v/regs3v.h@@/PUBLIC-LATEST Sun Aug 10 13:06:10 1997 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/s3v/regs3v.h Fri Mar 6 16:54:28 1998 *************** *** 1,8 **** ! /* $TOG: regs3v.h /main/2 1997/08/10 13:04:46 kaleb $ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/s3v/regs3v.h,v 1.1.2.2 1997/06/29 08:43:37 dawes Exp $ */ /* regs3v.h * --- 1,8 ---- ! /* $TOG: regs3v.h /main/3 1998/03/06 16:56:05 kaleb $ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/s3v/regs3v.h,v 1.1.2.3 1998/01/31 14:23:30 hohndel Exp $ */ /* regs3v.h * *************** *** 23,29 **** * PERFORMANCE OF THIS SOFTWARE. * */ ! /* $TOG: regs3v.h /main/2 1997/08/10 13:04:46 kaleb $ */ /* Taken from accel/s3_virge code */ /* 23/03/97 S. Marineau: fixed bug with first Doubleword Offset macros --- 23,29 ---- * PERFORMANCE OF THIS SOFTWARE. * */ ! /* $TOG: regs3v.h /main/3 1998/03/06 16:56:05 kaleb $ */ /* Taken from accel/s3_virge code */ /* 23/03/97 S. Marineau: fixed bug with first Doubleword Offset macros *************** *** 72,77 **** --- 72,79 ---- #define PCI_ViRGE 0x5631 #define PCI_ViRGE_VX 0x883D #define PCI_ViRGE_DXGX 0x8A01 + #define PCI_ViRGE_GX2 0x8A10 + #define PCI_ViRGE_MX 0x8C01 /* Chip tags */ #define S3_UNKNOWN 0 *************** *** 78,83 **** --- 80,87 ---- #define S3_ViRGE 1 #define S3_ViRGE_VX 2 #define S3_ViRGE_DXGX 3 + #define S3_ViRGE_GX2 4 + #define S3_ViRGE_MX 5 /* VESA Approved Register Definitions */ *************** *** 377,383 **** #define WaitIdle() do { mem_barrier(); while (!(IN_SUBSYS_STAT() & 0x2000)); } while (0) /* Wait until Command FIFO is empty */ ! #define WaitCommandEmpty() do { mem_barrier(); while (!(((((mmtr)s3vMmioMem)->subsys_regs.regs.adv_func_cntl)) & 0x200)); } while (0) /* Wait until a DMA transfer is done */ #define WaitDMAEmpty() do { mem_barrier(); while ((((mmtr)s3vMmioMem)->dma_regs.regs.cmd.write_pointer) != (((mmtr)s3vMmioMem)->dma_regs.regs.cmd.read_pointer)); } while(0) --- 381,392 ---- #define WaitIdle() do { mem_barrier(); while (!(IN_SUBSYS_STAT() & 0x2000)); } while (0) /* Wait until Command FIFO is empty */ ! #define WaitCommandEmpty() do { mem_barrier(); \ ! if (s3vPriv.chip == S3_ViRGE_GX2 || s3vPriv.chip == S3_ViRGE_MX) \ ! while (!(((((mmtr)s3vMmioMem)->subsys_regs.regs.adv_func_cntl)) & 0x400)); \ ! else \ ! while (!(((((mmtr)s3vMmioMem)->subsys_regs.regs.adv_func_cntl)) & 0x200)); \ ! } while (0) /* Wait until a DMA transfer is done */ #define WaitDMAEmpty() do { mem_barrier(); while ((((mmtr)s3vMmioMem)->dma_regs.regs.cmd.write_pointer) != (((mmtr)s3vMmioMem)->dma_regs.regs.cmd.read_pointer)); } while(0) *** ./xfree86/vga256/drivers/s3v/s3v_accel.c@@/PUBLIC-LATEST Sun Aug 10 13:06:18 1997 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/s3v/s3v_accel.c Fri Mar 6 16:54:33 1998 *************** *** 1,8 **** ! /* $TOG: s3v_accel.c /main/2 1997/08/10 13:04:53 kaleb $ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/s3v/s3v_accel.c,v 1.1.2.5 1997/06/29 08:43:38 dawes Exp $ */ /* * --- 1,8 ---- ! /* $TOG: s3v_accel.c /main/3 1998/03/06 16:56:10 kaleb $ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/s3v/s3v_accel.c,v 1.1.2.7 1998/02/09 14:27:39 robin Exp $ */ /* * *************** *** 50,55 **** --- 50,56 ---- #include "vga.h" #include "xf86xaa.h" #include "xf86_OSlib.h" + #include "xf86Priv.h" #include "regs3v.h" #include "s3v_driver.h" #include "s3v_rop.h" *************** *** 144,150 **** BACKGROUND_OPERATIONS | COP_FRAMEBUFFER_CONCURRENCY | NO_SYNC_AFTER_CPU_COLOR_EXPAND | - HARDWARE_PATTERN_MONO_TRANSPARENCY | HARDWARE_PATTERN_BIT_ORDER_MSBFIRST | HARDWARE_PATTERN_PROGRAMMED_BITS | HARDWARE_PATTERN_SCREEN_ORIGIN; --- 145,150 ---- *************** *** 325,331 **** --- 325,333 ---- S3VGEReset() { unsigned char tmp; + int r; + WaitIdleEmpty(); if(s3vPriv.chip == S3_ViRGE_VX){ outb(vgaCRIndex, 0x63); } *************** *** 333,344 **** outb(vgaCRIndex, 0x66); } tmp = inb(vgaCRReg); ! outb(vgaCRReg, tmp | 0x02); ! outb(vgaCRReg, tmp & ~0x02); usleep(10000); ! WaitIdleEmpty(); ! SETB_DEST_SRC_STR(s3vPriv.Bpl, s3vPriv.Bpl); SETB_SRC_BASE(0); SETB_DEST_BASE(0); --- 335,358 ---- outb(vgaCRIndex, 0x66); } tmp = inb(vgaCRReg); ! usleep(10000); ! for (r=1; r<10; r++) { /* try multiple times to avoid lockup of ViRGE/MX */ ! outb(vgaCRReg, tmp | 0x02); ! usleep(10000); ! outb(vgaCRReg, tmp & ~0x02); ! usleep(10000); ! WaitIdleEmpty(); ! SETB_DEST_SRC_STR(s3vPriv.Bpl, s3vPriv.Bpl); ! ! usleep(10000); ! if (((IN_SUBSYS_STAT() & 0x3f00) != 0x3000)) ! ErrorF("restarting S3 graphics engine reset %2d ...\n",r); ! else ! break; ! } ! SETB_SRC_BASE(0); SETB_DEST_BASE(0); *************** *** 356,363 **** s3vCached_PAT_FGCLR = -1; s3vCached_PAT_BGCLR = -1; s3vCached_CMD_SET = -1; ! ! ErrorF("ViRGE register cache hits: %d misses: %d\n",s3vCacheHit, s3vCacheMiss); s3vCacheHit = 0; s3vCacheMiss = 0; } --- 370,378 ---- s3vCached_PAT_FGCLR = -1; s3vCached_PAT_BGCLR = -1; s3vCached_CMD_SET = -1; ! if (xf86Verbose > 1) ! ErrorF("ViRGE register cache hits: %d misses: %d\n", ! s3vCacheHit, s3vCacheMiss); s3vCacheHit = 0; s3vCacheMiss = 0; } *** ./xfree86/vga256/drivers/s3v/s3v_cursor.c@@/PUBLIC-LATEST Sat Jul 19 10:57:15 1997 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/s3v/s3v_cursor.c Fri Mar 6 16:54:38 1998 *************** *** 1,8 **** ! /* $TOG: s3v_cursor.c /main/1 1997/07/19 10:57:17 kaleb $ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/s3v/s3v_cursor.c,v 1.1.2.2 1997/05/31 13:34:45 dawes Exp $ */ /* * --- 1,8 ---- ! /* $TOG: s3v_cursor.c /main/2 1998/03/06 16:56:15 kaleb $ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/s3v/s3v_cursor.c,v 1.1.2.3 1998/02/07 10:05:46 hohndel Exp $ */ /* * *************** *** 336,343 **** x -= s3vHotX; y -= s3vHotY; ! if (vgaBitsPerPixel > 16) ! x &= ~1; /* * Make these even when used. There is a bug/feature on at least --- 336,348 ---- x -= s3vHotX; y -= s3vHotY; ! /* adjust for frame buffer base address granularity */ ! if (vgaBitsPerPixel == 8) ! x += ((vga256InfoRec.frameX0) & 3); ! else if (vgaBitsPerPixel == 16) ! x += ((vga256InfoRec.frameX0) & 1); ! else if (vgaBitsPerPixel == 24) ! x += ((vga256InfoRec.frameX0+2) & 3) - 2; /* * Make these even when used. There is a bug/feature on at least *************** *** 360,366 **** } /* WaitIdle(); */ - /* This is the recomended order to move the cursor */ outb(vgaCRIndex, 0x46); outb(vgaCRReg, (x & 0xff00)>>8); --- 365,370 ---- *************** *** 400,405 **** --- 404,410 ---- switch (vgaBitsPerPixel) { case 8: + if (!(s3vPriv.chip == S3_ViRGE_GX2 || s3vPriv.chip == S3_ViRGE_MX)) { vgaGetInstalledColormaps(pScr, &pmap); sourceColor.red = pCurs->foreRed; sourceColor.green = pCurs->foreGreen; *************** *** 423,429 **** --- 428,436 ---- outb(vgaCRReg, maskColor.pixel); outb(vgaCRReg, maskColor.pixel); break; + } /* else fall through for ViRGE/MX... */ case 16: + if (!(s3vPriv.chip == S3_ViRGE_GX2 || s3vPriv.chip == S3_ViRGE_MX)) { if (vga256InfoRec.weight.green == 5 && s3vPriv.chip != S3_ViRGE_VX) { packedcolfg = ((pCurs->foreRed & 0xf800) >> 1) | ((pCurs->foreGreen & 0xf800) >> 6) *************** *** 450,455 **** --- 457,463 ---- outb(vgaCRReg, packedcolbg); outb(vgaCRReg, packedcolbg>>8); break; + } /* else fall through for ViRGE/MX... */ case 24: case 32: outb(vgaCRIndex, 0x45); *** ./xfree86/vga256/drivers/s3v/s3v_driver.c@@/PUBLIC-LATEST Sun Aug 10 13:06:23 1997 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/s3v/s3v_driver.c Fri Mar 6 16:54:42 1998 *************** *** 1,8 **** ! /* $TOG: s3v_driver.c /main/2 1997/08/10 13:04:58 kaleb $ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/s3v/s3v_driver.c,v 1.1.2.13 1997/07/26 06:30:55 dawes Exp $ */ /* * --- 1,8 ---- ! /* $TOG: s3v_driver.c /main/3 1998/03/06 16:56:19 kaleb $ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/s3v/s3v_driver.c,v 1.1.2.17 1998/02/22 12:49:14 hohndel Exp $ */ /* * *************** *** 155,161 **** { S3_UNKNOWN, "unknown"}, { S3_ViRGE, "ViRGE"}, { S3_ViRGE_VX, "ViRGE/VX"}, ! { S3_ViRGE_DXGX, "ViRGE/DXGX"}, { -1, ""}, }; --- 155,163 ---- { S3_UNKNOWN, "unknown"}, { S3_ViRGE, "ViRGE"}, { S3_ViRGE_VX, "ViRGE/VX"}, ! { S3_ViRGE_DXGX,"ViRGE/DXGX"}, ! { S3_ViRGE_GX2, "ViRGE/GX2"}, ! { S3_ViRGE_MX, "ViRGE/MX"}, { -1, ""}, }; *************** *** 221,228 **** outb(vgaCRIndex, 0x39); outb(vgaCRReg, 0xa5); outb(vgaCRIndex, 0x40); ! tmp = inb(vgaCRIndex); ! outb(vgaCRReg, tmp | 0x01); /* Unlocks extended functions */ enterCalled = TRUE; } --- 223,230 ---- outb(vgaCRIndex, 0x39); outb(vgaCRReg, 0xa5); outb(vgaCRIndex, 0x40); ! tmp = inb(vgaCRReg); ! outb(vgaCRReg, tmp & ~0x01); /* avoid lockups when reading I/O port 0x92e8 */ enterCalled = TRUE; } *************** *** 324,329 **** --- 326,343 ---- outb(0x3c5, restore->SR12); outb(0x3c4, 0x13); outb(0x3c5, restore->SR13); + if (s3vPriv.chip == S3_ViRGE_GX2 || s3vPriv.chip == S3_ViRGE_MX) { + outb(0x3c4, 0x29); + outb(0x3c5, restore->SR29); + outb(0x3c4, 0x54); + outb(0x3c5, restore->SR54); + outb(0x3c4, 0x55); + outb(0x3c5, restore->SR55); + outb(0x3c4, 0x56); + outb(0x3c5, restore->SR56); + outb(0x3c4, 0x57); + outb(0x3c5, restore->SR57); + } outb(0x3c4, 0x15); outb(0x3c5, restore->SR15); *************** *** 361,368 **** --- 375,386 ---- /* Other mode timing and extended regs */ outb(vgaCRIndex, 0x34); outb(vgaCRReg, restore->CR34); + outb(vgaCRIndex, 0x40); + outb(vgaCRReg, restore->CR40); outb(vgaCRIndex, 0x42); outb(vgaCRReg, restore->CR42); + outb(vgaCRIndex, 0x45); + outb(vgaCRReg, restore->CR45); outb(vgaCRIndex, 0x51); outb(vgaCRReg, restore->CR51); outb(vgaCRIndex, 0x54); *************** *** 381,386 **** --- 399,406 ---- if (s3vPriv.chip == S3_ViRGE_DXGX) { outb(vgaCRIndex, 0x86); outb(vgaCRReg, restore->CR86); + } + if (s3vPriv.chip == S3_ViRGE_DXGX || s3vPriv.chip == S3_ViRGE_GX2 || s3vPriv.chip == S3_ViRGE_MX) { outb(vgaCRIndex, 0x90); outb(vgaCRReg, restore->CR90); } *************** *** 406,411 **** --- 426,443 ---- outb(0x3c5, restore->SR12); outb(0x3c4, 0x13); outb(0x3c5, restore->SR13); + if (s3vPriv.chip == S3_ViRGE_GX2 || s3vPriv.chip == S3_ViRGE_MX) { + outb(0x3c4, 0x29); + outb(0x3c5, restore->SR29); + outb(0x3c4, 0x54); + outb(0x3c5, restore->SR54); + outb(0x3c4, 0x55); + outb(0x3c5, restore->SR55); + outb(0x3c4, 0x56); + outb(0x3c5, restore->SR56); + outb(0x3c4, 0x57); + outb(0x3c5, restore->SR57); + } outb(0x3c4, 0x18); outb(0x3c5, restore->SR18); *************** *** 546,553 **** save->CR36 = inb(vgaCRReg); outb(vgaCRIndex, 0x3a); save->CR3A = inb(vgaCRReg); ! outb(vgaCRIndex, 0x42); save->CR42 = inb(vgaCRReg); outb(vgaCRIndex, 0x51); save->CR51 = inb(vgaCRReg); outb(vgaCRIndex, 0x53); --- 578,589 ---- save->CR36 = inb(vgaCRReg); outb(vgaCRIndex, 0x3a); save->CR3A = inb(vgaCRReg); ! outb(vgaCRIndex, 0x40); ! save->CR40 = inb(vgaCRReg); ! outb(vgaCRIndex, 0x42); save->CR42 = inb(vgaCRReg); + outb(vgaCRIndex, 0x45); + save->CR45 = inb(vgaCRReg); outb(vgaCRIndex, 0x51); save->CR51 = inb(vgaCRReg); outb(vgaCRIndex, 0x53); *************** *** 572,577 **** --- 608,615 ---- if (s3vPriv.chip == S3_ViRGE_DXGX) { outb(vgaCRIndex, 0x86); save->CR86 = inb(vgaCRReg); + } + if (s3vPriv.chip == S3_ViRGE_DXGX || s3vPriv.chip == S3_ViRGE_GX2 || s3vPriv.chip == S3_ViRGE_MX) { outb(vgaCRIndex, 0x90); save->CR90 = inb(vgaCRReg); } *************** *** 605,610 **** --- 643,660 ---- save->SR12 = inb(0x3c5); outb(0x3c4, 0x13); save->SR13 = inb(0x3c5); + if (s3vPriv.chip == S3_ViRGE_GX2 || s3vPriv.chip == S3_ViRGE_MX) { + outb(0x3c4, 0x29); + save->SR29 = inb(0x3c5); + outb(0x3c4, 0x54); + save->SR54 = inb(0x3c5); + outb(0x3c4, 0x55); + save->SR55 = inb(0x3c5); + outb(0x3c4, 0x56); + save->SR56 = inb(0x3c5); + outb(0x3c4, 0x57); + save->SR57 = inb(0x3c5); + } outb(0x3c4, 0x15); save->SR15 = inb(0x3c5); *************** *** 723,734 **** if (!pciInfo) return FALSE; ! if (pciInfo && pciInfo->MemBase) vga256InfoRec.MemBase = pciInfo->MemBase; if (pciInfo) if(pciInfo->ChipType != S3_ViRGE && pciInfo->ChipType != S3_ViRGE_VX && ! pciInfo->ChipType != S3_ViRGE_DXGX){ if (xf86Verbose > 1) ErrorF("%s %s: Unsupported (non-ViRGE) S3 chipset detected!\n", XCONFIG_PROBED, vga256InfoRec.name); --- 773,786 ---- if (!pciInfo) return FALSE; ! if (pciInfo && pciInfo->MemBase && !vga256InfoRec.MemBase) vga256InfoRec.MemBase = pciInfo->MemBase; if (pciInfo) if(pciInfo->ChipType != S3_ViRGE && pciInfo->ChipType != S3_ViRGE_VX && ! pciInfo->ChipType != S3_ViRGE_DXGX && ! pciInfo->ChipType != S3_ViRGE_GX2 && ! pciInfo->ChipType != S3_ViRGE_MX){ if (xf86Verbose > 1) ErrorF("%s %s: Unsupported (non-ViRGE) S3 chipset detected!\n", XCONFIG_PROBED, vga256InfoRec.name); *************** *** 741,747 **** ErrorF("%s %s: using driver for chipset \"%s\"\n",XCONFIG_PROBED, vga256InfoRec.name, S3VIdent(0)); } ! vga256InfoRec.chipset = S3VIdent(0); #ifdef __alpha__ --- 793,799 ---- ErrorF("%s %s: using driver for chipset \"%s\"\n",XCONFIG_PROBED, vga256InfoRec.name, S3VIdent(0)); } ! vga256InfoRec.chipset = S3VIdent(0); #ifdef __alpha__ *************** *** 798,803 **** --- 850,865 ---- } vga256InfoRec.videoRam -= s3vPriv.MemOffScreen; } + else if (s3vPriv.chip == S3_ViRGE_GX2 || s3vPriv.chip == S3_ViRGE_MX) { + switch((config1 & 0xC0) >> 6) { + case 1: + vga256InfoRec.videoRam = 4 * 1024; + break; + case 3: + vga256InfoRec.videoRam = 2 * 1024; + break; + } + } else { switch((config1 & 0xE0) >> 5) { case 0: *************** *** 866,877 **** if (vga256InfoRec.dacSpeeds[2] <= 0) vga256InfoRec.dacSpeeds[2] = 135000; if (vga256InfoRec.dacSpeeds[3] <= 0) vga256InfoRec.dacSpeeds[3] = 135000; } ! else if (s3vPriv.chip == S3_ViRGE_DXGX) { if (vga256InfoRec.dacSpeeds[0] <= 0) vga256InfoRec.dacSpeeds[0] = 170000; if (vga256InfoRec.dacSpeeds[1] <= 0) vga256InfoRec.dacSpeeds[1] = 170000; if (vga256InfoRec.dacSpeeds[2] <= 0) vga256InfoRec.dacSpeeds[2] = 135000; if (vga256InfoRec.dacSpeeds[3] <= 0) vga256InfoRec.dacSpeeds[3] = 135000; } else { if (vga256InfoRec.dacSpeeds[0] <= 0) vga256InfoRec.dacSpeeds[0] = 135000; if (vga256InfoRec.dacSpeeds[1] <= 0) vga256InfoRec.dacSpeeds[1] = 95000; --- 928,945 ---- if (vga256InfoRec.dacSpeeds[2] <= 0) vga256InfoRec.dacSpeeds[2] = 135000; if (vga256InfoRec.dacSpeeds[3] <= 0) vga256InfoRec.dacSpeeds[3] = 135000; } ! else if (s3vPriv.chip == S3_ViRGE_DXGX || s3vPriv.chip == S3_ViRGE_GX2) { if (vga256InfoRec.dacSpeeds[0] <= 0) vga256InfoRec.dacSpeeds[0] = 170000; if (vga256InfoRec.dacSpeeds[1] <= 0) vga256InfoRec.dacSpeeds[1] = 170000; if (vga256InfoRec.dacSpeeds[2] <= 0) vga256InfoRec.dacSpeeds[2] = 135000; if (vga256InfoRec.dacSpeeds[3] <= 0) vga256InfoRec.dacSpeeds[3] = 135000; } + else if (s3vPriv.chip == S3_ViRGE_MX) { + if (vga256InfoRec.dacSpeeds[0] <= 0) vga256InfoRec.dacSpeeds[0] = 135000; + if (vga256InfoRec.dacSpeeds[1] <= 0) vga256InfoRec.dacSpeeds[1] = 135000; + if (vga256InfoRec.dacSpeeds[2] <= 0) vga256InfoRec.dacSpeeds[2] = 100000; + if (vga256InfoRec.dacSpeeds[3] <= 0) vga256InfoRec.dacSpeeds[3] = 100000; + } else { if (vga256InfoRec.dacSpeeds[0] <= 0) vga256InfoRec.dacSpeeds[0] = 135000; if (vga256InfoRec.dacSpeeds[1] <= 0) vga256InfoRec.dacSpeeds[1] = 95000; *************** *** 935,943 **** } else s3vPriv.MCLK = 0; /* Set scale factors for mode timings */ ! if (s3vPriv.chip == S3_ViRGE_VX){ s3vPriv.HorizScaleFactor = 1; } else if (vgaBitsPerPixel == 8){ --- 1003,1045 ---- } else s3vPriv.MCLK = 0; + + if (s3vPriv.chip == S3_ViRGE_MX && xf86Verbose) { + int lcdclk, h_lcd, v_lcd; + if (OFLG_ISSET(XCONFIG_LCDCLOCK, &vga256InfoRec.xconfigFlag)) { + lcdclk = vga256InfoRec.LCDClk; + } else { + int n1, n2, sr12, sr13, sr29; + outb(0x3c4, 0x12); + sr12 = inb(0x3c5); + outb(0x3c4, 0x13); + sr13 = inb(0x3c5) & 0x7f; + outb(0x3c4, 0x29); + sr29 = inb(0x3c5); + n1 = sr12 & 0x1f; + n2 = ((sr12>>6) & 0x03) | ((sr29 & 0x01) << 2); + lcdclk = ((2 * 1431818 * (sr13+2)) / (n1+2) / (1 << n2) + 50) / 100; + } + outb(0x3c4, 0x61); + h_lcd = inb(0x3c5); + outb(0x3c4, 0x66); + h_lcd |= ((inb(0x3c5) & 0x02) << 7); + h_lcd = (h_lcd+1) * 8; + outb(0x3c4, 0x69); + v_lcd = inb(0x3c5); + outb(0x3c4, 0x6e); + v_lcd |= ((inb(0x3c5) & 0x70) << 4); + v_lcd++; + ErrorF("%s %s: LCD size %dx%d, clock %1.3f MHz\n" + , OFLG_ISSET(XCONFIG_LCDCLOCK, &vga256InfoRec.xconfigFlag) ? XCONFIG_GIVEN : XCONFIG_PROBED + , vga256InfoRec.name + , h_lcd, v_lcd + , lcdclk / 1000.0); + } + /* Set scale factors for mode timings */ ! if (s3vPriv.chip == S3_ViRGE_VX || s3vPriv.chip == S3_ViRGE_MX){ s3vPriv.HorizScaleFactor = 1; } else if (vgaBitsPerPixel == 8){ *************** *** 1028,1036 **** --- 1130,1141 ---- OFLG_SET(OPTION_FIFO_AGGRESSIVE, &S3V.ChipOptionFlags); OFLG_SET(OPTION_PCI_RETRY, &S3V.ChipOptionFlags); OFLG_SET(OPTION_NOACCEL, &S3V.ChipOptionFlags); + OFLG_SET(OPTION_SW_CURSOR, &S3V.ChipOptionFlags); OFLG_SET(OPTION_HW_CURSOR, &S3V.ChipOptionFlags); OFLG_SET(OPTION_EARLY_RAS_PRECHARGE, &S3V.ChipOptionFlags); OFLG_SET(OPTION_LATE_RAS_PRECHARGE, &S3V.ChipOptionFlags); + if (s3vPriv.chip == S3_ViRGE_MX) + OFLG_SET(OPTION_LCD_CENTER, &S3V.ChipOptionFlags); s3vPriv.NoPCIRetry = 1; S3V.ChipLinearBase = vga256InfoRec.MemBase; *************** *** 1075,1080 **** --- 1180,1197 ---- vgaBitsPerPixel); return MODE_BAD; } + + /* For ViRGE and DX, others ? This limit is imposed by */ + /* the 12 bit Stream stride register. */ + if((vgaBitsPerPixel == 32) && (mode->HDisplay > 1023) && + ((s3vPriv.chip == S3_ViRGE) || (s3vPriv.chip == S3_ViRGE_DXGX)) + ) { + if(verbose) + ErrorF("%s %s: %s: Mode '%s' discarded. Width (%d) > 1023 at 32 bpp.\n", + XCONFIG_PROBED, vga256InfoRec.name, vga256InfoRec.chipset, + mode->name, mode->HDisplay); + return MODE_BAD; + } /* Now make sure we have enough vidram to support mode */ mem = ((vga256InfoRec.displayWidth > mode->HDisplay) ? *************** *** 1106,1114 **** int Base, hwidth; unsigned char tmp; ! if(s3vPriv.STREAMSRunning == FALSE) { Base = ((y * vga256InfoRec.displayWidth + x) * (vgaBitsPerPixel / 8)) >> 2; /* Now program the start address registers */ outw(vgaCRIndex, (Base & 0x00FF00) | 0x0C); --- 1223,1234 ---- int Base, hwidth; unsigned char tmp; ! if(s3vPriv.STREAMSRunning == FALSE || ! s3vPriv.chip == S3_ViRGE_GX2 || s3vPriv.chip == S3_ViRGE_MX) { Base = ((y * vga256InfoRec.displayWidth + x) * (vgaBitsPerPixel / 8)) >> 2; + if (vgaBitsPerPixel == 24) + Base = Base+2 - (Base+2) % 3; /* Now program the start address registers */ outw(vgaCRIndex, (Base & 0x00FF00) | 0x0C); *************** *** 1126,1131 **** --- 1246,1254 ---- ((y * vga256InfoRec.displayWidth + (x & ~3)) * vgaBitsPerPixel / 8); } + if (!OFLG_ISSET(OPTION_SW_CURSOR, &vga256InfoRec.options)) + S3VRepositionCursor(NULL); + #ifdef XFreeXDGA if (vga256InfoRec.directMode & XF86DGADirectGraphics) { /* Wait until vertical retrace is in progress. */ *************** *** 1213,1220 **** --- 1336,1347 ---- new->SR15 = 0x03 | 0x80; new->SR18 = 0x00; new->CR43 = 0x00; + new->CR45 = 0x00; new->CR65 = 0x00; new->CR54 = 0x00; + + outb(vgaCRIndex, 0x40); + new->CR40 = inb(vgaCRReg) & ~0x01; /* Memory controller registers. Optimize for better graphics engine * performance. These settings are adjusted/overridden below for other bpp/ *************** *** 1273,1278 **** --- 1400,1476 ---- 220000, 440000, &new->SR13, &new->SR12); } + else if (s3vPriv.chip == S3_ViRGE_GX2 || s3vPriv.chip == S3_ViRGE_MX) { + if (vgaBitsPerPixel == 8) { + if (dclk <= 85000) new->CR67 = 0x00; /* 8bpp, 85MHz */ + else new->CR67 = 0x10; /* 8bpp, 170MHz */ + } + else if (vgaBitsPerPixel == 16) { + if (vga256InfoRec.weight.green == 5) + new->CR67 = 0x30; /* 15bpp */ + else + new->CR67 = 0x50; /* 16bpp */ + } + else if ((vgaBitsPerPixel == 24) /* || (vgaBitsPerPixel == 32) */ ) { + new->CR67 = 0x74; /* 24bpp, STREAMS */ + S3VInitSTREAMS(new->STREAMS, mode); + new->MMPR0 = 0xc098; /* Adjust FIFO slots */ + } + else if (vgaBitsPerPixel == 32) { + new->CR67 = 0xd0; /* 32bpp */ + /* new->MMPR0 = 0xc098; /* Adjust FIFO slots */ + } + { + unsigned char ndiv; + if (s3vPriv.chip == S3_ViRGE_MX) { + int lcd_freq; + outb(0x3c4, 0x08); /* unlock extended SEQ regs */ + outb(0x3c5, 0x06); + outb(0x3c4, 0x31); + if (inb(0x3c5) & 0x10) { /* LCD on */ + if (!vga256InfoRec.LCDClk) { /* entered only once for first mode */ + int h_lcd, v_lcd; + outb(0x3c4, 0x61); + h_lcd = inb(0x3c5); + outb(0x3c4, 0x66); + h_lcd |= ((inb(0x3c5) & 0x02) << 7); + h_lcd = (h_lcd+1) * 8; + outb(0x3c4, 0x69); + v_lcd = inb(0x3c5); + outb(0x3c4, 0x6e); + v_lcd |= ((inb(0x3c5) & 0x70) << 4); + v_lcd++; + + /* check if first mode has physical LCD resolution */ + if (vga256InfoRec.modes->HDisplay == h_lcd && vga256InfoRec.modes->VDisplay == v_lcd) + vga256InfoRec.LCDClk = vga256InfoRec.clock[vga256InfoRec.modes->Clock]; + else { + int n1, n2, sr12, sr13, sr29; + outb(0x3c4, 0x12); + sr12 = inb(0x3c5); + outb(0x3c4, 0x13); + sr13 = inb(0x3c5) & 0x7f; + outb(0x3c4, 0x29); + sr29 = inb(0x3c5); + n1 = sr12 & 0x1f; + n2 = ((sr12>>6) & 0x03) | ((sr29 & 0x01) << 2); + vga256InfoRec.LCDClk = ((2 * 1431818 * (sr13+2)) / (n1+2) / (1 << n2) + 50) / 100; + } + } + commonCalcClock(vga256InfoRec.LCDClk/2, 1, 1, 31, 0, 4, + 170000, 340000, &new->SR13, &ndiv); + } + else + commonCalcClock(dclk/2, 1, 1, 31, 0, 4, + 170000, 340000, &new->SR13, &ndiv); + } + else /* S3_ViRGE_GX2 */ + commonCalcClock(dclk, 1, 1, 31, 0, 4, + 170000, 340000, &new->SR13, &ndiv); + new->SR29 = ndiv >> 7; + new->SR12 = (ndiv & 0x1f) | ((ndiv & 0x60) << 1); + } + } else { /* Is this correct for DX/GX as well? */ if (vgaBitsPerPixel == 8) { if(dclk > 80000) { /* We need pixmux */ *************** *** 1373,1378 **** --- 1571,1578 ---- new->CR33 = 0x20; if (s3vPriv.chip == S3_ViRGE_DXGX) { new->CR86 = 0x80; /* disable DAC power saving to avoid bright left edge */ + } + if (s3vPriv.chip == S3_ViRGE_DXGX || s3vPriv.chip == S3_ViRGE_GX2) { new->CR90 = 0x00; /* disable the stream display fetch length control */ } *************** *** 1379,1388 **** /* Now we handle various XConfig memory options and others */ /* option "slow_edodram" sets EDO to 2 cycle mode on ViRGE */ if (s3vPriv.chip == S3_ViRGE) { - outb(vgaCRIndex, 0x36); - new->CR36 = inb(vgaCRReg); if(OFLG_ISSET(OPTION_SLOW_EDODRAM, &vga256InfoRec.options)) new->CR36 = (new->CR36 & 0xf3) | 0x08; else --- 1579,1588 ---- /* Now we handle various XConfig memory options and others */ + outb(vgaCRIndex, 0x36); + new->CR36 = inb(vgaCRReg); /* option "slow_edodram" sets EDO to 2 cycle mode on ViRGE */ if (s3vPriv.chip == S3_ViRGE) { if(OFLG_ISSET(OPTION_SLOW_EDODRAM, &vga256InfoRec.options)) new->CR36 = (new->CR36 & 0xf3) | 0x08; else *************** *** 1391,1398 **** /* Option "fpm_vram" for ViRGE_VX sets memory in fast page mode */ if (s3vPriv.chip == S3_ViRGE_VX) { - outb(vgaCRIndex, 0x36); - new->CR36 = inb(vgaCRReg); if(OFLG_ISSET(OPTION_FPM_VRAM, &vga256InfoRec.options)) new->CR36 |= 0x0c; else --- 1591,1596 ---- *************** *** 1432,1439 **** new->CR68 = inb(vgaCRReg); new->CR69 = 0; ! return TRUE; } /* This function inits the frame buffer. Right now, it is is rather limited --- 1630,1650 ---- new->CR68 = inb(vgaCRReg); new->CR69 = 0; + if (s3vPriv.chip == S3_ViRGE_MX && + OFLG_ISSET(OPTION_LCD_CENTER, &vga256InfoRec.options)) { + new->SR54 = 0x10 ; + new->SR55 = 0x80 ; + new->SR56 = 0x10 ; + new->SR57 = 0x80 ; + } else { + new->SR54 = 0x1f ; + new->SR55 = 0x9f ; + new->SR56 = 0x1f ; + new->SR57 = 0xff ; + } ! ! return TRUE; } /* This function inits the frame buffer. Right now, it is is rather limited *************** *** 1460,1466 **** ErrorF("%s %s: \"pci_retry\" option requires \"pci_burst\".\n", XCONFIG_GIVEN, vga256InfoRec.name); } ! if (OFLG_ISSET(OPTION_HW_CURSOR, &vga256InfoRec.options)) { vgaHWCursor.Initialized = TRUE; vgaHWCursor.Init = S3VCursorInit; vgaHWCursor.Restore = S3VRestoreCursor; --- 1671,1677 ---- ErrorF("%s %s: \"pci_retry\" option requires \"pci_burst\".\n", XCONFIG_GIVEN, vga256InfoRec.name); } ! if (!OFLG_ISSET(OPTION_SW_CURSOR, &vga256InfoRec.options)) { vgaHWCursor.Initialized = TRUE; vgaHWCursor.Init = S3VCursorInit; vgaHWCursor.Restore = S3VRestoreCursor; *** ./xfree86/vga256/drivers/s3v/s3v_driver.h@@/PUBLIC-LATEST Sun Aug 10 13:06:28 1997 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/s3v/s3v_driver.h Fri Mar 6 16:54:48 1998 *************** *** 1,8 **** ! /* $TOG: s3v_driver.h /main/2 1997/08/10 13:05:04 kaleb $ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/s3v/s3v_driver.h,v 1.1.2.3 1997/06/11 12:08:56 dawes Exp $ */ /* Header file for ViRGE server */ --- 1,8 ---- ! /* $TOG: s3v_driver.h /main/3 1998/03/06 16:56:25 kaleb $ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/s3v/s3v_driver.h,v 1.1.2.5 1998/02/07 10:05:47 hohndel Exp $ */ /* Header file for ViRGE server */ *************** *** 15,25 **** /* Driver data structure; this should contain all neeeded info for a mode */ typedef struct { vgaHWRec std; ! unsigned char SR10, SR11, SR12, SR13, SR15, SR18; /* SR9-SR1C, ext seq. */ unsigned char Clock; unsigned char s3DacRegs[0x101]; unsigned char CR31, CR33, CR34, CR36, CR3A, CR3B, CR3C; ! unsigned char CR42, CR43; unsigned char CR51, CR53, CR54, CR58, CR5D, CR5E; unsigned char CR63, CR65, CR66, CR67, CR68, CR69, CR6D; /* Video attrib. */ unsigned char CR86; --- 15,26 ---- /* Driver data structure; this should contain all neeeded info for a mode */ typedef struct { vgaHWRec std; ! unsigned char SR10, SR11, SR12, SR13, SR15, SR18, SR29; /* SR9-SR1C, ext seq. */ ! unsigned char SR54, SR55, SR56, SR57; unsigned char Clock; unsigned char s3DacRegs[0x101]; unsigned char CR31, CR33, CR34, CR36, CR3A, CR3B, CR3C; ! unsigned char CR40, CR42, CR43, CR45; unsigned char CR51, CR53, CR54, CR58, CR5D, CR5E; unsigned char CR63, CR65, CR66, CR67, CR68, CR69, CR6D; /* Video attrib. */ unsigned char CR86; *** ./xfree86/vga256/drivers/s3v/s3v_misc.c@@/PUBLIC-LATEST Sat Jul 19 10:57:28 1997 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/s3v/s3v_misc.c Fri Mar 6 16:54:52 1998 *************** *** 1,8 **** ! /* $TOG: s3v_misc.c /main/1 1997/07/19 10:57:29 kaleb $ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/s3v/s3v_misc.c,v 1.1.2.3 1997/05/28 13:12:53 dawes Exp $ */ /* * --- 1,8 ---- ! /* $TOG: s3v_misc.c /main/2 1998/03/06 16:56:29 kaleb $ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/s3v/s3v_misc.c,v 1.1.2.6 1998/02/09 14:27:40 robin Exp $ */ /* * *************** *** 16,21 **** --- 16,24 ---- * * Created 18/03/97 by Sebastien Marineau * Revision: + * [0.2] 08/02/98: Rewrite to use the VGA PCI information instead of re-probing + * the PCI bus. + * * [0.1] 18/03/97: Added PCI probe function, taken from accel/s3_virge server. * Not sure if the code used to adjust the PCI base address is * still needed for the ViRGE chipsets. *************** *** 49,54 **** --- 52,58 ---- #include "regs3v.h" #include "s3v_driver.h" + extern vgaPCIInformation *vgaPCIInfo; extern SymTabRec s3vChipTable[]; extern S3VPRIV s3vPriv; *************** *** 61,99 **** s3vGetPCIInfo() { static S3PCIInformation info = {0, }; ! pciConfigPtr pcrp, *pcrpp; Bool found = FALSE; int i = 0; - pcrpp = xf86scanpci(vga256InfoRec.scrnIndex); ! if (!pcrpp) ! return NULL; ! while ((pcrp = pcrpp[i])) { ! if (pcrp->_vendor == PCI_S3_VENDOR_ID) { ! found = TRUE; ! switch (pcrp->_device) { ! case PCI_ViRGE: ! info.ChipType = S3_ViRGE; break; ! case PCI_ViRGE_VX: ! info.ChipType = S3_ViRGE_VX; ! break; ! case PCI_ViRGE_DXGX: ! info.ChipType = S3_ViRGE_DXGX; ! break; ! default: ! info.ChipType = S3_UNKNOWN; ! info.DevID = pcrp->_device; ! break; ! } ! info.ChipRev = pcrp->_rev_id; ! info.MemBase = pcrp->_base0 & 0xFF800000; ! break; ! } i++; } /* for new mmio we have to ensure that the PCI base address is * 64MB aligned and that there are no address collitions within 64MB. --- 65,116 ---- s3vGetPCIInfo() { static S3PCIInformation info = {0, }; ! pciConfigPtr pcrp = NULL; Bool found = FALSE; int i = 0; ! if (vgaPCIInfo && vgaPCIInfo->AllCards) { ! while (pcrp = vgaPCIInfo->AllCards[i]) { ! if (pcrp->_vendor == PCI_S3_VENDOR_ID) { ! int ChipId = pcrp->_device; ! if (vga256InfoRec.chipID) { ! ErrorF("%s %s: S3 chipset override, using chip_id = 0x%04x instead of 0x%04x\n", ! XCONFIG_GIVEN, vga256InfoRec.name, vga256InfoRec.chipID, ChipId); ! ChipId = vga256InfoRec.chipID; ! } ! found = TRUE; ! switch (ChipId) { ! case PCI_ViRGE: ! info.ChipType = S3_ViRGE; ! break; ! case PCI_ViRGE_VX: ! info.ChipType = S3_ViRGE_VX; ! break; ! case PCI_ViRGE_DXGX: ! info.ChipType = S3_ViRGE_DXGX; ! break; ! case PCI_ViRGE_GX2: ! info.ChipType = S3_ViRGE_GX2; ! break; ! case PCI_ViRGE_MX: ! info.ChipType = S3_ViRGE_MX; ! break; ! default: ! info.ChipType = S3_UNKNOWN; ! info.DevID = pcrp->_device; ! break; ! } ! info.ChipRev = pcrp->_rev_id; ! info.MemBase = pcrp->_base0 & 0xFF800000; break; ! } i++; + } } + else + return (FALSE); /* for new mmio we have to ensure that the PCI base address is * 64MB aligned and that there are no address collitions within 64MB. *************** *** 118,124 **** /* map allocated 64MB blocks */ for (j=0; j<64; j++) map_64m[j] = 0; map_64m[63] = 1; /* don't use the last 64MB area */ ! for (j=0; (pcrp = pcrpp[j]); j++) { if (i != j) { map_64m[ (pcrp->_base0 >> 26) & 0x3f] = 1; map_64m[((pcrp->_base0+0x3ffffff) >> 26) & 0x3f] = 1; --- 135,141 ---- /* map allocated 64MB blocks */ for (j=0; j<64; j++) map_64m[j] = 0; map_64m[63] = 1; /* don't use the last 64MB area */ ! for (j=0; (pcrp = vgaPCIInfo->AllCards[j]); j++) { if (i != j) { map_64m[ (pcrp->_base0 >> 26) & 0x3f] = 1; map_64m[((pcrp->_base0+0x3ffffff) >> 26) & 0x3f] = 1; *************** *** 145,167 **** probed, vga256InfoRec.name); ErrorF("\t\tbase address changed from 0x%08lx to 0x%08lx\n", base0, info.MemBase); ! xf86writepci(vga256InfoRec.scrnIndex, pcrpp[i]->_bus, pcrpp[i]->_cardnum, ! pcrpp[i]->_func, PCI_MAP_REG_START, ~0L, info.MemBase | PCI_MAP_MEMORY | PCI_MAP_MEMORY_TYPE_32BIT); } } else { ! if (vga256InfoRec.MemBase != 0) { ! /* Should we allow the user to specify this??? */ ! /* Guess this should be reenabled for VLB */ ! } ! else { ! ! } } - /* Free PCI information */ - xf86cleanpci(); if (found && xf86Verbose) { if (info.ChipType != S3_UNKNOWN) { ErrorF("%s %s: S3V: %s rev %x, Linear FB @ 0x%08lx\n", XCONFIG_PROBED, --- 162,178 ---- probed, vga256InfoRec.name); ErrorF("\t\tbase address changed from 0x%08lx to 0x%08lx\n", base0, info.MemBase); ! xf86writepci(vga256InfoRec.scrnIndex, vgaPCIInfo->AllCards[i]->_bus, ! vgaPCIInfo->AllCards[i]->_cardnum, ! vgaPCIInfo->AllCards[i]->_func, ! PCI_MAP_REG_START, ~0L, info.MemBase | PCI_MAP_MEMORY | PCI_MAP_MEMORY_TYPE_32BIT); } } else { ! /* Don't do this check for other chipsets. */ } if (found && xf86Verbose) { if (info.ChipType != S3_UNKNOWN) { ErrorF("%s %s: S3V: %s rev %x, Linear FB @ 0x%08lx\n", XCONFIG_PROBED, *** /dev/null Tue Jun 30 15:22:56 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/IBMRGBCurs.c Fri Mar 6 16:52:39 1998 *************** *** 0 **** --- 1,180 ---- + /* $TOG: IBMRGBCurs.c /main/1 1998/03/06 16:54:16 kaleb $ */ + + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/IBMRGBCurs.c,v 1.1.2.1 1998/02/09 13:57:42 robin Exp $ */ + /* + * + * Copyright 1995 The XFree86 Project, Inc. + * + */ + + #include <X.h> + #include "Xproto.h" + #include <misc.h> + #include <input.h> + #include <cursorstr.h> + #include <regionstr.h> + #include <scrnintstr.h> + #include <servermd.h> + #include <windowstr.h> + #include "xf86.h" + #include "inputstr.h" + #include "xf86Priv.h" + #include "xf86_OSlib.h" + #include "s3.h" + #include "s3reg.h" + #include "mipointer.h" + #define S3_SERVER + #include "IBMRGB.h" + + #ifndef __GNUC__ + # define __inline__ /**/ + #endif + + /* + * Convert the cursor from server-format to hardware-format. + * The IBM RGB52x has one array of two-bit-pixels. The MSB contains + * the transparency information (mask) and the LSB is the color bit. + * The pixel order within a byte can be selected and is MSB-to-LSB + * or "00112233". + */ + + void + s3IBMRGBShowCursor() + { + unsigned char tmp; + + UNLOCK_SYS_REGS; + + /* turn on external cursor */ + outb(vgaCRIndex, 0x55); + tmp = (inb(vgaCRReg) & 0xDF) | 0x20; + outb(vgaCRReg, tmp); + + /* Enable IBMRGB */ + outb(vgaCRIndex, 0x45); + tmp = inb(vgaCRReg) & ~0x20; + outb(vgaCRReg, tmp); + + /* Enable cursor - X11 mode */ + s3OutIBMRGBIndReg(IBMRGB_curs, 0, 0x27); + + LOCK_SYS_REGS; + } + + void + s3IBMRGBHideCursor() + { + UNLOCK_SYS_REGS; + + /* + * Don't need to undo the S3 registers here; they will be undone when + * the mode is restored from save registers. If it is done here, it + * causes the cursor to flash each time it is loaded, so don't do that. + */ + + /* Disable cursor */ + s3OutIBMRGBIndReg(IBMRGB_curs, ~3, 0x00); + + LOCK_SYS_REGS; + } + + void + s3IBMRGBSetCursorPosition(x, y, xorigin, yorigin) + int x, y, xorigin, yorigin; + { + unsigned char tmp; + + x -= xorigin; + y -= yorigin; + + if (vga256InfoRec.modes->Flags & V_DBLSCAN) + y <<= 1; + + if (vga256InfoRec.modes->Flags & V_INTERLACE) + y >>= 1; + + UNLOCK_SYS_REGS; + + outb(vgaCRIndex, 0x55); + tmp = inb(vgaCRReg) & 0xFC; + outb(vgaCRReg, tmp | 0x01); + outb(IBMRGB_INDEX_LOW,IBMRGB_curs_xl); outb(IBMRGB_INDEX_DATA, x); + outb(IBMRGB_INDEX_LOW,IBMRGB_curs_xh); outb(IBMRGB_INDEX_DATA, x>>8); + outb(IBMRGB_INDEX_LOW,IBMRGB_curs_yl); outb(IBMRGB_INDEX_DATA, y); + outb(IBMRGB_INDEX_LOW,IBMRGB_curs_yh); outb(IBMRGB_INDEX_DATA, y>>8); + outb(vgaCRReg, tmp); + + LOCK_SYS_REGS; + } + + void + s3IBMRGBSetCursorColors(bg, fg) + int bg, fg; + { + unsigned char tmp; + UNLOCK_SYS_REGS; + + /* The IBM RGB52x cursor is always 8 bits so shift 8, not 10 */ + + outb(vgaCRIndex, 0x55); + tmp = inb(vgaCRReg) & 0xFC; + outb(vgaCRReg, tmp | 0x01); + outb(IBMRGB_INDEX_LOW,IBMRGB_curs_col1_r); + outb(IBMRGB_INDEX_DATA, (bg & 0x00FF0000) >> 16); + outb(IBMRGB_INDEX_LOW,IBMRGB_curs_col1_g); + outb(IBMRGB_INDEX_DATA, (bg & 0x0000FF00) >> 8); + outb(IBMRGB_INDEX_LOW,IBMRGB_curs_col1_b); + outb(IBMRGB_INDEX_DATA, (bg & 0x000000FF)); + outb(IBMRGB_INDEX_LOW,IBMRGB_curs_col2_r); + outb(IBMRGB_INDEX_DATA, (fg & 0x00FF0000) >> 16); + outb(IBMRGB_INDEX_LOW,IBMRGB_curs_col2_g); + outb(IBMRGB_INDEX_DATA, (fg & 0x0000FF00) >> 8); + outb(IBMRGB_INDEX_LOW,IBMRGB_curs_col2_b); + outb(IBMRGB_INDEX_DATA, (fg & 0x000000FF)); + outb(vgaCRReg, tmp); + + LOCK_SYS_REGS; + } + + void + s3IBMRGBLoadCursorImage(bits, xorigin, yorigin) + unsigned char *bits; + int xorigin, yorigin; + { + unsigned char tmp, tmp2; + register int i; + + UNLOCK_SYS_REGS; + + outb(vgaCRIndex, 0x55); + tmp = inb(vgaCRReg) & 0xFC; + outb(vgaCRReg, tmp | 0x01); + outb(IBMRGB_INDEX_LOW,IBMRGB_curs_hot_x); outb(IBMRGB_INDEX_DATA, 0); + outb(IBMRGB_INDEX_LOW,IBMRGB_curs_hot_y); outb(IBMRGB_INDEX_DATA, 0); + outb(IBMRGB_INDEX_LOW,IBMRGB_curs_xl); outb(IBMRGB_INDEX_DATA, 0xff); + outb(IBMRGB_INDEX_LOW,IBMRGB_curs_xh); outb(IBMRGB_INDEX_DATA, 0x7f); + outb(IBMRGB_INDEX_LOW,IBMRGB_curs_yl); outb(IBMRGB_INDEX_DATA, 0xff); + outb(IBMRGB_INDEX_LOW,IBMRGB_curs_yh); outb(IBMRGB_INDEX_DATA, 0x7f); + + tmp2 = inb(IBMRGB_INDEX_CONTROL) & 0xfe; + outb(IBMRGB_INDEX_CONTROL, tmp2 | 1); /* enable auto-increment */ + + outb(IBMRGB_INDEX_HIGH, (unsigned char) (IBMRGB_curs_array >> 8)); + outb(IBMRGB_INDEX_LOW, (unsigned char) IBMRGB_curs_array); + + for (i = 0; i < 1024; i++) + outb(IBMRGB_INDEX_DATA, *bits++); + + outb(IBMRGB_INDEX_HIGH, 0); + outb(IBMRGB_INDEX_CONTROL, tmp2); /* disable auto-increment */ + outb(vgaCRIndex, 0x55); + outb(vgaCRReg, tmp); + + LOCK_SYS_REGS; + + } + + *** /dev/null Tue Jun 30 15:22:57 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/newmmio.h Fri Mar 6 16:52:55 1998 *************** *** 0 **** --- 1,265 ---- + /* $TOG: newmmio.h /main/1 1998/03/06 16:54:33 kaleb $ */ + + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/newmmio.h,v 1.1.2.1 1998/02/07 10:05:30 hohndel Exp $ */ + + /* + * + * Copyright 1995-1997 The XFree86 Project, Inc. + * + */ + + #ifndef _NEWMMIO_H_ + #define _NEWMMIO_H_ + + #include <Xmd.h> + + + #define int16 CARD16 + #define int32 CARD32 + + #define S3_NEWMMIO_VGABASE (S3_NEWMMIO_REGBASE + 0x8000) + + typedef struct { int16 vendor_ID; int16 device_ID; } pci_id; + typedef struct { int16 cmd; int16 devsel; } cmd_devsel; + + typedef struct { + pci_id pci_ident; + cmd_devsel cmd_device_sel; + int32 class_code; + int32 dummy5; + int32 base0; + char dummy1[0x20-sizeof(int32)]; + int32 bios_base; + char dummy2[0x3c - 0x32]; + } pci_conf_regs; + + + typedef struct { int16 filler; int16 adv_f_cntl; } adv_f_cntl; + + typedef struct { + int32 cur_point; + char dummy1[4]; + int32 dest_stp; + char dummy2[4]; + int32 err_term; + char dummy3[4]; + int32 command; + int32 short_stroke; + int32 bkgd_color; + int32 frgd_color; + int32 wrt_mask; + int32 rd_mask; + int32 color_cmp; + int32 col_mix; + int32 sciss_topleft; + int32 sciss_botright; + int32 pix_mult; + int32 mult_misc; + int32 axis_pcnt; + } packed_enhanced_regs; + + typedef struct { + int32 prim_stream_cntl; + int32 col_chroma_key_cntl; + char dummy1[0x8190 - 0x8184-sizeof(int32)]; + int32 second_stream_cntl; + int32 chroma_key_upper_bound; + int32 second_stream_stretch; + char dummy2[0x81a0 - 0x8198-sizeof(int32)]; + int32 blend_cntl; + char dummy3[0x81c0 - 0x81a0-sizeof(int32)]; + int32 prim_fbaddr0; + int32 prim_fbaddr1; + int32 prim_stream_stride; + int32 double_buffer; + int32 second_fbaddr0; + int32 second_fbaddr1; + int32 second_stream_stride; + int32 opaq_overlay_cntl; + int32 k1; + int32 k2; + int32 dda_vert; + int32 streams_fifo; + int32 prim_start_coord; + int32 prim_window_size; + int32 second_start_coord; + int32 second_window_size; + } streams_proc_regs; + + typedef struct { char atr_cntl_ind; char attr_cntl_dat; char misc_out; + char viseo_enable; } v3c0; + typedef struct { char seq_index; char seq_data; char dac_mask; + char dac_rd_index; } v3c4; + typedef struct { char dac_wr_index; char dac_data; char feature_cntl; + char filler; } v3c8; + typedef struct v3cc { char misc_out; char filler; char graph_cntl_index; + char graph_cntl_data; } v3cc; + typedef struct { + v3c0 v3c0_regs; + v3c4 v3c4_regs; + v3c8 v3c8_regs; + v3cc v3cc_regs; + } vga_3c_regs; + + typedef struct { char crt_index; char crt_data; int16 filler; } v3d4; + typedef struct { int16 filler1; char feature_cntl; char filler2;} v3d8; + + typedef struct { + int32 filler; + v3d4 v3d4_regs; + v3d8 v3d8_regs; + } vga_3bd_regs ; + + typedef struct { + int32 subsystem_csr; + int32 dummy; + adv_f_cntl adv_func_cntl; + } subsys_regs; + + + typedef struct { + int32 cur_x; + char filler1[0x8ae8 - 0x86e8 - sizeof(int32)]; + int32 dy_axstep; + char filler2[0x8ee8 - 0x8ae8 - sizeof(int32)]; + int32 dx_diastep; + char filler3[0x92e8 - 0x8ee8 - sizeof(int32)]; + int32 line_err; + char filler33[0x96e8 - 0x92e8 - sizeof(int32)]; + int32 mj_ax_pcnt; + char filler4[0x9ae8 - 0x96e8 - sizeof(int32)]; + int32 gp_stat; + char filler5[0x9ee8 - 0x9ae8 - sizeof(int32)]; + int32 stroke_vectrans; + char filler6[0xa2e8 - 0x9ee8 - sizeof(int32)]; + int32 back_color; + char filler7[0xa6e8 - 0xa2e8 - sizeof(int32)]; + int32 fore_col; + char filler8[0xaae8 - 0xa6e8 - sizeof(int32)]; + int32 bitplane_wmask; + char filler88[0xaee8 - 0xaae8 - sizeof(int32)]; + int32 bitplane_rmask; + char filler9[0xb2e8 - 0xaee8 - sizeof(int32)]; + int32 color_compare; + char filler10[0xb6e8 - 0xb2e8 - sizeof(int32)]; + int32 back_mix; + char filler101[0xbae8 - 0xb6e8 - sizeof(int32)]; + int32 fore_mix; + char filler11[0xbee8 - 0xbae8 - sizeof(int32)]; + int32 r_reg_data; + char filler12[0xe2e8 - 0xbee8 - sizeof(int32)]; + int32 pixel_data_transfer; + } enhanced_regs; + + typedef struct { + int32 lpb_mode; + int32 lpb_fifostat; + int32 lpb_intflags; + int32 lpb_fb0addr; + int32 lpb_fb1addr; + int32 lpb_direct_addr; + int32 lpb_direct_data; + int32 lpb_gpio; + int32 lpb_serial_port; + int32 lpb_input_winsize; + int32 lpb_data_offsets; + int32 lpb_hor_decimctl; + int32 lpb_vert_decimctl; + int32 lpb_line_stride; + int32 lpb_output_fifo; + } lpbus_regs; + + typedef struct { + int32 img[0x8000/4]; + union { pci_conf_regs regs; + char dummy[0x100]; + } pci_regs; + union { packed_enhanced_regs regs; + char dummy[0x80]; + } pk_enh_regs; + union { streams_proc_regs regs; + char dummy[0x82e8-0x8180]; + } streams_regs; + union { int32 cur_y; + char dummy[0x83b0 - 0x82e8]; + } cur_y; + union { vga_3bd_regs regs; + char dummy[0x83c0 - 0x83b0]; + } v3b_regs; + union { vga_3c_regs regs; + char dummy[0x83d0 - 0x83c0]; + } v3c_regs; + union { vga_3bd_regs regs; + char dummy[0x8504 - 0x83d0]; + } v3d_regs; + union { subsys_regs regs; + char dummy[0x86e8 - 0x8504]; + } subs_regs; + union { enhanced_regs regs; + char dummy[0xff00 - 0x86e8]; + } enh_regs; + union { lpbus_regs regs; + char dummy[0xff5c - 0xff00]; + } lbp_regs; + } mm_trio_regs ; + + #define mmtr volatile mm_trio_regs * + + #define IMG_TRANS (((mmtr)s3MmioMem)->img) + + #define SET_WRT_MASK(msk) ((mmtr)s3MmioMem)->pk_enh_regs.regs.wrt_mask = (msk) + #define SET_RD_MASK(msk) ((mmtr)s3MmioMem)->pk_enh_regs.regs.rd_mask = (msk) + #define SET_FRGD_COLOR(col) ((mmtr)s3MmioMem)->pk_enh_regs.regs.frgd_color = (col) + #define SET_BKGD_COLOR(col) ((mmtr)s3MmioMem)->pk_enh_regs.regs.bkgd_color = (col) + #define SET_COLOR_CMP(col) ((mmtr)s3MmioMem)->pk_enh_regs.regs.color_cmp = (col) + #define SET_FRGD_MIX(fmix) ((mmtr)s3MmioMem)->enh_regs.regs.fore_mix = (fmix) + #define SET_BKGD_MIX(bmix) ((mmtr)s3MmioMem)->enh_regs.regs.back_mix = (bmix) + #define SET_PIX_CNTL(val) ((mmtr)s3MmioMem)->pk_enh_regs.regs.pix_mult = (val) | (MULT_MISC2 << 16) + #define SET_MIN_AXIS_PCNT(min) ((mmtr)s3MmioMem)->enh_regs.regs.r_reg_data = (min) & 0xffff + #define SET_MAJ_AXIS_PCNT(maj) ((mmtr)s3MmioMem)->enh_regs.regs.mj_ax_pcnt = (maj) + #define SET_CURPT(c_x, c_y) ((mmtr)s3MmioMem)->pk_enh_regs.regs.cur_point = ((c_y)&0xffff) | ((c_x) << 16) + #define SET_CUR_X(c_x) ((mmtr)s3MmioMem)->enh_regs.regs.cur_x = (c_x) + #define SET_CUR_Y(c_y) ((mmtr)s3MmioMem)->cur_y.cur_y = (c_y) + #define SET_DESTSTP(x,y) ((mmtr)s3MmioMem)->pk_enh_regs.regs.dest_stp = ((y)&0xffff) | ((x) << 16) + #define SET_AXIS_PCNT(maj, min) ((mmtr)s3MmioMem)->pk_enh_regs.regs.axis_pcnt = ((min)&0xffff) | ((maj) << 16) + #define SET_CMD(c_d) { mem_barrier(); ((mmtr)s3MmioMem)->pk_enh_regs.regs.command = (c_d); } + #define SET_ERR_TERM(e) ((mmtr)s3MmioMem)->pk_enh_regs.regs.err_term = (e) + #define SET_SCISSORS(x1,y1,x2,y2) {\ + ((mmtr)s3MmioMem)->pk_enh_regs.regs.sciss_topleft = ((y1)&0xffff) | ((x1) << 16);\ + ((mmtr)s3MmioMem)->pk_enh_regs.regs.sciss_botright = ((y2)&0xffff) | ((x2) << 16);\ + } + #define SET_SCISSORS_RB(x,y) ((mmtr)s3MmioMem)->pk_enh_regs.regs.sciss_botright = ((y)&0xffff) | ((x) << 16) + #define SET_SCISSORS_L(l) ((mmtr)s3MmioMem)->pk_enh_regs.regs.sciss_topleft = ((l) << 16); + #define SET_MULT_MISC(val) ((mmtr)s3MmioMem)->pk_enh_regs.regs.mult_misc = (val) + + /* + * reads from GP_STAT + */ + #if !defined(__alpha__) + #define INB_GP_STAT() ((((mmtr)s3MmioMem)->enh_regs.regs.gp_stat) & 0xff) + #define INW_GP_STAT() ((((mmtr)s3MmioMem)->enh_regs.regs.gp_stat)) + #else + #define INB_GP_STAT() inb(GP_STAT) + #define INW_GP_STAT() inw(GP_STAT) + #endif + + #define SET_PIX_TRANS_L(val) ((mmtr)s3MmioMem)->img[0] = (val) + #define SET_MIX(b,f) ((mmtr)s3MmioMem)->pk_enh_regs.regs.col_mix = ((b) << 16) | (f) + + + #define WaitQueue(v) \ + if(!s3PCIRetry) { \ + mem_barrier(); \ + while(inb(GP_STAT) & (0x0100 >> (v))); \ + } + + #define CMD_REG_WIDTH 0x200 /* select 32bit command register */ + + #define WaitQueue16_32(n16,n32) \ + if(s3Bpp <= 2) { WaitQueue(n16); } \ + else { WaitQueue(n32); } + + #endif /* _NEWMMIO_H_ */ *** /dev/null Tue Jun 30 15:22:58 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/README.S3 Fri Mar 6 16:52:47 1998 *************** *** 0 **** --- 1,56 ---- + + This is the README for the new experimental S3 driver for + non-ViRGE S3 chipsets in the XF86_SVGA server. This is definitely + an ALPHA quality driver and hasn't been well tested. + Because of this, the configuration programs will install XF86_S3 by + default rather than this one. But if you're adventurous or had some + problems with XF86_S3, you might want to give it a try. + + The driver includes generic S3 support which should work on + all non-ViRGE S3 chips (in theory, that is). It also has improved + support for chips that support S3's new style memory mapped I/O. + These chips include the 868, 968 and recent Trio64 variants (not + the plain old Trio64s). Chips that are capable of using the new + style MMIO will use it automatically. The option "NO_MMIO" can + be used to turn this off. + + Performance for chips using the new style MMIO is expected + to be better than XF86_S3, especially on a PCI bus. Performance + without MMIO, however, is expected to be roughly comparable + to XF86_S3 (faster in some areas, slower in others). + + All color depths achievable with XF86_S3 should be possible + with these drivers. Additionally, packed 24 bpp "sortof" works + for the 868 and 968. Your results may vary. + + Nearly all the options and features supported by XF86_S3 + are supported by this driver. Additionally, the standard XAA/SVGA + server options such as NO_ACCEL, SW_CURSOR, and NO_PIXMAP_CACHE are + also supported. XF86_S3 features which are NOT supported in this + driver are DPMS support and gamma correction. + + The driver supports the PCI_RETRY option when using MMIO and + a PCI card. This option can give large performance boosts for + some operations, but has a tendency to hog the bus. Because + of this, the option is not set by default. Most hardware + combinations may not have any problems using this option, but + sound card gliches during intensive graphics operations have + been reported on some. + + One shortcoming worth noting is that this driver does not yet + contain the work-around for some S3 PCI bioses that report + their memory usage incorrectly. This can result in conflicting + address spaces. If this is the case on your hardware you should + run XF86_S3 once and write down the address that your card is + relocated to (as printed out in the server output). Then you can + force the server to use this address with the MemBase field in the + XF86Config (see the man page on XF86Config). + + + + + $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/README.S3,v 1.1.2.3 1998/02/27 03:29:58 dawes Exp $ + + + + $TOG: README.S3 /main/1 1998/03/06 16:54:24 kaleb $ *** /dev/null Tue Jun 30 15:22:58 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/s3accel.c Fri Mar 6 16:53:23 1998 *************** *** 0 **** --- 1,1394 ---- + /* $TOG: s3accel.c /main/1 1998/03/06 16:55:00 kaleb $ */ + + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/s3accel.c,v 1.1.2.1 1998/02/07 10:05:38 hohndel Exp $ */ + + /* + * + * Copyright 1996-1997 The XFree86 Project, Inc. + * + * + * Written by Mark Vojkovich (mvojkovi@ucsd.edu) + * + */ + + #define PSZ 8 + + #include "vga256.h" + #include "xf86.h" + #include "vga.h" + + #include "xf86xaa.h" + + #include "s3.h" + #include "s3reg.h" + + static void S3Sync(); + static void S3SetupForScreenToScreenCopy(); + static void S3SubsequentScreenToScreenCopy(); + static void S3SetupForFillRectSolid(); + static void S3SubsequentFillRectSolid(); + static void S3SubsequentBresenhamLine(); + static void S3SetupForDashedLine(); + static void S3SubsequentDashedBresenhamLine32(); + static void S3SetupForFill8x8Pattern(); + static void S3SubsequentFill8x8Pattern(); + static void S3SetupForCPUToScreenColorExpand(); + static void S3FillRectStippledCPUToScreenColorExpand(); + static void S3WriteBitmapCPUToScreenColorExpand32(); + #ifdef S3_NEWMMIO + static void S3SubsequentCPUToScreenColorExpand32(); + #else + static void S3SubsequentDashedBresenhamLine16(); + static void S3SetupForScanlineScreenToScreenColorExpand(); + static void S3SubsequentScanlineScreenToScreenColorExpand16(); + static void S3SubsequentScanlineScreenToScreenColorExpand32(); + static void S3WriteBitmapCPUToScreenColorExpand16(); + #endif + + static Bool Transfer32 = FALSE; + static Bool ColorExpandBug = FALSE; + static unsigned char ScratchBuffer[512]; + static unsigned char SwappedBytes[256]; + static CARD32 ShiftMasks[32]; + + #define MAX_LINE_PATTERN_LENGTH 512 + #define LINE_PATTERN_START ((MAX_LINE_PATTERN_LENGTH >> 5) - 1) + static CARD32 DashPattern[MAX_LINE_PATTERN_LENGTH >> 5]; + + void + #ifdef S3_NEWMMIO + S3AccelInit_NewMMIO() + #else + S3AccelInit() + #endif + { + #ifndef S3_NEWMMIO + if(S3_x64_SERIES(s3ChipId)) + #endif + Transfer32 = TRUE; + + if(S3_x68_SERIES(s3ChipId)) + ColorExpandBug = TRUE; + + xf86AccelInfoRec.Flags = BACKGROUND_OPERATIONS | PIXMAP_CACHE | + COP_FRAMEBUFFER_CONCURRENCY | + LINE_PATTERN_MSBFIRST_MSBJUSTIFIED | + HARDWARE_PATTERN_NOT_LINEAR; + + if(s3Bpp != 3) + xf86AccelInfoRec.Flags |= HARDWARE_PATTERN_TRANSPARENCY; + + xf86AccelInfoRec.Sync = S3Sync; + + /* copy area */ + if((s3Bpp == 3) || S3_911_SERIES(s3ChipId)) + xf86GCInfoRec.CopyAreaFlags = NO_TRANSPARENCY; + else + xf86GCInfoRec.CopyAreaFlags = TRANSPARENCY_GXCOPY; + + xf86AccelInfoRec.SetupForScreenToScreenCopy = + S3SetupForScreenToScreenCopy; + xf86AccelInfoRec.SubsequentScreenToScreenCopy = + S3SubsequentScreenToScreenCopy; + + /* filled rects */ + xf86AccelInfoRec.SetupForFillRectSolid = S3SetupForFillRectSolid; + xf86AccelInfoRec.SubsequentFillRectSolid = S3SubsequentFillRectSolid; + + + /* lines */ + xf86AccelInfoRec.SubsequentBresenhamLine = S3SubsequentBresenhamLine; + if(S3_911_SERIES(s3ChipId)) + xf86AccelInfoRec.ErrorTermBits = 11; + else + xf86AccelInfoRec.ErrorTermBits = 12; + + /* dashed lines */ + if(s3Bpp != 3) { + xf86AccelInfoRec.SetupForDashedLine = S3SetupForDashedLine; + xf86AccelInfoRec.LinePatternBuffer = (void*)DashPattern; + xf86AccelInfoRec.LinePatternMaxLength = MAX_LINE_PATTERN_LENGTH; + #ifndef S3_NEWMMIO + if(!Transfer32) + xf86AccelInfoRec.SubsequentDashedBresenhamLine = + S3SubsequentDashedBresenhamLine16; + else + #endif + xf86AccelInfoRec.SubsequentDashedBresenhamLine = + S3SubsequentDashedBresenhamLine32; + } + + /* 8x8 pattern fills */ + /* A hardware bug in some S3's at 32bpp is worked-around in + the XAA pixmap code */ + if(!S3_911_SERIES(s3ChipId)) { + xf86AccelInfoRec.SetupForFill8x8Pattern = S3SetupForFill8x8Pattern; + xf86AccelInfoRec.SubsequentFill8x8Pattern = S3SubsequentFill8x8Pattern; + } + + + /* Color Expand */ + #ifdef S3_NEWMMIO + xf86AccelInfoRec.SetupForCPUToScreenColorExpand = + S3SetupForCPUToScreenColorExpand; + xf86AccelInfoRec.SubsequentCPUToScreenColorExpand = + S3SubsequentCPUToScreenColorExpand32; + + xf86AccelInfoRec.CPUToScreenColorExpandBase = (void*) &IMG_TRANS; + xf86AccelInfoRec.CPUToScreenColorExpandRange = 0x8000; + + xf86AccelInfoRec.ColorExpandFlags = CPU_TRANSFER_PAD_DWORD | + BIT_ORDER_IN_BYTE_MSBFIRST | + SCANLINE_PAD_DWORD; + + #else + xf86AccelInfoRec.SetupForScanlineScreenToScreenColorExpand = + S3SetupForScanlineScreenToScreenColorExpand; + if(Transfer32) { + xf86AccelInfoRec.SubsequentScanlineScreenToScreenColorExpand = + S3SubsequentScanlineScreenToScreenColorExpand32; + } else { + xf86AccelInfoRec.SubsequentScanlineScreenToScreenColorExpand = + S3SubsequentScanlineScreenToScreenColorExpand16; + } + + xf86AccelInfoRec.ColorExpandFlags = BIT_ORDER_IN_BYTE_MSBFIRST; + + xf86AccelInfoRec.ScratchBufferAddr = 1; + xf86AccelInfoRec.ScratchBufferSize = 512; + xf86AccelInfoRec.ScratchBufferBase = (void*)ScratchBuffer; + xf86AccelInfoRec.PingPongBuffers = 1; + + #endif + + + /* Stippled rect replacements */ + + xf86AccelInfoRec.FillRectOpaqueStippled = + S3FillRectStippledCPUToScreenColorExpand; + xf86AccelInfoRec.FillRectStippled = + S3FillRectStippledCPUToScreenColorExpand; + + + /* Write Bitmap replacements */ + #ifndef S3_NEWMMIO + if(!Transfer32) + xf86AccelInfoRec.WriteBitmap = + S3WriteBitmapCPUToScreenColorExpand16; + else + #endif + xf86AccelInfoRec.WriteBitmap = + S3WriteBitmapCPUToScreenColorExpand32; + + + /* pixmap cache */ + xf86AccelInfoRec.PixmapCacheMemoryStart = + vga256InfoRec.virtualY * s3BppDisplayWidth; + xf86AccelInfoRec.PixmapCacheMemoryEnd = + (vga256InfoRec.videoRam * 1024) - s3CursorBytes; + + { + int i,j; + register unsigned char newbyte; + register unsigned char oldbyte; + + for(i = 0; i < 256; i++) { + oldbyte = i; + newbyte = 0; + j = 8; + while(j--) { + newbyte <<= 1; + if(oldbyte & 0x01) newbyte++; + oldbyte >>= 1; + } + SwappedBytes[i] = newbyte; + } + + for(i = 0; i < 32; i++) + ShiftMasks[i] = (1 << i) - 1; + } + + } + + /******************\ + | Sync | + \******************/ + + void S3Sync() { + WaitIdle(); + } + + + /***************************************\ + | Screen-to-Screen Copy | + \***************************************/ + + + static unsigned short BltDirection; + static int TransColor = -1; + + static + void S3SetupForScreenToScreenCopy(xdir, ydir, rop, planemask, trans_color) + int xdir, ydir; + int rop; + unsigned planemask; + int trans_color; + { + BltDirection = CMD_BITBLT | DRAW | WRTDATA; + + if(xdir == 1) BltDirection |= INC_X; + if(ydir == 1) BltDirection |= INC_Y; + + TransColor = trans_color; + + WaitQueue16_32(3,4); + SET_PIX_CNTL(0); + SET_FRGD_MIX(FSS_BITBLT | s3alu[rop]); + SET_WRT_MASK(planemask); + } + + + static + void S3SubsequentScreenToScreenCopy(srcX, srcY, destX, destY, w, h) + int srcX, srcY, destX, destY, w, h; + { + w--; h--; + + if(!(BltDirection & INC_Y)) { + srcY += h; + destY += h; + } + + if(!(BltDirection & INC_X)) { + srcX += w; + destX += w; + } + + if(TransColor == -1) { + WaitQueue(7); + SET_CURPT((short)srcX,(short)srcY); + SET_DESTSTP((short)destX, (short)destY); + SET_AXIS_PCNT((short)w,(short)h); + SET_CMD(BltDirection); + } else { + WaitQueue16_32(2,3); + SET_MULT_MISC(CMD_REG_WIDTH | 0x0100); /* enable compare */ + SET_COLOR_CMP(TransColor); + + WaitQueue(8); + SET_CURPT((short)srcX,(short)srcY); + SET_DESTSTP((short)destX, (short)destY); + SET_AXIS_PCNT((short)w,(short)h); + SET_CMD(BltDirection); + SET_MULT_MISC(CMD_REG_WIDTH); /* disable compare */ + } + } + + /***********************\ + | Solid Rects | + \***********************/ + + + static + void S3SetupForFillRectSolid(color, rop, planemask) + int color, rop; + unsigned planemask; + { + WaitQueue16_32(4,6); + SET_PIX_CNTL(0); + SET_FRGD_COLOR(color); + SET_FRGD_MIX(FSS_FRGDCOL | s3alu[rop]); + SET_WRT_MASK(planemask); + } + + static + void S3SubsequentFillRectSolid(x, y, w, h) + int x, y, w, h; + { + WaitQueue(5); + SET_CURPT((short)x, (short)y); + SET_AXIS_PCNT(w - 1, h - 1); + SET_CMD(CMD_RECT | DRAW | INC_X | INC_Y | WRTDATA); + } + + /***********************\ + | Lines | + \***********************/ + + #include "miline.h" + + static + void S3SubsequentBresenhamLine(x1, y1, octant, err, e1, e2, length) + int x1, y1, octant, err, e1, e2, length; + { + unsigned short cmd; + + /* Note: + We rely on the fact that XAA will never send us a horizontal line + */ + if(e1) { + cmd = CMD_LINE | DRAW | WRTDATA | LASTPIX; + + if(octant & YMAJOR) cmd |= YMAJAXIS; + if(!(octant & XDECREASING)) cmd |= INC_X; + if(!(octant & YDECREASING)) cmd |= INC_Y; + + WaitQueue(7); + SET_CURPT((short)x1, (short)y1); + SET_ERR_TERM((short)err); + SET_DESTSTP((short)e2, (short)e1); + SET_MAJ_AXIS_PCNT((short)length); + SET_CMD(cmd); + } else { /* vertical line */ + WaitQueue(4); + SET_CURPT((short)x1, (short)y1); + SET_MAJ_AXIS_PCNT((short)length - 1); + SET_CMD(CMD_LINE | DRAW | LINETYPE | WRTDATA | VECDIR_270); + } + } + + + + /*******************************\ + | 8x8 Fill Patterns | + \*******************************/ + + static + void S3SetupForFill8x8Pattern(patternx, patterny, rop, planemask, trans_col) + int patternx, patterny, rop, planemask, trans_col; + { + TransColor = trans_col; + WaitQueue16_32(3,4); + SET_PIX_CNTL(0); + SET_FRGD_MIX(FSS_BITBLT | s3alu[rop]); + SET_WRT_MASK(planemask); + } + + static + void S3SubsequentFill8x8Pattern(patternx, patterny, x, y, w, h) + int patternx, patterny, x, y, w, h; + { + if(TransColor == -1) { + WaitQueue(7); + SET_CURPT((short)patternx, (short)patterny); + SET_DESTSTP((short)x, (short)y); + SET_AXIS_PCNT(w - 1, h - 1); + SET_CMD(CMD_PFILL | DRAW | INC_Y | INC_X | WRTDATA); + } else { + WaitQueue16_32(2,3); + SET_MULT_MISC(CMD_REG_WIDTH | 0x0100); /* enable compare */ + SET_COLOR_CMP(TransColor); + + WaitQueue(8); + SET_CURPT((short)patternx, (short)patterny); + SET_DESTSTP((short)x, (short)y); + SET_AXIS_PCNT(w - 1, h - 1); + SET_CMD(CMD_PFILL | DRAW | INC_Y | INC_X | WRTDATA); + SET_MULT_MISC(CMD_REG_WIDTH); /* disable compare */ + } + } + + /***************************************\ + | CPU to Screen Color Expansion | + \***************************************/ + + + static + void S3SetupForCPUToScreenColorExpand(bg, fg, rop, planemask) + int bg, fg, rop; + unsigned planemask; + { + WaitQueue16_32(3, 4); + if(bg == -1) { + if(ColorExpandBug) { + SET_MIX(FSS_FRGDCOL | s3alu[rop], BSS_BKGDCOL | MIX_XOR); + SET_BKGD_COLOR(0); + } else + SET_MIX(FSS_FRGDCOL | s3alu[rop], BSS_BKGDCOL | MIX_DST); + } else { + SET_MIX(FSS_FRGDCOL | s3alu[rop], BSS_BKGDCOL | s3alu[rop]); + SET_BKGD_COLOR(bg); + } + + WaitQueue16_32(3, 5); + SET_FRGD_COLOR(fg); + SET_WRT_MASK(planemask); + SET_PIX_CNTL(MIXSEL_EXPPC); + } + + + #ifdef S3_NEWMMIO + + static + void S3SubsequentCPUToScreenColorExpand32(x, y, w, h, skipleft) + int x, y, w, h, skipleft; + { + WaitQueue(4); + SET_CURPT((short)x, (short)y); + SET_AXIS_PCNT((short)w - 1, (short)h - 1); + + WaitIdle(); + SET_CMD(CMD_RECT | BYTSEQ | _32BIT | PCDATA | DRAW | PLANAR | + INC_Y | INC_X | WRTDATA); + } + + #endif + + /***********************************************\ + | Indirect Color Expansion Hack | + \***********************************************/ + + #ifndef S3_NEWMMIO + + static int ScanlineWordCount; + + static + void S3SetupForScanlineScreenToScreenColorExpand(x, y, w, h, bg, fg, + rop, planemask) + int x, y, w, h, bg, fg, rop, planemask; + { + S3SetupForCPUToScreenColorExpand(bg, fg, rop, planemask); + + WaitQueue(4); + SET_CURPT((short)x, (short)y); + SET_AXIS_PCNT((short)w - 1, (short)h - 1); + + if(Transfer32) { + ScanlineWordCount = (w + 31) >> 5; + + WaitIdle(); + SET_CMD(CMD_RECT | BYTSEQ | _32BIT | PCDATA | DRAW | PLANAR | + INC_Y | INC_X | WRTDATA); + } else { + ScanlineWordCount = (w + 15) >> 4; + + WaitIdle(); + SET_CMD(CMD_RECT | BYTSEQ | _16BIT | PCDATA | DRAW | PLANAR | + INC_Y | INC_X | WRTDATA); + } + } + + static + void S3SubsequentScanlineScreenToScreenColorExpand16(int srcaddr) + { + register unsigned short *ptr = (unsigned short*)ScratchBuffer; + register int count = ScanlineWordCount; + + while(count--) + SET_PIX_TRANS_W(*(ptr++)); + } + + static + void S3SubsequentScanlineScreenToScreenColorExpand32(int srcaddr) + { + register CARD32 *ptr = (CARD32*)ScratchBuffer; + register int count = ScanlineWordCount; + + while(count--) + SET_PIX_TRANS_L(*(ptr++)); + } + + #endif + + /***********************\ + | Dashed Lines | + \***********************/ + + + static int DashPatternSize; + static Bool NicePattern; + + static + void S3SetupForDashedLine(fg, bg, rop, planemask, size) + int fg, bg, rop, planemask, size; + { + S3SetupForCPUToScreenColorExpand(bg, fg, rop, planemask); + + NicePattern = FALSE; + + if(size <= 32) { + register CARD32 scratch = DashPattern[LINE_PATTERN_START]; + if(size & (size - 1)) { + while(size < 16) { + scratch |= (scratch >> size); + size <<= 1; + } + scratch |= (scratch >> size); + DashPattern[LINE_PATTERN_START] = scratch; + } else { + switch(size) { + case 2: scratch |= scratch >> 2; + case 4: scratch |= scratch >> 4; + case 8: scratch |= scratch >> 8; + case 16: scratch |= scratch >> 16; + DashPattern[LINE_PATTERN_START] = scratch; + case 32: NicePattern = TRUE; + default: break; + } + } + } + DashPatternSize = size; + } + + + static void + S3SubsequentDashedBresenhamLine32(x1, y1, octant, err, e1, e2, length, start) + int x1, y1, octant, err, e1, e2, length, start; + { + register int count = (length + 31) >> 5; + register CARD32 pattern; + + if(e1) { + unsigned short cmd = _32BIT | PLANAR | WRTDATA | DRAW | PCDATA | + LASTPIX | CMD_LINE; + + if(octant & YMAJOR) cmd |= YMAJAXIS; + if(!(octant & XDECREASING)) cmd |= INC_X; + if(!(octant & YDECREASING)) cmd |= INC_Y; + + WaitQueue(7); + SET_CURPT((short)x1, (short)y1); + SET_ERR_TERM((short)err); + SET_DESTSTP((short)e2, (short)e1); + SET_MAJ_AXIS_PCNT((short)length); + SET_CMD(cmd); + } else { + if (octant & YMAJOR){ + WaitQueue(4); + SET_CURPT((short)x1, (short)y1); + SET_MAJ_AXIS_PCNT((short)length - 1); + + if(octant & YDECREASING) { + SET_CMD(_32BIT | PLANAR | WRTDATA | DRAW | PCDATA | + CMD_LINE | LINETYPE | VECDIR_090); + } else { + SET_CMD(_32BIT | PLANAR | WRTDATA | DRAW | PCDATA | + CMD_LINE | LINETYPE | VECDIR_270); + } + } else { + if(octant & XDECREASING) { + WaitQueue(4); + SET_CURPT((short)x1, (short)y1); + SET_MAJ_AXIS_PCNT((short)length - 1); + SET_CMD(_32BIT | PLANAR | WRTDATA | DRAW | PCDATA | + CMD_LINE | LINETYPE | VECDIR_180); + } else { /* he he */ + WaitQueue(4); + SET_CURPT((short)x1, (short)y1); + SET_AXIS_PCNT((short)length - 1, 0); + + WaitIdle(); + SET_CMD(_32BIT | PLANAR | WRTDATA | DRAW | PCDATA | + CMD_RECT | INC_Y | INC_X); + } + } + } + + if(NicePattern) { + #ifdef S3_NEWMMIO + register CARD32* dest = (CARD32*)&IMG_TRANS; + #endif + pattern = (start) ? + (DashPattern[LINE_PATTERN_START] << start) | + (DashPattern[LINE_PATTERN_START] >> (32 - start)) : + DashPattern[LINE_PATTERN_START]; + + #ifdef S3_NEWMMIO + while(count & ~0x03) { + dest[0] = dest[1] = dest[2] = dest[3] = pattern; + dest += 4; + count -= 4; + } + switch(count) { + case 1: dest[0] = pattern; + break; + case 2: dest[0] = dest[1] = pattern; + break; + case 3: dest[0] = dest[1] = dest[2] = pattern; + break; + } + #else + while(count--) + SET_PIX_TRANS_L(pattern); + #endif + } else if(DashPatternSize < 32) { + register int offset = start; + + while(count--) { + SET_PIX_TRANS_L((DashPattern[LINE_PATTERN_START] << offset) | + (DashPattern[LINE_PATTERN_START] >> (DashPatternSize-offset))); + offset += 32; + while(offset > DashPatternSize) + offset -= DashPatternSize; + } + } else { + int offset = start; + register unsigned char* srcp = (unsigned char*)(DashPattern) + + (MAX_LINE_PATTERN_LENGTH >> 3) - 1; + register CARD32* scratch; + int scratch2, shift; + + while(count--) { + shift = DashPatternSize - offset; + scratch = (CARD32*)(srcp - (offset >> 3) - 3); + scratch2 = offset & 0x07; + + if(shift & ~31) { + if(scratch2) { + pattern = (*scratch << scratch2) | + (*(scratch - 1) >> (32 - scratch2)); + } else + pattern = *scratch; + } else { + pattern = (*((CARD32*)(srcp - 3)) >> shift) | + (*scratch << scratch2); + } + SET_PIX_TRANS_L(pattern); + offset += 32; + while(offset >= DashPatternSize) + offset -= DashPatternSize; + } + } + } + + #ifndef S3_NEWMMIO + + static + void S3SubsequentDashedBresenhamLine16(x1, y1, octant, err, e1, e2, length, + start) + int x1, y1, octant, err, e1, e2, length, start; + { + register int count = (length + 15) >> 4; + register CARD32 pattern; + Bool plus_one; + + plus_one = (count & 0x01); + count >>= 1; + + if(e1) { + unsigned short cmd = _16BIT | PLANAR | WRTDATA | DRAW | PCDATA | + LASTPIX | CMD_LINE; + + + if(octant & YMAJOR) cmd |= YMAJAXIS; + if(!(octant & XDECREASING)) cmd |= INC_X; + if(!(octant & YDECREASING)) cmd |= INC_Y; + + WaitQueue(7); + SET_CURPT((short)x1, (short)y1); + SET_ERR_TERM((short)err); + SET_DESTSTP((short)e2, (short)e1); + SET_MAJ_AXIS_PCNT((short)length); + SET_CMD(cmd); + } else { + if (octant & YMAJOR){ + WaitQueue(4); + SET_CURPT((short)x1, (short)y1); + SET_MAJ_AXIS_PCNT((short)length - 1); + + if(octant & YDECREASING) { + SET_CMD(_16BIT | PLANAR | WRTDATA | DRAW | PCDATA | + CMD_LINE | LINETYPE | VECDIR_090); + } else { + SET_CMD(_16BIT | PLANAR | WRTDATA | DRAW | PCDATA | + CMD_LINE | LINETYPE | VECDIR_270); + } + } else { + if(octant & XDECREASING) { + WaitQueue(4); + SET_CURPT((short)x1, (short)y1); + SET_MAJ_AXIS_PCNT((short)length - 1); + SET_CMD(_16BIT | PLANAR | WRTDATA | DRAW | PCDATA | + CMD_LINE | LINETYPE | VECDIR_180); + } else { /* he he */ + WaitQueue(4); + SET_CURPT((short)x1, (short)y1); + SET_AXIS_PCNT((short)length - 1, 0); + + WaitIdle(); + SET_CMD(_16BIT | PLANAR | WRTDATA | DRAW | PCDATA | + CMD_RECT | INC_Y | INC_X); + } + } + } + + if(NicePattern) { + pattern = (start) ? + (DashPattern[LINE_PATTERN_START] << start) | + (DashPattern[LINE_PATTERN_START] >> (32 - start)) : + DashPattern[LINE_PATTERN_START]; + + while(count--) { + SET_PIX_TRANS_W(pattern >> 16); + SET_PIX_TRANS_W(pattern); + } + if(plus_one) + SET_PIX_TRANS_W(pattern >> 16); + + } else if(DashPatternSize < 32) { + register int offset = start; + + while(count--) { + pattern = (DashPattern[LINE_PATTERN_START] << offset) | + (DashPattern[LINE_PATTERN_START] >> (DashPatternSize-offset)); + SET_PIX_TRANS_W(pattern >> 16); + offset += 32; + while(offset > DashPatternSize) + offset -= DashPatternSize; + SET_PIX_TRANS_W(pattern); + } + if(plus_one) + SET_PIX_TRANS_W(((DashPattern[LINE_PATTERN_START] << offset) | + (DashPattern[LINE_PATTERN_START] >> + (DashPatternSize - offset))) >> 16); + } else { + int offset = start; + register unsigned char* srcp = (unsigned char*)(DashPattern) + + (MAX_LINE_PATTERN_LENGTH >> 3) - 1; + register CARD32* scratch; + int scratch2, shift; + + while(count--) { + shift = DashPatternSize - offset; + scratch = (CARD32*)(srcp - (offset >> 3) - 3); + scratch2 = offset & 0x07; + + if(shift & ~31) { + if(scratch2) { + pattern = (*scratch << scratch2) | + (*(scratch - 1) >> (32 - scratch2)); + } else + pattern = *scratch; + } else { + pattern = (*((CARD32*)(srcp - 3)) >> shift) | + (*scratch << scratch2); + + } + SET_PIX_TRANS_W(pattern >> 16); + offset += 32; + while(offset >= DashPatternSize) + offset -= DashPatternSize; + SET_PIX_TRANS_W(pattern); + } + if(plus_one) { + shift = DashPatternSize - offset; + scratch = (CARD32*)(srcp - (offset >> 3) - 3); + scratch2 = offset & 0x07; + + if(shift & ~31) { + if(scratch2) { + pattern = (*scratch << scratch2) | + (*(scratch - 1) >> (32 - scratch2)); + } else + pattern = *scratch; + } else { + pattern = (*((CARD32*)(srcp - 3)) >> shift) | + (*scratch << scratch2); + + } + SET_PIX_TRANS_W(pattern >> 16); + } + } + } + + #endif + + /***************************************\ + | Some static helper functions | + \***************************************/ + + + #if defined(__GNUC__) && defined(__i386__) + static __inline__ CARD32 reverse_bitorder(CARD32 data) { + #if defined(Lynx) || (defined(SYSV) || defined(SVR4)) && !defined(ACK_ASSEMBLER) || (defined(linux) || defined (__OS2ELF__)) && defined(__ELF__) + __asm__( + "movl $0,%%ecx\n" + "movb %%al,%%cl\n" + "movb SwappedBytes(%%ecx),%%al\n" + "movb %%ah,%%cl\n" + "movb SwappedBytes(%%ecx),%%ah\n" + "roll $16,%%eax\n" + "movb %%al,%%cl\n" + "movb SwappedBytes(%%ecx),%%al\n" + "movb %%ah,%%cl\n" + "movb SwappedBytes(%%ecx),%%ah\n" + "roll $16,%%eax\n" + : "=a" (data) : "0" (data) + : "cx" + ); + #else + __asm__( + "movl $0,%%ecx\n" + "movb %%al,%%cl\n" + "movb _SwappedBytes(%%ecx),%%al\n" + "movb %%ah,%%cl\n" + "movb _SwappedBytes(%%ecx),%%ah\n" + "roll $16,%%eax\n" + "movb %%al,%%cl\n" + "movb _SwappedBytes(%%ecx),%%al\n" + "movb %%ah,%%cl\n" + "movb _SwappedBytes(%%ecx),%%ah\n" + "roll $16,%%eax\n" + : "=a" (data) : "0" (data) + : "cx" + ); + #endif + return data; + } + #else + static __inline__ CARD32 reverse_bitorder(CARD32 data) { + unsigned char* kludge = (unsigned char*)&data; + + kludge[0] = SwappedBytes[kludge[0]]; + kludge[1] = SwappedBytes[kludge[1]]; + kludge[2] = SwappedBytes[kludge[2]]; + kludge[3] = SwappedBytes[kludge[3]]; + + return data; + } + #endif + + #ifdef S3_NEWMMIO + static __inline__ SetDWORDS(dest, value, dwords) + register CARD32* dest; + register CARD32 value; + register int dwords; + { + while(dwords & ~0x03) { + dest[0] = dest[1] = dest[2] = dest[3] = value; + dest += 4; + dwords -= 4; + } + switch(dwords) { + case 1: dest[0] = value; + break; + case 2: dest[0] = dest[1] = value; + break; + case 3: dest[0] = dest[1] = dest[2] = value; + break; + } + } + #endif + + + /***********************************************\ + | Stippled Rectangle Replacements | + \***********************************************/ + + + + static void + S3FillStippledCPUToScreenColorExpand32(x, y, w, h, src, srcwidth, + stipplewidth, stippleheight, srcx, srcy) + int x, y, w, h; + unsigned char *src; + int srcwidth; + int stipplewidth, stippleheight; + int srcx, srcy; + { + unsigned char *srcp; + int dwords, count; + + WaitQueue(4); + SET_CURPT((short)x, (short)y); + SET_AXIS_PCNT((short)w - 1, (short)h - 1); + + dwords = (w + 31) >> 5; + srcp = (srcwidth * srcy) + src; + + WaitIdle(); + SET_CMD(CMD_RECT | BYTSEQ | _32BIT | PCDATA | DRAW | PLANAR | + INC_Y | INC_X | WRTDATA); + + + if(!((stipplewidth > 32) || (stipplewidth & (stipplewidth - 1)))) { + CARD32 pattern; + register unsigned char* kludge = (unsigned char*)(&pattern); + + while(h--) { + switch(stipplewidth) { + case 32: + pattern = *((CARD32*)srcp); + break; + case 16: + kludge[0] = kludge[2] = srcp[0]; + kludge[1] = kludge[3] = srcp[1]; + break; + case 8: + kludge[0] = kludge[1] = kludge[2] = kludge[3] = srcp[0]; + break; + case 4: + kludge[0] = kludge[1] = kludge[2] = kludge[3] = + (srcp[0] & 0x0F); + pattern |= (pattern << 4); + break; + case 2: + kludge[0] = kludge[1] = kludge[2] = kludge[3] = + (srcp[0] & 0x03); + pattern |= (pattern << 2); + pattern |= (pattern << 4); + break; + default: /* case 1: */ + if(srcp[0] & 0x01) + pattern = 0xffffffff; + else + pattern = 0x00000000; + break; + } + + if(srcx) + pattern = (pattern >> srcx) | (pattern << (32 - srcx)); + pattern = reverse_bitorder(pattern); + + #ifdef S3_NEWMMIO + SetDWORDS((CARD32*)&IMG_TRANS, pattern, dwords); + #else + count = dwords; + while(count--) + SET_PIX_TRANS_L(pattern); + #endif + srcy++; + srcp += srcwidth; + if (srcy >= stippleheight) { + srcy = 0; + srcp = src; + } + } + } else if(stipplewidth < 32) { + register int width, offset; + register CARD32 pattern; + + while(h--) { + width = stipplewidth; + pattern = *((CARD32*)srcp) & ShiftMasks[width]; + while(!(width & ~15)) { + pattern |= (pattern << width); + width <<= 1; + } + pattern |= (pattern << width); + + + offset = srcx; + + count = dwords; + while(count--) { + SET_PIX_TRANS_L(reverse_bitorder((pattern >> offset) | + (pattern << (width - offset)))); + offset += 32; + while(offset >= width) + offset -= width; + } + + srcy++; + srcp += srcwidth; + if (srcy >= stippleheight) { + srcy = 0; + srcp = src; + } + } + } else { + register CARD32* scratch; + register CARD32 pattern; + int shift, offset, scratch2; + + while(h--) { + count = dwords; + offset = srcx; + + while(count--) { + shift = stipplewidth - offset; + scratch = (CARD32*)(srcp + (offset >> 3)); + scratch2 = offset & 0x07; + + if(shift & ~31) { + if(scratch2) { + pattern = (*scratch >> scratch2) | + (scratch[1] << (32 - scratch2)); + } else + pattern = *scratch; + } else { + pattern = (*((CARD32*)srcp) << shift) | + ((*scratch >> scratch2) & ShiftMasks[shift]); + } + SET_PIX_TRANS_L(reverse_bitorder(pattern)); + offset += 32; + while(offset >= stipplewidth) + offset -= stipplewidth; + } + + srcy++; + srcp += srcwidth; + if (srcy >= stippleheight) { + srcy = 0; + srcp = src; + } + } + } + } + + #ifndef S3_NEWMMIO + + static void + S3FillStippledCPUToScreenColorExpand16(x, y, w, h, src, srcwidth, + stipplewidth, stippleheight, srcx, srcy) + int x, y, w, h; + unsigned char *src; + int srcwidth; + int stipplewidth, stippleheight; + int srcx, srcy; + { + unsigned char *srcp; + int dwords, count; + Bool PlusOne; + + WaitQueue(4); + SET_CURPT((short)x, (short)y); + SET_AXIS_PCNT((short)w - 1, (short)h - 1); + + dwords = (w + 15) >> 4; + PlusOne = (dwords & 0x01); + dwords >>= 1; + srcp = (srcwidth * srcy) + src; + + WaitIdle(); + SET_CMD(CMD_RECT | BYTSEQ | _16BIT | PCDATA | DRAW | PLANAR | + INC_Y | INC_X | WRTDATA); + + if(!((stipplewidth > 32) || (stipplewidth & (stipplewidth - 1)))) { + CARD32 pattern; + register unsigned char* kludge = (unsigned char*)(&pattern); + + while(h--) { + switch(stipplewidth) { + case 32: + pattern = *((CARD32*)srcp); + break; + case 16: + kludge[0] = kludge[2] = srcp[0]; + kludge[1] = kludge[3] = srcp[1]; + break; + case 8: + kludge[0] = kludge[1] = kludge[2] = kludge[3] = srcp[0]; + break; + case 4: + kludge[0] = kludge[1] = kludge[2] = kludge[3] = + (srcp[0] & 0x0F); + pattern |= (pattern << 4); + break; + case 2: + kludge[0] = kludge[1] = kludge[2] = kludge[3] = + (srcp[0] & 0x03); + pattern |= (pattern << 2); + pattern |= (pattern << 4); + break; + default: /* case 1: */ + if(srcp[0] & 0x01) + pattern = 0xffffffff; + else + pattern = 0x00000000; + break; + } + + if(srcx) + pattern = (pattern >> srcx) | (pattern << (32 - srcx)); + pattern = reverse_bitorder(pattern); + + count = dwords; + while(count--) { + SET_PIX_TRANS_W(pattern); + SET_PIX_TRANS_W(*((unsigned short*)(&kludge[2]))); + } + if(PlusOne) + SET_PIX_TRANS_W(pattern); + + + srcy++; + srcp += srcwidth; + if (srcy >= stippleheight) { + srcy = 0; + srcp = src; + } + } + } else if(stipplewidth < 32) { + int width, offset; + register CARD32 pattern2; + register CARD32 pattern; + + while(h--) { + width = stipplewidth; + pattern = *((CARD32*)srcp) & ShiftMasks[width]; + while(!(width & ~15)) { + pattern |= (pattern << width); + width <<= 1; + } + pattern |= (pattern << width); + + offset = srcx; + + count = dwords; + while(count--) { + pattern2 = reverse_bitorder((pattern >> offset) | + (pattern << (width - offset))); + SET_PIX_TRANS_W(pattern2); + offset += 32; + while(offset >= width) + offset -= width; + SET_PIX_TRANS_W(pattern2 >> 16); + } + if(PlusOne) + SET_PIX_TRANS_W(reverse_bitorder((pattern >> offset) | + (pattern << (width - offset)))); + + srcy++; + srcp += srcwidth; + if (srcy >= stippleheight) { + srcy = 0; + srcp = src; + } + } + } else { + register CARD32* scratch; + register CARD32 pattern; + int shift, offset, scratch2; + + while(h--) { + count = dwords; + offset = srcx; + + while(count--) { + shift = stipplewidth - offset; + scratch = (CARD32*)(srcp + (offset >> 3)); + scratch2 = offset & 0x07; + + if(shift & ~31) { + if(scratch2) { + pattern = (*scratch >> scratch2) | + (*(scratch + 1) << (32 - scratch2)); + } else + pattern = *scratch; + } else { + pattern = (*((CARD32*)srcp) << shift) | + ((*scratch >> scratch2) & ShiftMasks[shift]); + } + pattern = reverse_bitorder(pattern); + SET_PIX_TRANS_W(pattern); + offset += 32; + while(offset >= stipplewidth) + offset -= stipplewidth; + SET_PIX_TRANS_W(pattern >> 16); + } + if(PlusOne) { + shift = stipplewidth - offset; + scratch = (CARD32*)(srcp + (offset >> 3)); + scratch2 = offset & 0x07; + + if(shift & ~31) { + if(scratch2) { + pattern = (*scratch >> scratch2) | + (*(scratch + 1) << (32 - scratch2)); + } else + pattern = *scratch; + } else { + pattern = (*((CARD32*)srcp) << shift) | + ((*scratch >> scratch2) & ShiftMasks[shift]); + } + SET_PIX_TRANS_W(reverse_bitorder(pattern)); + } + + srcy++; + srcp += srcwidth; + if (srcy >= stippleheight) { + srcy = 0; + srcp = src; + } + } + } + + } + + #endif + + static void + S3FillRectStippledCPUToScreenColorExpand(pDrawable, pGC, nBoxInit, pBoxInit) + DrawablePtr pDrawable; + GCPtr pGC; + int nBoxInit; /* number of rectangles to fill */ + BoxPtr pBoxInit; /* Pointer to first rectangle to fill */ + { + PixmapPtr pPixmap; /* Pixmap of the area to draw */ + int rectWidth; /* Width of the rect to be drawn */ + int rectHeight; /* Height of the rect to be drawn */ + BoxPtr pBox; /* current rectangle to fill */ + int nBox; /* Number of rectangles to fill */ + int xoffset, yoffset; + Bool AlreadySetup = FALSE; + + pPixmap = pGC->stipple; + + for (nBox = nBoxInit, pBox = pBoxInit; nBox > 0; nBox--, pBox++) { + + rectWidth = pBox->x2 - pBox->x1; + rectHeight = pBox->y2 - pBox->y1; + + if ((rectWidth > 0) && (rectHeight > 0)) { + if(!AlreadySetup) { + S3SetupForCPUToScreenColorExpand( + (pGC->fillStyle == FillStippled) ? -1 : pGC->bgPixel, + pGC->fgPixel, pGC->alu, pGC->planemask); + AlreadySetup = TRUE; + } + + xoffset = (pBox->x1 - (pGC->patOrg.x + pDrawable->x)) + % pPixmap->drawable.width; + if (xoffset < 0) + xoffset += pPixmap->drawable.width; + yoffset = (pBox->y1 - (pGC->patOrg.y + pDrawable->y)) + % pPixmap->drawable.height; + if (yoffset < 0) + yoffset += pPixmap->drawable.height; + #ifndef S3_NEWMMIO + if(!Transfer32) + S3FillStippledCPUToScreenColorExpand16( + pBox->x1, pBox->y1, rectWidth, rectHeight, + pPixmap->devPrivate.ptr, pPixmap->devKind, + pPixmap->drawable.width, pPixmap->drawable.height, + xoffset, yoffset); + else + #endif + S3FillStippledCPUToScreenColorExpand32( + pBox->x1, pBox->y1, rectWidth, rectHeight, + pPixmap->devPrivate.ptr, pPixmap->devKind, + pPixmap->drawable.width, pPixmap->drawable.height, + xoffset, yoffset); + } + } /* end for loop through each rectangle to draw */ + + } + + /***************************************\ + | Write Bitmap Replacement | + \***************************************/ + + + static void + S3WriteBitmapCPUToScreenColorExpand32(x, y, w, h, src, srcwidth, srcx, + srcy, bg, fg, rop, planemask) + int x, y, w, h; + unsigned char *src; + int srcwidth; + int srcx, srcy; + int bg, fg; + int rop; + unsigned int planemask; + { + unsigned char *srcp; + int dwords, shift; + register int count; + register CARD32* pattern; + + S3SetupForCPUToScreenColorExpand(bg, fg, rop, planemask); + + WaitQueue(4); + SET_CURPT((short)x, (short)y); + SET_AXIS_PCNT((short)w - 1, (short)h - 1); + + dwords = (w + 31) >> 5; + srcp = (srcwidth * srcy) + (srcx >> 3) + src; + + WaitIdle(); + SET_CMD(CMD_RECT | BYTSEQ | _32BIT | PCDATA | DRAW | PLANAR | + INC_Y | INC_X | WRTDATA); + + if(shift = srcx & 0x07) { + while(h--) { + count = dwords; + pattern = (CARD32*)srcp; + while(count--) { + SET_PIX_TRANS_L(reverse_bitorder((*pattern >> shift) | + (*(pattern + 1) << (32 - shift)))); + pattern++; + } + srcp += srcwidth; + } + } else { + while(h--) { + count = dwords; + pattern = (CARD32*)srcp; + while(count--) + SET_PIX_TRANS_L(reverse_bitorder(*(pattern++))); + srcp += srcwidth; + } + } + } + + #ifndef S3_NEWMMIO + + static + void S3WriteBitmapCPUToScreenColorExpand16(x, y, w, h, src, srcwidth, srcx, + srcy, bg, fg, rop, planemask) + int x, y, w, h; + unsigned char *src; + int srcwidth; + int srcx, srcy; + int bg, fg; + int rop; + unsigned int planemask; + { + unsigned char *srcp; + int dwords, count, shift; + register CARD32* pattern; + register CARD32 pattern2; + Bool PlusOne; + + S3SetupForCPUToScreenColorExpand(bg, fg, rop, planemask); + + WaitQueue(4); + SET_CURPT((short)x, (short)y); + SET_AXIS_PCNT((short)w - 1, (short)h - 1); + + dwords = (w + 15) >> 4; + PlusOne = (dwords & 0x01); + dwords >>= 1; + srcp = (srcwidth * srcy) + (srcx >> 3) + src; + + WaitIdle(); + SET_CMD(CMD_RECT | BYTSEQ | _16BIT | PCDATA | DRAW | PLANAR | + INC_Y | INC_X | WRTDATA); + + if((shift = srcx & 0x07)) { + while(h--) { + count = dwords; + pattern = (CARD32*)srcp; + while(count--) { + pattern2 = reverse_bitorder((*pattern >> shift) | + (*(pattern + 1) << (32 - shift))); + SET_PIX_TRANS_W(pattern2); + pattern++; + SET_PIX_TRANS_W(pattern2 >> 16); + } + if(PlusOne) + SET_PIX_TRANS_W(reverse_bitorder((*pattern >> shift) | + (*(pattern + 1) << (32 - shift)))); + srcp += srcwidth; + } + } else { + while(h--) { + count = dwords; + pattern = (CARD32*)srcp; + while(count--) { + pattern2 = reverse_bitorder(*(pattern++)); + SET_PIX_TRANS_W(pattern2); + SET_PIX_TRANS_W(pattern2 >> 16); + } + if(PlusOne) + SET_PIX_TRANS_W(reverse_bitorder(*(pattern))); + srcp += srcwidth; + } + } + } + + #endif + *** /dev/null Tue Jun 30 15:23:00 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/s3Bt485.h Fri Mar 6 16:53:03 1998 *************** *** 0 **** --- 1,85 ---- + /* $TOG: s3Bt485.h /main/1 1998/03/06 16:54:41 kaleb $ */ + + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/s3Bt485.h,v 1.1.2.1 1998/02/07 10:05:31 hohndel Exp $ */ + /* + * Copyright 1993 by David Wexelblat <dwex@XFree86.org> + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of David Wexelblat not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. David Wexelblat makes no representations + * about the suitability of this software for any purpose. It is provided + * "as is" without express or implied warranty. + * + * DAVID WEXELBLAT DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL DAVID WEXELBLAT BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + * + */ + + #include "compiler.h" + #include <X11/Xfuncproto.h> + + #define BT_WRITE_ADDR 0x00 + #define BT_RAMDAC_DATA 0x01 + #define BT_PIXEL_MASK 0x02 + #define BT_READ_ADDR 0x03 + #define BT_CURS_WR_ADDR 0x04 + #define BT_CURS_DATA 0x05 + #define BT_COMMAND_REG_0 0x06 + #define BT_CURS_RD_ADDR 0x07 + #define BT_COMMAND_REG_1 0x08 + #define BT_COMMAND_REG_2 0x09 + #define BT_STATUS_REG 0x0A + #define BT_CURS_RAM_DATA 0x0B + #define BT_CURS_X_LOW 0x0C + #define BT_CURS_X_HIGH 0x0D + #define BT_CURS_Y_LOW 0x0E + #define BT_CURS_Y_HIGH 0x0F + + _XFUNCPROTOBEGIN + + extern void s3OutBtReg( + #if NeedFunctionPrototypes + unsigned short, + unsigned char, + unsigned char + #endif + ); + + extern unsigned char s3InBtReg( + #if NeedFunctionPrototypes + unsigned short + #endif + ); + + extern void s3OutBtRegCom3( + #if NeedFunctionPrototypes + unsigned char, + unsigned char + #endif + ); + + extern unsigned char s3InBtRegCom3( + #if NeedFunctionPrototype + void + #endif + ); + + extern unsigned char s3InBtStatReg( + #if NeedFunctionPrototype + void + #endif + ); + + _XFUNCPROTOEND *** /dev/null Tue Jun 30 15:23:01 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/s3BtCursor.c Fri Mar 6 16:53:07 1998 *************** *** 0 **** --- 1,394 ---- + /* $TOG: s3BtCursor.c /main/1 1998/03/06 16:54:45 kaleb $ */ + + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/s3BtCursor.c,v 1.1.2.1 1998/02/07 10:05:35 hohndel Exp $ */ + /* + * Copyright 1993 by David Wexelblat <dwex@goblin.org> + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of David Wexelblat not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. David Wexelblat makes no representations + * about the suitability of this software for any purpose. It is provided + * "as is" without express or implied warranty. + * + * DAVID WEXELBLAT DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL DAVID WEXELBLAT BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + * + */ + + #define NEED_EVENTS + #include <X.h> + #include "Xproto.h" + #include <misc.h> + #include <input.h> + #include <cursorstr.h> + #include <regionstr.h> + #include <scrnintstr.h> + #include <servermd.h> + #include <windowstr.h> + #include "xf86.h" + #include "inputstr.h" + #include "xf86Priv.h" + #include "xf86_Option.h" + #include "xf86_OSlib.h" + #include "s3.h" + #include "s3reg.h" + #include "s3Bt485.h" + #include <mipointer.h> + + static unsigned short s3BtLowBits[] = { 0x3C8, 0x3C9, 0x3C6, 0x3C7 }; + static unsigned char s3BtYPosMask = 0xFF; + + /* + * Convert the cursor from server-format to hardware-format. The Bt485 + * has two planes, output sequentially. + */ + + #ifndef __GNUC__ + # define __inline__ /**/ + #endif + + /* + * The Bt485 has 16 command registers. The low-order two bits of the + * register address follow normal VGA DAC addressing conventions (which + * for some reason aren't in numeric order, so we remap them through + * an array). The S3 provides access to the two high-order bits via + * the two low-order bits of CR55. This is a fairly obnoxious way to + * go about doing this kind of thing, but it's not all that common + * an operation, so I don't feel too bad about wasting cycles. We + * can optimize it later, if need be. + */ + #if NeedFunctionPrototypes + void s3OutBtReg(unsigned short reg, unsigned char mask, unsigned char data) + #else + void s3OutBtReg(reg, mask, data) + unsigned short reg; + unsigned char mask; + unsigned char data; + #endif + { + unsigned char tmp; + unsigned char tmp1 = 0x00; + + /* High 2 bits of reg in CR55 bits 0-1 */ + outb(vgaCRIndex, 0x55); + tmp = inb(vgaCRReg) & 0xFC; + outb(vgaCRReg, tmp | ((reg & 0x0C) >> 2)); + + /* Have to map the low two bits to the correct DAC register */ + if (mask != 0x00) + tmp1 = inb(s3BtLowBits[reg & 0x03]) & mask; + outb(s3BtLowBits[reg & 0x03], tmp1 | data); + + /* Now clear 2 high-order bits so that other things work */ + outb(vgaCRReg, tmp); + } + + #if NeedFunctionPrototypes + unsigned char s3InBtReg(unsigned short reg) + #else + unsigned char s3InBtReg(reg) + unsigned short reg; + #endif + { + unsigned char tmp, ret; + + /* High 2 bits of reg in CR55 bits 0-1 */ + outb(vgaCRIndex, 0x55); + tmp = inb(vgaCRReg) & 0xFC; + outb(vgaCRReg, tmp | ((reg & 0x0C) >> 2)); + + /* Have to map the low two bits to the correct DAC register */ + ret = inb(s3BtLowBits[reg & 0x03]); + + /* Now clear 2 high-order bits so that other things work */ + outb(vgaCRReg, tmp); + + return(ret); + } + + /* + * The Command Register 3 register in the Bt485 must be accessed through + * a very odd sequence, as the older RAMDACs had already defined 16 + * registers. Apparently this overlays the Status register. + */ + #if NeedFunctionPrototypes + void s3OutBtRegCom3(unsigned char mask, unsigned char data) + #else + void s3OutBtRegCom3(mask, data) + unsigned char mask; + unsigned char data; + #endif + { + s3OutBtReg(BT_COMMAND_REG_0, 0x7F, 0x80); + s3OutBtReg(BT_WRITE_ADDR, 0x00, 0x01); + s3OutBtReg(BT_STATUS_REG, mask, data); + } + + unsigned char s3InBtRegCom3() + { + unsigned char ret; + + s3OutBtReg(BT_COMMAND_REG_0, 0x7F, 0x80); + s3OutBtReg(BT_WRITE_ADDR, 0x00, 0x01); + ret = s3InBtReg(BT_STATUS_REG); + return(ret); + } + + /* + * Status register may be hidden behind Command Register 3; need to check + * both possibilities. + */ + unsigned char s3InBtStatReg() + { + unsigned char tmp, ret; + + tmp = s3InBtReg(BT_COMMAND_REG_0); + if ((tmp & 0x80) == 0x80) { + /* Behind Command Register 3 */ + tmp = s3InBtReg(BT_WRITE_ADDR); + s3OutBtReg(BT_WRITE_ADDR, 0x00, 0x00); + ret = s3InBtReg(BT_STATUS_REG); + s3OutBtReg(BT_WRITE_ADDR, 0x00, tmp); + } else { + ret = s3InBtReg(BT_STATUS_REG); + } + return(ret); + } + + /* + * These three functions partition the work so it can be done more + * efficiently. + */ + static __inline__ void s3StartBtData(addr_reg, addr, data_reg) + unsigned short addr_reg; + unsigned char addr; + unsigned short data_reg; + { + unsigned char tmp; + + s3OutBtReg(addr_reg, 0x00, addr); + + /* High 2 bits of reg in CR55 bits 0-1 */ + outb(vgaCRIndex, 0x55); + tmp = inb(vgaCRReg) & 0xFC; + outb(vgaCRReg, tmp | ((data_reg & 0x0C) >> 2)); + } + static __inline__ void s3OutBtData(reg, data) + unsigned short reg; + unsigned char data; + { + /* Output data to RAMDAC */ + outb(s3BtLowBits[reg & 0x03], data); + } + static __inline__ void s3EndBtData() + { + unsigned char tmp; + + outb(vgaCRIndex, 0x55); + tmp = inb(vgaCRReg) & 0xFC; + outb(vgaCRReg, tmp); + } + + + void + s3BtShowCursor() + { + unsigned char tmp; + + UNLOCK_SYS_REGS; + + /* turn on external cursor */ + outb(vgaCRIndex, 0x55); + tmp = inb(vgaCRReg) & 0xDF; + outb(vgaCRReg, tmp | 0x20); + + /* Enable Bt485 */ + if(!S3_x64_SERIES(s3ChipId)) { + outb(vgaCRIndex, 0x45); + tmp = inb(vgaCRReg) & 0xDF; + outb(vgaCRReg, tmp | 0x20); + } + + /* Enable cursor mode 3 - X11 mode */ + s3OutBtReg(BT_COMMAND_REG_2, 0xFC, 0x03); + + LOCK_SYS_REGS; + } + + void + s3BtHideCursor() + { + UNLOCK_SYS_REGS; + + /* + * Don't need to undo the S3 registers here; they will be undone when + * the mode is restore from save registers. If it is done here, it + * causes the cursor to flash each time it is loaded, so don't do that. + */ + + /* Disable cursor */ + s3OutBtReg(BT_COMMAND_REG_2, 0xFC, 0x00); + + LOCK_SYS_REGS; + } + + void + s3BtSetCursorPosition(x, y, xorigin, yorigin) + int x, y, xorigin, yorigin; + { + x += 64 - xorigin; + /* Compensate for using Bt485 Cursor without pixel multiplexing. */ + if ((OFLG_ISSET(OPTION_STB_PEGASUS, &vga256InfoRec.options) || + OFLG_ISSET(OPTION_MIRO_MAGIC_S4, &vga256InfoRec.options)) && + !s3PixelMultiplexing) + x -= 2; + + if (vga256InfoRec.modes->Flags & V_DBLSCAN) + y <<= 1; + + y += 64 - yorigin; + + UNLOCK_SYS_REGS; + + /* Output position - "only" 12 bits of location documented */ + s3OutBtReg(BT_CURS_X_LOW, 0x00, x & 0xFF); + s3OutBtReg(BT_CURS_X_HIGH, 0x00, (x >> 8) & 0x0F); + s3OutBtReg(BT_CURS_Y_LOW, 0x00, y & s3BtYPosMask); + s3OutBtReg(BT_CURS_Y_HIGH, 0x00, (y >> 8) & 0x0F); + + LOCK_SYS_REGS; + return; + } + + void + s3BtSetCursorColors(bg, fg) + int bg, fg; + { + UNLOCK_SYS_REGS; + + /* Start writing at address 1 (0 is overscan color) */ + s3StartBtData(BT_CURS_WR_ADDR, 0x01, BT_CURS_DATA); + + /* Background color */ + if (s3DAC8Bit) { + s3OutBtData(BT_CURS_DATA, (bg & 0x00FF0000) >> 16); + s3OutBtData(BT_CURS_DATA, (bg & 0x0000FF00) >> 8); + s3OutBtData(BT_CURS_DATA, (bg & 0x000000FF)); + } else { + s3OutBtData(BT_CURS_DATA, (bg & 0x00FF0000) >> 18); + s3OutBtData(BT_CURS_DATA, (bg & 0x0000FF00) >> 10); + s3OutBtData(BT_CURS_DATA, (bg & 0x0000FF00) >> 2); + } + + /* Foreground color */ + if (s3DAC8Bit) { + s3OutBtData(BT_CURS_DATA, (fg & 0x00FF0000) >> 16); + s3OutBtData(BT_CURS_DATA, (fg & 0x0000FF00) >> 8); + s3OutBtData(BT_CURS_DATA, (fg & 0x000000FF)); + } else { + s3OutBtData(BT_CURS_DATA, (fg & 0x00FF0000) >> 18); + s3OutBtData(BT_CURS_DATA, (fg & 0x0000FF00) >> 10); + s3OutBtData(BT_CURS_DATA, (fg & 0x0000FF00) >> 2); + } + + /* Now clean up */ + s3EndBtData(); + + LOCK_SYS_REGS; + } + + void + s3BtLoadCursorImage(bits, xorigin, yorigin) + unsigned char *bits; + int xorigin, yorigin; + { + register int i, j; + unsigned char *p, *mask = bits + 1; + + UNLOCK_SYS_REGS; + + /* + * Bit 2 == 1 ==> 64x64 cursor; 2 low-order bits are extensions to the + * address register, and must be cleared since we're going to start + * writing data at address 0. + */ + s3OutBtRegCom3(0xF8, 0x04); + + if (vga256InfoRec.modes->Flags & V_INTERLACE) { + s3StartBtData(BT_WRITE_ADDR, 0x00, BT_CURS_RAM_DATA); + + for (i=0; i < 64; i++) { /* 64 rows in cursor */ + p = mask + (((i % 2) ? i-1 : i+1)*16); + for (j=0; j < 8; j++,p+=2) { /* 8 bytes per row */ + s3OutBtData(BT_CURS_RAM_DATA, *p); + } + } + for (i=0; i < 64; i++) { /* 64 rows in cursor */ + p = bits + (((i % 2) ? i-1 : i+1)*16); + for (j=0; j < 8; j++,p+=2) { /* 8 bytes per row */ + s3OutBtData(BT_CURS_RAM_DATA, *p); + } + } + + s3EndBtData(); + + s3BtYPosMask = 0xFE; + s3OutBtReg(BT_COMMAND_REG_2, 0xF7, 0x08); + } else if (vga256InfoRec.modes->Flags & V_DBLSCAN) { + s3StartBtData(BT_WRITE_ADDR, 0x00, BT_CURS_RAM_DATA); + + for (i=0; i < 32; i++) { /* 64 rows in cursor */ + p = mask + i * 16; + for (j=0; j < 8; j++,p+=2) { /* 8 bytes per row */ + s3OutBtData(BT_CURS_RAM_DATA, *p); + } + p = mask + i * 16; + for (j=0; j < 8; j++,p+=2) { /* 8 bytes per row */ + s3OutBtData(BT_CURS_RAM_DATA, *p); + } + } + for (i=0; i < 32; i++) { /* 64 rows in cursor */ + p = bits + i * 16; + for (j=0; j < 8; j++,p+=2) { /* 8 bytes per row */ + s3OutBtData(BT_CURS_RAM_DATA, *p); + } + p = bits + i * 16; + for (j=0; j < 8; j++,p+=2) { /* 8 bytes per row */ + s3OutBtData(BT_CURS_RAM_DATA, *p); + } + } + + s3EndBtData(); + + s3BtYPosMask = 0xFF; + s3OutBtReg(BT_COMMAND_REG_2, 0xF7, 0x00); + } else { + /* Start data output */ + s3StartBtData(BT_WRITE_ADDR, 0x00, BT_CURS_RAM_DATA); + + for (i = 0; i < 512; i++, mask+=2) + s3OutBtData(BT_CURS_RAM_DATA, *mask); + for (i = 0; i < 512; i++, bits+=2) + s3OutBtData(BT_CURS_RAM_DATA, *bits); + + s3EndBtData(); + + s3BtYPosMask = 0xFF; + s3OutBtReg(BT_COMMAND_REG_2, 0xF7, 0x00); + } + + LOCK_SYS_REGS; + + } *** /dev/null Tue Jun 30 15:23:01 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/s3cursor.c Fri Mar 6 16:53:41 1998 *************** *** 0 **** --- 1,339 ---- + /* $TOG: s3cursor.c /main/1 1998/03/06 16:55:19 kaleb $ */ + + + + + /* + * $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/s3cursor.c,v 1.1.2.2 1998/02/24 13:54:26 hohndel Exp $ + * + */ + + /* Written by Mark Vojkovich (mvojkovi@ucsd.edu) */ + + #define PSZ 8 + + #include "X.h" + #include "Xproto.h" + #include "misc.h" + #include "input.h" + #include "cursorstr.h" + #include "regionstr.h" + #include "scrnintstr.h" + #include "servermd.h" + #include "windowstr.h" + + #include "compiler.h" + #include "vga256.h" + #include "xf86.h" + #include "mipointer.h" + #include "xf86Priv.h" + #include "xf86_Option.h" + #include "xf86_OSlib.h" + #include "vga.h" + #include "xf86cursor.h" + + #define XCONFIG_FLAGS_ONLY + #include "xf86_Config.h" + + #include "s3.h" + #include "s3reg.h" + + extern void s3IBMRGBShowCursor(); + extern void s3IBMRGBHideCursor(); + extern void s3IBMRGBSetCursorPosition(); + extern void s3IBMRGBSetCursorColors(); + extern void s3IBMRGBLoadCursorImage(); + + extern void s3BtShowCursor(); + extern void s3BtHideCursor(); + extern void s3BtSetCursorPosition(); + extern void s3BtSetCursorColors(); + extern void s3BtLoadCursorImage(); + + extern void s3TiShowCursor(); + extern void s3TiHideCursor(); + extern void s3TiSetCursorPosition(); + extern void s3TiSetCursorColors(); + extern void s3TiLoadCursorImage(); + + extern void s3Ti3026ShowCursor(); + extern void s3Ti3026HideCursor(); + extern void s3Ti3026SetCursorPosition(); + extern void s3Ti3026SetCursorColors(); + extern void s3Ti3026LoadCursorImage(); + + static void s3ShowCursor(); + void s3HideCursor(); /* this is needed in EnterLeave for DGA... */ + static void s3SetCursorPosition(); + static void s3SetCursorColors(); + static void s3LoadCursorImage(); + + extern vgaHWCursorRec vgaHWCursor; + + extern Bool XAACursorInit(); + extern void XAARestoreCursor(); + extern void XAAWarpCursor(); + extern void XAAQueryBestSize(); + + static unsigned int CursorAddress; + + void S3CursorInit() + { + s3CursorBytes = 0; + + XAACursorInfoRec.MaxWidth = 64; + XAACursorInfoRec.MaxHeight = 64; + + if(DAC_IS_BT485_SERIES) { + XAACursorInfoRec.Flags = USE_HARDWARE_CURSOR | + HARDWARE_CURSOR_BIT_ORDER_MSBFIRST | + HARDWARE_CURSOR_TRUECOLOR_AT_8BPP | + HARDWARE_CURSOR_PROGRAMMED_ORIGIN | + HARDWARE_CURSOR_AND_SOURCE_WITH_MASK | + HARDWARE_CURSOR_CHAR_BIT_FORMAT | + HARDWARE_CURSOR_PROGRAMMED_BITS; + XAACursorInfoRec.SetCursorColors = s3BtSetCursorColors; + XAACursorInfoRec.SetCursorPosition = s3BtSetCursorPosition; + XAACursorInfoRec.LoadCursorImage = s3BtLoadCursorImage; + XAACursorInfoRec.HideCursor = s3BtHideCursor; + XAACursorInfoRec.ShowCursor = s3BtShowCursor; + ErrorF("%s %s: Using Bt485/att20c505 hardware cursor.\n", + XCONFIG_PROBED, vga256InfoRec.name); + } + else if(DAC_IS_IBMRGB) { + XAACursorInfoRec.Flags = USE_HARDWARE_CURSOR | + HARDWARE_CURSOR_TRUECOLOR_AT_8BPP | + HARDWARE_CURSOR_SOURCE_MASK_INTERLEAVE | + HARDWARE_CURSOR_AND_SOURCE_WITH_MASK | + HARDWARE_CURSOR_PROGRAMMED_ORIGIN | + HARDWARE_CURSOR_CHAR_BIT_FORMAT | + HARDWARE_CURSOR_PROGRAMMED_BITS; + XAACursorInfoRec.SetCursorColors = s3IBMRGBSetCursorColors; + XAACursorInfoRec.SetCursorPosition = s3IBMRGBSetCursorPosition; + XAACursorInfoRec.LoadCursorImage = s3IBMRGBLoadCursorImage; + XAACursorInfoRec.HideCursor = s3IBMRGBHideCursor; + XAACursorInfoRec.ShowCursor = s3IBMRGBShowCursor; + ErrorF("%s %s: Using IBM RGB_52x hardware cursor.\n", + XCONFIG_PROBED, vga256InfoRec.name); + } + else if(DAC_IS_TI3020_SERIES) { + XAACursorInfoRec.Flags = USE_HARDWARE_CURSOR | + HARDWARE_CURSOR_BIT_ORDER_MSBFIRST | + HARDWARE_CURSOR_TRUECOLOR_AT_8BPP | + HARDWARE_CURSOR_PROGRAMMED_ORIGIN | + HARDWARE_CURSOR_AND_SOURCE_WITH_MASK | + HARDWARE_CURSOR_CHAR_BIT_FORMAT | + HARDWARE_CURSOR_PROGRAMMED_BITS; + XAACursorInfoRec.SetCursorColors = s3TiSetCursorColors; + XAACursorInfoRec.SetCursorPosition = s3TiSetCursorPosition; + XAACursorInfoRec.LoadCursorImage = s3TiLoadCursorImage; + XAACursorInfoRec.HideCursor = s3TiHideCursor; + XAACursorInfoRec.ShowCursor = s3TiShowCursor; + ErrorF("%s %s: Using Ti3020/3025 hardware cursor.\n", + XCONFIG_PROBED, vga256InfoRec.name); + } else if(DAC_IS_TI3026 || DAC_IS_TI3030) { + XAACursorInfoRec.Flags = USE_HARDWARE_CURSOR | + HARDWARE_CURSOR_BIT_ORDER_MSBFIRST | + HARDWARE_CURSOR_TRUECOLOR_AT_8BPP | + HARDWARE_CURSOR_PROGRAMMED_ORIGIN | + HARDWARE_CURSOR_AND_SOURCE_WITH_MASK | + HARDWARE_CURSOR_CHAR_BIT_FORMAT | + HARDWARE_CURSOR_PROGRAMMED_BITS; + XAACursorInfoRec.SetCursorColors = s3Ti3026SetCursorColors; + XAACursorInfoRec.SetCursorPosition = s3Ti3026SetCursorPosition; + XAACursorInfoRec.LoadCursorImage = s3Ti3026LoadCursorImage; + XAACursorInfoRec.HideCursor = s3Ti3026HideCursor; + XAACursorInfoRec.ShowCursor = s3Ti3026ShowCursor; + ErrorF("%s %s: Using Ti3026/3030 hardware cursor.\n", + XCONFIG_PROBED, vga256InfoRec.name); + } else { /* generic S3 cursor */ + CursorAddress = (vga256InfoRec.videoRam - 1) << 10; + + if(CursorAddress < (vga256InfoRec.virtualY * s3BppDisplayWidth)) { + ErrorF("%s %s: Not enough video memory left for hardware cursor " + "storage... Disabling.\n", XCONFIG_PROBED, vga256InfoRec.name); + OFLG_SET(OPTION_SW_CURSOR, &vga256InfoRec.options); + return; + } + + XAACursorInfoRec.CursorDataX = + (CursorAddress % s3BppDisplayWidth) / s3Bpp; + XAACursorInfoRec.CursorDataY = CursorAddress / s3BppDisplayWidth; + s3CursorBytes = 1024; + CursorAddress >>= 10; + + + XAACursorInfoRec.Flags = USE_HARDWARE_CURSOR | + HARDWARE_CURSOR_PROGRAMMED_ORIGIN | + HARDWARE_CURSOR_BIT_ORDER_MSBFIRST | + HARDWARE_CURSOR_SHORT_BIT_FORMAT; + XAACursorInfoRec.SetCursorColors = s3SetCursorColors; + XAACursorInfoRec.SetCursorPosition = s3SetCursorPosition; + XAACursorInfoRec.HideCursor = s3HideCursor; + XAACursorInfoRec.ShowCursor = s3ShowCursor; + XAACursorInfoRec.GetInstalledColormaps = vgaGetInstalledColormaps; + + ErrorF("%s %s: Using built-in S3 hardware cursor.\n", + XCONFIG_PROBED, vga256InfoRec.name); + } + + if(XAACursorInfoRec.Flags & USE_HARDWARE_CURSOR) { + vgaHWCursor.Init = XAACursorInit; + vgaHWCursor.Initialized = TRUE; + vgaHWCursor.Restore = XAARestoreCursor; + vgaHWCursor.Warp = XAAWarpCursor; + vgaHWCursor.QueryBestSize = XAAQueryBestSize; + } + } + + + void + s3ShowCursor() + { + unsigned char tmp; + + UNLOCK_SYS_REGS; + + outb(vgaCRIndex, 0x55); + tmp = inb(vgaCRReg); + outb(vgaCRReg, tmp | 0x10); + + outb(vgaCRIndex, 0x4c); + outb(vgaCRReg, CursorAddress >> 8); + outb(vgaCRIndex, 0x4d); + outb(vgaCRReg, CursorAddress); + + outb(vgaCRIndex, 0x45); + tmp = inb(vgaCRReg); + outb(vgaCRReg, tmp | 0x01); + + LOCK_SYS_REGS; + } + + + void + s3HideCursor() + { + unsigned char tmp; + + UNLOCK_SYS_REGS; + + outb(vgaCRIndex, 0x45); + tmp = inb(vgaCRReg); + outb(vgaCRReg, tmp & ~0x01); + + LOCK_SYS_REGS; + } + + + void + s3SetCursorPosition(x, y, xoff, yoff) + int x, y, xoff, yoff; + { + UNLOCK_SYS_REGS; + + if (!S3_TRIOxx_SERIES(s3ChipId)) { + if (S3_968_SERIES(s3ChipId)) + x *= (2 * s3Bpp); + else if (!S3_x64_SERIES(s3ChipId) && !S3_805_I_SERIES(s3ChipId)) + x *= s3Bpp; + else if (s3Bpp > 2) + x *= 2; + } + + if (vga256InfoRec.modes->Flags & V_DBLSCAN) + y *= 2; + + outb(vgaCRIndex, 0x46); + outb(vgaCRReg, x >> 8); + + outb(vgaCRIndex, 0x47); + outb(vgaCRReg, x); + + outb(vgaCRIndex, 0x49); + outb(vgaCRReg, y); + + outb(vgaCRIndex, 0x4e); + outb(vgaCRReg, xoff); + + outb(vgaCRIndex, 0x4f); + outb(vgaCRReg, yoff); + + outb(vgaCRIndex, 0x48); + outb(vgaCRReg, y >> 8); + + LOCK_SYS_REGS; + + } + + void + s3SetCursorColors(bg, fg) + unsigned int bg, fg; + { + unsigned short packfg, packbg; + + switch(s3Bpp) { + case 1: + if(S3_TRIOxx_SERIES(s3ChipId)) { + outb(vgaCRIndex, 0x45); + inb(vgaCRReg); /* reset stack pointer */ + outb(vgaCRIndex, 0x4A); + outb(vgaCRReg, fg); + outb(vgaCRReg, fg); + + outb(vgaCRIndex, 0x45); + inb(vgaCRReg); /* reset stack pointer */ + outb(vgaCRIndex, 0x4B); + outb(vgaCRReg, bg); + outb(vgaCRReg, bg); + } else { + outb(vgaCRIndex, 0x0E); + outb(vgaCRReg, fg); + outb(vgaCRIndex, 0x0F); + outb(vgaCRReg, bg); + } + break; + case 2: + if(vga256InfoRec.depth == 15) { + packfg = ((fg & 0x00F80000) >> 19) | ((fg & 0x0000F800) >> 6) | + ((fg & 0x000000F8) << 7); + packbg = ((bg & 0x00F80000) >> 19) | ((bg & 0x0000F800) >> 6) | + ((bg & 0x000000F8) << 7); + } else { + packfg = ((fg & 0x00F80000) >> 19) | ((fg & 0x0000Fc00) >> 5) | + ((fg & 0x000000F8) << 8); + packbg = ((bg & 0x00F80000) >> 19) | ((bg & 0x0000Fc00) >> 5) | + ((bg & 0x000000F8) << 8); + } + + outb(vgaCRIndex, 0x45); + inb(vgaCRReg); /* reset stack pointer */ + outb(vgaCRIndex, 0x4A); + outb(vgaCRReg, packfg); + outb(vgaCRReg, packfg >> 8); + + outb(vgaCRIndex, 0x45); + inb(vgaCRReg); /* reset stack pointer */ + outb(vgaCRIndex, 0x4B); + outb(vgaCRReg, packbg); + outb(vgaCRReg, packbg >> 8); + break; + default: + outb(vgaCRIndex, 0x45); + inb(vgaCRReg); /* reset stack pointer */ + outb(vgaCRIndex, 0x4A); + outb(vgaCRReg, (fg & 0x00FF0000) >> 16); + outb(vgaCRReg, (fg & 0x0000FF00) >> 8); + outb(vgaCRReg, (fg & 0x000000FF)); + + outb(vgaCRIndex, 0x45); + inb(vgaCRReg); /* reset stack pointer */ + outb(vgaCRIndex, 0x4B); + outb(vgaCRReg, (bg & 0x00FF0000) >> 16); + outb(vgaCRReg, (bg & 0x0000FF00) >> 8); + outb(vgaCRReg, (bg & 0x000000FF)); + break; + } + } + + *** /dev/null Tue Jun 30 15:23:02 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/s3ELSA.c Fri Mar 6 16:53:11 1998 *************** *** 0 **** --- 1,425 ---- + /* $TOG: s3ELSA.c /main/1 1998/03/06 16:54:48 kaleb $ */ + + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/s3ELSA.c,v 1.1.2.1 1998/02/07 10:05:36 hohndel Exp $ */ + /* + * s3ELSA.c + * + * compile standalone program with + * + rm -f s3ELSA.o + make DEFINES=-DELSA_MAIN "LDLIBS=../../os-support/libxf86_os.a" s3ELSA + rm -f s3ELSA.o + * + * + */ + + #ifdef linux + #include <stdlib.h> + #endif + + #include "s3.h" + #include "s3ELSA.h" + #include "xf86_OSlib.h" + + #ifdef ELSA_MAIN + #include <stdio.h> + #ifdef linux + #include <unistd.h> + #endif /* linux */ + #ifndef SVR4 + #include <getopt.h> + #endif /* SVR4 */ + #ifdef xalloc + #undef xalloc + #endif + #define xalloc(_p) malloc(_p) + #ifdef xrealloc + #undef xrealloc + #endif + #define xrealloc(_o,_s) realloc(_o,_s) + #ifdef xfree + #undef xfree + #endif + #define xfree(_p) free(_p) + #endif /* ELSA_MAIN */ + + + #define BIOS_BSIZE 512 + #define BIOS_BASE 0xc0000 + + + elsa_board_types_t elsa_board_types[] = { + ELSA_WINNER_1000, "ELSA Winner 1000", 0, + ELSA_WINNER_1000VL, "ELSA Winner 1000VL", 0, + ELSA_WINNER_1000PCI, "ELSA Winner 1000PCI", 0, + ELSA_WINNER_1000ISA, "ELSA Winner 1000ISA", 0, + ELSA_WINNER_2000, "ELSA Winner 2000", 0, + ELSA_WINNER_2000VL, "ELSA Winner 2000VL", 0, + ELSA_WINNER_2000PCI, "ELSA Winner 2000PCI", 0, + ELSA_WINNER_1000PRO, "ELSA Winner 1000PRO", 0, + ELSA_WINNER_1000PRO_TRIO32, "ELSA Winner 1000PRO Trio32", 0, + ELSA_WINNER_1000PRO_TRIO64, "ELSA Winner 1000PRO Trio64", 0, + ELSA_WINNER_1000AVI, "ELSA Winner 1000AVI", 0, + ELSA_WINNER_1000PRO_X, "ELSA Winner 1000PRO/X", 0, + ELSA_WINNER_2000PRO, "ELSA Winner 2000PRO", 0, + ELSA_WINNER_2000PRO_X, "ELSA Winner 2000PRO/X", 0, + ELSA_WINNER_2000AVI, "ELSA Winner 2000AVI", 0, + ELSA_WINNER_2000PRO_X8, "ELSA Winner 2000PRO/X-8", 0, + ELSA_GLORIA_4, "ELSA Gloria-4", 0, + ELSA_GLORIA_8, "ELSA Gloria-8", 0, + 0, 0, 0 + }; + + + static __inline__ void shift_out(int b) { + int i,j; + outb(0x3d4,0x5c); i = (inb(0x3d5) & 0xaf) | ((b)?0x10:0x00); + j = i; + outb(0x3d5,j); outb(0x3d5,j); outb(0x3d5,j); outb(0x3d5,j); + j = i | 0x40; + outb(0x3d5,j); outb(0x3d5,j); outb(0x3d5,j); outb(0x3d5,j); + } + + static __inline__ int shift_in() + { + int i,j; + outb(0x3d4,0x5c); i = inb(0x3d5) & 0xaf; + j = i; + outb(0x3d5,j); outb(0x3d5,j); outb(0x3d5,j); outb(0x3d5,j); + j = i | 0x40; + outb(0x3d5,j); outb(0x3d5,j); outb(0x3d5,j); outb(0x3d5,j); + return (inb(0x3c2) & 0x10) != 0; + } + + static int read_eeprom_byte(int r) + { + int i,j; + + outb(0x3d4,0x5c); i = inb(0x3d5) | 0x20; outb(0x3d5,i); + outb(0x3d5,i); outb(0x3d5,i); outb(0x3d5,i); + + shift_out(1); + shift_out(1); + shift_out(0); + + for(i=5; i>=0; i--) + shift_out((r>>i) & 1); + + #if 0 + shift_out(0); + #endif + + j=0; + for(i=0; i<16; i++) + j = (j<<1) | shift_in(); + + outb(0x3d4,0x5c); i = inb(0x3d5) & ~0x20; outb(0x3d5,i); + outb(0x3d5,i); outb(0x3d5,i); outb(0x3d5,i); + + return j; + } + + + static int read_eeprom_data(unsigned short **pdata) + { + int i; + int sr01, cr45, cr50, cr55, cr5c; + int ndata=6; + unsigned short *data; + elsa_eeprom_data_t *eedata; + + #ifdef ELSA_MAIN + #ifdef linux + iopl(3); + #endif + #endif + + outb(0x3d4,0x38); outb(0x3d5,0x48); + outb(0x3d4,0x39); outb(0x3d5,0xa5); + + outb(0x3c4,0x01); sr01 = inb(0x3c5); + outb(0x3d4,0x45); cr45 = inb(0x3d5); + outb(0x3d4,0x50); cr50 = inb(0x3d5); + outb(0x3d4,0x55); cr55 = inb(0x3d5); + outb(0x3d4,0x5c); cr5c = inb(0x3d5); + + + outb(0x3c4,0x01); i = inb(0x3c5) | 0x20; outb(0x3c5,i); + outb(0x3d4,0x45); i = inb(0x3d5) & ~0x20; outb(0x3d5,i); + outb(0x3d4,0x50); i = inb(0x3d5) & ~0x04; outb(0x3d5,i); + outb(0x3d4,0x55); i = inb(0x3d5) & ~0x20; outb(0x3d5,i); + outb(0x3d4,0x5c); i = inb(0x3d5) | 0x80; outb(0x3d5,i); + outb(0x3d5,i); outb(0x3d5,i); outb(0x3d5,i); + + for(i=0; i<64; i++) + shift_out(0); + + data = (unsigned short*) xalloc(ndata*sizeof(unsigned short)); + + for (i=0; i<ndata; i++) + data[i] = read_eeprom_byte(i); + + eedata = (elsa_eeprom_data_t *) data; + + if (eedata->wnr_type == ('S' | '3'<<8)) { + if (eedata->eeprom_size > ndata) { + ndata = eedata->eeprom_size; + data = (unsigned short*) xrealloc(data, ndata*sizeof(unsigned short)); + for (; i<ndata; i++) + data[i] = read_eeprom_byte(i); + } + } + + outb(0x3d4,0x5c); outb(0x3d5,cr5c); + outb(0x3d4,0x55); outb(0x3d5,cr55); + outb(0x3d4,0x50); outb(0x3d5,cr50); + outb(0x3d4,0x45); outb(0x3d5,cr45); + outb(0x3c4,0x01); outb(0x3c5,sr01); + + #if 0 + outb(0x3d4,0x39); outb(0x3d5,0x00); + outb(0x3d4,0x38); outb(0x3d5,0x00); + #endif + + #ifdef ELSA_MAIN + #ifdef linux + iopl(0); + #endif + #endif + + eedata = (elsa_eeprom_data_t *) data; + if (eedata->wnr_type == ('S' | '3'<<8)) { + *pdata = data; + } + else { + xfree(data); + ndata = -1; + } + return ndata; + } + + static int calc_crc16(int ndata, unsigned short *data) + { + int i,j,s,crc16; + unsigned short d; + + crc16 = 0; + for(i=1; i<ndata; i++) { + d = data[i]; + for (j=0; j<16; j++) { + s = (crc16>>1) + (crc16>>14) + (crc16>>15) + d + 1; + crc16 = (crc16<<1) | (s&1); + d >>= 1; + } + } + return crc16; + } + + static int check_ELSA_bios(int BIOSbase) + { + unsigned char bios[BIOS_BSIZE]; + char *match = " ELSA GmbH"; + int i,l; + + if (xf86ReadBIOS(BIOSbase, 0, bios, BIOS_BSIZE) != BIOS_BSIZE) + return -1; + + if ((bios[0] != 0x55) || (bios[1] != 0xaa)) + return -2; + + l = strlen(match); + for (i=0; i<BIOS_BSIZE-l; i++) + if (bios[i] == match[0] && !memcmp(&bios[i],match,l)) + return 1; + return 0; + } + + + #ifdef ELSA_MAIN + + void ErrorF(char *s, ...) + { + } + + void main() + { + int i; + int ndata; + unsigned short *data; + unsigned short crc16; + elsa_eeprom_data_t *eedata; + elsa_eeprom_timing_t *eetim; + unsigned long serno; + + if (check_ELSA_bios(BIOS_BASE) <= 0) { + printf("no ELSA Bios detected\n"); + exit(1); + } + + ndata = read_eeprom_data(&data); + if (ndata<0) { + printf("no ELSA Winner card detected\n"); + exit(1); + } + + crc16 = calc_crc16(ndata,data); + eedata = (elsa_eeprom_data_t *) data; + + + printf("EEPROM size %d bytes\n",ndata); + if (eedata->crc16 == crc16) + printf("CRC ok (%04x)\n",crc16); + else + printf("CRC not ok (%04x != %04x)\n",eedata->crc16,crc16); + printf("Chip type %s\n" + ,(eedata->wnr_type == 'S' | '3'<<8) ? "S3" : "unknown"); + for (i=0; elsa_board_types[i].code; i++) + if (elsa_board_types[i].code == eedata->board_code) break; + if (elsa_board_types[i].code) + printf("%s\n",elsa_board_types[i].name); + else + printf("unknown ELSA board code %x, please report\n", eedata->board_code); + + serno = (eedata->serno_h<<16) | eedata->serno_l; + printf("Ser.No. %c-%04ld.%03ld.%03ld\n", + (char)('A' + ((serno>>27) & 0x0f)), + ((serno>>17) & 0x3ff) | ((serno>>21) & 0x400), + (serno & 0x1ffff) / 1000, + (serno & 0x1ffff) % 1000); + printf("max pixel clock %7.3f MHz\n" + ,(eedata->max_pixclock,eedata->max_pixclock*4)/1000.0); + printf("max memory clock %7.3f MHz\n" + ,(eedata->max_memclock,eedata->max_memclock*4)/1000.0); + printf("monitor size %d %d\n",eedata->xsize,eedata->ysize); + printf("software version %d\n",eedata->sw_vers); + printf("hardware config %d\n",eedata->hw_conf); + + for (i= 26; i<ndata-9; i+=9) { + eetim = (elsa_eeprom_timing_t *) (data + i); + #if 0 + printf("\ntiming %d:\n",i); + printf("\tbpp %d\n",ELSA_TIM_bpp(*eetim)); + printf("\txres %d\n",ELSA_TIM_xres(*eetim)); + printf("\tyres %d\n",ELSA_TIM_yres(*eetim)); + printf("\tpixfrq %1.3f MHz\n",(ELSA_TIM_pixfrq4(*eetim)*4)/1000.0); + + printf("\tflags %d\n",ELSA_TIM_flags(*eetim)); + printf("\thtot %d\n",ELSA_TIM_htot(*eetim)); + printf("\thfp %d\n",ELSA_TIM_hfp(*eetim)); + printf("\thsw %d\n",ELSA_TIM_hsw(*eetim)); + printf("\tvtot %d\n",ELSA_TIM_vtot(*eetim)); + printf("\tvfp %d\n",ELSA_TIM_vfp(*eetim)); + printf("\tvsw %d\n",ELSA_TIM_vsw(*eetim)); + #endif + if (ELSA_ET_VM_VALID(eetim)) + printf("\"%dx%dx%d\" \t %7.3f %4d %4d %4d %4d %4d %4d %4d %4d\n" + ,ELSA_TIM_xres(*eetim),ELSA_TIM_yres(*eetim),ELSA_TIM_bpp(*eetim) + ,(ELSA_TIM_pixfrq4(*eetim)*4)/1000.0 + ,ELSA_TIM_xres(*eetim) + ,ELSA_TIM_xres(*eetim)+ELSA_TIM_hfp(*eetim) + ,ELSA_TIM_xres(*eetim)+ELSA_TIM_hfp(*eetim)+ELSA_TIM_hsw(*eetim) + ,ELSA_TIM_htot(*eetim) + ,ELSA_TIM_yres(*eetim) + ,ELSA_TIM_yres(*eetim)+ELSA_TIM_vfp(*eetim) + ,ELSA_TIM_yres(*eetim)+ELSA_TIM_vfp(*eetim)+ELSA_TIM_vsw(*eetim) + ,ELSA_TIM_vtot(*eetim) + ); + } + xfree(data); + } + + #else + int s3DetectELSA(int BIOSbase, char **pcard, char **pserno, + int *max_pix_clock, int *max_mem_clock, int *hwconfig, + char **modes) + { + int i; + int ndata; + unsigned short *data; + unsigned short crc16; + elsa_eeprom_data_t *eedata; + elsa_eeprom_timing_t *eetim; + unsigned long serno; + + if (check_ELSA_bios(BIOSbase>0 ? BIOSbase : BIOS_BASE) <= 0) { + return -1; + } + + ndata = read_eeprom_data(&data); + if (ndata<0) + return -2; + + crc16 = calc_crc16(ndata,data); + eedata = (elsa_eeprom_data_t *) data; + + if (eedata->crc16 != crc16) { + xfree(data); + return -3; + } + + if (eedata->wnr_type != ('S' | '3'<<8)) { + xfree(data); + return -4; + } + + for (i=0; elsa_board_types[i].code; i++) + if (elsa_board_types[i].code == eedata->board_code) break; + + if (pcard) { + *pcard = (char*) xalloc(80); + if (elsa_board_types[i].code) + ErrorF(*pcard,"%s detected",elsa_board_types[i].name); + else + ErrorF(*pcard,"unknown ELSA Winner board code %04x detected, please report\n" + , eedata->board_code); + } + + if (modes) { + char *p; + p = *modes = (char*) xalloc(80 * ((ndata-9-26)/9 +1)); + *p = '\0'; + for (i= 26; i<ndata-9; i+=9) { + eetim = (elsa_eeprom_timing_t *) (data + i); + if (ELSA_ET_VM_VALID(eetim)) + ErrorF(p,"\t\"%dx%dx%d\" \t %7.3f %4d %4d %4d %4d %4d %4d %4d %4d\n" + ,ELSA_TIM_xres(*eetim),ELSA_TIM_yres(*eetim),ELSA_TIM_bpp(*eetim) + ,(ELSA_TIM_pixfrq4(*eetim)*4)/1000.0 + ,ELSA_TIM_xres(*eetim) + ,ELSA_TIM_xres(*eetim)+ELSA_TIM_hfp(*eetim) + ,ELSA_TIM_xres(*eetim)+ELSA_TIM_hfp(*eetim)+ELSA_TIM_hsw(*eetim) + ,ELSA_TIM_htot(*eetim) + ,ELSA_TIM_yres(*eetim) + ,ELSA_TIM_yres(*eetim)+ELSA_TIM_vfp(*eetim) + ,ELSA_TIM_yres(*eetim)+ELSA_TIM_vfp(*eetim)+ELSA_TIM_vsw(*eetim) + ,ELSA_TIM_vtot(*eetim) + ); + p += strlen(p); + } + } + + if (pserno) { + *pserno = (char*) xalloc(20); + serno = (eedata->serno_h<<16) | eedata->serno_l; + ErrorF(*pserno,"%c-%04ld.%03ld.%03ld", + (char)('A' + ((serno>>27) & 0x0f)), + ((serno>>17) & 0x3ff) | ((serno>>21) & 0x400), + (serno & 0x1ffff) / 1000, + (serno & 0x1ffff) % 1000); + } + + if (max_pix_clock) + *max_pix_clock = eedata->max_pixclock * 4; + if (max_mem_clock) + *max_mem_clock = eedata->max_memclock * 4; + if (hwconfig) + *hwconfig = eedata->hw_conf; + + i = eedata->board_code; + xfree(data); + return i; + } + + #endif *** /dev/null Tue Jun 30 15:23:03 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/s3ELSA.h Fri Mar 6 16:53:15 1998 *************** *** 0 **** --- 1,133 ---- + /* $TOG: s3ELSA.h /main/1 1998/03/06 16:54:52 kaleb $ */ + + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/s3ELSA.h,v 1.1.2.1 1998/02/07 10:05:36 hohndel Exp $ */ + + + /* + * + * Copyright 1995-1997 The XFree86 Project, Inc. + * + */ + + #ifndef _S3ELSA_H_ + #define _S3ELSA_H_ + + #define ELSA_WINNER_1000 0x910 + #define ELSA_WINNER_1000VL 0x912 + #define ELSA_WINNER_1000PCI 0x914 + #define ELSA_WINNER_1000ISA 0x91A + #define ELSA_WINNER_2000 0x920 + #define ELSA_WINNER_2000VL 0x922 + #define ELSA_WINNER_2000PCI 0x924 + #define ELSA_WINNER_1000PRO 0x930 + #define ELSA_WINNER_1000PRO_TRIO32 0x931 + #define ELSA_WINNER_1000PRO_TRIO64 0x932 + #define ELSA_WINNER_1000AVI 0x936 + #define ELSA_WINNER_1000PRO_X 0x937 + #define ELSA_WINNER_2000PRO 0x940 + #define ELSA_WINNER_2000PRO_X 0x942 + #define ELSA_WINNER_2000AVI 0x943 + #define ELSA_WINNER_2000PRO_X8 0x94a + #define ELSA_GLORIA_4 0x980 + #define ELSA_GLORIA_8 0x981 + + typedef struct { + unsigned short code; + char *name; + long *flags; + } elsa_board_types_t; + + extern elsa_board_types_t elsa_board_types[]; + + /* structure to hold timing/mode info read from EEROM + */ + + typedef struct { + unsigned short + crc16, + wnr_type, /* 0x3353 ("S3") */ + board_code, + serno_l, /* low word */ + serno_h, /* high word */ + eeprom_size, /* EEROM size in words */ + hw_conf, /* reserved */ + max_pixclock, /* max pixel clock [MHz] / 4000 */ + max_memclock, /* max memory clock [MHz] / 4000 */ + vmode0, /* reserved */ + key_word, /* reserved */ + xsize, /* monitor size in mm */ + ysize, + sw_vers; /* currently 1 */ + } elsa_eeprom_data_t; + + + typedef struct { + unsigned short + bpp_xres4, /* bpp (6bit) + xres/4 (10bit) */ + fl_yres, /* flags (4bit) + yres (12bit) */ + pixfrq4, /* pixel clock frequency in kHz / 4 (16bit) */ + hfph_htot, /* hor-frontporch-hi4bit + hor-total (12bit) */ + hfpl_hsw, /* hor-frontporch-lo6bit + hor-syncwidth (10bit) */ + vfph_vtot, /* ver-frontporch-hi4bit + ver-total (12bit) */ + vfpl_vsw, /* ver-frontporch-lo6bit + ver-syncwidth (10bit) */ + res1, /* reserved */ + res2; /* reserved */ + } elsa_eeprom_timing_t; + + + + /* how to make the fields in this struct */ + + #define ELSA_TIM_bx(_bpp_, _xres_) (ushort) ((_bpp_) << 10 | (_xres_) / 4) + #define ELSA_TIM_fy(_flags_, _yres_) (ushort) ((_flags_) << 12 | _yres_) + #define ELSA_TIM_fp(_pixfreq_) (ushort) ((_pixfreq_) / 4) + #define ELSA_TIM_h1(_hfp_, _htot_) (ushort) (((_hfp_) & 0x3c0) << 6 | (_htot_)) + #define ELSA_TIM_h2(_hfp_, _hsw_) (ushort) (((_hfp_) & 0x03f) << 10 | (_hsw_)) + #define ELSA_TIM_v1(_vfp_, _vtot_) (ushort) (((_vfp_) & 0x3c0) << 6 | (_vtot_)) + #define ELSA_TIM_v2(_vfp_, _vsw_) (ushort) (((_vfp_) & 0x03f) << 10 | (_vsw_)) + + + /* how to extract info from this struct */ + + #define ELSA_TIM_bpp(et) (((et).bpp_xres4 & 0xfc00) >> 10) + #define ELSA_TIM_xres(et) (((et).bpp_xres4 & 0x03ff) * 4) + #define ELSA_TIM_flags(et) (((et).fl_yres & 0xf000) >> 12) + #define ELSA_TIM_yres(et) ((et).fl_yres & 0x0fff) + #define ELSA_TIM_pixfrq4(et) ((et).pixfrq4) + #define ELSA_TIM_htot(et) ((et).hfph_htot & 0x0fff) + #define ELSA_TIM_hfp(et) ((((et).hfph_htot & 0xf000) >> 6) | (((et).hfpl_hsw & 0xfc00) >> 10)) + #define ELSA_TIM_hsw(et) ((et).hfpl_hsw & 0x03ff) + #define ELSA_TIM_vtot(et) ((et).vfph_vtot & 0x0fff) + #define ELSA_TIM_vfp(et) ((((et).vfph_vtot & 0xf000) >> 6) | (((et).vfpl_vsw & 0xfc00) >> 10)) + #define ELSA_TIM_vsw(et) ((et).vfpl_vsw & 0x03ff) + + + + /* Macro to check validity of timing data */ + + #define ELSA_ET_VM_VALID(pet) ( \ + (pet)->bpp_xres4 != 0xFFFF && ((pet)->bpp_xres4 & 0x3FF) >= 16/4 && \ + (pet)->fl_yres != 0xFFFF && ((pet)->fl_yres & 0xFFF) >= 16 && \ + (pet)->pixfrq4 != 0xFFFF && (pet)->pixfrq4 ) + + + _XFUNCPROTOBEGIN + + extern int s3DetectELSA( + #if NeedFunctionPrototypes + int BIOSbase, + char **pcard, + char **pserno, + int *max_pix_clock, + int *max_mem_clock, + int *hwconf, + char **modes + #endif + ); + + _XFUNCPROTOEND + + #endif /* _S3ELSA_H_ */ *** /dev/null Tue Jun 30 15:23:04 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/s3fbinit.c Fri Mar 6 16:53:49 1998 *************** *** 0 **** --- 1,269 ---- + /* $TOG: s3fbinit.c /main/1 1998/03/06 16:55:27 kaleb $ */ + + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/s3fbinit.c,v 1.1.2.1 1998/02/07 10:05:41 hohndel Exp $ */ + /* + * + * Copyright 1995-1997 The XFree86 Project, Inc. + * + */ + #define USE_VGAHWINIT + + #include "X.h" + #include "Xmd.h" + #include "input.h" + #include "servermd.h" + #include "scrnintstr.h" + #include "site.h" + + #include "xf86Procs.h" + #include "xf86_OSlib.h" + #include "xf86_HWlib.h" + #include "vga.h" + + #include "s3.h" + #include "s3reg.h" + #include "s3Bt485.h" + #define S3_SERVER + #include "Ti302X.h" + #include "IBMRGB.h" + #define XCONFIG_FLAGS_ONLY + #include "xf86_Config.h" + + + extern int nonMuxMaxClock; + extern int pixMuxMinClock; + + + /* + * S3FbInit -- + * + * This function is different in that some stuff seemingly more + * suitable for the Probe function is in here, but that is only + * because it had to wait until after the modelines were validated + * or the width was determined etc... + * + * MArk. + * + */ + + + void S3FbInit(void) + { + int i; + + #ifdef S3_DEBUG + ErrorF("In S3FbInit()\n"); + #endif + + /**********************************************************************\ + | Adjust vga256InfoRec.clock[] when not using a programable clock chip | + \**********************************************************************/ + /* This had to wait until after the clocks were setup (MArk). */ + + if (!OFLG_ISSET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions)) { + Bool clocksChanged = FALSE; + Bool numClocksChanged = FALSE; + int newNumClocks = vga256InfoRec.clocks; + + + /* New rules if we don't have a programmable clock ?*/ + if (S3_864_SERIES(s3ChipId)) + nonMuxMaxClock = 95000; + else if (S3_805_I_SERIES(s3ChipId)) + nonMuxMaxClock = 90000; + + /* Clock Modifications for some RAMDACs */ + for (i = 0; i < vga256InfoRec.clocks; i++) { + switch(s3RamdacType) { + case ATT20C498_DAC: + case ATT22C498_DAC: + case STG1700_DAC: + case STG1703_DAC: + switch (s3Bpp) { + case 1: + if (!numClocksChanged) { + newNumClocks = 32; + numClocksChanged = TRUE; + clocksChanged = TRUE; + for(i = vga256InfoRec.clocks; i < newNumClocks; i++) + vga256InfoRec.clock[i] = 0; + if (vga256InfoRec.clocks > 16) + vga256InfoRec.clocks = 16; + } + if (vga256InfoRec.clock[i] * 2 > pixMuxMinClock && + vga256InfoRec.clock[i] * 2 <= vga256InfoRec.dacSpeeds[0]) + vga256InfoRec.clock[i + 16] = vga256InfoRec.clock[i] * 2; + else + vga256InfoRec.clock[i + 16] = 0; + if (vga256InfoRec.clock[i] > nonMuxMaxClock) + vga256InfoRec.clock[i] = 0; + break; + case 4: + vga256InfoRec.clock[i] /= 2; + clocksChanged = TRUE; + break; + } + break; + case ATT20C490_DAC: + case SS2410_DAC: + case SC1148x_DAC: + case TI3020_DAC: + case SC15025_DAC: + if (s3Bpp > 1) { + vga256InfoRec.clock[i] /= s3Bpp; + clocksChanged = TRUE; + } + break; + default: + break; + } + } + if (numClocksChanged) + vga256InfoRec.clocks = newNumClocks; + + if (xf86Verbose && clocksChanged) { + ErrorF("%s %s: Effective pixel clocks available for depth %d:\n", + XCONFIG_PROBED, vga256InfoRec.name, vga256InfoRec.depth); + for (i = 0; i < vga256InfoRec.clocks; i++) { + if ((i % 8) == 0) { + if (i != 0) + ErrorF("\n"); + ErrorF("%s %s: pixel clocks:", XCONFIG_PROBED, + vga256InfoRec.name); + } + ErrorF(" %6.2f", (double)vga256InfoRec.clock[i] / 1000.0); + } + ErrorF("\n"); + } + } + + /* At this point, the vga256InfoRec.clock[] values are pixel clocks */ + + + /* + * Reduce the videoRam value if necessary to prevent Y coords exceeding + * the 12-bit (4096) limit when small display widths are used on cards + * with a lot of memory + */ + /* should this go somewhere else? (MArk) */ + + if (vga256InfoRec.videoRam * 1024 / s3BppDisplayWidth > 4096) { + vga256InfoRec.videoRam = s3BppDisplayWidth * 4096 / 1024; + ErrorF("%s %s: videoram usage reduced to %dk to avoid co-ord overflow\n", + XCONFIG_PROBED, vga256InfoRec.name, vga256InfoRec.videoRam); + } + + + if (S3_964_SERIES(s3ChipId) && + !OFLG_ISSET(OPTION_NUMBER_NINE, &vga256InfoRec.options)) + s3SAM256 = 0x40; + else if ((OFLG_ISSET(OPTION_SPEA_MERCURY, &vga256InfoRec.options) && + S3_928_ONLY(s3ChipId)) || + OFLG_ISSET(OPTION_STB_PEGASUS, &vga256InfoRec.options)) + s3SAM256 = 0x80; /* set 6 MCLK cycles for R/W time on Mercury */ + else + s3SAM256 = 0x00; + + + if(xf86Verbose) + ErrorF("%s %s: Framebuffer aligned on %i pixel width\n", + XCONFIG_PROBED, vga256InfoRec.name, s3DisplayWidth); + + + /* I should probably stick this somewhere else ? */ + s3ScissB = ((vga256InfoRec.videoRam * 1024) / s3BppDisplayWidth) - 1; + s3ScissR = s3DisplayWidth - 1; + + + + /*******************************\ + | Set Linear Base | + \*******************************/ + + + /* determine if we are linear addressing */ + + if (s3newmmio || (S3_801_928_SERIES(s3ChipId) && s3Localbus + && !OFLG_ISSET(OPTION_NOLINEAR_MODE, &vga256InfoRec.options) + && !OFLG_ISSET(OPTION_NO_MEM_ACCESS, &vga256InfoRec.options))) + { + + s3InfoRec.ChipUseLinearAddressing = TRUE; + + + if (vga256InfoRec.MemBase) + s3InfoRec.ChipLinearBase = vga256InfoRec.MemBase; + else if (vgaPCIInfo && (vgaPCIInfo->Vendor == PCI_S3_VENDOR_ID) && + (vgaPCIInfo->MemBase & 0xFF800000)) + s3InfoRec.ChipLinearBase = vgaPCIInfo->MemBase & 0xFF800000; + else if (S3_x64_SERIES(s3ChipId)) + s3InfoRec.ChipLinearBase = 0xf3000000; + else + s3InfoRec.ChipLinearBase = 0x03000000; + + + s3Port59 = s3InfoRec.ChipLinearBase >> 24; + s3Port5A = s3InfoRec.ChipLinearBase >> 16; + + s3InfoRec.ChipLinearSize = vga256InfoRec.videoRam * 1024; + + /* Map the registers */ + if(s3newmmio) { + if(!(s3MmioMem = xf86MapVidMem(vga256InfoRec.scrnIndex, MMIO_REGION, + (pointer)(s3InfoRec.ChipLinearBase + S3_NEWMMIO_REGBASE), + S3_NEWMMIO_REGSIZE))) + FatalError("Unable to memory map registers!\n"); + } + + if (vga256InfoRec.videoRam <= 1024) + s3LinApOpt = 0x15; + else if (vga256InfoRec.videoRam <= 2048) + s3LinApOpt = 0x16; + else + s3LinApOpt = 0x17; + + if(s3newmmio) + s3LinApOpt &= ~0x04; + + } + + if(xf86Verbose) { + if(s3InfoRec.ChipUseLinearAddressing) + ErrorF("%s %s: Linear mapped framebuffer at 0x%08lx\n", + XCONFIG_PROBED, vga256InfoRec.name, s3InfoRec.ChipLinearBase); + else + ErrorF("%s %s: Bank switching... Bank size %i\n", + XCONFIG_PROBED, vga256InfoRec.name, 0x10000); + } + + + + /*******************************\ + | Hardware Cursor | + \*******************************/ + + if(!OFLG_ISSET(OPTION_SW_CURSOR, &vga256InfoRec.options)) + S3CursorInit(); + else { + ErrorF("%s %s: Hardware cursor disabled in XF86Config\n", + XCONFIG_GIVEN, vga256InfoRec.name); + s3CursorBytes = 0; + } + + + /*******************************\ + | Setup XAA | + \*******************************/ + + if(!OFLG_ISSET(OPTION_NOACCEL, &vga256InfoRec.options)) { + if(s3newmmio) + S3AccelInit_NewMMIO(); + else + S3AccelInit(); + } + + } + *** /dev/null Tue Jun 30 15:23:05 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/s3init.c Fri Mar 6 16:53:53 1998 *************** *** 0 **** --- 1,1083 ---- + /* $TOG: s3init.c /main/1 1998/03/06 16:55:31 kaleb $ */ + + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/s3init.c,v 1.1.2.1 1998/02/07 10:05:42 hohndel Exp $ */ + /* + * + * Copyright 1995-1997 The XFree86 Project, Inc. + * + */ + #define USE_VGAHWINIT + + #include "X.h" + #include "Xmd.h" + #include "input.h" + #include "servermd.h" + #include "scrnintstr.h" + #include "site.h" + + #include "xf86Procs.h" + #include "xf86_OSlib.h" + #include "xf86_HWlib.h" + #include "vga.h" + + #include "s3.h" + #include "s3reg.h" + #include "s3Bt485.h" + #define S3_SERVER + #include "Ti302X.h" + #include "IBMRGB.h" + #define XCONFIG_FLAGS_ONLY + #include "xf86_Config.h" + + + #define new ((vgaHWPtr)vgaNewVideoState) + #define newVS ((vgaS3Ptr)vgaNewVideoState) + #define REG50_MASK 0x673b + + static vgaS3Ptr OldS3 = NULL; + + + extern Bool pixMuxPossible; + extern Bool allowPixMuxInterlace; + extern Bool allowPixMuxSwitching; + extern int nonMuxMaxClock; + + + /* + * S3Init -- + * + * The SVGA server does Init then Save then Restore. The idea + * being that Init doesn't write any registers but merely fills + * in a data structure. Save then saves the original state (you + * could do that if Init didn't write any registers). Then Restore + * restores the data structure that you completed in Init. But + * since we couldn't refrain from writing registers in Init, our + * Save will be corrupted and the Restore is useless. I have + * essentially pounded the SVGA server into the form of the S3 + * server. Now Init writes registers, Save saves a bogus state + * so our restore doesn't do anything (empty function). Save + * is functional though. I do use it to save the initial state. + * It's just not the same initial state that the SVGA server + * saves. I call it sooner on the first pass through Init (S3 + * server style) and restore it explicitly in the EnterLeave + * function (also S3 server style). + * + * MArk + */ + + + Bool S3Init(DisplayModePtr mode) + { + static Bool FirstTime = TRUE; + short InitLevel = 3; + + #ifdef S3_DEBUG + ErrorF("In S3Init()\n"); + #endif + + if(FirstTime) { + /* save the initial state */ + OldS3 = S3Save(OldS3); + FirstTime = FALSE; + } + + /* There should be a flag or something that tells if we have already + filled in mode info. Perhaps something in Private? This only needs + to be filled in when the mode is being run for the first time or + when there is a change that forces us to go to init level 2 (MArk) */ + S3FillInModeInfo(mode); + + + if(pixMuxPossible) { + unsigned char verdict; + Bool PriorPixMux = s3PixelMultiplexing; + /* in case we are using a prior computed mode. not needed yet */ + Bool PriorModeMux = (mode->Flags & V_PIXMUX); + + /* If mux is changing, fill in mode info again and take to init level 2. + Note that the S3MuxOrNot function merely states if we must or can't + mux. If it's indifferent, we don't change the mux state. */ + + if((verdict = S3MuxOrNot(mode)) == (MUSTMUX | CANTMUX)) + return FALSE; + else if(!verdict) { /* don't care */ + if(s3PixelMultiplexing) mode->Flags |= V_PIXMUX; + else mode->Flags &= ~V_PIXMUX; + } else { /* must be one way or the other */ + if(verdict == MUSTMUX) mode->Flags |= V_PIXMUX; + else mode->Flags &= ~V_PIXMUX; + } + + + s3PixelMultiplexing = (mode->Flags & V_PIXMUX) ? TRUE : FALSE; + + #ifdef S3_DEBUG + ErrorF("Mode \"%s\" %s pixmux\n",mode->name,s3PixelMultiplexing ? + "Using" : "Not Using"); + #endif + if((s3PixelMultiplexing != PriorPixMux) || + (s3PixelMultiplexing != PriorModeMux)) { + /* If multiplexing state has changed, recalculate Mux Shift + and take initialization back a level */ + S3FillInModeInfo(mode); + InitLevel = 2; + } + } + + + if(!s3Initialized) { + InitLevel = 1; + s3Initialized = TRUE; + } + + switch(InitLevel) { + case 1: + if(!S3InitLevelOne(mode)) return FALSE; + case 2: + if(!S3InitLevelTwo(mode)) return FALSE; + default: + if(!S3InitLevelThree(mode)) return FALSE; + } + + s3CurrentMode = mode; + + return TRUE; + } + + + /* I'll work on Levels One and Two when I figure out where to make + the cuts. We essentially do a full init every time for the + moment. That's almost what the S3 server was doing anyhow (MArk) */ + + + /* + * S3InitLevelOne -- + * + * Full reinitialization + */ + + Bool S3InitLevelOne(DisplayModePtr mode) + { + #ifdef S3_DEBUG + ErrorF("In S3InitLevelOne()\n"); + #endif + + return TRUE; + } + + + + + + /* + * S3InitLevelTwo -- + * + * Take it back one level in some cases. + */ + + Bool S3InitLevelTwo(DisplayModePtr mode) + { + #ifdef S3_DEBUG + ErrorF("In S3InitLevelTwo()\n"); + #endif + + + return TRUE; + + } + + + + /* + * S3InitLevelThree -- + * + * Simple mode change. + * + * Everything is stuck in here for now (Init level 1 every time!) + * We migrate things back to 1 and 2 when we figure out where to + * make the cuts. If you know what a particular piece of code does + * and it isn't labeled... label it! (MArk) + * + */ + + Bool S3InitLevelThree(DisplayModePtr mode) + { + unsigned char CR5C, tmp; + unsigned int itmp; + short i,n,m; + int interlacedivisor = mode->Flags & V_INTERLACE ? 2 : 1; + + #ifdef S3_DEBUG + ErrorF("In S3InitLevelThree()\n"); + #endif + + + if (!vgaHWInit(mode, sizeof(vgaS3Rec))) + return FALSE; + + + /* S3Adjust() needs this */ + s3HDisplay = mode->HDisplay; + + new->MiscOutReg |= 0x0C; /* enable CR42 clock selection */ + new->Sequencer[0] = 0x03; /* XXXX shouldn't need this */ + new->CRTC[19] = s3BppDisplayWidth >> 3; + new->CRTC[23] = 0xE3; /* XXXX shouldn't need this */ + new->Attribute[0x11] = s3DACBoarder; /* The overscan colour AR11 gets */ + /* disabled anyway */ + + /* !! double negative? (MArk) */ + if ((S3_TRIO64V_SERIES(s3ChipId) && (s3ChipRev <= 0x53) && (s3Bpp==1)) ^ + !!OFLG_ISSET(OPTION_TRIO64VP_BUG2, &vga256InfoRec.options)) { + /* set correct blanking for broken Trio64V+ to avoid bright left border: + blank signal needs to go off ~400 usec before video signal starts + w/o border: blank_shift = 0 */ + int blank_shift = 400 * vga256InfoRec.clock[mode->Clock] / 1000000 / 8; + new->CRTC[2] = mode->CrtcHDisplay >> 3; + new->CRTC[3] &= ~0x1f; + new->CRTC[3] |= ((mode->CrtcHTotal >> 3) - 2 - blank_shift) & 0x1f; + new->CRTC[5] &= ~0x80; + new->CRTC[5] |= (((mode->CrtcHTotal >> 3) - 2 - blank_shift) & 0x20) << 2; + + new->CRTC[21] = (mode->CrtcVDisplay - 1) & 0xff; + new->CRTC[7] &= ~0x08; + new->CRTC[7] |= ((mode->CrtcVDisplay - 1) & 0x100) >> 5; + new->CRTC[9] &= ~0x20; + new->CRTC[9] |= ((mode->CrtcVDisplay - 1) & 0x200) >> 4; + + new->CRTC[22] = (mode->CrtcVTotal - 2) & 0xFF; + } + + if (vgaIOBase == 0x3B0) + new->MiscOutReg &= 0xFE; + else + new->MiscOutReg |= 0x01; + + /***********************\ + | BLAH!!!!! | + \***********************/ + + /* here's where I blow it and give into the idea of actually + writing registers in here (MArk). */ + + vgaProtect(TRUE); + + if (DAC_IS_TI3025) { + /* switch the ramdac from bt485 to ti3020 mode clearing RS4 */ + outb(vgaCRIndex, 0x5C); + CR5C = inb(vgaCRReg); + outb(vgaCRReg, CR5C & 0xDF); + + /* clear TI_PLANAR_ACCESS bit */ + s3OutTiIndReg(TI_CURS_CONTROL, 0x7F, 0x00); + } + + + + /* can this be moved to the DACInit functions ? It gets it out + of the common code and if we ever stick ramdac support + in modules, the rest of the server doesn't have to + deal with it (MArk) */ + if (OFLG_ISSET(OPTION_SPEA_MERCURY, &vga256InfoRec.options) && + S3_928_ONLY(s3ChipId)) { + /* + * Make sure that parallel option is already set correctly before + * changing the clock doubler state. + * XXXX maybe the !s3PixelMultiplexing bit is not required? + */ + if (s3PixelMultiplexing) { + outb(vgaCRIndex, 0x5C); + outb(vgaCRReg, 0x20); + outb(0x3C7, 0x21); + /* set s3 reg53 to parallel addressing by or'ing 0x20 */ + outb(vgaCRIndex, 0x53); + tmp = inb(vgaCRReg) | 0x20; + outb(vgaCRReg, tmp); + outb(vgaCRIndex, 0x5C); + outb(vgaCRReg, 0x00); + } else { + outb(vgaCRIndex, 0x5C); + outb(vgaCRReg, 0x20); + outb(0x3C7, 0x00); + /* set s3 reg53 to non-parallel addressing by and'ing 0xDF */ + outb(vgaCRIndex, 0x53); + tmp = inb(vgaCRReg) & 0xDF; + outb(vgaCRReg, tmp); + outb(vgaCRIndex, 0x5C); + outb(vgaCRReg, 0x00); + } + if (s3Bpp == 4) + s3OutTi3026IndReg(TI_LATCH_CONTROL, ~1, 1); /* 0x06 -> 0x07 */ + else + s3OutTi3026IndReg(TI_LATCH_CONTROL, ~1, 0); /* 0x06 */ + } + + + /* should be able to move this to the DACInit functions (MArk) */ + if((DAC_IS_TI3026 || DAC_IS_TI3030) && + (OFLG_ISSET(CLOCK_OPTION_ICD2061A, &vga256InfoRec.clockOptions))){ + /* + * for the boards with Ti3026 and external ICD2061A clock chip we + * need to enable clock doubling, if necessary + */ + if( mode->Flags & V_DBLCLK ) { + s3OutTi3026IndReg(TI_INPUT_CLOCK_SELECT,0x00,0x08); + } + else { + s3OutTi3026IndReg(TI_INPUT_CLOCK_SELECT,0x00,0x00); + } + if (s3Bpp == 4) + s3OutTi3026IndReg(TI_LATCH_CONTROL, ~1, 1); /* 0x06 -> 0x07 */ + else + s3OutTi3026IndReg(TI_LATCH_CONTROL, ~1, 0); /* 0x06 */ + } + + + /* Don't change the clock bits when using an external clock program */ + + if (new->NoClock < 0) { + new->MiscOutReg = (new->MiscOutReg & 0xF3) | (inb(0x3CC) & 0x0C); + } else { + /* XXXX Should we really do something about the return value? */ + if (OFLG_ISSET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions)) + (void) (s3ClockSelectFunc)(mode->SynthClock); + else + (void) (s3ClockSelectFunc)(mode->Clock); + + /* OK. how about + if(!(s3ClockSelectFunc)( + OFLG_ISSET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions) ? + mode->SynthClock : mode->Clock)) return FALSE; + + */ + + if ((mode->Flags & V_DBLCLK) + && (DAC_IS_TI3026 || DAC_IS_TI3030) + && (OFLG_ISSET(CLOCK_OPTION_ICD2061A, &vga256InfoRec.clockOptions))){ + if (s3Bpp <= 2) + Ti3026SetClock(mode->SynthClock / 2, 2, s3Bpp, TI_LOOP_CLOCK); + else + Ti3026SetClock(mode->SynthClock, 2, s3Bpp, TI_LOOP_CLOCK); + s3OutTi3026IndReg(TI_MCLK_LCLK_CONTROL, ~0x20, 0x20); + } + if ((DAC_IS_TI3026 || DAC_IS_TI3030) && s3Bpp == 3) { + s3OutTi3026IndReg(TI_MCLK_LCLK_CONTROL, ~0x20, 0x20); + } + } + + + /* Initialize Ramdac */ + if(!(s3Ramdacs[s3RamdacType].DacInit)(mode)) { + ErrorF("%s RAMDAC initialization failed!\n", + s3Ramdacs[s3RamdacType].DacName); + return FALSE; + } + + outb(0x3C2, new->MiscOutReg); + + for (i = 1; i < 5; i++) + outw(0x3C4, (new->Sequencer[i] << 8) | i); + + for (i = 0; i < 25; i++) + outw(vgaCRIndex, (new->CRTC[i] << 8) | i); + + for (i = 0; i < 9; i++) + outw(0x3CE, (new->Graphics[i] << 8) | i); + + inb(vgaIOBase + 0x0A); /* reset flip-flop */ + for (i = 0; i < 16; i++) { + outb(0x3C0, i); + outb(0x3C0, new->Attribute[i]); + } + for (i = 16; i < 21; i++) { + outb(0x3C0, i | 0x20); + outb(0x3C0, new->Attribute[i]); + } + + /****** CR31 ******/ + /* We need to save CR31 since it is also used for the display + start address. Here we initialize for two page setup when + using a 2048 width */ + if (s3DisplayWidth == 2048) + s3Port31 = 0x8f; + else + s3Port31 = 0x8d; + outb(vgaCRIndex, 0x31); outb(vgaCRReg, s3Port31); + + /***** CR32, CR33 and CR34 *****/ + /* These are the backwards compatibility registers */ + outb(vgaCRIndex, 0x32); outb(vgaCRReg, 0x00); /* Back compat 1 */ + outb(vgaCRIndex, 0x33); /* Back compat 2 */ + if (OFLG_ISSET(OPTION_STB_PEGASUS, &vga256InfoRec.options)) + /* Blank border comes earlier than display enable. */ + outb(vgaCRReg, 0x00); + else if (!S3_TRIOxx_SERIES(s3ChipId)) + outb(vgaCRReg, 0x20); + outb(vgaCRIndex, 0x34); outb(vgaCRReg, 0x10); /* Back compat 3 */ + S3BankZero(); + + + /****** CR3A ******/ + outb(vgaCRIndex, 0x3a); + if (OFLG_ISSET(OPTION_SLOW_DRAM_REFRESH, &vga256InfoRec.options)) + outb(vgaCRReg, 0xb7); + else + outb(vgaCRReg, 0xb5); + + /****** CR3B ******/ + /* CR3B and CR3C may undergo some additional modifications + later on */ + outb(vgaCRIndex, 0x3b); + outb(vgaCRReg, (new->CRTC[0] + new->CRTC[4] + 1) / 2); + + /****** CR3C ******/ + outb(vgaCRIndex, 0x3c); + outb(vgaCRReg, new->CRTC[0]/2); /* Interlace mode frame offset */ + + /****** CR40 ******/ + outb(vgaCRIndex, 0x40); + tmp = inb(vgaCRReg); + if (S3_911_SERIES (s3ChipId)) + tmp = (tmp & 0xf2) | 0x09; + else { + if (s3Localbus) { + tmp &= 0xf2; + if (OFLG_ISSET(OPTION_STB_PEGASUS, &vga256InfoRec.options) || + OFLG_ISSET(OPTION_MIRO_MAGIC_S4, &vga256InfoRec.options)) + tmp |= 0x01; /* no wait states */ + else tmp |= 0x05; /* one wait state */ + } else tmp = (tmp & 0xf6) | 0x01; + } + outb(vgaCRReg, tmp); + + /****** CR43 ******/ + outb(vgaCRIndex, 0x43); + switch (vga256InfoRec.depth) { + case 24: + case 32: + if (S3_864_SERIES(s3ChipId)) + outb(vgaCRReg, 0x08); /* 0x88 can't be used for 864/964 */ + else if (S3_801_928_SERIES(s3ChipId) && DAC_IS_SC15025) + outb(vgaCRReg, 0x01); /* ELSA Winner 1000 */ + else if (DAC_IS_BT485_SERIES && S3_928_SERIES(s3ChipId)) + outb(vgaCRReg, 0x00); + break; + case 15: + case 16: + if (DAC_IS_ATT490 || DAC_IS_GENDAC || DAC_IS_SC1148x /* JON */ + || DAC_IS_SS2410 ) /*??? I'm not sure - but the 490 does it */ + outb(vgaCRReg, 0x80); + else if (DAC_IS_TI3025) + outb(vgaCRReg, 0x10); + else if (DAC_IS_TI3026 || DAC_IS_TI3030) + outb(vgaCRReg, 0x10); + else if (DAC_IS_IBMRGB) + outb(vgaCRReg, 0x10); + else if (S3_864_SERIES(s3ChipId)) + outb(vgaCRReg, 0x08); /* 0x88 can't be used for 864/964 */ + else if (S3_928_SERIES(s3ChipId)) { + if (DAC_IS_SC15025) + outb(vgaCRReg, 0x01); /* ELSA Winner 1000 */ + else if (DAC_IS_BT485_SERIES || DAC_IS_TI3020) + outb(vgaCRReg, 0x00); + else + outb(vgaCRReg, 0x09); /* who uses this ? */ + } + else if (DAC_IS_ATT498 && S3_805_I_SERIES(s3ChipId)) + outb(vgaCRReg, 0x00); + else + outb(vgaCRReg, 0x09); + break; + case 8: + default: + outb(vgaCRReg, 0x00); /* DON'T enable XOR addresses */ + break; + } + + /****** CR44 ******/ + /* What is this? */ + outb(vgaCRIndex, 0x44); outb(vgaCRReg, 0x00); + + /****** CR45 ******/ + outb(vgaCRIndex, 0x45); + tmp = inb(vgaCRReg) & 0xf2; + /* hi/true cursor color enable */ + switch (vga256InfoRec.bitsPerPixel) { + case 16: + if (!S3_x64_SERIES(s3ChipId) && !S3_805_I_SERIES(s3ChipId) && + !DAC_IS_TI3020) + tmp |= 0x04; + break; + case 32: + if (S3_x64_SERIES(s3ChipId) || S3_805_I_SERIES(s3ChipId) || + DAC_IS_TI3020) + tmp |= 0x04; /* for 16bit RAMDAC, 0x0c for 8bit RAMDAC */ + else + tmp |= 0x08; + break; + } + outb(vgaCRReg, tmp); + + + /************ Big section for all but 911/914 **************/ + + if (S3_801_928_SERIES(s3ChipId)) { + /****** CR50 ******/ + outb(vgaCRIndex, 0x50); + tmp = inb(vgaCRReg) & ~0xf1; + switch (vga256InfoRec.bitsPerPixel) { + case 8: + break; + case 16: + tmp |= 0x10; + break; + case 24: + tmp |= 0x20; + break; + case 32: + tmp |= 0x30; + break; + } + switch (s3DisplayWidth) { + case 640: + tmp |= 0x40; + break; + case 800: + tmp |= 0x80; + break; + case 1152: + tmp |= 0x01; + break; + case 1280: + tmp |= 0xc0; + break; + case 1600: + tmp |= 0x81; + break; + default: /* 1024 and 2048 */ + break; + } + outb(vgaCRReg, tmp); + + /****** CR51 ******/ + outb(vgaCRIndex, 0x51); + s3Port51 = (inb(vgaCRReg) & 0xC0) | ((s3BppDisplayWidth >> 7) & 0x30); + if (OFLG_ISSET(OPTION_STB_PEGASUS, &vga256InfoRec.options) || + OFLG_ISSET(OPTION_MIRO_MAGIC_S4, &vga256InfoRec.options)) { + if (s3PixelMultiplexing) + /* In Pixel Multiplexing mode, disable split transfers. */ + s3Port51 |= 0x40; + else + /* In VGA mode, enable split transfers. */ + s3Port51 &= ~0x40; + } + outb(vgaCRReg, s3Port51); + + + /****** CR53 ******/ + outb(vgaCRIndex, 0x53); + tmp = inb(vgaCRReg); + + if(s3newmmio) + tmp |= 0x18; + else + tmp &= ~0x18; + + /* + * Now the DRAM interleaving bit for the 801/805 chips + * Note, we don't touch this bit for 928 chips because they use it + * for pixel multiplexing control. + */ + if (S3_801_SERIES(s3ChipId)) { + if (S3_805_I_SERIES(s3ChipId) && vga256InfoRec.videoRam == 2048) + tmp |= 0x20; + else + tmp &= ~0x20; + } + outb(vgaCRReg, tmp); + + + /****** CR54 ******/ + n = 255; + outb(vgaCRIndex, 0x54); + if (S3_x64_SERIES(s3ChipId) || S3_805_I_SERIES(s3ChipId)) { + int clock2,mclk; + clock2 = vga256InfoRec.clock[mode->Clock] * s3Bpp; + if (vga256InfoRec.s3MClk > 0) + mclk = vga256InfoRec.s3MClk; + else if (S3_805_I_SERIES(s3ChipId)) + mclk = 50000; /* 50 MHz, guess for 805i limit */ + else + mclk = 60000; /* 60 MHz, limit for 864 */ + if (vga256InfoRec.videoRam < 2048 || S3_TRIO32_SERIES(s3ChipId)) + clock2 *= 2; + m = (int)((mclk/1000.0*.72+16.867)*89.736/(clock2/1000.0+39)-21.1543); + if (vga256InfoRec.videoRam < 2048 || S3_TRIO32_SERIES(s3ChipId)) + m /= 2; + m -= vga256InfoRec.s3Madjust; + if (m > 31) m = 31; + else if (m < 0) { + m = 0; + n = 16; + } + } + else if (vga256InfoRec.videoRam == 512 || mode->HDisplay > 1200) + m = 0; + else if (vga256InfoRec.videoRam == 1024) + m = 2; + else + m = 20; + + if (OFLG_ISSET(OPTION_STB_PEGASUS, &vga256InfoRec.options)) + tmp = 0x7F; + else if (OFLG_ISSET(OPTION_MIRO_MAGIC_S4, &vga256InfoRec.options)) + tmp = 0; + else tmp = m << 3; + outb(vgaCRReg, tmp); + + /****** CR60 ******/ + n -= vga256InfoRec.s3Nadjust; + if (n < 0) n = 0; + else if (n > 255) n = 255; + outb(vgaCRIndex, 0x60); + outb(vgaCRReg, n); + + + /****** CR55 ******/ + if(!OFLG_ISSET(OPTION_MIRO_MAGIC_S4, &vga256InfoRec.options)) { + outb(vgaCRIndex, 0x55); + /* remove mysterious dot at 60Hz */ + tmp = (inb(vgaCRReg) & 0x08) | 0x40; + outb(vgaCRReg, tmp); + } + + /* This shouldn't be needed -- they should be set by vgaHWInit() */ + if (!mode->CrtcVAdjusted) { + mode->CrtcVTotal /= interlacedivisor; + mode->CrtcVDisplay /= interlacedivisor; + mode->CrtcVSyncStart /= interlacedivisor; + mode->CrtcVSyncEnd /= interlacedivisor; + mode->CrtcVAdjusted = TRUE; + } + + + /****** CR5E ******/ + outb(vgaCRIndex, 0x5e); + if ((S3_TRIO64V_SERIES(s3ChipId) && (s3ChipRev <= 0x53) && (s3Bpp==1)) ^ + !!OFLG_ISSET(OPTION_TRIO64VP_BUG2, &vga256InfoRec.options)) + i = (((mode->CrtcVTotal - 2) & 0x400) >> 10) | + (((mode->CrtcVDisplay - 1) & 0x400) >> 9) | + (((mode->CrtcVDisplay - 1) & 0x400) >> 8) | + (((mode->CrtcVSyncStart) & 0x400) >> 6) | 0x40; + else + i = (((mode->CrtcVTotal - 2) & 0x400) >> 10) | + (((mode->CrtcVDisplay - 1) & 0x400) >> 9) | + (((mode->CrtcVSyncStart) & 0x400) >> 8) | + (((mode->CrtcVSyncStart) & 0x400) >> 6) | 0x40; + outb(vgaCRReg, i); + + if ((S3_TRIO64V_SERIES(s3ChipId) && (s3ChipRev <= 0x53) && (s3Bpp==1)) ^ + !!OFLG_ISSET(OPTION_TRIO64VP_BUG2, &vga256InfoRec.options)) { + i = ((((mode->CrtcHTotal >> 3) - 5) & 0x100) >> 8) | + ((((mode->CrtcHDisplay >> 3) - 1) & 0x100) >> 7) | + (((mode->CrtcHDisplay >> 3) & 0x100) >> 6) | + ((mode->CrtcHSyncStart & 0x800) >> 7); + if ((mode->CrtcHTotal >> 3) - (mode->CrtcHDisplay >> 3) > 64) + i |= 0x08; /* add another 64 DCLKs to blank pulse width */ + } + else { + i = ((((mode->CrtcHTotal >> 3) - 5) & 0x100) >> 8) | + ((((mode->CrtcHDisplay >> 3) - 1) & 0x100) >> 7) | + ((((mode->CrtcHSyncStart >> 3) - 1) & 0x100) >> 6) | + ((mode->CrtcHSyncStart & 0x800) >> 7); + if ((mode->CrtcHSyncEnd >> 3) - (mode->CrtcHSyncStart >> 3) > 64) + i |= 0x08; /* add another 64 DCLKs to blank pulse width */ + } + + if ((mode->CrtcHSyncEnd >> 3) - (mode->CrtcHSyncStart >> 3) > 32) + i |= 0x20; /* add another 32 DCLKs to hsync pulse width */ + + + /****** CR3B ******/ + outb(vgaCRIndex, 0x3b); + if (DAC_IS_IBMRGB528) { + if (s3Bpp==1) + itmp = ((new->CRTC[4] + ((i&0x10)<<4) + 2) + 1) & ~1; + else + itmp = ((new->CRTC[4] + ((i&0x10)<<4) + 4) + 1) & ~1; + } + else { + itmp = ( new->CRTC[0] + ((i&0x01)<<8) + + new->CRTC[4] + ((i&0x10)<<4) + 1) / 2; + if (itmp-(new->CRTC[4] + ((i&0x10)<<4)) < 4) + if (new->CRTC[4] + ((i&0x10)<<4) + 4 <= new->CRTC[0]+ ((i&0x01)<<8)) + itmp = new->CRTC[4] + ((i&0x10)<<4) + 4; + else + itmp = new->CRTC[0]+ ((i&0x01)<<8) + 1; + } + outb(vgaCRReg, itmp & 0xff); + i |= (itmp&0x100) >> 2; + + /****** CR3C ******/ + outb(vgaCRIndex, 0x3c); + /* Interlace mode frame offset */ + outb(vgaCRReg, (new->CRTC[0] + ((i&0x01)<<8)) /2); + + /****** CR5D ******/ + outb(vgaCRIndex, 0x5d); + tmp = (inb(vgaCRReg) & 0x80) | i; + outb(vgaCRReg, tmp); + + if (vga256InfoRec.videoRam > 1024 && S3_x64_SERIES(s3ChipId)) + i = mode->HDisplay * s3Bpp / 8 + 1; + else /* XXX should be checked for 801/805 */ + i = mode->HDisplay * s3Bpp / 4 + 1; + + /****** CR61 ******/ + outb(vgaCRIndex, 0x61); + tmp = 0x80 | (inb(vgaCRReg) & 0x60) | (i >> 8); + outb(vgaCRReg, tmp); + outb(vgaCRIndex, 0x62); + outb(vgaCRReg, i & 0xff); + } /* (S3_801_928_SERIES(s3ChipId) */ + + + /****** CR42 ******/ + outb(vgaCRIndex, 0x42); + tmp = inb(vgaCRReg); + if ((mode->Flags & V_INTERLACE) != 0) + tmp |= 0x20; + else + tmp &= ~0x20; + outb(vgaCRReg, tmp); + + /****** CR67, CR6D and CR65 ******/ + if (mode->Private) { + if (mode->Private[0] & (1 << S3_INVERT_VCLK)) { + outb(vgaCRIndex, 0x67); + tmp = inb(vgaCRReg) & 0xfe; + if (mode->Private[S3_INVERT_VCLK]) + tmp |= 1; + outb(vgaCRReg, tmp); + } + if (mode->Private[0] & (1 << S3_BLANK_DELAY)) { + outb(vgaCRIndex, 0x6d); + outb(vgaCRReg, mode->Private[S3_BLANK_DELAY]); + } + if (mode->Private[0] & (1 << S3_EARLY_SC)) { + outb(vgaCRIndex, 0x65); + tmp = inb(vgaCRReg) & ~2; + if (mode->Private[S3_EARLY_SC]) + tmp |= 2; + outb(vgaCRReg, tmp); + } + } + + + /****** CR66 ******/ + /* PCI disconect enable - perhaps this can be hidden from the 911 + and 914 in the 801_928 section above */ + outb(vgaCRIndex, 0x66); + tmp = inb(vgaCRReg); + + if(s3newmmio && s3PCIRetry) + outb(vgaCRReg, tmp | 0x88); + else + outb(vgaCRReg, tmp | 0x80); + + + if (OFLG_ISSET(OPTION_FAST_VRAM, &vga256InfoRec.options)) { + outb(vgaCRIndex, 0x39); + outb(vgaCRReg, 0xa5); + outb(vgaCRIndex, 0x68); + /* -RAS low timing 3.5 MCLKs, -RAS precharge timing 2.5 MCLKs */ + tmp = inb(vgaCRReg) | 0xf0; + outb(vgaCRReg, tmp); + } + + if (OFLG_ISSET(OPTION_SLOW_VRAM, &vga256InfoRec.options)) { + /* + * some Diamond Stealth 64 VRAM cards have a problem with VRAM timing, + * increase -RAS low timing from 3.5 MCLKs to 4.5 MCLKs + */ + outb(vgaCRIndex, 0x39); + outb(vgaCRReg, 0xa5); + outb(vgaCRIndex, 0x68); + tmp = inb(vgaCRReg); + if (tmp & 0x30) /* 3.5 MCLKs */ + outb(vgaCRReg, tmp & 0xef); /* 4.5 MCLKs */ + } + + if (OFLG_ISSET(OPTION_SLOW_DRAM, &vga256InfoRec.options)) { + /* + * fixes some pixel errors for a SPEA Trio64V+ card + * increase -RAS precharge timing from 2.5 MCLKs to 3.5 MCLKs + */ + outb(vgaCRIndex, 0x39); + outb(vgaCRReg, 0xa5); + outb(vgaCRIndex, 0x68); + tmp = inb(vgaCRReg) & 0xf7; + outb(vgaCRReg, tmp); /* 3.5 MCLKs */ + } + + if (OFLG_ISSET(OPTION_SLOW_EDODRAM, &vga256InfoRec.options)) { + /* + * fixes some pixel errors for a SPEA Trio64V+ card + * increase from 1-cycle to 2-cycle EDO mode + */ + outb(vgaCRIndex, 0x39); + outb(vgaCRReg, 0xa5); + outb(vgaCRIndex, 0x36); + tmp = inb(vgaCRReg); + if (!(tmp & 0x0c)) /* 1-cycle EDO */ + outb(vgaCRReg, tmp | 0x08); /* 2-cycle EDO */ + } + + if (S3_964_SERIES(s3ChipId) && DAC_IS_BT485_SERIES) { + if (OFLG_ISSET(OPTION_S3_964_BT485_VCLK, &vga256InfoRec.options)) { + /* + * This is the design alert from S3 with Bt485A and Vision 964. + */ + int i1, last, cr55, cr67; + int port, bit; + + + if (OFLG_ISSET(OPTION_DIAMOND, &vga256InfoRec.options)) { + port = 0x3c2; + bit = 0x10; + } + else { /* MIRO 20SV Rev.2 */ + port = 0x3c8; + bit = 0x04; + } + + if (port == 0x3c8) { + outb(vgaCRIndex, 0x55); + cr55 = inb(vgaCRReg); + outb(vgaCRReg, cr55 | 0x04); /* enable rad of general input */ + } + outb(vgaCRIndex, 0x67); + cr67 = inb(vgaCRReg); + + for(last=i1=30; --i1;) { + S3RetraceWait(); + S3RetraceWait(); + if ((inb(port) & bit) == 0) { /* if GD2 is low then */ + last = i1; + outb(vgaCRIndex, 0x67); + /* clock should be inverted */ + tmp = inb(vgaCRReg) ^ 0x01; + outb(vgaCRReg, tmp); + } + if (last-i1 > 4) break; + } + if (!i1) { /* didn't get stable input, restore original CR67 value */ + outb(vgaCRIndex, 0x67); + outb(vgaCRReg, cr67); + } + if (port == 0x3c8) { + outb(vgaCRIndex, 0x55); + outb(vgaCRReg, cr55); + } + } + } + + if (OFLG_ISSET(OPTION_ELSA_W2000PRO_X8, &vga256InfoRec.options)) { + /* check LCLK/SCLK phase */ + unsigned char cr5c, cr42; + + outb(vgaCRIndex, 0x42); + cr42 = inb(vgaCRReg); + + if (inb(0x3cc) & 0x40) /* hsync polarity */ + cr42 &= 0xfb; + else + cr42 |= 0x04; + outb(vgaCRReg, cr42); + + outb(vgaCRIndex, 0x5c); + cr5c = inb(vgaCRReg); + outb(vgaCRReg, cr5c | 0xa0); /* set GD7 & GD5 */ + + usleep(100000); /* wait at least 2 VSYNCs to latch clock phase */ + + if (inb(0x3c2) & 0x10) /* query SENSE */ + cr42 &= 0xf7; + else + cr42 |= 0x08; + + outb(vgaCRIndex, 0x42); + outb(vgaCRReg, cr42); + + outb(vgaCRIndex, 0x5c); + outb(vgaCRReg, cr5c & 0x7f | 0x20); + } + + if (OFLG_ISSET(CLOCK_OPTION_ICS2595, &vga256InfoRec.clockOptions)) + (void) (s3ClockSelectFunc)(mode->SynthClock); + /* fixes the ICS2595 initialisation problems */ + + S3Adjust(vga256InfoRec.frameX0, vga256InfoRec.frameY0); + + if ( S3_TRIO64V2_SERIES(s3ChipId) ) { + /* disable DAC power saving to avoid bright left edge */ + outb(0x3d4,0x86); + outb(0x3d5,0x80); + /* disable the stream display fetch length control */ + outb(0x3d4,0x90); + outb(0x3d5,0x00); + } + + vgaProtect(FALSE); + + if (s3DisplayWidth == 1024) /* this is unclear Jon */ + outw(ADVFUNC_CNTL, 0x0007); + else + outw(ADVFUNC_CNTL, 0x0003); + + /* + * Blank the screen temporarily to display color 0 by turning the display of + * all planes off + */ + outb(DAC_MASK, 0x00); + + /* Reset the 8514/A, and disable all interrupts. */ + outw(SUBSYS_CNTL, GPCTRL_RESET | CHPTEST_NORMAL); + outw(SUBSYS_CNTL, GPCTRL_ENAB | CHPTEST_NORMAL); + + inw(SUBSYS_STAT); + + outw(MULTIFUNC_CNTL, MEM_CNTL | VRTCFG_4 | HORCFG_8); + + outb(DAC_MASK, 0xff); + + #ifdef PC98 + crtswitch(1); + #endif + + /***************************************\ + | Set up Linear Addressing | + \***************************************/ + + + if (s3InfoRec.ChipUseLinearAddressing) { + outb(vgaCRIndex, 0x59); outb(vgaCRReg, s3Port59); + outb(vgaCRIndex, 0x5a); outb(vgaCRReg, s3Port5A); + + outb (vgaCRIndex, 0x58); + outb (vgaCRReg, s3LinApOpt | s3SAM256); + } else { + outb(vgaCRIndex, 0x58); + outb(vgaCRReg, s3SAM256); + } + + WaitQueue(5); + SET_SCISSORS(0,0,s3ScissR,s3ScissB); + if(s3Bpp > 2) { + if(s3newmmio) + SET_MULT_MISC(0x200); + else + SET_MULT_MISC(0); + } + + return TRUE; + } + + + + + + /* + * S3CleanUp -- + * + */ + + + void S3CleanUp() + { + vgaS3Ptr restore = OldS3; + short i; + + #ifdef S3_DEBUG + ErrorF("In S3CleanUp()\n"); + #endif + + vgaProtect(TRUE); + + + WaitQueue(8); + S3BankZero(); + + outw(ADVFUNC_CNTL, 0); + + if(s3newmmio) + outb(vgaCRIndex, 0x53); outb(vgaCRReg, 0x00); + + (s3Ramdacs[s3RamdacType].DacRestore)(restore); + + if (DAC_IS_TI3025) { + outb(vgaCRIndex, 0x5C); + outb(vgaCRReg, restore->s3sysreg[0x0C + 16]); + } + + /* restore s3 special bits */ + if (S3_801_928_SERIES(s3ChipId)) { + /* restore 801 specific registers */ + + for (i = 32; i < (S3_x64_SERIES(s3ChipId) ? 46 : + S3_805_I_SERIES(s3ChipId) ? 40 : 38) ; i++) { + outb(vgaCRIndex, 0x40 + i); + outb(vgaCRReg, restore->s3sysreg[i]); + + } + for (i = 0; i < 16; i++) { + if (!((1 << i) & REG50_MASK)) + continue; + outb(vgaCRIndex, 0x50 + i); + outb(vgaCRReg, restore->s3sysreg[i + 16]); + } + } + for (i = 0; i < 5; i++) { + outb(vgaCRIndex, 0x30 + i); + outb(vgaCRReg, restore->s3reg[i]); + outb(vgaCRIndex, 0x38 + i); + outb(vgaCRReg, restore->s3reg[5 + i]); + } + + for (i = 0; i < 16; i++) { + outb(vgaCRIndex, 0x40 + i); + outb(vgaCRReg, restore->s3sysreg[i]); + } + + outb(vgaCRIndex, 0x45); + inb(vgaCRReg); /* reset color stack pointer */ + outb(vgaCRIndex, 0x4A); + for (i = 0; i < 4; i++) + outb(vgaCRReg, restore->ColorStack[i]); + + outb(vgaCRIndex, 0x45); + inb(vgaCRReg); /* reset color stack pointer */ + outb(vgaCRIndex, 0x4B); + for (i = 4; i < 8; i++) + outb(vgaCRReg, restore->ColorStack[i]); + + + if (OFLG_ISSET(CLOCK_OPTION_ICS2595, &vga256InfoRec.clockOptions)){ + outb(vgaCRIndex, 0x42); + outb(vgaCRReg, (restore->s3sysreg[2] & 0xf0) | 0x01); + outb(vgaCRIndex, 0x5c); /* switch back to 28MHz clock */ + outb(vgaCRReg, 0x20); + outb(vgaCRReg, 0x00); + } + + vgaHWRestore((vgaHWPtr)restore); + + outb(0x3c2, restore->Clock); + + + vgaProtect(FALSE); + } + *** /dev/null Tue Jun 30 15:23:06 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/s3misc.c Sat Mar 7 17:09:49 1998 *************** *** 0 **** --- 1,752 ---- + /* $TOG: s3misc.c /main/2 1998/03/07 17:11:31 kaleb $ */ + + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/s3misc.c,v 1.1.2.2 1998/02/20 14:28:01 robin Exp $ */ + /* + * + * Copyright 1995-1997 The XFree86 Project, Inc. + * + */ + #include "X.h" + #include "input.h" + #include "screenint.h" + + #include "compiler.h" + #include "xf86.h" + #include "xf86Priv.h" + #include "xf86_OSlib.h" + #include "xf86_HWlib.h" + #include "xf86_PCI.h" + #include "vga.h" + #include "vgaPCI.h" + + #ifdef XFreeXDGA + #include "X.h" + #include "Xproto.h" + #include "scrnintstr.h" + #include "servermd.h" + #define _XF86DGA_SERVER_ + #include "extensions/xf86dgastr.h" + #endif + + #define XCONFIG_FLAGS_ONLY + #include "xf86_Config.h" + + #include "s3reg.h" + #include "s3.h" + + + extern int nonMuxMaxClock; + extern int nonMuxMaxMemory; + extern int pixMuxMinClock; + extern int pixMuxMinWidth; + extern Bool allowPixMuxInterlace; + extern Bool pixMuxLimitedWidths; + extern Bool pixMuxPossible; + + + + /* + * S3PixMuxShift -- + * + * Determine pixmux shift. + * Clocks need to be setup by here and V_DBLCLK needs to be + * determined beforehand (ie. call S3SetSynthClock() first). + * I think this is a nice example of something that shouldn't + * be stuck in S3Init like it was in the original S3 server. + * Modularity. Modularity. Modularity + * + * MArk + */ + + static short S3PixMuxShift(DisplayModePtr mode) + { + short pixMuxShift; + + #ifdef S3_DEBUG + ErrorF("In S3PixMuxShift()\n"); + #endif + + + if (OFLG_ISSET(OPTION_ELSA_W2000PRO, &vga256InfoRec.options)) + pixMuxShift = (vga256InfoRec.clock[mode->Clock] > 120000) ? 2 : + ((vga256InfoRec.clock[mode->Clock] > 60000) ? 1 : 0); + else if (DAC_IS_IBMRGB528) + pixMuxShift = (vga256InfoRec.clock[mode->Clock] > 220000 && s3Bpp <= 2) ? + 2 : ((vga256InfoRec.clock[mode->Clock] > 110000) ? 1 : 0 ); + else if ((mode->Flags & V_DBLCLK) && (DAC_IS_TI3026) + && (OFLG_ISSET(CLOCK_OPTION_ICD2061A, &vga256InfoRec.clockOptions))) + pixMuxShift = (s3Bpp <= 2) ? 2 : 1; + else if ((mode->Flags & V_DBLCLK) && DAC_IS_TI3030) + pixMuxShift = 1; + else if (S3_964_SERIES(s3ChipId) && DAC_IS_IBMRGB) { + pixMuxShift = (mode->Flags & V_DBLCLK) ? 1 : 0; + if (s3Bpp == 4) + pixMuxShift = 0; /* cf CR67 */ + } else if (S3_964_SERIES(s3ChipId) && DAC_IS_TI3025) + pixMuxShift = (mode->Flags & V_DBLCLK) ? 1 : 0; + else if (S3_964_SERIES(s3ChipId) && DAC_IS_BT485_SERIES) + pixMuxShift = (mode->Flags & V_DBLCLK) ? 1 : 0; + else if (S3_801_928_SERIES(s3ChipId) && DAC_IS_SC15025) + pixMuxShift = -(s3Bpp>>1); /* for 16/32 bpp */ + else if (S3_864_SERIES(s3ChipId) || S3_805_I_SERIES(s3ChipId)) + pixMuxShift = -(s3Bpp>>1); /* for 16/32 bpp */ + else if (S3_TRIOxx_SERIES(s3ChipId)) + pixMuxShift = -(s3Bpp == 2); + else if (S3_x64_SERIES(s3ChipId)) + pixMuxShift = 0; + else if ((S3_928_SERIES(s3ChipId) && + (DAC_IS_TI3020 || DAC_IS_BT485_SERIES)) && s3PixelMultiplexing) { + if (s3Bpp == 4) pixMuxShift = 0; /* 32 bit */ + else if (s3Bpp == 2) pixMuxShift = 1; /* 16 bit */ + else pixMuxShift = 2; /* 8 bit */ + } else if (s3PixelMultiplexing) + pixMuxShift = 2; + else + pixMuxShift = 0; + + return pixMuxShift; + } + + + + + + /* + * S3SetSynthClock -- + * + * For programmable clocks, fill in the SynthClock value + * and set V_DBLCLK as required for each mode + * + */ + + static void S3SetSynthClock(DisplayModePtr mode) + { + #ifdef S3_DEBUG + ErrorF("In S3SetSynthClock()\n"); + #endif + + mode->SynthClock = vga256InfoRec.clock[mode->Clock]; + + switch(s3RamdacType) { + case NORMAL_DAC: + /* only suports 8bpp -- nothing to do */ + break; + case BT485_DAC: + { + int c; + if (OFLG_ISSET(OPTION_STB_PEGASUS, &vga256InfoRec.options) || + OFLG_ISSET(OPTION_MIRO_MAGIC_S4, &vga256InfoRec.options)) + c = 85000; + else if (S3_964_SERIES(s3ChipId) && s3Bpp == 4) + c = 90000; + else + c = 67500; + if (mode->SynthClock > c) { + mode->SynthClock /= 2; + mode->Flags |= V_DBLCLK; + } + } + break; + case ATT20C505_DAC: + if (mode->SynthClock > 90000) { + mode->SynthClock /= 2; + mode->Flags |= V_DBLCLK; + } + break; + case TI3020_DAC: + if (mode->SynthClock > 100000) { + mode->SynthClock /= 2; + mode->Flags |= V_DBLCLK; + } + break; + case TI3025_DAC: + if (mode->SynthClock > 80000) { + /* the SynthClock will be divided and clock doubled by the PLL */ + mode->Flags |= V_DBLCLK; + } + break; + case TI3026_DAC: /* IBMRGB??? */ + case TI3030_DAC: + if (OFLG_ISSET(CLOCK_OPTION_ICD2061A, &vga256InfoRec.clockOptions)) + { + /* + * for the mixed Ti3026/3030 + ICD2061A cases we need to split + * at 120MHz; Since the ICD2061A clock code dislikes 120MHz + * we already double for that + */ + if (mode->SynthClock >= 120000) { + mode->Flags |= V_DBLCLK; + mode->SynthClock /= 2; + } + + } else { + /* + * use the Ti3026/3030 clock + */ + if (mode->SynthClock > 80000) { + /* + * the SynthClock will be divided and clock doubled + * by the PLL + */ + mode->Flags |= V_DBLCLK; + } + } + break; + case IBMRGB524_DAC: + case IBMRGB525_DAC: + case IBMRGB528_DAC: + if (mode->SynthClock > 80000 || S3_968_SERIES(s3ChipId)) + mode->Flags |= V_DBLCLK; + break; + case ATT20C498_DAC: + case ATT22C498_DAC: + case ATT20C409_DAC: + case STG1700_DAC: + case STG1703_DAC: + case S3_SDAC_DAC: + switch (s3Bpp) { + case 1: + /* + * This one depends on pixel multiplexing for 8bpp. + * Although existing code implies it depends on ramdac + * clock doubling instead (are the two tied together?). + * CEG: Yes, if the AT&T dac is in pixmux mode, the clock + * must be halved (and the DBLCLK flag set, go figure). + */ + if (( DAC_IS_ATT20C498 && mode->SynthClock > nonMuxMaxClock) + || (!DAC_IS_ATT20C498 && mode->SynthClock > 67500) + || (mode->Flags & V_PIXMUX)) { + if (!(DAC_IS_SDAC)) { + mode->SynthClock /= 2; + mode->Flags |= V_DBLCLK; + } + } + break; + case 2: + /* No change for 16bpp */ + break; + case 4: + mode->SynthClock *= 2; + break; + } + break; + case S3_TRIO32_DAC: + case S3_TRIO64_DAC: + switch (s3Bpp) { + case 1: + #if 0 + + /* XXXX mode->SynthClock /= 2 might be better with sr15 &= ~0x40 + in s3init.c if screen wouldn't completely blank... */ + if (mode->SynthClock > nonMuxMaxClock) { + mode->SynthClock /= 2; + mode->Flags |= V_DBLCLK; + } + #endif + break; + case 2: + case 4: + /* No change for 16bpp and 24bpp */ + break; + } + break; + case ATT20C490_DAC: + case SS2410_DAC: /* just guessing ( based on 490 ) */ + case SC1148x_DAC: + case SC15025_DAC: + case S3_GENDAC_DAC: + if (s3Bpp > 1) + mode->SynthClock *= s3Bpp; + break; + default: + /* Do nothing */ + break; + } + + } + + + + /* + * S3SetupModePrivate -- + * + * Need to know if you are using V_DBLCLK first. + */ + + static void S3SetupModePrivate(DisplayModePtr mode) + { + #ifdef S3_DEBUG + ErrorF("In S3SetupModePrivate()\n"); + #endif + + /* couldn't we set this up in the modeline validation stage and add + one more element to it - the flag that I talked about in + S3Init() ? MArk */ + if(!mode->PrivSize || !mode->Private) { + mode->PrivSize = S3_MODEPRIV_SIZE; + mode->Private = (INT32 *)Xcalloc(sizeof(INT32) * S3_MODEPRIV_SIZE); + } + + mode->Private[0] = 0; + + /***********************************************\ + | Set default for S3_INVERT_VCLK | + \***********************************************/ + + + if (!(mode->Private[0] & (1 << S3_INVERT_VCLK))) { + if (DAC_IS_TI3026 && (s3BiosVendor == DIAMOND_BIOS || + OFLG_ISSET(OPTION_DIAMOND, + &vga256InfoRec.options))) + mode->Private[S3_INVERT_VCLK] = 1; + else if (DAC_IS_TI3030) + if ((s3Bpp == 2 && (mode->Flags & V_DBLCLK)) || s3Bpp == 4) + mode->Private[S3_INVERT_VCLK] = 1; + else + mode->Private[S3_INVERT_VCLK] = 0; + else if (DAC_IS_IBMRGB) + if (s3Bpp == 4) + mode->Private[S3_INVERT_VCLK] = 0; + else if (s3BiosVendor == STB_BIOS && s3Bpp == 2 + && vga256InfoRec.clock[mode->Clock] > 125000 + && vga256InfoRec.clock[mode->Clock] < 175000) + mode->Private[S3_INVERT_VCLK] = 0; + else if ((s3BiosVendor == NUMBER_NINE_BIOS || + s3BiosVendor == HERCULES_BIOS) && + S3_968_SERIES(s3ChipId)) + mode->Private[S3_INVERT_VCLK] = 0; + else + mode->Private[S3_INVERT_VCLK] = 1; + else + mode->Private[S3_INVERT_VCLK] = 0; + mode->Private[0] |= 1 << S3_INVERT_VCLK; + } + + /***********************************************\ + | Set default for S3_BLANK_DELAY | + \***********************************************/ + + if (!(mode->Private[0] & (1 << S3_BLANK_DELAY))) { + mode->Private[0] |= (1 << S3_BLANK_DELAY); + if (S3_964_SERIES(s3ChipId) && DAC_IS_BT485_SERIES) { + if ((mode->Flags & V_DBLCLK) || s3Bpp > 1) + mode->Private[S3_BLANK_DELAY] = 0x00; + else + mode->Private[S3_BLANK_DELAY] = 0x01; + } else if (DAC_IS_TI3025) { + if (s3Bpp == 1) + if (mode->Flags & V_DBLCLK) + mode->Private[S3_BLANK_DELAY] = 0x02; + else + mode->Private[S3_BLANK_DELAY] = 0x03; + else if (s3Bpp == 2) + if (mode->Flags & V_DBLCLK) + mode->Private[S3_BLANK_DELAY] = 0x00; + else + mode->Private[S3_BLANK_DELAY] = 0x01; + else /* (s3Bpp == 4) */ + mode->Private[S3_BLANK_DELAY] = 0x00; + } else if (DAC_IS_TI3026) { + if (s3BiosVendor == DIAMOND_BIOS + || OFLG_ISSET(OPTION_DIAMOND, &vga256InfoRec.options)) { + if (s3Bpp == 1) + mode->Private[S3_BLANK_DELAY] = 0x72; + else if (s3Bpp == 2) + mode->Private[S3_BLANK_DELAY] = 0x73; + else /*if (s3Bpp == 4)*/ + mode->Private[S3_BLANK_DELAY] = 0x75; + } else { + if (s3Bpp == 1) + mode->Private[S3_BLANK_DELAY] = 0x00; + else if (s3Bpp == 2) + mode->Private[S3_BLANK_DELAY] = 0x01; + else /*if (s3Bpp == 4)*/ + mode->Private[S3_BLANK_DELAY] = 0x00; + } + } else if (DAC_IS_TI3030){ + if (s3Bpp == 1 || (s3Bpp == 2 && !(mode->Flags & V_DBLCLK))) + mode->Private[S3_BLANK_DELAY] = 0x01; + else + mode->Private[S3_BLANK_DELAY] = 0x00; + } else if (DAC_IS_IBMRGB) { + if (s3BiosVendor == GENOA_BIOS) { + mode->Private[S3_BLANK_DELAY] = 0x00; + } + else if (s3BiosVendor == STB_BIOS) { + if (s3Bpp == 1 && vga256InfoRec.clock[mode->Clock] > 50000) + mode->Private[S3_BLANK_DELAY] = 0x55; + else + mode->Private[S3_BLANK_DELAY] = 0x00; + } + else if (s3BiosVendor == HERCULES_BIOS) { + if (S3_968_SERIES(s3ChipId)) { + mode->Private[S3_BLANK_DELAY] = 0x00; + } + else { + mode->Private[S3_BLANK_DELAY] = (4/s3Bpp) - 1; + if (mode->Flags & V_DBLCLK) + mode->Private[S3_BLANK_DELAY] >>= 1; + } + } + else + mode->Private[S3_BLANK_DELAY] = 0x00; + } else { + mode->Private[S3_BLANK_DELAY] = 0x00; + } + } + + /***************************************\ + | Set default for S3_EARLY_SC | + \***************************************/ + + if (!(mode->Private[0] & (1 << S3_EARLY_SC))) { + mode->Private[0] |= 1 << S3_EARLY_SC; + if (DAC_IS_TI3025) { + if (OFLG_ISSET(OPTION_NUMBER_NINE,&vga256InfoRec.options)) + mode->Private[S3_EARLY_SC] = 1; + else + mode->Private[S3_EARLY_SC] = 0; + } else if ((DAC_IS_TI3026 || DAC_IS_TI3030) + && OFLG_ISSET(CLOCK_OPTION_ICD2061A, + &vga256InfoRec.clockOptions)) { + if (s3Bpp == 2 && (mode->Flags & V_DBLCLK)) + mode->Private[S3_EARLY_SC] = 1; + else + mode->Private[S3_EARLY_SC] = 0; + } else if (DAC_IS_TI3026 + && OFLG_ISSET(CLOCK_OPTION_ICD2061A, + &vga256InfoRec.clockOptions)) { + if (s3Bpp == 2 && (mode->Flags & V_DBLCLK)) + mode->Private[S3_EARLY_SC] = 1; + else + mode->Private[S3_EARLY_SC] = 0; + } else if (DAC_IS_IBMRGB) { + if (s3BiosVendor == GENOA_BIOS) { + mode->Private[S3_EARLY_SC] = 0; + } + else if (s3BiosVendor == STB_BIOS) { + if (s3Bpp == 2 && vga256InfoRec.clock[mode->Clock] > 125000) + mode->Private[S3_EARLY_SC] = 0; + else if (s3Bpp == 4) + mode->Private[S3_EARLY_SC] = 0; + else + mode->Private[S3_EARLY_SC] = 1; + } + else if (s3BiosVendor == HERCULES_BIOS) { + if (S3_968_SERIES(s3ChipId)) + mode->Private[S3_EARLY_SC] = 0; + else + mode->Private[S3_EARLY_SC] = 0; + } + else + mode->Private[S3_EARLY_SC] = 0; + } else { + mode->Private[S3_EARLY_SC] = 0; + } + } + } + + /* + * S3MuxOrNot -- + * + */ + + unsigned char S3MuxOrNot(DisplayModePtr mode) + { + unsigned char verdict = 0x00; + + #ifdef S3_DEBUG + ErrorF("In S3MuxOrNot()\n"); + #endif + + /* Find out if the mode requires pixmux */ + + if ((s3Bpp == 1) && s3ATT498PixMux && !DAC_IS_SDAC && + (S3_864_SERIES(s3ChipId) || S3_805_I_SERIES(s3ChipId)) + && !OFLG_ISSET(CLOCK_OPTION_PROGRAMABLE, + &vga256InfoRec.clockOptions)) { + if (mode->Clock > 15) + verdict |= MUSTMUX; + } + + if (vga256InfoRec.clock[mode->Clock] > nonMuxMaxClock) { + verdict |= MUSTMUX; + } + + if (vga256InfoRec.videoRam > nonMuxMaxMemory) + verdict |= MUSTMUX; + + /* Really? virtual size is not exactly memory usage (MArk) */ + if ((OFLG_ISSET(OPTION_STB_PEGASUS, &vga256InfoRec.options) || + OFLG_ISSET(OPTION_MIRO_MAGIC_S4, &vga256InfoRec.options)) && + vga256InfoRec.virtualX * vga256InfoRec.virtualY > 2*1024*1024) { + verdict |= MUSTMUX; + } + + + /* Find out if the mode can't be used with pixmux */ + + if (mode->HDisplay < pixMuxMinWidth) + verdict |= CANTMUX; + + if ((mode->Flags & V_INTERLACE) && !allowPixMuxInterlace) + verdict |= CANTMUX; + + if (vga256InfoRec.clock[mode->Clock] < pixMuxMinClock) + verdict |= CANTMUX; + + if((verdict == (MUSTMUX | CANTMUX))) + ErrorF("%s: %s: Error! Conflicting multiplexing requirements for " + "mode \"%s\"\n", vga256InfoRec.name, vga256InfoRec.chipset, + mode->name); + + return verdict; + } + + + + + /* + * S3GetWidth -- + * + */ + + int S3GetWidth(int width) + { + if (pixMuxPossible && pixMuxLimitedWidths) { + /* NOTE: this happens if pixmux is merely possible. + A casualty of my method (MArk). */ + if (width <= 1024) + return 1024; + } else if (S3_911_SERIES(s3ChipId)) { + return 1024; + } else { + if (width <= 640) + return 640; + else if (width <= 800) + return 800; + else if (width <= 1024) + return 1024; + else if ((width <= 1152) && + ( S3_801_REV_C(s3ChipId) + || S3_805_I_SERIES(s3ChipId) + || S3_928_REV_E(s3ChipId) + || S3_x64_SERIES(s3ChipId))) + return 1152; + else if (width <= 1280) + return 1280; + else if ((width <= 1600) && + ((S3_928_REV_E(s3ChipId) && + !(OFLG_ISSET(OPTION_NUMBER_NINE, &vga256InfoRec.options) && + (s3Bpp == 1))) || S3_x64_SERIES(s3ChipId))) + return 1600; + } + + return 2048; + } + + + /* + * S3RetraceWait -- + * + */ + + void S3RetraceWait(void) + { + outb(vgaCRIndex, 0x17); /* is that better ? MArk */ + if(inb(vgaCRReg) & 0x80) { + while (inb(vgaIOBase + 0x0A) & 0x08); + while (!(inb(vgaIOBase + 0x0A) & 0x08)); + } + } + + + /* + * S3Unlock -- + * + */ + + void S3Unlock(void) + { + outb(vgaCRIndex, 0x38); outb(vgaCRReg, 0x48); + outb(vgaCRIndex, 0x39); outb(vgaCRReg, 0xa5); + } + + /* + * S3Lock -- + * + * I don't actually use this one (MArk) + */ + + void S3Lock(void) + { + outb(vgaCRIndex, 0x38); outb(vgaCRReg, 0x00); + outb(vgaCRIndex, 0x39); outb(vgaCRReg, 0x5A); + } + + + /* + * S3BankZero -- + * + */ + + void S3BankZero() + { + unsigned char tmp; + + outb(vgaCRIndex, 0x35); + tmp = inb(vgaCRReg) & 0xf0; + outb(vgaCRReg, tmp); + /* but wait, there's more! */ + if(S3_801_928_SERIES(s3ChipId)) { + outb(vgaCRIndex, 0x51); + tmp = inb(vgaCRReg) & 0xf3; + outb(vgaCRReg, tmp); + } + } + + + + /* + * S3FillInModeInfo -- + * + */ + + + void S3FillInModeInfo(DisplayModePtr mode) + { + short pixMuxShift = 0; + Bool changed=FALSE; + int oldCrtcHSyncStart, oldCrtcHSyncEnd, oldCrtcHTotal; + + #ifdef S3_DEBUG + ErrorF("In S3FillInModeInfo()\n"); + #endif + + /* Do we need this if we aren't using a programmable clock? (MArk) */ + S3SetSynthClock(mode); + + if (S3_964_SERIES(s3ChipId)) + S3SetupModePrivate(mode); + + pixMuxShift = S3PixMuxShift(mode); + + if (!mode->CrtcHAdjusted) { + if (s3Bpp == 3 && S3_968_SERIES(s3ChipId) && + (DAC_IS_TI3026 || DAC_IS_TI3030)) { + mode->CrtcHTotal = (mode->CrtcHTotal * 3) / 4; + mode->CrtcHDisplay = (mode->CrtcHDisplay * 3) / 4; + mode->CrtcHSyncStart = (mode->CrtcHSyncStart * 3) / 4; + mode->CrtcHSyncEnd = (mode->CrtcHSyncEnd * 3) / 4; + mode->CrtcHSkew = (mode->CrtcHSkew * 3) / 4; + } + if (pixMuxShift > 0) { + /* now divide the horizontal timing parameters as required */ + mode->CrtcHTotal >>= pixMuxShift; + mode->CrtcHDisplay >>= pixMuxShift; + mode->CrtcHSyncStart >>= pixMuxShift; + mode->CrtcHSyncEnd >>= pixMuxShift; + mode->CrtcHSkew >>= pixMuxShift; + } + else if (pixMuxShift < 0) { + /* now multiply the horizontal timing parameters as required */ + mode->CrtcHTotal <<= -pixMuxShift; + mode->CrtcHDisplay <<= -pixMuxShift; + mode->CrtcHSyncStart <<= -pixMuxShift; + mode->CrtcHSyncEnd <<= -pixMuxShift; + mode->CrtcHSkew <<= -pixMuxShift; + } + mode->CrtcHAdjusted = TRUE; + } + + /*************************************************************\ + | Do some sanity checks on the horizontal timing parameters | + \*************************************************************/ + + oldCrtcHSyncStart = mode->CrtcHSyncStart; + oldCrtcHSyncEnd = mode->CrtcHSyncEnd; + oldCrtcHTotal = mode->CrtcHTotal; + if (mode->CrtcHTotal > 4096) { /* CrtcHTotal/8 is a 9 bit value */ + mode->CrtcHTotal = 4096; + changed = TRUE; + } + if (mode->CrtcHSyncEnd >= mode->CrtcHTotal) { + mode->CrtcHSyncEnd = mode->CrtcHTotal - 1; + changed = TRUE; + } + if (mode->CrtcHSyncStart >= mode->CrtcHSyncEnd) { + mode->CrtcHSyncStart = mode->CrtcHSyncEnd - 1; + changed = TRUE; + } + if ((DAC_IS_TI3030 || DAC_IS_IBMRGB528) && s3Bpp==1) { + /* for 128bit bus we need multiple of 16 8bpp pixels... */ + if (mode->CrtcHTotal & 0x0f) { + mode->CrtcHTotal = (mode->CrtcHTotal + 0x0f) & ~0x0f; + changed = TRUE; + } + } + if (s3Bpp == 3) { + /* for packed 24bpp CrtcHTotal must be multiple of 3*8... */ + if ((mode->CrtcHTotal >> 3) % 3 != 0) { + mode->CrtcHTotal >>= 3; + mode->CrtcHTotal += 3 - mode->CrtcHTotal % 3; + mode->CrtcHTotal <<= 3; + changed = TRUE; + } + } + if (changed) { + ErrorF("%s %s: mode line has to be modified ...\n", + XCONFIG_PROBED, vga256InfoRec.name); + ErrorF("\t\tfrom %4d %4d %4d %4d %4d %4d %4d %4d\n" + ,mode->HDisplay, mode->HSyncStart, mode->HSyncEnd, mode->HTotal + ,mode->VDisplay, mode->VSyncStart, mode->VSyncEnd, mode->VTotal + ); + if(pixMuxShift < 0) + ErrorF("\t\tto %4d %4d %4d %4d %4d %4d %4d %4d\n", + mode->CrtcHDisplay >> -pixMuxShift, + mode->CrtcHSyncStart >> -pixMuxShift, + mode->CrtcHSyncEnd >> -pixMuxShift, + mode->CrtcHTotal >> -pixMuxShift, + mode->VDisplay, mode->VSyncStart, mode->VSyncEnd, mode->VTotal + ); + else + ErrorF("\t\tto %4d %4d %4d %4d %4d %4d %4d %4d\n", + mode->CrtcHDisplay << pixMuxShift, + mode->CrtcHSyncStart << pixMuxShift, + mode->CrtcHSyncEnd << pixMuxShift, + mode->CrtcHTotal << pixMuxShift, + mode->VDisplay, mode->VSyncStart, mode->VSyncEnd, mode->VTotal + ); + } + + + } + + + void S3SavePalette(LUTENTRY* pal) + { + register short i; + + outb(DAC_R_INDEX, 0); + for (i=0; i < 256; i++) { + pal[i].r = inb(DAC_DATA); + pal[i].g = inb(DAC_DATA); + pal[i].b = inb(DAC_DATA); + } + } + + + void S3RestorePalette(LUTENTRY* pal) + { + register short i; + + outb(DAC_W_INDEX, 0); + for (i=0; i < 256; i++) { + outb(DAC_DATA, pal[i].r); + outb(DAC_DATA, pal[i].g); + outb(DAC_DATA, pal[i].b); + } + } *** /dev/null Tue Jun 30 15:23:07 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/s3probe.c Fri Mar 6 16:54:03 1998 *************** *** 0 **** --- 1,897 ---- + /* $TOG: s3probe.c /main/1 1998/03/06 16:55:41 kaleb $ */ + + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/s3probe.c,v 1.1.2.4 1998/02/24 13:54:26 hohndel Exp $ */ + /* + * + * Copyright 1995-1997 The XFree86 Project, Inc. + * + */ + #include "X.h" + #include "input.h" + #include "screenint.h" + + #include "compiler.h" + #include "xf86.h" + #include "xf86Priv.h" + #include "xf86_OSlib.h" + #include "xf86_HWlib.h" + #include "xf86_PCI.h" + #include "vga.h" + #include "vgaPCI.h" + + #ifdef XFreeXDGA + #include "X.h" + #include "Xproto.h" + #include "scrnintstr.h" + #include "servermd.h" + #define _XF86DGA_SERVER_ + #include "extensions/xf86dgastr.h" + #endif + + #define XCONFIG_FLAGS_ONLY + #include "xf86_Config.h" + + #include "s3reg.h" + #include "s3.h" + + + static SymTabRec s3DacTable[] = { + { NORMAL_DAC, "normal" }, + { BT485_DAC, "bt485" }, + { BT485_DAC, "bt9485" }, + { ATT20C505_DAC, "att20c505" }, + { TI3020_DAC, "ti3020" }, + { ATT20C498_DAC, "att20c498" }, + { ATT20C498_DAC, "att21c498" }, + { ATT22C498_DAC, "att22c498" }, + { TI3025_DAC, "ti3025" }, + { TI3026_DAC, "ti3026" }, + { TI3030_DAC, "ti3030" }, + { IBMRGB525_DAC, "ibm_rgb514" }, + { IBMRGB524_DAC, "ibm_rgb524" }, + { IBMRGB525_DAC, "ibm_rgb525" }, + { IBMRGB524_DAC, "ibm_rgb526" }, + { IBMRGB528_DAC, "ibm_rgb528" }, + { ATT20C490_DAC, "att20c490" }, + { ATT20C490_DAC, "att20c491" }, + { ATT20C490_DAC, "ch8391" }, + { SC1148x_DAC, "sc11482" }, + { SC1148x_DAC, "sc11483" }, + { SC1148x_DAC, "sc11484" }, + { SC1148x_DAC, "sc11485" }, + { SC1148x_DAC, "sc11487" }, + { SC1148x_DAC, "sc11489" }, + { SC15025_DAC, "sc15025" }, + { STG1700_DAC, "stg1700" }, + { STG1703_DAC, "stg1703" }, + { S3_SDAC_DAC, "s3_sdac" }, + { S3_SDAC_DAC, "ics5342" }, + { S3_GENDAC_DAC, "s3gendac" }, + { S3_GENDAC_DAC, "ics5300" }, + { S3_TRIO32_DAC, "s3_trio32" }, + { S3_TRIO64_DAC, "s3_trio64" }, + { S3_TRIO64_DAC, "s3_trio" }, + { ATT20C409_DAC, "att20c409" }, + { SS2410_DAC, "ss2410" }, + { S3_TRIO64V2_DAC, "s3_trio64v2" }, + { -1, "" } + }; + + static unsigned S3_IOPorts[] = { DISP_STAT, H_TOTAL, H_DISP, H_SYNC_STRT, + H_SYNC_WID, V_TOTAL, V_DISP, V_SYNC_STRT, V_SYNC_WID, DISP_CNTL, + ADVFUNC_CNTL, SUBSYS_STAT, SUBSYS_CNTL, ROM_PAGE_SEL, CUR_Y, CUR_X, + DESTY_AXSTP, DESTX_DIASTP, ERR_TERM, MAJ_AXIS_PCNT, GP_STAT, CMD, + SHORT_STROKE, BKGD_COLOR, FRGD_COLOR, WRT_MASK, RD_MASK, COLOR_CMP, + BKGD_MIX, FRGD_MIX, MULTIFUNC_CNTL, PIX_TRANS, PIX_TRANS_EXT, + }; + + #define Num_S3_IOPorts (sizeof(S3_IOPorts)/sizeof(S3_IOPorts[0])) + + + /* + * S3Probe -- + * + * This is essentially what s3Probe was in the old + * S3 server but with some things removed or moved. The + * SVGA server prints out some things for us (like videoram) + * so we don't duplicate the messages in here. A major + * modification has been letting the SVGA server handle + * the modeline validation. Since modelines are not validated + * from within S3Probe as they were in the old server, the + * virtual size and display widths, etc... cannot be determined + * in this function. They are determined in S3FbInit. See + * the discussion in s3fbinit.c for more details. + * + * MArk. + * + */ + + /* + * These characterize a RAMDACs pixel multiplexing capabilities and + * requirements: + * + * pixMuxPossible - pixmux is supported for the current RAMDAC + * allowPixMuxInterlace - pixmux supports interlaced modes + * allowPixMuxSwitching - possible to use pixmux for some modes + * and non-pixmux for others + * pixMuxMinWidth - smallest physical width supported in + * pixmux mode + * nonMuxMaxClock - highest dot clock supported without pixmux + * pixMuxMinClock - lowest dot clock supported with pixmux + * nonMuxMaxMemory - max video memory accessible without pixmux + * pixMuxLimitedWidths - pixmux only works for logical display + * widths 1024 and 2048 + * pixMuxInterlaceOK - FALSE if pixmux isn't possible because + * there is an interlaced mode present + * pixMuxWidthOK - FALSE if pixmux isn't possible because + * there is mode with too small a width + * pixMuxClockOK - FALSE if pixmux isn't possible because + * of a clock with too low of a value. + */ + + Bool pixMuxPossible = FALSE; + Bool allowPixMuxInterlace = FALSE; + Bool allowPixMuxSwitching = FALSE; + Bool pixMuxInterlaceOK = TRUE; + Bool pixMuxWidthOK = TRUE; + Bool pixMuxClockOK = TRUE; + int nonMuxMaxClock = 0; + int nonMuxMaxMemory = 8192; + int pixMuxMinWidth = 1024; + int pixMuxMinClock = 0; + Bool pixMuxLimitedWidths = TRUE; + + + static Bool VirtualNotGiven = FALSE; + + + Bool S3Probe() + { + unsigned char config; + int i; + + if (vga256InfoRec.chipset) { + if (StrCaseCmp(vga256InfoRec.chipset,S3Ident(0))) + return(FALSE); + } + + + /* check for fake S3 chips :-(( */ + if (vgaPCIInfo && (vgaPCIInfo->Vendor == PCI_VENDOR_SIGMADESIGNS || + vgaPCIInfo->Vendor == PCI_VENDOR_INTERGRAPHICS)) { + char *vendor, chip[80]; + if (vgaPCIInfo->Vendor == PCI_VENDOR_SIGMADESIGNS) { + vendor = "Sigma Designs"; + if (vgaPCIInfo->ChipType == PCI_CHIP_SD_REALMAGIG64GX) + strcpy(chip,"REALmagic64/GX (SD 6425) chip"); + else + sprintf(chip,"unknown chip (chip_id 0x%x)",vgaPCIInfo->ChipType); + } + else { + vendor = "Intergraphics"; + if (vgaPCIInfo->Vendor == PCI_CHIP_INTERG_1680) + strcpy(chip,"IGA-1680 chip"); + else if (vgaPCIInfo->Vendor == PCI_CHIP_INTERG_1682) + strcpy(chip,"IGA-1682 chip"); + else + sprintf(chip,"unknown chip (chip_id 0x%x)",vgaPCIInfo->ChipType); + } + ErrorF("\n%s %s: WARNING: %s %s detected!\n" + "\tNote: this chip is not a product of S3, Inc., and it is not\n" + "\tcompatible with the XFree86 S3 drivers. We understand that\n" + "\tsome video cards are being sold with these chips relabeled\n" + "\tas S3 Inc. chips, including S3's logo. They are NOT S3 chips.\n" + "\tPlease see http://www.s3.com\n\n", + XCONFIG_PROBED, vga256InfoRec.name); + } + + + S3EnterLeave(ENTER); /* this will unlock the regs. */ + + + /***********************************************\ + | Is it an S3? | + \***********************************************/ + + + /* Lock */ + outb(vgaCRIndex, 0x38); outb(vgaCRReg, 0x00); + + /* Make sure we can't write when locked */ + if (testinx2(vgaCRIndex, 0x35, 0x0f)) { + S3EnterLeave(LEAVE); + return(FALSE); + } + + /* Unlock */ + outb(vgaCRIndex, 0x38); outb(vgaCRReg, 0x48); + + /* Make sure we can write when unlocked */ + if (!testinx2(vgaCRIndex, 0x35, 0x0f)) { + S3EnterLeave(LEAVE); + return(FALSE); + } + + /* OK, it's an S3. So find out which one */ + + outb(vgaCRIndex, 0x30); + s3ChipId = inb(vgaCRReg); + + s3ChipRev = s3ChipId & 0x0f; + if (s3ChipId >= 0xe0) { + outb(vgaCRIndex, 0x2d); + s3ChipId = inb(vgaCRReg) << 8; + outb(vgaCRIndex, 0x2e); + s3ChipId |= inb(vgaCRReg); + outb(vgaCRIndex, 0x2f); + s3ChipRev = inb(vgaCRReg); + } + + if (vga256InfoRec.chipID) { + ErrorF("%s %s: S3 chipset override, using chip_id = 0x%02x instead of 0x%02x\n", + XCONFIG_GIVEN, vga256InfoRec.name, vga256InfoRec.chipID, s3ChipId); + s3ChipId = vga256InfoRec.chipID; + } + if (vga256InfoRec.chipRev) { + ErrorF("%s %s: S3 chipset override, using chip_rev = %x instead of %x\n", + XCONFIG_GIVEN, vga256InfoRec.name, vga256InfoRec.chipRev, s3ChipRev); + s3ChipRev = vga256InfoRec.chipRev; + } + + /* We complain (and bail) when we have no idea what S3 chip it is */ + + if (S3_ANY_ViRGE_SERIES(s3ChipId)) { + ErrorF("%s %s: S3 ViRGE chipset: please load \"libs3v.a\" module\n", + XCONFIG_PROBED, vga256InfoRec.name); + S3EnterLeave(LEAVE); + return(FALSE); + } + + if (!S3_ANY_SERIES(s3ChipId)) { + ErrorF("%s %s: Unknown S3 chipset: chip_id = 0x%02x rev. %x\n", + XCONFIG_PROBED,vga256InfoRec.name,s3ChipId,s3ChipRev); + S3EnterLeave(LEAVE); + return(FALSE); + } + + + /* We print out the type even though we may not have support for + it in this driver */ + + outb(vgaCRIndex, 0x36); + config = inb(vgaCRReg); + + if (xf86Verbose) { + if (S3_x64_SERIES(s3ChipId)) { + char *chipname = "unknown"; + if (S3_868_SERIES(s3ChipId)) { + chipname = "868"; + } else if (S3_866_SERIES(s3ChipId)) { + chipname = "866"; + } else if (S3_864_SERIES(s3ChipId)) { + chipname = "864"; + } else if (S3_968_SERIES(s3ChipId)) { + chipname = "968"; + } else if (S3_964_SERIES(s3ChipId)) { + chipname = "964"; + } else if (S3_ViRGE_SERIES(s3ChipId)) { + chipname = "ViRGE"; + } else if (S3_TRIO32_SERIES(s3ChipId)) { + chipname = "Trio32"; + } else if (S3_TRIO64V_SERIES(s3ChipId)) { + chipname = "Trio64V+"; + } else if (S3_TRIO64UVP_SERIES(s3ChipId)) { + chipname = "Trio64UV+"; + } else if (S3_AURORA64VP_SERIES(s3ChipId)) { + chipname = "Aurora64V+ (preliminary support; please report)"; + } else if (S3_TRIO64V2_SERIES(s3ChipId)) { + outb(vgaCRIndex, 0x39); + outb(vgaCRReg, 0xa5); + outb(vgaCRIndex, 0x6f); + if (inb(vgaCRReg) & 1) + chipname = "Trio64V2/GX"; + else + chipname = "Trio64V2/DX"; + } else if (S3_TRIO64_SERIES(s3ChipId)) { + chipname = "Trio64"; + } else if (S3_PLATO_PX_SERIES(s3ChipId)) { + chipname = "PLATO/PX (preliminary support; please report)"; + } + ErrorF("%s %s: chipset: %s rev. %x\n", + XCONFIG_PROBED, vga256InfoRec.name, chipname, s3ChipRev); + } else if (S3_801_928_SERIES(s3ChipId)) { + if (S3_801_SERIES(s3ChipId)) { + if (S3_805_I_SERIES(s3ChipId)) { + ErrorF("%s %s: chipset: 805i", + XCONFIG_PROBED, vga256InfoRec.name); + if ((config & 0x03) == 3) + ErrorF(" (ISA)"); + else + ErrorF(" (VL)"); + } + else if (!((config & 0x03) == 3)) + ErrorF("%s %s: chipset: 805", + XCONFIG_PROBED, vga256InfoRec.name); + else + ErrorF("%s %s: chipset: 801", + XCONFIG_PROBED, vga256InfoRec.name); + ErrorF(", "); + if (S3_801_REV_C(s3ChipId)) + ErrorF("rev C or above\n"); + else + ErrorF("rev A or B\n"); + } else if (S3_928_SERIES(s3ChipId)) { + char *pci = S3_928_P(s3ChipId) ? "-P" : ""; + if (S3_928_REV_E(s3ChipId)) + ErrorF("%s %s: chipset: 928%s, rev E or above\n", + XCONFIG_PROBED, vga256InfoRec.name, pci); + else + ErrorF("%s %s: chipset: 928%s, rev D or below\n", + XCONFIG_PROBED, vga256InfoRec.name, pci); + } + } else if (S3_911_SERIES(s3ChipId)) { + if (S3_911_ONLY(s3ChipId)) { + ErrorF("%s %s: chipset: 911 \n", + XCONFIG_PROBED, vga256InfoRec.name); + } else if (S3_924_ONLY(s3ChipId)) { + ErrorF("%s %s: chipset: 924\n", + XCONFIG_PROBED, vga256InfoRec.name); + } else { + ErrorF("%s %s: S3 chipset type unknown, chip_id = 0x%02x\n", + XCONFIG_PROBED, vga256InfoRec.name, s3ChipId); + } + } + } + + /* Here's where we bail if the driver doesn't have support for + the particular chipset */ + + if(S3_ViRGE_SERIES(s3ChipId)) { + ErrorF("The ViRGE chipset is unsupported by the s3_svga driver\n" + "\tPlease use the s3v driver instead\n"); + S3EnterLeave(LEAVE); + return(FALSE); + } + + if((!S3_TRIO64V_SERIES(s3ChipId) && !S3_x68_SERIES(s3ChipId)) || + OFLG_ISSET(OPTION_NO_MMIO, &vga256InfoRec.options)){ + ErrorF("%s %s: Using Port I/O\n", + XCONFIG_PROBED, vga256InfoRec.name); + } else { + s3newmmio = TRUE; + ErrorF("%s %s: Using new style S3 MMIO\n", + XCONFIG_PROBED, vga256InfoRec.name); + } + + /***************************************\ + | Set Some Options | + \***************************************/ + + #ifdef PC98 + if (OFLG_ISSET(OPTION_PW_MUX, &vga256InfoRec.options)) + OFLG_SET(OPTION_SPEA_MERCURY, &vga256InfoRec.options); + #endif + + if (OFLG_ISSET(OPTION_GENOA, &vga256InfoRec.options)) + s3BiosVendor = GENOA_BIOS; + else if (OFLG_ISSET(OPTION_STB, &vga256InfoRec.options)) + s3BiosVendor = STB_BIOS; + else if (OFLG_ISSET(OPTION_HERCULES, &vga256InfoRec.options)) + s3BiosVendor = HERCULES_BIOS; + else if (OFLG_ISSET(OPTION_NUMBER_NINE, &vga256InfoRec.options)) + s3BiosVendor = NUMBER_NINE_BIOS; + else if (OFLG_ISSET(OPTION_DIAMOND, &vga256InfoRec.options)) + s3BiosVendor = DIAMOND_BIOS; + + + if (OFLG_ISSET(OPTION_POWER_SAVER, &vga256InfoRec.options)) + s3PowerSaver = TRUE; + + if(s3newmmio) + if (OFLG_ISSET(OPTION_NOLINEAR_MODE, &vga256InfoRec.options)) { + ErrorF("Linear addressing is required for the s3_newmmio driver\n" + "\tPlease remove \"no_linear\" option from the XF86Config file\n"); + S3EnterLeave(LEAVE); + return(FALSE); + } + else + if (S3_911_SERIES(s3ChipId)) { + OFLG_SET(OPTION_NOLINEAR_MODE, &vga256InfoRec.options); + } + + + /***************************************\ + | LocalBus, EISA or PCI ? | + \***************************************/ + + + s3Localbus = ((config & 0x03) <= 2) || S3_928_P(s3ChipId); + + { + char* bustype = "PCI"; + + if (!S3_928_P(s3ChipId)) { + switch (config & 0x03) { + case 0: + bustype = "EISA\n"; + break; + case 1: + bustype = "386/486 localbus", + s3VLB = TRUE; + break; + case 3: + bustype = "ISA"; + break; + default: /* anything else is PCI */ + break; + } + } + if(xf86Verbose) + ErrorF("%s %s: bus type: %s\n", XCONFIG_PROBED, + vga256InfoRec.name, bustype); + } + + if(s3newmmio) { + if(OFLG_ISSET(OPTION_PCI_RETRY, &vga256InfoRec.options)) { + if(config & 0x02) { + ErrorF("%s %s: Using PCI retry\n", XCONFIG_GIVEN, + vga256InfoRec.name); + s3PCIRetry = TRUE; + } else { + ErrorF("%s %s: PCI retry only available on PCI bus\n" + "\t\tOption disabled\n", XCONFIG_GIVEN, vga256InfoRec.name); + OFLG_CLR(OPTION_PCI_RETRY, &vga256InfoRec.options); + } + } + } + + /***************************************\ + | Detect VideoRam amount | + \***************************************/ + + + if (!vga256InfoRec.videoRam) { + if (((config & 0x20) != 0) /* if bit 5 is a 1, then 512k RAM */ + && (!S3_964_SERIES(s3ChipId))) { + vga256InfoRec.videoRam = 512; + } else { /* must have more than 512k */ + if (S3_911_SERIES(s3ChipId)) { + vga256InfoRec.videoRam = 1024; + } else { + if (S3_PLATO_PX_SERIES(s3ChipId)) + vga256InfoRec.videoRam = (8-((config & 0xE0) >> 5)) * 512; + else switch ((config & 0xE0) >> 5) { /* look at bits 6 and 7 */ + case 0: + vga256InfoRec.videoRam = 4096; + break; + case 2: + vga256InfoRec.videoRam = 3072; + break; + case 3: + vga256InfoRec.videoRam = 8192; + break; + case 4: + vga256InfoRec.videoRam = 2048; + break; + case 5: + vga256InfoRec.videoRam = 6144; + break; + case 6: + vga256InfoRec.videoRam = 1024; + break; + } + } + } + } /* Gets printed out by svga server later */ + + if (vga256InfoRec.videoRam > 1024) + s3Mbanks = -1; + else + s3Mbanks = 0; + + /*****************************************************\ + | Determine card vendor to aid in clockchip detection | + \*****************************************************/ + + + /* stick that in here (MArk) */ + + /*******************************\ + | Determine RAMDAC | + \*******************************/ + + /* Is one given in the XF86Config? */ + if (vga256InfoRec.ramdac) { + s3RamdacType = xf86StringToToken(s3DacTable, vga256InfoRec.ramdac); + if (s3RamdacType < 0) { + ErrorF("%s %s: Unknown RAMDAC type \"%s\"\n", XCONFIG_GIVEN, + vga256InfoRec.name, vga256InfoRec.ramdac); + S3EnterLeave(LEAVE); + return(FALSE); + } + } + + /* if not given in XF86Config, probe for one */ + if(s3RamdacType == UNKNOWN_DAC) { + for (i = 1; s3Ramdacs[i].DacName; i++) { + if ((s3Ramdacs[i].DacProbe)()) { + s3RamdacType = i; + break; + } + } + } else { /* if given in XF86Config, verify it */ + if(!(s3Ramdacs[s3RamdacType].DacProbe)()) { + ErrorF("WARNING: Did not detect a ramdac of type \"%s\" as specified!\n", + s3Ramdacs[s3RamdacType].DacName); + /* but we accept the user's assertion */ + } + } + + /* If we still don't know the ramdac type, set it to NORMAL_DAC */ + if (s3RamdacType == UNKNOWN_DAC) { + if (xf86Verbose) + ErrorF("%s %s: Unknown ramdac. Setting type to \"normal_dac\".\n", + XCONFIG_PROBED, vga256InfoRec.name); + s3RamdacType = NORMAL_DAC; + } + + vga256InfoRec.ramdac = s3Ramdacs[s3RamdacType].DacName; + + if (xf86Verbose) { + ErrorF("%s %s: Ramdac type: %s or compatible.\n", + OFLG_ISSET(XCONFIG_RAMDAC, &vga256InfoRec.xconfigFlag) ? + XCONFIG_GIVEN : XCONFIG_PROBED, vga256InfoRec.name, + vga256InfoRec.ramdac); + } + + + /*******************************************************\ + | Set some SPEA specific options that had to wait until | + | after we knew what the ramdac was. | + \*******************************************************/ + + /* do something different here MArk */ + + /*******************************************************\ + | Now set the DAC speed if not already set | + \*******************************************************/ + + if(vga256InfoRec.bitsPerPixel > 8) + s3Bpp = vga256InfoRec.bitsPerPixel >> 3; + + i = s3Bpp - 1; + + if (vga256InfoRec.dacSpeeds[i] <= 0) { + vga256InfoRec.dacSpeeds[i] = s3Ramdacs[s3RamdacType].DacSpeeds[i]; + } else { + if(vga256InfoRec.dacSpeeds[i] > s3Ramdacs[s3RamdacType].DacSpeeds[i]) + ErrorF("WARNING!!! default dacSpeed limit for %i bpp has been " + "overridden\n\t %d MHz changed to %d MHz\n",s3Bpp << 3, + s3Ramdacs[s3RamdacType].DacSpeeds[i] / 1000, + vga256InfoRec.dacSpeeds[i] / 1000); + s3Ramdacs[s3RamdacType].DacSpeeds[i] = vga256InfoRec.dacSpeeds[i]; + } + + if (xf86Verbose) { + ErrorF("%s %s: Max RAMDAC speed for this depth: %d MHz\n", + OFLG_ISSET(XCONFIG_DACSPEED, &vga256InfoRec.xconfigFlag) ? + XCONFIG_GIVEN : XCONFIG_PROBED, vga256InfoRec.name, + vga256InfoRec.dacSpeeds[i] / 1000); + } + + /*******************************************************************\ + | Check that the depth requested is supported by the ramdac/chipset | + \*******************************************************************/ + + + if (S3_801_SERIES(s3ChipId)) { + if (s3Bpp > 2) { + ErrorF("Depths greater than 16bpp are not supported for 801/805 " + "chips.\n"); + S3EnterLeave(LEAVE); + return(FALSE); + } + } + else if (S3_911_SERIES(s3ChipId)) { + if (s3Bpp > 1) { + ErrorF("Depths greater than 8bpp are not supported for 911/924 " + "chips.\n"); + S3EnterLeave(LEAVE); + return(FALSE); + } + } + + if (!S3_868_SERIES(s3ChipId) && !S3_968_SERIES(s3ChipId)) { + if (s3Bpp == 3) { + ErrorF("Packed-pixel 24bpp depths are only supported for 868/968 " + "chips\n"); + S3EnterLeave(LEAVE); + return(FALSE); + } + } + + /* I guess these should return a status flag. Just 0 or 1 for now (MArk)*/ + if ((s3Ramdacs[s3RamdacType].PreInit)() <= 0) { + S3EnterLeave(LEAVE); + return(FALSE); + } + + if (xf86Verbose && pixMuxPossible) /* Best we can do (MArk) */ + ErrorF("%s %s: Operating RAMDAC in pixel multiplex mode\n", + XCONFIG_PROBED, vga256InfoRec.name); + + + /***************************************\ + | Last minute Clock Checks | + \***************************************/ + + /* Check that maxClock is not higher than dacSpeed */ + if (vga256InfoRec.maxClock > vga256InfoRec.dacSpeeds[s3Bpp - 1]) + vga256InfoRec.maxClock = vga256InfoRec.dacSpeeds[s3Bpp - 1]; + + /* Modify vga256InfoRec.maxClock if necessary */ + if(s3clockDoublingPossible) + s3maxRawClock *= 2; + if ((s3maxRawClock > 0) && (vga256InfoRec.maxClock > s3maxRawClock)) + vga256InfoRec.maxClock = s3maxRawClock; + + /* check DCLK limit of 100MHz for 866/868 */ + if (S3_866_SERIES(s3ChipId) || S3_868_SERIES(s3ChipId)) { + if (((s3Bpp==1 && !pixMuxPossible) || s3Bpp==2) + && vga256InfoRec.maxClock > 100000) + vga256InfoRec.maxClock = 100000; + else if (s3Bpp>2 && vga256InfoRec.maxClock > 50000) + vga256InfoRec.maxClock = 50000; + } + /* check DCLK limit of 95MHz for 864 */ + else if (S3_864_SERIES(s3ChipId)) { + if (((s3Bpp==1 && !pixMuxPossible) || s3Bpp==2) + && vga256InfoRec.maxClock > 95000) + vga256InfoRec.maxClock = 95000; + + /* for 24bpp the limit should be 95/2 == 47.5MHz + but I set the limit to 50MHz to allow VESA 800x600@72Hz */ + else if (s3Bpp>2 && vga256InfoRec.maxClock > 50000) + vga256InfoRec.maxClock = 50000; + } + + /***********************************************\ + | Set s3maxDisplayHeight and Width | + \***********************************************/ + + if (S3_911_SERIES(s3ChipId)) { + s3maxDisplayWidth = 1024; + s3maxDisplayHeight = 1024; + } else { + s3maxDisplayWidth = 2048; + s3maxDisplayHeight = 4096; + } + + if((vga256InfoRec.virtualX <= 0) || (vga256InfoRec.virtualY <= 0)) + VirtualNotGiven = TRUE; + else { /* Virtual size was given */ + if (vga256InfoRec.virtualX > s3maxDisplayWidth) { + ErrorF("%s: Virtual width (%d) is too large. Maximum is %d\n", + vga256InfoRec.name, vga256InfoRec.virtualX, s3maxDisplayWidth); + S3EnterLeave(LEAVE); + return (FALSE); + } + if (vga256InfoRec.virtualY > s3maxDisplayHeight) { + ErrorF("%s: Virtual height (%d) is too large. Maximum is %d\n", + vga256InfoRec.name, vga256InfoRec.virtualY, s3maxDisplayHeight); + S3EnterLeave(LEAVE); + return (FALSE); + } + + s3DisplayWidth = S3GetWidth(vga256InfoRec.virtualX); + s3BppDisplayWidth = s3DisplayWidth * s3Bpp; + } + + + + /***********************\ + | 8 bit DAC | + \***********************/ + + + + /* Is this correct? (MArk) */ + if((DAC_IS_SC15025 || DAC_IS_ATT498 || DAC_IS_STG1700 || DAC_IS_ATT20C409 || + DAC_IS_ATT490 || DAC_IS_BT485_SERIES || DAC_IS_TI3020_SERIES || + DAC_IS_TI3026 || DAC_IS_TI3030 || DAC_IS_IBMRGB) && + !OFLG_ISSET(OPTION_DAC_6_BIT, &vga256InfoRec.options)) { + s3DAC8Bit = TRUE; + OFLG_SET(OPTION_DAC_8_BIT, &vga256InfoRec.options); + } + + + if (OFLG_ISSET(OPTION_DAC_8_BIT, &vga256InfoRec.options) && !s3DAC8Bit) { + OFLG_CLR(OPTION_DAC_8_BIT, &vga256InfoRec.options); + ErrorF("%s %s: Option \"dac_8_bit\" not recognized for RAMDAC \"%s\"\n", + XCONFIG_PROBED, vga256InfoRec.name, vga256InfoRec.ramdac); + } + + + /*******************************\ + | Sync-On-Green | + \*******************************/ + + + if (DAC_IS_BT485_SERIES || DAC_IS_TI3020_SERIES || DAC_IS_TI3026 || + DAC_IS_TI3030 || DAC_IS_IBMRGB) { + if (OFLG_ISSET(OPTION_SYNC_ON_GREEN, &vga256InfoRec.options)) { + s3DACSyncOnGreen = TRUE; + if (xf86Verbose) + ErrorF("%s %s: Putting RAMDAC into sync-on-green mode\n", + XCONFIG_GIVEN, vga256InfoRec.name); + } + } + + + #ifdef XFreeXDGA + vga256InfoRec.directMode = XF86DGADirectPresent; + #endif + + vga256InfoRec.bankedMono = FALSE; + vga256InfoRec.chipset = S3Ident(0); + + /*******************************\ + | Set the Valid Options | + \*******************************/ + + /* if you see one that isn't used/needed anymore, please remove it (MArk) */ + + OFLG_SET(OPTION_LEGEND, &s3InfoRec.ChipOptionFlags); + OFLG_SET(OPTION_CLKDIV2, &s3InfoRec.ChipOptionFlags); + OFLG_SET(OPTION_NOACCEL, &s3InfoRec.ChipOptionFlags); + OFLG_SET(OPTION_NOLINEAR_MODE, &s3InfoRec.ChipOptionFlags); + if (!S3_x64_SERIES(s3ChipId)) + OFLG_SET(OPTION_NO_MEM_ACCESS, &s3InfoRec.ChipOptionFlags); + OFLG_SET(OPTION_SW_CURSOR, &s3InfoRec.ChipOptionFlags); + OFLG_SET(OPTION_BT485_CURS, &s3InfoRec.ChipOptionFlags); + OFLG_SET(OPTION_SHOWCACHE, &s3InfoRec.ChipOptionFlags); + OFLG_SET(OPTION_FB_DEBUG, &s3InfoRec.ChipOptionFlags); + OFLG_SET(OPTION_NO_FONT_CACHE, &s3InfoRec.ChipOptionFlags); + OFLG_SET(OPTION_NO_PIXMAP_CACHE, &s3InfoRec.ChipOptionFlags); + OFLG_SET(OPTION_TI3020_CURS, &s3InfoRec.ChipOptionFlags); + OFLG_SET(OPTION_TI3026_CURS, &s3InfoRec.ChipOptionFlags); + OFLG_SET(OPTION_IBMRGB_CURS, &s3InfoRec.ChipOptionFlags); + OFLG_SET(OPTION_DAC_8_BIT, &s3InfoRec.ChipOptionFlags); + OFLG_SET(OPTION_DAC_6_BIT, &s3InfoRec.ChipOptionFlags); + OFLG_SET(OPTION_SYNC_ON_GREEN, &s3InfoRec.ChipOptionFlags); + OFLG_SET(OPTION_SPEA_MERCURY, &s3InfoRec.ChipOptionFlags); + OFLG_SET(OPTION_NUMBER_NINE, &s3InfoRec.ChipOptionFlags); + OFLG_SET(OPTION_STB_PEGASUS, &s3InfoRec.ChipOptionFlags); + OFLG_SET(OPTION_MIRO_MAGIC_S4, &s3InfoRec.ChipOptionFlags); + #ifdef PC98 + OFLG_SET(OPTION_PCSKB, &s3InfoRec.ChipOptionFlags); + OFLG_SET(OPTION_PCSKB4, &s3InfoRec.ChipOptionFlags); + OFLG_SET(OPTION_PCHKB, &s3InfoRec.ChipOptionFlags); + OFLG_SET(OPTION_NECWAB, &s3InfoRec.ChipOptionFlags); + OFLG_SET(OPTION_PW805I, &s3InfoRec.ChipOptionFlags); + OFLG_SET(OPTION_PWLB, &s3InfoRec.ChipOptionFlags); + OFLG_SET(OPTION_PW968, &s3InfoRec.ChipOptionFlags); + OFLG_SET(OPTION_EPSON_MEM_WIN, &s3InfoRec.ChipOptionFlags); + OFLG_SET(OPTION_PW_MUX, &s3InfoRec.ChipOptionFlags); + OFLG_SET(OPTION_NOINIT, &s3InfoRec.ChipOptionFlags); + #endif + /* ELSA_W1000PRO isn't really required any more */ + OFLG_SET(OPTION_ELSA_W1000PRO, &s3InfoRec.ChipOptionFlags); + OFLG_SET(OPTION_ELSA_W2000PRO, &s3InfoRec.ChipOptionFlags); + OFLG_SET(OPTION_DIAMOND, &s3InfoRec.ChipOptionFlags); + OFLG_SET(OPTION_GENOA, &s3InfoRec.ChipOptionFlags); + OFLG_SET(OPTION_STB, &s3InfoRec.ChipOptionFlags); + OFLG_SET(OPTION_HERCULES, &s3InfoRec.ChipOptionFlags); + if (S3_928_P(s3ChipId)) + OFLG_SET(OPTION_PCI_HACK, &s3InfoRec.ChipOptionFlags); + OFLG_SET(OPTION_S3_964_BT485_VCLK, &s3InfoRec.ChipOptionFlags); + OFLG_SET(OPTION_SLOW_DRAM, &s3InfoRec.ChipOptionFlags); + OFLG_SET(OPTION_SLOW_EDODRAM, &s3InfoRec.ChipOptionFlags); + OFLG_SET(OPTION_SLOW_VRAM, &s3InfoRec.ChipOptionFlags); + OFLG_SET(OPTION_SLOW_DRAM_REFRESH, &s3InfoRec.ChipOptionFlags); + OFLG_SET(OPTION_FAST_VRAM, &s3InfoRec.ChipOptionFlags); + OFLG_SET(OPTION_TRIO32_FC_BUG, &s3InfoRec.ChipOptionFlags); + OFLG_SET(OPTION_S3_968_DASH_BUG, &s3InfoRec.ChipOptionFlags); + OFLG_SET(OPTION_TRIO64VP_BUG1, &s3InfoRec.ChipOptionFlags); + OFLG_SET(OPTION_TRIO64VP_BUG2, &s3InfoRec.ChipOptionFlags); + OFLG_SET(OPTION_TRIO64VP_BUG3, &s3InfoRec.ChipOptionFlags); + OFLG_SET(OPTION_PCI_RETRY, &s3InfoRec.ChipOptionFlags); + OFLG_SET(OPTION_NO_MMIO, &s3InfoRec.ChipOptionFlags); + + return TRUE; + } + + + + + + + + + /* + * S3ValidMode -- + * + * Validates modelines. Can be used by the VidMode extension (I hope). + * Determines virtual size if one wasn't given in the XF86Config. + * Also determines s3DisplayWidth & s3BppDisplayWidth. + * + * MArk. + */ + + int S3ValidMode(DisplayModePtr pMode, Bool verbose, int flag) + { + int ProposedVirtualX; + int ProposedVirtualY; + int ProposedDisplayWidth; + int ProposedBppDisplayWidth; + int ProposedMemUsage; + + ProposedVirtualX = pMode->HDisplay; + ProposedVirtualY = pMode->VDisplay; + ProposedDisplayWidth = max(S3GetWidth(ProposedVirtualX),s3DisplayWidth); + ProposedBppDisplayWidth = ProposedDisplayWidth * s3Bpp; + ProposedMemUsage = ProposedBppDisplayWidth * ProposedVirtualY; + + + /***********************\ + | Trivial Size Tests | + \***********************/ + + if(ProposedVirtualX > s3maxDisplayWidth) { + if(verbose) + ErrorF("%s %s: Width of mode \"%s\" is too large (max is %d)\n", + XCONFIG_PROBED, vga256InfoRec.name, pMode->name, s3maxDisplayWidth); + return MODE_BAD; + } else + + if(ProposedVirtualY > s3maxDisplayHeight) { + if(verbose) + ErrorF("%s %s: Height of mode \"%s\" is too large (max is %d)\n", + XCONFIG_PROBED, vga256InfoRec.name, pMode->name, s3maxDisplayHeight); + return MODE_BAD; + } else + + if(ProposedMemUsage > (vga256InfoRec.videoRam * 1024)) { + if(verbose) + ErrorF("%s %s: Too little video memory for mode \"%s\" " + "(%d bytes required)\n", XCONFIG_PROBED, vga256InfoRec.name, + pMode->name, ProposedMemUsage); + return MODE_BAD; + } + + + /* sizes are within the capabilities of the hardware by here */ + /* we want it to return here on the first pass */ + + if(VirtualNotGiven && !s3Initialized) { + /* Need a better test to keep the VidMode extesion out than + !s3Initialized (Mark). */ + /* Well, we should add a special flag value for that (dhh) */ + if( flag == MODE_USED ) { + vga256InfoRec.virtualX = max(ProposedVirtualX,vga256InfoRec.virtualX); + vga256InfoRec.virtualY = max(ProposedVirtualY,vga256InfoRec.virtualY); + } + + } else { /* fixed size */ + if((ProposedVirtualX > vga256InfoRec.virtualX) || + (ProposedVirtualY > vga256InfoRec.virtualY)) { + if(verbose) + ErrorF("%s %s: Resolution %dx%d too large for virtual %dx%d\n", + XCONFIG_PROBED, vga256InfoRec.name, ProposedVirtualX, + ProposedVirtualY, vga256InfoRec.virtualX, vga256InfoRec.virtualY); + return MODE_BAD; + } + + } + + if( flag == MODE_USED ) { + s3DisplayWidth = max(ProposedDisplayWidth, s3DisplayWidth); + s3BppDisplayWidth = s3DisplayWidth * s3Bpp; + } + + return MODE_OK; + } + *** /dev/null Tue Jun 30 15:23:09 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/s3ramdacs.c Fri Mar 6 16:54:08 1998 *************** *** 0 **** --- 1,4884 ---- + /* $TOG: s3ramdacs.c /main/1 1998/03/06 16:55:45 kaleb $ */ + + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/s3ramdacs.c,v 1.1.2.5 1998/02/24 13:54:27 hohndel Exp $ */ + /* + * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany. + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Thomas Roell not be used in + * advertising or publicity pertaining to distribution of the software + * without specific, written prior permission. Thomas Roell makes no + * representations about the suitability of this software for any purpose. It + * is provided "as is" without express or implied warranty. + * + * THOMAS ROELL AND KEVIN E. MARTIN DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS + * SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, + * IN NO EVENT SHALL THOMAS ROELL OR KEVIN E. MARTIN BE LIABLE FOR ANY + * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER + * RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF + * CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * Author: Thomas Roell, roell@informatik.tu-muenchen.de + * + * Rewritten for the 8514/A by Kevin E. Martin (martin@cs.unc.edu) + * + * Header: /home/src/xfree86/mit/server/ddx/xf86/accel/s3/RCS/s3.c,v 2.0 + * 1993/02/22 05:58:13 jon Exp + * + * Modified by Amancio Hasty and Jon Tombs + * + * Rather severely reorganized by Mark Vojkovich (mvojkovi@ucsd.edu) + * + */ + + #include "misc.h" + #include "pixmapstr.h" + #include "fontstruct.h" + #include "s3.h" + #include "s3reg.h" + #include "xf86_HWlib.h" + #include "xf86_PCI.h" + #define XCONFIG_FLAGS_ONLY + #include "xf86_Config.h" + #include "s3Bt485.h" + #define S3_SERVER + #include "Ti302X.h" + #include "IBMRGB.h" + #include "s3ELSA.h" + + extern Bool pixMuxPossible; + extern Bool allowPixMuxInterlace; + extern Bool allowPixMuxSwitching; + extern int nonMuxMaxClock; + extern int nonMuxMaxMemory; + extern int pixMuxMinWidth; + extern int pixMuxMinClock; + extern Bool pixMuxLimitedWidths; + static unsigned char *find_bios_string(int, char *, char *); + static int s3DetectMIRO_20SV_Rev(); + static void Probe_ELSA(); + + static Bool NORMAL_Probe(); + static Bool S3_TRIO32_Probe(); + static Bool S3_TRIO64_Probe(); + static Bool S3_TRIO64V2_Probe(); + static Bool TI3026_Probe(); + static Bool TI3030_Probe(); + static Bool TI3020_Probe(); + static Bool TI3025_Probe(); + static Bool BT485_Probe(); + static Bool ATT20C505_Probe(); + static Bool ATT22C498_Probe(); + static Bool ATT498_Probe(); + static Bool ATT20C409_Probe(); + static Bool SC15025_Probe(); + static Bool STG1700_Probe(); + static Bool STG1703_Probe(); + static Bool IBMRGB524_Probe(); + static Bool IBMRGB525_Probe(); + static Bool IBMRGB528_Probe(); + static Bool S3_SDAC_Probe(); + static Bool S3_GENDAC_Probe(); + static Bool ATT20C490_Probe(); + static Bool SS2410_Probe(); + static Bool SC1148x_Probe(); + static Bool Null_Probe() {return FALSE;} + + static int BT485_SERIES_PreInit(); + static int TI3020_3025_PreInit(); + static int ATT409_498_PreInit(); + static int SC15025_PreInit(); + static int STG17xx_PreInit(); + static int S3_SDAC_GENDAC_PreInit(); + static int S3_TRIO_PreInit(); + static int TI3030_3026_PreInit(); + static int IBMRGB52x_PreInit(); + static int MISC_HI_COLOR_PreInit(); + static int NORMAL_PreInit(); + static int Null_PreInit() {return 0;} + + + static void Null_Restore(vgaS3Ptr restore){} + static void S3_TRIO_Restore(vgaS3Ptr restore); + static void TI3030_3026_Restore(vgaS3Ptr restore); + static void TI3020_3025_Restore(vgaS3Ptr restore); + static void BT485_Restore(vgaS3Ptr restore); + static void ATT409_498_Restore(vgaS3Ptr restore); + static void SC15025_Restore(vgaS3Ptr restore); + static void STG17xx_Restore(vgaS3Ptr restore); + static void IBMRGB52x_Restore(vgaS3Ptr restore); + static void S3_SDAC_GENDAC_Restore(vgaS3Ptr restore); + static void SC1148x_Restore(vgaS3Ptr restore); + static void SS2410_Restore(vgaS3Ptr restore); + static void ATT20C490_Restore(vgaS3Ptr restore); + + static void Null_Save(vgaS3Ptr save){} + static void S3_TRIO_Save(vgaS3Ptr save); + static void TI3030_3026_Save(vgaS3Ptr save); + static void TI3020_3025_Save(vgaS3Ptr save); + static void BT485_Save(vgaS3Ptr save); + static void ATT409_498_Save(vgaS3Ptr save); + static void SC15025_Save(vgaS3Ptr save); + static void STG17xx_Save(vgaS3Ptr save); + static void IBMRGB52x_Save(vgaS3Ptr save); + static void S3_SDAC_GENDAC_Save(vgaS3Ptr save); + static void SC1148x_Save(vgaS3Ptr save); + static void SS2410_Save(vgaS3Ptr save); + static void ATT20C490_Save(vgaS3Ptr save); + + static int Null_Init(DisplayModePtr mode){return 1;} + static int SC1148x_Init(DisplayModePtr); + static int ATT20C490_Init(DisplayModePtr); + static int ATT409_498_Init(DisplayModePtr); + static int STG17xx_Init(DisplayModePtr); + static int S3_SDAC_Init(DisplayModePtr); + static int S3_GENDAC_Init(DisplayModePtr); + static int S3_TRIO_Init(DisplayModePtr); + static int BT485_Init(DisplayModePtr); + static int TI3020_3025_Init(DisplayModePtr); + static int TI3030_3026_Init(DisplayModePtr); + static int IBMRGB52x_Init(DisplayModePtr); + static int SC15025_Init(DisplayModePtr); + static int SS2410_Init(DisplayModePtr); + + + extern pointer vgaNewVideoState; + #define new ((vgaHWPtr)vgaNewVideoState) + + + Bool (*s3ClockSelectFunc) (); + static Bool LegendClockSelect(); + static Bool s3ClockSelect(); + static Bool icd2061ClockSelect(); + static Bool s3GendacClockSelect(); + static Bool ti3025ClockSelect(); + static Bool ti3026ClockSelect(); + static Bool IBMRGBClockSelect(); + static void s3ProgramTi3025Clock( + #if NeedFunctionPrototypes + int clk, + unsigned char n, + unsigned char m, + unsigned char p + #endif + ); + static Bool ch8391ClockSelect(); + static Bool att409ClockSelect(); + static Bool STG1703ClockSelect(); + static Bool Gloria8ClockSelect(); + + /* + Miscellaneous ramblings... This is pretty much the same + as in the S3 server. I cleaned up a few things though. + All this code should be revaluated to determine how much + of it is really needed and how much is just an old fix + for a nolonger existant problem. I'm considering getting + rid of the stg1700 and stg1703 entries and just making + an stg170x entry. The two are identical except for the + clock and the server can distinguish the between the two + by the clock option being set or not. + + MArk + */ + + + /* NOTE: This order must be the same as the #define order in + s3.h !!!!!!!! */ + s3RamdacInfo s3Ramdacs[] = { + /* DacName, DacSpeeds, DacProbe(), PreInit(), + DacRestore(vgaS3Ptr save), DacSave(), DacInit() */ + /* 0 */ {"normal", {110000,0,0,0}, NORMAL_Probe, NORMAL_PreInit, + Null_Restore, Null_Save, Null_Init}, + /* 1 */ {"s3_trio32", {135000,80000,0,50000}, S3_TRIO32_Probe, + S3_TRIO_PreInit, S3_TRIO_Restore, S3_TRIO_Save, + S3_TRIO_Init}, + /* 2 */ {"s3_trio64", {135000,80000,0,50000}, S3_TRIO64_Probe, + S3_TRIO_PreInit, S3_TRIO_Restore,S3_TRIO_Save, + S3_TRIO_Init}, + /* 3 */ {"ti3026", {135000,135000,135000,135000}, + TI3026_Probe, TI3030_3026_PreInit, TI3030_3026_Restore, + TI3030_3026_Save, TI3030_3026_Init}, + /* 4 */ {"ti3030", {175000,175000,175000,175000}, TI3030_Probe, + TI3030_3026_PreInit, TI3030_3026_Restore, + TI3030_3026_Save, TI3030_3026_Init}, + /* 5 */ {"ti3020", {135000,135000,135000,135000}, TI3020_Probe, + TI3020_3025_PreInit, TI3020_3025_Restore, + TI3020_3025_Save, TI3020_3025_Init}, + /* 6 */ {"ti3025", {135000,135000,135000,135000}, TI3025_Probe, + TI3020_3025_PreInit, TI3020_3025_Restore, + TI3020_3025_Save, TI3020_3025_Init}, + /* 7 */ {"Bt485", {135000,135000,135000,135000}, BT485_Probe, + BT485_SERIES_PreInit, BT485_Restore, BT485_Save, + BT485_Init}, + /* 8 */ {"att20c505", {135000,135000,135000,135000}, ATT20C505_Probe, + BT485_SERIES_PreInit,BT485_Restore, BT485_Save, + BT485_Init}, + /* 9 */ {"att22c498", {135000,135000,135000,135000}, ATT22C498_Probe, + ATT409_498_PreInit,ATT409_498_Restore, + ATT409_498_Save,ATT409_498_Init}, + /* 10 */ {"att20c498", {135000,135000,135000,135000}, ATT498_Probe, + ATT409_498_PreInit, ATT409_498_Restore, + ATT409_498_Save, ATT409_498_Init}, + /* 11 */ {"att20c409", {135000,135000,135000,135000}, ATT20C409_Probe, + ATT409_498_PreInit, ATT409_498_Restore, ATT409_498_Save, + ATT409_498_Init}, + /* 12 */ {"sc15025", {110000,110000,110000,110000}, SC15025_Probe, + SC15025_PreInit, SC15025_Restore, SC15025_Save, + SC15025_Init}, + /* 13 */ {"stg1700", {135000,135000,135000,135000}, STG1700_Probe, + STG17xx_PreInit, STG17xx_Restore, STG17xx_Save, + STG17xx_Init}, + /* 14 */ {"stg1703", {135000,135000,135000,135000}, STG1703_Probe, + STG17xx_PreInit, STG17xx_Restore, STG17xx_Save, + STG17xx_Init}, + /* 15 */ {"ibm_rgb524", {170000,170000,170000,170000}, IBMRGB524_Probe, + IBMRGB52x_PreInit,IBMRGB52x_Restore,IBMRGB52x_Save, + IBMRGB52x_Init}, + /* 16 */ {"ibm_rgb525", {170000,170000,170000,170000}, IBMRGB525_Probe, + IBMRGB52x_PreInit,IBMRGB52x_Restore,IBMRGB52x_Save, + IBMRGB52x_Init}, + /* 17 */ {"ibm_rgb528", {170000,170000,170000,170000}, IBMRGB528_Probe, + IBMRGB52x_PreInit,IBMRGB52x_Restore,IBMRGB52x_Save, + IBMRGB52x_Init}, + /* 18 */ {"s3_sdac", {135000,110000,0,55000}, S3_SDAC_Probe, + S3_SDAC_GENDAC_PreInit,S3_SDAC_GENDAC_Restore, + S3_SDAC_GENDAC_Save,S3_SDAC_Init}, + /* 19 */ {"s3_gendac", {110000,55000,0,27500}, S3_GENDAC_Probe, + S3_SDAC_GENDAC_PreInit,S3_SDAC_GENDAC_Restore, + S3_SDAC_GENDAC_Save,S3_GENDAC_Init}, + /* 20 */ {"att20c490", {110000,110000,110000,110000}, ATT20C490_Probe, + MISC_HI_COLOR_PreInit,ATT20C490_Restore,ATT20C490_Save, + ATT20C490_Init}, + /* 21 */ {"ss2410", {110000,110000,110000,110000}, SS2410_Probe, + MISC_HI_COLOR_PreInit, SS2410_Restore, SS2410_Save, + SS2410_Init}, + /* 22 */ {"sc1148x", {110000,110000,110000,110000}, SC1148x_Probe, + MISC_HI_COLOR_PreInit,SC1148x_Restore,SC1148x_Save, + SC1148x_Init}, + /* 23 */ {"s3_trio64v2", {170000,170000,0,135000}, S3_TRIO64V2_Probe, + S3_TRIO_PreInit, S3_TRIO_Restore,S3_TRIO_Save, + S3_TRIO_Init}, + /* 24 */ {NULL, {0,0,0,0}, Null_Probe, Null_PreInit, Null_Restore, + Null_Save,Null_Init} + }; + + #if 0 + + static Bool TEMPLATE_PreInit() + { + /* Verify that depth is supported by ramdac */ + + /* Check if PixMux is supported and set the PixMux + related flags and variables */ + + /* If there is an internal clock, set s3ClockSelectFunc, s3maxRawClock + s3numClocks and whatever options need to be set. For external + clocks, pass the job to OtherClocksSetup() */ + + /* Make any necessary clock alterations due to multiplexing, + clock doubling, etc... s3Probe will do some last minute + clock sanity checks when we return */ + + return 1; + } + + #endif + + static void OtherClocksSetup(); + + + /*************************************************************\ + + BT485_DAC + + \*************************************************************/ + + static Bool BT485_Probe() + { + /* + * Probe for the bloody thing. Set 0x3C6 to a bogus value, then + * try to get the Bt485 status register. If it's there, then we will + * get something else back from this port. + */ + + Bool found = FALSE; + unsigned char tmp, tmp2, saveCR43; + int card_id; + + /*quick check*/ + if (!S3_928_ONLY(s3ChipId) && !S3_964_SERIES(s3ChipId)) + return FALSE; + + outb(vgaCRIndex, 0x43); + saveCR43 = inb(vgaCRReg); + outb(vgaCRReg, saveCR43 & ~0x02); + + tmp = inb(0x3C6); + outb(0x3C6, 0x0F); + tmp2 = s3InBtStatReg(); + if ((tmp2 & 0x80) && ((tmp2 & 0xF0) != 0xD0)){ + found = TRUE; + ErrorF("%s %s: Detected a BrookTree Bt485 RAMDAC\n", + XCONFIG_PROBED, vga256InfoRec.name); + + card_id = s3DetectMIRO_20SV_Rev(vga256InfoRec.BIOSbase); + if (card_id > 1) { + ErrorF("%s %s: MIRO 20SV Rev.2 or newer detected.\n", + XCONFIG_PROBED, vga256InfoRec.name); + if (!OFLG_ISSET(OPTION_S3_964_BT485_VCLK, &vga256InfoRec.options)) + ErrorF("\tplease use Option \"s3_964_bt485_vclk\"\n"); + } + + /* If it is a Bt485 and no clockchip is specified in the + XF86Config, set clockchips for SPEA Mercury / Mercury P64 */ + + if (!OFLG_ISSET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions) && + OFLG_ISSET(OPTION_SPEA_MERCURY, &vga256InfoRec.options)) { + if (S3_964_SERIES(s3ChipId)) { + OFLG_SET(CLOCK_OPTION_ICD2061A, &vga256InfoRec.clockOptions); + OFLG_SET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions); + s3ClockChipProbed = XCONFIG_PROBED; + } else if (S3_928_ONLY(s3ChipId)) { + OFLG_SET(CLOCK_OPTION_SC11412, &vga256InfoRec.clockOptions); + OFLG_SET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions); + s3ClockChipProbed = XCONFIG_PROBED; + } + } + } + outb(0x3C6, tmp); + + outb(vgaCRIndex, 0x43); + outb(vgaCRReg, saveCR43); + + return found; + } + + + static int BT485_SERIES_PreInit() + { + /* Verify that depth is supported by ramdac */ + /* all are supported */ + + /* Check if PixMux is supported and set the PixMux + related flags and variables */ + if ( OFLG_ISSET(OPTION_STB_PEGASUS, &vga256InfoRec.options) || + OFLG_ISSET(OPTION_NUMBER_NINE, &vga256InfoRec.options) || + OFLG_ISSET(OPTION_MIRO_MAGIC_S4, &vga256InfoRec.options) || + OFLG_ISSET(OPTION_SPEA_MERCURY, &vga256InfoRec.options) || + S3_964_SERIES(s3ChipId) || S3_968_SERIES(s3ChipId)) { + s3Bt485PixMux = TRUE; + /* XXXX Are the defaults for the other parameters correct? */ + pixMuxPossible = TRUE; + allowPixMuxInterlace = FALSE; /* It doesn't work right (yet) */ + allowPixMuxSwitching = FALSE; /* XXXX Is this right? */ + if (OFLG_ISSET(OPTION_SPEA_MERCURY, &vga256InfoRec.options) && + S3_928_ONLY(s3ChipId)) { + nonMuxMaxClock = 67500; /* Doubling only works in mux mode */ + nonMuxMaxMemory = 1024; /* Can't access more without mux */ + allowPixMuxSwitching = FALSE; + pixMuxLimitedWidths = FALSE; + pixMuxMinWidth = 1024; + if (s3Bpp == 2) { + nonMuxMaxMemory = 0; /* Only 2:1MUX works (yet)! */ + pixMuxMinWidth = 800; + } else if (s3Bpp==4) { + nonMuxMaxMemory = 0; + pixMuxMinWidth = 640; + } + } else if (OFLG_ISSET(OPTION_NUMBER_NINE, &vga256InfoRec.options)) { + nonMuxMaxClock = 67500; + allowPixMuxSwitching = TRUE; + pixMuxLimitedWidths = TRUE; + pixMuxMinWidth = 800; + } else if (OFLG_ISSET(OPTION_STB_PEGASUS, &vga256InfoRec.options)) { + allowPixMuxSwitching = TRUE; + pixMuxLimitedWidths = TRUE; + /* For 8bpp mode, allow PIXMUX selection based on Clock and Width. */ + if (s3Bpp == 1) { + nonMuxMaxClock = 85000; + pixMuxMinWidth = 1024; + } else { + /* For 16bpp and 32bpp modes, require PIXMUX. */ + nonMuxMaxClock = 0; + pixMuxMinWidth = 0; + } + } else if (OFLG_ISSET(OPTION_MIRO_MAGIC_S4, &vga256InfoRec.options)) { + allowPixMuxSwitching = FALSE; + pixMuxLimitedWidths = TRUE; + /* For 8bpp mode, allow PIXMUX selection based on Clock and Width. */ + if (s3Bpp == 1) { + nonMuxMaxClock = 85000; + pixMuxMinWidth = 1024; + } else { + /* For 16bpp and 32bpp modes, require PIXMUX. */ + nonMuxMaxClock = 0; + pixMuxMinWidth = 0; + } + } else if (S3_964_SERIES(s3ChipId) || S3_968_SERIES(s3ChipId)) { + nonMuxMaxClock = 0; /* 964 can only be in pixmux mode when */ + pixMuxMinWidth = 0; /* working in enhanced mode */ + pixMuxLimitedWidths = FALSE; + } else { + nonMuxMaxClock = 85000; + } + + } + + + /* If there is an internal clock, set s3ClockSelectFunc, s3maxRawClock + s3numClocks and whatever options need to be set. For external + clocks, pass the job to OtherClocksSetup() */ + + /* Diamond Stealth 64 VRAM uses an ICD2061A */ + if (!OFLG_ISSET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions) && + (s3BiosVendor == DIAMOND_BIOS) && S3_964_ONLY(s3ChipId)) { + OFLG_SET(CLOCK_OPTION_ICD2061A, &vga256InfoRec.clockOptions); + OFLG_SET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions); + s3ClockChipProbed = XCONFIG_PROBED; + } + + OtherClocksSetup(); /* setup clock */ + + /* Make any necessary clock alterations due to multiplexing, + clock doubling, etc... s3Probe will do some last minute + clock sanity checks when we return */ + + if(s3RamdacType == BT485_DAC) { + if (s3maxRawClock > 67500) + s3clockDoublingPossible = TRUE; + /* These limits are based on the LCLK rating, and may be too high */ + if (s3Bt485PixMux && s3Bpp < 4) + vga256InfoRec.maxClock = vga256InfoRec.dacSpeeds[s3Bpp - 1]; + else { + if (vga256InfoRec.dacSpeeds[0] < 150000) /* 110 and 135 */ + vga256InfoRec.maxClock = 90000; + else /* 150 and 170 (if they exist) */ + vga256InfoRec.maxClock = 110000; + } + } else { /* ATT20C505_DAC */ + if (s3maxRawClock > 90000) + s3clockDoublingPossible = TRUE; + /* These limits are based on the LCLK rating, and may be too high */ + if (s3Bt485PixMux && s3Bpp < 4) + vga256InfoRec.maxClock = vga256InfoRec.dacSpeeds[s3Bpp - 1]; + else { + if (vga256InfoRec.dacSpeeds[0] < 110000) /* 85 */ + vga256InfoRec.maxClock = 85000; + else if (vga256InfoRec.dacSpeeds[0] < 135000) /* 110 */ + vga256InfoRec.maxClock = 90000; + else /* 135, 150, 170 */ + vga256InfoRec.maxClock = 110000; + } + } + + return 1; + } + + static void BT485_Restore(vgaS3Ptr restore) + { + unsigned char tmp; + + /* Turn off parallel mode explicitly here */ + if (s3Bt485PixMux) { + if (OFLG_ISSET(OPTION_SPEA_MERCURY, &vga256InfoRec.options) && + S3_928_ONLY(s3ChipId)) + { + outb(vgaCRIndex, 0x5C); + outb(vgaCRReg, 0x20); + outb(0x3C7, 0x00); + /* set s3 reg53 to non-parallel addressing by and'ing 0xDF */ + outb(vgaCRIndex, 0x53); + tmp = inb(vgaCRReg); + outb(vgaCRReg, tmp & 0xDF); + outb(vgaCRIndex, 0x5C); + outb(vgaCRReg, 0x00); + } + if (OFLG_ISSET(OPTION_MIRO_MAGIC_S4, &vga256InfoRec.options) && + S3_928_ONLY(s3ChipId)) + { + outb(vgaCRIndex, 0x5C); + outb(vgaCRReg, 0x40); /* XXXXXXXXXXXXXXXXXXXXX */ + outb(0x3C7, 0x00); + /* set s3 reg53 to non-parallel addressing by and'ing 0xDF */ + outb(vgaCRIndex, 0x53); + tmp = inb(vgaCRReg); + outb(vgaCRReg, tmp & 0xDF); + } + } + + s3OutBtReg(BT_COMMAND_REG_0, 0xFE, 0x01); + s3OutBtRegCom3(0x00, restore->s3DacRegs[3]); + if (s3Bt485PixMux) { + s3OutBtReg(BT_COMMAND_REG_2, 0x00, restore->s3DacRegs[2]); + s3OutBtReg(BT_COMMAND_REG_1, 0x00, restore->s3DacRegs[1]); + } + s3OutBtReg(BT_COMMAND_REG_0, 0x00, restore->s3DacRegs[0]); + } + + static void BT485_Save(vgaS3Ptr save) + { + save->s3DacRegs[0] = s3InBtReg(BT_COMMAND_REG_0); + if (s3Bt485PixMux) { + save->s3DacRegs[1] = s3InBtReg(BT_COMMAND_REG_1); + save->s3DacRegs[2] = s3InBtReg(BT_COMMAND_REG_2); + } + save->s3DacRegs[3] = s3InBtRegCom3(); + } + + static int BT485_Init(DisplayModePtr mode) + { + register unsigned char tmp, blank; + + outb(0x3C4, 1); + blank = inb(0x3C5); + outb(0x3C5, blank | 0x20); /* blank the screen */ + s3OutBtReg(BT_COMMAND_REG_0, 0xFE, 0x01); /* sleep mode */ + + if (s3Bt485PixMux) { + if (s3PixelMultiplexing) { + /* fun timing mods for pixel-multiplexing! + + Pixel Multiplexing is selected for 16bpp, 32bpp, or 8bpp + with Width > 1024. Pixel Multiplexing requires we also + Select Parallel VRAM Addressing (CR53.5), and Parallel + VRAM Addressing also requires a line width of 1024 or + 2048, external SID enabled (CR55.3), and split transfers + disabled (CR51.6). + */ + + if (OFLG_ISSET(OPTION_STB_PEGASUS, &vga256InfoRec.options) || + OFLG_ISSET(OPTION_MIRO_MAGIC_S4, &vga256InfoRec.options)) { + outb(vgaCRIndex, 0x53); + tmp = inb(vgaCRReg); + outb(vgaCRReg, tmp | 0x20); + } + + if (OFLG_ISSET(OPTION_SPEA_MERCURY, &vga256InfoRec.options) && + S3_928_ONLY(s3ChipId)) + { + outb(vgaCRIndex, 0x5C); + outb(vgaCRReg, 0x20); + outb(0x3C7, 0x21); + + /* set s3 reg53 to parallel addressing by or'ing 0x20 */ + outb(vgaCRIndex, 0x53); + tmp = inb(vgaCRReg); + outb(vgaCRReg, tmp | 0x20); + + outb(vgaCRIndex, 0x5C); + outb(vgaCRReg, 0x00); + } + + /* set s3 reg55 to external serial by or'ing 0x08 */ + outb(vgaCRIndex, 0x55); + tmp = inb(vgaCRReg); /* XXXX Something should be masked here */ + if (vga256InfoRec.bitsPerPixel == 32 && + !OFLG_ISSET(OPTION_MIRO_MAGIC_S4,&vga256InfoRec.options)) + /* 24bpp truecolor */ + tmp |= 0x48; + else + tmp |= 0x08; + outb(vgaCRReg, tmp); + if (S3_964_SERIES(s3ChipId) || S3_968_SERIES(s3ChipId)) { + /* Stealth 64 and Miro Crystal 20SV */ + outb(vgaCRIndex, 0x66); + tmp = inb(vgaCRReg) & 0xc0; + if (mode->Flags & V_DBLCLK) { + /* Set VCLK = DCLCK/2 */ + /* And set up a 32 bit interleaved bus */ + if (s3Bpp == 1) + tmp |= 0x11; + else + tmp |= 0x10; /* 16bpp */ + } else { + if (s3Bpp == 1) + tmp |= 0x12; + else if (s3Bpp == 2) + tmp |= 0x11; + else + tmp |= 0x10; /* for 20SV, Stealth needs 0x10 ? */ + } + outb(vgaCRReg, tmp); + + /* blank_delay = 0 (at least for Miro Crystal 20SV) */ + outb(vgaCRIndex, 0x6d); + if ((mode->Flags & V_DBLCLK) || s3Bpp > 1) + outb(vgaCRReg, 0); + else + outb(vgaCRReg, 1); /* or 2; needed for 20SV with ATT 20C505 */ + } + outb(vgaCRIndex, 0x65); + tmp = inb(vgaCRReg); + + if (OFLG_ISSET(OPTION_STB_PEGASUS, &vga256InfoRec.options)) + /* + Setting this register non-zero on the Pegasus causes a wrap of + the rightmost pixels back to the left of the display. + */ + outb(vgaCRReg, 0x00); + else if (!(OFLG_ISSET(OPTION_SPEA_MERCURY, &vga256InfoRec.options) && + S3_928_ONLY(s3ChipId))) { + outb(vgaCRReg, tmp | 0x20); + /* set s3 reg65 for some unknown reason */ + /* Setting this for the SPEA Mercury affects clocks > 120MHz */ + } else if (OFLG_ISSET(OPTION_MIRO_MAGIC_S4, &vga256InfoRec.options)) { + /* do nothing */ ; + } else if ((s3DisplayWidth >= 1024) || (vga256InfoRec.depth == 24) + || (vga256InfoRec.depth == 32)) { + #ifndef PC98_PW + outb(vgaCRReg, tmp | 0x40); + #else + outb(vgaCRReg, tmp | 0x08); + #endif + /* remove horizontal stripes in 1600/8bpp and 1152/16bpp */ + /* 800/32bpp linewidth pixmux modes */ + /* someone should check this for other 928 + Bt485 cards */ + } else outb(vgaCRReg, tmp & 0xBF); + + /* + * set output clocking to 4:1 multiplexing + */ + if (vga256InfoRec.depth == 24 || vga256InfoRec.depth == 32) /* 24bpp */ + tmp = 0x10; + else if (vga256InfoRec.depth == 16) /* 5-6-5 */ + tmp = 0x38; + else if (vga256InfoRec.depth == 15) /* 5-5-5 */ + tmp = 0x30; + else + tmp = 0x40; /* 8bpp */ + s3OutBtReg(BT_COMMAND_REG_1, 0x00, tmp); + + /* SCLK enable,pclk1,pixport */ + if (mode->Flags & V_INTERLACE) + s3OutBtReg(BT_COMMAND_REG_2, 0x00, 0x30 | 0x08); + else + s3OutBtReg(BT_COMMAND_REG_2, 0x00, 0x30); + + } else { + + if (OFLG_ISSET(OPTION_SPEA_MERCURY, &vga256InfoRec.options) && + S3_928_ONLY(s3ChipId)) + { + outb(vgaCRIndex, 0x5C); + outb(vgaCRReg, 0x20); + outb(0x3C7, 0x00); + } + if (OFLG_ISSET(OPTION_MIRO_MAGIC_S4, &vga256InfoRec.options) && + S3_928_ONLY(s3ChipId)) + { + outb(vgaCRIndex, 0x5C); + outb(vgaCRReg, 0x20); + outb(0x3C7, 0x00); + } + + /* set s3 reg53 to non-parallel addressing by and'ing 0xDF */ + outb(vgaCRIndex, 0x53); + tmp = inb(vgaCRReg); + if (OFLG_ISSET(OPTION_SPEA_MERCURY, &vga256InfoRec.options) && + S3_928_ONLY(s3ChipId) && (s3Bpp != 1)) { + outb(vgaCRReg, tmp | 0x20); + } else { + outb(vgaCRReg, tmp & 0xDF); + } + + /* set s3 reg65 for some unknown reason */ + outb(vgaCRIndex, 0x65); + tmp = inb(vgaCRReg); + outb(vgaCRReg, tmp & 0xDF); + + if (OFLG_ISSET(OPTION_SPEA_MERCURY, &vga256InfoRec.options) && + S3_928_ONLY(s3ChipId)) + { + outb(vgaCRIndex, 0x5C); + outb(vgaCRReg, 0x00); + } + + if (OFLG_ISSET(OPTION_MIRO_MAGIC_S4, &vga256InfoRec.options)) + { + outb(vgaCRIndex, 0x5C); + outb(vgaCRReg, 0x00); + outb(vgaCRIndex, 0x55); + outb(vgaCRReg, 0x20); + } else { + /* set s3 reg55 to non-external serial by and'ing 0xF7 */ + outb(vgaCRIndex, 0x55); + tmp = inb(vgaCRReg); + outb(vgaCRReg, tmp & 0xF7); + } + + if (vga256InfoRec.depth == 24 || vga256InfoRec.depth == 32)/* 24bpp */ + tmp = 0x10; + else if (vga256InfoRec.depth == 16) /* 5-6-5 */ + tmp = 0x3c; /* 1:1 MUX */ + else if (vga256InfoRec.depth == 15) /* 5-5-5 */ + tmp = 0x34; /* 1:1 MUX */ + else + tmp = 0x00; + s3OutBtReg(BT_COMMAND_REG_1, 0x00, tmp); + + if (vga256InfoRec.bitsPerPixel > 8) + tmp = 0x30; + else + tmp = 0x10; + + /* pclk1,vgaport */ + if (mode->Flags & V_INTERLACE) + s3OutBtReg(BT_COMMAND_REG_2, 0x00, tmp | 0x08); + else + s3OutBtReg(BT_COMMAND_REG_2, 0x00, tmp); + + } /* end of s3PixelMultiplexing */ + } + + /* Set 6/8 bit mode and sync-on-green if required */ + s3OutBtReg(BT_COMMAND_REG_0, 0x00, 0x01 | + (s3DAC8Bit ? 0x02 : 0) | (s3DACSyncOnGreen ? 0x08 : 0x00)); + #ifdef CLOCKDEBUG + if (mode->Flags & V_DBLCLK) { + ErrorF("Setting clock doubler in s3Init(), freq = %.3f\n", + vga256InfoRec.clock[mode->Clock] / 1000.0); + } + #endif + /* Use Bt485 clock doubler - Bit 3 of Command Reg 3 */ + s3OutBtRegCom3(0xF7, (mode->Flags & V_DBLCLK ? 0x08 : 0x00)); + s3OutBtReg(BT_COMMAND_REG_0, 0xFE, 0x00); /* wake up */ + outb(0x3C4, 1); + outb(0x3C5, blank); /* unblank the screen */ + + return 1; + } + + /************************************************************\ + + ATT20C505_DAC + + \************************************************************/ + + static Bool ATT20C505_Probe() + { + Bool found = FALSE; + unsigned char tmp,tmp2; + + /*quick check*/ + if (!S3_928_ONLY(s3ChipId) && !S3_964_SERIES(s3ChipId)) + return FALSE; + + tmp = inb(0x3C6); + outb(0x3C6, 0x0F); + tmp2 = s3InBtStatReg(); + if ((tmp2 & 0x80) && ((tmp2 & 0xF0) == 0xD0)) { + found = TRUE; + ErrorF("%s %s: Detected an AT&T 20C505 RAMDAC\n", + XCONFIG_PROBED, vga256InfoRec.name); + } + outb(0x3C6, tmp); + return found; + } + + + /*******************************************************\ + + TI3020_DAC + TI3025_DAC + + \*******************************************************/ + + static Bool TI3020_3025_Probe(int type) + { + int found = 0; + unsigned char saveCR55, saveCR45, saveCR43, saveCR5C; + unsigned char saveTIndx,saveTIndx2,saveTIdata; + + outb(vgaCRIndex, 0x43); + saveCR43 = inb(vgaCRReg); + outb(vgaCRReg, saveCR43 & ~0x02); + + outb(vgaCRIndex, 0x45); + saveCR45 = inb(vgaCRReg); + outb(vgaCRReg, saveCR45 & ~0x20); + + outb(vgaCRIndex, 0x55); + saveCR55 = inb(vgaCRReg); + + /* toggle to upper 4 direct registers */ + outb(vgaCRReg, (saveCR55 & 0xFC) | 0x01); + + saveTIndx = inb(TI_INDEX_REG); + outb(TI_INDEX_REG, TI_ID); + if (inb(TI_DATA_REG) == TI_VIEWPOINT20_ID) { + /* + * Found TI ViewPoint 3020 DAC + */ + found = TI3020_DAC; + saveCR43 &= ~0x02; + saveCR45 &= ~0x20; + } else { + outb(vgaCRIndex, 0x5C); + saveCR5C = inb(vgaCRReg); + /* clear 0x20 (RS4) for 3020 mode */ + outb(vgaCRReg, saveCR5C & 0xDF); + saveTIndx2 = inb(TI_INDEX_REG); + /* already twiddled CR55 above */ + outb(TI_INDEX_REG, TI_CURS_CONTROL); + saveTIdata = inb(TI_DATA_REG); + /* clear TI_PLANAR_ACCESS bit */ + outb(TI_DATA_REG, saveTIdata & 0x7F); + + outb(TI_INDEX_REG, TI_ID); + if (inb(TI_DATA_REG) == TI_VIEWPOINT25_ID) { + /* + * Found TI ViewPoint 3025 DAC + */ + found = TI3025_DAC; + saveCR43 &= ~0x02; + saveCR45 &= ~0x20; + } + + /* restore this mess */ + outb(TI_INDEX_REG, TI_CURS_CONTROL); + outb(TI_DATA_REG, saveTIdata); + outb(TI_INDEX_REG, saveTIndx2); + outb(vgaCRIndex, 0x5C); + outb(vgaCRReg, saveCR5C); + } + + outb(TI_INDEX_REG, saveTIndx); + outb(vgaCRIndex, 0x55); + outb(vgaCRReg, saveCR55); + + outb(vgaCRIndex, 0x45); + outb(vgaCRReg, saveCR45); + + outb(vgaCRIndex, 0x43); + outb(vgaCRReg, saveCR43); + + return (found == type); + } + + static Bool TI3020_Probe() + { + if (!S3_928_ONLY(s3ChipId) && !S3_964_SERIES(s3ChipId)) + return FALSE; + else if (TI3020_3025_Probe(TI3020_DAC)) { + ErrorF("%s %s: Detected a TI ViewPoint 3020 RAMDAC\n", + XCONFIG_PROBED, vga256InfoRec.name); + return TRUE; + } else return FALSE; + } + + static Bool TI3025_Probe() + { + if (!S3_964_SERIES(s3ChipId)) + return FALSE; + else if(TI3020_3025_Probe(TI3025_DAC)) { + ErrorF("%s %s: Detected a TI ViewPoint 3025 RAMDAC\n", + XCONFIG_PROBED, vga256InfoRec.name); + return TRUE; + } else return FALSE; + } + + static int TI3020_3025_PreInit() + { + /* Verify that depth is supported by ramdac */ + /* all are supported */ + + + /* Check if PixMux is supported and set the PixMux + related flags and variables */ + pixMuxPossible = TRUE; + allowPixMuxInterlace = FALSE; + allowPixMuxSwitching = FALSE; + nonMuxMaxClock = 70000; + pixMuxLimitedWidths = FALSE; + if (S3_964_SERIES(s3ChipId)) { + nonMuxMaxClock = 0; /* 964 can only be in pixmux mode when */ + pixMuxMinWidth = 0; /* working in enhanced mode */ + } + + /* If there is an internal clock, set s3ClockSelectFunc, s3maxRawClock + s3numClocks and whatever options need to be set. For external + clocks, pass the job to OtherClocksSetup() */ + + if (DAC_IS_TI3025 && + !OFLG_ISSET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions)) { + OFLG_SET(CLOCK_OPTION_TI3025, &vga256InfoRec.clockOptions); + OFLG_SET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions); + s3ClockChipProbed = XCONFIG_PROBED; + } + if (OFLG_ISSET(CLOCK_OPTION_TI3025, &vga256InfoRec.clockOptions)) { + int mclk, m, n, p, mcc, cr5c; + + s3ClockSelectFunc = ti3025ClockSelect; + s3numClocks = 3; + s3maxRawClock = vga256InfoRec.dacSpeeds[0]; + + outb(vgaCRIndex, 0x5c); + cr5c = inb(vgaCRReg); + outb(vgaCRReg, cr5c & 0xdf); /* clear RS4 - use 3020 mode */ + + s3OutTiIndReg(TI_PLL_CONTROL, 0x00, 0x00); + n = s3InTiIndReg(TI_MCLK_PLL_DATA) & 0x7f; + s3OutTiIndReg(TI_PLL_CONTROL, 0x00, 0x01); + m = s3InTiIndReg(TI_MCLK_PLL_DATA) & 0x7f; + s3OutTiIndReg(TI_PLL_CONTROL, 0x00, 0x02); + p = s3InTiIndReg(TI_MCLK_PLL_DATA) & 0x03; + mcc = s3InTiIndReg(TI_MCLK_DCLK_CONTROL); + if (mcc & 0x08) + mcc = (mcc & 0x07) * 2 + 2; + else + mcc = 1; + mclk = ((1431818 * ((m+2) * 8)) / (n+2) / (1 << p) / mcc + 50) / 100; + if (xf86Verbose) + ErrorF("%s %s: Using TI 3025 programmable clock (MCLK %1.3f MHz)\n", + s3ClockChipProbed, vga256InfoRec.name, mclk / 1000.0); + if (OFLG_ISSET(OPTION_NUMBER_NINE, &vga256InfoRec.options)) { + mclk = 55000; + if (xf86Verbose) + ErrorF("%s %s: Setting MCLK to %1.3f MHz for #9GXE64 Pro\n", + XCONFIG_PROBED, vga256InfoRec.name, mclk / 1000.0); + Ti3025SetClock(2 * mclk, TI_MCLK_PLL_DATA, s3ProgramTi3025Clock); + mcc = s3InTiIndReg(TI_MCLK_DCLK_CONTROL); + s3OutTiIndReg(TI_MCLK_DCLK_CONTROL,0x00, (mcc & 0xf0) | 0x08); + } + if (!vga256InfoRec.s3MClk) + vga256InfoRec.s3MClk = mclk; + outb(vgaCRIndex, 0x5c); + outb(vgaCRReg, cr5c); + + } /* Ti3020 will have an external clock */ + else + OtherClocksSetup(); /* external clocks */ + + /* Make any necessary clock alterations due to multiplexing, + clock doubling, etc... s3Probe will do some last minute + clock sanity checks when we return */ + s3clockDoublingPossible = TRUE; + vga256InfoRec.maxClock = vga256InfoRec.dacSpeeds[s3Bpp - 1]; + + return 1; + } + + + static void TI3020_3025_Restore(vgaS3Ptr restore) + { + s3OutTiIndReg(TI_MUX_CONTROL_1, 0x00, restore->s3DacRegs[TI_MUX_CONTROL_1]); + s3OutTiIndReg(TI_MUX_CONTROL_2, 0x00, restore->s3DacRegs[TI_MUX_CONTROL_2]); + s3OutTiIndReg(TI_INPUT_CLOCK_SELECT, 0x00, + restore->s3DacRegs[TI_INPUT_CLOCK_SELECT]); + s3OutTiIndReg(TI_OUTPUT_CLOCK_SELECT, 0x00, + restore->s3DacRegs[TI_OUTPUT_CLOCK_SELECT]); + s3OutTiIndReg(TI_GENERAL_CONTROL, 0x00, + restore->s3DacRegs[TI_GENERAL_CONTROL]); + s3OutTiIndReg(TI_AUXILIARY_CONTROL, 0x00, + restore->s3DacRegs[TI_AUXILIARY_CONTROL]); + s3OutTiIndReg(TI_GENERAL_IO_CONTROL, 0x00, 0x1f); + s3OutTiIndReg(TI_GENERAL_IO_DATA, 0x00, + restore->s3DacRegs[TI_GENERAL_IO_DATA]); + if (DAC_IS_TI3025) { + s3OutTiIndReg(TI_PLL_CONTROL, 0x00, 0x00); + /* N */ + s3OutTiIndReg(TI_PIXEL_CLOCK_PLL_DATA, 0x00, restore->s3DacRegs[0 + 0x40]); + /* M */ + s3OutTiIndReg(TI_PIXEL_CLOCK_PLL_DATA, 0x00, restore->s3DacRegs[1 + 0x40]); + /* P */ + s3OutTiIndReg(TI_PIXEL_CLOCK_PLL_DATA, 0x00, restore->s3DacRegs[2 + 0x40]); + + /* N */ + s3OutTiIndReg(TI_MCLK_PLL_DATA, 0x00, restore->s3DacRegs[3 + 0x40]); + /* M */ + s3OutTiIndReg(TI_MCLK_PLL_DATA, 0x00, restore->s3DacRegs[4 + 0x40]); + /* P */ + s3OutTiIndReg(TI_MCLK_PLL_DATA, 0x00,restore->s3DacRegs[5 + 0x40] | 0x80 ); + + /* N */ + s3OutTiIndReg(TI_LOOP_CLOCK_PLL_DATA, 0x00, restore->s3DacRegs[6 + 0x40]); + /* M */ + s3OutTiIndReg(TI_LOOP_CLOCK_PLL_DATA, 0x00, restore->s3DacRegs[7 + 0x40]); + /* P */ + s3OutTiIndReg(TI_LOOP_CLOCK_PLL_DATA, 0x00, restore->s3DacRegs[8 + 0x40]); + + s3OutTiIndReg(TI_TRUE_COLOR_CONTROL, 0x00, + restore->s3DacRegs[TI_TRUE_COLOR_CONTROL]); + s3OutTiIndReg(TI_MISC_CONTROL, 0x00, restore->s3DacRegs[TI_MISC_CONTROL]); + } + + s3OutTiIndReg(TI_CURS_CONTROL, 0x00, restore->s3DacRegs[TI_CURS_CONTROL]); + } + + + static void TI3020_3025_Save(vgaS3Ptr save) + { + if (DAC_IS_TI3025) { + unsigned char CR5C; + + /* switch the ramdac from bt485 to ti3020 mode clearing RS4 */ + outb(vgaCRIndex, 0x5C); + CR5C = inb(vgaCRReg); + outb(vgaCRReg, CR5C & 0xDF); + + save->s3DacRegs[TI_CURS_CONTROL] = s3InTiIndReg(TI_CURS_CONTROL); + /* clear TI_PLANAR_ACCESS bit */ + s3OutTiIndReg(TI_CURS_CONTROL, 0x7F, 0x00); + } + + save->s3DacRegs[TI_MUX_CONTROL_1] = s3InTiIndReg(TI_MUX_CONTROL_1); + save->s3DacRegs[TI_MUX_CONTROL_2] = s3InTiIndReg(TI_MUX_CONTROL_2); + save->s3DacRegs[TI_INPUT_CLOCK_SELECT] = + s3InTiIndReg(TI_INPUT_CLOCK_SELECT); + save->s3DacRegs[TI_OUTPUT_CLOCK_SELECT] = + s3InTiIndReg(TI_OUTPUT_CLOCK_SELECT); + save->s3DacRegs[TI_GENERAL_CONTROL] = s3InTiIndReg(TI_GENERAL_CONTROL); + save->s3DacRegs[TI_AUXILIARY_CONTROL] = + s3InTiIndReg(TI_AUXILIARY_CONTROL); + s3OutTiIndReg(TI_GENERAL_IO_CONTROL, 0x00, 0x1f); + save->s3DacRegs[TI_GENERAL_IO_DATA] = s3InTiIndReg(TI_GENERAL_IO_DATA); + + if (DAC_IS_TI3025) { + save->s3DacRegs[TI_TRUE_COLOR_CONTROL] = + s3InTiIndReg(TI_TRUE_COLOR_CONTROL); + save->s3DacRegs[TI_MISC_CONTROL] = s3InTiIndReg(TI_MISC_CONTROL); + + s3OutTiIndReg(TI_PLL_CONTROL, 0x00, 0x00); + /* N */ + save->s3DacRegs[0 + 0x40] = s3InTiIndReg(TI_PIXEL_CLOCK_PLL_DATA); + /* M */ + s3OutTiIndReg(TI_PIXEL_CLOCK_PLL_DATA,0x00,save->s3DacRegs[0 + 0x40]); + save->s3DacRegs[1 + 0x40] = s3InTiIndReg(TI_PIXEL_CLOCK_PLL_DATA); + /* P */ + s3OutTiIndReg(TI_PIXEL_CLOCK_PLL_DATA,0x00,save->s3DacRegs[1 + 0x40]); + save->s3DacRegs[2 + 0x40] = s3InTiIndReg(TI_PIXEL_CLOCK_PLL_DATA); + s3OutTiIndReg(TI_PIXEL_CLOCK_PLL_DATA,0x00,save->s3DacRegs[2 + 0x40]); + + save->s3DacRegs[3 + 0x40] = s3InTiIndReg(TI_MCLK_PLL_DATA); /* N */ + s3OutTiIndReg(TI_MCLK_PLL_DATA, 0x00, save->s3DacRegs[3 + 0x40]); + save->s3DacRegs[4 + 0x40] = s3InTiIndReg(TI_MCLK_PLL_DATA); /* M */ + s3OutTiIndReg(TI_MCLK_PLL_DATA, 0x00, save->s3DacRegs[4 + 0x40]); + save->s3DacRegs[5 + 0x40] = s3InTiIndReg(TI_MCLK_PLL_DATA); /* P */ + s3OutTiIndReg(TI_MCLK_PLL_DATA, 0x00, save->s3DacRegs[5 + 0x40]); + + save->s3DacRegs[6 + 0x40] = s3InTiIndReg(TI_LOOP_CLOCK_PLL_DATA); + /* N */ + s3OutTiIndReg(TI_LOOP_CLOCK_PLL_DATA,0x00,save->s3DacRegs[6 + 0x40]); + save->s3DacRegs[7 + 0x40] = s3InTiIndReg(TI_LOOP_CLOCK_PLL_DATA); + /* M */ + s3OutTiIndReg(TI_LOOP_CLOCK_PLL_DATA,0x00,save->s3DacRegs[7 + 0x40]); + save->s3DacRegs[8 + 0x40] = s3InTiIndReg(TI_LOOP_CLOCK_PLL_DATA); + /* P */ + s3OutTiIndReg(TI_LOOP_CLOCK_PLL_DATA,0x00,save->s3DacRegs[8 + 0x40]); + + } + } + + static int TI3020_3025_Init(DisplayModePtr mode) + { + unsigned char tmp, tmp1, tmp2; + + outb(0x3C4, 1); + tmp2 = inb(0x3C5); + outb(0x3C5, tmp2 | 0x20); /* blank the screen */ + + /* change polarity on S3 to pass through control to the 3020 */ + tmp = new->MiscOutReg; /* BUG tmp = inb(0x3CC); */ + new->MiscOutReg |= 0xC0; + tmp1 = 0x00; + if (!(tmp & 0x80)) tmp1 |= 0x02; /* invert bits for the 3020 */ + if (!(tmp & 0x40)) tmp1 |= 0x01; + if (s3DACSyncOnGreen) tmp1 |= 0x20; /* add IOG sync */ + s3OutTiIndReg(TI_GENERAL_CONTROL, 0x00, tmp1); + s3OutTiIndReg(TI_TRUE_COLOR_CONTROL, 0x00, 0x00); + + if (DAC_IS_TI3020) { + /* the 3025 clock programming code sets the input clock select */ + if (mode->Flags & V_DBLCLK) + s3OutTiIndReg(TI_INPUT_CLOCK_SELECT, 0x00, TI_ICLK_CLK1_DOUBLE); + else + s3OutTiIndReg(TI_INPUT_CLOCK_SELECT, 0x00, TI_ICLK_CLK1); + } + + outb(vgaCRIndex, 0x65); + if (DAC_IS_TI3025) { + if (OFLG_ISSET(OPTION_NUMBER_NINE,&vga256InfoRec.options)) { + outb(vgaCRReg, 0x82); + } else { + outb(vgaCRReg, 0); + } + } else { + /* set s3 reg65 for some unknown reason */ + if (vga256InfoRec.bitsPerPixel == 32) { + if (OFLG_ISSET(OPTION_ELSA_W2000PRO,&vga256InfoRec.options)) + outb(vgaCRReg, 0x40); + else + outb(vgaCRReg, 0x80); + } else if (vga256InfoRec.bitsPerPixel == 16) + outb(vgaCRReg, 0x40); + else + outb(vgaCRReg, 0x00); + } + + if (s3PixelMultiplexing) { + /* fun timing mods for pixel-multiplexing! */ + + if (OFLG_ISSET(OPTION_ELSA_W2000PRO,&vga256InfoRec.options)) { + /* set CR40 acording to Bernhard Bender */ + outb(vgaCRIndex, 0x40); + outb(vgaCRReg, 0xd1); + } else if (DAC_IS_TI3025) { + outb(vgaCRIndex, 0x40); + outb(vgaCRReg, 0x11); + outb(vgaCRIndex, 0x55); + outb(vgaCRReg, 0x00); + } else { + /* set s3 reg53 to parallel addressing by or'ing 0x20 */ + outb(vgaCRIndex, 0x53); + tmp = inb(vgaCRReg); + outb(vgaCRReg, tmp | 0x20); + + /* set s3 reg55 to external serial by or'ing 0x08 */ + outb(vgaCRIndex, 0x55); + tmp = inb(vgaCRReg); + outb(vgaCRReg, tmp | 0x08); + } + /* the input clock is already set to clk1 or clk1double (s3.c) */ + + if (DAC_IS_TI3025) { + if (vga256InfoRec.bitsPerPixel > 8) + s3OutTiIndReg(TI_AUXILIARY_CONTROL, 0, 0x00); + else + s3OutTiIndReg(TI_AUXILIARY_CONTROL, 0, TI_AUX_W_CMPL); + } else { + /* set aux control to self clocked, window function complement */ + if (vga256InfoRec.bitsPerPixel > 8) + s3OutTiIndReg(TI_AUXILIARY_CONTROL, 0, TI_AUX_SELF_CLOCK); + else + s3OutTiIndReg(TI_AUXILIARY_CONTROL, 0, + TI_AUX_SELF_CLOCK | TI_AUX_W_CMPL); + } + if (OFLG_ISSET(OPTION_ELSA_W2000PRO,&vga256InfoRec.options)) { + int vclock,rclock; + + /* + * The 964 needs different VCLK division depending on the + * clock frequenzy used. VCLK/1 for 0-60MHz, VCLK/2 for + * 60-120MHz and VCLK/4 for 120-175MHz (or -200MHz, depending + * on the RAMDAC actually used) + * the RCLK output is tied to the LCLK input which is the same + * as SCLK but with no blanking. SCLK is the actual pixel + * shift clock for the pixel bus. + * RCLK/8 is used because of the 8:1 pixel-multiplexing below. + * (964 uses always 8:1 in 256 color modes) + */ + if (vga256InfoRec.clock[mode->Clock] > 120000) { + vclock = TI_OCLK_V4; + } else if (vga256InfoRec.clock[mode->Clock] > 60000){ + vclock = TI_OCLK_V2; + } else { + vclock = TI_OCLK_V1; + } + if (vga256InfoRec.bitsPerPixel == 32) { /* 24bpp */ + rclock = TI_OCLK_R2; + } else if (vga256InfoRec.bitsPerPixel == 16) { /* 15/16bpp */ + rclock = TI_OCLK_R4; + } else { + rclock = TI_OCLK_R8; + } + s3OutTiIndReg(TI_OUTPUT_CLOCK_SELECT, 0x00, + TI_OCLK_S | vclock | rclock); + outb(vgaCRIndex, 0x66); + tmp = inb(vgaCRReg); + outb(vgaCRReg, (tmp & 0xf8) | ((rclock - (vclock >> 3)) & 7)); + } else if (DAC_IS_TI3025) { + if (vga256InfoRec.bitsPerPixel == 32) { /* 24bpp */ + s3OutTiIndReg(TI_OUTPUT_CLOCK_SELECT, 0x00, TI_OCLK_S_V2_R2); + outb(vgaCRIndex, 0x66); + tmp = inb(vgaCRReg); + if (mode->Flags & V_DBLCLK) + outb(vgaCRReg, (tmp & 0xf8) | 0x00); + else + outb(vgaCRReg, (tmp & 0xf8) | 0x01); + } else if (vga256InfoRec.bitsPerPixel == 16) { /* 5-6-5 */ + s3OutTiIndReg(TI_OUTPUT_CLOCK_SELECT, 0x00, TI_OCLK_S_V2_R4); + outb(vgaCRIndex, 0x66); + tmp = inb(vgaCRReg); + if (mode->Flags & V_DBLCLK) + outb(vgaCRReg, (tmp & 0xf8) | 0x01); + else + outb(vgaCRReg, (tmp & 0xf8) | 0x02); + } else { + s3OutTiIndReg(TI_OUTPUT_CLOCK_SELECT, 0x00, TI_OCLK_S_V2_R8); + outb(vgaCRIndex, 0x66); + tmp = inb(vgaCRReg); + if (mode->Flags & V_DBLCLK) + outb(vgaCRReg, (tmp & 0xf8) | 0x02); + else + outb(vgaCRReg, (tmp & 0xf8) | 0x03); + } + } else { + /* + * for all other boards with Ti3020 (only #9 level 14/16 ?) + * set output clocking to VCLK/4, RCLK/8 like the fixed Bt485. + * RCLK/8 is used because of the 8:1 pixel-multiplexing below. + */ + if (vga256InfoRec.bitsPerPixel == 32) { /* 24bpp */ + s3OutTiIndReg(TI_OUTPUT_CLOCK_SELECT, 0x00, TI_OCLK_S_V1_R2); + } else if (vga256InfoRec.bitsPerPixel == 16) { /* 5-6-5 */ + s3OutTiIndReg(TI_OUTPUT_CLOCK_SELECT, 0x00, TI_OCLK_S_V2_R4); + } else { + s3OutTiIndReg(TI_OUTPUT_CLOCK_SELECT, 0x00, TI_OCLK_S_V4_R8); + } + } + + /* + * set the serial access mode 256 words control + */ + outb(vgaCRIndex, 0x58); + tmp = inb(vgaCRReg); + outb(vgaCRReg, (tmp & 0xbf) | s3SAM256); + + if (vga256InfoRec.depth == 24 || vga256InfoRec.depth == 32) { /* 24bpp */ + if (DAC_IS_TI3025) { + s3OutTiIndReg(TI_MUX_CONTROL_1, 0x00, TI_MUX1_3025T_888); + s3OutTiIndReg(TI_MUX_CONTROL_2, 0x00, TI_MUX2_BUS_TC_D24P64); + s3OutTiIndReg(TI_COLOR_KEY_CONTROL, 0x00, 0x01); + } else { + s3OutTiIndReg(TI_MUX_CONTROL_1, 0x00, TI_MUX1_DIRECT_888); + s3OutTiIndReg(TI_MUX_CONTROL_2, 0x00, TI_MUX2_BUS_DC_D24P64); + s3OutTiIndReg(TI_COLOR_KEY_CONTROL, 0x00, 0x00); + } + } else if (vga256InfoRec.depth == 16) { /* 5-6-5 */ + if (DAC_IS_TI3025) { + s3OutTiIndReg(TI_MUX_CONTROL_1, 0x00, TI_MUX1_3025T_565); + s3OutTiIndReg(TI_MUX_CONTROL_2, 0x00, TI_MUX2_BUS_TC_D16P64); + s3OutTiIndReg(TI_COLOR_KEY_CONTROL, 0x00, 0x01); + } else { + s3OutTiIndReg(TI_MUX_CONTROL_1, 0x00, TI_MUX1_DIRECT_565); + s3OutTiIndReg(TI_MUX_CONTROL_2, 0x00, TI_MUX2_BUS_DC_D16P64); + s3OutTiIndReg(TI_COLOR_KEY_CONTROL, 0x00, 0x00); + } + } else if (vga256InfoRec.depth == 15) { /* 5-5-5 */ + if (DAC_IS_TI3025) { + s3OutTiIndReg(TI_MUX_CONTROL_1, 0x00, TI_MUX1_3025T_555); + s3OutTiIndReg(TI_MUX_CONTROL_2, 0x00, TI_MUX2_BUS_TC_D15P64); + s3OutTiIndReg(TI_COLOR_KEY_CONTROL, 0x00, 0x01); + } else { + s3OutTiIndReg(TI_MUX_CONTROL_1, 0x00, TI_MUX1_DIRECT_555); + s3OutTiIndReg(TI_MUX_CONTROL_2, 0x00, TI_MUX2_BUS_DC_D15P64); + s3OutTiIndReg(TI_COLOR_KEY_CONTROL, 0x00, 0x00); + } + } else { + /* set mux control 1 and 2 to provide pseudocolor sub-mode 4 */ + /* this provides a 64-bit pixel bus with 8:1 multiplexing */ + s3OutTiIndReg(TI_MUX_CONTROL_1, 0x00, TI_MUX1_PSEUDO_COLOR); + s3OutTiIndReg(TI_MUX_CONTROL_2, 0x00, TI_MUX2_BUS_PC_D8P64); + } + /* change to 8-bit DAC and re-route the data path and clocking */ + s3OutTiIndReg(TI_GENERAL_IO_CONTROL, 0x00, TI_GIC_ALL_BITS); + if (s3DAC8Bit) { + if (DAC_IS_TI3025) { + s3OutTiIndReg(TI_GENERAL_IO_DATA , 0x00, TI_GID_N9_964); + s3OutTiIndReg(TI_GENERAL_IO_CONTROL, 0x00, 0x00); + s3OutTiIndReg(TI_MISC_CONTROL , 0xF0, + TI_MC_INT_6_8_CONTROL | TI_MC_8_BPP); + } else if(OFLG_ISSET(OPTION_ELSA_W2000PRO,&vga256InfoRec.options)) + s3OutTiIndReg(TI_GENERAL_IO_DATA , 0x00 , TI_GID_W2000_8BIT); + else + s3OutTiIndReg(TI_GENERAL_IO_DATA, 0x00, TI_GID_TI_DAC_8BIT); + } else { + if (DAC_IS_TI3025) { + s3OutTiIndReg(TI_GENERAL_IO_DATA , 0x00, TI_GID_N9_964); + s3OutTiIndReg(TI_GENERAL_IO_CONTROL, 0x00, 0x00); + s3OutTiIndReg(TI_MISC_CONTROL , 0xF0, TI_MC_INT_6_8_CONTROL); + } else if(OFLG_ISSET(OPTION_ELSA_W2000PRO,&vga256InfoRec.options)) + s3OutTiIndReg( TI_GENERAL_IO_DATA , 0x00 , TI_GID_W2000_6BIT ); + else + s3OutTiIndReg(TI_GENERAL_IO_DATA, 0x00, TI_GID_TI_DAC_6BIT); + } + if (DAC_IS_TI3025) { + outb(vgaCRIndex, 0x6D); + if (s3Bpp == 1) + if (mode->Flags & V_DBLCLK) + outb(vgaCRReg, 0x02); + else + outb(vgaCRReg, 0x03); + else if (s3Bpp == 2) + if (mode->Flags & V_DBLCLK) + outb(vgaCRReg, 0x00); + else + outb(vgaCRReg, 0x01); + else /* (s3Bpp == 4) */ + outb(vgaCRReg, 0x00); + } + } else { + /* set s3 reg53 to non-parallel addressing by and'ing 0xDF */ + outb(vgaCRIndex, 0x53); + tmp = inb(vgaCRReg); + outb(vgaCRReg, tmp & 0xDF); + + /* set s3 reg55 to non-external serial by and'ing 0xF7 */ + outb(vgaCRIndex, 0x55); + tmp = inb(vgaCRReg); + outb(vgaCRReg, tmp & 0xF7); + + /* the input clock is already set to clk1 or clk1double (s3.c) */ + + if (DAC_IS_TI3025) { + if (vga256InfoRec.bitsPerPixel > 8) + s3OutTiIndReg(TI_AUXILIARY_CONTROL, 0, 0); + else + s3OutTiIndReg(TI_AUXILIARY_CONTROL, 0, TI_AUX_W_CMPL); + } + else { + /* set aux control to self clocked only */ + s3OutTiIndReg(TI_AUXILIARY_CONTROL, 0, TI_AUX_SELF_CLOCK); + } + /* + * set output clocking to default of VGA. + */ + s3OutTiIndReg(TI_OUTPUT_CLOCK_SELECT, 0x00, TI_OCLK_VGA); + + /* set mux control 1 and 2 to provide pseudocolor VGA */ + s3OutTiIndReg(TI_MUX_CONTROL_1, 0x00, TI_MUX1_PSEUDO_COLOR); + s3OutTiIndReg(TI_MUX_CONTROL_2, 0x00, TI_MUX2_BUS_VGA); + + /* change to 8-bit DAC and re-route the data path and clocking */ + s3OutTiIndReg(TI_GENERAL_IO_CONTROL, 0x00, TI_GIC_ALL_BITS); + if (s3DAC8Bit) + s3OutTiIndReg(TI_GENERAL_IO_DATA, 0x00, TI_GID_S3_DAC_8BIT); + else + s3OutTiIndReg(TI_GENERAL_IO_DATA, 0x00, TI_GID_S3_DAC_6BIT); + } /* end of s3PixelMultiplexing */ + + /* for some reason the bios doesn't set this properly */ + s3OutTiIndReg(TI_SENSE_TEST, 0x00, 0x00); + + /* True color modes need the palette initialized. */ + if (s3Bpp > 1) { + int i; + + outb(0x3C6, 0xFF); + outb(0x3C8, 0x00); + for (i = 0; i < 768; i++) { + outb(0x3C9, i); + DACDelay; + outb(0x3C9, i); + DACDelay; + outb(0x3C9, i); + DACDelay; + } + } + + outb(0x3C4, 1); + outb(0x3C5, tmp2); /* unblank the screen */ + + return 1; + } + + /***********************************************************\ + + ATT498_DAC + ATT20C498_DAC + ATT22C498_DAC + ATT20C409_DAC + + \***********************************************************/ + + static Bool ATT409_498_Probe(int type) + { + int found = 0; + int dir, mir, olddaccomm; + + /*quick check*/ + if (!S3_86x_SERIES(s3ChipId) && !S3_805_I_SERIES(s3ChipId)) + return FALSE; + + xf86dactopel(); + xf86dactocomm(); + (void)inb(0x3C6); + mir = inb(0x3C6); + dir = inb(0x3C6); + xf86dactopel(); + + if ((mir == 0x84) && (dir == 0x98)) { + olddaccomm = xf86getdaccomm(); + xf86setdaccomm(0x0a); + if (xf86getdaccomm() == 0) + found = ATT22C498_DAC; + else + found = ATT498_DAC; + + xf86setdaccomm(olddaccomm); + } else if ((mir == 0x84) && (dir == 0x09)) { + found = ATT20C409_DAC; + } else if ((mir == 0x84) && (dir == 0x99)) { + /* + * according to the 21C499 data sheet it is fully compatible + * with the 22C409. So we will only miss its new features + * this way, but in theory things might work. + */ + found = ATT20C409_DAC; + if(type == ATT20C409_DAC) { + ErrorF("%s %s: Detected an ATT 21C499 RAMDAC\n", + XCONFIG_PROBED, vga256InfoRec.name); + ErrorF("%s %s: support for this RAMDAC is untested. " + "Please report to XFree86@XFree86.Org\n", + XCONFIG_PROBED, vga256InfoRec.name); + } + } + + if (found == ATT20C409_DAC) { + if (!OFLG_ISSET(CLOCK_OPTION_ATT409, &vga256InfoRec.clockOptions)) { + OFLG_SET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions); + OFLG_SET(CLOCK_OPTION_ATT409, &vga256InfoRec.clockOptions); + s3ClockChipProbed = XCONFIG_PROBED; + } + } + + return (found == type); + } + + static Bool ATT498_Probe() + { + if(ATT409_498_Probe(ATT498_DAC)) { + ErrorF("%s %s: Detected an ATT 20C498/21C498 RAMDAC\n", + XCONFIG_PROBED, vga256InfoRec.name); + return TRUE; + } else return FALSE; + } + + static Bool ATT22C498_Probe() + { + if(ATT409_498_Probe(ATT22C498_DAC)) { + ErrorF("%s %s: Detected an ATT 22C498 RAMDAC\n", + XCONFIG_PROBED, vga256InfoRec.name); + return TRUE; + } else return FALSE; + } + + static Bool ATT20C409_Probe() + { + if(ATT409_498_Probe(ATT20C409_DAC)) { + ErrorF("%s %s: Detected an ATT 20C409 RAMDAC\n", + XCONFIG_PROBED, vga256InfoRec.name); + return TRUE; + } else return FALSE; + } + + + static int ATT409_498_PreInit() + { + /* Verify that depth is supported by ramdac */ + /* all are supported */ + + /* Check if PixMux is supported and set the PixMux + related flags and variables */ + if((xf86bpp <= 8) && + (S3_x64_SERIES(s3ChipId) || S3_805_I_SERIES(s3ChipId))) { + s3ATT498PixMux = TRUE; + pixMuxPossible = TRUE; + + if (DAC_IS_ATT20C498) { + if (S3_866_SERIES(s3ChipId) || S3_868_SERIES(s3ChipId)) { + nonMuxMaxClock = 100000; /* 866/868 DCLK limit */ + pixMuxMinClock = 67500; + } + else if (S3_864_SERIES(s3ChipId)) { + nonMuxMaxClock = 95000; /* 864 DCLK limit */ + pixMuxMinClock = 67500; + } + else if (S3_805_I_SERIES(s3ChipId)) { + nonMuxMaxClock = 80000; /* XXXX just a guess, who has 805i docs? */ + pixMuxMinClock = 67500; + } + else { + nonMuxMaxClock = 67500; + pixMuxMinClock = 67500; + } + } + else { + nonMuxMaxClock = 67500; + pixMuxMinClock = 67500; + } + allowPixMuxInterlace = TRUE; + allowPixMuxSwitching = TRUE; + pixMuxLimitedWidths = FALSE; + pixMuxMinWidth = 0; + + } + + /* If there is an internal clock, set s3ClockSelectFunc, s3maxRawClock + s3numClocks and whatever options need to be set. For external + clocks, pass the job to OtherClocksSetup() */ + if (DAC_IS_ATT20C409 && + !OFLG_ISSET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions)) { + OFLG_SET(CLOCK_OPTION_ATT409, &vga256InfoRec.clockOptions); + OFLG_SET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions); + s3ClockChipProbed = XCONFIG_PROBED; + } + if (OFLG_ISSET(CLOCK_OPTION_ATT409, &vga256InfoRec.clockOptions)) { + s3ClockSelectFunc = att409ClockSelect; + s3numClocks = 3; + s3maxRawClock = vga256InfoRec.dacSpeeds[0]; /* Is this right?? */ + if (xf86Verbose) + ErrorF("%s %s: Using ATT20C409/ATT20C499 programmable clock\n", + s3ClockChipProbed, vga256InfoRec.name); + } + else + OtherClocksSetup(); + + + if (s3ATT498PixMux) { + vga256InfoRec.maxClock = vga256InfoRec.dacSpeeds[s3Bpp - 1]; + if (s3Bpp == 1) /* XXXX is this right?? */ + s3clockDoublingPossible = TRUE; + } else { + if (vga256InfoRec.dacSpeeds[0] >= 135000) /* 20C498 -13, -15, -17 */ + vga256InfoRec.maxClock = 110000; + else /* 20C498 -11 */ + vga256InfoRec.maxClock = 80000; + /* Halve it for 32bpp */ + if (s3Bpp == 4) { + vga256InfoRec.maxClock /= 2; + s3maxRawClock /= 2; + } + } + + return 1; + } + + static void ATT409_498_Restore(vgaS3Ptr restore) + { + xf86setdaccomm(restore->s3DacRegs[0]); + } + + static void ATT409_498_Save(vgaS3Ptr save) + { + save->s3DacRegs[0] = xf86getdaccomm(); + } + + static int ATT409_498_Init(DisplayModePtr mode) + { + unsigned char tmp, blank; + + if (s3DAC8Bit) + xf86setdaccommbit(0x02); + else + xf86clrdaccommbit(0x02); + + + outb(0x3C4, 1); + blank = inb(0x3C5); + outb(0x3C5, blank | 0x20); /* blank the screen */ + + if (s3PixelMultiplexing) { /* x64:pixmux */ + /* pixmux with 16/32 bpp not possible for 864 ==> only 8bit mode */ + int daccomm; + tmp = xf86getdaccomm(); + + if (DAC_IS_ATT22C498) { + if (vga256InfoRec.clock[mode->Clock]/2 < 22500) daccomm = 0x20; + else if (vga256InfoRec.clock[mode->Clock]/2 < 45000) daccomm = 0x21; + else daccomm = 0x24; + #if 0 + /* using digital clock doubler; 20C498 compatible */ + daccomm = 0x25; + #endif + } else daccomm = 0x20; + + #ifdef EXTENDED_DEBUG + ErrorF("Putting AT&T 2xC4[09][89] RAMDAC into pixmux\n"); + #endif + xf86setdaccomm( (tmp&0x02) | daccomm ); /* set mode 2, + pixel multiplexing on */ + + if ( ! DAC_IS_ATT20C409 ) { + outb(vgaCRIndex, 0x33); /* set VCLK = -DCLK */ + tmp = inb(vgaCRReg) | 0x08; + outb(vgaCRReg, tmp); + } + + if (S3_x64_SERIES(s3ChipId) || S3_805_I_SERIES(s3ChipId)) { + outb(vgaCRIndex, 0x67); /* set Mode 8: Two 8-bit color + 1 VCLK / 2 pixels */ + if ( OFLG_ISSET(OPTION_NUMBER_NINE, &vga256InfoRec.options) + || DAC_IS_ATT20C409 ) + outb(vgaCRReg, 0x10 ); /* VCLK is out of phase with DCLK */ + else + outb(vgaCRReg, 0x11 ); /* VCLK is in phase with DCLK */ + + outb(vgaCRIndex, 0x6d); + outb(vgaCRReg, 2 ); /* delay -BLANK pulse by 2 DCLKs */ + } + else { + /* don't know */ + } + } else { /* !s3PixelMultiplexing */ + outb(vgaCRIndex, 0x33); + tmp = inb(vgaCRReg) & ~0x08; + outb(vgaCRReg, tmp); + + tmp = xf86getdaccomm() & 0x0f; + + if (S3_x64_SERIES(s3ChipId) || S3_805_I_SERIES(s3ChipId)) { + int invert_vclk = 0; + int delay_blank = 0; + outb(vgaCRIndex, 0x67); + + switch (vga256InfoRec.bitsPerPixel) { + case 8: /* set Mode 0: 8-bit color, 1 VCLK/pixel */ + outb(vgaCRReg, 0x00 | invert_vclk); + xf86setdaccomm(tmp | 0x00); /* set mode 0 */ + break; + case 16: + if (xf86weight.green == 5) { + outb(vgaCRReg, 0x30 | invert_vclk); /* set Mode 9: + 15-bit color, 1 VCLK/pixel */ + xf86setdaccomm(tmp | 0x10); /* set mode 1 */ + } + else { + outb(vgaCRReg, 0x50 | invert_vclk); /* set Mode 10: + 16-bit color, 1 VCLK/pixel */ + xf86setdaccomm(tmp | 0x30); /* set mode 3 */ + } + delay_blank = 2; + break; + case 32: /* set Mode 11: 24/32-bit color, 2 VCLK/pixel */ + outb(vgaCRReg, 0x70 | invert_vclk); + xf86setdaccomm(tmp | 0x50); /* set mode 5 */ + if (mode->HDisplay > 640) /* why not for 640 ? tsk */ + delay_blank = 2; + break; + default: + ; + } + outb(vgaCRIndex, 0x6d); + outb(vgaCRReg, delay_blank); + } + else { + /* don't know */ + } + } /* end of s3PixelMultiplexing */ + + outb(0x3C4, 1); + outb(0x3C5, blank); /* unblank the screen */ + + + return 1; + } + + /********************************************************\ + + SC15025_DAC + + \********************************************************/ + + static Bool SC15025_Probe() + { + /* What chipsets use this? so we can do a quick check */ + + Bool found = FALSE; + int i; + unsigned char c,id[4]; + + c = xf86getdaccomm(); + xf86setdaccomm(c | 0x10); + for (i=0; i<4; i++) { + outb(0x3C7, 0x9+i); + id[i] = inb(0x3C8); + } + xf86setdaccomm(c); + xf86dactopel(); + if (id[0] == 'S' && ((id[1]<<8)|id[2]) == 15025) { + /* unique for the SC 15025/26 */ + if (id[3] != 'A') { /* version number */ + ErrorF( + "%s %s: ==> New Sierra SC 15025/26 version (0x%x) found,\n", + XCONFIG_PROBED, vga256InfoRec.name, id[3]); + ErrorF("\tplease report!\n"); + } + ErrorF("%s %s: Detected a Sierra SC 15025/26 RAMDAC\n", + XCONFIG_PROBED, vga256InfoRec.name); + found = TRUE; + } + return found; + } + + static int SC15025_PreInit() + { + int doubleEdgeLimit; + /* Verify that depth is supported by ramdac */ + /* all are supported */ + + /* Check if PixMux is supported and set the PixMux + related flags and variables */ + /* no PixMux */ + + /* let OtherClocksSetup() take care of the clock options */ + OtherClocksSetup(); + + /* Make any necessary clock alterations due to multiplexing, + clock doubling, etc... s3Probe will do some last minute + clock sanity checks when we return */ + + if (vga256InfoRec.dacSpeeds[0] >= 125000) /* -125 */ + doubleEdgeLimit = 85000; + else if (vga256InfoRec.dacSpeeds[0] >= 110000) /* -110 */ + doubleEdgeLimit = 65000; + else /* -80, -66 */ + doubleEdgeLimit = 50000; + switch (s3Bpp) { + case 1: + vga256InfoRec.maxClock = vga256InfoRec.dacSpeeds[0]; + break; + case 2: + vga256InfoRec.maxClock = doubleEdgeLimit; + s3maxRawClock /= 2; + break; + case 4: + vga256InfoRec.maxClock = doubleEdgeLimit / 2; + s3maxRawClock /= 4; + break; + } + + return 1; + } + + static void SC15025_Restore(vgaS3Ptr restore) + { + unsigned char c; + + c=xf86getdaccomm(); + xf86setdaccomm( c | 0x10 ); /* set internal register access */ + (void)xf86dactocomm(); + outb(0x3c7, 0x8); /* Auxiliary Control Register */ + outb(0x3c8, restore->s3DacRegs[1]); + outb(0x3c7, 0x10); /* Pixel Repack Register */ + outb(0x3c8, restore->s3DacRegs[2]); + xf86setdaccomm( c ); + xf86setdaccomm(restore->s3DacRegs[0]); + } + + static void SC15025_Save(vgaS3Ptr save) + { + LOCK_SYS_REGS; + save->s3DacRegs[0] = xf86getdaccomm(); + xf86setdaccomm((save->s3DacRegs[0] | 0x10)); + (void)xf86dactocomm(); + outb(0x3c7,0x8); /* Auxiliary Control Register */ + save->s3DacRegs[1] = inb(0x3c8); + outb(0x3c7,0x10); /* Pixel Repack Register */ + save->s3DacRegs[2] = inb(0x3c8); + xf86setdaccomm(save->s3DacRegs[0]); + UNLOCK_SYS_REGS; + } + + static int SC15025_Init(DisplayModePtr mode) + { + unsigned char aux=0, comm=0, prr=0; + + if (s3DAC8Bit || vga256InfoRec.bitsPerPixel > 8) aux=1; + switch (vga256InfoRec.bitsPerPixel) { + case 8: + comm = 0; /* repack mode 0, color mode 0 */ + break; + case 16: + if (xf86weight.green == 5) { + comm = 0x80; /* repack mode 1a using both clock edges */ + } + else { /* RGB16_565 */ + comm = 0xc0; /* repack mode 1a using both clock edges */ + } + break; + case 32: + comm = 0x40; /* repack mode 3a using both clock edges */ + prr = 1; + break; + default: + return 0; + } + + comm |= 0x08; /* enable LUT for gamma correction */ + + xf86setdaccomm(comm | 0x10); + outb(0x3c7,0x8); + outb(0x3c8,aux); + outb(0x3c7,0x10); + outb(0x3c8,prr); + xf86setdaccomm(comm); + + return 1; + } + + /*********************************************************\ + + STG1700_DAC + STG1703_DAC + + \*********************************************************/ + + static Bool STG17xx_Probe(int type) + { + int found = 0; + int cid, did, daccomm, readmask; + + if (!S3_86x_SERIES(s3ChipId) && !S3_805_I_SERIES(s3ChipId)) + return FALSE; + + readmask = inb(0x3c6); + xf86dactopel(); + daccomm = xf86getdaccomm(); + xf86setdaccommbit(0x10); + xf86dactocomm(); + inb(0x3c6); + outb(0x3c6, 0x00); + outb(0x3c6, 0x00); + cid = inb(0x3c6); /* company ID */ + did = inb(0x3c6); /* device ID */ + xf86dactopel(); + outb(0x3c6,readmask); + + if ((cid == 0x44) && (did == 0x00)) + { + found = STG1700_DAC; + } else if ((cid == 0x44) && (did == 0x03)) { + found = STG1703_DAC; + if (!OFLG_ISSET(CLOCK_OPTION_PROGRAMABLE,&vga256InfoRec.clockOptions)) { + OFLG_SET(CLOCK_OPTION_STG1703, &vga256InfoRec.clockOptions); + OFLG_SET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions); + s3ClockChipProbed = XCONFIG_PROBED; + } + } + + xf86setdaccomm(daccomm); + + return (found == type); + } + + static Bool STG1700_Probe() + { + if(STG17xx_Probe(STG1700_DAC)) { + ErrorF("%s %s: Detected an STG1700 RAMDAC\n", + XCONFIG_PROBED, vga256InfoRec.name); + return TRUE; + } else return FALSE; + } + + static Bool STG1703_Probe() + { + if(STG17xx_Probe(STG1703_DAC)) { + ErrorF("%s %s: Detected an STG1703 RAMDAC\n", + XCONFIG_PROBED, vga256InfoRec.name); + return TRUE; + } else return FALSE; + } + + + + static int STG17xx_PreInit() + { + /* Verify that depth is supported by ramdac */ + /* all are supported */ + + /* Check if PixMux is supported and set the PixMux + related flags and variables */ + if((xf86bpp <= 8) && (S3_x64_SERIES(s3ChipId) || + S3_805_I_SERIES(s3ChipId))) { + s3ATT498PixMux = TRUE; + pixMuxPossible = TRUE; + nonMuxMaxClock = 67500; + pixMuxMinClock = 67500; + allowPixMuxInterlace = TRUE; + allowPixMuxSwitching = TRUE; + pixMuxLimitedWidths = FALSE; + pixMuxMinWidth = 0; + + } + + /* If there is an internal clock, set s3ClockSelectFunc, s3maxRawClock + s3numClocks and whatever options need to be set. For external + clocks, pass the job to OtherClocksSetup() */ + if (OFLG_ISSET(CLOCK_OPTION_STG1703, &vga256InfoRec.clockOptions)) { + unsigned char mi, ml, mh, tmp; + int mclk; + + outb(vgaCRIndex, 0x43); + tmp = inb(vgaCRReg); + outb(vgaCRReg, tmp & ~0x02); + + outb(vgaCRIndex, 0x55); + tmp = inb(vgaCRReg) & ~0x03; + outb(vgaCRReg, tmp | 1); /* set RS2 */ + + outb(0x3c7, 0x00); /* index high */ + outb(0x3c8, 0x48); /* index low */ + mi = (inb(0x3c9) >> 4) & 0x03; + + outb(0x3c8, 0x40 + 2*mi); /* index low */ + ml = inb(0x3c9); + mh = inb(0x3c9); + + outb(vgaCRReg, tmp); /* reset RS2 */ + + mclk = ((((1431818 * ((ml&0x7f) + 2)) / ((mh&0x1f) + 2)) + >> ((mh>>5)&0x03)) + 50) / 100; + + s3ClockSelectFunc = STG1703ClockSelect; + s3numClocks = 3; + s3maxRawClock = 135000; + + if (xf86Verbose) + ErrorF("%s %s: Using STG1703 programmable clock(MCLK%d %02x %02x " + "%1.3f MHz)\n",XCONFIG_GIVEN, vga256InfoRec.name, mi, ml,mh, mclk/1e3); + if (vga256InfoRec.s3MClk > 0) { + if (xf86Verbose) + ErrorF("%s %s: using specified MCLK value of %1.3f MHz for DRAM " + "timings\n",XCONFIG_GIVEN, vga256InfoRec.name, vga256InfoRec.s3MClk / 1000.0); + } + else + vga256InfoRec.s3MClk = mclk; + + } + else + OtherClocksSetup(); + + /* Make any necessary clock alterations due to multiplexing, + clock doubling, etc... s3Probe will do some last minute + clock sanity checks when we return */ + if (s3ATT498PixMux) { + vga256InfoRec.maxClock = vga256InfoRec.dacSpeeds[s3Bpp - 1]; + if (s3Bpp == 1) /* XXXX is this right?? */ + s3clockDoublingPossible = TRUE; + } + else { + if (vga256InfoRec.dacSpeeds[0] >= 135000) /* 20C498 -13, -15, -17 */ + vga256InfoRec.maxClock = 110000; + else /* 20C498 -11 */ + vga256InfoRec.maxClock = 80000; + /* Halve it for 32bpp */ + if (s3Bpp == 4) { + vga256InfoRec.maxClock /= 2; + s3maxRawClock /= 2; + } + } + + return 1; + } + + static void STG17xx_Restore(vgaS3Ptr restore) + { + xf86dactopel(); + xf86setdaccommbit(0x10); /* enable extended registers */ + xf86dactocomm(); + inb(0x3c6); /* command reg */ + + outb(0x3c6, 0x03); /* index low */ + outb(0x3c6, 0x00); /* index high */ + + outb(0x3c6, restore->s3DacRegs[1]); /* primary pixel mode */ + outb(0x3c6, restore->s3DacRegs[2]); /* secondary pixel mode */ + outb(0x3c6, restore->s3DacRegs[3]); /* PLL control */ + usleep(500); /* PLL settling time */ + + xf86dactopel(); + xf86setdaccomm(restore->s3DacRegs[0]); + } + + + static void STG17xx_Save(vgaS3Ptr save) + { + xf86dactopel(); + save->s3DacRegs[0] = xf86getdaccomm(); + + xf86setdaccommbit(0x10); /* enable extended registers */ + xf86dactocomm(); + inb(0x3c6); /* command reg */ + + outb(0x3c6, 0x03); /* index low */ + outb(0x3c6, 0x00); /* index high */ + + save->s3DacRegs[1] = inb(0x3c6); /* primary pixel mode */ + save->s3DacRegs[2] = inb(0x3c6); /* secondary pixel mode */ + save->s3DacRegs[3] = inb(0x3c6); /* PLL control */ + + xf86dactopel(); + } + + static int STG17xx_Init(DisplayModePtr mode) + { + unsigned char blank, tmp; + int daccomm; + + if (s3DAC8Bit) + xf86setdaccommbit(0x02); + else + xf86clrdaccommbit(0x02); + + daccomm = (xf86getdaccomm() & 0x06) | 0x10; + + outb(0x3C4, 1); + blank = inb(0x3C5); + outb(0x3C5, blank | 0x20); /* blank the screen */ + + if (s3PixelMultiplexing) { + /* x64:pixmux */ + /* pixmux with 16/32 bpp not possible for 864 ==> only 8bit mode */ + daccomm |= 0x08; /* enable extended pixel modes */ + xf86setdaccomm(daccomm); /* pixel multiplexing on */ + + xf86dactocomm(); + inb(0x3c6); /* command reg */ + + outb(0x3c6, 0x03); /* index low */ + outb(0x3c6, 0x00); /* index high */ + + outb(0x3c6, 0x05); /* primary pixel mode */ + outb(0x3c6, 0x05); /* secondary pixel mode */ + outb(0x3c6, 0x02); /* PLL control for 64-135 MHz pixclk */ + usleep(500); /* PLL settling time before LUT access */ + + xf86dactopel(); + + outb(vgaCRIndex, 0x33); + tmp = inb(vgaCRReg) | 0x08; + outb(vgaCRReg, tmp); + + if (S3_x64_SERIES(s3ChipId) || S3_805_I_SERIES(s3ChipId)) { + outb(vgaCRIndex, 0x67); + outb(vgaCRReg, 0x11 ); /* set Mode 5: double 8-bit indexed color, + 1 VCLK/2 pixels */ + outb(vgaCRIndex, 0x6d); + outb(vgaCRReg, 2 ); /* delay -BLANK pulse by 2 DCLKs */ + } + else { + /* don't know */ + } + } + else + { /* !s3PixelMultiplexing */ + outb(vgaCRIndex, 0x33); + tmp = inb(vgaCRReg) & ~0x08; + outb(vgaCRReg, tmp); + + if (S3_x64_SERIES(s3ChipId) || S3_805_I_SERIES(s3ChipId)) { + int invert_vclk = 0; + int delay_blank = 0; + int pixmode = 0; + int s3mux = 0; + + outb(vgaCRIndex, 0x67); + + switch (vga256InfoRec.bitsPerPixel) + { + case 8: /* set Mode 0: 8-bit indexed color, 1 VCLK/pixel */ + daccomm |= 0x00; + s3mux = 0x00 | invert_vclk; + break; + + case 16: + if (xf86weight.green == 5) + { /* set Mode 2: 15-bit direct color */ + daccomm |= 0xa8; + pixmode = 0x02; + s3mux = 0x30 | invert_vclk; + } + else + { /* set Mode 3: 16-bit (565) direct color */ + daccomm |= 0xc8; + pixmode = 0x03; + s3mux = 0x50 | invert_vclk; + } + delay_blank = 2; + break; + + case 32: /* set Mode 4: 24-bit direct color, 2 VCLK/pixel */ + daccomm |= 0xe8; + pixmode = 0x04; + s3mux = 0x70 | invert_vclk; + delay_blank = 2; + break; + + default: + ErrorF("default switch 2\n"); + } + outb(vgaCRReg, s3mux); + xf86setdaccomm(daccomm); + + xf86dactocomm(); + inb(0x3c6); /* command reg */ + + outb(0x3c6, 0x03); /* index low */ + outb(0x3c6, 0x00); /* index high */ + + outb(0x3c6, pixmode); /* primary pixel mode */ + outb(0x3c6, pixmode); /* secondary pixel mode */ + + xf86dactopel(); + + outb(vgaCRIndex, 0x6d); + outb(vgaCRReg, delay_blank); + } + else { + /* don't know */ + } + } /* end of s3PixelMultiplexing */ + + outb(0x3C4, 1); + outb(0x3C5, blank); /* unblank the screen */ + + return 1; + } + + /*********************************************************\ + + S3_SDAC_DAC + S3_GENDAC_DAC + + \*********************************************************/ + + static Bool S3_SDAC_GENDAC_Probe(int type) + { + /* probe for S3 GENDAC or SDAC */ + /* + * S3 GENDAC and SDAC have two fixed read only PLL clocks + * CLK0 f0: 25.255MHz M-byte 0x28 N-byte 0x61 + * CLK0 f1: 28.311MHz M-byte 0x3d N-byte 0x62 + * which can be used to detect GENDAC and SDAC since there is no chip-id + * for the GENDAC. + * + * NOTE: for the GENDAC on a MIRO 10SD (805+GENDAC) reading PLL values + * for CLK0 f0 and f1 always returns 0x7f (but is documented "read only") + */ + + unsigned char saveCR55, saveCR45, saveCR43, savelut[6]; + unsigned int i; /* don't use signed int, UW2.0 compiler bug */ + long clock01, clock23; + int found = 0; + + outb(vgaCRIndex, 0x43); + saveCR43 = inb(vgaCRReg); + outb(vgaCRReg, saveCR43 & ~0x02); + + outb(vgaCRIndex, 0x45); + saveCR45 = inb(vgaCRReg); + outb(vgaCRReg, saveCR45 & ~0x20); + + outb(vgaCRIndex, 0x55); + saveCR55 = inb(vgaCRReg); + outb(vgaCRReg, saveCR55 & ~1); + + outb(0x3c7,0); + for(i=0; i<2*3; i++) /* save first two LUT entries */ + savelut[i] = inb(0x3c9); + outb(0x3c8,0); + for(i=0; i<2*3; i++) /* set first two LUT entries to zero */ + outb(0x3c9,0); + + outb(vgaCRIndex, 0x55); + outb(vgaCRReg, saveCR55 | 1); + + outb(0x3c7,0); + for(i=clock01=0; i<4; i++) + clock01 = (clock01 << 8) | (inb(0x3c9) & 0xff); + for(i=clock23=0; i<4; i++) + clock23 = (clock23 << 8) | (inb(0x3c9) & 0xff); + + outb(vgaCRIndex, 0x55); + outb(vgaCRReg, saveCR55 & ~1); + + outb(0x3c8,0); + for(i=0; i<2*3; i++) /* restore first two LUT entries */ + outb(0x3c9,savelut[i]); + + outb(vgaCRIndex, 0x55); + outb(vgaCRReg, saveCR55); + + if ( clock01 == 0x28613d62 || + (clock01 == 0x7f7f7f7f && clock23 != 0x7f7f7f7f)) { + + + xf86dactopel(); + inb(0x3c6); + inb(0x3c6); + inb(0x3c6); + + /* the fourth read will show the SDAC chip ID and revision */ + if (((i=inb(0x3c6)) & 0xf0) == 0x70) { + found = S3_SDAC_DAC; + saveCR43 &= ~0x02; + saveCR45 &= ~0x20; + } + else { + found = S3_GENDAC_DAC; + saveCR43 &= ~0x02; + saveCR45 &= ~0x20; + } + xf86dactopel(); + } + + outb(vgaCRIndex, 0x45); + outb(vgaCRReg, saveCR45); + + outb(vgaCRIndex, 0x43); + outb(vgaCRReg, saveCR43); + + if((found==type) && !OFLG_ISSET(CLOCK_OPTION_PROGRAMABLE, + &vga256InfoRec.clockOptions)) { + OFLG_SET(CLOCK_OPTION_S3GENDAC, &vga256InfoRec.clockOptions); + OFLG_SET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions); + s3ClockChipProbed = XCONFIG_PROBED; + } + + + return (found == type); + } + + static Bool S3_SDAC_Probe() + { + if (!S3_86x_SERIES(s3ChipId) && !S3_805_I_SERIES(s3ChipId)) + return FALSE; + else if(S3_SDAC_GENDAC_Probe(S3_SDAC_DAC)) { + ErrorF("%s %s: Detected an S3 SDAC 86C716 RAMDAC and programmable clock\n", + XCONFIG_PROBED, vga256InfoRec.name); + return TRUE; + } else return FALSE; + } + + static Bool S3_GENDAC_Probe() + { + if (!S3_801_SERIES(s3ChipId)) + return FALSE; + else if (S3_SDAC_GENDAC_Probe(S3_GENDAC_DAC)) { + ErrorF("%s %s: Detected an S3 GENDAC 86C708 RAMDAC and programmable clock\n", + XCONFIG_PROBED, vga256InfoRec.name); + return TRUE; + } else return FALSE; + } + + static int S3_SDAC_GENDAC_PreInit() + { + /* Verify that depth is supported by ramdac */ + /* all are supported */ + + /* Check if PixMux is supported and set the PixMux + related flags and variables */ + if(DAC_IS_SDAC && (xf86bpp <= 8) && + (S3_x64_SERIES(s3ChipId) || S3_805_I_SERIES(s3ChipId))) { + s3ATT498PixMux = TRUE; + pixMuxPossible = TRUE; + nonMuxMaxClock = 67500; + pixMuxMinClock = 67500; + allowPixMuxInterlace = TRUE; + allowPixMuxSwitching = TRUE; + pixMuxLimitedWidths = FALSE; + pixMuxMinWidth = 0; + } + + OtherClocksSetup(); /* S3_GENDAC clock is in OtherClocksSetup() + since it is compatible with the ICS5342 */ + + /* Make any necessary clock alterations due to multiplexing, + clock doubling, etc... s3Probe will do some last minute + clock sanity checks when we return */ + if(DAC_IS_SDAC) { + if (s3ATT498PixMux) { + vga256InfoRec.maxClock = vga256InfoRec.dacSpeeds[s3Bpp - 1]; + if (s3Bpp == 1) /* XXXX is this right?? */ + s3clockDoublingPossible = TRUE; + } else { + if (vga256InfoRec.dacSpeeds[0] >= 135000) /* 20C498 -13, -15, -17 */ + vga256InfoRec.maxClock = 110000; + else /* 20C498 -11 */ + vga256InfoRec.maxClock = 80000; + /* Halve it for 32bpp */ + if (s3Bpp == 4) { + vga256InfoRec.maxClock /= 2; + s3maxRawClock /= 2; + } + } + } else /* DAC_IS_GENDAC */ + vga256InfoRec.maxClock = vga256InfoRec.dacSpeeds[s3Bpp - 1]; + + return 1; + } + + + static void S3_SDAC_GENDAC_Restore(vgaS3Ptr restore) + { + #if !defined(PC98_PW) && !defined(PC98_PWLB) + unsigned char tmp; + + outb(vgaCRIndex, 0x55); + tmp = inb(vgaCRReg); + outb(vgaCRReg, tmp | 1); + + outb(0x3c6, restore->s3DacRegs[0]); /* Enhanced command register */ + outb(0x3c8, 2); /* index to f2 reg */ + outb(0x3c9, restore->s3DacRegs[3]); /* f2 PLL M divider */ + outb(0x3c9, restore->s3DacRegs[4]); /* f2 PLL N1/N2 divider */ + outb(0x3c8, 0x0e); /* index to PLL control */ + outb(0x3c9, restore->s3DacRegs[5]); /* PLL control */ + outb(0x3c8, restore->s3DacRegs[2]); /* PLL write index */ + outb(0x3c7, restore->s3DacRegs[1]); /* PLL read index */ + + outb(vgaCRReg, tmp & ~1); + #endif + } + + static void S3_SDAC_GENDAC_Save(vgaS3Ptr save) + { + #if !defined(PC98_PW) && !defined(PC98_PWLB) + unsigned char tmp; + + outb(vgaCRIndex, 0x55); + tmp = inb(vgaCRReg); + outb(vgaCRReg, tmp | 1); + + save->s3DacRegs[0] = inb(0x3c6); /* Enhanced command register */ + save->s3DacRegs[2] = inb(0x3c8); /* PLL write index */ + save->s3DacRegs[1] = inb(0x3c7); /* PLL read index */ + outb(0x3c7, 2); /* index to f2 reg */ + save->s3DacRegs[3] = inb(0x3c9); /* f2 PLL M divider */ + save->s3DacRegs[4] = inb(0x3c9); /* f2 PLL N1/N2 divider */ + outb(0x3c7, 0x0e); /* index to PLL control */ + save->s3DacRegs[5] = inb(0x3c9); /* PLL control */ + + outb(vgaCRReg, tmp & ~1); + #endif + } + + static int S3_SDAC_Init(DisplayModePtr mode) + { + int pixmux = 0; /* SDAC command and CR67 */ + int blank_delay = 0; /* CR6D */ + int invert_vclk = 0; /* CR66 bit 0 */ + unsigned char blank, tmp; + + outb(0x3C4, 1); + blank = inb(0x3C5); + outb(0x3C5, blank | 0x20); /* blank the screen */ + + if (s3PixelMultiplexing) + { + /* x64:pixmux */ + /* pixmux with 16/32 bpp not possible for 864 ==> only 8bit mode */ + pixmux = 0x10; /* two 8bit pixels per clock */ + if (!S3_866_SERIES(s3ChipId) && !S3_868_SERIES(s3ChipId)) + invert_vclk = 1; + blank_delay = 2; + } + else + { + switch (vga256InfoRec.bitsPerPixel) + { + case 8: /* 8-bit color, 1 VCLK/pixel */ + break; + + case 16: /* 15/16-bit color, 1VCLK/pixel */ + if (xf86weight.green == 5) + pixmux = 0x30; + else + pixmux = 0x50; + blank_delay = 2; + break; + + case 32: /* 32-bit color, 2VCLK/pixel */ + pixmux = 0x70; + blank_delay = 2; + } + } + + outb(vgaCRIndex, 0x55); + tmp = inb(vgaCRReg) | 1; + outb(vgaCRReg, tmp); + + outb(vgaCRIndex, 0x67); + outb(vgaCRReg, pixmux | invert_vclk); /* set S3 mux mode */ + outb(0x3c6, pixmux); /* set SDAC mux mode */ + + outb(vgaCRIndex, 0x6D); + outb(vgaCRReg, blank_delay); /* set blank delay */ + + outb(vgaCRIndex, 0x55); + tmp = inb(vgaCRReg) & ~1; + outb(vgaCRReg, tmp); + + outb(0x3C4, 1); + outb(0x3C5, blank); /* unblank the screen */ + + return 1; + } + + static int S3_GENDAC_Init(DisplayModePtr mode) + { + int daccomm = 0; /* GENDAC command */ + unsigned char blank, tmp; + + outb(0x3C4, 1); + blank = inb(0x3C5); + outb(0x3C5, blank | 0x20); /* blank the screen */ + + switch (vga256InfoRec.bitsPerPixel) + { + case 8: /* 8-bit color, 1 VCLK/pixel */ + break; + + case 16: /* 15/16-bit color, 2VCLK/pixel */ + if (xf86weight.green == 5) + daccomm = 0x20; + else + daccomm = 0x60; + break; + + case 32: /* 32-bit color, 3VCLK/pixel */ + daccomm = 0x40; + } + + outb(vgaCRIndex, 0x55); + tmp = inb(vgaCRReg) | 1; + outb(vgaCRReg, tmp); + + outb(0x3c6, daccomm); /* set GENDAC mux mode */ + + outb(vgaCRIndex, 0x55); + tmp = inb(vgaCRReg) & ~1; + outb(vgaCRReg, tmp); + + outb(0x3C4, 1); + outb(0x3C5, blank); /* unblank the screen */ + + return 1; + } + + /***********************************************************\ + + S3_TRIO32_DAC + S3_TRIO64_DAC + + \***********************************************************/ + + + static Bool S3_TRIO_Probe(int type) + { + int found = 0; + + if (S3_TRIOxx_SERIES(s3ChipId)) { + if (S3_TRIO32_SERIES(s3ChipId)) + found = S3_TRIO32_DAC; + else if (S3_TRIO64V2_SERIES(s3ChipId)) + found = S3_TRIO64V2_DAC; + else + found = S3_TRIO64_DAC; + } + + if(found == type) + { + if (S3_AURORA64VP_SERIES(s3ChipId)) { + if ( OFLG_ISSET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions) && + !OFLG_ISSET(CLOCK_OPTION_S3TRIO, &vga256InfoRec.clockOptions) && + !OFLG_ISSET(CLOCK_OPTION_S3AURORA, &vga256InfoRec.clockOptions)) { + ErrorF("%s %s: for Aurora64 chips you shouldn't specify any Clockchip\n" + "\t other than \"s3_aurora64\" or maybe \"s3_trio64\"\n", + XCONFIG_PROBED, vga256InfoRec.name); + /* Clear the other clock options */ + OFLG_ZERO(&vga256InfoRec.clockOptions); + } + if (S3_AURORA64VP_SERIES(s3ChipId) && + !OFLG_ISSET(CLOCK_OPTION_S3TRIO, &vga256InfoRec.clockOptions)) { + OFLG_SET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions); + OFLG_SET(CLOCK_OPTION_S3AURORA, &vga256InfoRec.clockOptions); + s3ClockChipProbed = XCONFIG_PROBED; + } + } + else if (S3_TRIO64V2_SERIES(s3ChipId)) { + if ( OFLG_ISSET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions) && + !OFLG_ISSET(CLOCK_OPTION_S3TRIO, &vga256InfoRec.clockOptions) && + !OFLG_ISSET(CLOCK_OPTION_S3TRIO64V2, &vga256InfoRec.clockOptions)) { + ErrorF("%s %s: for Trio64V2 chips you shouldn't specify any Clockchip\n" + "\t other than \"s3_trio64v2\" or maybe \"s3_trio64\"\n", + XCONFIG_PROBED, vga256InfoRec.name); + /* Clear the other clock options */ + OFLG_ZERO(&vga256InfoRec.clockOptions); + } + if (S3_TRIO64V2_SERIES(s3ChipId) && + !OFLG_ISSET(CLOCK_OPTION_S3TRIO, &vga256InfoRec.clockOptions)) { + OFLG_SET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions); + OFLG_SET(CLOCK_OPTION_S3TRIO64V2, &vga256InfoRec.clockOptions); + s3ClockChipProbed = XCONFIG_PROBED; + } + } + else { + if ( OFLG_ISSET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions) && + !OFLG_ISSET(CLOCK_OPTION_S3TRIO, &vga256InfoRec.clockOptions)) { + ErrorF("%s %s: for Trio32/64 chips you shouldn't specify a Clockchip\n", + XCONFIG_PROBED, vga256InfoRec.name); + /* Clear the other clock options */ + OFLG_ZERO(&vga256InfoRec.clockOptions); + } + if (!OFLG_ISSET(CLOCK_OPTION_S3TRIO, &vga256InfoRec.clockOptions)) { + OFLG_SET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions); + OFLG_SET(CLOCK_OPTION_S3TRIO, &vga256InfoRec.clockOptions); + s3ClockChipProbed = XCONFIG_PROBED; + } + } + } + + return (found == type); + } + + static Bool S3_TRIO64V2_Probe() + { + return S3_TRIO_Probe(S3_TRIO64V2_DAC); + } + + static Bool S3_TRIO64_Probe() + { + return S3_TRIO_Probe(S3_TRIO64_DAC); + } + + static Bool S3_TRIO32_Probe() + { + return S3_TRIO_Probe(S3_TRIO32_DAC); + } + + static int S3_TRIO_PreInit() + { + unsigned char sr8, sr27, sr28; + int m,n,n1,n2, mclk; + + /* Verify that depth is supported by ramdac */ + /* all are supported */ + + /* Check if PixMux is supported and set the PixMux + related flags and variables */ + if(xf86bpp <= 8) { + s3ATT498PixMux = TRUE; + pixMuxPossible = TRUE; + if (OFLG_ISSET(OPTION_TRIO64VP_BUG3, &vga256InfoRec.options)) { + nonMuxMaxClock = 0; /* need CR67=10 and DCLK/2 all the time */ + pixMuxMinClock = 0; /* to avoid problems with blank signal */ + } else { + nonMuxMaxClock = 80000; + pixMuxMinClock = 80000; + } + allowPixMuxInterlace = TRUE; + allowPixMuxSwitching = TRUE; + pixMuxLimitedWidths = FALSE; + pixMuxMinWidth = 0; + } + + vga256InfoRec.maxClock = vga256InfoRec.dacSpeeds[s3Bpp - 1]; + + + /* If there is an internal clock, set s3ClockSelectFunc, s3maxRawClock + s3numClocks and whatever options need to be set. For external + clocks, pass the job to OtherClocksSetup() */ + s3ClockSelectFunc = s3GendacClockSelect; + s3numClocks = 3; + if (OFLG_ISSET(CLOCK_OPTION_S3TRIO64V2, &vga256InfoRec.clockOptions)) + s3maxRawClock = 170000; + else + s3maxRawClock = 135000; + + outb(0x3c4, 0x08); + sr8 = inb(0x3c5); + outb(0x3c5, 0x06); + + outb(0x3c4, 0x11); + m = inb(0x3c5); + outb(0x3c4, 0x10); + n = inb(0x3c5); + + m &= 0x7f; + n1 = n & 0x1f; + n2 = (n>>5) & 0x03; + mclk = ((1431818 * (m+2)) / (n1+2) / (1 << n2) + 50) / 100; + if (OFLG_ISSET(CLOCK_OPTION_S3AURORA, &vga256InfoRec.clockOptions)) { + outb(0x3c4, 0x27); + sr27 = inb(0x3c5); + outb(0x3c4, 0x28); + sr28 = inb(0x3c5); + mclk /= ((sr27 >> 2) & 0x03) + 1; + } + + outb(0x3c4, 0x08); + outb(0x3c5, sr8); + + if (xf86Verbose) + if (OFLG_ISSET(CLOCK_OPTION_S3AURORA, &vga256InfoRec.clockOptions)) + ErrorF("%s %s: Using Aurora64 programmable clock (MCLK %1.3f MHz, SR27=%02x, SR28=%02x)\n" + ,s3ClockChipProbed, vga256InfoRec.name + ,mclk / 1000.0, sr27, sr28); + else if (OFLG_ISSET(CLOCK_OPTION_S3TRIO64V2, &vga256InfoRec.clockOptions)) + ErrorF("%s %s: Using Trio64V2 programmable clock (MCLK %1.3f MHz)\n" + ,s3ClockChipProbed, vga256InfoRec.name + ,mclk / 1000.0); + else + ErrorF("%s %s: Using Trio32/64 programmable clock (MCLK %1.3f MHz)\n" + ,s3ClockChipProbed, vga256InfoRec.name + ,mclk / 1000.0); + if (vga256InfoRec.s3MClk > 0) { + if (xf86Verbose) + ErrorF("%s %s: using specified MCLK value of %1.3f MHz for DRAM " + "timings\n",XCONFIG_GIVEN, vga256InfoRec.name, vga256InfoRec.s3MClk/1000.0); + } else { + vga256InfoRec.s3MClk = mclk; + } + + + return 1; + } + + static void S3_TRIO_Restore(vgaS3Ptr restore) + { + unsigned char tmp; + + outb(0x3c2, restore->s3DacRegs[0]); + outb(0x3c4, 0x08); outb(0x3c5, 0x06); + + outb(0x3c4, 0x09); outb(0x3c5, restore->s3DacRegs[2]); + outb(0x3c4, 0x0a); outb(0x3c5, restore->s3DacRegs[3]); + outb(0x3c4, 0x0b); outb(0x3c5, restore->s3DacRegs[4]); + outb(0x3c4, 0x0d); outb(0x3c5, restore->s3DacRegs[5]); + + outb(0x3c4, 0x10); outb(0x3c5, restore->s3DacRegs[8]); + outb(0x3c4, 0x11); outb(0x3c5, restore->s3DacRegs[9]); + outb(0x3c4, 0x12); outb(0x3c5, restore->s3DacRegs[10]); + outb(0x3c4, 0x13); outb(0x3c5, restore->s3DacRegs[11]); + outb(0x3c4, 0x1a); outb(0x3c5, restore->s3DacRegs[12]); + outb(0x3c4, 0x1b); outb(0x3c5, restore->s3DacRegs[13]); + outb(0x3c4, 0x15); + tmp = inb(0x3c5); + outb(0x3c4, tmp & ~0x20); + outb(0x3c4, tmp | 0x20); + outb(0x3c4, tmp & ~0x20); + + outb(0x3c4, 0x15); outb(0x3c5, restore->s3DacRegs[6]); + outb(0x3c4, 0x18); outb(0x3c5, restore->s3DacRegs[7]); + + /* if (S3_AURORA64VP_SERIES(s3ChipId)) { */ + if (OFLG_ISSET(CLOCK_OPTION_S3AURORA, &vga256InfoRec.clockOptions)) { + int i; + for (i=0x1a; i<= 0x6f; i++) { + outb(0x3c4, i); outb(0x3c5, restore->s3DacRegs[i]); + } + } + + outb(0x3c4, 0x08); outb(0x3c5, restore->s3DacRegs[1]); + + } + + static void S3_TRIO_Save(vgaS3Ptr save) + { + save->s3DacRegs[0] = inb(0x3cc); + + outb(0x3c4, 0x08); save->s3DacRegs[1] = inb(0x3c5); + outb(0x3c5, 0x06); + + outb(0x3c4, 0x09); save->s3DacRegs[2] = inb(0x3c5); + outb(0x3c4, 0x0a); save->s3DacRegs[3] = inb(0x3c5); + outb(0x3c4, 0x0b); save->s3DacRegs[4] = inb(0x3c5); + outb(0x3c4, 0x0d); save->s3DacRegs[5] = inb(0x3c5); + outb(0x3c4, 0x15); save->s3DacRegs[6] = inb(0x3c5) & 0xfe; + outb(0x3c5, save->s3DacRegs[6]); + outb(0x3c4, 0x18); save->s3DacRegs[7] = inb(0x3c5); + + outb(0x3c4, 0x10); save->s3DacRegs[8] = inb(0x3c5); + outb(0x3c4, 0x11); save->s3DacRegs[9] = inb(0x3c5); + outb(0x3c4, 0x12); save->s3DacRegs[10] = inb(0x3c5); + outb(0x3c4, 0x13); save->s3DacRegs[11] = inb(0x3c5); + outb(0x3c4, 0x1a); save->s3DacRegs[12] = inb(0x3c5); + outb(0x3c4, 0x1b); save->s3DacRegs[13] = inb(0x3c5); + + /* if (S3_AURORA64VP_SERIES(s3ChipId)) { */ + if (OFLG_ISSET(CLOCK_OPTION_S3AURORA, &vga256InfoRec.clockOptions)) { + int i; + for (i=0x1a; i<= 0x6f; i++) { + outb(0x3c4, i); save->s3DacRegs[i] = inb(0x3c5); + } + } + + outb(0x3c4, 8); + outb(0x3c5, 0x00); + } + + static int S3_TRIO_Init(DisplayModePtr mode) + { + int pixmux = 0; /* SDAC command and CR67 */ + int invert_vclk = 0; /* CR66 bit 0 */ + int sr8, sr15, sr18, cr33; + unsigned char blank, tmp; + + outb(0x3C4, 1); + blank = inb(0x3C5); + outb(0x3C5, blank | 0x20); /* blank the screen */ + + outb(0x3c4, 0x08); + sr8 = inb(0x3c5); + outb(0x3c5, 0x06); + + outb(0x3c4, 0x0d); /* fix for VideoLogic GrafixStar cards: */ + tmp = inb(0x3c5) & ~1; + outb(0x3c5, tmp); + + outb(0x3c4, 0x15); + sr15 = inb(0x3c5) & ~0x10; /* XXXX ~0x40 and SynthClock /= 2 in s3.c + might be better... */ + outb(0x3c4, 0x18); + sr18 = inb(0x3c5) & ~0x80; + outb(vgaCRIndex, 0x33); + cr33 = inb(vgaCRReg) & ~0x28; + + /* for Trio64+ we need corrected blank signal timing */ + if (!(S3_TRIO64V_SERIES(s3ChipId) && (s3ChipRev <= 0x53) + || (S3_TRIO64V2_SERIES(s3ChipId))) ^ + !!OFLG_ISSET(OPTION_TRIO64VP_BUG1, &vga256InfoRec.options)) { + cr33 |= 0x20; + } + + if (s3PixelMultiplexing) + { + /* x64:pixmux */ + /* pixmux with 16/32 bpp not possible for 864 ==> only 8bit mode */ + pixmux = 0x10; /* two 8bit pixels per clock */ + invert_vclk = 2; /* XXXX strange: reserved bit which helps! */ + sr15 |= 0x10; /* XXXX 0x40? see above! */ + sr18 |= 0x80; + } + else + { + switch (vga256InfoRec.bitsPerPixel) + { + case 8: /* 8-bit color, 1 VCLK/pixel */ + break; + + case 16: /* 15/16-bit color, 1VCLK/pixel */ + cr33 |= 0x08; + if (xf86weight.green == 5) + pixmux = 0x30; + else + pixmux = 0x50; + break; + + case 32: /* 32-bit color, 2VCLK/pixel */ + pixmux = 0xd0; + } + } + + outb(vgaCRReg, cr33); + + outb(vgaCRIndex, 0x67); + outb(vgaCRReg, pixmux | invert_vclk); /* set S3 mux mode */ + + outb(0x3c4, 0x15); + outb(0x3c5, sr15); + outb(0x3c4, 0x18); + outb(0x3c5, sr18); + + if (OFLG_ISSET(CLOCK_OPTION_S3AURORA, &vga256InfoRec.clockOptions)) { + outb(0x3c4, 0x28); + outb(0x3c5, 0); + } + + outb(0x3c4, 0x08); + outb(0x3c5, sr8); + + outb(0x3C4, 1); + outb(0x3C5, blank); /* unblank the screen */ + + return 1; + } + + /******************************************************\ + + TI3030_DAC + TI3026_DAC + + \******************************************************/ + + static Bool TI3030_3026_Probe(int type) + { + int found = 0; + unsigned char saveCR55, saveCR45, saveCR43, saveID, saveTIndx; + + if (!S3_964_SERIES(s3ChipId) && !S3_968_SERIES(s3ChipId)) + return FALSE; + + outb(vgaCRIndex, 0x43); + saveCR43 = inb(vgaCRReg); + outb(vgaCRReg, saveCR43 & ~0x02); + + outb(vgaCRIndex, 0x45); + saveCR45 = inb(vgaCRReg); + outb(vgaCRReg, saveCR45 & ~0x20); + + outb(vgaCRIndex, 0x55); + saveCR55 = inb(vgaCRReg); + + outb(vgaCRReg, (saveCR55 & 0xFC) | 0x00); + saveTIndx = inb(0x3c8); + outb(0x3c8, 0x3f); + + outb(vgaCRReg, (saveCR55 & 0xFC) | 0x02); + saveID = inb(0x3c6); + if (saveID == 0x26 || saveID == 0x30) { + outb(0x3c6, ~saveID); /* check if ID reg. is read-only */ + if (inb(0x3c6) != saveID) { + outb(0x3c6, saveID); + } + else { + /* + * Found TI ViewPoint 3026/3030 DAC + */ + int rev; + outb(vgaCRReg, (saveCR55 & 0xFC) | 0x00); + saveTIndx = inb(0x3c8); + outb(0x3c8, 0x01); + outb(vgaCRReg, (saveCR55 & 0xFC) | 0x02); + rev = inb(0x3c6); + + if (saveID == 0x26) + found = TI3026_DAC; + else /* saveID == 0x30 */ + found = TI3030_DAC; + + if(found == type) + ErrorF("%s %s: Detected a TI ViewPoint 30%02x RAMDAC rev. %x\n", + XCONFIG_PROBED, vga256InfoRec.name, saveID, rev); + saveCR43 &= ~0x02; + saveCR45 &= ~0x20; + } + } + + /* restore this mess */ + outb(vgaCRReg, (saveCR55 & 0xFC) | 0x00); + outb(0x3c8, saveTIndx); + + outb(vgaCRIndex, 0x55); + outb(vgaCRReg, saveCR55); + + outb(vgaCRIndex, 0x45); + outb(vgaCRReg, saveCR45); + + outb(vgaCRIndex, 0x43); + outb(vgaCRReg, saveCR43); + + if (found == type) + Probe_ELSA(); + + return (found == type); + } + + static Bool TI3030_Probe() + { + return TI3030_3026_Probe(TI3030_DAC); + } + + static Bool TI3026_Probe() + { + return TI3030_3026_Probe(TI3026_DAC); + } + + static int TI3030_3026_PreInit() + { + int mclk, m, n, p; + + /* Verify that depth is supported by ramdac */ + /* all are supported */ + + /* Check if PixMux is supported and set the PixMux + related flags and variables */ + pixMuxPossible = TRUE; + allowPixMuxInterlace = TRUE; + allowPixMuxSwitching = FALSE; + nonMuxMaxClock = 70000; + pixMuxLimitedWidths = FALSE; + if (S3_964_SERIES(s3ChipId)) { + nonMuxMaxClock = 0; /* 964 can only be in pixmux mode when */ + pixMuxMinWidth = 0; /* working in enhanced mode */ + } + + /* If there is an internal clock, set s3ClockSelectFunc, s3maxRawClock + s3numClocks and whatever options need to be set. For external + clocks, pass the job to OtherClocksSetup() */ + + if(!OFLG_ISSET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions)) { + OFLG_SET(CLOCK_OPTION_TI3026, &vga256InfoRec.clockOptions); + OFLG_SET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions); + s3ClockChipProbed = XCONFIG_PROBED; + } /* there are cards with Ti3026 and EXTERNAL clock! */ + + s3OutTi3026IndReg(TI_PLL_CONTROL, 0x00, 0x00); + n = s3InTi3026IndReg(TI_MCLK_PLL_DATA) & 0x3f; + s3OutTi3026IndReg(TI_PLL_CONTROL, 0x00, 0x04); + m = s3InTi3026IndReg(TI_MCLK_PLL_DATA) & 0x3f; + s3OutTi3026IndReg(TI_PLL_CONTROL, 0x00, 0x08); + p = s3InTi3026IndReg(TI_MCLK_PLL_DATA) & 0x03; + mclk = ((1431818 * ((65-m) * 8)) / (65-n) / (1 << p) + 50) / 100; + if (xf86Verbose) + ErrorF("%s %s: Using Ti3026/3030 programmable MCLK (MCLK %1.3f MHz)\n", + s3ClockChipProbed, vga256InfoRec.name, mclk / 1000.0); + s3numClocks = 3; + if (!vga256InfoRec.s3MClk) + vga256InfoRec.s3MClk = mclk; + + if (OFLG_ISSET(CLOCK_OPTION_TI3026, &vga256InfoRec.clockOptions)) { + s3ClockSelectFunc = ti3026ClockSelect; + s3maxRawClock = vga256InfoRec.dacSpeeds[0]; /* Is this right?? */ + OFLG_SET(CLOCK_OPTION_TI3026, &vga256InfoRec.clockOptions); + OFLG_SET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions); + if (xf86Verbose) + ErrorF("%s %s: Using Ti3026/3030 programmable DCLK\n", + s3ClockChipProbed, vga256InfoRec.name); + } /* there are cards with Ti3026 and EXTERNAL clock! */ + else + OtherClocksSetup(); + + s3clockDoublingPossible = TRUE; + vga256InfoRec.maxClock = vga256InfoRec.dacSpeeds[s3Bpp - 1]; + dacOutTi3026IndReg = s3OutTi3026IndReg; + dacInTi3026IndReg = s3InTi3026IndReg; + + return 1; + } + + static void TI3030_3026_Restore(vgaS3Ptr restore) + { + int i; + + /* select pixel clock PLL as dot clock soure */ + s3OutTi3026IndReg(TI_INPUT_CLOCK_SELECT, 0x00, TI_ICLK_PLL); + + /* programm dot clock PLL to new MCLK frequency */ + s3OutTi3026IndReg(TI_PLL_CONTROL, 0x00, 0x00); + s3OutTi3026IndReg(TI_PIXEL_CLOCK_PLL_DATA, 0x00, restore->s3DacRegs[3 + 0x40]); + s3OutTi3026IndReg(TI_PIXEL_CLOCK_PLL_DATA, 0x00, restore->s3DacRegs[4 + 0x40]); + s3OutTi3026IndReg(TI_PIXEL_CLOCK_PLL_DATA, 0x00, restore->s3DacRegs[5 + 0x40]); + + /* wait until PLL is locked */ + for (i=0; i<10000; i++) + if (s3InTi3026IndReg(TI_PIXEL_CLOCK_PLL_DATA) & 0x40) + break; + + /* switch to output dot clock on the MCLK terminal */ + s3OutTi3026IndReg(0x39, 0xe7, 0x00); + s3OutTi3026IndReg(0x39, 0xe7, 0x08); + + /* Set MCLK */ + s3OutTi3026IndReg(TI_PLL_CONTROL, 0x00, 0x00); + s3OutTi3026IndReg(TI_MCLK_PLL_DATA, 0x00, restore->s3DacRegs[3 + 0x40]); + s3OutTi3026IndReg(TI_MCLK_PLL_DATA, 0x00, restore->s3DacRegs[4 + 0x40]); + s3OutTi3026IndReg(TI_MCLK_PLL_DATA, 0x00, restore->s3DacRegs[5 + 0x40]); + + /* wait until PLL is locked */ + for (i=0; i<10000; i++) + if (s3InTi3026IndReg(TI_MCLK_PLL_DATA) & 0x40) + break; + + /* switch to output MCLK on the MCLK terminal */ + s3OutTi3026IndReg(0x39, 0xe7, 0x10); + s3OutTi3026IndReg(0x39, 0xe7, 0x18); + + + /* restore dot clock PLL */ + + s3OutTi3026IndReg(TI_PIXEL_CLOCK_PLL_DATA, 0x00, + restore->s3DacRegs[0 + 0x40]); + s3OutTi3026IndReg(TI_PIXEL_CLOCK_PLL_DATA, 0x00, + restore->s3DacRegs[1 + 0x40]); + s3OutTi3026IndReg(TI_PIXEL_CLOCK_PLL_DATA, 0x00, + restore->s3DacRegs[2 + 0x40]); + + s3OutTi3026IndReg(TI_LOOP_CLOCK_PLL_DATA, 0x00, + restore->s3DacRegs[6 + 0x40]); + s3OutTi3026IndReg(TI_LOOP_CLOCK_PLL_DATA, 0x00, + restore->s3DacRegs[7 + 0x40]); + s3OutTi3026IndReg(TI_LOOP_CLOCK_PLL_DATA, 0x00, + restore->s3DacRegs[8 + 0x40]); + + s3OutTi3026IndReg(TI_CURS_CONTROL, 0x00, + restore->s3DacRegs[TI_CURS_CONTROL]); + s3OutTi3026IndReg(TI_INPUT_CLOCK_SELECT, 0x00, + restore->s3DacRegs[TI_INPUT_CLOCK_SELECT]); + s3OutTi3026IndReg(TI_MUX_CONTROL_1, 0x00, + restore->s3DacRegs[TI_MUX_CONTROL_1]); + s3OutTi3026IndReg(TI_MUX_CONTROL_2, 0x00, + restore->s3DacRegs[TI_MUX_CONTROL_2]); + s3OutTi3026IndReg(TI_COLOR_KEY_CONTROL, 0x00, + restore->s3DacRegs[TI_COLOR_KEY_CONTROL]); + s3OutTi3026IndReg(TI_GENERAL_CONTROL, 0x00, + restore->s3DacRegs[TI_GENERAL_CONTROL]); + s3OutTi3026IndReg(TI_MISC_CONTROL, 0x00, + restore->s3DacRegs[TI_MISC_CONTROL]); + s3OutTi3026IndReg(TI_MCLK_LCLK_CONTROL, 0x00, + restore->s3DacRegs[TI_MCLK_LCLK_CONTROL]); + s3OutTi3026IndReg(TI_GENERAL_IO_CONTROL, 0x00, + restore->s3DacRegs[TI_GENERAL_IO_CONTROL]); + s3OutTi3026IndReg(TI_GENERAL_IO_DATA, 0x00, + restore->s3DacRegs[TI_GENERAL_IO_DATA]); + } + + static void TI3030_3026_Save(vgaS3Ptr save) + { + int i; + + for (i=0; i<0x40; i++) + save->s3DacRegs[i] = s3InTi3026IndReg(i); + + s3OutTi3026IndReg(TI_PLL_CONTROL, 0x00, 0x00); + save->s3DacRegs[0 + 0x40] = s3InTi3026IndReg(TI_PIXEL_CLOCK_PLL_DATA); + s3OutTi3026IndReg(TI_PLL_CONTROL, 0x00, 0x01); + save->s3DacRegs[1 + 0x40] = s3InTi3026IndReg(TI_PIXEL_CLOCK_PLL_DATA); + s3OutTi3026IndReg(TI_PLL_CONTROL, 0x00, 0x02); + save->s3DacRegs[2 + 0x40] = s3InTi3026IndReg(TI_PIXEL_CLOCK_PLL_DATA); + + s3OutTi3026IndReg(TI_PLL_CONTROL, 0x00, 0x00); + save->s3DacRegs[3 + 0x40] = s3InTi3026IndReg(TI_MCLK_PLL_DATA); + s3OutTi3026IndReg(TI_PLL_CONTROL, 0x00, 0x04); + save->s3DacRegs[4 + 0x40] = s3InTi3026IndReg(TI_MCLK_PLL_DATA); + s3OutTi3026IndReg(TI_PLL_CONTROL, 0x00, 0x08); + save->s3DacRegs[5 + 0x40] = s3InTi3026IndReg(TI_MCLK_PLL_DATA); + + s3OutTi3026IndReg(TI_PLL_CONTROL, 0x00, 0x00); + save->s3DacRegs[6 + 0x40] = s3InTi3026IndReg(TI_LOOP_CLOCK_PLL_DATA); + s3OutTi3026IndReg(TI_PLL_CONTROL, 0x00, 0x10); + save->s3DacRegs[7 + 0x40] = s3InTi3026IndReg(TI_LOOP_CLOCK_PLL_DATA); + s3OutTi3026IndReg(TI_PLL_CONTROL, 0x00, 0x20); + save->s3DacRegs[8 + 0x40] = s3InTi3026IndReg(TI_LOOP_CLOCK_PLL_DATA); + s3OutTi3026IndReg(TI_PLL_CONTROL, 0x00, 0x00); + + } + + static int TI3030_3026_Init(DisplayModePtr mode) + { + unsigned char tmp, tmp1, blank; + + outb(0x3C4, 1); + blank = inb(0x3C5); + outb(0x3C5, blank | 0x20); /* blank the screen */ + + /* change polarity on S3 to pass through control to the 3020 */ + tmp = new->MiscOutReg; + new->MiscOutReg |= 0xC0; + tmp1 = 0x00; + if (!(tmp & 0x80)) tmp1 |= 0x02; /* invert bits for the 3020 */ + if (!(tmp & 0x40)) tmp1 |= 0x01; + if (s3DACSyncOnGreen) tmp1 |= 0x30; /* add IOG sync & 7.5 IRE */ + s3OutTi3026IndReg(TI_GENERAL_CONTROL, 0x00, tmp1); + + if (s3DACSyncOnGreen) { /* needed for ELSA Winner 2000PRO/X */ + s3OutTi3026IndReg(TI_GENERAL_IO_CONTROL, 0x00, TI_GIC_ALL_BITS); + s3OutTi3026IndReg(TI_GENERAL_IO_DATA, ~TI_GID_ELSA_SOG, 0); + } + + outb(vgaCRIndex, 0x65); + if (DAC_IS_TI3030) + outb(vgaCRReg, 0x80); + else + outb(vgaCRReg, 0); + + if (s3PixelMultiplexing) { + int vclock,rclock; + /* fun timing mods for pixel-multiplexing! */ + + outb(vgaCRIndex, 0x40); + outb(vgaCRReg, 0x11); + outb(vgaCRIndex, 0x55); + outb(vgaCRReg, 0x00); + + if (vga256InfoRec.clock[mode->Clock] > 120000) { + vclock = TI_OCLK_V4; + } else if (vga256InfoRec.clock[mode->Clock] > 60000){ + vclock = TI_OCLK_V2; + } else { + vclock = TI_OCLK_V1; + } + if (vga256InfoRec.bitsPerPixel >= 24) { /* 32bpp or packed 24bpp */ + rclock = TI_OCLK_R2; + } else if (vga256InfoRec.bitsPerPixel == 16) { /* 15/16bpp */ + rclock = TI_OCLK_R4; + } else { + rclock = TI_OCLK_R8; + } + + outb(vgaCRIndex, 0x66); + tmp = inb(vgaCRReg); + if (DAC_IS_TI3030) + tmp |= 0x60; + if ((mode->Flags & V_DBLCLK) + && OFLG_ISSET(CLOCK_OPTION_ICD2061A, &vga256InfoRec.clockOptions)) + if (s3Bpp <= 2) + outb(vgaCRReg, (tmp & 0xf8) | (rclock-2)); + else + outb(vgaCRReg, (tmp & 0xf8) | (rclock-1)); + else if ((mode->Flags & V_DBLCLK) && DAC_IS_TI3030) + outb(vgaCRReg, (tmp & 0xf8) | (rclock-1)); + else + outb(vgaCRReg, (tmp & 0xf8) | (rclock-0)); + + /* + * set the serial access mode 256 words control + */ + outb(vgaCRIndex, 0x58); + tmp = (inb(vgaCRReg) & 0xbf) | s3SAM256; + outb(vgaCRReg, tmp); + + if (vga256InfoRec.bitsPerPixel == 24) { /* packed 24bpp */ + s3OutTi3026IndReg(TI_MUX_CONTROL_1, 0x00, TI_MUX1_3026D_888_P8); + if (DAC_IS_TI3030) + s3OutTi3026IndReg(TI_MUX_CONTROL_2, 0x00, + TI_MUX2_BUS_3030TC_D24P128); + else + s3OutTi3026IndReg(TI_MUX_CONTROL_2, 0x00, + TI_MUX2_BUS_3026DC_D24P64); + s3OutTi3026IndReg(TI_COLOR_KEY_CONTROL, 0x00, 0x00); + } else if (vga256InfoRec.bitsPerPixel == 32) { /* 32bpp */ + s3OutTi3026IndReg(TI_MUX_CONTROL_1, 0x00, TI_MUX1_3026D_888); + if (DAC_IS_TI3030) + s3OutTi3026IndReg(TI_MUX_CONTROL_2, 0x00, + TI_MUX2_BUS_3030TC_D24P128); + else + s3OutTi3026IndReg(TI_MUX_CONTROL_2, 0x00, + TI_MUX2_BUS_3026DC_D24P64); + s3OutTi3026IndReg(TI_COLOR_KEY_CONTROL, 0x00, 0x00); + } else if (vga256InfoRec.depth == 16) { /* 5-6-5 */ + s3OutTi3026IndReg(TI_MUX_CONTROL_1, 0x00, TI_MUX1_3026D_565); + if (DAC_IS_TI3030) + s3OutTi3026IndReg(TI_MUX_CONTROL_2, 0x00, + TI_MUX2_BUS_3030TC_D16P128); + else + s3OutTi3026IndReg(TI_MUX_CONTROL_2, 0x00, + TI_MUX2_BUS_3026DC_D16P64); + s3OutTi3026IndReg(TI_COLOR_KEY_CONTROL, 0x00, 0x00); + } else if (vga256InfoRec.depth == 15) { /* 5-5-5 */ + s3OutTi3026IndReg(TI_MUX_CONTROL_1, 0x00, TI_MUX1_3026D_555); + if (DAC_IS_TI3030) + s3OutTi3026IndReg(TI_MUX_CONTROL_2, 0x00, + TI_MUX2_BUS_3030TC_D15P128); + else + s3OutTi3026IndReg(TI_MUX_CONTROL_2, 0x00, + TI_MUX2_BUS_3026DC_D15P64); + s3OutTi3026IndReg(TI_COLOR_KEY_CONTROL, 0x00, 0x00); + } else { + /* set mux control 1 and 2 to provide pseudocolor sub-mode 4 */ + /* this provides a 64-bit pixel bus with 8:1 multiplexing */ + s3OutTi3026IndReg(TI_MUX_CONTROL_1, 0x00, TI_MUX1_PSEUDO_COLOR); + if (DAC_IS_TI3030) + s3OutTi3026IndReg(TI_MUX_CONTROL_2, 0x00, + TI_MUX2_BUS_3030PC_D8P128); + else + s3OutTi3026IndReg(TI_MUX_CONTROL_2, 0x00, + TI_MUX2_BUS_3026PC_D8P64); + } + + /* change to 8-bit DAC and re-route the data path and clocking */ + s3OutTi3026IndReg(TI_GENERAL_IO_CONTROL, 0x00, TI_GIC_ALL_BITS); + if (s3DAC8Bit) { + if (vga256InfoRec.bitsPerPixel>8) + s3OutTi3026IndReg(TI_MISC_CONTROL , 0xF0, + TI_MC_INT_6_8_CONTROL | TI_MC_8_BPP + | TI_MC_PSEL_POLARITY); + else + s3OutTi3026IndReg(TI_MISC_CONTROL , 0xF0, + TI_MC_INT_6_8_CONTROL | TI_MC_8_BPP); + } else { + if (vga256InfoRec.bitsPerPixel>8) + s3OutTi3026IndReg(TI_MISC_CONTROL , 0xF0, TI_MC_INT_6_8_CONTROL + | TI_MC_PSEL_POLARITY); + else + s3OutTi3026IndReg(TI_MISC_CONTROL , 0xF0, TI_MC_INT_6_8_CONTROL); + } + if (OFLG_ISSET(OPTION_DIAMOND, &vga256InfoRec.options)) { + outb(vgaCRIndex, 0x67); + outb(vgaCRReg, 0x01); + outb(vgaCRIndex, 0x6D); + if (s3Bpp == 1) + outb(vgaCRReg, 0x72); + else if (s3Bpp == 2) + outb(vgaCRReg, 0x73); + else /* if (s3Bpp == 4) */ + outb(vgaCRReg, 0x75); + } + else { + outb(vgaCRIndex, 0x67); + outb(vgaCRReg, 0x00); + outb(vgaCRIndex, 0x6d); + if (s3Bpp == 1) + outb(vgaCRReg, 0x00); + else if (s3Bpp == 2) + outb(vgaCRReg, 0x01); + else /* if (s3Bpp == 4) */ + outb(vgaCRReg, 0x00); + } + if (DAC_IS_TI3030) { + /* set s3 reg53 to parallel addressing by or'ing 0x20 */ + outb(vgaCRIndex, 0x53); + tmp = inb(vgaCRReg) | 0x20; + outb(vgaCRReg, tmp); + } + } else { + outb(vgaCRIndex, 0x53); + tmp = inb(vgaCRReg); + if (DAC_IS_TI3030) + /* set s3 reg53 to parallel addressing by or'ing 0x20 */ + outb(vgaCRReg, tmp | 0x20); + else + /* set s3 reg53 to non-parallel addressing by and'ing 0xDF */ + outb(vgaCRReg, tmp & ~0x20); + /* set s3 reg55 to non-external serial by and'ing 0xF7 */ + outb(vgaCRIndex, 0x55); + tmp = inb(vgaCRReg) & 0xF7; + outb(vgaCRReg, tmp); + + /* set mux control 1 and 2 to provide pseudocolor VGA */ + s3OutTi3026IndReg(TI_MUX_CONTROL_1, 0x00, TI_MUX1_PSEUDO_COLOR); + s3OutTi3026IndReg(TI_MUX_CONTROL_2, 0x00, TI_MUX2_BUS_VGA); + } /* end of s3PixelMultiplexing */ + + /* for some reason the bios doesn't set this properly */ + s3OutTi3026IndReg(TI_SENSE_TEST, 0x00, 0x00); + + if (OFLG_ISSET(OPTION_TI3026_CURS, &vga256InfoRec.options)) { + /* enable interlaced cursor; + not very useful without CR45 bit 5 set, but anyway */ + if (mode->Flags & V_INTERLACE) { + static int already = 0; + if (!already) { + already++; + ErrorF("%s %s: Ti3026 hardware cursor in interlaced modes " + "doesn't work correctly,\n" + "\tplease use Option \"sw_cursor\" when using " + "interlaced modes!\n" + ,XCONFIG_PROBED, vga256InfoRec.name); + } + s3OutTi3026IndReg(TI_CURS_CONTROL, ~0x60, 0x60); + } + else + s3OutTi3026IndReg(TI_CURS_CONTROL, ~0x60, 0x00); + } + + outb(0x3C4, 1); + outb(0x3C5, blank); /* unblank the screen */ + + return 1; + + } + + /*********************************************************\ + + IBMRGB524_DAC + IBMRGB525_DAC + IBMRGB528_DAC + + \*********************************************************/ + + + static Bool IBMRGB52x_Probe(int type) + { + int found = 0; + int ibm_id; + + if (!S3_964_SERIES(s3ChipId) && !S3_968_SERIES(s3ChipId)) + return FALSE; + + if ((ibm_id = s3IBMRGB_Probe())) { + s3IBMRGB_Init(); + switch(ibm_id >> 8) { + case 1: + if(type == IBMRGB525_DAC) { + ErrorF("%s %s: Detected an IBM RGB525 ramdac rev. %x\n", + XCONFIG_PROBED, vga256InfoRec.name, ibm_id&0xff); + found = IBMRGB525_DAC; + } + break; + case 2: + if(type == IBMRGB524_DAC) { + ErrorF("%s %s: Detected an IBM RGB524 ramdac rev. %x\n", + XCONFIG_PROBED, vga256InfoRec.name, ibm_id&0xff); + found = IBMRGB524_DAC; + } + break; + case 0x102: + if(type == IBMRGB528_DAC) { + ErrorF("%s %s: Detected an IBM RGB528 ramdac rev. %x\n", + XCONFIG_PROBED, vga256InfoRec.name, ibm_id&0xff); + found = IBMRGB528_DAC; + } + break; + default: + break; + } + } + + if (found == type) + Probe_ELSA(); + + return (found == type); + } + + static Bool IBMRGB524_Probe() + { + return IBMRGB52x_Probe(IBMRGB524_DAC); + } + + static Bool IBMRGB525_Probe() + { + return IBMRGB52x_Probe(IBMRGB525_DAC); + } + + static Bool IBMRGB528_Probe() + { + return IBMRGB52x_Probe(IBMRGB528_DAC); + } + + static int IBMRGB52x_PreInit() + { + /* Verify that depth is supported by ramdac */ + /* all are supported */ + + /* Check if PixMux is supported and set the PixMux + related flags and variables */ + pixMuxPossible = TRUE; + allowPixMuxInterlace = TRUE; + allowPixMuxSwitching = TRUE; + nonMuxMaxClock = 70000; + pixMuxLimitedWidths = FALSE; + if (S3_964_SERIES(s3ChipId)) { + nonMuxMaxClock = 0; /* 964 can only be in pixmux mode when */ + pixMuxMinWidth = 0; /* working in enhanced mode */ + } + + /* Set Clock options, s3ClockSelectFunc, & s3maxRawClock + for internal clocks. Pass the job to the OtherClocksSetup() + function for external clocks*/ + if (DAC_IS_IBMRGB && + !OFLG_ISSET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions)) { + OFLG_SET(CLOCK_OPTION_IBMRGB, &vga256InfoRec.clockOptions); + OFLG_SET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions); + s3ClockChipProbed = XCONFIG_PROBED; + } + + if (OFLG_ISSET(CLOCK_OPTION_IBMRGB, &vga256InfoRec.clockOptions)) { + char *refclock_probed; + int mclk=0, m, n, df; + int m0,m1,n0,n1; + double f0,f1,f,fdiff; + + s3maxRawClock = vga256InfoRec.dacSpeeds[s3Bpp - 1]; /* Is this right?? */ + s3ClockSelectFunc = IBMRGBClockSelect; + s3numClocks = 3; + + OFLG_SET(CLOCK_OPTION_IBMRGB, &vga256InfoRec.clockOptions); + OFLG_SET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions); + + if (vga256InfoRec.s3RefClk) + refclock_probed = XCONFIG_GIVEN; + else + refclock_probed = XCONFIG_PROBED; + + if (s3InIBMRGBIndReg(IBMRGB_pll_ctrl1) & 1) { + m0 = s3InIBMRGBIndReg(IBMRGB_m0+0*2); + n0 = s3InIBMRGBIndReg(IBMRGB_n0+0*2) & 0x1f; + m1 = s3InIBMRGBIndReg(IBMRGB_m0+1*2); + n1 = s3InIBMRGBIndReg(IBMRGB_n0+1*2) & 0x1f; + } + else { + m0 = s3InIBMRGBIndReg(IBMRGB_f0+0); + m1 = s3InIBMRGBIndReg(IBMRGB_f0+1); + n0 = s3InIBMRGBIndReg(IBMRGB_pll_ref_div_fix) & 0x1f; + n1 = n0; + } + f0 = 25.175 / ((m0&0x3f)+65.0) * n0 * (8 >> (m0>>6)); + f1 = 28.322 / ((m1&0x3f)+65.0) * n1 * (8 >> (m1>>6)); + if (f1>f0) fdiff = f1-f0; + else fdiff = f0-f1; + + + /* refclock defaults should not depend on vendor options + * but only on probed BIOS tags; it's too dangerous + * when users play with options */ + + if (find_bios_string(vga256InfoRec.BIOSbase,"VideoBlitz III AV", + "Genoa Systems Corporation") != NULL) { + if (s3BiosVendor == UNKNOWN_BIOS) + s3BiosVendor = GENOA_BIOS; + if (xf86Verbose) + ErrorF("%s %s: Genoa VideoBlitz III AV BIOS found\n", + XCONFIG_PROBED, vga256InfoRec.name); + if (!vga256InfoRec.s3RefClk) + vga256InfoRec.s3RefClk = 50000; + } + else if (find_bios_string(vga256InfoRec.BIOSbase,"STB Systems, Inc.", NULL) + != NULL) { + if (s3BiosVendor == UNKNOWN_BIOS) + s3BiosVendor = STB_BIOS; + if (xf86Verbose) + ErrorF("%s %s: STB Velocity 64 BIOS found\n", + XCONFIG_PROBED, vga256InfoRec.name); + if (!vga256InfoRec.s3RefClk) + vga256InfoRec.s3RefClk = 24000; + } + else if (find_bios_string(vga256InfoRec.BIOSbase, + "Number Nine Visual Technology","Motion 771") + != NULL) { + if (s3BiosVendor == UNKNOWN_BIOS) + s3BiosVendor = NUMBER_NINE_BIOS; + if (xf86Verbose) + ErrorF("%s %s: #9 Motion 771 BIOS found\n", + XCONFIG_PROBED, vga256InfoRec.name); + if (!vga256InfoRec.s3RefClk) + vga256InfoRec.s3RefClk = 16000; + } + else if (OFLG_ISSET(OPTION_ELSA_W2000PRO_X8, &vga256InfoRec.options)) { + if (!vga256InfoRec.s3RefClk) + vga256InfoRec.s3RefClk = 28322; + } + else if (find_bios_string(vga256InfoRec.BIOSbase, + "Hercules Graphite Terminator",NULL) != NULL) { + if (s3BiosVendor == UNKNOWN_BIOS) + s3BiosVendor = HERCULES_BIOS; + if (xf86Verbose) + ErrorF("%s %s: Hercules Graphite Terminator BIOS found\n", + XCONFIG_PROBED, vga256InfoRec.name); + if (!vga256InfoRec.s3RefClk) + if (S3_968_SERIES(s3ChipId)) + /* Hercules Graphite Terminator Pro(tm) BIOS. */ + vga256InfoRec.s3RefClk = 16000; + else /* S3 964 */ + /* Hercules Graphite Terminator 64(tm) BIOS. */ + vga256InfoRec.s3RefClk = 50000; + } + else if (!vga256InfoRec.s3RefClk) { + if (fdiff < f0*0.02) { + int i; + /* f = (f0+f1)/2; */ + f = f1; + i = (int)(f*1e3/200+0.5); + /* 28.322 MHz clock seems to be more acurate then 25.175 */ + /* try to match some known reclock values */ + if (i == (14318+100)/200) + vga256InfoRec.s3RefClk = 14318; + else if (i == (16000+100)/200) + vga256InfoRec.s3RefClk = 16000; + else if (i == (24000+100)/200) + vga256InfoRec.s3RefClk = 24000; + else if (i == (28322+100)/200) + vga256InfoRec.s3RefClk = 28322; + else if (i == (50000+100)/200) + vga256InfoRec.s3RefClk = 50000; + else + vga256InfoRec.s3RefClk = (int)(f*2+0.5)*500; + } + } + else if (!vga256InfoRec.s3RefClk) { + vga256InfoRec.s3RefClk = 16000; /* default */ + } + + if (!DAC_IS_IBMRGB525) { + m = s3InIBMRGBIndReg(IBMRGB_sysclk_vco_div); + n = s3InIBMRGBIndReg(IBMRGB_sysclk_ref_div) & 0x1f; + df = m>>6; + m &= 0x3f; + if (!n) { m=0; n=1; } + mclk = ((vga256InfoRec.s3RefClk*100 * (m+65)) / n / (8 >> df) + 50) / 100; + } + if (xf86Verbose) { + ErrorF("%s %s: Using IBM RGB52x programmable clock", + s3ClockChipProbed, vga256InfoRec.name); + if (mclk) + ErrorF(" (MCLK %1.3f MHz)", mclk / 1000.0); + ErrorF("\n"); + ErrorF("%s %s: with refclock %1.3f MHz (probed %1.3f & %1.3f)\n", + refclock_probed,vga256InfoRec.name,vga256InfoRec.s3RefClk/1e3,f0,f1); + } + if (!vga256InfoRec.s3MClk) + vga256InfoRec.s3MClk = mclk; + } + else + OtherClocksSetup(); + + s3clockDoublingPossible = FALSE; + /* LCLK & SCLK limit is 100 MHz */ + if ((vga256InfoRec.dacSpeeds[0] * s3Bpp) / 8 > 100000) + vga256InfoRec.maxClock = (100000 * 8) / s3Bpp; + else + vga256InfoRec.maxClock = vga256InfoRec.dacSpeeds[s3Bpp - 1]; + + return 1; + } + + static void IBMRGB52x_Restore(vgaS3Ptr restore) + { + int i; + + if (DAC_IS_IBMRGB525) { + s3OutIBMRGBIndReg(IBMRGB_vram_mask_0, 0, 3); + s3OutIBMRGBIndReg(IBMRGB_misc1, ~0x40, 0x40); + usleep (1000); + s3OutIBMRGBIndReg(IBMRGB_misc2, ~1, 0); + } + for (i=0; i<0x100; i++) + s3OutIBMRGBIndReg(i, 0, restore->s3DacRegs[i]); + outb(vgaCRIndex, 0x22); + outb(vgaCRReg, restore->s3DacRegs[0x100]); + } + + static void IBMRGB52x_Save(vgaS3Ptr save) + { + int i; + + for (i=0; i<0x100; i++) { + save->s3DacRegs[i] = s3InIBMRGBIndReg(i); + } + outb(vgaCRIndex, 0x22); + save->s3DacRegs[0x100] = inb(vgaCRReg); + } + + static int IBMRGB52x_Init(DisplayModePtr mode) + { + unsigned char tmp, blank; + + outb(0x3C4, 1); + blank = inb(0x3C5); + outb(0x3C5, blank | 0x20); /* blank the screen */ + + if (DAC_IS_IBMRGB528) { + if (vga256InfoRec.clock[mode->Clock] <= 110000) + s3OutIBMRGBIndReg(IBMRGB_misc_clock, 0xf0, 0x01); + else if (vga256InfoRec.clock[mode->Clock] <= 220000) + s3OutIBMRGBIndReg(IBMRGB_misc_clock, 0xf0, 0x03); + else + s3OutIBMRGBIndReg(IBMRGB_misc_clock, 0xf0, 0x05); + } + else if (mode->Flags & V_DBLCLK) + s3OutIBMRGBIndReg(IBMRGB_misc_clock, 0xf0, 0x03); + else + s3OutIBMRGBIndReg(IBMRGB_misc_clock, 0xf0, 0x01); + + s3OutIBMRGBIndReg(IBMRGB_sync, 0, 0); + if ((mode->Private[0] & (1 << S3_BLANK_DELAY)) + && S3_968_SERIES(s3ChipId)) { + int pixels = (mode->Private[S3_BLANK_DELAY] & 0x07) * 8 / s3Bpp; + if (pixels > 15) pixels = 15; + s3OutIBMRGBIndReg(IBMRGB_hsync_pos, 0, pixels); + } + else if (s3Bpp < 3) + s3OutIBMRGBIndReg(IBMRGB_hsync_pos, 0, 0); + else + s3OutIBMRGBIndReg(IBMRGB_hsync_pos, 0, 2); + s3OutIBMRGBIndReg(IBMRGB_pwr_mgmt, 0, 0); + s3OutIBMRGBIndReg(IBMRGB_dac_op, ~8, s3DACSyncOnGreen ? 8 : 0); + s3OutIBMRGBIndReg(IBMRGB_dac_op, ~2, 1 /* fast slew */ ? 2 : 0); + s3OutIBMRGBIndReg(IBMRGB_pal_ctrl, 0, 0); + + /* set VRAM size to 128/64 bit and disable VRAM mask */ + if (DAC_IS_IBMRGB528) + s3OutIBMRGBIndReg(IBMRGB_misc1, ~0x43, 3); + else + s3OutIBMRGBIndReg(IBMRGB_misc1, ~0x43, 1); + if (s3DAC8Bit) + s3OutIBMRGBIndReg(IBMRGB_misc2, 0, 0x47); + else + s3OutIBMRGBIndReg(IBMRGB_misc2, 0, 0x43); + + #if 0 /* this will lock up the S3 chip & PC sometimes */ + outb(vgaCRIndex, 0x22); /* don't know why it's important */ + outb(vgaCRReg, 0xff); /* to set a "read only" register ?? */ + #else + outb(vgaCRIndex, 0x22); + tmp = inb(vgaCRReg); + if (s3Bpp == 1 && S3_968_SERIES(s3ChipId) && !DAC_IS_IBMRGB528) + outb(vgaCRReg, tmp | 8); + else + outb(vgaCRReg, tmp & ~8); + #endif + + outb(vgaCRIndex, 0x65); + if (DAC_IS_IBMRGB528) + outb(vgaCRReg, 0x80); + else + outb(vgaCRReg, 0); + + if (s3PixelMultiplexing) { + outb(vgaCRIndex, 0x40); + outb(vgaCRReg, 0x11); + outb(vgaCRIndex, 0x55); + outb(vgaCRReg, 0x00); + + if (vga256InfoRec.bitsPerPixel == 32) { /* 32 bpp */ + if(0){ + /* turn on color keying with key 0x00 */ + s3OutIBMRGBIndReg(0x68, 0, 0x00); + s3OutIBMRGBIndReg(0x6c, 0, 0xFF); + s3OutIBMRGBIndReg(0x78, 0xFE, 0x01); + } + s3OutIBMRGBIndReg(IBMRGB_pix_fmt, 0xf8, 6); + s3OutIBMRGBIndReg(IBMRGB_32bpp, 0, 0x03); + } else if (vga256InfoRec.bitsPerPixel == 24) { /* 24 bpp */ + s3OutIBMRGBIndReg(IBMRGB_pix_fmt, 0xf8, 5); + s3OutIBMRGBIndReg(IBMRGB_24bpp, 0, 0x01); + } else if (vga256InfoRec.bitsPerPixel == 16) { + if(xf86weight.green == 5) { /* 15 bpp */ + s3OutIBMRGBIndReg(IBMRGB_pix_fmt, 0xf8, 4); + s3OutIBMRGBIndReg(IBMRGB_16bpp, 0, 0xC0); + } else { /* 16 bpp */ + s3OutIBMRGBIndReg(IBMRGB_pix_fmt, 0xf8, 4); + s3OutIBMRGBIndReg(IBMRGB_16bpp, 0, 0xC2); + } + } else { /* 8 bpp */ + s3OutIBMRGBIndReg(IBMRGB_pix_fmt, 0xf8, 3); + s3OutIBMRGBIndReg(IBMRGB_8bpp, 0, 0); + } + /* if (DAC_IS_RGB528) tmp++; */ + + outb(vgaCRIndex, 0x66); + tmp = inb(vgaCRReg) & 0xf8; + if (DAC_IS_IBMRGB528) { + int tmp2; + tmp = tmp & 0x80 | 0x60; /* 128 bit SID mode */ + if (vga256InfoRec.clock[mode->Clock] <= 110000) tmp2 = 3; + else if (vga256InfoRec.clock[mode->Clock] <= 220000) tmp2 = 2; + else tmp2 = 1; + if (s3Bpp == 2) tmp2--; + else if (s3Bpp == 4) { + if (tmp2 >= 2) tmp2 -= 2; + else tmp2 = 0; + } + tmp |= tmp2; + } + else if (!S3_968_SERIES(s3ChipId)) { + if (s3Bpp == 1) tmp |= 3; + else if (s3Bpp == 2) tmp |= 2; + else /* if (s3Bpp == 4) */ tmp |= 1; + if (mode->Flags & V_DBLCLK) tmp--; + } + outb(vgaCRReg, tmp); + + /* + * set the serial access mode 256 words control + */ + outb(vgaCRIndex, 0x58); + tmp = (inb(vgaCRReg) & 0xbf) | s3SAM256; + outb(vgaCRReg, tmp); + + outb(vgaCRIndex, 0x67); + if (DAC_IS_IBMRGB528) + if (s3Bpp == 1) + outb(vgaCRReg, 0x01); + else + outb(vgaCRReg, 0x00); + else if (s3Bpp == 4) + if (DAC_IS_IBMRGB && S3_968_SERIES(s3ChipId)) + outb(vgaCRReg, 0x10); + else + outb(vgaCRReg, 0x00); + else + if (S3_968_SERIES(s3ChipId)) + outb(vgaCRReg, 0x11); + else + outb(vgaCRReg, 0x01); + + outb(vgaCRIndex, 0x6d); + if (s3Bpp == 1) + outb(vgaCRReg, 0x21); + else if (s3Bpp == 2) + outb(vgaCRReg, 0x10); + else /* if (s3Bpp == 4) */ + outb(vgaCRReg, 0x00); + + } else { + /* set s3 reg53 to non-parallel addressing by and'ing 0xDF */ + outb(vgaCRIndex, 0x53); + tmp = inb(vgaCRReg) & 0xDF; + outb(vgaCRReg, tmp); + + /* set s3 reg55 to non-external serial by and'ing 0xF7 */ + outb(vgaCRIndex, 0x55); + tmp = inb(vgaCRReg) & 0xF7; + outb(vgaCRReg, tmp); + + /* provide pseudocolor VGA */ + s3OutIBMRGBIndReg(IBMRGB_misc2, 0, 0); + } /* end of s3PixelMultiplexing */ + + if (DAC_IS_IBMRGB528) { + /* set s3 reg53 to parallel addressing */ + outb(vgaCRIndex, 0x53); + tmp = inb(vgaCRReg); + outb(vgaCRReg, tmp | 0x20); + } + + #if 0 + if (OFLG_ISSET(OPTION_IBMRGB_CURS, &vga256InfoRec.options)) { + /* enable interlaced cursor; + not very useful without CR45 bit 5 set, but anyway */ + if (mode->Flags & V_INTERLACE) { + static int already = 0; + if (!already) { + already++; + ErrorF("%s %s: IBMRGB hardware cursor in interlaced modes " + "doesn't work correctly,\n" + "\tplease use Option \"sw_cursor\" when using " + "interlaced modes!\n" + ,XCONFIG_PROBED, vga256InfoRec.name); + } + s3OutIBMRGBIndReg(TI_CURS_CONTROL, ~0x60, 0x60); + } + else + s3OutIBMRGBIndReg(TI_CURS_CONTROL, ~0x60, 0x00); + } + #endif + + outb(0x3C4, 1); + outb(0x3C5, blank); /* unblank the screen */ + + return 1; + } + + /***********************************************************\ + + ATT20C490_DAC + SS2410_DAC + SC1148x_DAC + + \***********************************************************/ + + #define Setcomm(v) (xf86dactocomm(),outb(0x3C6,v),\ + xf86dactocomm(),inb(0x3C6)) + + static Bool MISC_HI_COLOR_Probe(int type) + { + int found = 0; + unsigned char tmp, olddacpel, olddaccomm, notdaccomm; + + /*quick check*/ + if(!S3_8XX_9XX_SERIES(s3ChipId)) + return FALSE; + + (void) xf86dactocomm(); + olddaccomm = inb(0x3C6); + xf86dactopel(); + olddacpel = inb(0x3C6); + + notdaccomm = ~olddaccomm; + outb(0x3C6, notdaccomm); + (void) xf86dactocomm(); + + if (inb(0x3C6) != notdaccomm) { + /* Looks like a HiColor RAMDAC */ + if ((Setcomm(0xE0) & 0xE0) == 0xE0) { + if ((Setcomm(0x60) & 0xE0) == 0x00) { + if ((Setcomm(0x02) & 0x02) != 0x00) { + found = ATT20C490_DAC; + } + } else { + tmp = Setcomm(olddaccomm); + if (inb(0x3C6) != notdaccomm) { + (void) inb(0x3C6); + (void) inb(0x3C6); + (void) inb(0x3C6); + if (inb(0x3C6) != notdaccomm) { + xf86dactopel(); + outb(0x3C6, 0xFF); + (void) inb(0x3C6); + (void) inb(0x3C6); + (void) inb(0x3C6); + switch (inb(0x3C6)) { + case 0x44: + case 0x82: + break; + case 0x8E: + found = SS2410_DAC; + break; + default: + xf86dactopel(); + outb(0x3C6, olddacpel & 0xFB); + xf86dactocomm(); + outb(0x3C6, olddaccomm & 0x04); + tmp = inb(0x3C6); + outb(0x3C6, tmp & 0xFB); + if ((tmp & 0x04) == 0) { + found = SC1148x_DAC; + } + } + } + } + } + } + } + (void) xf86dactocomm(); + outb(0x3C6, olddaccomm); + xf86dactopel(); + outb(0x3C6, olddacpel); + + return (found == type); + } + #undef Setcomm + + static Bool SC1148x_Probe() + { + return MISC_HI_COLOR_Probe(SC1148x_DAC); + } + + static Bool SS2410_Probe() + { + return MISC_HI_COLOR_Probe(SS2410_DAC); + } + + static Bool ATT20C490_Probe() + { + return MISC_HI_COLOR_Probe(ATT20C490_DAC); + } + + static int MISC_HI_COLOR_PreInit() + { + /* Verify that depth is supported by ramdac */ + switch(s3RamdacType) { + case SC1148x_DAC: + if ( vga256InfoRec.depth > 16 ) { + ErrorF("Depths greater than 16bpp are not supported for " + "the Sierra 1148x RAMDAC.\n"); + return 0; + } + break; + case SS2410_DAC: + if ( vga256InfoRec.depth > 24 ) { + ErrorF("Depths greater than 24bpp are not supported for " + "the Diamond SS2410 RAMDAC.\n"); + return 0; + } + break; + case ATT20C490_DAC: + if (s3Bpp > 2) { + ErrorF("Depths greater than 16bpp are not supported for " + "the ATT20C490 RAMDAC.\n"); + return 0; + } + break; + default: + ErrorF("Internal error in MISC_HI_COLOR_PreInit().\n"); + return 0; + } + + + /* Check if PixMux is supported and set the PixMux + related flags and variables */ + /* No PixMux */ + + /* Set Clock options, s3ClockSelectFunc, & s3maxRawClock + for internal clocks. Pass the job to the OtherClocksSetup() + function for external clocks*/ + OtherClocksSetup(); + + vga256InfoRec.maxClock = vga256InfoRec.dacSpeeds[s3Bpp - 1]; + /* Halve it for 16bpp (32bpp not supported) */ + if (s3Bpp > 1) { + vga256InfoRec.maxClock /= 2; + s3maxRawClock /= 2; + } + + return 1; + } + + + static void SC1148x_Restore(vgaS3Ptr restore) + { + xf86setdaccomm(restore->s3DacRegs[0]); + } + + static void ATT20C490_Restore(vgaS3Ptr restore) + { + xf86setdaccomm(restore->s3DacRegs[0]); + } + + static void SS2410_Restore(vgaS3Ptr restore) + { + unsigned char tmp; + + outb( vgaCRIndex, 0x55 ); + tmp = inb( vgaCRReg ); + outb( vgaCRReg, tmp | 1 ); + xf86setdaccomm(restore->s3DacRegs[0]); + outb( vgaCRReg, tmp ); + } + + static void SC1148x_Save(vgaS3Ptr save) + { + save->s3DacRegs[0] = xf86getdaccomm(); + } + + static void ATT20C490_Save(vgaS3Ptr save) + { + save->s3DacRegs[0] = xf86getdaccomm(); + } + + static void SS2410_Save(vgaS3Ptr save) + { + unsigned char tmp; + + outb( vgaCRIndex, 0x55 ); + tmp = inb( vgaCRReg ); + outb( vgaCRReg, tmp | 1 ); + save->s3DacRegs[0] = xf86getdaccomm( ); + outb( vgaCRReg, tmp ); + } + + static int SC1148x_Init(DisplayModePtr mode) + { + if (vga256InfoRec.bitsPerPixel == 8) { + xf86clrdaccommbit(0xe0); + } else { + if (vga256InfoRec.depth == 16) { + xf86setdaccommbit(0xe0); + } else if (vga256InfoRec.depth == 15) { + xf86setdaccommbit(0xa0); + } else { + ErrorF("Depths greater than 16bpp are not supported by the SC1148x!\n"); + return 0; + } + } + return 1; + } + + static int ATT20C490_Init(DisplayModePtr mode) + { + if (vga256InfoRec.bitsPerPixel == 8) { + if (s3DAC8Bit) { + xf86setdaccomm(0x02); + } else { + xf86setdaccomm(0x00); + } + } else { + switch (vga256InfoRec.depth) { + case 15: + xf86setdaccomm(0xa0); + break; + case 16: + xf86setdaccomm(0xc0); + break; + case 24: + case 32: + xf86setdaccomm(0xe0); /* XXXX just a guess, check !!! */ + break; + default: + ErrorF("Bad depth %i!\n",vga256InfoRec.depth); + return 0; + } + } + return 1; + } + + static int SS2410_Init(DisplayModePtr mode) + { + register unsigned char tmp; + + if ( vga256InfoRec.bitsPerPixel == 8 ) { + outb( vgaCRIndex, 0x55 ); + tmp = inb( vgaCRReg ); + outb( vgaCRReg, tmp | 1 ); + xf86setdaccomm( 0 ); + outb( vgaCRReg, tmp ); + } else { + switch ( vga256InfoRec.depth ) { + case 15: + outb( vgaCRIndex, 0x55 ); + tmp = inb( vgaCRReg ); + outb( vgaCRReg, tmp | 1 ); + xf86setdaccomm( 0xA0 ); + outb( vgaCRReg, tmp ); + break; + case 16: + outb( vgaCRIndex, 0x55 ); + tmp = inb( vgaCRReg ); + outb( vgaCRReg, tmp | 1 ); + xf86setdaccomm( 0xA6 ); + outb( vgaCRReg, tmp ); + break; + case 24: + outb( vgaCRIndex, 0x55 ); + tmp = inb( vgaCRReg ); + outb( vgaCRReg, tmp | 1 ); + xf86setdaccomm( 0x9E ); + outb( vgaCRReg, tmp ); + break; + default: + ErrorF("Bad depth %i!\n",vga256InfoRec.depth); + return 0; + + } + } + + return 1; + } + + /*****************************************************\ + + NORMAL_DAC + + \*****************************************************/ + + static Bool NORMAL_Probe() + { + return TRUE; + } + + static int NORMAL_PreInit() + { + /* Verify that depth is supported by ramdac */ + if(s3Bpp > 1) { + ErrorF("Depths greater than 8bpp are not supported for a " + "\"normal\" RAMDAC.\n"); + return 0; /* BAD_DEPTH */ + } + + /* Check if PixMux is supported and set the PixMux + related flags and variables */ + /* of course not */ + + /* If there is an internal clock, set s3ClockSelectFunc, s3maxRawClock + s3numClocks and whatever options need to be set. For external + clocks, pass the job to OtherClocksSetup() */ + OtherClocksSetup(); + + /* anything else */ + vga256InfoRec.maxClock = 100000; /* ???? MArk */ + + return 1; + } + + + + /**********************************************************\ + + THE CLOCKS + + \**********************************************************/ + + + void OtherClocksSetup() + { + /*******************************************\ + | Clocks that aren't built into the ramdac | + \*******************************************/ + + if (OFLG_ISSET(OPTION_LEGEND, &vga256InfoRec.options)) { + s3ClockSelectFunc = LegendClockSelect; + s3numClocks = 32; + /* s3maxRawClock = ; (MArk) what to do here? */ + if (xf86Verbose) + ErrorF("%s %s: Using Sigma Legend ICS 1394-046 clock generator\n", + s3ClockChipProbed, vga256InfoRec.name); + } else if (OFLG_ISSET(CLOCK_OPTION_ICD2061A, &vga256InfoRec.clockOptions)) { + s3ClockSelectFunc = icd2061ClockSelect; + s3numClocks = 3; + s3maxRawClock = 120000; + if (xf86Verbose) + ErrorF("%s %s: Using ICD2061A programmable clock\n", + s3ClockChipProbed, vga256InfoRec.name); + } else if (OFLG_ISSET(CLOCK_OPTION_GLORIA8, &vga256InfoRec.clockOptions)) { + s3ClockSelectFunc = Gloria8ClockSelect; + s3numClocks = 3; + /* s3maxRawClock = ; (MArk) what to do here? */ + if (xf86Verbose) + ErrorF("%s %s: Using ELSA Gloria-8 ICS9161/TVP3030 programmable " + "clock\n",s3ClockChipProbed, vga256InfoRec.name); + } else if (OFLG_ISSET(CLOCK_OPTION_SC11412, &vga256InfoRec.clockOptions)) { + s3ClockSelectFunc = icd2061ClockSelect; + s3numClocks = 3; + if (OFLG_ISSET(CLOCK_OPTION_SC11412, &vga256InfoRec.clockOptions)) { + if (!OFLG_ISSET(OPTION_SPEA_MERCURY, &vga256InfoRec.options)) { + switch (s3RamdacType) { + case BT485_DAC: + s3maxRawClock = 67500; + break; + case ATT20C505_DAC: + s3maxRawClock = 90000; + break; + default: + s3maxRawClock = 100000; + break; + } + } else { + s3maxRawClock = 100000; + } + } + if (xf86Verbose) + ErrorF("%s %s: Using Sierra SC11412 programmable clock\n", + s3ClockChipProbed, vga256InfoRec.name); + } else if (OFLG_ISSET(CLOCK_OPTION_ICS2595, &vga256InfoRec.clockOptions)) { + s3ClockSelectFunc = icd2061ClockSelect; + s3numClocks = 3; + s3maxRawClock = 145000; /* This is what is in common_hw/ICS2595.h */ + if (xf86Verbose) + ErrorF("%s %s: Using ICS2595 programmable clock\n", + XCONFIG_GIVEN, vga256InfoRec.name); + } else if (OFLG_ISSET(CLOCK_OPTION_CH8391, &vga256InfoRec.clockOptions)) { + s3ClockSelectFunc = ch8391ClockSelect; + s3numClocks = 3; + s3maxRawClock = 135000; + if (xf86Verbose) + ErrorF("%s %s: Using Chrontel 8391 programmable clock\n", + XCONFIG_GIVEN, vga256InfoRec.name); + } else if (OFLG_ISSET(CLOCK_OPTION_S3GENDAC, &vga256InfoRec.clockOptions) || + OFLG_ISSET(CLOCK_OPTION_ICS5342, &vga256InfoRec.clockOptions)) { + unsigned char saveCR55; + int m,n,n1,n2, mclk; + + s3ClockSelectFunc = s3GendacClockSelect; + s3numClocks = 3; + s3maxRawClock = 110000; + + outb(vgaCRIndex, 0x55); + saveCR55 = inb(vgaCRReg); + outb(vgaCRReg, saveCR55 | 1); + + outb(0x3C7, 10); /* read MCLK */ + m = inb(0x3C9); + n = inb(0x3C9); + + outb(vgaCRIndex, 0x55); + outb(vgaCRReg, saveCR55); + + m &= 0x7f; + n1 = n & 0x1f; + n2 = (n>>5) & 0x03; + mclk = ((1431818 * (m+2)) / (n1+2) / (1 << n2) + 50) / 100; + + if (xf86Verbose) + ErrorF("%s %s: Using %s programmable clock (MCLK %1.3f MHz)\n" + ,s3ClockChipProbed, vga256InfoRec.name + ,OFLG_ISSET(CLOCK_OPTION_ICS5342, &vga256InfoRec.clockOptions) + ? "ICS5342" : "S3 Gendac/SDAC" + ,mclk / 1000.0); + if (vga256InfoRec.s3MClk > 0) { + if (xf86Verbose) + ErrorF("%s %s: using specified MCLK value of %1.3f MHz for DRAM " + "timings\n",XCONFIG_GIVEN, vga256InfoRec.name, vga256InfoRec.s3MClk/1000.0); + } else { + vga256InfoRec.s3MClk = mclk; + } + } else { + s3ClockSelectFunc = s3ClockSelect; + s3numClocks = 16; + if (!vga256InfoRec.clocks) + vgaGetClocks(s3numClocks, s3ClockSelectFunc); + } + + } + + + + static Bool + s3ClockSelect(no) + int no; + + { + unsigned char temp; + static unsigned char save1, save2; + + UNLOCK_SYS_REGS; + + switch(no) + { + case CLK_REG_SAVE: + save1 = inb(0x3CC); + outb(vgaCRIndex, 0x42); + save2 = inb(vgaCRReg); + break; + case CLK_REG_RESTORE: + outb(0x3C2, save1); + outb(vgaCRIndex, 0x42); + outb(vgaCRReg, save2); + break; + default: + no &= 0xF; + if (no == 0x03) + { + /* + * Clock index 3 is a 0Hz clock on all the S3-recommended + * synthesizers (except the Chrontel). A 0Hz clock will lock up + * the chip but good (requiring power to be cycled). Nuke that. + */ + LOCK_SYS_REGS; + return(FALSE); + } + temp = inb(0x3CC); + outb(0x3C2, temp | 0x0C); + outb(vgaCRIndex, 0x42); + temp = inb(vgaCRReg) & 0xf0; + outb(vgaCRReg, temp | no); + usleep(150000); + } + LOCK_SYS_REGS; + return(TRUE); + } + + + + static Bool + LegendClockSelect(no) + int no; + { + + /* + * Sigma Legend special handling + * + * The Legend uses an ICS 1394-046 clock generator. This can generate 32 + * different frequencies. The Legend can use all 32. Here's how: + * + * There are two flip/flops used to latch two inputs into the ICS clock + * generator. The five inputs to the ICS are then + * + * ICS ET-4000 --- --- FS0 CS0 FS1 CS1 FS2 ff0 flip/flop 0 + * outbut FS3 CS2 FS4 ff1 flip/flop 1 outbut + * + * The flip/flops are loaded from CS0 and CS1. The flip/flops are latched by + * CS2, on the rising edge. After CS2 is set low, and then high, it is then + * set to its final value. + * + */ + static unsigned char save1, save2; + unsigned char temp = inb(0x3CC); + + switch(no) + { + case CLK_REG_SAVE: + save1 = inb(0x3CC); + outb(vgaCRIndex, 0x34); + save2 = inb(vgaCRReg); + break; + case CLK_REG_RESTORE: + outb(0x3C2, save1); + outw(vgaCRIndex, 0x34 | (save2 << 8)); + break; + default: + outb(0x3C2, (temp & 0xF3) | ((no & 0x10) >> 1) | (no & 0x04)); + outw(vgaCRIndex, 0x0034); + outw(vgaCRIndex, 0x0234); + outw(vgaCRIndex, ((no & 0x08) << 6) | 0x34); + outb(0x3C2, (temp & 0xF3) | ((no << 2) & 0x0C)); + } + return(TRUE); + } + + + + + static Bool + icd2061ClockSelect(freq) + int freq; + { + Bool result = TRUE; + + UNLOCK_SYS_REGS; + switch(freq) + { + case CLK_REG_SAVE: + case CLK_REG_RESTORE: + result = s3ClockSelect(freq); + break; + default: + { + /* Convert freq to Hz */ + freq *= 1000; + /* Use the "Alt" version always since it is more reliable */ + if (OFLG_ISSET(CLOCK_OPTION_ICD2061A, &vga256InfoRec.clockOptions)) { + /* setting exactly 120 MHz doesn't work all the time */ + if (freq > 119900000) freq = 119900000; + #if defined(PC98_PW) || defined(PC98_PWLB) + AltICD2061SetClock(freq, 0); + #else + AltICD2061SetClock(freq, 2); + AltICD2061SetClock(freq, 2); + AltICD2061SetClock(freq, 2); + #endif + if (DAC_IS_TI3026 || DAC_IS_TI3030) { + /* + * then we need to setup the loop clock + */ + Ti3026SetClock(freq/1000, 2, s3Bpp, TI_LOOP_CLOCK); + s3OutTi3026IndReg(TI_MCLK_LCLK_CONTROL, ~0x20, 0x20); + } + } else if (OFLG_ISSET(CLOCK_OPTION_SC11412, &vga256InfoRec.clockOptions)) { + result = SC11412SetClock((long)freq/1000); + } else if (OFLG_ISSET(CLOCK_OPTION_ICS2595, &vga256InfoRec.clockOptions)) { + result = ICS2595SetClock((long)freq/1000); + result = ICS2595SetClock((long)freq/1000); + } else { /* Should never get here */ + result = FALSE; + break; + } + + if (!OFLG_ISSET(CLOCK_OPTION_ICS2595, &vga256InfoRec.clockOptions)) { + unsigned char tmp; + outb(vgaCRIndex, 0x42);/* select the clock */ + tmp = inb(vgaCRReg) & 0xf0; + if (OFLG_ISSET(OPTION_SPEA_MERCURY, &vga256InfoRec.options) && + S3_964_SERIES(s3ChipId)) /* SPEA Mercury P64 uses bit2/3 */ + outb(vgaCRReg, tmp | 0x06); /* for synchronizing reasons (?) */ + else outb(vgaCRReg, tmp | 0x02); + usleep(150000); + } + /* Do the clock doubler selection in s3Init() */ + } + } + LOCK_SYS_REGS; + return(result); + } + + + + + /* the ELSA Gloria-8 uses a TVP3030 with ICS9161 as refclock */ + + static Bool + Gloria8ClockSelect(freq) + int freq; + { + Bool result = TRUE; + unsigned char tmp; + int p; + + UNLOCK_SYS_REGS; + switch(freq) + { + case CLK_REG_SAVE: + case CLK_REG_RESTORE: + result = s3ClockSelect(freq); + break; + default: + for(p=0; p<4; p++) + if ((freq << p) >= 120000) break; + + AltICD2061SetClock((freq * 1000) >> (3-p), 2); + + Ti3030SetClock(14318 << (3-p), 2, s3Bpp, TI_BOTH_CLOCKS); + Ti3030SetClock(freq, 2, s3Bpp, TI_LOOP_CLOCK); + s3OutTi3026IndReg(TI_MCLK_LCLK_CONTROL, ~0x38, 0x30); + s3OutTi3026IndReg(TI_MCLK_LCLK_CONTROL, ~0x38, 0x38); + + outb(vgaCRIndex, 0x42);/* select the clock */ + tmp = inb(vgaCRReg) & 0xf0; + outb(vgaCRReg, tmp | 0x06); + } + LOCK_SYS_REGS; + return(result); + } + + + + + + + /* The GENDAC code also works for the SDAC, used for Trio32/Trio64 too */ + + static Bool + s3GendacClockSelect(freq) + int freq; + + { + Bool result = TRUE; + unsigned char tmp; + + UNLOCK_SYS_REGS; + + switch(freq) + { + case CLK_REG_SAVE: + case CLK_REG_RESTORE: + result = s3ClockSelect(freq); + break; + default: + { + #if defined(PC98_PW) + (void) S3gendacSetClock(freq, 7); /* PW805i can't use reg 2 */ + #else + + if (S3_TRIOxx_SERIES(s3ChipId)) { + if (OFLG_ISSET(CLOCK_OPTION_S3AURORA, &vga256InfoRec.clockOptions)) + (void) S3AuroraSetClock(freq, 2); /* can't fail */ + else if (OFLG_ISSET(CLOCK_OPTION_S3TRIO64V2, &vga256InfoRec.clockOptions)) + (void) S3Trio64V2SetClock(freq, 2); /* can't fail */ + else + (void) S3TrioSetClock(freq, 2); /* can't fail */ + } + else { + if (OFLG_ISSET(CLOCK_OPTION_ICS5342, &vga256InfoRec.clockOptions)) + (void) ICS5342SetClock(freq, 2); /* can't fail */ + else + (void) S3gendacSetClock(freq, 2); /* can't fail */ + #endif + outb(vgaCRIndex, 0x42);/* select the clock */ + #if defined(PC98_PW) + tmp = inb(vgaCRReg) & 0xf0; + outb(vgaCRReg, tmp | 0x07); + #else + tmp = inb(vgaCRReg) & 0xf0; + outb(vgaCRReg, tmp | 0x02); + #endif + usleep(150000); + #if !defined(PC98_PW) + } + #endif + } + } + LOCK_SYS_REGS; + return(result); + } + + + + static void + #if NeedFunctionPrototypes + s3ProgramTi3025Clock( + int clk, + unsigned char n, + unsigned char m, + unsigned char p) + #else + s3ProgramTi3025Clock(clk, n, m, p) + int clk; + unsigned char n; + unsigned char m; + unsigned char p; + #endif + { + /* + * Reset the clock data index + */ + s3OutTiIndReg(TI_PLL_CONTROL, 0x00, 0x00); + + if (clk != TI_MCLK_PLL_DATA) { + /* + * Now output the clock frequency + */ + s3OutTiIndReg(TI_PIXEL_CLOCK_PLL_DATA, 0x00, n); + s3OutTiIndReg(TI_PIXEL_CLOCK_PLL_DATA, 0x00, m); + s3OutTiIndReg(TI_PIXEL_CLOCK_PLL_DATA, 0x00, p | TI_PLL_ENABLE); + + /* + * And now set up the loop clock for RCLK + */ + s3OutTiIndReg(TI_LOOP_CLOCK_PLL_DATA, 0x00, 0x01); + s3OutTiIndReg(TI_LOOP_CLOCK_PLL_DATA, 0x00, 0x01); + s3OutTiIndReg(TI_LOOP_CLOCK_PLL_DATA, 0x00, p>0 ? p : 1); + s3OutTiIndReg(TI_MISC_CONTROL, 0x00, + TI_MC_LOOP_PLL_RCLK | TI_MC_LCLK_LATCH | TI_MC_INT_6_8_CONTROL); + + /* + * And finally enable the clock + */ + s3OutTiIndReg(TI_INPUT_CLOCK_SELECT, 0x00, TI_ICLK_PLL); + } else { + /* + * Set MCLK + */ + s3OutTiIndReg(TI_MCLK_PLL_DATA, 0x00, n); + s3OutTiIndReg(TI_MCLK_PLL_DATA, 0x00, m); + s3OutTiIndReg(TI_MCLK_PLL_DATA, 0x00, p | 0x80); + } + } + + + + + static Bool + ti3025ClockSelect(freq) + int freq; + + { + Bool result = TRUE; + unsigned char tmp; + + UNLOCK_SYS_REGS; + + switch(freq) + { + case CLK_REG_SAVE: + case CLK_REG_RESTORE: + result = s3ClockSelect(freq); + break; + default: + { + /* Check if clock frequency is within range */ + /* XXXX Check this elsewhere */ + if (freq < 20000) { + ErrorF("%s %s: Specified dot clock (%.3f) too low for TI 3025", + XCONFIG_PROBED, vga256InfoRec.name, freq / 1000.0); + result = FALSE; + break; + } + (void) Ti3025SetClock(freq, 2, s3ProgramTi3025Clock); /* can't fail */ + outb(vgaCRIndex, 0x42);/* select the clock */ + tmp = inb(vgaCRReg) & 0xf0; + outb(vgaCRReg, tmp | 0x02); + usleep(150000); + } + } + LOCK_SYS_REGS; + return(result); + } + + + + + static Bool + ti3026ClockSelect(freq) + int freq; + + { + Bool result = TRUE; + unsigned char tmp; + + UNLOCK_SYS_REGS; + + switch(freq) + { + case CLK_REG_SAVE: + case CLK_REG_RESTORE: + result = s3ClockSelect(freq); + break; + default: + { + /* Check if clock frequency is within range */ + /* XXXX Check this elsewhere */ + if (freq < 13750) { + ErrorF("%s %s: Specified dot clock (%.3f) too low for Ti3026/3030", + XCONFIG_PROBED, vga256InfoRec.name, freq / 1000.0); + result = FALSE; + break; + } + (void) Ti3026SetClock(freq, 2, s3Bpp, TI_BOTH_CLOCKS); /* can't fail */ + outb(vgaCRIndex, 0x42);/* select the clock */ + tmp = inb(vgaCRReg) & 0xf0; + outb(vgaCRReg, tmp | 0x02); + } + } + LOCK_SYS_REGS; + return(result); + } + + + + + static Bool + IBMRGBClockSelect(freq) + int freq; + + { + Bool result = TRUE; + + UNLOCK_SYS_REGS; + + switch(freq) + { + case CLK_REG_SAVE: + case CLK_REG_RESTORE: + result = s3ClockSelect(freq); + break; + default: + { + /* Check if clock frequency is within range */ + /* XXXX Check this elsewhere */ + if (freq < 16250) { + ErrorF("%s %s: Specified dot clock (%.3f) too low for IBM RGB52x\n", + XCONFIG_PROBED, vga256InfoRec.name, freq / 1000.0); + result = FALSE; + break; + } + (void)IBMRGBSetClock(freq, 2, vga256InfoRec.maxClock, + vga256InfoRec.s3RefClk); + } + } + LOCK_SYS_REGS; + return(result); + } + + + + + static Bool + ch8391ClockSelect(freq) + int freq; + + { + Bool result = TRUE; + unsigned char tmp; + + UNLOCK_SYS_REGS; + + switch(freq) + { + case CLK_REG_SAVE: + case CLK_REG_RESTORE: + result = s3ClockSelect(freq); + break; + default: + { + /* Check if clock frequency is within range */ + /* XXXX Check this elsewhere */ + if (freq < 8500 || freq > 135000) { + ErrorF("%s %s: Specified dot clock (%.3f) out of range for Chrontel 8391", + XCONFIG_PROBED, vga256InfoRec.name, freq / 1000.0); + result = FALSE; + break; + } + (void) Chrontel8391SetClock(freq, 2); /* can't fail */ + outb(vgaCRIndex, 0x42);/* select the clock */ + tmp = inb(vgaCRReg) & 0xf0; + outb(vgaCRReg, tmp | 0x02); + usleep(150000); + } + } + LOCK_SYS_REGS; + return(result); + } + + + + + static Bool + att409ClockSelect(freq) + int freq; + + { + Bool result = TRUE; + unsigned char tmp; + + UNLOCK_SYS_REGS; + + switch(freq) + { + case CLK_REG_SAVE: + case CLK_REG_RESTORE: + result = s3ClockSelect(freq); + break; + default: + { + /* Check if clock frequency is within range */ + /* XXXX Check this elsewhere */ + if (freq < 15000 || freq > 240000) { + ErrorF("%s %s: Specified dot clock (%.3f) out of range for ATT20C409", + XCONFIG_PROBED, vga256InfoRec.name, freq / 1000.0); + result = FALSE; + break; + } + (void) Att409SetClock(freq, 2); /* can't fail */ + outb(vgaCRIndex, 0x42);/* select the clock */ + tmp = inb(vgaCRReg) & 0xf0; + outb(vgaCRReg, tmp | 0x02); + usleep(150000); + } + } + LOCK_SYS_REGS; + return(result); + } + + + + + static Bool + STG1703ClockSelect(freq) + int freq; + + { + Bool result = TRUE; + unsigned char tmp; + + UNLOCK_SYS_REGS; + + switch(freq) + { + case CLK_REG_SAVE: + case CLK_REG_RESTORE: + result = s3ClockSelect(freq); + break; + default: + { + /* Check if clock frequency is within range */ + /* XXXX Check this elsewhere */ + if (freq < 8500 || freq > 135000) { + ErrorF("%s %s: Specified dot clock (%.3f) out of range for STG1703", + XCONFIG_PROBED, vga256InfoRec.name, freq / 1000.0); + result = FALSE; + break; + } + (void) STG1703SetClock(freq, 2); /* can't fail */ + outb(vgaCRIndex, 0x42);/* select the clock */ + tmp = inb(vgaCRReg) & 0xf0; + outb(vgaCRReg, tmp | 0x02); + usleep(150000); + } + } + LOCK_SYS_REGS; + return(result); + } + + static unsigned char *find_bios_string(int BIOSbase, char *match1, char *match2) + { + #define BIOS_BSIZE 1024 + #define BIOS_BASE 0xc0000 + + static unsigned char bios[BIOS_BSIZE]; + static int init=0; + int i,j,l1,l2; + + if (!init) { + init = 1; + if (xf86ReadBIOS(BIOSbase, 0, bios, BIOS_BSIZE) != BIOS_BSIZE) + return NULL; + if ((bios[0] != 0x55) || (bios[1] != 0xaa)) + return NULL; + } + if (match1 == NULL) + return NULL; + + l1 = strlen(match1); + if (match2 != NULL) + l2 = strlen(match2); + else /* for compiler-warnings */ + l2 = 0; + + for (i=0; i<BIOS_BSIZE-l1; i++) + if (bios[i] == match1[0] && !memcmp(&bios[i],match1,l1)) + if (match2 == NULL) + return &bios[i+l1]; + else + for(j=i+l1; (j<BIOS_BSIZE-l2) && bios[j]; j++) + if (bios[j] == match2[0] && !memcmp(&bios[j],match2,l2)) + return &bios[j+l2]; + return NULL; + } + + + + static int s3DetectMIRO_20SV_Rev(int BIOSbase) + { + char *match1 = "miroCRYSTAL\37720SV", *match2 = "Rev."; + unsigned char *p; + + if ((p = find_bios_string(BIOSbase,match1,match2)) != NULL) { + if (s3BiosVendor == UNKNOWN_BIOS) + s3BiosVendor = MIRO_BIOS; + if (*p >= '0' && *p <= '9') + return *p - '0'; + } + return -1; + } + + + static void Probe_ELSA() + { + char *card, *serno, *elsa_modes; + int card_id, max_pix_clock, max_mem_clock, hwconf; + static int only_once=0; + + if (only_once) + return; + only_once = 1; + + card_id = s3DetectELSA(vga256InfoRec.BIOSbase, &card, &serno, &max_pix_clock, + &max_mem_clock, &hwconf, &elsa_modes); + if (card_id > 0) { + if (s3BiosVendor == UNKNOWN_BIOS) + s3BiosVendor = ELSA_BIOS; + if (xf86Verbose) { + ErrorF("%s %s: card: %s, Ser.No. %s\n", + XCONFIG_PROBED, vga256InfoRec.name, card, serno); + if (elsa_modes && *elsa_modes) + ErrorF("%s %s: video modes stores in ELSA EEPROM:\n%s", + XCONFIG_PROBED, vga256InfoRec.name, elsa_modes); + } + xfree(card); + xfree(serno); + xfree(elsa_modes); + + if (vga256InfoRec.dacSpeeds[0] <= 0) + vga256InfoRec.dacSpeeds[0] = max_pix_clock; + + do { + switch (card_id) { + case ELSA_WINNER_1000AVI: + case ELSA_WINNER_1000PRO: + /* This option isn't required at the moment */ + OFLG_SET(OPTION_ELSA_W1000PRO, &vga256InfoRec.options); + /* fallthrough */ + case ELSA_WINNER_1000: + case ELSA_WINNER_1000VL: + case ELSA_WINNER_1000PCI: + case ELSA_WINNER_1000ISA: + if ((s3Ramdacs[S3_SDAC_DAC].DacProbe)()) { + s3RamdacType = S3_SDAC_DAC; + continue; /* SDAC detected, don't set ICD2061A clock */ + } + if((s3Ramdacs[ATT20C409_DAC].DacProbe)()) + s3RamdacType = ATT20C409_DAC; + /* if ATT20C409 is detected, the clockchip is + * already set apropriately + */ + /* otherwise it's a STG1700,20C498, or SC15025 and will get + detected later. The clockchip ICD2061A will get set at + the at the end of this loop */ + break; + case ELSA_WINNER_2000PRO: + OFLG_SET(OPTION_ELSA_W2000PRO, &vga256InfoRec.options); + break; + case ELSA_WINNER_2000PRO_X8: + OFLG_SET(OPTION_ELSA_W2000PRO_X8, &vga256InfoRec.options); + continue; /* use IBM RGB528 clock, don't set ICD2061A flags */ + case ELSA_WINNER_2000: + case ELSA_WINNER_2000VL: + case ELSA_WINNER_2000PCI: + break; /* set ICD2061A clock chip */ + case ELSA_GLORIA_8: + if (OFLG_ISSET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions)) { + FatalError("%s %s: for the ELSA Gloria-8 card you should not " + "specify a clock chip!\n",XCONFIG_GIVEN, vga256InfoRec.name); + } + OFLG_SET(CLOCK_OPTION_GLORIA8, &vga256InfoRec.clockOptions); + OFLG_SET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions); + s3ClockChipProbed = XCONFIG_PROBED; + /* fall through ... */ + + case ELSA_WINNER_2000AVI: + case ELSA_WINNER_2000PRO_X: + case ELSA_GLORIA_4: + if (OFLG_ISSET(OPTION_ELSA_W2000PRO,&vga256InfoRec.options)) { + ErrorF("%s %s: for Ti3026/3030 RAMDACs you must not specify " + "Option \"elsa_w2000pro\"\n",XCONFIG_PROBED, vga256InfoRec.name); + OFLG_CLR(OPTION_ELSA_W2000PRO, &vga256InfoRec.options); + } + if ((card_id==ELSA_WINNER_2000PRO_X) && (hwconf & 2)) { + /* + * this version of the Winner 2000PRO/X has an external ICS9161A + * clockchip, so set ICD2061A flag + */ + if (xf86Verbose) + ErrorF("%s %s: Rev. G Winner 2000PRO/X with external " + "clockchip detected\n",XCONFIG_PROBED, vga256InfoRec.name); + break; + } else { + continue; + } + case ELSA_WINNER_1000PRO_TRIO32: + case ELSA_WINNER_1000PRO_TRIO64: + case ELSA_WINNER_1000PRO_X: + default: + continue; /* unknown card_id, don't set ICD2061A flags */ + } + + /* a known ELSA card_id was returned, set ICD 2061A clock support + if there is no ClockChip specified in XF86Config */ + + if (!OFLG_ISSET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions)) { + OFLG_SET(CLOCK_OPTION_ICD2061A, &vga256InfoRec.clockOptions); + OFLG_SET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions); + s3ClockChipProbed = XCONFIG_PROBED; + } + } while (0); + } + } *** /dev/null Tue Jun 30 15:23:11 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/s3reg.h Fri Mar 6 16:54:15 1998 *************** *** 0 **** --- 1,568 ---- + /* $TOG: s3reg.h /main/1 1998/03/06 16:55:53 kaleb $ */ + + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/s3reg.h,v 1.1.2.1 1998/02/07 10:05:45 hohndel Exp $ */ + /* + * s3reg.h + * + * Written by Jake Richter Copyright (c) 1989, 1990 Panacea Inc., Londonderry, + * NH - All Rights Reserved + * + * This code may be freely incorporated in any program without royalty, as long + * as the copyright notice stays intact. + * + * Additions by Kevin E. Martin (martin@cs.unc.edu) + * + * KEVIN E. MARTIN DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL KEVIN E. MARTIN BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF + * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + * + */ + + /* + * Modified by Amancio Hasty and Jon Tombs + * + * Id: reg8514.h,v 2.2 1993/06/22 20:54:09 jon Exp jon + */ + + /* + * S3 chipset definitions Provided by Jim Nichols <nichols@felix.cmd.usf.edu> + * intended use: if (S3_801_928_SERIES(chip_id)) { <S3 801 and 928 specific + * code here> } Note: The S3 801 and 928 chipsets are very similar. The + * primary difference is that the 801 is DRAM based and the 928 is VRAM + * based. If you add code for the 801, chances are it will also work fine + * with the 928, so please use S3_801_928_SERIES and have someone with a 928 + * test it. The 801 and the 805 appear to be indistinguishable from each + * other using just the chip_id byte. The 805 is the localbus and EISA + * version of the 801. S3_911_SERIES will match both the 911 and 924 (as well + * as any future versions of the 911/924 chips, but not the 801 or 928). + */ + + + #ifndef _S3REG_H + #define _S3REG_H + + #include "compiler.h" + + #define UNLOCK_SYS_REGS do { \ + outb(vgaCRIndex, 0x39); \ + outb(vgaCRReg, 0xa5); } while (0) + + #define LOCK_SYS_REGS /**/ + + + #define S3_911_ONLY(chip) (chip==0x81) + #define S3_924_ONLY(chip) (chip==0x82) + #define S3_911_SERIES(chip) ((chip&0xf0)==0x80) + #define S3_801_SERIES(chip) ((chip&0xf0)==0xa0) + #define S3_805_I_SERIES(chip) ((chip&0xf8)==0xa8) + #define S3_801_REV_C(chip) (S3_801_SERIES(chip) && ((chip) & 0x07) >= 2) + #define S3_928_P(chip) ((chip&0xf0)==0xb0) + #define S3_928_ONLY(chip) ((chip&0xd0)==0x90) + #define S3_928_REV_E(chip) (S3_928_ONLY(chip) && ((chip) & 0x0F) >= 4) + #define S3_801_928_SERIES(chip) (S3_801_SERIES(chip) || S3_928_ONLY(chip) || \ + S3_x64_SERIES(chip)) + #define S3_8XX_9XX_SERIES(chip) (S3_911_SERIES(chip)||S3_801_928_SERIES(chip)) + #define S3_864_SERIES(chip) ((chip&0xf0)==0xc0) + #define S3_964_SERIES(chip) ((chip&0xf0)==0xd0) + + #define S3_866_SERIES(chip) (chip==PCI_868) + #define S3_868_SERIES(chip) (chip==(PCI_868 | 0x10)) + #define S3_86x_SERIES(chip) ((chip&0xf0)==0xc0 || (chip&0xffef)==PCI_868) + #undef S3_864_SERIES + #define S3_864_SERIES(chip) S3_86x_SERIES(chip) + #define S3_968_SERIES(chip) (chip==PCI_968) + #define S3_964_ONLY(chip) S3_964_SERIES(chip) + #undef S3_964_SERIES + #define S3_964_SERIES(chip) (((chip&0xf0)==0xd0) || S3_968_SERIES(chip)) + #define S3_x66_SERIES(chip) S3_866_SERIES(chip) + #define S3_x68_SERIES(chip) ((chip&0xff9f)==0x8890) /* ((S3_868_SERIES(chip) || S3_968_SERIES(chip)) */ + #define S3_x6x_SERIES(chip) ((chip&0xff8f)==0x8880) /* ((S3_x66_SERIES(chip) || S3_x68_SERIES(chip)) */ + #define S3_TRIO32_SERIES(chip) (chip==(PCI_TRIO_32_64 & ~1)) + #define S3_TRIO64_SERIES(chip) (chip==PCI_TRIO_32_64 || S3_TRIO64UVP_SERIES(chip) || S3_AURORA64VP_SERIES(chip) || S3_TRIO64V2_SERIES(chip) || S3_PLATO_PX_SERIES(chip)) + #define S3_TRIO64V_SERIES(chip) (S3_TRIO64_SERIES(chip) && (s3ChipRev & 0x40)) + #define S3_AURORA64VP_SERIES(chip) (chip==PCI_AURORA64VP) + #define S3_TRIO64UVP_SERIES(chip) (chip==PCI_TRIO64UVP) + #define S3_TRIO64V2_SERIES(chip) (chip==PCI_TRIO64V2_DXGX) + #define S3_PLATO_PX_SERIES(chip) (chip==PCI_PLATO_PX) + #define S3_TRIOxx_SERIES(chip) (S3_TRIO32_SERIES(chip) || \ + S3_TRIO64_SERIES(chip)) + #define S3_ViRGE_SERIES(chip) (chip==PCI_ViRGE) + #define S3_ViRGE_VX_SERIES(chip) (chip==PCI_ViRGE_VX) + #define S3_ViRGE_DXGX_SERIES(chip) (chip==PCI_ViRGE_DXGX) + #define S3_ANY_ViRGE_SERIES(chip) ( S3_ViRGE_SERIES(chip) \ + || S3_ViRGE_VX_SERIES(chip) \ + || S3_ViRGE_DXGX_SERIES(chip)) + #define S3_x64_SERIES(chip) (((chip&0xe0)==0xc0) || S3_x6x_SERIES(chip) || S3_TRIOxx_SERIES(chip)) + #define S3_928_SERIES(chip) (S3_928_ONLY(chip) || S3_x64_SERIES(chip)) + #define S3_ANY_SERIES(chip) (S3_8XX_9XX_SERIES(chip) || S3_x64_SERIES(chip) || S3_x66_SERIES(chip) || S3_x68_SERIES(chip)) + + /* PCI data */ + #define PCI_S3_VENDOR_ID 0x5333 + #define PCI_TRIO_32_64 0x8811 + #define PCI_AURORA64VP 0x8812 + #define PCI_TRIO64UVP 0x8814 + #define PCI_TRIO64V2_DXGX 0x8901 + #define PCI_PLATO_PX 0x8902 + #define PCI_928 0x88B0 + #define PCI_864_0 0x88C0 + #define PCI_864_1 0x88C1 + #define PCI_868 0x8880 + #define PCI_964_0 0x88D0 + #define PCI_964_1 0x88D1 + #define PCI_968 0x88F0 + #define PCI_ViRGE 0x5631 + #define PCI_ViRGE_VX 0x883d + #define PCI_ViRGE_DXGX 0x8A01 + + /* Chip tags */ + #define S3_UNKNOWN 0 + #define S3_911 1 + #define S3_924 2 + #define S3_801 3 + #define S3_805 4 + #define S3_928 5 + #define S3_TRIO_32_64 6 + #define S3_864 7 + #define S3_868 8 + #define S3_964 9 + #define S3_968 10 + #define S3_TRIO32 11 + #define S3_TRIO64 12 + #define S3_TRIO64VP 13 + #define S3_TRIO64UVP 14 + #define S3_AURORA64VP 15 + #define S3_TRIO64V2 16 + #define S3_PLATO_PX 17 + #define S3_ViRGE 18 + #define S3_ViRGE_VX 19 + #define S3_ViRGE_DXGX 20 + + /* VESA Approved Register Definitions */ + #define DAC_MASK 0x03c6 + #define DAC_R_INDEX 0x03c7 + #define DAC_W_INDEX 0x03c8 + #define DAC_DATA 0x03c9 + + #define DISP_STAT 0x02e8 + #define H_TOTAL 0x02e8 + #define H_DISP 0x06e8 + #define H_SYNC_STRT 0x0ae8 + #define H_SYNC_WID 0x0ee8 + #define V_TOTAL 0x12e8 + #define V_DISP 0x16e8 + #define V_SYNC_STRT 0x1ae8 + #define V_SYNC_WID 0x1ee8 + #define DISP_CNTL 0x22e8 + #if !defined(PC98_PW) && !defined(PC98_XKB) && !defined(PC98_NEC) + #define ADVFUNC_CNTL 0x4ae8 + #define SUBSYS_STAT 0x42e8 + #define SUBSYS_CNTL 0x42e8 + #define ROM_PAGE_SEL 0x46e8 + #define CUR_Y 0x82e8 + #define CUR_X 0x86e8 + #define CUR_Y2 0x82ea + #define CUR_X2 0x86ea + #define DESTY_AXSTP 0x8ae8 + #define DESTX_DIASTP 0x8ee8 + #define DESTY_AXSTP2 0x8aea + #define DESTX_DIASTP2 0x8eea + #define ERR_TERM 0x92e8 + #define ERR_TERM2 0x92ea + #define MAJ_AXIS_PCNT 0x96e8 + #define MAJ_AXIS_PCNT2 0x96ea + #define GP_STAT 0x9ae8 + #define CMD 0x9ae8 + #define CMD2 0x9aea + #define SHORT_STROKE 0x9ee8 + #define BKGD_COLOR 0xa2e8 + #define FRGD_COLOR 0xa6e8 + #define WRT_MASK 0xaae8 + #define RD_MASK 0xaee8 + #define COLOR_CMP 0xb2e8 + #define BKGD_MIX 0xb6e8 + #define FRGD_MIX 0xbae8 + #define MULTIFUNC_CNTL 0xbee8 + #define PIX_TRANS 0xe2e8 + #define PIX_TRANS_EXT 0xe2ea + #else /* PC98_PW || PC98_XKB || PC98_NEC */ + #ifdef S3_MMIO + #define ADVFUNC_CNTL 0x4a + #define SUBSYS_STAT 0x42 + #define SUBSYS_CNTL 0x42 + #define ROM_PAGE_SEL 0x46 + #define CUR_Y 0x82e8 + #define CUR_X 0x86e8 + #define CUR_Y2 0x82ea + #define CUR_X2 0x86ea + #define DESTY_AXSTP 0x8ae8 + #define DESTX_DIASTP 0x8ee8 + #define DESTY_AXSTP2 0x8aea + #define DESTX_DIASTP2 0x8eea + #define ERR_TERM 0x92e8 + #define ERR_TERM2 0x92ea + #define MAJ_AXIS_PCNT 0x96e8 + #define MAJ_AXIS_PCNT2 0x96ea + #define GP_STAT 0x9a + #define CMD 0x9ae8 + #define CMD2 0x9aea + #define SHORT_STROKE 0x9ee8 + #define BKGD_COLOR 0xa2e8 + #define FRGD_COLOR 0xa6e8 + #define WRT_MASK 0xaae8 + #define RD_MASK 0xaee8 + #define COLOR_CMP 0xb2e8 + #define BKGD_MIX 0xb6e8 + #define FRGD_MIX 0xbae8 + #define MULTIFUNC_CNTL 0xbee8 + #define PIX_TRANS 0xe2e8 + #define PIX_TRANS_EXT 0xe2ea + #else /* regs3>>8 */ + #define ADVFUNC_CNTL 0x4a + #define SUBSYS_STAT 0x42 + #define SUBSYS_CNTL 0x42 + #define ROM_PAGE_SEL 0x46 + #define CUR_Y 0x82 + #define CUR_X 0x86 + #define DESTY_AXSTP 0x8a + #define DESTX_DIASTP 0x8e + #define ERR_TERM 0x92 + #define MAJ_AXIS_PCNT 0x96 + #define GP_STAT 0x9a + #define CMD 0x9a + #define SHORT_STROKE 0x9e + #define BKGD_COLOR 0xa2 + #define FRGD_COLOR 0xa6 + #define WRT_MASK 0xaa + #define RD_MASK 0xae + #define COLOR_CMP 0xb2 + #define BKGD_MIX 0xb6 + #define FRGD_MIX 0xba + #define MULTIFUNC_CNTL 0xbe + #define PIX_TRANS 0xe2 + #define PIX_TRANS_EXT 0xe2 /* (0xe2ea) not used? ignored for PC98 */ + #endif /* S3MMIO */ + #endif /* PC98_PW || PC98_XKB || PC98_NEC */ + #define MIN_AXIS_PCNT 0x0000 + #define SCISSORS_T 0x1000 + #define SCISSORS_L 0x2000 + #define SCISSORS_B 0x3000 + #define SCISSORS_R 0x4000 + #define MEM_CNTL 0x5000 + #define PATTERN_L 0x8000 + #define PATTERN_H 0x9000 + #define PIX_CNTL 0xa000 + #define MULT_MISC2 0xd000 + #define MULT_MISC 0xe000 + #define READ_SEL 0xf000 + + + /* Display Status Bit Fields */ + #define HORTOG 0x0004 + #define VBLANK 0x0002 + #define SENSE 0x0001 + + /* Horizontal Sync Width Bit Field */ + #define HSYNCPOL_NEG 0x0020 + #define HSYNCPOL_POS 0x0000 + + /* Vertical Sync Width Bit Field */ + #define VSYNCPOL_NEG 0x0020 + #define VSYNCPOL_POS 0x0000 + + /* Display Control Bit Field */ + #define DISPEN_NC 0x0000 + #define DISPEN_DISAB 0x0040 + #define DISPEN_ENAB 0x0020 + #define INTERLACE 0x0010 + #define DBLSCAN 0x0008 + #define MEMCFG_2 0x0000 + #define MEMCFG_4 0x0002 + #define MEMCFG_6 0x0004 + #define MEMCFG_8 0x0006 + #define ODDBNKENAB 0x0001 + + /* Subsystem Status Register */ + #define _8PLANE 0x0080 + #define MONITORID_8503 0x0050 + #define MONITORID_8507 0x0010 + #define MONITORID_8512 0x0060 + #define MONITORID_8513 0x0060 + #define MONITORID_8514 0x0020 + #define MONITORID_NONE 0x0070 + #define MONITORID_MASK 0x0070 + #define GPIDLE 0x0008 + #define INVALIDIO 0x0004 + #define PICKFLAG 0x0002 + #define VBLNKFLG 0x0001 + + /* Subsystem Control Register */ + #define GPCTRL_NC 0x0000 + #define GPCTRL_ENAB 0x4000 + #define GPCTRL_RESET 0x8000 + #define CHPTEST_NC 0x0000 + #define CHPTEST_NORMAL 0x1000 + #define CHPTEST_ENAB 0x2000 + #define IGPIDLE 0x0800 + #define IINVALIDIO 0x0400 + #define IPICKFLAG 0x0200 + #define IVBLNKFLG 0x0100 + #define RGPIDLE 0x0008 + #define RINVALIDIO 0x0004 + #define RPICKFLAG 0x0002 + #define RVBLNKFLG 0x0001 + + /* Current X, Y & Dest X, Y Mask */ + #define COORD_MASK 0x07ff + + #ifdef CLKSEL + #undef CLKSEL + #endif + + /* Advanced Function Control Regsiter */ + #define CLKSEL 0x0004 + #define DISABPASSTHRU 0x0001 + + /* Graphics Processor Status Register */ + #define GPBUSY 0x0200 + #define DATDRDY 0x0100 + + /* Command Register */ + #define CMD_NOP 0x0000 + #define CMD_LINE 0x2000 + #define CMD_RECT 0x4000 + #define CMD_RECTV1 0x6000 + #define CMD_RECTV2 0x8000 + #define CMD_LINEAF 0xa000 + #define CMD_BITBLT 0xc000 + #define CMD_PFILL 0xe000 + #define CMD_OP_MSK 0xf000 + #define BYTSEQ 0x1000 + #define _16BIT 0x0200 + #define _32BIT 0x0400 + #define PCDATA 0x0100 + #define INC_Y 0x0080 + #define YMAJAXIS 0x0040 + #define INC_X 0x0020 + #define DRAW 0x0010 + #define LINETYPE 0x0008 + #define LASTPIX 0x0004 + #define PLANAR 0x0002 + #define WRTDATA 0x0001 + + /* + * Short Stroke Vector Transfer Register (The angular Defs also apply to the + * Command Register + */ + #define VECDIR_000 0x0000 + #define VECDIR_045 0x0020 + #define VECDIR_090 0x0040 + #define VECDIR_135 0x0060 + #define VECDIR_180 0x0080 + #define VECDIR_225 0x00a0 + #define VECDIR_270 0x00c0 + #define VECDIR_315 0x00e0 + #define SSVDRAW 0x0010 + + /* Background Mix Register */ + #define BSS_BKGDCOL 0x0000 + #define BSS_FRGDCOL 0x0020 + #define BSS_PCDATA 0x0040 + #define BSS_BITBLT 0x0060 + + /* Foreground Mix Register */ + #define FSS_BKGDCOL 0x0000 + #define FSS_FRGDCOL 0x0020 + #define FSS_PCDATA 0x0040 + #define FSS_BITBLT 0x0060 + + /* The Mixes */ + #define MIX_MASK 0x001f + + #define MIX_NOT_DST 0x0000 + #define MIX_0 0x0001 + #define MIX_1 0x0002 + #define MIX_DST 0x0003 + #define MIX_NOT_SRC 0x0004 + #define MIX_XOR 0x0005 + #define MIX_XNOR 0x0006 + #define MIX_SRC 0x0007 + #define MIX_NAND 0x0008 + #define MIX_NOT_SRC_OR_DST 0x0009 + #define MIX_SRC_OR_NOT_DST 0x000a + #define MIX_OR 0x000b + #define MIX_AND 0x000c + #define MIX_SRC_AND_NOT_DST 0x000d + #define MIX_NOT_SRC_AND_DST 0x000e + #define MIX_NOR 0x000f + + #define MIX_MIN 0x0010 + #define MIX_DST_MINUS_SRC 0x0011 + #define MIX_SRC_MINUS_DST 0x0012 + #define MIX_PLUS 0x0013 + #define MIX_MAX 0x0014 + #define MIX_HALF__DST_MINUS_SRC 0x0015 + #define MIX_HALF__SRC_MINUS_DST 0x0016 + #define MIX_AVERAGE 0x0017 + #define MIX_DST_MINUS_SRC_SAT 0x0018 + #define MIX_SRC_MINUS_DST_SAT 0x001a + #define MIX_HALF__DST_MINUS_SRC_SAT 0x001c + #define MIX_HALF__SRC_MINUS_DST_SAT 0x001e + #define MIX_AVERAGE_SAT 0x001f + + /* Memory Control Register */ + #define BUFSWP 0x0010 + #define VRTCFG_2 0x0000 + #define VRTCFG_4 0x0004 + #define VRTCFG_6 0x0008 + #define VRTCFG_8 0x000C + #define HORCFG_4 0x0000 + #define HORCFG_5 0x0001 + #define HORCFG_8 0x0002 + #define HORCFG_10 0x0003 + + /* Pixel Control Register */ + #define MIXSEL_FRGDMIX 0x0000 + #define MIXSEL_PATT 0x0040 + #define MIXSEL_EXPPC 0x0080 + #define MIXSEL_EXPBLT 0x00c0 + #define COLCMPOP_F 0x0000 + #define COLCMPOP_T 0x0008 + #define COLCMPOP_GE 0x0010 + #define COLCMPOP_LT 0x0018 + #define COLCMPOP_NE 0x0020 + #define COLCMPOP_EQ 0x0028 + #define COLCMPOP_LE 0x0030 + #define COLCMPOP_GT 0x0038 + #define PLANEMODE 0x0004 + + typedef struct { + unsigned char r, g, b; + } LUTENTRY; + + + #define WaitIdle() do { \ + mem_barrier(); \ + while(inw(GP_STAT) & GPBUSY); \ + } while(0) + + + #define BLOCK_CURSOR s3BlockCursor = TRUE; + #define UNBLOCK_CURSOR { \ + mem_barrier(); \ + if (s3ReloadCursor) \ + S3RestoreCursor(s3savepScreen); \ + s3BlockCursor = FALSE; \ + } + + /* base for S3_OUTW macro */ + #define S3_NEWMMIO_REGBASE 0x1000000 /* 16MB */ + #define S3_NEWMMIO_REGSIZE 0x10000 /* 64KB */ + + + #ifdef S3_NEWMMIO + #include "newmmio.h" + #else + #define WaitQueue(v) do { \ + mem_barrier(); \ + while(inb(GP_STAT) & (0x0100 >> (v))); \ + } while (0) + + #define CMD_REG_WIDTH 0 /* select 16bit command register */ + + #define WaitQueue16_32(n16,n32) \ + if(s3Bpp <= 2) { WaitQueue(n16); } \ + else { WaitQueue(n32); } + + #define S3_OUTW(p,n) outw(p,n) + #define S3_OUTL(p,n) outl(p,n) + + #define S3_OUTW32(p,n) if(s3Bpp > 2) { \ + outw(p,n); \ + outw(p,(n) >> 16); \ + } else outw(p,n) + + #define SET_FRGD_MIX(fmix) S3_OUTW(FRGD_MIX, (fmix)) + #define SET_BKGD_MIX(bmix) S3_OUTW(BKGD_MIX, (bmix)) + + #define SET_PIX_CNTL(val) S3_OUTW(MULTIFUNC_CNTL, PIX_CNTL| (val)) + + #define SET_WRT_MASK(msk) S3_OUTW32(WRT_MASK,msk) + #define SET_RD_MASK(msk) S3_OUTW32(RD_MASK,msk) + + #define SET_FRGD_COLOR(col) S3_OUTW32(FRGD_COLOR, col) + #define SET_BKGD_COLOR(col) S3_OUTW32(BKGD_COLOR, col) + + #define SET_COLOR_CMP(col) S3_OUTW32(COLOR_CMP, col) + + #define SET_CUR_X(cur_x) S3_OUTW(CUR_X, cur_x) + #define SET_CUR_Y(cur_y) S3_OUTW(CUR_Y, cur_y) + #define SET_CUR_X2(cur_x) S3_OUTW(CUR_X2, cur_x) + #define SET_CUR_Y2(cur_y) S3_OUTW(CUR_Y2, cur_y) + #define SET_CURPT(cur_x, cur_y) { \ + SET_CUR_X(cur_x); \ + SET_CUR_Y(cur_y); \ + } + #define SET_CURPT2(cur_x, cur_y) { \ + SET_CUR_X2(cur_x); \ + SET_CUR_Y2(cur_y); \ + } + #define SET_DESTSTP(x,y) { \ + S3_OUTW(DESTX_DIASTP, x); \ + S3_OUTW(DESTY_AXSTP, y); \ + } + #define SET_DESTSTP2(x,y) { \ + S3_OUTW(DESTX_DIASTP2, x); \ + S3_OUTW(DESTY_AXSTP2, y); \ + } + #define SET_AXIS_PCNT(maj, min) { \ + S3_OUTW(MAJ_AXIS_PCNT, maj); \ + S3_OUTW(MULTIFUNC_CNTL, MIN_AXIS_PCNT | (min)); \ + } + #define SET_MAJ_AXIS_PCNT(maj) S3_OUTW(MAJ_AXIS_PCNT, maj) + #define SET_MAJ_AXIS_PCNT2(maj) S3_OUTW(MAJ_AXIS_PCNT2, maj) + #define SET_MIN_AXIS_PCNT(min) S3_OUTW(MULTIFUNC_CNTL,MIN_AXIS_PCNT | (min)) + + #define SET_CMD(cmd) S3_OUTW(CMD, cmd) + #define SET_CMD2(cmd) S3_OUTW(CMD2, cmd) + + #define SET_SCISSORS_RB(x,y) { \ + S3_OUTW(MULTIFUNC_CNTL, SCISSORS_R | (x)); \ + S3_OUTW(MULTIFUNC_CNTL, SCISSORS_B | (y)); \ + } + #define SET_MULT_MISC(val) S3_OUTW(MULTIFUNC_CNTL, MULT_MISC | (val)) + #define SET_SCISSORS(x1,y1,x2,y2) { \ + S3_OUTW(MULTIFUNC_CNTL, SCISSORS_T | (y1)); \ + S3_OUTW(MULTIFUNC_CNTL, SCISSORS_L | (x1)); \ + S3_OUTW(MULTIFUNC_CNTL, SCISSORS_R | (x2)); \ + S3_OUTW(MULTIFUNC_CNTL, SCISSORS_B | (y2)); \ + } + + #define SET_ERR_TERM(err) S3_OUTW(ERR_TERM, err) + #define SET_ERR_TERM2(err) S3_OUTW(ERR_TERM2, err) + + #define INB_GP_STAT() inb(GP_STAT) + #define INW_GP_STAT() inw(GP_STAT) + + #define SET_PIX_TRANS_L(val) outl(PIX_TRANS, val) + #define SET_MIX(fmix,bmix) { \ + SET_FRGD_MIX(fmix); \ + SET_BKGD_MIX(bmix); \ + } + + #endif + + #define SET_PIX_TRANS_W(val) outw(PIX_TRANS, val) + + #define SET_DAC_W_INDEX(index) outb(DAC_W_INDEX, index) + #define SET_DAC_DATA(val) outb(DAC_DATA,val) + + + + #endif /* _S3REG_H */ *** /dev/null Tue Jun 30 15:23:12 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/s3save.c Fri Mar 6 16:54:19 1998 *************** *** 0 **** --- 1,142 ---- + /* $TOG: s3save.c /main/1 1998/03/06 16:55:57 kaleb $ */ + + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/s3save.c,v 1.1.2.1 1998/02/07 10:05:45 hohndel Exp $ */ + /* + * + * Copyright 1995-1997 The XFree86 Project, Inc. + * + */ + #include "X.h" + #include "input.h" + #include "screenint.h" + + #include "compiler.h" + #include "xf86.h" + #include "xf86Priv.h" + #include "xf86_OSlib.h" + #include "xf86_HWlib.h" + #include "xf86_PCI.h" + #include "vga.h" + #include "vgaPCI.h" + + #ifdef XFreeXDGA + #include "X.h" + #include "Xproto.h" + #include "scrnintstr.h" + #include "servermd.h" + #define _XF86DGA_SERVER_ + #include "extensions/xf86dgastr.h" + #endif + + #define XCONFIG_FLAGS_ONLY + #include "xf86_Config.h" + + #include "s3reg.h" + #include "s3.h" + + #define REG50_MASK 0x673b + + /* + * S3Save -- + * + * Save the current video mode. + * + */ + + void* S3Save(vgaS3Ptr save) + { + int i; + unsigned char CR5C; + + + #ifdef S3_DEBUG + ErrorF("In S3Save()\n"); + #endif + + S3BankZero(); + + i = inb(0x3CC); + + /* save generic vga regs */ + save = vgaHWSave((vgaHWPtr)save, sizeof(vgaS3Rec)); + + save->Clock = i; /* ? MArk */ + + /* now we need to save the special registers */ + + /* save a good copy now as it gets corrupted later */ + if (DAC_IS_TI3025) { + outb(vgaCRIndex, 0x5C); + CR5C = inb(vgaCRReg); + } + + + /* Save Ramdac registers */ + (s3Ramdacs[s3RamdacType].DacSave)(save); + + + for (i = 0; i < 5; i++) { + outb(vgaCRIndex, 0x30 + i); + save->s3reg[i] = inb(vgaCRReg); + outb(vgaCRIndex, 0x38 + i); + save->s3reg[5 + i] = inb(vgaCRReg); + } + + for (i = 0; i < 16; i++) { + outb(vgaCRIndex, 0x40 + i); + save->s3sysreg[i] = inb(vgaCRReg); + } + + outb(vgaCRIndex, 0x45); + inb(vgaCRReg); /* reset color stack pointer */ + outb(vgaCRIndex, 0x4A); + for (i = 0; i < 4; i++) { + save->ColorStack[i] = inb(vgaCRReg); + outb(vgaCRReg,save->ColorStack[i]); /* advance stack pointer */ + } + + outb(vgaCRIndex, 0x45); + inb(vgaCRReg); /* reset color stack pointer */ + outb(vgaCRIndex, 0x4B); + for (i = 4; i < 8; i++) { + save->ColorStack[i] = inb(vgaCRReg); + outb(vgaCRReg,save->ColorStack[i]); /* advance stack pointer */ + } + + if (S3_801_928_SERIES(s3ChipId)) { + for (i = 0; i < 16; i++) { + if (!((1 << i) & REG50_MASK)) + continue; + outb(vgaCRIndex, 0x50 + i); + save->s3sysreg[i + 16] = inb(vgaCRReg); + } + } + + if (DAC_IS_TI3025) /* restore 5C from above */ + save->s3sysreg[0x0C + 16] = CR5C; + + for (i = 32; i < (S3_x64_SERIES(s3ChipId) ? 46 : + S3_805_I_SERIES(s3ChipId) ? 40 : 38); i++) { + outb(vgaCRIndex, 0x40 + i); + save->s3sysreg[i] = inb(vgaCRReg); + } + + return ((void *) save); + } + + /* + * S3Restore -- + * + * Restore the given mode + * + */ + + void S3Restore(vgaS3Ptr restore) + { + #ifdef S3_DEBUG + ErrorF("In S3Restore()\n"); + #endif + } *** /dev/null Tue Jun 30 15:23:13 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/s3TiCursor.c Fri Mar 6 16:53:19 1998 *************** *** 0 **** --- 1,312 ---- + /* $TOG: s3TiCursor.c /main/1 1998/03/06 16:54:57 kaleb $ */ + + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/s3TiCursor.c,v 1.1.2.1 1998/02/07 10:05:37 hohndel Exp $ */ + /* + * Copyright 1994 by Robin Cutshaw <robin@XFree86.org> + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Robin Cutshaw not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Robin Cutshaw makes no representations + * about the suitability of this software for any purpose. It is provided + * "as is" without express or implied warranty. + * + * ROBIN CUTSHAW DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL ROBIN CUTSHAW BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + * + */ + + #define NEED_EVENTS + #include <X.h> + #include "Xproto.h" + #include <misc.h> + #include <input.h> + #include <cursorstr.h> + #include <regionstr.h> + #include <scrnintstr.h> + #include <servermd.h> + #include <windowstr.h> + #include "xf86.h" + #include "inputstr.h" + #include "xf86Priv.h" + #include "xf86_OSlib.h" + #include "s3.h" + #include "s3reg.h" + #define S3_SERVER + #include "Ti302X.h" + #include "mipointer.h" + + + /* + * TI ViewPoint 3020/3025 support - Robin Cutshaw + * + * The Ti3020 has 8 direct command registers and indirect registers + * 0x00-0x3F and 0xFF. The low-order two bits of the direct register + * address follow normal VGA DAC addressing conventions (which + * for some reason aren't in numeric order, so we remap them through + * an array). The S3 provides access to the high-order bit via + * the low-order bit of CR55. The indirect registers are accessed + * through the direct index and data registers. See s3Ti3020.h for + * details. + * + * The Ti3025 is both Ti3020 and Bt485 compatable. The mode of + * operation is set via RS4 using S3 register 0x5C and the 3020 + * cursor control register. The 3025 also has a built in PLL + * clock generator. + */ + + static Bool s3In3020mode = FALSE; /* starts in Bt485 mode */ + + void s3set3020mode() + { + unsigned char tmp, tmp1, tmp2; + + outb(vgaCRIndex, 0x5C); + tmp = inb(vgaCRReg); + outb(vgaCRReg, tmp & 0xDF); /* clear RS4 - use 3020 mode */ + + outb(vgaCRIndex, 0x55); + tmp = inb(vgaCRReg) & 0xFC; + outb(vgaCRReg, tmp | 0x01); /* toggle to upper 4 direct registers */ + tmp1 = inb(TI_INDEX_REG); + outb(TI_INDEX_REG, TI_CURS_CONTROL); + tmp2 = inb(TI_DATA_REG); + outb(TI_DATA_REG, tmp2 & 0x7F); /* clear TI_PLANAR_ACCESS bit */ + + outb(TI_INDEX_REG, tmp1); + outb(vgaCRIndex, 0x55); + outb(vgaCRReg, tmp); + s3In3020mode = TRUE; + } + + void s3set485mode() + { + unsigned char tmp, tmp1; + + outb(vgaCRIndex, 0x5C); + tmp = inb(vgaCRReg); + outb(vgaCRReg, tmp & 0xDF); /* clear RS4 - use 3020 mode */ + + outb(vgaCRIndex, 0x55); + tmp = inb(vgaCRReg) & 0xFC; + outb(vgaCRReg, tmp | 0x01); /* toggle to upper 4 direct registers */ + outb(TI_INDEX_REG, TI_CURS_CONTROL); + tmp1 = inb(TI_DATA_REG); + outb(TI_DATA_REG, tmp1 | 0x80); /* set TI_PLANAR_ACCESS bit */ + + outb(vgaCRIndex, 0x5C); + outb(vgaCRReg, tmp | 0x20); /* set RS4 - use 485 mode */ + + outb(vgaCRIndex, 0x55); + outb(vgaCRReg, tmp); + s3In3020mode = FALSE; + } + + /* + * s3OutTiIndReg() and s3InTiIndReg() are used to access the indirect + * 3020 registers only. + */ + + #ifdef __STDC__ + void s3OutTiIndReg(unsigned char reg, unsigned char mask, unsigned char data) + #else + void s3OutTiIndReg(reg, mask, data) + unsigned char reg; + unsigned char mask; + unsigned char data; + #endif + { + unsigned char tmp, tmp1, tmp2 = 0x00; + + /* High 2 bits of reg in CR55 bits 0-1 (1 is cleared for the TI ramdac) */ + outb(vgaCRIndex, 0x55); + tmp = inb(vgaCRReg) & 0xFC; + outb(vgaCRReg, tmp | 0x01); /* toggle to upper 4 direct registers */ + tmp1 = inb(TI_INDEX_REG); + outb(TI_INDEX_REG, reg); + + /* Have to map the low two bits to the correct DAC register */ + if (mask != 0x00) + tmp2 = inb(TI_DATA_REG) & mask; + outb(TI_DATA_REG, tmp2 | data); + + /* Now clear 2 high-order bits so that other things work */ + outb(TI_INDEX_REG, tmp1); /* just in case anyone relies on this */ + outb(vgaCRReg, tmp); + } + + #ifdef __STDC__ + unsigned char s3InTiIndReg(unsigned char reg) + #else + unsigned char s3InTiIndReg(reg) + unsigned char reg; + #endif + { + unsigned char tmp, tmp1, ret; + + /* High 2 bits of reg in CR55 bits 0-1 (1 is cleared for the TI ramdac) */ + outb(vgaCRIndex, 0x55); + tmp = inb(vgaCRReg) & 0xFC; + outb(vgaCRReg, tmp | 0x01); /* toggle to upper 4 direct registers */ + tmp1 = inb(TI_INDEX_REG); + outb(TI_INDEX_REG, reg); + + /* Have to map the low two bits to the correct DAC register */ + ret = inb(TI_DATA_REG); + + /* Now clear 2 high-order bits so that other things work */ + outb(TI_INDEX_REG, tmp1); /* just in case anyone relies on this */ + outb(vgaCRReg, tmp); + + return(ret); + } + + /* + * Convert the cursor from server-format to hardware-format. The Ti3020 + * has two planes, plane 0 selects cursor color 0 or 1 and plane 1 + * selects transparent or display cursor. The bits of these planes + * are packed together so that one byte has 4 pixels. The organization + * looks like: + * Byte 0x000 - 0x00F top scan line, left to right + * 0x010 - 0x01F + * . . + * 0x3F0 - 0x3FF bottom scan line + * + * Byte/bit map - D7D6,D5D4,D3D2,D1D0 four pixels, two planes each + * Pixel/bit map - P1P0 (plane 1) == 1 maps to cursor color + * (plane 1) == 0 maps to transparent + * (plane 0) maps to cursor colors 0 and 1 + */ + + + void + s3TiShowCursor() + { + unsigned char tmp; + + UNLOCK_SYS_REGS; + + /* turn on external cursor */ + outb(vgaCRIndex, 0x55); + tmp = inb(vgaCRReg) & 0xDF; + outb(vgaCRReg, tmp | 0x20); + + /* Enable Ti3020 */ + outb(vgaCRIndex, 0x45); + tmp = inb(vgaCRReg) & 0xDF; + outb(vgaCRReg, tmp | 0x20); + + /* Enable cursor - sprite enable, X11 mode */ + s3OutTiIndReg(TI_CURS_CONTROL, + (unsigned char )~TI_CURS_CTRL_MASK, + TI_CURS_SPRITE_ENABLE | TI_CURS_X_WINDOW_MODE); + + LOCK_SYS_REGS; + } + + void + s3TiHideCursor() + { + UNLOCK_SYS_REGS; + + /* + * Don't need to undo the S3 registers here; they will be undone when + * the mode is restored from save registers. If it is done here, it + * causes the cursor to flash each time it is loaded, so don't do that. + */ + + /* Disable cursor */ + s3OutTiIndReg(TI_CURS_CONTROL, + (unsigned char )~TI_CURS_CTRL_MASK, 0x00); + + LOCK_SYS_REGS; + } + + void + s3TiSetCursorPosition(x, y, xorigin, yorigin) + int x, y, xorigin, yorigin; + { + UNLOCK_SYS_REGS; + + outb(TI_INDEX_REG, TI_SPRITE_ORIGIN_X); /* offset into cursor data */ + outb(TI_DATA_REG, xorigin); + outb(TI_INDEX_REG, TI_SPRITE_ORIGIN_Y); + outb(TI_DATA_REG, yorigin); + + s3OutTiIndReg(TI_CURS_X_LOW, 0x00, x & 0xFF); + s3OutTiIndReg(TI_CURS_X_HIGH, 0x00, (x >> 8) & 0x0F); + s3OutTiIndReg(TI_CURS_Y_LOW, 0x00, y & 0xFF); + s3OutTiIndReg(TI_CURS_Y_HIGH, 0x00, (y >> 8) & 0x0F); + + LOCK_SYS_REGS; + } + + void + s3TiSetCursorColors(bg, fg) + int bg, fg; + { + UNLOCK_SYS_REGS; + + /* The TI 3020 cursor is always 8 bits so shift 8, not 10 */ + + /* Background color */ + s3OutTiIndReg(TI_CURSOR_COLOR_0_RED, 0, (bg & 0x00FF0000) >> 16); + s3OutTiIndReg(TI_CURSOR_COLOR_0_GREEN, 0, (bg & 0x0000FF00) >> 8); + s3OutTiIndReg(TI_CURSOR_COLOR_0_BLUE, 0, (bg & 0x000000FF)); + + /* Foreground color */ + s3OutTiIndReg(TI_CURSOR_COLOR_1_RED, 0, (fg & 0x00FF0000) >> 16); + s3OutTiIndReg(TI_CURSOR_COLOR_1_GREEN, 0, (fg & 0x0000FF00) >> 8); + s3OutTiIndReg(TI_CURSOR_COLOR_1_BLUE, 0, (fg & 0x000000FF)); + + LOCK_SYS_REGS; + } + + void + s3TiLoadCursorImage(bits, xorigin, yorigin) + unsigned char *bits; + int xorigin, yorigin; + { + register int i; + unsigned char tmp, tmp1; + register unsigned char *mask = bits + 1; + + UNLOCK_SYS_REGS; + + /* The hardware cursor is not supported in interlaced mode */ + + /* High 2 bits of reg in CR55 bits 0-1 (1 is cleared for the TI ramdac) */ + outb(vgaCRIndex, 0x55); + tmp = inb(vgaCRReg) & 0xFC; + outb(vgaCRReg, tmp | 0x01); /* toggle to the high four direct registers */ + tmp1 = inb(TI_INDEX_REG); + + outb(TI_INDEX_REG, TI_CURS_RAM_ADDR_LOW); /* must be first */ + outb(TI_DATA_REG, 0x00); + outb(TI_INDEX_REG, TI_CURS_RAM_ADDR_HIGH); + outb(TI_DATA_REG, 0x00); + outb(TI_INDEX_REG, TI_CURS_RAM_DATA); + + for (i = 0; i < 512; i++, mask+=2) + outb(TI_DATA_REG, *mask); + for (i = 0; i < 512; i++, bits+=2) + outb(TI_DATA_REG, *bits); + + outb(TI_INDEX_REG, tmp1); + + outb(vgaCRIndex, 0x55); + outb(vgaCRReg, tmp); + + LOCK_SYS_REGS; + } *** /dev/null Tue Jun 30 15:23:14 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/s3.h Fri Mar 6 16:52:59 1998 *************** *** 0 **** --- 1,225 ---- + /* $TOG: s3.h /main/1 1998/03/06 16:54:37 kaleb $ */ + + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/s3.h,v 1.1.2.1 1998/02/07 10:05:31 hohndel Exp $ */ + /* + * + * Copyright 1995-1997 The XFree86 Project, Inc. + * + */ + #ifndef _S3_H_ + #define _S3_H_ + + #include "compiler.h" + #include "xf86.h" + #include "xf86Priv.h" + #include "xf86_OSlib.h" + #include "xf86_HWlib.h" + #include "xf86_PCI.h" + #include "vga.h" + #include "vgaPCI.h" + + /* s3InfoRec needs to be defined as the directory everything is in. */ + + #define s3InfoRec S3_SVGA + + /* uncomment S3_DEBUG to get a comfortable level of debugging info (MArk) */ + /* #define S3_DEBUG */ + + #include "s3reg.h" + + /* Structure definitions */ + + typedef struct { + vgaHWRec std; /* good old IBM VGA */ + unsigned char Clock; /* Do I need this here? (MArk) */ + unsigned char s3DacRegs[0x101]; + unsigned char s3reg[10]; /* Video Atribute (CR30-34, CR38-3C) */ + unsigned char s3sysreg[46]; /* Video Atribute (CR40-6D)*/ + unsigned char ColorStack[8]; /* S3 hw cursor color stack CR4A/CR4B */ + } + vgaS3Rec, *vgaS3Ptr; + + typedef struct { + char *DacName; + int DacSpeeds[MAXDACSPEEDS]; + Bool (*DacProbe)(); + int (*PreInit)(); + void (*DacRestore)(vgaS3Ptr); + void (*DacSave)(vgaS3Ptr); + int (*DacInit)(DisplayModePtr); + } s3RamdacInfo; + + + /* Global variable declarations */ + + extern int s3maxRawClock; + extern int s3BppDisplayWidth; + extern int s3CursorBytes; + extern int s3MaxClock; + extern int s3maxDisplayWidth; + extern int s3maxDisplayHeight; + extern int s3numClocks; + extern int s3ScissB; + extern int s3ScissR; + extern int s3BankSize; + extern int s3HDisplay; + extern int s3DisplayWidth; + extern unsigned short s3ChipRev; + extern unsigned short s3ChipId; + extern short s3BiosVendor; + extern short s3RamdacType; + extern short s3Weight; + extern short s3Bpp; + extern short s3alu[16]; + extern char s3Mbanks; + extern char *s3ClockChipProbed; + extern Bool s3Localbus; + extern Bool s3PCIRetry; + extern Bool s3VLB; + extern Bool s3DAC8Bit; + extern Bool s3DACSyncOnGreen; + extern Bool s3PixelMultiplexing; + extern Bool s3Bt485PixMux; + extern Bool s3ATT498PixMux; + extern Bool s3PowerSaver; + extern Bool s3clockDoublingPossible; + extern Bool s3Initialized; + extern Bool s3newmmio; + extern unsigned char s3Port31; + extern unsigned char s3Port51; + extern unsigned char s3Port59; + extern unsigned char s3Port5A; + extern unsigned char s3LinApOpt; + extern unsigned char s3SAM256; + extern unsigned char s3DACBoarder; + extern unsigned char s3SwapBits[256]; + extern ScreenPtr s3savepScreen; + extern DisplayModePtr s3CurrentMode; + + extern pointer s3MmioMem; + + extern int vgaCRIndex; + extern int vgaCRReg; + + extern Bool (*s3ClockSelectFunc)(); + + extern int S3ValidMode(DisplayModePtr, Bool, int); + extern int S3GetWidth(int); + extern char* S3Ident(int); + extern void* S3Save(vgaS3Ptr); + extern void S3Restore(vgaS3Ptr); + extern void S3RetraceWait(void); + extern void S3BankZero(void); + extern void S3Unlock(void); + extern void S3FbInit(); + extern void S3SetRead(); + extern void S3CleanUp(void); + extern void S3FillInModeInfo(DisplayModePtr); + extern void S3EnterLeave(Bool); + extern void S3Adjust(int,int); + extern void S3AccelInit(void); + extern void S3AccelInit_NewMMIO(void); + extern Bool S3InitLevelOne(DisplayModePtr); + extern Bool S3InitLevelTwo(DisplayModePtr); + extern Bool S3Probe(void); + extern Bool S3InitLevelThree(DisplayModePtr); + extern Bool S3Init(DisplayModePtr); + extern void S3CursorInit(); + extern unsigned char S3MuxOrNot(DisplayModePtr); + extern void S3SavePalette(LUTENTRY*); + extern void S3RestorePalette(LUTENTRY*); + + extern void (* dacOutTi3026IndReg)(unsigned char,unsigned char,unsigned char); + extern unsigned char (* dacInTi3026IndReg)(unsigned char); + extern void s3OutTi3026IndReg(unsigned char, unsigned char, unsigned char); + extern unsigned char s3InTi3026IndReg(unsigned char); + extern void s3OutTiIndReg(unsigned char, unsigned char, unsigned char); + extern unsigned char s3InTiIndReg(unsigned char); + + + + extern vgaVideoChipRec s3InfoRec; + extern s3RamdacInfo s3Ramdacs[]; + + /* DAC Numbers */ + + #define UNKNOWN_DAC -1 + #define NORMAL_DAC 0 + #define S3_TRIO32_DAC 1 + #define S3_TRIO64_DAC 2 + #define TI3026_DAC 3 + #define TI3030_DAC 4 + #define TI3020_DAC 5 + #define TI3025_DAC 6 + #define BT485_DAC 7 + #define ATT20C505_DAC 8 + #define ATT22C498_DAC 9 + #define ATT498_DAC 10 + #define ATT20C498_DAC ATT498_DAC + #define ATT20C409_DAC 11 + #define SC15025_DAC 12 + #define STG1700_DAC 13 + #define STG1703_DAC 14 + #define IBMRGB524_DAC 15 + #define IBMRGB525_DAC 16 + #define IBMRGB528_DAC 17 + #define S3_SDAC_DAC 18 + #define S3_GENDAC_DAC 19 + #define ATT20C490_DAC 20 + #define SS2410_DAC 21 + #define SC1148x_DAC 22 + #define S3_TRIO64V2_DAC 23 + + /* DAC Macros */ + + #define DAC_IS_BT485_SERIES (s3RamdacType == BT485_DAC || \ + s3RamdacType == ATT20C505_DAC) + #define DAC_IS_TI3020_SERIES (s3RamdacType == TI3020_DAC || \ + s3RamdacType == TI3025_DAC) + #define DAC_IS_TI3020 (s3RamdacType == TI3020_DAC) + #define DAC_IS_TI3025 (s3RamdacType == TI3025_DAC) + #define DAC_IS_TI3026 (s3RamdacType == TI3026_DAC) + #define DAC_IS_TI3030 (s3RamdacType == TI3030_DAC) + #define DAC_IS_ATT20C498 (s3RamdacType == ATT20C498_DAC) + #define DAC_IS_ATT22C498 (s3RamdacType == ATT22C498_DAC) + #define DAC_IS_ATT498 (DAC_IS_ATT20C498 || DAC_IS_ATT22C498) + #define DAC_IS_ATT490 (s3RamdacType == ATT20C490_DAC) + #define DAC_IS_SC15025 (s3RamdacType == SC15025_DAC) + #define DAC_IS_STG1703 (s3RamdacType == STG1703_DAC) + #define DAC_IS_STG1700 (s3RamdacType == STG1700_DAC || DAC_IS_STG1703) + #define DAC_IS_SDAC (s3RamdacType == S3_SDAC_DAC) + #define DAC_IS_GENDAC (s3RamdacType == S3_GENDAC_DAC) + #define DAC_IS_TRIO32 (s3RamdacType == S3_TRIO32_DAC) + #define DAC_IS_TRIO64 (s3RamdacType == S3_TRIO64_DAC) + #define DAC_IS_TRIO64V2 (s3RamdacType == S3_TRIO64V2_DAC) + #define DAC_IS_TRIO (DAC_IS_TRIO32 || DAC_IS_TRIO64 || DAC_IS_TRIO64V2) + #define DAC_IS_IBMRGB524 (s3RamdacType == IBMRGB524_DAC) + #define DAC_IS_IBMRGB525 (s3RamdacType == IBMRGB525_DAC) + #define DAC_IS_IBMRGB528 (s3RamdacType == IBMRGB528_DAC) + #define DAC_IS_IBMRGB (DAC_IS_IBMRGB524 || DAC_IS_IBMRGB525 || \ + DAC_IS_IBMRGB528) + #define DAC_IS_SC1148x (s3RamdacType == SC1148x_DAC) + #define DAC_IS_ATT20C409 (s3RamdacType == ATT20C409_DAC) + #define DAC_IS_SS2410 (s3RamdacType == SS2410_DAC ) + + /* Vendor BIOS types */ + + #define UNKNOWN_BIOS -1 + #define ELSA_BIOS 1 + #define MIRO_BIOS 2 + #define SPEA_BIOS 3 + #define GENOA_BIOS 4 + #define STB_BIOS 5 + #define NUMBER_NINE_BIOS 6 + #define HERCULES_BIOS 7 + #define DIAMOND_BIOS 8 + + #define MUSTMUX 1 + #define CANTMUX 2 + + + + #endif /* _S3_H_ */ *** /dev/null Tue Jun 30 15:23:15 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/Ti3026Curs.c Fri Mar 6 16:52:51 1998 *************** *** 0 **** --- 1,279 ---- + /* $TOG: Ti3026Curs.c /main/1 1998/03/06 16:54:29 kaleb $ */ + + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/Ti3026Curs.c,v 1.1.2.1 1998/02/07 10:05:30 hohndel Exp $ */ + /* + * Copyright 1994 by Robin Cutshaw <robin@XFree86.org> + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Robin Cutshaw not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Robin Cutshaw makes no representations + * about the suitability of this software for any purpose. It is provided + * "as is" without express or implied warranty. + * + * ROBIN CUTSHAW DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL ROBIN CUTSHAW BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + * + * + * Modified for TVP3026 by Harald Koenig <koenig@tat.physik.uni-tuebingen.de> + * + */ + + + #define NEED_EVENTS + #include <X.h> + #include "Xproto.h" + #include <misc.h> + #include <input.h> + #include <cursorstr.h> + #include <regionstr.h> + #include <scrnintstr.h> + #include <servermd.h> + #include <windowstr.h> + #include "xf86.h" + #include "inputstr.h" + #include "xf86Priv.h" + #include "xf86_OSlib.h" + #include "s3.h" + #include "s3reg.h" + #include "Ti302X.h" + #include "mipointer.h" + + + /* + * s3OutTi3026IndReg() and s3InTi3026IndReg() are used to access the indirect + * 3026 registers only. + */ + + #ifdef __STDC__ + void s3OutTi3026IndReg(unsigned char reg, unsigned char mask, unsigned char data) + #else + void s3OutTi3026IndReg(reg, mask, data) + unsigned char reg; + unsigned char mask; + unsigned char data; + #endif + { + unsigned char tmp, tmp0, tmp1, tmp2 = 0x00; + + outb(vgaCRIndex, 0x55); + tmp0 = inb(vgaCRReg); + tmp = tmp0 & 0xFC; + outb(vgaCRReg, tmp | 0x00); + tmp1 = inb(0x3c8); + outb(0x3c8, reg); + outb(vgaCRReg, tmp | 0x02); + + if (mask != 0x00) + tmp2 = inb(0x3c6) & mask; + outb(0x3c6, tmp2 | data); + + outb(vgaCRReg, tmp | 0x00); + outb(0x3c8, tmp1); /* just in case anyone relies on this */ + outb(vgaCRReg, tmp0); + + #ifdef EXTENDED_DEBUG + ErrorF("Set Ti Ind 0x%x to 0x%x\n",reg,tmp2|data); + #endif + } + + #ifdef __STDC__ + unsigned char s3InTi3026IndReg(unsigned char reg) + #else + unsigned char s3InTi3026IndReg(reg) + unsigned char reg; + #endif + { + unsigned char tmp, tmp0, tmp1, ret; + + outb(vgaCRIndex, 0x55); + tmp0 = inb(vgaCRReg); + tmp = tmp0 & 0xFC; + outb(vgaCRReg, tmp | 0x00); + tmp1 = inb(0x3c8); + outb(0x3c8, reg); + outb(vgaCRReg, tmp | 0x02); + + ret = inb(0x3c6); + + outb(vgaCRReg, tmp | 0x00); + outb(0x3c8, tmp1); /* just in case anyone relies on this */ + outb(vgaCRReg, tmp0); + + return(ret); + } + + /* + * Convert the cursor from server-format to hardware-format. The Ti3020 + * has two planes, plane 0 selects cursor color 0 or 1 and plane 1 + * selects transparent or display cursor. The bits of these planes + * loaded sequentially so that one byte has 8 pixels. The organization + * looks like: + * Byte 0x000 - 0x007 top scan line, left to right plane 0 + * 0x008 - 0x00F + * . . + * 0x1F8 - 0x1FF bottom scan line plane 0 + * + * 0x200 - 0x207 top scan line, left to right plane 1 + * 0x208 - 0x20F + * . . + * 0x3F8 - 0x3FF bottom scan line plane 1 + * + * Byte/bit map - D7,D6,D5,D4,D3,D2,D1,D0 eight pixels each + * Pixel/bit map - P1P0 (plane 1) == 1 maps to cursor color + * (plane 1) == 0 maps to transparent + * (plane 0) maps to cursor colors 0 and 1 + */ + + + void + s3Ti3026ShowCursor() + { + unsigned char tmp; + + UNLOCK_SYS_REGS; + + /* turn on external cursor */ + outb(vgaCRIndex, 0x55); + tmp = inb(vgaCRReg) & 0xDF; + outb(vgaCRReg, tmp | 0x20); + + /* Enable Ti3026 */ + outb(vgaCRIndex, 0x45); + tmp = inb(vgaCRReg); + outb(vgaCRReg, tmp & ~0x20); + + /* Enable cursor - X11 mode */ + s3OutTi3026IndReg(TI_CURS_CONTROL, 0x6c, 0x13); + + LOCK_SYS_REGS; + } + + void + s3Ti3026HideCursor() + { + UNLOCK_SYS_REGS; + + /* + * Don't need to undo the S3 registers here; they will be undone when + * the mode is restored from save registers. If it is done here, it + * causes the cursor to flash each time it is loaded, so don't do that. + */ + + /* Disable cursor */ + s3OutTi3026IndReg(TI_CURS_CONTROL, 0xfc, 0x00); + + LOCK_SYS_REGS; + } + + void + s3Ti3026SetCursorPosition(x, y, xorigin, yorigin) + int x, y, xorigin, yorigin; + { + unsigned char tmp; + + x += 64 - xorigin; + y += 64 - yorigin; + + UNLOCK_SYS_REGS; + + outb(vgaCRIndex, 0x55); + tmp = inb(vgaCRReg) & 0xFC; + outb(vgaCRReg, tmp | 0x03); + + /* Output position - "only" 12 bits of location documented */ + outb(0x3c8, x & 0xFF); + outb(0x3c9, (x >> 8) & 0x0F); + outb(0x3c6, y & 0xFF); + outb(0x3c7, (y >> 8) & 0x0F); + + outb(vgaCRIndex, 0x55); + outb(vgaCRReg, tmp | 0x00); + + LOCK_SYS_REGS; + } + + void + s3Ti3026SetCursorColors(bg, fg) + int bg, fg; + { + unsigned char tmp; + UNLOCK_SYS_REGS; + + /* The TI 3026 cursor is always 8 bits so shift 8, not 10 */ + + outb(vgaCRIndex, 0x55); + tmp = inb(vgaCRReg) & 0xFC; + outb(vgaCRReg, tmp | 0x01); + + /* Background color */ + outb(0x3c8, 0x01); /* cursor color write address */ + outb(0x3c9, (bg & 0x00FF0000) >> 16); + outb(0x3c9, (bg & 0x0000FF00) >> 8); + outb(0x3c9, (bg & 0x000000FF)); + + /* Foreground color */ + outb(0x3c8, 0x02); /* cursor color write address */ + outb(0x3c9, (fg & 0x00FF0000) >> 16); + outb(0x3c9, (fg & 0x0000FF00) >> 8); + outb(0x3c9, (fg & 0x000000FF)); + + outb(vgaCRIndex, 0x55); + outb(vgaCRReg, tmp | 0x00); + + LOCK_SYS_REGS; + } + + void + s3Ti3026LoadCursorImage(bits, xorigin, yorigin) + unsigned char *bits; + int xorigin, yorigin; + { + register int i; + unsigned char tmp; + register unsigned char *mask = bits + 1; + + UNLOCK_SYS_REGS; + + /* position cursor off screen */ + outb(vgaCRIndex, 0x55); + tmp = inb(vgaCRReg) & 0xFC; + outb(vgaCRReg, tmp | 0x03); + + outb(0x3c8, 0); + outb(0x3c9, 0); + outb(0x3c6, 0); + outb(0x3c7, 0); + + outb(vgaCRIndex, 0x55); + outb(vgaCRReg, tmp | 0x00); + + s3OutTi3026IndReg(TI_CURS_CONTROL, 0xf3, 0x00); /* reset A9,A8 */ + outb(0x3c8, 0x00); /* reset cursor RAM load address A7..A0 */ + + outb(vgaCRIndex, 0x55); + outb(vgaCRReg, tmp | 0x02); + + for (i = 0; i < 512; i++, mask+=2) + outb(0x3c7, *mask); + for (i = 0; i < 512; i++, bits+=2) + outb(0x3c7, *bits); + + outb(vgaCRIndex, 0x55); + outb(vgaCRReg, tmp); + + LOCK_SYS_REGS; + } + + *** ./xfree86/vga256/drivers/tvga8900/tgui_accel.c@@/PUBLIC-LATEST Sun Aug 10 13:07:04 1997 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/tvga8900/tgui_accel.c Fri Mar 6 16:55:12 1998 *************** *** 1,8 **** ! /* $TOG: tgui_accel.c /main/2 1997/08/10 13:05:40 kaleb $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/tvga8900/tgui_accel.c,v 3.6.2.4 1997/06/25 08:16:57 hohndel Exp $ */ /* * Copyright 1996 by Alan Hourihane, Wigan, England. --- 1,8 ---- ! /* $TOG: tgui_accel.c /main/3 1998/03/06 16:56:50 kaleb $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/tvga8900/tgui_accel.c,v 3.6.2.5 1998/01/18 10:35:38 hohndel Exp $ */ /* * Copyright 1996 by Alan Hourihane, Wigan, England. *************** *** 43,48 **** --- 43,49 ---- extern int TGUIRops_Pixalu[16]; extern int GE_OP; extern int revision; + extern Bool ClipOn; #include "t89_driver.h" #include "tgui_ger.h" #include "tgui_mmio.h" *************** *** 56,61 **** --- 57,64 ---- #define TGUISetupForFillRectSolid MMIONAME(TGUISetupForFillRectSolid) #define TGUI9685SetupForFillRectSolid MMIONAME(TGUI9685SetupForFillRectSolid) #define TGUISubsequentFillRectSolid MMIONAME(TGUISubsequentFillRectSolid) + #define TGUILinearSubsequentFillRectSolid MMIONAME(TGUILinearSubsequentFillRectSolid) + #define TGUISetClippingRectangle MMIONAME(TGUISetClippingRectangle) #define TGUISetupForScreenToScreenCopy MMIONAME(TGUISetupForScreenToScreenCopy) #define TGUISubsequentScreenToScreenCopy MMIONAME(TGUISubsequentScreenToScreenCopy) #define TGUISubsequentBresenhamLine MMIONAME(TGUISubsequentBresenhamLine) *************** *** 65,72 **** #define TGUISubsequentScreenToScreenColorExpand MMIONAME(TGUISubsequentScreenToScreenColorExpand) #define TGUISetupForFill8x8Pattern MMIONAME(TGUISetupForFill8x8Pattern) #define TGUISubsequentFill8x8Pattern MMIONAME(TGUISubsequentFill8x8Pattern) - #define TGUISetupFor8x8PatternColorExpand MMIONAME(TGUISetupFor8x8PatternColorExpand) - #define TGUISubsequent8x8PatternColorExpand MMIONAME(TGUISubsequent8x8PatternColorExpand) #endif --- 68,73 ---- *************** *** 74,79 **** --- 75,82 ---- void TGUISetupForFillRectSolid(); void TGUI9685SetupForFillRectSolid(); void TGUISubsequentFillRectSolid(); + void TGUILinearSubsequentFillRectSolid(); + void TGUISetClippingRectangle(); void TGUISetupForScreenToScreenCopy(); void TGUISubsequentScreenToScreenCopy(); void TGUISubsequentBresenhamLine(); *************** *** 83,91 **** void TGUISubsequentScreenToScreenColorExpand(); void TGUISetupForFill8x8Pattern(); void TGUISubsequentFill8x8Pattern(); ! void TGUISetupFor8x8PatternColorExpand(); ! void TGUISubsequent8x8PatternColorExpand(); /* * The following function sets up the supported acceleration. Call it * from the FbInit() function in the SVGA driver. --- 86,111 ---- void TGUISubsequentScreenToScreenColorExpand(); void TGUISetupForFill8x8Pattern(); void TGUISubsequentFill8x8Pattern(); ! void TGUISetupForImageWrite(); ! void TGUISubsequentImageWrite(); + #define REPLICATE(x) \ + if (vgaBitsPerPixel < 32) { \ + x |= x << 16; \ + if (vgaBitsPerPixel < 16) \ + x |= x << 8; \ + } + + #define PLANEMASKCHECK(x) \ + x & ((1 << vgaBitsPerPixel)-1) != \ + (1 << vgaBitsPerPixel)-1 + + + #define HAVE_CLIPPING (IsTGUI9685 || IsTGUI9682 || IsTGUI9680 || \ + IsTGUI9660 || IsAdvCyber) + #define HAVE_TRANSPARENCY (IsTGUI9440 || IsTGUI9682 || IsTGUI9685 || IsAdvCyber) + #define HAVE_DASHEDLINES (IsTGUI9685) + /* * The following function sets up the supported acceleration. Call it * from the FbInit() function in the SVGA driver. *************** *** 93,149 **** void TGUIAccelInit() { xf86AccelInfoRec.Flags = BACKGROUND_OPERATIONS | PIXMAP_CACHE | ! HARDWARE_PATTERN_TRANSPARENCY | ! HARDWARE_PATTERN_ALIGN_64 | ! HARDWARE_PATTERN_BIT_ORDER_MSBFIRST | ! HARDWARE_PATTERN_SCREEN_ORIGIN; xf86AccelInfoRec.Sync = TGUISync; xf86GCInfoRec.PolyFillRectSolidFlags = NO_PLANEMASK; ! if ((TVGAchipset == TGUI96xx) && (revision == TGUI9685)) xf86AccelInfoRec.SetupForFillRectSolid = TGUI9685SetupForFillRectSolid; ! else xf86AccelInfoRec.SetupForFillRectSolid = TGUISetupForFillRectSolid; ! xf86AccelInfoRec.SubsequentFillRectSolid = TGUISubsequentFillRectSolid; xf86AccelInfoRec.ErrorTermBits = 11; xf86AccelInfoRec.SubsequentBresenhamLine = TGUISubsequentBresenhamLine; ! xf86GCInfoRec.CopyAreaFlags = NO_TRANSPARENCY | NO_PLANEMASK; xf86AccelInfoRec.SetupForScreenToScreenCopy = TGUISetupForScreenToScreenCopy; xf86AccelInfoRec.SubsequentScreenToScreenCopy = TGUISubsequentScreenToScreenCopy; ! /* In 16/24/32bpp on the 9440 and 96xx, the pattern needs aligning on ! /* a 128/256 pixel boundary, we don't deal with this yet ! */ ! if (vgaBitsPerPixel == 8) ! { ! /* Fill 8x8 Pattern */ ! xf86AccelInfoRec.SetupForFill8x8Pattern = TGUISetupForFill8x8Pattern; ! xf86AccelInfoRec.SubsequentFill8x8Pattern = TGUISubsequentFill8x8Pattern; ! ! /* 8x8 Pattern Color Expand */ ! if (TVGAchipset != TGUI96xx) { ! xf86AccelInfoRec.SetupFor8x8PatternColorExpand = ! TGUISetupFor8x8PatternColorExpand; ! xf86AccelInfoRec.Subsequent8x8PatternColorExpand = ! TGUISubsequent8x8PatternColorExpand; ! } } /* Color Expansion */ ! xf86AccelInfoRec.ColorExpandFlags = VIDEO_SOURCE_GRANULARITY_DWORD | BIT_ORDER_IN_BYTE_MSBFIRST | SCANLINE_PAD_DWORD | CPU_TRANSFER_PAD_DWORD | - LEFT_EDGE_CLIPPING | - NO_TRANSPARENCY | NO_PLANEMASK; xf86AccelInfoRec.SetupForCPUToScreenColorExpand = TGUISetupForCPUToScreenColorExpand; xf86AccelInfoRec.SubsequentCPUToScreenColorExpand = --- 113,175 ---- void TGUIAccelInit() { xf86AccelInfoRec.Flags = BACKGROUND_OPERATIONS | PIXMAP_CACHE | ! HARDWARE_PATTERN_MOD_64_OFFSET | ! HARDWARE_PATTERN_SCREEN_ORIGIN | ! HARDWARE_PATTERN_BIT_ORDER_MSBFIRST; + if (!HAVE_TRANSPARENCY) + xf86AccelInfoRec.Flags |= HARDWARE_PATTERN_TRANSPARENCY | + HARDWARE_PATTERN_MONO_TRANSPARENCY; + xf86AccelInfoRec.Sync = TGUISync; xf86GCInfoRec.PolyFillRectSolidFlags = NO_PLANEMASK; ! if (!HAVE_TRANSPARENCY) ! xf86GCInfoRec.PolyFillRectSolidFlags |= NO_TRANSPARENCY; ! ! if (IsTGUI9685) { xf86AccelInfoRec.SetupForFillRectSolid = TGUI9685SetupForFillRectSolid; ! xf86AccelInfoRec.SubsequentFillRectSolid = TGUISubsequentFillRectSolid; ! } else { xf86AccelInfoRec.SetupForFillRectSolid = TGUISetupForFillRectSolid; ! xf86AccelInfoRec.SubsequentFillRectSolid = TGUISubsequentFillRectSolid; ! } + if (HAVE_CLIPPING) { + xf86AccelInfoRec.SetClippingRectangle = TGUISetClippingRectangle; + xf86AccelInfoRec.Flags |= HARDWARE_CLIP_LINE; + } + xf86AccelInfoRec.ErrorTermBits = 11; xf86AccelInfoRec.SubsequentBresenhamLine = TGUISubsequentBresenhamLine; ! xf86GCInfoRec.CopyAreaFlags = NO_PLANEMASK; + if (!HAVE_TRANSPARENCY) + xf86GCInfoRec.CopyAreaFlags |= NO_TRANSPARENCY; + xf86AccelInfoRec.SetupForScreenToScreenCopy = TGUISetupForScreenToScreenCopy; xf86AccelInfoRec.SubsequentScreenToScreenCopy = TGUISubsequentScreenToScreenCopy; ! /* Fill 8x8 Pattern */ ! if ((vgaBitsPerPixel != 32) && (vga256InfoRec.displayWidth <= 1024)) { ! xf86AccelInfoRec.SetupForFill8x8Pattern = TGUISetupForFill8x8Pattern; ! xf86AccelInfoRec.SubsequentFill8x8Pattern = TGUISubsequentFill8x8Pattern; } /* Color Expansion */ ! xf86AccelInfoRec.ColorExpandFlags = VIDEO_SOURCE_GRANULARITY_PIXEL | BIT_ORDER_IN_BYTE_MSBFIRST | SCANLINE_PAD_DWORD | CPU_TRANSFER_PAD_DWORD | NO_PLANEMASK; + if (!HAVE_TRANSPARENCY) + xf86AccelInfoRec.ColorExpandFlags |= NO_TRANSPARENCY; + xf86AccelInfoRec.SetupForCPUToScreenColorExpand = TGUISetupForCPUToScreenColorExpand; xf86AccelInfoRec.SubsequentCPUToScreenColorExpand = *************** *** 155,165 **** xf86AccelInfoRec.ServerInfoRec = &vga256InfoRec; ! xf86AccelInfoRec.PixmapCacheMemoryStart = vga256InfoRec.virtualY * ! vga256InfoRec.displayWidth * vga256InfoRec.bitsPerPixel / 8; ! xf86AccelInfoRec.PixmapCacheMemoryEnd = vga256InfoRec.videoRam * 1024 - ! (IsCyber ? 4096 : 1024); } /* --- 181,191 ---- xf86AccelInfoRec.ServerInfoRec = &vga256InfoRec; ! xf86AccelInfoRec.PixmapCacheMemoryStart = ! (vga256InfoRec.virtualY * ! vga256InfoRec.displayWidth * vga256InfoRec.bitsPerPixel / 8); ! xf86AccelInfoRec.PixmapCacheMemoryEnd = vga256InfoRec.videoRam * 1024 - 4096; } /* *************** *** 196,204 **** int color, rop; unsigned planemask; { ! /* 9680 has a bug and needs this replication ! */ ! if (vgaBitsPerPixel == 8) ! color = color << 16 | color << 8 | color; TGUI_FCOLOUR(color); TGUI_BCOLOUR(color); --- 222,228 ---- int color, rop; unsigned planemask; { ! REPLICATE(color); TGUI_FCOLOUR(color); TGUI_BCOLOUR(color); *************** *** 209,214 **** --- 233,240 ---- int color, rop; unsigned planemask; { + REPLICATE(color); + TGUI_FPATCOL(color); TGUI_BPATCOL(color); TGUI_FMIX(TGUIRops_Pixalu[rop]); *************** *** 222,239 **** void TGUISubsequentFillRectSolid(x, y, w, h) int x, y, w, h; { ! TGUI_DRAWFLAG(SOLIDFILL | PATMONO); TGUI_DIM_XY(w,h); TGUI_DEST_XY(x,y); TGUI_COMMAND(GE_BLT); } ! /* ! * This is the implementation of the SetupForScreenToScreenCopy function ! * that sets up the coprocessor for a subsequent batch for solid ! * screen-to-screen copies. Remember, we don't handle transparency, ! * so the transparency color is ignored. ! */ static int blitxdir, blitydir; void TGUISetupForScreenToScreenCopy(xdir, ydir, rop, planemask, --- 248,284 ---- void TGUISubsequentFillRectSolid(x, y, w, h) int x, y, w, h; { ! int direction = 0; ! TGUI_DRAWFLAG(SOLIDFILL | PATMONO | direction); TGUI_DIM_XY(w,h); TGUI_DEST_XY(x,y); TGUI_COMMAND(GE_BLT); } ! void TGUILinearSubsequentFillRectSolid(x, y, w, h) ! int x, y, w, h; ! { ! int dstaddr = y * vga256InfoRec.displayWidth + x; ! ! TGUI_DRAWFLAG(SOLIDFILL | PATMONO | DSTLINEAR); ! #if 0 ! TGUI_BBDSTSIZE(h,w); ! TGUI_BBDST(dstaddr); ! #else ! TGUI_DIM_XY(w,h); ! TGUI_DEST_LINEAR(dstaddr); ! TGUI_DEST_PITCH(vga256InfoRec.virtualX); ! #endif ! TGUI_COMMAND(GE_BLT); ! } ! ! void TGUISetClippingRectangle(x1, y1, x2, y2) ! { ! TGUI_SRCCLIP_XY(x1, y1); ! TGUI_DSTCLIP_XY(x2, y2); ! ClipOn = TRUE; ! } ! static int blitxdir, blitydir; void TGUISetupForScreenToScreenCopy(xdir, ydir, rop, planemask, *************** *** 247,256 **** if (xdir < 0) direction |= XNEG; if (ydir < 0) direction |= YNEG; ! if (transparency_color != -1) ! { ! TGUI_FCOLOUR(transparency_color); direction |= TRANS_ENABLE; } TGUI_DRAWFLAG(direction | SCR2SCR); TGUI_FMIX(TGUIRops_alu[rop]); --- 292,301 ---- if (xdir < 0) direction |= XNEG; if (ydir < 0) direction |= YNEG; ! if ((HAVE_TRANSPARENCY) && (transparency_color != -1)) { direction |= TRANS_ENABLE; + REPLICATE(transparency_color); + TGUI_BCOLOUR(transparency_color); } TGUI_DRAWFLAG(direction | SCR2SCR); TGUI_FMIX(TGUIRops_alu[rop]); *************** *** 257,270 **** blitxdir = xdir; blitydir = ydir; } ! /* ! * This is the implementation of the SubsequentForScreenToScreenCopy ! * that sends commands to the coprocessor to perform a screen-to-screen ! * copy of the specified areas, with the parameters from the SetUp call. ! * In this sample implementation, the direction must be taken into ! * account when calculating the addresses (with coordinates, it might be ! * a little easier). ! */ void TGUISubsequentScreenToScreenCopy(x1, y1, x2, y2, w, h) int x1, y1, x2, y2, w, h; { --- 302,308 ---- blitxdir = xdir; blitydir = ydir; } ! void TGUISubsequentScreenToScreenCopy(x1, y1, x2, y2, w, h) int x1, y1, x2, y2, w, h; { *************** *** 293,300 **** --- 331,349 ---- TGUI_SRC_XY(e2,e1); TGUI_DEST_XY(x1,y1); TGUI_DIM_XY(err,length); + if ((HAVE_CLIPPING) && (ClipOn)) { + if ((IsTGUI9682) || (IsAdvCyber)) { + GE_OP &= 0xFEFF; /* Enable Clipping */ + } else + if (IsTGUI9685) { + direction |= CLIPENABLE; + } + } TGUI_DRAWFLAG(SOLIDFILL | STENCIL | direction); TGUI_COMMAND(GE_BRESLINE); + if ((IsTGUI9682) || (IsAdvCyber)) + GE_OP |= 0x100; /* Disable Clipping */ + ClipOn = FALSE; } void TGUISetupForCPUToScreenColorExpand(bg, fg, rop, planemask) *************** *** 303,319 **** { int drawflag = 0; ! /* 9680 has a bug, replication needed ! */ ! if (vgaBitsPerPixel == 8) { ! fg = fg << 16 | fg << 8 | fg; ! bg = bg << 16 | bg << 8 | bg; ! } TGUI_FCOLOUR(fg); ! if (bg == -1) drawflag |= TRANS_ENABLE; ! else TGUI_BCOLOUR(bg); TGUI_DRAWFLAG(SRCMONO | drawflag); TGUI_FMIX(TGUIRops_alu[rop]); } --- 352,367 ---- { int drawflag = 0; ! REPLICATE(fg); TGUI_FCOLOUR(fg); ! if ((HAVE_TRANSPARENCY) && (bg == -1)) { drawflag |= TRANS_ENABLE; ! TGUI_BCOLOUR(~fg); ! } else { ! REPLICATE(bg); TGUI_BCOLOUR(bg); + } TGUI_DRAWFLAG(SRCMONO | drawflag); TGUI_FMIX(TGUIRops_alu[rop]); } *************** *** 321,327 **** void TGUISubsequentCPUToScreenColorExpand(x, y, w, h, skipleft) int x, y, w, h, skipleft; { - TGUI_OUTB(0x2B, skipleft); TGUI_DEST_XY(x,y); TGUI_DIM_XY(w,h); TGUI_COMMAND(GE_BLT); --- 369,374 ---- *************** *** 333,343 **** unsigned planemask; int transparency_color; { ! int drawflag = 0; ! TGUI_FMIX(TGUIRops_Pixalu[rop]); /* ROP */ ! TGUI_DRAWFLAG(drawflag | PAT2SCR); ! TGUI_PATLOC((patterny * vga256InfoRec.displayWidth + (patternx/8)) >> 6); } void TGUISubsequentFill8x8Pattern(patternx, patterny, x, y, w, h) --- 380,396 ---- unsigned planemask; int transparency_color; { ! int direction = 0; ! if ((HAVE_TRANSPARENCY) && (transparency_color != -1)) { ! direction |= TRANS_ENABLE; ! REPLICATE(transparency_color); ! TGUI_BCOLOUR(transparency_color); ! } TGUI_FMIX(TGUIRops_Pixalu[rop]); /* ROP */ ! TGUI_DRAWFLAG(PAT2SCR | direction); ! TGUI_PATLOC(((patterny * vga256InfoRec.displayWidth * ! vga256InfoRec.bitsPerPixel / 8) + ! (patternx * vga256InfoRec.bitsPerPixel / 8)) >> 6); } void TGUISubsequentFill8x8Pattern(patternx, patterny, x, y, w, h) *************** *** 355,371 **** { int drawflag = 0; ! /* 9680 has a bug, replication needed */ ! if (vgaBitsPerPixel == 8) { ! fg = fg << 16 | fg << 8 | fg; ! bg = bg << 16 | bg << 8 | bg; ! } TGUI_FCOLOUR(fg); ! if (bg == -1) drawflag |= TRANS_ENABLE; ! else TGUI_BCOLOUR(bg); TGUI_DRAWFLAG(SCR2SCR | SRCMONO | drawflag); TGUI_FMIX(TGUIRops_alu[rop]); } --- 408,423 ---- { int drawflag = 0; ! REPLICATE(fg); TGUI_FCOLOUR(fg); ! if ((HAVE_TRANSPARENCY) && (bg == -1)) { drawflag |= TRANS_ENABLE; ! TGUI_BCOLOUR(~fg); ! } else { ! REPLICATE(bg); TGUI_BCOLOUR(bg); + } TGUI_DRAWFLAG(SCR2SCR | SRCMONO | drawflag); TGUI_FMIX(TGUIRops_alu[rop]); } *************** *** 374,408 **** int srcx, srcy, x, y, w, h; { TGUI_SRC_XY(srcx,srcy); - TGUI_DEST_XY(x,y); - TGUI_DIM_XY(w,h); - TGUI_COMMAND(GE_BLT); - } - - void TGUISetupFor8x8PatternColorExpand(patternx, patterny, bg, fg, rop, - planemask) - int patternx, patterny, bg, fg, rop, planemask; - { - int drawflag = 0; - - /* 9680 has bug, needs replication */ - if (vgaBitsPerPixel == 8) { - fg = fg << 16 | fg << 8 | fg; - bg = bg << 16 | bg << 8 | bg; - } - - TGUI_FCOLOUR(fg); - if (bg != -1) - TGUI_BCOLOUR(bg); - - TGUI_FMIX(TGUIRops_Pixalu[rop]); /* ROP */ - TGUI_DRAWFLAG(drawflag | PATMONO | PAT2SCR); - TGUI_PATLOC((patterny * vga256InfoRec.displayWidth + (patternx/8)) >> 6); - } - - void TGUISubsequent8x8PatternColorExpand(patternx, patterny, x, y, w, h) - int patternx, patterny, x, y, w, h; - { TGUI_DEST_XY(x,y); TGUI_DIM_XY(w,h); TGUI_COMMAND(GE_BLT); --- 426,431 ---- *** ./xfree86/vga256/drivers/tvga8900/tgui_mmio.h@@/PUBLIC-LATEST Sun Aug 10 13:07:17 1997 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/tvga8900/tgui_mmio.h Fri Mar 6 16:55:20 1998 *************** *** 1,8 **** ! /* $TOG: tgui_mmio.h /main/2 1997/08/10 13:05:53 kaleb $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/tvga8900/tgui_mmio.h,v 3.1.2.3 1997/06/25 08:16:57 hohndel Exp $ */ /* * Copyright 1996 by Alan Hourihane, Wigan, England. * --- 1,8 ---- ! /* $TOG: tgui_mmio.h /main/3 1998/03/06 16:56:58 kaleb $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/tvga8900/tgui_mmio.h,v 3.1.2.4 1998/01/18 10:35:39 hohndel Exp $ */ /* * Copyright 1996 by Alan Hourihane, Wigan, England. * *************** *** 65,72 **** --- 65,76 ---- *(unsigned long *)(tguiMMIOBase + GER_BCOLOUR) = c; #define TGUI_BPATCOL(c) \ *(unsigned long *)(tguiMMIOBase + GER_BPATCOL) = c; + #define TGUI_DSTKEY(c) \ + *(unsigned long *)(tguiMMIOBase + GER_DSTKEY) = c; #define OLDTGUI_BCOLOUR(c) \ *(unsigned long *)(tguiMMIOBase + OLDGER_BCOLOUR) = c; + #define TGUI_PENSTYLE(c) \ + *(unsigned long *)(tguiMMIOBase +GER_PENSTYLE) = c; #define TGUI_DRAWFLAG(c) \ *(unsigned long *)(tguiMMIOBase + GER_DRAWFLAG) = c; #define OLDTGUI_STYLE(c) \ *************** *** 85,90 **** --- 89,106 ---- *(unsigned long *)(tguiMMIOBase + GER_SRC_XY) = XY_MERGE(x,y); #define TGUI_DEST_XY(x,y) \ *(unsigned long *)(tguiMMIOBase + GER_DEST_XY) = XY_MERGE(x,y); + #define TGUI_DEST_LINEAR(c) \ + *(unsigned long *)(tguiMMIOBase + GER_DEST_LINEAR) = (c & 0xFFF) | ((c & 0xFFFFF000) << 4); + #define TGUI_DEST_PITCH(c) \ + *(unsigned long *)(tguiMMIOBase + GER_DEST_PITCH) = c; + #define TGUI_BBDST(c) \ + *(unsigned long *)(tguiMMIOBase + GER_BBDST) = c; + #define TGUI_BBSRC(c) \ + *(unsigned long *)(tguiMMIOBase + GER_BBSRC) = c; + #define TGUI_BBDSTSIZE(x,y) \ + *(unsigned long *)(tguiMMIOBase + GER_BBDSTSIZE) = XY_MERGE(x,y); + #define TGUI_BBSRCSIZE(x,y) \ + *(unsigned long *)(tguiMMIOBase + GER_BBSRCSIZE) = XY_MERGE(x,y); #define OLDTGUI_DESTXY(x,y) \ *(unsigned long *)(tguiMMIOBase + OLDGER_DESTXY) = XY_MERGE(x,y); #define OLDTGUI_DESTLINEAR(c) \ *************** *** 95,110 **** *(unsigned long *)(tguiMMIOBase + GER_DSTCLIP_XY) = XY_MERGE(x,y); #define TGUI_PATLOC(addr) \ *(unsigned short *)(tguiMMIOBase +GER_PATLOC) = addr; #define TGUI_OUTB(addr, c) \ ! *(unsigned char *)(tguiMMIOBase + addr) = c; #define TGUI_COMMAND(c) \ { \ - if (TVGAchipset >= TGUI96xx) { \ - TGUI_SRCCLIP_XY(0,0); \ - TGUI_DSTCLIP_XY(4095,2047); \ - } \ TGUI_OPERMODE(GE_OP); \ ! TGUISync(); \ *(unsigned char *)(tguiMMIOBase + GER_COMMAND) = c; \ } #define OLDTGUI_COMMAND(c) \ --- 111,129 ---- *(unsigned long *)(tguiMMIOBase + GER_DSTCLIP_XY) = XY_MERGE(x,y); #define TGUI_PATLOC(addr) \ *(unsigned short *)(tguiMMIOBase +GER_PATLOC) = addr; + #define TGUI_PLANEMASK(c) \ + *(unsigned long *)(tguiMMIOBase + GER_PLANEMASK) = c; #define TGUI_OUTB(addr, c) \ ! *(unsigned long *)(tguiMMIOBase + addr) = c; #define TGUI_COMMAND(c) \ { \ TGUI_OPERMODE(GE_OP); \ ! if ((IsTGUI9660 || IsTGUI9680) && !ClipOn) { \ ! TGUI_SRCCLIP_XY(0,0);\ ! TGUI_DSTCLIP_XY(2047, 2047);\ ! }; \ ! if (!OFLG_ISSET(OPTION_PCI_RETRY, &vga256InfoRec.options)) \ ! TGUISync(); \ *(unsigned char *)(tguiMMIOBase + GER_COMMAND) = c; \ } #define OLDTGUI_COMMAND(c) \ *************** *** 150,160 **** --- 169,183 ---- outl(GER_BASE+GER_BCOLOUR, c); #define TGUI_BPATCOL(c) \ outl(GER_BASE+GER_BPATCOL, c); + #define TGUI_DSTKEY(c) \ + outl(GER_BASE+GER_DSTKEY, c); #define OLDTGUI_BCOLOUR(c) \ { \ outb(GER_INDEX, OLDGER_BCOLOUR); \ outl(GER_BYTE0, c); \ } + #define TGUI_PENSTYLE(c) \ + outl(GER_BASE+GER_PENSTYLE, c); #define TGUI_DRAWFLAG(c) \ outl(GER_BASE+GER_DRAWFLAG, c); #define OLDTGUI_STYLE(c) \ *************** *** 185,190 **** --- 208,225 ---- outl(GER_BASE+GER_SRC_XY, XY_MERGE(x,y)); #define TGUI_DEST_XY(x,y) \ outl(GER_BASE+GER_DEST_XY, XY_MERGE(x,y)); + #define TGUI_DEST_LINEAR(c) \ + outl(GER_BASE+GER_DEST_LINEAR, (c & 0xFFF) | ((c & 0xFFFFF000) << 4)); + #define TGUI_DEST_PITCH(c) \ + outl(GER_BASE+GER_DEST_PITCH, c); + #define TGUI_BBDST(c) \ + outl(GER_BASE+GER_BBDST, c); + #define TGUI_BBSRC(c) \ + outl(GER_BASE+GER_BBSRC, c); + #define TGUI_BBDSTSIZE(x,y) \ + outl(GER_BASE+GER_BBDSTSIZE, XY_MERGE(x,y)); + #define TGUI_BBSRCSIZE(x,y) \ + outl(GER_BASE+GER_BBSRCSIZE, XY_MERGE(x,y)); #define OLDTGUI_DESTXY(x,y) \ { \ outb(GER_INDEX, OLDGER_DESTXY); \ *************** *** 201,216 **** outl(GER_BASE+GER_DSTCLIP_XY, XY_MERGE(x,y)); #define TGUI_PATLOC(addr) \ outw(GER_BASE+GER_PATLOC, addr); #define TGUI_OUTB(addr, c) \ ! outw(GER_BASE+addr, c); #define TGUI_COMMAND(c) \ { \ - if (TVGAchipset >= TGUI96xx) { \ - outl(GER_BASE+GER_SRCCLIP_XY,XY_MERGE(0,0)); \ - outl(GER_BASE+GER_DSTCLIP_XY,XY_MERGE(4095,2047)); \ - } \ outw(GER_BASE+GER_OPERMODE,GE_OP); \ ! TGUISync(); \ outb(GER_BASE+GER_COMMAND, c); \ } #define OLDTGUI_COMMAND(c) \ --- 236,254 ---- outl(GER_BASE+GER_DSTCLIP_XY, XY_MERGE(x,y)); #define TGUI_PATLOC(addr) \ outw(GER_BASE+GER_PATLOC, addr); + #define TGUI_PLANEMASK(c) \ + outl(GER_BASE+GER_PLANEMASK, c); #define TGUI_OUTB(addr, c) \ ! outb(GER_BASE+addr, c); #define TGUI_COMMAND(c) \ { \ outw(GER_BASE+GER_OPERMODE,GE_OP); \ ! if ((IsTGUI9660 || IsTGUI9680) && !ClipOn) { \ ! TGUI_SRCCLIP_XY(0,0);\ ! TGUI_DSTCLIP_XY(vga256InfoRec.displayWidth - 1, 2047);\ ! }; \ ! if (OFLG_ISSET(OPTION_PCI_RETRY, &vga256InfoRec.options)) \ ! TGUISync(); \ outb(GER_BASE+GER_COMMAND, c); \ } #define OLDTGUI_COMMAND(c) \ *** ./xfree86/xaa/Imakefile@@/PUBLIC-LATEST Sat Jul 19 19:01:23 1997 --- xc/programs/Xserver/hw/xfree86/xaa/Imakefile Sat Mar 7 13:48:53 1998 *************** *** 1,8 **** ! XCOMM $TOG: Imakefile /main/2 1997/07/19 19:01:25 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree86/xaa/Imakefile,v 3.7.2.1 1997/05/03 09:50:21 dawes Exp $ #include <Server.tmpl> --- 1,8 ---- ! XCOMM $TOG: Imakefile /main/4 1998/03/07 13:50:35 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree86/xaa/Imakefile,v 3.7.2.4 1998/02/22 01:28:27 robin Exp $ #include <Server.tmpl> *************** *** 16,22 **** xf86expblt.c xf86expblM.c xf86bitmap.c xf86plane.c \ xf86orect.c xf86line.c xf86seg.c \ xf86bench.c xf86line2.c xf86seg2.c \ ! xf86expblF.c xf86expbFM.c xf86tables.c xf86stip.c BPPOBJS = xaavga256/xaavga256.o xaa8/xaa8.o xaa16/xaa16.o xaa32/xaa32.o --- 16,23 ---- xf86expblt.c xf86expblM.c xf86bitmap.c xf86plane.c \ xf86orect.c xf86line.c xf86seg.c \ xf86bench.c xf86line2.c xf86seg2.c \ ! xf86expblF.c xf86expbFM.c xf86tables.c xf86stip.c xf86dseg.c \ ! xf86dline.c xf86wline.c xf86cursor.c BPPOBJS = xaavga256/xaavga256.o xaa8/xaa8.o xaa16/xaa16.o xaa32/xaa32.o *************** *** 26,32 **** xf86expblt.o xf86expblM.o xf86bitmap.o xf86plane.o \ xf86orect.o xf86line.o xf86seg.o \ xf86bench.o xf86line2.o xf86seg2.o \ ! xf86expblF.o xf86expbFM.o xf86tables.o xf86stip.o #ifdef i386Architecture SRCS = $(GENSRCS) xf86txtblt.s xf86txtblM.s --- 27,34 ---- xf86expblt.o xf86expblM.o xf86bitmap.o xf86plane.o \ xf86orect.o xf86line.o xf86seg.o \ xf86bench.o xf86line2.o xf86seg2.o \ ! xf86expblF.o xf86expbFM.o xf86tables.o xf86stip.o xf86dseg.o \ ! xf86dline.o xf86wline.o xf86cursor.o #ifdef i386Architecture SRCS = $(GENSRCS) xf86txtblt.s xf86txtblM.s *************** *** 62,72 **** --- 64,79 ---- ObjectFromSpecialSource(xf86seg, xf86line, -DPOLYSEGMENT) ObjectFromSpecialSource(xf86seg2, xf86line2, -DPOLYSEGMENT) + #ifndef OS2Architecture DependTarget() + #endif ForceSubdirs($(SUBDIRS)) DependSubdirs($(SUBDIRS)) InstallLinkKitLibrary(xaa,$(LINKKITDIR)/lib) + InstallLinkKitNonExecFile(xf86cursor.h,$(LINKKITDIR)/include) + InstallLinkKitNonExecFile(xf86expblt.h,$(LINKKITDIR)/include) + InstallLinkKitNonExecFile(xf86local.h,$(LINKKITDIR)/include) InstallLinkKitNonExecFile(xf86scrin.h,$(LINKKITDIR)/include) InstallLinkKitNonExecFile(xf86xaa.h,$(LINKKITDIR)/include) *** ./xfree86/xaa/xf86bench.c@@/PUBLIC-LATEST Sat Jul 19 10:59:14 1997 --- xc/programs/Xserver/hw/xfree86/xaa/xf86bench.c Fri Mar 6 16:56:06 1998 *************** *** 1,8 **** ! /* $TOG: xf86bench.c /main/1 1997/07/19 10:59:16 kaleb $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/xaa/xf86bench.c,v 3.5.2.1 1997/05/16 11:35:23 hohndel Exp $ */ /* * Copyright 1996 The XFree86 Project --- 1,8 ---- ! /* $TOG: xf86bench.c /main/2 1998/03/06 16:57:44 kaleb $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/xaa/xf86bench.c,v 3.5.2.3 1998/01/23 14:27:06 robin Exp $ */ /* * Copyright 1996 The XFree86 Project *************** *** 34,39 **** --- 34,40 ---- * This is experimental, and should probably be made optional. */ + #include <X11/Xos.h> #include "servermd.h" #include "windowstr.h" #include "gcstruct.h" *************** *** 40,51 **** #include "regionstr.h" #include "mi.h" #include "fcntl.h" - #include "time.h" - #ifndef Lynx - #include "sys/time.h" - #else - #include <time.h> - #endif #include "xf86.h" #include "xf86xaa.h" --- 41,46 ---- *** /dev/null Tue Jun 30 15:23:21 1998 --- xc/programs/Xserver/hw/xfree86/xaa/xf86cursor.c Fri Mar 6 16:56:11 1998 *************** *** 0 **** --- 1,913 ---- + /* $TOG: xf86cursor.c /main/1 1998/03/06 16:57:49 kaleb $ */ + + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/xaa/xf86cursor.c,v 3.7.2.2 1998/02/07 10:05:51 hohndel Exp $ */ + /* + * Copyright 1996 The XFree86 Project + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * HARM HANEMAAYER BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Written by Harm Hanemaayer (H.Hanemaayer@inter.nl.net). + * Adapted for hardware/software cursor switching (alanh@fairlite.demon.co.uk) + */ + + /* + * Exported functions: + * + * Bool XAACursorInit(char *pm, ScreenPtr pScr) + * void XAARestoreCursor(ScreenPtr pScr) + * void XAAWarpCursor(ScreenPtr pScr, int x, int y) + * void XAAQueryBestSize(int class, unsigned short *pwidth, + * unsigned short *pheight, ScreenPtr pScreen) + * + * In addition, the XAAPointerSpriteFuncs structure is passed to the + * mi initialization function. + */ + + #include "X.h" + #include "Xproto.h" + #include "misc.h" + #include "input.h" + #include "cursorstr.h" + #include "regionstr.h" + #include "scrnintstr.h" + #include "servermd.h" + #include "windowstr.h" + #include "gcstruct.h" + + #include "compiler.h" + #include "xf86.h" + #include "mipointer.h" + #include "xf86Priv.h" + #include "xf86_Option.h" + #include "xf86_OSlib.h" + + #include "xf86xaa.h" + #include "xf86local.h" + #include "xf86cursor.h" + + + extern unsigned char byte_reversed[256]; + extern miPointerScreenFuncRec xf86PointerScreenFuncs; + extern miPointerSpriteFuncRec miSpritePointerFuncs; + + static Bool CharRealizeCursor(ScreenPtr pScr, CursorPtr pCurs); + static Bool ShortRealizeCursor(ScreenPtr pScr, CursorPtr pCurs); + static Bool LongRealizeCursor(ScreenPtr pScr, CursorPtr pCurs); + static Bool Int64RealizeCursor(ScreenPtr pScr, CursorPtr pCurs); + static Bool UnrealizeCursor(ScreenPtr pScr, CursorPtr pCurs); + static void SetCursor(ScreenPtr pScr, CursorPtr pCurs, int x, int y); + static void MoveCursor(ScreenPtr pScr, int x, int y); + + static miPointerSpriteFuncRec XAACharPointerSpriteFuncs = + { + CharRealizeCursor, + UnrealizeCursor, + SetCursor, + MoveCursor, + }; + + static miPointerSpriteFuncRec XAAShortPointerSpriteFuncs = + { + ShortRealizeCursor, + UnrealizeCursor, + SetCursor, + MoveCursor, + }; + + static miPointerSpriteFuncRec XAALongPointerSpriteFuncs = + { + LongRealizeCursor, + UnrealizeCursor, + SetCursor, + MoveCursor, + }; + + static miPointerSpriteFuncRec XAAInt64PointerSpriteFuncs = + { + Int64RealizeCursor, + UnrealizeCursor, + SetCursor, + MoveCursor, + }; + /* + * This set of variables defines the cursor state within the driver. + */ + + static CursorPtr CurrentlyLoadedCursor; + static int CursorGeneration = -1; + static int CursorHotX; + static int CursorHotY; + static int CurrentCursorIsSkewed = FALSE; + Bool tempSWCursor = FALSE; + + static void RecolorCursor(ScreenPtr pScr, CursorPtr pCurs, Bool displayed); + static void LoadCursor(ScreenPtr pScr, CursorPtr pCurs, int x, int y); + static void LoadCursorToCard(ScreenPtr pScr, CursorPtr pCurs, int xoffset, + int yoffset); + + /* + * This is a high-level init function, called once; it passes a local + * miPointerSpriteFuncRec with additional functions that we need to provide. + */ + + Bool XAACursorInit(char *pm, ScreenPtr pScr) + { + CursorHotX = 0; + CursorHotY = 0; + + if (CursorGeneration != serverGeneration) { + miDCInitialize (pScr, &xf86PointerScreenFuncs); + + if (HARDWARE_CURSOR_INT64_BIT_FORMAT & XAACursorInfoRec.Flags) { + if (!(miPointerInitialize(pScr, &XAAInt64PointerSpriteFuncs, + &xf86PointerScreenFuncs, FALSE))) + return FALSE; + } else + + if (HARDWARE_CURSOR_LONG_BIT_FORMAT & XAACursorInfoRec.Flags) { + if (!(miPointerInitialize(pScr, &XAALongPointerSpriteFuncs, + &xf86PointerScreenFuncs, FALSE))) + return FALSE; + } else + + if (HARDWARE_CURSOR_SHORT_BIT_FORMAT & XAACursorInfoRec.Flags) { + if (!(miPointerInitialize(pScr, &XAAShortPointerSpriteFuncs, + &xf86PointerScreenFuncs, FALSE))) + return FALSE; + } else { + if (!(miPointerInitialize(pScr, &XAACharPointerSpriteFuncs, + &xf86PointerScreenFuncs, FALSE))) + return FALSE; + } + + pScr->RecolorCursor = RecolorCursor; + CursorGeneration = serverGeneration; + } + + return TRUE; + } + + + /* + * This function should redisplay a cursor that has been + * displayed earlier. We have to allow for the possiblity + * of a switch between hardware and software cursor. This + * also means that we have to realize the cursor again for + * hardware cursors. + */ + + void XAARestoreCursor(ScreenPtr pScr) + { + int x, y; + + if (tempSWCursor) { + miPointerWarpCursor(pScr, x, y); + LoadCursor(pScr, CurrentlyLoadedCursor, x, y); + } + else { + miPointerPosition(&x, &y); + LoadCursor(pScr, CurrentlyLoadedCursor, x, y); + } + } + + /* + * This doesn't do very much. It just calls the mi routine. + */ + + void XAAWarpCursor(ScreenPtr pScr, int x, int y) + { + miPointerWarpCursor(pScr, x, y); + xf86Info.currentScreen = pScr; + } + + /* + * This function returns the size of the hardware cursor that we + * support when asked for. + */ + + void XAAQueryBestSize(int class, unsigned short *pwidth, + unsigned short *pheight, ScreenPtr pScreen) + { + if (*pwidth > 0) { + if (class == CursorShape) { + *pwidth = XAACursorInfoRec.MaxWidth; + *pheight = XAACursorInfoRec.MaxHeight; + } + else + (void) mfbQueryBestSize(class, pwidth, pheight, pScreen); + } + } + + + /* + * The following functions are also called by the higher level code, + * since they are included in the miPointerSpriteFuncs. + */ + + /* + * This is called when a cursor is no longer used. The intermediate + * cursor image storage that we created needs to be deallocated. + */ + + static Bool UnrealizeCursor(ScreenPtr pScr, CursorPtr pCurs) + { + pointer priv; + + if (pCurs->bits->height > XAACursorInfoRec.MaxHeight || + pCurs->bits->width > XAACursorInfoRec.MaxWidth) { + extern miPointerSpriteFuncRec miSpritePointerFuncs; + return (miSpritePointerFuncs.UnrealizeCursor)(pScr, pCurs); + } + + if (pCurs->bits->refcnt <= 1 && + (priv = pCurs->bits->devPriv[pScr->myNum])) { + xfree(priv); + pCurs->bits->devPriv[pScr->myNum] = 0x0; + } + return TRUE; + } + + /* + * This function is called when the current cursor is moved. It makes + * the graphic chip display the cursor at the new position. + */ + + static void MoveCursor(ScreenPtr pScr, int x, int y) + { + int xorigin, yorigin; + + if (!xf86VTSema) + return; + + if (tempSWCursor) { + (miSpritePointerFuncs.MoveCursor)(pScr, x, y); + return; + } + + x -= xf86AccelInfoRec.ServerInfoRec->frameX0 + CursorHotX; + y -= xf86AccelInfoRec.ServerInfoRec->frameY0 + CursorHotY; + + /* + * If the cursor is partly out of screen at the left or top, + * we need set the origin. + */ + xorigin = 0; + yorigin = 0; + if (x < 0) { + xorigin = -x; + x = 0; + } + if (y < 0) { + yorigin = -y; + y = 0; + } + + if (HARDWARE_CURSOR_SYNC_NEEDED & XAACursorInfoRec.Flags) + xf86AccelInfoRec.Sync(); + + /* Handle cursor hardware that does not have a programmed origin. */ + if (!(XAACursorInfoRec.Flags & HARDWARE_CURSOR_PROGRAMMED_ORIGIN)) { + if (xorigin || yorigin) { + /* Need to upload new cursor image, simulating origin offset. */ + LoadCursorToCard(pScr, CurrentlyLoadedCursor, xorigin, yorigin); + CurrentCursorIsSkewed = TRUE; + } + else + if (CurrentCursorIsSkewed) { + /* Need to upload clean cursor image. */ + LoadCursorToCard(pScr, CurrentlyLoadedCursor, 0, 0); + CurrentCursorIsSkewed = FALSE; + } + } + + XAACursorInfoRec.SetCursorPosition(x, y, xorigin, yorigin); + } + + /* + * This function should display a new cursor at a new position. Due + * to switches between hardware and software cursors, the function + * might need to realize the cursor again. + */ + + static void SetCursor(ScreenPtr pScr, CursorPtr pCurs, int x, int y) + { + + if (!pCurs) + return; + + CurrentlyLoadedCursor = pCurs; + + if (HARDWARE_CURSOR_SYNC_NEEDED & XAACursorInfoRec.Flags) + xf86AccelInfoRec.Sync(); + + if ((pCurs->bits->height > XAACursorInfoRec.MaxHeight) || + (pCurs->bits->width > XAACursorInfoRec.MaxWidth)) { + if(!tempSWCursor) { + XAACursorInfoRec.HideCursor(); + tempSWCursor = TRUE; + } + (miSpritePointerFuncs.SetCursor)(pScr, pCurs, x, y); + return; + } + + if (tempSWCursor) { + (miSpritePointerFuncs.MoveCursor)(pScr, -9999, -9999); + tempSWCursor = FALSE; + } + + CursorHotX = pCurs->bits->xhot; + CursorHotY = pCurs->bits->yhot; + + LoadCursor(pScr, pCurs, x, y); + } + + /* + * This function is called when a new cursor image is requested by + * the server. The main thing to do is convert the bitwise image + * provided by the server into a format that the graphics card + * can conveniently handle, and store that in system memory. + * Adapted from accel/s3/s3Cursor.c. + */ + + static Bool Int64RealizeCursor(ScreenPtr pScr, CursorPtr pCurs) + { + register int i, j; + unsigned long *pServMsk; + unsigned long *pServSrc; + int index = pScr->myNum; + pointer *pPriv = &pCurs->bits->devPriv[index]; + int wsrc, h; + unsigned long *ram; + CursorBitsPtr bits = pCurs->bits; + + if ((bits->height > XAACursorInfoRec.MaxHeight || + bits->width > XAACursorInfoRec.MaxWidth)) { + return (miSpritePointerFuncs.RealizeCursor)(pScr, pCurs); + } + + if (pCurs->bits->refcnt > 1) + return TRUE; + + ram = (unsigned long *)xalloc(1024); + *pPriv = (pointer) ram; + if (!ram) + return FALSE; + + pServSrc = (unsigned long *)bits->source; + pServMsk = (unsigned long *)bits->mask; + + h = bits->height; + if (h > XAACursorInfoRec.MaxHeight) + h = XAACursorInfoRec.MaxHeight; + + wsrc = PixmapBytePad(bits->width, 1); /* Bytes per line. */ + + for (i = 0; i < XAACursorInfoRec.MaxHeight; i++) { + for (j = 0; j < XAACursorInfoRec.MaxWidth / 64; j++) { + unsigned long mask, source; + unsigned long mask_low, source_low; + unsigned long mask_high, source_high; + + if (i < h && j < wsrc/8) { + mask_low = *pServMsk++; + source_low = *pServSrc++; + mask_high = *pServMsk++; + source_high = *pServSrc++; + + if (XAACursorInfoRec.Flags & HARDWARE_CURSOR_BIT_ORDER_MSBFIRST) { + ((char *)&mask_low)[0] = byte_reversed[((unsigned char *)&mask_low)[0]]; + ((char *)&mask_low)[1] = byte_reversed[((unsigned char *)&mask_low)[1]]; + ((char *)&mask_low)[2] = byte_reversed[((unsigned char *)&mask_low)[2]]; + ((char *)&mask_low)[3] = byte_reversed[((unsigned char *)&mask_low)[3]]; + ((char *)&mask_high)[0] = byte_reversed[((unsigned char *)&mask_high)[0]]; + ((char *)&mask_high)[1] = byte_reversed[((unsigned char *)&mask_high)[1]]; + ((char *)&mask_high)[2] = byte_reversed[((unsigned char *)&mask_high)[2]]; + ((char *)&mask_high)[3] = byte_reversed[((unsigned char *)&mask_high)[3]]; + ((char *)&source_low)[0] = byte_reversed[((unsigned char *)&source_low)[0]]; + ((char *)&source_low)[1] = byte_reversed[((unsigned char *)&source_low)[1]]; + ((char *)&source_low)[2] = byte_reversed[((unsigned char *)&source_low)[2]]; + ((char *)&source_low)[3] = byte_reversed[((unsigned char *)&source_low)[3]]; + ((char *)&source_high)[0] = byte_reversed[((unsigned char *)&source_high)[0]]; + ((char *)&source_high)[1] = byte_reversed[((unsigned char *)&source_high)[1]]; + ((char *)&source_high)[2] = byte_reversed[((unsigned char *)&source_high)[2]]; + ((char *)&source_high)[3] = byte_reversed[((unsigned char *)&source_high)[3]]; + } + if (XAACursorInfoRec.Flags & HARDWARE_CURSOR_AND_SOURCE_WITH_MASK) { + source_low &= mask_low; + source_high &= mask_high; + } + + if (XAACursorInfoRec.Flags & HARDWARE_CURSOR_INVERT_MASK) { + mask_low = ~mask_low; + mask_high = ~mask_high; + } + + if (j < XAACursorInfoRec.MaxWidth / 8) { + if (XAACursorInfoRec.Flags & HARDWARE_CURSOR_SWAP_SOURCE_AND_MASK) { + *ram++ = source_low; + *ram++ = source_high; + *ram++ = mask_low; + *ram++ = mask_high; + } else { + *ram++ = mask_low; + *ram++ = mask_high; + *ram++ = source_low; + *ram++ = source_high; + } + } + } else { + if (XAACursorInfoRec.Flags & HARDWARE_CURSOR_INVERT_MASK) + mask = 0xFFFFFFFF; + else + mask = 0x00000000; + + if (XAACursorInfoRec.Flags & HARDWARE_CURSOR_AND_SOURCE_WITH_MASK) + source = 0x00000000; + else + source = 0xFFFFFFFF; + + if (XAACursorInfoRec.Flags & HARDWARE_CURSOR_SWAP_SOURCE_AND_MASK) { + *ram++ = source; + *ram++ = source; + *ram++ = mask; + *ram++ = mask; + } else { + *ram++ = mask; + *ram++ = mask; + *ram++ = source; + *ram++ = source; + } + } + } + /* + * if we still have more bytes on this line (j < wsrc), + * we have to ignore the rest of the line. + */ + while (j++ < wsrc/8) pServMsk++,pServSrc++; + } + return TRUE; + } + + static Bool LongRealizeCursor(ScreenPtr pScr, CursorPtr pCurs) + { + register int i, j; + unsigned long *pServMsk; + unsigned long *pServSrc; + int index = pScr->myNum; + pointer *pPriv = &pCurs->bits->devPriv[index]; + int wsrc, h; + unsigned long *ram; + CursorBitsPtr bits = pCurs->bits; + + if ((bits->height > XAACursorInfoRec.MaxHeight || + bits->width > XAACursorInfoRec.MaxWidth)) { + return (miSpritePointerFuncs.RealizeCursor)(pScr, pCurs); + } + + if (pCurs->bits->refcnt > 1) + return TRUE; + + ram = (unsigned long *)xalloc(1024); + *pPriv = (pointer) ram; + if (!ram) + return FALSE; + + pServSrc = (unsigned long *)bits->source; + pServMsk = (unsigned long *)bits->mask; + + h = bits->height; + if (h > XAACursorInfoRec.MaxHeight) + h = XAACursorInfoRec.MaxHeight; + + wsrc = PixmapBytePad(bits->width, 1); /* Bytes per line. */ + + for (i = 0; i < XAACursorInfoRec.MaxHeight; i++) { + for (j = 0; j < XAACursorInfoRec.MaxWidth / 32; j++) { + unsigned long mask, source; + + if (i < h && j < wsrc/4) { + mask = *pServMsk++; + source = *pServSrc++; + + if (XAACursorInfoRec.Flags & HARDWARE_CURSOR_BIT_ORDER_MSBFIRST) { + ((char *)&mask)[0] = byte_reversed[((unsigned char *)&mask)[0]]; + ((char *)&mask)[1] = byte_reversed[((unsigned char *)&mask)[1]]; + ((char *)&mask)[2] = byte_reversed[((unsigned char *)&mask)[2]]; + ((char *)&mask)[3] = byte_reversed[((unsigned char *)&mask)[3]]; + ((char *)&source)[0] = byte_reversed[((unsigned char *)&source)[0]]; + ((char *)&source)[1] = byte_reversed[((unsigned char *)&source)[1]]; + ((char *)&source)[2] = byte_reversed[((unsigned char *)&source)[2]]; + ((char *)&source)[3] = byte_reversed[((unsigned char *)&source)[3]]; + } + if (XAACursorInfoRec.Flags & HARDWARE_CURSOR_AND_SOURCE_WITH_MASK) + source &= mask; + + if (XAACursorInfoRec.Flags & HARDWARE_CURSOR_INVERT_MASK) + mask = ~mask; + + if (j < XAACursorInfoRec.MaxWidth / 8) { + if (XAACursorInfoRec.Flags & HARDWARE_CURSOR_SWAP_SOURCE_AND_MASK) { + *ram++ = source; + *ram++ = mask; + } else { + *ram++ = mask; + *ram++ = source; + } + } + } else { + if (XAACursorInfoRec.Flags & HARDWARE_CURSOR_INVERT_MASK) + mask = 0xFFFFFFFF; + else + mask = 0x00000000; + + if (XAACursorInfoRec.Flags & HARDWARE_CURSOR_AND_SOURCE_WITH_MASK) + source = 0x00000000; + else + source = 0xFFFFFFFF; + + if (XAACursorInfoRec.Flags & HARDWARE_CURSOR_SWAP_SOURCE_AND_MASK) { + *ram++ = source; + *ram++ = mask; + } else { + *ram++ = mask; + *ram++ = source; + } + } + } + /* + * if we still have more bytes on this line (j < wsrc), + * we have to ignore the rest of the line. + */ + while (j++ < wsrc/4) pServMsk++,pServSrc++; + } + return TRUE; + } + + static Bool ShortRealizeCursor(ScreenPtr pScr, CursorPtr pCurs) + { + register int i, j; + unsigned short *pServMsk; + unsigned short *pServSrc; + int index = pScr->myNum; + pointer *pPriv = &pCurs->bits->devPriv[index]; + int wsrc, h; + unsigned short *ram; + CursorBitsPtr bits = pCurs->bits; + + if ((bits->height > XAACursorInfoRec.MaxHeight || + bits->width > XAACursorInfoRec.MaxWidth)) { + return (miSpritePointerFuncs.RealizeCursor)(pScr, pCurs); + } + + if (pCurs->bits->refcnt > 1) + return TRUE; + + ram = (unsigned short *)xalloc(1024); + *pPriv = (pointer) ram; + if (!ram) + return FALSE; + + pServSrc = (unsigned short *)bits->source; + pServMsk = (unsigned short *)bits->mask; + + h = bits->height; + if (h > XAACursorInfoRec.MaxHeight) + h = XAACursorInfoRec.MaxHeight; + + wsrc = PixmapBytePad(bits->width, 1); /* Bytes per line. */ + + for (i = 0; i < XAACursorInfoRec.MaxHeight; i++) { + for (j = 0; j < XAACursorInfoRec.MaxWidth / 16; j++) { + unsigned short mask, source; + + if (i < h && j < wsrc/2) { + mask = *pServMsk++; + source = *pServSrc++; + + if (XAACursorInfoRec.Flags & HARDWARE_CURSOR_BIT_ORDER_MSBFIRST) { + ((char *)&mask)[0] = byte_reversed[((unsigned char *)&mask)[0]]; + ((char *)&mask)[1] = byte_reversed[((unsigned char *)&mask)[1]]; + ((char *)&source)[0] = byte_reversed[((unsigned char *)&source)[0]]; + ((char *)&source)[1] = byte_reversed[((unsigned char *)&source)[1]]; + } + if (XAACursorInfoRec.Flags & HARDWARE_CURSOR_AND_SOURCE_WITH_MASK) + source &= mask; + + if (XAACursorInfoRec.Flags & HARDWARE_CURSOR_INVERT_MASK) + mask = ~mask; + + if (j < XAACursorInfoRec.MaxWidth / 8) { + if (XAACursorInfoRec.Flags & HARDWARE_CURSOR_SWAP_SOURCE_AND_MASK) { + *ram++ = source; + *ram++ = mask; + } else { + *ram++ = mask; + *ram++ = source; + } + } + } else { + if (XAACursorInfoRec.Flags & HARDWARE_CURSOR_INVERT_MASK) + mask = 0xFFFF; + else + mask = 0x0000; + + if (XAACursorInfoRec.Flags & HARDWARE_CURSOR_AND_SOURCE_WITH_MASK) + source = 0x0000; + else + source = 0xFFFF; + + if (XAACursorInfoRec.Flags & HARDWARE_CURSOR_SWAP_SOURCE_AND_MASK) { + *ram++ = source; + *ram++ = mask; + } else { + *ram++ = mask; + *ram++ = source; + } + } + } + /* + * if we still have more bytes on this line (j < wsrc), + * we have to ignore the rest of the line. + */ + while (j++ < wsrc/2) pServMsk++,pServSrc++; + } + return TRUE; + } + + static Bool CharRealizeCursor(ScreenPtr pScr, CursorPtr pCurs) + { + register int i, j; + unsigned char *pServMsk; + unsigned char *pServSrc; + int index = pScr->myNum; + pointer *pPriv = &pCurs->bits->devPriv[index]; + int wsrc, h; + unsigned char *ram; + CursorBitsPtr bits = pCurs->bits; + + if ((bits->height > XAACursorInfoRec.MaxHeight || + bits->width > XAACursorInfoRec.MaxWidth)) { + return (miSpritePointerFuncs.RealizeCursor)(pScr, pCurs); + } + + if (pCurs->bits->refcnt > 1) + return TRUE; + + ram = (unsigned char *)xalloc(1024); + *pPriv = (pointer) ram; + if (!ram) + return FALSE; + + pServSrc = (unsigned char *)bits->source; + pServMsk = (unsigned char *)bits->mask; + + h = bits->height; + if (h > XAACursorInfoRec.MaxHeight) + h = XAACursorInfoRec.MaxHeight; + + wsrc = PixmapBytePad(bits->width, 1); /* Bytes per line. */ + + for (i = 0; i < XAACursorInfoRec.MaxHeight; i++) { + for (j = 0; j < XAACursorInfoRec.MaxWidth / 8; j++) { + unsigned char mask, source, m, s; + + if (i < h && j < wsrc) { + mask = *pServMsk++; + source = *pServSrc++; + + if (XAACursorInfoRec.Flags & HARDWARE_CURSOR_BIT_ORDER_MSBFIRST) { + mask = byte_reversed[mask]; + source = byte_reversed[source]; + } + if (XAACursorInfoRec.Flags & HARDWARE_CURSOR_AND_SOURCE_WITH_MASK) + source &= mask; + + if (XAACursorInfoRec.Flags & HARDWARE_CURSOR_INVERT_MASK) + mask = ~mask; + + if (XAACursorInfoRec.Flags & HARDWARE_CURSOR_SOURCE_MASK_INTERLEAVE) { + m = ((mask&0x01) << 7) | ((source&0x01) << 6) | + ((mask&0x02) << 4) | ((source&0x02) << 3) | + ((mask&0x04) << 1) | (source&0x04) | + ((mask&0x08) >> 2) | ((source&0x08) >> 3) ; + s = ((mask&0x10) << 3) | ((source&0x10) << 2) | + (mask&0x20) | ((source&0x20) >> 1) | + ((mask&0x40) >> 3) | ((source&0x40) >> 4) | + ((mask&0x80) >> 6) | ((source&0x80) >> 7) ; + mask = m; + source = s; + } + if (XAACursorInfoRec.Flags & HARDWARE_CURSOR_SWAP_SOURCE_AND_MASK) { + *ram++ = source; + *ram++ = mask; + } else { + *ram++ = mask; + *ram++ = source; + } + } else { + if (XAACursorInfoRec.Flags & HARDWARE_CURSOR_INVERT_MASK) + mask = 0xFF; + else + mask = 0x00; + + if (XAACursorInfoRec.Flags & HARDWARE_CURSOR_AND_SOURCE_WITH_MASK) + source = 0x00; + else + source = 0xFF; + + if (XAACursorInfoRec.Flags & HARDWARE_CURSOR_SWAP_SOURCE_AND_MASK) { + m = mask; + mask = source; + source = m; + } + + if (XAACursorInfoRec.Flags & HARDWARE_CURSOR_SOURCE_MASK_INTERLEAVE) { + if ((source == 0x00) && (mask == 0x00)) { + source = 0x00; + mask = 0x00; + } else if ((source == 0xFF) && (mask == 0x00)) { + if (XAACursorInfoRec.Flags & HARDWARE_CURSOR_BIT_ORDER_MSBFIRST) { + source = 0xAA; + mask = 0xAA; + } else { + source = 0x55; + mask = 0x55; + } + } else if ((source == 0x00) && (mask == 0xFF)) { + if (XAACursorInfoRec.Flags & HARDWARE_CURSOR_BIT_ORDER_MSBFIRST) { + source = 0x55; + mask = 0x55; + } else { + source = 0xAA; + mask = 0xAA; + } + } else { + source = 0xFF; + mask = 0xFF; + } + } + *ram++ = mask; + *ram++ = source; + } + } + /* + * if we still have more bytes on this line (j < wsrc), + * we have to ignore the rest of the line. + */ + while (j++ < wsrc) pServMsk++,pServSrc++; + } + return TRUE; + } + + + /* + * Now local functions that are not directly called by higher-level code. + */ + + static void RecolorCursor(ScreenPtr pScr, CursorPtr pCurs, Bool displayed) + { + ColormapPtr pmap; + unsigned short packedcolfg, packedcolbg; + + if (!xf86VTSema || tempSWCursor) { + miRecolorCursor(pScr, pCurs, displayed); + return; + } + + if (!displayed) + return; + + if (HARDWARE_CURSOR_SYNC_NEEDED & XAACursorInfoRec.Flags) + xf86AccelInfoRec.Sync(); + + if (xf86AccelInfoRec.BitsPerPixel == 8 && + !(XAACursorInfoRec.Flags & HARDWARE_CURSOR_TRUECOLOR_AT_8BPP)) { + xColorItem sourceColor, maskColor; + XAACursorInfoRec.GetInstalledColormaps(pScr, &pmap); + sourceColor.red = pCurs->foreRed; + sourceColor.green = pCurs->foreGreen; + sourceColor.blue = pCurs->foreBlue; + FakeAllocColor(pmap, &sourceColor); + maskColor.red = pCurs->backRed; + maskColor.green = pCurs->backGreen; + maskColor.blue = pCurs->backBlue; + FakeAllocColor(pmap, &maskColor); + FakeFreeColor(pmap, sourceColor.pixel); + FakeFreeColor(pmap, maskColor.pixel); + XAACursorInfoRec.SetCursorColors(maskColor.pixel, sourceColor.pixel); + } + else + /* Pass colors in 8-8-8 RGB format, blue byte first. */ + XAACursorInfoRec.SetCursorColors( + (pCurs->backBlue >> 8) | + ((pCurs->backGreen >> 8) << 8) | + ((pCurs->backRed >> 8) << 16), + (pCurs->foreBlue >> 8) | + ((pCurs->foreGreen >> 8) << 8) | + ((pCurs->foreRed >> 8) << 16) + ); + } + + /* + * This function uploads a cursor image to the video memory of the + * graphics card. The source image has already been converted by the + * Realize function to a format that can be quickly transferred to + * the card. + * This is a local function that is not called from outside of this + * module. + */ + + static void LoadCursorToCard(ScreenPtr pScr, CursorPtr pCurs, int xoffset, + int yoffset) + { + unsigned char *cursor_image; + int index = pScr->myNum; + + if (tempSWCursor) + return; + + cursor_image = (unsigned char *)pCurs->bits->devPriv[index]; + + if (XAACursorInfoRec.Flags & HARDWARE_CURSOR_PROGRAMMED_BITS) { + /* + * Cursor image must be explicitly programmed in a chip-specific + * function. + */ + XAACursorInfoRec.LoadCursorImage(cursor_image, xoffset, yoffset); + } + else + if (xoffset == 0 && yoffset == 0) + xf86AccelInfoRec.ImageWrite( + XAACursorInfoRec.CursorDataX, + XAACursorInfoRec.CursorDataY, + (XAACursorInfoRec.MaxWidth * XAACursorInfoRec.MaxHeight * 2) / xf86bpp, + 1, + cursor_image, + 0, GXcopy, ~0 + ); + else + /* + * XXX + * Must simulate programmable origin by uploading pattern + * "skewed" (horizontally and/or vertically). + */ + ; + } + + /* + * This function should make the graphics chip display new cursor that + * has already been "realized". We need to upload it to video memory, + * make the graphics chip display it. + * This is a local function that is not called from outside of this + * module (although it largely corresponds to what the SetCursor + * function in the Pointer record needs to do). + */ + + static void LoadCursor(ScreenPtr pScr, CursorPtr pCurs, int x, int y) + { + if (!xf86VTSema) + return; + + if (!pCurs) + return; + + if (HARDWARE_CURSOR_SYNC_NEEDED & XAACursorInfoRec.Flags) + xf86AccelInfoRec.Sync(); + + if (!tempSWCursor) XAACursorInfoRec.HideCursor(); + + /* + * In the case of no programmable origin, the pattern will be + * reloaded during MoveCursor if necessary. + */ + LoadCursorToCard(pScr, pCurs, 0, 0); + + RecolorCursor(pScr, pCurs, 1); + + /* Position cursor */ + MoveCursor(pScr, x, y); + + /* Turn it on. */ + if (!tempSWCursor) XAACursorInfoRec.ShowCursor(); + } + + *** /dev/null Tue Jun 30 15:23:22 1998 --- xc/programs/Xserver/hw/xfree86/xaa/xf86cursor.h Fri Mar 6 16:56:16 1998 *************** *** 0 **** --- 1,39 ---- + /* $TOG: xf86cursor.h /main/1 1998/03/06 16:57:54 kaleb $ */ + + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/xaa/xf86cursor.h,v 3.5.2.1 1998/02/01 16:42:14 robin Exp $ */ + typedef struct { + int Flags; + int MaxWidth; + int MaxHeight; + int CursorDataX; + int CursorDataY; + void (*SetCursorColors)(int bg, int fg); + void (*SetCursorPosition)(int x, int y, int xorigin, int yorigin); + void (*LoadCursorImage)(void *bits, int xorigin, int yorigin); + void (*HideCursor)(); + void (*ShowCursor)(); + int (*GetInstalledColormaps)(); + } XAACursorInfoRecType; + + enum { + HARDWARE_CURSOR_TRUECOLOR_AT_8BPP = 0x1, + HARDWARE_CURSOR_PROGRAMMED_BITS = 0x2, + HARDWARE_CURSOR_BIT_ORDER_MSBFIRST = 0x4, + HARDWARE_CURSOR_PROGRAMMED_ORIGIN = 0x8, + HARDWARE_CURSOR_PLANES_NOT_INTERLEAVED = 0x10, + HARDWARE_CURSOR_AND_SOURCE_WITH_MASK = 0x20, + HARDWARE_CURSOR_SWAP_SOURCE_AND_MASK = 0x40, + USE_HARDWARE_CURSOR = 0x80, + HARDWARE_CURSOR_INT64_BIT_FORMAT = 0x100, + HARDWARE_CURSOR_LONG_BIT_FORMAT = 0x200, + HARDWARE_CURSOR_SHORT_BIT_FORMAT = 0x400, + HARDWARE_CURSOR_CHAR_BIT_FORMAT = 0x800, + HARDWARE_CURSOR_SOURCE_MASK_INTERLEAVE = 0x1000, + HARDWARE_CURSOR_SYNC_NEEDED = 0x2000, + HARDWARE_CURSOR_INVERT_MASK = 0x4000 + }; + + extern XAACursorInfoRecType XAACursorInfoRec; *** ./xfree86/xaa/xf86defs.c@@/PUBLIC-LATEST Sat Jul 19 10:59:30 1997 --- xc/programs/Xserver/hw/xfree86/xaa/xf86defs.c Fri Mar 6 16:56:19 1998 *************** *** 1,13 **** ! /* $TOG: xf86defs.c /main/1 1997/07/19 10:59:32 kaleb $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/xaa/xf86defs.c,v 3.4 1997/01/20 12:38:19 dawes Exp $ */ #include "windowstr.h" #include "gcstruct.h" #include "regionstr.h" #include "xf86.h" #include "xf86xaa.h" --- 1,14 ---- ! /* $TOG: xf86defs.c /main/2 1998/03/06 16:57:57 kaleb $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/xaa/xf86defs.c,v 3.4.2.1 1998/02/01 16:05:20 robin Exp $ */ #include "windowstr.h" #include "gcstruct.h" #include "regionstr.h" + #include "xf86cursor.h" #include "xf86.h" #include "xf86xaa.h" *************** *** 34,39 **** --- 35,42 ---- NULL, 0, /* FillSpansStippled() */ NULL, 0, /* FillSpansOpaqueStippled() */ NULL, 0, /* CopyArea() */ + NULL, 0, /* PolyLineDashedZeroWidth() */ + NULL, 0, /* PolySegmentDashedZeroWidth() */ NULL, /* FillSpansFallBack */ NULL, /* PolyGlyphBltFallBack() */ NULL, /* ImageGlyphBltFallBack() */ *************** *** 62,67 **** --- 65,71 ---- NULL, /* WriteBitmapFallBack() */ NULL, /* SetupForFillRectSolid() */ NULL, /* SubsequentFillRectSolid() */ + NULL, /* SubsequentFillTrapezoidSolid() */ NULL, /* SetupForScreenToScreenCopy() */ NULL, /* SubsequentScreenToScreenCopy() */ NULL, /* SubsequentBresenhamLine() */ *************** *** 70,76 **** NULL, /* SetupForFill8x8Pattern() */ NULL, /* SubsequentFill8x8Pattern() */ NULL, /* SetupFor8x8PatternColorExpand() */ ! NULL, /* SetupFor8x8PatternColorExpand() */ NULL, /* SetupForCPUToScreenColorExpand() */ NULL, /* SubsequentCPUToScreenColorExpand() */ NULL, /* SetupForScreenToScreenColorExpand() */ --- 74,80 ---- NULL, /* SetupForFill8x8Pattern() */ NULL, /* SubsequentFill8x8Pattern() */ NULL, /* SetupFor8x8PatternColorExpand() */ ! NULL, /* Subsequent8x8PatternColorExpand() */ NULL, /* SetupForCPUToScreenColorExpand() */ NULL, /* SubsequentCPUToScreenColorExpand() */ NULL, /* SetupForScreenToScreenColorExpand() */ *************** *** 84,89 **** --- 88,96 ---- NULL, /* VerticalLineGXcopyFallBack() */ NULL, /* BresenhamLineFallBack() */ NULL, /* xf86GetLongWidthAndPointer() */ + NULL, /* SetupForDashedLine() */ + NULL, /* SubsequentDashedBresenhamLine() */ + NULL, /* SubsequentDashedTwoPointLine() */ NULL, /* Sync() */ 0, /* Flags */ 0, /* ColorExpandFlags */ *************** *** 103,106 **** --- 110,129 ---- NULL, /* ServerInfoRec */ 0, /* PixmapCacheMemoryStart */ 0, /* PixmapCacheMemoryEnd */ + 0, /* LinePatternMaxLength */ + NULL, /* LinePatternBuffer */ + }; + + XAACursorInfoRecType XAACursorInfoRec = { + 0, /* Flags */ + 0, /* MaxWidth */ + 0, /* MaxHeight */ + 0, /* CursorDataX */ + 0, /* CursorDataY */ + NULL, /* SetCursorColors */ + NULL, /* SetCursorPosition */ + NULL, /* LoadCursorImage */ + NULL, /* HideCursor */ + NULL, /* ShowCursor */ + NULL /* GetInstalledColormaps */ }; *** /dev/null Tue Jun 30 15:23:23 1998 --- xc/programs/Xserver/hw/xfree86/xaa/xf86dline.c Sat Mar 7 16:55:05 1998 *************** *** 0 **** --- 1,591 ---- + /* $TOG: xf86dline.c /main/2 1998/03/07 16:56:46 kaleb $ */ + + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/xaa/xf86dline.c,v 3.11.2.1 1998/02/01 16:42:14 robin Exp $ */ + + /*********************************************************** + + Copyright (c) 1987 X Consortium + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name of the X Consortium shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the X Consortium. + + + Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + + Permission to use, copy, modify, and distribute this software and its + documentation for any purpose and without fee is hereby granted, + provided that the above copyright notice appear in all copies and that + both that copyright notice and this permission notice appear in + supporting documentation, and that the name of Digital not be + used in advertising or publicity pertaining to distribution of the + software without specific, written prior permission. + + DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING + ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL + DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR + ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, + WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, + ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS + SOFTWARE. + + ******************************************************************/ + /* $TOG: xf86dline.c /main/2 1998/03/07 16:56:46 kaleb $ */ + /* $XFree86: xc/programs/Xserver/hw/xfree86/xaa/xf86dline.c,v 3.11.2.1 1998/02/01 16:42:14 robin Exp $ */ + + /* + * Accelerated dashed lines. + * Adapted from xf86line.c by Mark Vojkovich (mvojkovi@ucsd.edu). + * + * The xf86AccelInfoRec.Flags HARDWARE_CLIP_LINE flag indicates that + * lines are clipped by the hardware. In that case, SetClippingRectangle + * must be defined. + * + * At the moment, when software clipping is used the Bresenham error term + * gets to large, at which point it is scaled. The precision is taken + * from xf86AccelInfoRec.ErrorTermBits. + */ + + + #include "X.h" + #include "Xmd.h" + + #include "gcstruct.h" + #include "windowstr.h" + #include "pixmapstr.h" + #include "regionstr.h" + #include "scrnintstr.h" + #include "mistruct.h" + /* PSZ doesn't matter. */ + #define PSZ 8 + #include "cfb.h" + #include "miline.h" + + #include "xf86.h" + #include "xf86xaa.h" + #include "xf86local.h" + #include "xf86Priv.h" + + + int xf86PackDashPattern(GCPtr pGC) + { + Bool EvenDash = (pGC->numInDashList & 0x01) ? FALSE : TRUE; + int PatternLength = 0; + unsigned char* DashPtr = (unsigned char*)pGC->dash; + int count = pGC->numInDashList; + + while(count--) + PatternLength += *(DashPtr++); + + if(!EvenDash) + PatternLength <<= 1; + + if(PatternLength > xf86AccelInfoRec.LinePatternMaxLength) + return 0; + + if(xf86AccelInfoRec.Flags & LINE_PATTERN_POWER_OF_2_ONLY) { + if(PatternLength & (PatternLength - 1)) + return 0; + } + + DashPtr = (unsigned char*)pGC->dash; + + if(xf86AccelInfoRec.Flags & LINE_PATTERN_MSBFIRST_MSBJUSTIFIED) { + register CARD32* PatPtr = + (CARD32*)xf86AccelInfoRec.LinePatternBuffer + + ((xf86AccelInfoRec.LinePatternMaxLength - 1) >> 5); + register unsigned char value; + register int bits = 0; + Bool set = TRUE; + + count = (EvenDash) ? PatternLength : (PatternLength >> 1); + + CONCATENATE: + + while(count) { + value = *(DashPtr++); + + if(set) { + count -= value; + while(value--) { + *PatPtr = (*PatPtr << 1) | 0x01; + if((++bits) & 32) { + PatPtr--; + bits = 0; + } + } + set = FALSE; + } else { + count -= value; + while(value--) { + *PatPtr <<= 1; + if((++bits) & 32) { + PatPtr--; + bits = 0; + } + } + set = TRUE; + } + } + + if(!EvenDash) { + EvenDash = TRUE; + DashPtr = (unsigned char*)pGC->dash; + count = PatternLength >> 1; + goto CONCATENATE; + } + + if(bits) + *PatPtr <<= (32 - bits); + } else { /* LINE_PATTERN_MSBFIRST_LSBJUSTIFIED */ + register CARD32* PatPtr; + register unsigned char value; + register int bits; + Bool set = TRUE; + + count = (EvenDash) ? PatternLength : (PatternLength >> 1); + + PatPtr = (CARD32*)xf86AccelInfoRec.LinePatternBuffer + + ((PatternLength - 1) >> 5); + bits = (PatternLength - 1) & 31; + + CONCATENATE_2: + + while(count) { + value = *(DashPtr++); + + if(set) { + count -= value; + while(value--) { + *PatPtr = (*PatPtr << 1) | 0x01; + if(!(bits--)) { + PatPtr--; + bits = 31; + } + } + set = FALSE; + } else { + count -= value; + while(value--) { + *PatPtr <<= 1; + if(!(bits--)) { + PatPtr--; + bits = 31; + } + } + set = TRUE; + } + } + + if(!EvenDash) { + EvenDash = TRUE; + DashPtr = (unsigned char*)pGC->dash; + count = PatternLength >> 1; + goto CONCATENATE_2; + } + } + + + return PatternLength; + } + + + + + void + #ifdef POLYSEGMENT + xf86PolyDashedSegment(pDrawable, pGC, nseg, pSeg) + DrawablePtr pDrawable; + GCPtr pGC; + int nseg; + register xSegment *pSeg; + #else + xf86PolyDashedLine(pDrawable, pGC, mode, npt, pptInit) + DrawablePtr pDrawable; + GCPtr pGC; + int mode; /* Origin or Previous */ + int npt; /* number of points */ + DDXPointPtr pptInit; + #endif + { + int nboxInit; + register int nbox; + BoxPtr pboxInit; + register BoxPtr pbox; + #ifndef POLYSEGMENT + register DDXPointPtr ppt; /* pointer to list of translated points */ + #endif + + unsigned int oc1; /* outcode of point 1 */ + unsigned int oc2; /* outcode of point 2 */ + + int xorg, yorg; /* origin of window */ + + int adx; /* abs values of dx and dy */ + int ady; + int e, e1, e2; /* bresenham error and increments */ + int len; /* length of segment */ + unsigned int bias = miGetZeroLineBias(pDrawable->pScreen); + Bool EvenDash = TRUE; + int signdx, signdy, octant; + + /* a bunch of temporaries */ + int tmp; + register int y1, y2; + register int x1, x2; + RegionPtr cclip; + cfbPrivGCPtr devPriv; + int PatternOffset; + int PatternLength; + Bool UseTwoPointLine = (xf86AccelInfoRec.Flags & USE_TWO_POINT_LINE); + + if (((xf86AccelInfoRec.Flags & LINE_PATTERN_ONLY_TRANSPARENCY) && + (pGC->lineStyle == LineDoubleDash)) || + !(PatternLength = xf86PackDashPattern(pGC))) { + #ifdef POLYSEGMENT + switch (xf86bpp) { + case 8: + #ifdef VGA256 + vga256SegmentSD(pDrawable, pGC, nseg, pSeg); + #else + cfbSegmentSD(pDrawable, pGC, nseg, pSeg); + #endif + break; + case 16: + cfb16SegmentSD(pDrawable, pGC, nseg, pSeg); + break; + #if 0 + case 24: + cfb24SegmentSD(pDrawable, pGC, nseg, pSeg); + break; + #endif + case 32: + cfb32SegmentSD(pDrawable, pGC, nseg, pSeg); + break; + } + #else + switch (xf86bpp) { + case 8: + #ifdef VGA256 + vga256SegmentSD(pDrawable, pGC, mode, npt, pptInit); + #else + cfbLineSD(pDrawable, pGC, mode, npt, pptInit); + #endif + break; + case 16: + cfb16LineSD(pDrawable, pGC, mode, npt, pptInit); + break; + #if 0 + case 24: + cfb24LineSD(pDrawable, pGC, mode, npt, pptInit); + break; + #endif + case 32: + cfb32LineSD(pDrawable, pGC, mode, npt, pptInit); + break; + } + #endif + return; + } + + PatternOffset = pGC->dashOffset % PatternLength; + + + devPriv = cfbGetGCPrivate(pGC); + cclip = devPriv->pCompositeClip; + pboxInit = REGION_RECTS(cclip); + nboxInit = REGION_NUM_RECTS(cclip); + + + xf86AccelInfoRec.SetupForDashedLine(pGC->fgPixel, + (pGC->lineStyle == LineDoubleDash) ? pGC->bgPixel : -1, + pGC->alu, pGC->planemask, PatternLength); + + + xorg = pDrawable->x; + yorg = pDrawable->y; + #ifdef POLYSEGMENT + while (nseg--) + #else + ppt = pptInit; + x2 = ppt->x + xorg; + y2 = ppt->y + yorg; + while(--npt) + #endif + { + nbox = nboxInit; + pbox = pboxInit; + + #ifdef POLYSEGMENT + x1 = pSeg->x1 + xorg; + y1 = pSeg->y1 + yorg; + x2 = pSeg->x2 + xorg; + y2 = pSeg->y2 + yorg; + pSeg++; + #else + x1 = x2; + y1 = y2; + ++ppt; + if (mode == CoordModePrevious) + { + xorg = x1; + yorg = y1; + } + x2 = ppt->x + xorg; + y2 = ppt->y + yorg; + #endif + + CalcLineDeltas(x1, y1, x2, y2, adx, ady, signdx, signdy, + 1, 1, octant); + + if(!(adx | ady)) continue; + + if(!UseTwoPointLine) { + if (adx > ady) + { + e1 = ady << 1; + e2 = e1 - (adx << 1); + e = e1 - adx; + } + else + { + e1 = adx << 1; + e2 = e1 - (ady << 1); + e = e1 - ady; + SetYMajorOctant(octant); + } + + FIXUP_ERROR(e, octant, bias); + } + + /* we have bresenham parameters and two points. + all we have to do now is clip and draw. + */ + + while(nbox--) + { + oc1 = 0; + oc2 = 0; + OUTCODES(oc1, x1, y1, pbox); + OUTCODES(oc2, x2, y2, pbox); + if ((oc1 | oc2) == 0) + { + if (UseTwoPointLine) { + #ifdef POLYSEGMENT + xf86AccelInfoRec.SubsequentDashedTwoPointLine( + x1, y1, x2, y2, + (bias | pGC->capStyle == CapNotLast ? 0x100 : 0), + PatternOffset); + #else + xf86AccelInfoRec.SubsequentDashedTwoPointLine( + x1, y1, x2, y2, bias, PatternOffset); + #endif + break; + } + if (!(octant & YMAJOR)) + len = adx; + else + len = ady; + #ifdef POLYSEGMENT + if (pGC->capStyle != CapNotLast) + len++; + #endif + xf86AccelInfoRec.SubsequentDashedBresenhamLine(x1, y1, + octant, e, e1, e2, len, PatternOffset); + + break; + } + else if (oc1 & oc2) + { + pbox++; + } + else if (xf86AccelInfoRec.Flags & HARDWARE_CLIP_LINE) { + xf86AccelInfoRec.SetClippingRectangle( + pbox->x1, pbox->y1, pbox->x2 - 1, pbox->y2 - 1); + if (UseTwoPointLine) { + #ifdef POLYSEGMENT + /* + * Note: Two-point lines may not support + * CapNotLast, in which case I don't think + * PolySegment can use TwoPointLine with + * CapNotLast set. + */ + xf86AccelInfoRec.SubsequentDashedTwoPointLine( + x1, y1, x2, y2, bias | + (pGC->capStyle == CapNotLast ? 0x100 : 0), + PatternOffset); + #else + xf86AccelInfoRec.SubsequentDashedTwoPointLine( + x1, y1, x2, y2, bias, PatternOffset); + #endif + } else { + if (!(octant & YMAJOR)) + len = adx; + else + len = ady; + #ifdef POLYSEGMENT + if (pGC->capStyle != CapNotLast) + len++; + #endif + xf86AccelInfoRec.SubsequentDashedBresenhamLine(x1, y1, + octant, e, e1, e2, len, PatternOffset); + } + pbox++; + } + else + { + int new_x1 = x1, new_y1 = y1, new_x2 = x2, new_y2 = y2; + int clip1 = 0, clip2 = 0; + int clipdx, clipdy; + int err; + + /* + * If we were to support software clipping with + * two point lines, we would have to use + * CalculateLineDeltas() now. + */ + if (miZeroClipLine(pbox->x1, pbox->y1, pbox->x2-1, + pbox->y2-1, + &new_x1, &new_y1, &new_x2, &new_y2, + adx, ady, &clip1, &clip2, + octant, bias, oc1, oc2) == -1) + { + pbox++; + continue; + } + + if (!(octant & YMAJOR)) + len = abs(new_x2 - new_x1); + else + len = abs(new_y2 - new_y1); + #ifdef POLYSEGMENT + if (clip2 != 0 || pGC->capStyle != CapNotLast) + len++; + #else + len += (clip2 != 0); + #endif + if (len) + { + int offset; + + /* unwind bresenham error term to first point */ + if (clip1) + { + int range; + clipdx = abs(new_x1 - x1); + clipdy = abs(new_y1 - y1); + /* + * XXX This new error term is probably + * too big to be handled. + */ + if (!(octant & YMAJOR)) + err = e+((clipdy*e2) + ((clipdx-clipdy)*e1)); + else + err = e+((clipdx*e2) + ((clipdy-clipdx)*e1)); + /* + * Rescale the error terms. + */ + #define nbits xf86AccelInfoRec.ErrorTermBits + range = 1 << nbits; + if (abs(err) >= range + || abs(e1) >= range || abs(e2) >= range) { + int div; + if (abs(err) > abs(e1)) + div = (abs(err) > abs(e2)) ? + (abs(err) + range - 1) >> nbits : + (abs(e2) + range - 1) >> nbits; + else + div = (abs(e1) > abs(e2)) ? + (abs(e1) + range - 1) >> nbits : + (abs(e2) + range - 1) >> nbits; + err /= div; + e1 /= div; + e2 /= div; + } + } + else + err = e; + + if(octant & YMAJOR) + offset = abs(new_y1 - y1); + else + offset = abs(new_x1 - x1); + + offset += PatternOffset; + offset %= PatternLength; + + xf86AccelInfoRec.SubsequentDashedBresenhamLine( + new_x1, new_y1, octant, err, e1, e2, + len, offset); + + } + pbox++; + } + } /* while (nbox--) */ + + #ifndef POLYSEGMENT + PatternOffset += (octant & YMAJOR) ? ady : adx; + PatternOffset %= PatternLength; + #endif + + } /* while (nline--) */ + + #ifndef POLYSEGMENT + /* paint the last point if the end style isn't CapNotLast. + (Assume that a projecting, butt, or round cap that is one + pixel wide is the same as the single pixel of the endpoint.) + */ + + if ((pGC->capStyle != CapNotLast) && + ((ppt->x + xorg != pptInit->x + pDrawable->x) || + (ppt->y + yorg != pptInit->y + pDrawable->y) || + (ppt == pptInit + 1))) + { + nbox = nboxInit; + pbox = pboxInit; + while (nbox--) + { + if ((x2 >= pbox->x1) && + (y2 >= pbox->y1) && + (x2 < pbox->x2) && + (y2 < pbox->y2)) + { + if(UseTwoPointLine) + xf86AccelInfoRec.SubsequentDashedTwoPointLine( + x2, y2, x2, y2, 0, PatternOffset); + else + xf86AccelInfoRec.SubsequentDashedBresenhamLine( + x2, y2, YMAJOR, -1, 0, -2, 1, PatternOffset); + break; + } + else + pbox++; + } + } + #endif + if (xf86AccelInfoRec.Flags & BACKGROUND_OPERATIONS) + xf86AccelInfoRec.Sync(); + } + *** /dev/null Tue Jun 30 15:23:24 1998 --- xc/programs/Xserver/hw/xfree86/xaa/xf86dseg.c Sat Mar 7 17:12:38 1998 *************** *** 0 **** --- 1,467 ---- + /* $TOG: xf86dseg.c /main/2 1998/03/07 17:14:19 kaleb $ */ + + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/xaa/xf86dseg.c,v 3.8.2.1 1998/02/01 16:42:15 robin Exp $ */ + + /*********************************************************** + + Copyright (c) 1987 X Consortium + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name of the X Consortium shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the X Consortium. + + + Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + + Permission to use, copy, modify, and distribute this software and its + documentation for any purpose and without fee is hereby granted, + provided that the above copyright notice appear in all copies and that + both that copyright notice and this permission notice appear in + supporting documentation, and that the name of Digital not be + used in advertising or publicity pertaining to distribution of the + software without specific, written prior permission. + + DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING + ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL + DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR + ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, + WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, + ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS + SOFTWARE. + + ******************************************************************/ + /* $TOG: xf86dseg.c /main/2 1998/03/07 17:14:19 kaleb $ */ + /* $XFree86: xc/programs/Xserver/hw/xfree86/xaa/xf86dseg.c,v 3.8.2.1 1998/02/01 16:42:15 robin Exp $ */ + + /* + * Accelerated dashed lines. + * Adapted from xf86line.c by Mark Vojkovich (mvojkovi@ucsd.edu). + * + * The xf86AccelInfoRec.Flags HARDWARE_CLIP_LINE flag indicates that + * lines are clipped by the hardware. In that case, SetClippingRectangle + * must be defined. + * + * At the moment, when software clipping is used the Bresenham error term + * gets to large, at which point it is scaled. The precision is taken + * from xf86AccelInfoRec.ErrorTermBits. + */ + + + #include "X.h" + #include "Xmd.h" + + #include "gcstruct.h" + #include "windowstr.h" + #include "pixmapstr.h" + #include "regionstr.h" + #include "scrnintstr.h" + #include "mistruct.h" + /* PSZ doesn't matter. */ + #define PSZ 8 + #include "cfb.h" + #include "miline.h" + + #include "xf86.h" + #include "xf86xaa.h" + #include "xf86local.h" + #include "xf86Priv.h" + + #define POLYSEGMENT + + void + #ifdef POLYSEGMENT + xf86PolyDashedSegment(pDrawable, pGC, nseg, pSeg) + DrawablePtr pDrawable; + GCPtr pGC; + int nseg; + register xSegment *pSeg; + #else + xf86PolyDashedLine(pDrawable, pGC, mode, npt, pptInit) + DrawablePtr pDrawable; + GCPtr pGC; + int mode; /* Origin or Previous */ + int npt; /* number of points */ + DDXPointPtr pptInit; + #endif + { + int nboxInit; + register int nbox; + BoxPtr pboxInit; + register BoxPtr pbox; + #ifndef POLYSEGMENT + register DDXPointPtr ppt; /* pointer to list of translated points */ + #endif + + unsigned int oc1; /* outcode of point 1 */ + unsigned int oc2; /* outcode of point 2 */ + + int xorg, yorg; /* origin of window */ + + int adx; /* abs values of dx and dy */ + int ady; + int e, e1, e2; /* bresenham error and increments */ + int len; /* length of segment */ + unsigned int bias = miGetZeroLineBias(pDrawable->pScreen); + Bool EvenDash = TRUE; + int signdx, signdy, octant; + + /* a bunch of temporaries */ + int tmp; + register int y1, y2; + register int x1, x2; + RegionPtr cclip; + cfbPrivGCPtr devPriv; + int PatternOffset; + int PatternLength; + Bool UseTwoPointLine = (xf86AccelInfoRec.Flags & USE_TWO_POINT_LINE); + + if (((xf86AccelInfoRec.Flags & LINE_PATTERN_ONLY_TRANSPARENCY) && + (pGC->lineStyle == LineDoubleDash)) || + !(PatternLength = xf86PackDashPattern(pGC))) { + #ifdef POLYSEGMENT + switch (xf86bpp) { + case 8: + #ifdef VGA256 + vga256SegmentSD(pDrawable, pGC, nseg, pSeg); + #else + cfbSegmentSD(pDrawable, pGC, nseg, pSeg); + #endif + break; + case 16: + cfb16SegmentSD(pDrawable, pGC, nseg, pSeg); + break; + #if 0 + case 24: + cfb24SegmentSD(pDrawable, pGC, nseg, pSeg); + break; + #endif + case 32: + cfb32SegmentSD(pDrawable, pGC, nseg, pSeg); + break; + } + #else + switch (xf86bpp) { + case 8: + #ifdef VGA256 + cfbLineSD(pDrawable, pGC, mode, npt, pptInit); + #else + vga256LineSD(pDrawable, pGC, mode, npt, pptInit); + #endif + break; + case 16: + cfb16LineSD(pDrawable, pGC, mode, npt, pptInit); + break; + #if 0 + case 24: + cfb24LineSD(pDrawable, pGC, mode, npt, pptInit); + break; + #endif + case 32: + cfb32LineSD(pDrawable, pGC, mode, npt, pptInit); + break; + } + #endif + return; + } + + PatternOffset = pGC->dashOffset % PatternLength; + + + devPriv = cfbGetGCPrivate(pGC); + cclip = devPriv->pCompositeClip; + pboxInit = REGION_RECTS(cclip); + nboxInit = REGION_NUM_RECTS(cclip); + + + xf86AccelInfoRec.SetupForDashedLine(pGC->fgPixel, + (pGC->lineStyle == LineDoubleDash) ? pGC->bgPixel : -1, + pGC->alu, pGC->planemask, PatternLength); + + + xorg = pDrawable->x; + yorg = pDrawable->y; + #ifdef POLYSEGMENT + while (nseg--) + #else + ppt = pptInit; + x2 = ppt->x + xorg; + y2 = ppt->y + yorg; + while(--npt) + #endif + { + nbox = nboxInit; + pbox = pboxInit; + + #ifdef POLYSEGMENT + x1 = pSeg->x1 + xorg; + y1 = pSeg->y1 + yorg; + x2 = pSeg->x2 + xorg; + y2 = pSeg->y2 + yorg; + pSeg++; + #else + x1 = x2; + y1 = y2; + ++ppt; + if (mode == CoordModePrevious) + { + xorg = x1; + yorg = y1; + } + x2 = ppt->x + xorg; + y2 = ppt->y + yorg; + #endif + + CalcLineDeltas(x1, y1, x2, y2, adx, ady, signdx, signdy, + 1, 1, octant); + + if(!(adx | ady)) continue; + + if(!UseTwoPointLine) { + if (adx > ady) + { + e1 = ady << 1; + e2 = e1 - (adx << 1); + e = e1 - adx; + } + else + { + e1 = adx << 1; + e2 = e1 - (ady << 1); + e = e1 - ady; + SetYMajorOctant(octant); + } + + FIXUP_ERROR(e, octant, bias); + } + + /* we have bresenham parameters and two points. + all we have to do now is clip and draw. + */ + + while(nbox--) + { + oc1 = 0; + oc2 = 0; + OUTCODES(oc1, x1, y1, pbox); + OUTCODES(oc2, x2, y2, pbox); + if ((oc1 | oc2) == 0) + { + if (UseTwoPointLine) { + #ifdef POLYSEGMENT + xf86AccelInfoRec.SubsequentDashedTwoPointLine( + x1, y1, x2, y2, + bias | (pGC->capStyle == CapNotLast ? 0x100 : 0), + PatternOffset); + #else + xf86AccelInfoRec.SubsequentDashedTwoPointLine( + x1, y1, x2, y2, bias, PatternOffset); + #endif + break; + } + if (!(octant & YMAJOR)) + len = adx; + else + len = ady; + #ifdef POLYSEGMENT + if (pGC->capStyle != CapNotLast) + len++; + #endif + xf86AccelInfoRec.SubsequentDashedBresenhamLine(x1, y1, + octant, e, e1, e2, len, PatternOffset); + + break; + } + else if (oc1 & oc2) + { + pbox++; + } + else if (xf86AccelInfoRec.Flags & HARDWARE_CLIP_LINE) { + xf86AccelInfoRec.SetClippingRectangle( + pbox->x1, pbox->y1, pbox->x2 - 1, pbox->y2 - 1); + if (UseTwoPointLine) { + #ifdef POLYSEGMENT + /* + * Note: Two-point lines may not support + * CapNotLast, in which case I don't think + * PolySegment can use TwoPointLine with + * CapNotLast set. + */ + xf86AccelInfoRec.SubsequentDashedTwoPointLine( + x1, y1, x2, y2, bias | + (pGC->capStyle == CapNotLast ? 0x100 : 0), + PatternOffset); + #else + xf86AccelInfoRec.SubsequentDashedTwoPointLine( + x1, y1, x2, y2, bias, PatternOffset); + #endif + } else { + if (!(octant & YMAJOR)) + len = adx; + else + len = ady; + #ifdef POLYSEGMENT + if (pGC->capStyle != CapNotLast) + len++; + #endif + xf86AccelInfoRec.SubsequentDashedBresenhamLine(x1, y1, + octant, e, e1, e2, len, PatternOffset); + } + pbox++; + } + else + { + int new_x1 = x1, new_y1 = y1, new_x2 = x2, new_y2 = y2; + int clip1 = 0, clip2 = 0; + int clipdx, clipdy; + int err; + + /* + * If we were to support software clipping with + * two point lines, we would have to use + * CalculateLineDeltas() now. + */ + if (miZeroClipLine(pbox->x1, pbox->y1, pbox->x2-1, + pbox->y2-1, + &new_x1, &new_y1, &new_x2, &new_y2, + adx, ady, &clip1, &clip2, + octant, bias, oc1, oc2) == -1) + { + pbox++; + continue; + } + + if (!(octant & YMAJOR)) + len = abs(new_x2 - new_x1); + else + len = abs(new_y2 - new_y1); + #ifdef POLYSEGMENT + if (clip2 != 0 || pGC->capStyle != CapNotLast) + len++; + #else + len += (clip2 != 0); + #endif + if (len) + { + int offset; + + /* unwind bresenham error term to first point */ + if (clip1) + { + int range; + clipdx = abs(new_x1 - x1); + clipdy = abs(new_y1 - y1); + /* + * XXX This new error term is probably + * too big to be handled. + */ + if (!(octant & YMAJOR)) + err = e+((clipdy*e2) + ((clipdx-clipdy)*e1)); + else + err = e+((clipdx*e2) + ((clipdy-clipdx)*e1)); + /* + * Rescale the error terms. + */ + #define nbits xf86AccelInfoRec.ErrorTermBits + range = 1 << nbits; + if (abs(err) >= range + || abs(e1) >= range || abs(e2) >= range) { + int div; + if (abs(err) > abs(e1)) + div = (abs(err) > abs(e2)) ? + (abs(err) + range - 1) >> nbits : + (abs(e2) + range - 1) >> nbits; + else + div = (abs(e1) > abs(e2)) ? + (abs(e1) + range - 1) >> nbits : + (abs(e2) + range - 1) >> nbits; + err /= div; + e1 /= div; + e2 /= div; + } + } + else + err = e; + + if(octant & YMAJOR) + offset = abs(new_y1 - y1); + else + offset = abs(new_x1 - x1); + + offset += PatternOffset; + offset %= PatternLength; + + xf86AccelInfoRec.SubsequentDashedBresenhamLine( + new_x1, new_y1, octant, err, e1, e2, + len, offset); + + } + pbox++; + } + } /* while (nbox--) */ + + #ifndef POLYSEGMENT + PatternOffset += (octant & YMAJOR) ? ady : adx; + PatternOffset %= PatternLength; + #endif + + } /* while (nline--) */ + + #ifndef POLYSEGMENT + /* paint the last point if the end style isn't CapNotLast. + (Assume that a projecting, butt, or round cap that is one + pixel wide is the same as the single pixel of the endpoint.) + */ + + if ((pGC->capStyle != CapNotLast) && + ((ppt->x + xorg != pptInit->x + pDrawable->x) || + (ppt->y + yorg != pptInit->y + pDrawable->y) || + (ppt == pptInit + 1))) + { + nbox = nboxInit; + pbox = pboxInit; + while (nbox--) + { + if ((x2 >= pbox->x1) && + (y2 >= pbox->y1) && + (x2 < pbox->x2) && + (y2 < pbox->y2)) + { + if(UseTwoPointLine) + xf86AccelInfoRec.SubsequentDashedTwoPointLine( + x2, y2, x2, y2, 0, PatternOffset); + else + xf86AccelInfoRec.SubsequentDashedBresenhamLine( + x2, y2, YMAJOR, -1, 0, -2, 1, PatternOffset); + break; + } + else + pbox++; + } + } + #endif + if (xf86AccelInfoRec.Flags & BACKGROUND_OPERATIONS) + xf86AccelInfoRec.Sync(); + } + *** ./xfree86/xaa/xf86expblt.c@@/PUBLIC-LATEST Sun Aug 10 13:07:30 1997 --- xc/programs/Xserver/hw/xfree86/xaa/xf86expblt.c Fri Mar 6 16:56:32 1998 *************** *** 1,8 **** ! /* $TOG: xf86expblt.c /main/2 1997/08/10 13:06:05 kaleb $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/xaa/xf86expblt.c,v 3.8.2.4 1997/07/26 06:30:58 dawes Exp $ */ /* * Copyright 1996 The XFree86 Project --- 1,8 ---- ! /* $TOG: xf86expblt.c /main/3 1998/03/06 16:58:10 kaleb $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/xaa/xf86expblt.c,v 3.8.2.5 1998/02/01 16:05:20 robin Exp $ */ /* * Copyright 1996 The XFree86 Project *************** *** 492,497 **** --- 492,498 ---- static unsigned int *DrawTextScanlineWidth8(); unsigned int *DrawTextScanlineWidth8P(); unsigned int *DrawTextScanlineWidth8PMSBFirst(); + static unsigned int *DrawTextScanlineWidth9(); static unsigned int *DrawTextScanlineWidth10(); static unsigned int *DrawTextScanlineWidth12(); static unsigned int *DrawTextScanlineWidth14(); *************** *** 529,535 **** #else DrawTextScanlineWidth8, #endif ! NULL, DrawTextScanlineWidth10, NULL, DrawTextScanlineWidth12, NULL, DrawTextScanlineWidth14, NULL, DrawTextScanlineWidth16, NULL, DrawTextScanlineWidth18, NULL, NULL, NULL, NULL, NULL, DrawTextScanlineWidth24, --- 530,536 ---- #else DrawTextScanlineWidth8, #endif ! DrawTextScanlineWidth9, DrawTextScanlineWidth10, NULL, DrawTextScanlineWidth12, NULL, DrawTextScanlineWidth14, NULL, DrawTextScanlineWidth16, NULL, DrawTextScanlineWidth18, NULL, NULL, NULL, NULL, NULL, DrawTextScanlineWidth24, *************** *** 540,546 **** #if defined(MSBFIRST) && !defined(FIXEDBASE) /* This one needs to be defined only once. */ int glyphwidth_stretchsize[32] = { ! 0, 0, 0, 0, 0, 16, 0, 8, 0, 16, 0, 8, 0, 16, 0, 8, 0, 16, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0 }; #else --- 541,547 ---- #if defined(MSBFIRST) && !defined(FIXEDBASE) /* This one needs to be defined only once. */ int glyphwidth_stretchsize[32] = { ! 0, 0, 0, 0, 0, 16, 0, 8, 32, 16, 0, 8, 0, 16, 0, 8, 0, 16, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0 }; #else *************** *** 547,552 **** --- 548,598 ---- extern int glyphwidth_stretchsize[32]; #endif + + #if defined(__GNUC__) && defined(__i386__) + #ifdef FIXEDBASE + #ifdef MSBFIRST + #define WRITE_BITS() *base = reverse_bitorder(bits) + #else + #define WRITE_BITS() *base = bits + #endif + #else + #ifdef MSBFIRST + #define WRITE_BITS() *(base++) = reverse_bitorder(bits) + #else + #define WRITE_BITS() *(base++) = bits + #endif + #endif + #else /* If no (gcc on i386), don't use reverse_bitorder */ + #ifdef FIXEDBASE + #ifdef MSBFIRST + #define WRITE_BITS() \ + { unsigned data2; \ + data2 = byte_reversed[bits & 0xFF]; \ + data2 |= byte_reversed[(bits & 0xFF00) >> 8] << 8; \ + data2 |= byte_reversed[(bits & 0xFF0000) >> 16] << 16; \ + data2 |= byte_reversed[(bits & 0xFF000000) >> 24] << 24; \ + *(base) = data2; \ + } + #else + #define WRITE_BITS() *base = bits + #endif + #else + #ifdef MSBFIRST + #define WRITE_BITS() \ + { unsigned data2; \ + data2 = byte_reversed[bits & 0xFF]; \ + data2 |= byte_reversed[(bits & 0xFF00) >> 8] << 8; \ + data2 |= byte_reversed[(bits & 0xFF0000) >> 16] << 16; \ + data2 |= byte_reversed[(bits & 0xFF000000) >> 24] << 24; \ + *(base++) = data2; \ + } + #else + #define WRITE_BITS() *(base++) = bits + #endif + #endif + #endif /* (gcc on i386) */ + unsigned int *xf86DrawTextScanline(base, glyphp, line, nglyph, glyphwidth) unsigned int *base; unsigned int **glyphp; *************** *** 554,559 **** --- 600,640 ---- int nglyph; int glyphwidth; { + register CARD32 bits; + register int shift; + int count = 0; + + if (glyphwidth_stretchsize[glyphwidth - 1] && + glyphwidth_stretchsize[glyphwidth - 1] <= nglyph) { + base = (*glyphwidth_function[glyphwidth - 1])(base, glyphp, line, + nglyph); + count = nglyph - + (nglyph & (glyphwidth_stretchsize[glyphwidth - 1] - 1)); + } + + for(bits = 0, shift = 0;count < nglyph; count++) { + bits |= glyphp[count][line] << shift; + shift += glyphwidth; + if(shift & ~31) { + WRITE_BITS(); + shift &= 31; + bits = glyphp[count][line] >> (glyphwidth - shift); + } + } + if(shift) WRITE_BITS(); + + return base; + } + + #if 0 + /* this is the old code, new code is above (MArk) */ + unsigned int *xf86DrawTextScanline(base, glyphp, line, nglyph, glyphwidth) + unsigned int *base; + unsigned int **glyphp; + int line; + int nglyph; + int glyphwidth; + { UINT64_DECLARE(bits); int shift, i; *************** *** 598,603 **** --- 679,686 ---- return base; } + #endif + /* * This function does not transfer one scanline worth of bits like all the * other ones, but instead transfers the whole bitmap (padded to a DWORD *************** *** 927,932 **** --- 1010,1081 ---- WRITE_IN_BITORDER(base, 1, bits); return base + 2; #endif + return base; + } + + static unsigned int *DrawTextScanlineWidth9(base, glyphp, line, nglyph) + unsigned int *base; + unsigned int **glyphp; + int line; + int nglyph; + { + while (nglyph >= 32) { + unsigned int bits; + bits = glyphp[0][line]; + bits |= glyphp[1][line] << 9; + bits |= glyphp[2][line] << 18; + bits |= glyphp[3][line] << 27; + WRITE_IN_BITORDER(base, 0, bits); + bits = glyphp[3][line] >> 5; + bits |= glyphp[4][line] << 4; + bits |= glyphp[5][line] << 13; + bits |= glyphp[6][line] << 22; + bits |= glyphp[7][line] << 31; + WRITE_IN_BITORDER(base, 1, bits); + bits = glyphp[7][line] >> 1; + bits |= glyphp[8][line] << 8; + bits |= glyphp[9][line] << 17; + bits |= glyphp[10][line] << 26; + WRITE_IN_BITORDER(base, 2, bits); + bits = glyphp[10][line] >> 6; + bits |= glyphp[11][line] << 3; + bits |= glyphp[12][line] << 12; + bits |= glyphp[13][line] << 21; + bits |= glyphp[14][line] << 30; + WRITE_IN_BITORDER(base, 3, bits); + bits = glyphp[14][line] >> 2; + bits |= glyphp[15][line] << 7; + bits |= glyphp[16][line] << 16; + bits |= glyphp[17][line] << 25; + WRITE_IN_BITORDER(base, 4, bits); + bits = glyphp[17][line] >> 7; + bits |= glyphp[18][line] << 2; + bits |= glyphp[19][line] << 11; + bits |= glyphp[20][line] << 20; + bits |= glyphp[21][line] << 29; + WRITE_IN_BITORDER(base, 5, bits); + bits = glyphp[21][line] >> 3; + bits |= glyphp[22][line] << 6; + bits |= glyphp[23][line] << 15; + bits |= glyphp[24][line] << 24; + WRITE_IN_BITORDER(base, 6, bits); + bits = glyphp[24][line] >> 8; + bits |= glyphp[25][line] << 1; + bits |= glyphp[26][line] << 10; + bits |= glyphp[27][line] << 19; + bits |= glyphp[28][line] << 28; + WRITE_IN_BITORDER(base, 7, bits); + bits = glyphp[28][line] >> 4; + bits |= glyphp[29][line] << 5; + bits |= glyphp[30][line] << 14; + bits |= glyphp[31][line] << 23; + WRITE_IN_BITORDER(base, 8, bits); + #ifndef FIXEDBASE + base += 9; + #endif + nglyph -= 32; + glyphp += 32; + } return base; } *** ./xfree86/xaa/xf86fpoly.c@@/PUBLIC-LATEST Sat Jul 19 10:59:51 1997 --- xc/programs/Xserver/hw/xfree86/xaa/xf86fpoly.c Fri Mar 6 16:56:38 1998 *************** *** 1,9 **** ! /* $TOG: xf86fpoly.c /main/1 1997/07/19 10:59:52 kaleb $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/xaa/xf86fpoly.c,v 3.0 1996/11/18 13:22:17 dawes Exp $ */ ! /* * Copyright 1996 The XFree86 Project * --- 1,8 ---- ! /* $TOG: xf86fpoly.c /main/2 1998/03/06 16:58:15 kaleb $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/xaa/xf86fpoly.c,v 3.0.2.2 1998/02/21 06:07:09 robin Exp $ */ /* * Copyright 1996 The XFree86 Project * *************** *** 54,59 **** --- 53,110 ---- #include "xf86xaa.h" + #define Setup(c,x,vertex,dx,dy,e,sign,step,DX) {\ + x = intToX(vertex); \ + if (dy = intToY(c) - y) { \ + DX = dx = intToX(c) - x; \ + step = 0; \ + if (dx >= 0) \ + { \ + e = 0; \ + sign = 1; \ + if (dx >= dy) {\ + step = dx / dy; \ + dx %= dy; \ + } \ + } \ + else \ + { \ + e = 1 - dy; \ + sign = -1; \ + dx = -dx; \ + if (dx >= dy) { \ + step = - (dx / dy); \ + dx %= dy; \ + } \ + } \ + } \ + x += origin; \ + vertex = c; \ + } + + #define Step(x,dx,dy,e,sign,step) {\ + x += step; \ + if ((e += dx) > 0) \ + { \ + x += sign; \ + e -= dy; \ + } \ + } + + #define FixError(x, dx, dy, e, sign, step, h) { \ + e += (h) * dx; \ + x += (h) * step; \ + if(e > 0) { \ + x += e * sign/dy; \ + e %= dy; \ + if(e) { \ + x += sign; \ + e -= dy; \ + } \ + } \ + } + + void xf86FillPolygonSolid1Rect(pDrawable, pGC, shape, mode, count, ptsIn) DrawablePtr pDrawable; *************** *** 64,70 **** DDXPointPtr ptsIn; { cfbPrivGCPtr devPriv; - int nwidth; int maxy; int origin; register int vertex1, vertex2; --- 115,120 ---- *************** *** 82,102 **** int sign1, sign2; int h; int yoffset; if (mode == CoordModePrevious) { ! miFillPolygon (pDrawable, pGC, shape, mode, count, ptsIn); ! return; } devPriv = cfbGetGCPrivate(pGC); - #ifdef NO_ONE_RECT if (REGION_NUM_RECTS(devPriv->pCompositeClip) != 1) { miFillPolygon (pDrawable, pGC, shape, mode, count, ptsIn); return; } ! #endif origin = *((int *) &pDrawable->x); origin -= (origin & 0x8000) << 1; extents = &devPriv->pCompositeClip->extents; --- 132,158 ---- int sign1, sign2; int h; int yoffset; + int DX1, DX2; /* for trapezoid fills */ if (mode == CoordModePrevious) { ! register DDXPointPtr ppt = ptsIn + 1; ! ! for (c = 1; c < count; c++, ppt++) ! { ! ppt->x += (ppt-1)->x; ! ppt->y += (ppt-1)->y; ! } ! mode = CoordModeOrigin; } devPriv = cfbGetGCPrivate(pGC); if (REGION_NUM_RECTS(devPriv->pCompositeClip) != 1) { miFillPolygon (pDrawable, pGC, shape, mode, count, ptsIn); return; } ! origin = *((int *) &pDrawable->x); origin -= (origin & 0x8000) << 1; extents = &devPriv->pCompositeClip->extents; *************** *** 185,228 **** vertex2 = vertex1 = *vertex2p++; if (vertex2p == endp) vertex2p = (int *) ptsIn; - #define Setup(c,x,vertex,dx,dy,e,sign,step) {\ - x = intToX(vertex); \ - if (dy = intToY(c) - y) { \ - dx = intToX(c) - x; \ - step = 0; \ - if (dx >= 0) \ - { \ - e = 0; \ - sign = 1; \ - if (dx >= dy) {\ - step = dx / dy; \ - dx = dx % dy; \ - } \ - } \ - else \ - { \ - e = 1 - dy; \ - sign = -1; \ - dx = -dx; \ - if (dx >= dy) { \ - step = - (dx / dy); \ - dx = dx % dy; \ - } \ - } \ - } \ - x += origin; \ - vertex = c; \ - } - #define Step(x,dx,dy,e,sign,step) {\ - x += step; \ - if ((e += dx) > 0) \ - { \ - x += sign; \ - e -= dy; \ - } \ - } - yoffset = pDrawable->y; for (;;) { --- 241,247 ---- *************** *** 233,239 **** if (vertex1p == (int *) ptsIn) vertex1p = endp; c = *--vertex1p; ! Setup (c,x1,vertex1,dx1,dy1,e1,sign1,step1) } while (y >= intToY(vertex1)); h = dy1; } --- 252,258 ---- if (vertex1p == (int *) ptsIn) vertex1p = endp; c = *--vertex1p; ! Setup (c,x1,vertex1,dx1,dy1,e1,sign1,step1,DX1) } while (y >= intToY(vertex1)); h = dy1; } *************** *** 249,255 **** c = *vertex2p++; if (vertex2p == endp) vertex2p = (int *) ptsIn; ! Setup (c,x2,vertex2,dx2,dy2,e2,sign2,step2) } while (y >= intToY(vertex2)); if (dy2 < h) h = dy2; --- 268,274 ---- c = *vertex2p++; if (vertex2p == endp) vertex2p = (int *) ptsIn; ! Setup (c,x2,vertex2,dx2,dy2,e2,sign2,step2,DX2) } while (y >= intToY(vertex2)); if (dy2 < h) h = dy2; *************** *** 260,283 **** if ((c = (intToY(vertex2) - y)) < h) h = c; } /* fill spans for this segment */ ! for (;;) { if (x2 > x1) xf86AccelInfoRec.SubsequentFillRectSolid( ! x1, y + yoffset, x2 - x1, 1); else if (x1 > x2) xf86AccelInfoRec.SubsequentFillRectSolid( ! x2, y + yoffset, x1 - x2, 1); ! y++; ! if (!--h) ! break; ! Step(x1,dx1,dy1,e1,sign1,step1) ! Step(x2,dx2,dy2,e2,sign2,step2) ! } if (y == maxy) break; } if (xf86AccelInfoRec.Flags & BACKGROUND_OPERATIONS) xf86AccelInfoRec.Sync(); } --- 279,346 ---- if ((c = (intToY(vertex2) - y)) < h) h = c; } + /* fill spans for this segment */ ! if(DX1 | DX2) { ! if(xf86AccelInfoRec.SubsequentFillTrapezoidSolid && (h > 6)) { ! if(x1 == x2) { ! while(x1 == x2) { ! y++; ! if (!--h) ! break; ! Step(x1,dx1,dy1,e1,sign1,step1) ! Step(x2,dx2,dy2,e2,sign2,step2) ! } ! if(y == maxy) break; ! if(!h) continue; ! } ! ! if(x1 < x2) ! xf86AccelInfoRec.SubsequentFillTrapezoidSolid(y + yoffset, h, ! x1, DX1, dy1, e1, ! x2 - 1, DX2, dy2, e2); ! else ! xf86AccelInfoRec.SubsequentFillTrapezoidSolid(y + yoffset, h, ! x2, DX2, dy2, e2, ! x1 - 1, DX1, dy1, e1); ! y += h; ! if(--h) { ! FixError(x1,dx1,dy1,e1,sign1,step1,h); ! FixError(x2,dx2,dy2,e2,sign2,step2,h); ! h = 0; ! } ! } else { ! for (;;) { ! if (x2 > x1) ! xf86AccelInfoRec.SubsequentFillRectSolid( ! x1, y + yoffset, x2 - x1, 1); ! else ! if (x1 > x2) ! xf86AccelInfoRec.SubsequentFillRectSolid( ! x2, y + yoffset, x1 - x2, 1); ! y++; ! if (!--h) ! break; ! Step(x1,dx1,dy1,e1,sign1,step1) ! Step(x2,dx2,dy2,e2,sign2,step2) ! } ! } ! } else { if (x2 > x1) xf86AccelInfoRec.SubsequentFillRectSolid( ! x1, y + yoffset, x2 - x1, h); else if (x1 > x2) xf86AccelInfoRec.SubsequentFillRectSolid( ! x2, y + yoffset, x1 - x2, h); ! ! y += h; ! h = 0; ! } if (y == maxy) break; } + if (xf86AccelInfoRec.Flags & BACKGROUND_OPERATIONS) xf86AccelInfoRec.Sync(); } *** ./xfree86/xaa/xf86gcmisc.c@@/PUBLIC-LATEST Tue Nov 11 15:48:06 1997 --- xc/programs/Xserver/hw/xfree86/xaa/xf86gcmisc.c Fri Mar 6 16:56:42 1998 *************** *** 1,8 **** ! /* $TOG: xf86gcmisc.c /main/2 1997/11/11 15:48:08 msr $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/xaa/xf86gcmisc.c,v 3.7.2.3 1997/05/17 12:25:21 dawes Exp $ */ /* * Copyright 1996 The XFree86 Project --- 1,8 ---- ! /* $TOG: xf86gcmisc.c /main/3 1998/03/06 16:58:19 kaleb $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/xaa/xf86gcmisc.c,v 3.7.2.4 1998/02/01 16:05:21 robin Exp $ */ /* * Copyright 1996 The XFree86 Project *************** *** 51,56 **** --- 51,57 ---- #include "fontstruct.h" #include "dixfontstr.h" #include "mi.h" + #include "mispans.h" #ifdef VGA256 /* *************** *** 250,281 **** break; } } /* endif new_cfb_line */ ! if (xf86GCInfoRec.PolyLineSolidZeroWidth && ! pGC->lineStyle == LineSolid && ! pGC->fillStyle == FillSolid && ! pGC->lineWidth == 0 && #if !defined(NO_ONE_RECT) ! (!(xf86GCInfoRec.PolyLineSolidZeroWidthFlags & ONE_RECT_CLIPPING) ! || devPriv->oneRect) && #endif ! CHECKPLANEMASK(xf86GCInfoRec.PolyLineSolidZeroWidthFlags) && ! CHECKROP(xf86GCInfoRec.PolyLineSolidZeroWidthFlags) && ! CHECKRGBEQUAL(xf86GCInfoRec.PolyLineSolidZeroWidthFlags)) ! PolyLineFunc = xf86GCInfoRec.PolyLineSolidZeroWidth; ! if (xf86GCInfoRec.PolySegmentSolidZeroWidth && ! pGC->lineStyle == LineSolid && ! pGC->fillStyle == FillSolid && ! pGC->lineWidth == 0 && #if !defined(NO_ONE_RECT) ! (!(xf86GCInfoRec.PolyLineSolidZeroWidthFlags & ONE_RECT_CLIPPING) ! || devPriv->oneRect) && #endif ! CHECKPLANEMASK(xf86GCInfoRec.PolySegmentSolidZeroWidthFlags) && ! CHECKROP(xf86GCInfoRec.PolySegmentSolidZeroWidthFlags) && ! CHECKRGBEQUAL(xf86GCInfoRec.PolySegmentSolidZeroWidthFlags) && ! (pGC->capStyle != CapNotLast || ! !(xf86GCInfoRec.PolySegmentSolidZeroWidthFlags & NO_CAP_NOT_LAST))) ! PolySegmentFunc = xf86GCInfoRec.PolySegmentSolidZeroWidth; pGC->ops->Polylines = PolyLineFunc; pGC->ops->PolySegment = PolySegmentFunc; } --- 251,320 ---- break; } } /* endif new_cfb_line */ ! ! ! if((pGC->fillStyle == FillSolid) && (pGC->lineWidth == 0)) { ! if(pGC->lineStyle == LineSolid) { ! if(xf86GCInfoRec.PolyLineSolidZeroWidth && #if !defined(NO_ONE_RECT) ! (!(xf86GCInfoRec.PolyLineSolidZeroWidthFlags & ONE_RECT_CLIPPING) ! || devPriv->oneRect) && #endif ! CHECKPLANEMASK(xf86GCInfoRec.PolyLineSolidZeroWidthFlags) && ! CHECKROP(xf86GCInfoRec.PolyLineSolidZeroWidthFlags) && ! CHECKRGBEQUAL(xf86GCInfoRec.PolyLineSolidZeroWidthFlags)) ! PolyLineFunc = xf86GCInfoRec.PolyLineSolidZeroWidth; ! ! ! if (xf86GCInfoRec.PolySegmentSolidZeroWidth && #if !defined(NO_ONE_RECT) ! (!(xf86GCInfoRec.PolyLineSolidZeroWidthFlags & ONE_RECT_CLIPPING) ! || devPriv->oneRect) && #endif ! CHECKPLANEMASK(xf86GCInfoRec.PolySegmentSolidZeroWidthFlags) && ! CHECKROP(xf86GCInfoRec.PolySegmentSolidZeroWidthFlags) && ! CHECKRGBEQUAL(xf86GCInfoRec.PolySegmentSolidZeroWidthFlags) && ! (pGC->capStyle != CapNotLast || ! !(xf86GCInfoRec.PolySegmentSolidZeroWidthFlags & NO_CAP_NOT_LAST))) ! PolySegmentFunc = xf86GCInfoRec.PolySegmentSolidZeroWidth; ! ! } else { ! if(xf86GCInfoRec.PolyLineDashedZeroWidth && ! #if !defined(NO_ONE_RECT) ! (!(xf86GCInfoRec.PolyLineDashedZeroWidthFlags & ONE_RECT_CLIPPING) ! || devPriv->oneRect) && ! #endif ! CHECKPLANEMASK(xf86GCInfoRec.PolyLineDashedZeroWidthFlags) && ! CHECKROP(xf86GCInfoRec.PolyLineDashedZeroWidthFlags) && ! CHECKRGBEQUAL(xf86GCInfoRec.PolyLineDashedZeroWidthFlags)) ! PolyLineFunc = xf86GCInfoRec.PolyLineDashedZeroWidth; ! ! ! if (xf86GCInfoRec.PolySegmentDashedZeroWidth && ! #if !defined(NO_ONE_RECT) ! (!(xf86GCInfoRec.PolySegmentDashedZeroWidthFlags & ONE_RECT_CLIPPING) ! || devPriv->oneRect) && ! #endif ! CHECKPLANEMASK(xf86GCInfoRec.PolySegmentDashedZeroWidthFlags) && ! CHECKROP(xf86GCInfoRec.PolySegmentDashedZeroWidthFlags) && ! CHECKRGBEQUAL(xf86GCInfoRec.PolySegmentDashedZeroWidthFlags) && ! (pGC->capStyle != CapNotLast || ! !(xf86GCInfoRec.PolySegmentDashedZeroWidthFlags & NO_CAP_NOT_LAST))) ! PolySegmentFunc = xf86GCInfoRec.PolySegmentDashedZeroWidth; ! ! } ! } ! #if !defined(NO_ONE_RECT) ! else if((pGC->fillStyle == FillSolid) && (pGC->lineStyle == LineSolid) ! && miSpansEasyRop(pGC->alu)) { ! if (xf86AccelInfoRec.SubsequentFillRectSolid && devPriv->oneRect && ! CHECKPLANEMASK(xf86GCInfoRec.PolyFillRectSolidFlags) && ! CHECKROP(xf86GCInfoRec.PolyFillRectSolidFlags) && ! CHECKRGBEQUAL(xf86GCInfoRec.PolyFillRectSolidFlags)) ! PolyLineFunc = xf86WideLineSolid1Rect; ! } ! #endif ! pGC->ops->Polylines = PolyLineFunc; pGC->ops->PolySegment = PolySegmentFunc; } *** ./xfree86/xaa/xf86initac.c@@/PUBLIC-LATEST Sun Aug 10 13:07:36 1997 --- xc/programs/Xserver/hw/xfree86/xaa/xf86initac.c Fri Mar 6 16:56:46 1998 *************** *** 1,8 **** ! /* $TOG: xf86initac.c /main/2 1997/08/10 13:06:13 kaleb $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/xaa/xf86initac.c,v 3.10.2.5 1997/07/28 14:17:33 dawes Exp $ */ /* * Copyright 1996 The XFree86 Project --- 1,8 ---- ! /* $TOG: xf86initac.c /main/3 1998/03/06 16:58:24 kaleb $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/xaa/xf86initac.c,v 3.10.2.8 1998/02/21 10:47:12 hohndel Exp $ */ /* * Copyright 1996 The XFree86 Project *************** *** 65,83 **** int CPUToScreenColorExpand = FALSE; int ScreenToScreenColorExpand = FALSE; int ScanlineScreenToScreenColorExpand = FALSE; ! if (serverGeneration != 1) goto do_not_touch_xf86AccelInfoRec; - ErrorF("%s %s: Using XAA (XFree86 Acceleration Architecture)\n", - XCONFIG_PROBED, xf86AccelInfoRec.ServerInfoRec->name); - if ((xf86AccelInfoRec.Flags & PIXMAP_CACHE) && OFLG_ISSET(OPTION_NO_PIXMAP_CACHE, &(xf86AccelInfoRec.ServerInfoRec->options))) { xf86AccelInfoRec.Flags &= ~PIXMAP_CACHE; ! ErrorF("%s %s: Pixmap cache disabled\n", XCONFIG_GIVEN, xf86AccelInfoRec.ServerInfoRec->name); } /* --- 65,83 ---- int CPUToScreenColorExpand = FALSE; int ScreenToScreenColorExpand = FALSE; int ScanlineScreenToScreenColorExpand = FALSE; ! char MsgBuf[3200]; /* that's enough for 40 lines */ ! char *MsgPtr = MsgBuf; ! if (serverGeneration != 1) goto do_not_touch_xf86AccelInfoRec; if ((xf86AccelInfoRec.Flags & PIXMAP_CACHE) && OFLG_ISSET(OPTION_NO_PIXMAP_CACHE, &(xf86AccelInfoRec.ServerInfoRec->options))) { xf86AccelInfoRec.Flags &= ~PIXMAP_CACHE; ! sprintf(MsgPtr,"%s %s: Pixmap cache disabled\n", XCONFIG_GIVEN, xf86AccelInfoRec.ServerInfoRec->name); + MsgPtr += strlen(MsgPtr); } /* *************** *** 88,102 **** xf86AccelInfoRec.SubsequentFillRectSolid) { SimpleFillRectSolid = TRUE; if (xf86Verbose) ! ErrorF("%s %s: XAA: Solid filled rectangles\n", XCONFIG_PROBED, xf86AccelInfoRec.ServerInfoRec->name); } if (xf86AccelInfoRec.SetupForScreenToScreenCopy && xf86AccelInfoRec.SubsequentScreenToScreenCopy) { SimpleScreenToScreenCopy = TRUE; if (xf86Verbose) ! ErrorF("%s %s: XAA: Screen-to-screen copy\n", XCONFIG_PROBED, xf86AccelInfoRec.ServerInfoRec->name); } if (xf86AccelInfoRec.SetupForCPUToScreenColorExpand && xf86AccelInfoRec.SubsequentCPUToScreenColorExpand && --- 88,104 ---- xf86AccelInfoRec.SubsequentFillRectSolid) { SimpleFillRectSolid = TRUE; if (xf86Verbose) ! sprintf(MsgPtr,"%s %s: XAA: Solid filled rectangles\n", XCONFIG_PROBED, xf86AccelInfoRec.ServerInfoRec->name); + MsgPtr += strlen(MsgPtr); } if (xf86AccelInfoRec.SetupForScreenToScreenCopy && xf86AccelInfoRec.SubsequentScreenToScreenCopy) { SimpleScreenToScreenCopy = TRUE; if (xf86Verbose) ! sprintf(MsgPtr,"%s %s: XAA: Screen-to-screen copy\n", XCONFIG_PROBED, xf86AccelInfoRec.ServerInfoRec->name); + MsgPtr += strlen(MsgPtr); } if (xf86AccelInfoRec.SetupForCPUToScreenColorExpand && xf86AccelInfoRec.SubsequentCPUToScreenColorExpand && *************** *** 131,161 **** if (xf86AccelInfoRec.SetupForFill8x8Pattern && xf86AccelInfoRec.SubsequentFill8x8Pattern) { if (xf86Verbose) ! ErrorF("%s %s: XAA: 8x8 pattern fill", XCONFIG_PROBED, xf86AccelInfoRec.ServerInfoRec->name); if (((xf86AccelInfoRec.Flags & HARDWARE_PATTERN_ALIGN_64) && !(xf86AccelInfoRec.Flags & HARDWARE_PATTERN_PROGRAMMED_ORIGIN)) || ((xf86AccelInfoRec.Flags & HARDWARE_PATTERN_MOD_64_OFFSET) && ! (xf86AccelInfoRec.FramebufferWidth & 63) != 0)) ! ErrorF(" (not usable)"); ! ErrorF("\n"); } if (xf86AccelInfoRec.SetupFor8x8PatternColorExpand && xf86AccelInfoRec.Subsequent8x8PatternColorExpand) { if (xf86Verbose) ! ErrorF("%s %s: XAA: 8x8 color expand pattern fill\n", XCONFIG_PROBED, xf86AccelInfoRec.ServerInfoRec->name); } ! if (!SimpleFillRectSolid && !SimpleScreenToScreenCopy && !CPUToScreenColorExpand && !ScreenToScreenColorExpand && !ScanlineScreenToScreenColorExpand && !xf86AccelInfoRec.SubsequentTwoPointLine && !xf86AccelInfoRec.SubsequentBresenhamLine && !xf86AccelInfoRec.SubsequentFill8x8Pattern && ! !xf86AccelInfoRec.Subsequent8x8PatternColorExpand) ! ErrorF("%s %s: XAA: No acceleration primitives defined.\n", ! XCONFIG_PROBED, xf86AccelInfoRec.ServerInfoRec->name); /* * Set up the higher-level accelerated functions to make use of --- 133,168 ---- if (xf86AccelInfoRec.SetupForFill8x8Pattern && xf86AccelInfoRec.SubsequentFill8x8Pattern) { if (xf86Verbose) ! sprintf(MsgPtr,"%s %s: XAA: 8x8 pattern fill", XCONFIG_PROBED, xf86AccelInfoRec.ServerInfoRec->name); + MsgPtr += strlen(MsgPtr); if (((xf86AccelInfoRec.Flags & HARDWARE_PATTERN_ALIGN_64) && !(xf86AccelInfoRec.Flags & HARDWARE_PATTERN_PROGRAMMED_ORIGIN)) || ((xf86AccelInfoRec.Flags & HARDWARE_PATTERN_MOD_64_OFFSET) && ! (xf86AccelInfoRec.FramebufferWidth & 63) != 0)) { ! sprintf(MsgPtr," (not usable)"); ! MsgPtr += strlen(MsgPtr); ! } ! sprintf(MsgPtr,"\n"); ! MsgPtr += strlen(MsgPtr); } if (xf86AccelInfoRec.SetupFor8x8PatternColorExpand && xf86AccelInfoRec.Subsequent8x8PatternColorExpand) { if (xf86Verbose) ! sprintf(MsgPtr,"%s %s: XAA: 8x8 color expand pattern fill\n", XCONFIG_PROBED, xf86AccelInfoRec.ServerInfoRec->name); + MsgPtr += strlen(MsgPtr); } ! if (!(!SimpleFillRectSolid && !SimpleScreenToScreenCopy && !CPUToScreenColorExpand && !ScreenToScreenColorExpand && !ScanlineScreenToScreenColorExpand && !xf86AccelInfoRec.SubsequentTwoPointLine && !xf86AccelInfoRec.SubsequentBresenhamLine && !xf86AccelInfoRec.SubsequentFill8x8Pattern && ! !xf86AccelInfoRec.Subsequent8x8PatternColorExpand)) ! ErrorF("%s %s: Using XAA (XFree86 Acceleration Architecture)\n%s", ! XCONFIG_PROBED, xf86AccelInfoRec.ServerInfoRec->name,MsgBuf); /* * Set up the higher-level accelerated functions to make use of *************** *** 261,272 **** if ((!(xf86AccelInfoRec.ColorExpandFlags & ONLY_TRANSPARENCY_SUPPORTED) || SimpleFillRectSolid) && (xf86AccelInfoRec.ColorExpandFlags & SCANLINE_PAD_DWORD)) { ! xf86AccelInfoRec.WriteBitmap = ! xf86WriteBitmapCPUToScreenColorExpand; ! if (xf86Verbose) ! ErrorF("bitmap, "); #ifdef STIPPLE_COLOR_EXPANSION ! if ((xf86AccelInfoRec.ColorExpandFlags & LEFT_EDGE_CLIPPING) && (xf86AccelInfoRec.ColorExpandFlags & LEFT_EDGE_CLIPPING_NEGATIVE_X) && !(xf86AccelInfoRec.ColorExpandFlags & TRIPLE_BITS_24BPP)) { xf86AccelInfoRec.FillRectOpaqueStippled = --- 268,282 ---- if ((!(xf86AccelInfoRec.ColorExpandFlags & ONLY_TRANSPARENCY_SUPPORTED) || SimpleFillRectSolid) && (xf86AccelInfoRec.ColorExpandFlags & SCANLINE_PAD_DWORD)) { ! if(!xf86AccelInfoRec.WriteBitmap) { ! xf86AccelInfoRec.WriteBitmap = ! xf86WriteBitmapCPUToScreenColorExpand; ! if (xf86Verbose) ! ErrorF("bitmap, "); ! } #ifdef STIPPLE_COLOR_EXPANSION ! if (!xf86AccelInfoRec.FillRectOpaqueStippled && ! (xf86AccelInfoRec.ColorExpandFlags & LEFT_EDGE_CLIPPING) && (xf86AccelInfoRec.ColorExpandFlags & LEFT_EDGE_CLIPPING_NEGATIVE_X) && !(xf86AccelInfoRec.ColorExpandFlags & TRIPLE_BITS_24BPP)) { xf86AccelInfoRec.FillRectOpaqueStippled = *************** *** 281,287 **** #endif } #ifdef STIPPLE_COLOR_EXPANSION ! if (!(xf86AccelInfoRec.ColorExpandFlags & NO_TRANSPARENCY) && (xf86AccelInfoRec.ColorExpandFlags & SCANLINE_PAD_DWORD) && (xf86AccelInfoRec.ColorExpandFlags & LEFT_EDGE_CLIPPING) && (xf86AccelInfoRec.ColorExpandFlags & LEFT_EDGE_CLIPPING_NEGATIVE_X) && --- 291,298 ---- #endif } #ifdef STIPPLE_COLOR_EXPANSION ! if (!xf86AccelInfoRec.FillRectStippled && ! !(xf86AccelInfoRec.ColorExpandFlags & NO_TRANSPARENCY) && (xf86AccelInfoRec.ColorExpandFlags & SCANLINE_PAD_DWORD) && (xf86AccelInfoRec.ColorExpandFlags & LEFT_EDGE_CLIPPING) && (xf86AccelInfoRec.ColorExpandFlags & LEFT_EDGE_CLIPPING_NEGATIVE_X) && *************** *** 594,599 **** --- 605,638 ---- ErrorF("%s %s: XAA: Horizontal and vertical lines and segments\n", XCONFIG_PROBED, xf86AccelInfoRec.ServerInfoRec->name); } + } + + if ((xf86AccelInfoRec.SubsequentDashedBresenhamLine + && ((xf86AccelInfoRec.Flags & HARDWARE_CLIP_LINE) || + xf86AccelInfoRec.ErrorTermBits)) + || (xf86AccelInfoRec.SubsequentDashedTwoPointLine + && (xf86AccelInfoRec.Flags & HARDWARE_CLIP_LINE)) && + xf86AccelInfoRec.SetupForDashedLine && + xf86AccelInfoRec.LinePatternBuffer && + (xf86AccelInfoRec.LinePatternMaxLength > 0)) { + if (!xf86GCInfoRec.PolyLineDashedZeroWidth) + xf86GCInfoRec.PolyLineDashedZeroWidth = xf86PolyDashedLine; + if (!xf86GCInfoRec.PolySegmentDashedZeroWidth) + xf86GCInfoRec.PolySegmentDashedZeroWidth = + xf86PolyDashedSegment; + + if (!xf86AccelInfoRec.SubsequentDashedBresenhamLine && + !(xf86AccelInfoRec.Flags & TWO_POINT_LINE_NOT_LAST)) + /* + * If there's only TwoPointLine, and it doesn't support + * skipping of the last pixel, then PolySegment cannot + * be supported with the CapNotLast line style. + */ + xf86GCInfoRec.PolySegmentDashedZeroWidthFlags |= + NO_CAP_NOT_LAST; + if (xf86Verbose) + ErrorF("%s %s: XAA: Dashed lines and segments\n", + XCONFIG_PROBED, xf86AccelInfoRec.ServerInfoRec->name); } do_not_touch_xf86AccelInfoRec: *** ./xfree86/xaa/xf86local.h@@/PUBLIC-LATEST Sat Jul 19 11:00:37 1997 --- xc/programs/Xserver/hw/xfree86/xaa/xf86local.h Fri Mar 6 16:56:51 1998 *************** *** 1,8 **** ! /* $TOG: xf86local.h /main/1 1997/07/19 11:00:39 kaleb $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/xaa/xf86local.h,v 3.6 1997/01/23 11:04:24 dawes Exp $ */ /* Functions that are only referenced from within this directory. */ --- 1,8 ---- ! /* $TOG: xf86local.h /main/2 1998/03/06 16:58:29 kaleb $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/xaa/xf86local.h,v 3.6.2.1 1998/02/01 16:05:24 robin Exp $ */ /* Functions that are only referenced from within this directory. */ *************** *** 538,543 **** --- 538,583 ---- BoxPtr pBoxInit #endif ); + + void + xf86PolyDashedSegment( + #if NeedFunctionPrototypes + DrawablePtr pDrawable, + GCPtr pGC, + int nseg, + xSegment *pSeg + #endif + ); + + void + xf86PolyDashedLine( + #if NeedFunctionPrototypes + DrawablePtr pDrawable, + GCPtr pGC, + int mode, + int npt, + DDXPointPtr pptInit + #endif + ); + + int + xf86PackDashPattern( + #if NeedFunctionPrototypes + GCPtr pGC + #endif + ); + + void + xf86WideLineSolid1Rect ( + #if NeedFunctionPrototypes + DrawablePtr pDrawable, + GCPtr pGC, + int mode, + int npt, + DDXPointPtr pPts + #endif + ); + void xf86Bench(); *** ./xfree86/xaa/xf86pcache.c@@/PUBLIC-LATEST Sat Jul 19 21:23:36 1997 --- xc/programs/Xserver/hw/xfree86/xaa/xf86pcache.c Fri Mar 6 16:56:55 1998 *************** *** 1,8 **** ! /* $TOG: xf86pcache.c /main/2 1997/07/19 21:23:38 kaleb $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/xaa/xf86pcache.c,v 3.9.2.6 1997/05/29 14:01:06 dawes Exp $ */ /* * Copyright 1996 The XFree86 Project --- 1,8 ---- ! /* $TOG: xf86pcache.c /main/3 1998/03/06 16:58:33 kaleb $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/xaa/xf86pcache.c,v 3.9.2.8 1998/02/07 10:05:51 hohndel Exp $ */ /* * Copyright 1996 The XFree86 Project *************** *** 170,189 **** return; } ! if ((MaxHeight < 8) && ! (!(xf86AccelInfoRec.Flags & HARDWARE_PATTERN_PROGRAMMED_ORIGIN))) { ! if ((xf86AccelInfoRec.Flags & HARDWARE_PATTERN_PROGRAMMED_BITS) && ! (xf86AccelInfoRec.SubsequentFill8x8Pattern)) { ! ErrorF("%s %s: XAA: 8x8 Pattern fill disabled - insufficient video memory available\n", ! XCONFIG_PROBED, infoRec->name); ! xf86AccelInfoRec.SubsequentFill8x8Pattern = 0; ! } else if ((xf86AccelInfoRec.Subsequent8x8PatternColorExpand) || ! (xf86AccelInfoRec.SubsequentFill8x8Pattern)) { ! ErrorF("%s %s: XAA: 8x8 Pattern fill disabled - insufficient video memory available\n", ! XCONFIG_PROBED, infoRec->name); ! xf86AccelInfoRec.Subsequent8x8PatternColorExpand = 0; ! xf86AccelInfoRec.SubsequentFill8x8Pattern = 0; } } /* --- 170,204 ---- return; } ! /* see if there is enough room for 8x8 pattern storage */ ! if((xf86AccelInfoRec.SubsequentFill8x8Pattern || ! xf86AccelInfoRec.Subsequent8x8PatternColorExpand) && ! !(xf86AccelInfoRec.Flags & ! HARDWARE_PATTERN_PROGRAMMED_ORIGIN)){ ! Bool disable8x8 = TRUE; ! Bool disable8x8ColorExpand = TRUE; ! ! if (!(xf86AccelInfoRec.Flags & HARDWARE_PATTERN_PROGRAMMED_BITS)) ! disable8x8ColorExpand = FALSE; ! ! if(xf86AccelInfoRec.Flags & HARDWARE_PATTERN_NOT_LINEAR){ ! if(MaxHeight >= 15) { ! disable8x8 = FALSE; ! disable8x8ColorExpand = FALSE; } + } else if (MaxHeight >= 8) { + disable8x8 = FALSE; + disable8x8ColorExpand = FALSE; + } + + if(disable8x8 || disable8x8ColorExpand) { + ErrorF("%s %s: XAA: 8x8 Pattern fill disabled - insufficient " + "video memory available\n", XCONFIG_PROBED, infoRec->name); + if (disable8x8) + xf86AccelInfoRec.SubsequentFill8x8Pattern = 0; + if (disable8x8ColorExpand) + xf86AccelInfoRec.Subsequent8x8PatternColorExpand = 0; + } } /* *************** *** 1241,1251 **** { int cur_w = pci->pix_w; int cur_h = pci->pix_h; xf86AccelInfoRec.SetupForScreenToScreenCopy(1, 1, GXcopy, 0xFFFFFFFF, -1); /* Expand in the x direction */ ! while (cur_w * 2 <= pci->w) { xf86AccelInfoRec.SubsequentScreenToScreenCopy(pci->x, pci->y, pci->x + cur_w, pci->y, cur_w, cur_h); --- 1256,1274 ---- { int cur_w = pci->pix_w; int cur_h = pci->pix_h; + int width = pci->w; + int height = pci->h; xf86AccelInfoRec.SetupForScreenToScreenCopy(1, 1, GXcopy, 0xFFFFFFFF, -1); + if((xf86AccelInfoRec.Flags & HARDWARE_PATTERN_NOT_LINEAR) && + pci->flags == 1) { + width = 16; /* To fix a 32bpp S3 bug */ + height = 15; + } + /* Expand in the x direction */ ! while (cur_w * 2 <= width) { xf86AccelInfoRec.SubsequentScreenToScreenCopy(pci->x, pci->y, pci->x + cur_w, pci->y, cur_w, cur_h); *************** *** 1252,1266 **** cur_w *= 2; } ! if (cur_w != pci->w) { xf86AccelInfoRec.SubsequentScreenToScreenCopy((pci->x), (pci->y), ! (pci->x + cur_w), pci->y, (pci->w - cur_w), cur_h); ! cur_w = pci->w; } /* Expand in the y direction */ ! while (cur_h * 2 <= pci->h) { xf86AccelInfoRec.SubsequentScreenToScreenCopy((pci->x), (pci->y), (pci->x), (pci->y + cur_h), cur_w, cur_h); --- 1275,1289 ---- cur_w *= 2; } ! if (cur_w != width) { xf86AccelInfoRec.SubsequentScreenToScreenCopy((pci->x), (pci->y), ! (pci->x + cur_w), pci->y, (width - cur_w), cur_h); ! cur_w = width; } /* Expand in the y direction */ ! while (cur_h * 2 <= height) { xf86AccelInfoRec.SubsequentScreenToScreenCopy((pci->x), (pci->y), (pci->x), (pci->y + cur_h), cur_w, cur_h); *************** *** 1267,1276 **** cur_h *= 2; } ! if (cur_h != pci->h) { xf86AccelInfoRec.SubsequentScreenToScreenCopy((pci->x), (pci->y), ! (pci->x), (pci->y + cur_h), cur_w, (pci->h - cur_h)); } if (xf86AccelInfoRec.Flags & BACKGROUND_OPERATIONS) --- 1290,1299 ---- cur_h *= 2; } ! if (cur_h != height) { xf86AccelInfoRec.SubsequentScreenToScreenCopy((pci->x), (pci->y), ! (pci->x), (pci->y + cur_h), cur_w, (height - cur_h)); } if (xf86AccelInfoRec.Flags & BACKGROUND_OPERATIONS) *** /dev/null Tue Jun 30 15:23:32 1998 --- xc/programs/Xserver/hw/xfree86/xaa/xf86wline.c Fri Mar 6 16:57:01 1998 *************** *** 0 **** --- 1,939 ---- + /* $TOG: xf86wline.c /main/1 1998/03/06 16:58:39 kaleb $ */ + + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/xaa/xf86wline.c,v 1.8.2.2 1998/02/27 01:29:29 dawes Exp $ */ + /* + + xf86WideLine does not maintain a span list and subsequently does not + follow the "touch-each-pixel-once" rules for wide lines and arcs. + This means it can only be used in the case where we have + miSpansEasyRop(pGC->alu). Since we clip spans on the fly, we + limited usage of this function to one rect situations. This + function is used only for solid lines. + + Adapted from miWideLine by Mark Vojkovich (mvojkovi@ucsd.edu) + Original mi code written by Keith Packard. + + */ + + #include <stdio.h> + #include <math.h> + #include "X.h" + #include "windowstr.h" + #include "gcstruct.h" + #include "miscstruct.h" + #include "miwideline.h" + #include "mi.h" + #define PSZ 8 + #define NOXF86DEFS + #include "cfb.h" + + #ifdef ICEILTEMPDECL + ICEILTEMPDECL + #endif + + #include "xf86.h" + #include "xf86xaa.h" + #include "xf86local.h" + + extern int miPolyBuildEdge(); + + + static int LeftClip, RightClip, TopClip, BottomClip; + + #define Y_IN_BOX(y) (((y) >= TopClip) && ((y) <= BottomClip)) + #define CLIPSTEPEDGE(edgey,edge,edgeleft) \ + if (ybase == edgey) { \ + if (edgeleft) { \ + if (edge->x > xcl) \ + xcl = edge->x; \ + } else { \ + if (edge->x < xcr) \ + xcr = edge->x; \ + } \ + edgey++; \ + edge->x += edge->stepx; \ + edge->e += edge->dx; \ + if (edge->e > 0) { \ + edge->x += edge->signdx; \ + edge->e -= edge->dy; \ + } \ + } + + static void xf86PointHelper(x, y) + int x, y; + { + if(Y_IN_BOX(y) && (x >= LeftClip) && (x <= RightClip)) + xf86AccelInfoRec.SubsequentFillRectSolid(x, y, 1, 1); + } + + static void xf86FillRectHelper(x, y, dx, dy) + int x, y, dx, dy; + { + int x2 = x + dx - 1; + int y2 = y + dy - 1; + + if(x < LeftClip) x = LeftClip; + if(x2 > RightClip) x2 = RightClip; + if(y < TopClip) y = TopClip; + if(y2 > BottomClip) y2 = BottomClip; + + dx = x2 - x + 1; + dy = y2 - y + 1; + + if((dx > 0) && (dy > 0)) + xf86AccelInfoRec.SubsequentFillRectSolid(x, y, dx, dy); + } + + + /* The span helper does not check for y being clipped, caller beware */ + static void xf86SpanHelper(x1, y, width) + int x1, y, width; + { + int x2 = x1 + width - 1; + + if(x1 < LeftClip) x1 = LeftClip; + if(x2 > RightClip) x2 = RightClip; + width = x2 - x1 + 1; + + if(width > 0) + xf86AccelInfoRec.SubsequentFillRectSolid(x1, y, width, 1); + + } + + #define FixError(x, dx, dy, e, sign, step, h) { \ + e += (h) * dx; \ + x += (h) * step; \ + if(e > 0) { \ + x += e * sign/dy; \ + e %= dy; \ + if(e) { \ + x += sign; \ + e -= dy; \ + } \ + } \ + } + + + void + xf86FillPolyHelper (pDrawable, pGC, y, overall_height, left, right, + left_count, right_count) + DrawablePtr pDrawable; + GCPtr pGC; + int y; /* start y coordinate */ + int overall_height; /* height of entire segment */ + PolyEdgePtr left, right; + int left_count, right_count; + { + register int left_x, left_e; + int left_stepx; + int left_signdx; + int left_dy, left_dx; + register int right_x, right_e; + int right_stepx; + int right_signdx; + int right_dy, right_dx; + int height; + int left_height = 0; + int right_height = 0; + int xorg = 0; + + if (pGC->miTranslate) { + y += pDrawable->y; + xorg = pDrawable->x; + } + + + while ((left_count || left_height) && (right_count || right_height)) { + if (!left_height && left_count) { + left_height = left->height; + left_x = left->x + xorg; + left_stepx = left->stepx; + left_signdx = left->signdx; + left_e = left->e; + left_dy = left->dy; + left_dx = left->dx; + left_count--; + left++; + } + if (!right_height && right_count) { + right_height = right->height; + right_x = right->x + xorg + 1; + right_stepx = right->stepx; + right_signdx = right->signdx; + right_e = right->e; + right_dy = right->dy; + right_dx = right->dx; + right_count--; + right++; + } + + height = (left_height > right_height) ? right_height : left_height; + + left_height -= height; + right_height -= height; + + if(xf86AccelInfoRec.SubsequentFillTrapezoidSolid && (height > 6)) { + int right_DX = (right_dx * right_signdx) + + (right_stepx * right_dy); + int left_DX = (left_dx * left_signdx) + + (left_stepx * left_dy); + int left_box = (left_DX < 0) ? (left_x + left_DX) : left_x; + int right_box = (right_DX < 0) ? right_x : (right_x + right_DX); + + if((left_box >= LeftClip) && (right_box <= RightClip) && + (y >= TopClip) && ((y + height) <= BottomClip)){ + + xf86AccelInfoRec.SubsequentFillTrapezoidSolid(y, height, + left_x, left_DX, left_dy, left_e, + right_x - 1, right_DX, right_dy, right_e); + + FixError(left_x, left_dx, left_dy, left_e, left_signdx, + left_stepx, height); + FixError(right_x, right_dx, right_dy, right_e, right_signdx, + right_stepx, height); + y += height; + continue; + } + } + + while (height--) { + if((right_x > left_x) && Y_IN_BOX(y)) + xf86SpanHelper(left_x, y, right_x - left_x); + + y++; + + left_x += left_stepx; + left_e += left_dx; + if (left_e > 0) { + left_x += left_signdx; + left_e -= left_dy; + } + right_x += right_stepx; + right_e += right_dx; + if (right_e > 0) { + right_x += right_signdx; + right_e -= right_dy; + } + + } + } + } + + + + static void + xf86WideSegment (pDrawable, pGC, x1, y1, x2, y2, + projectLeft, projectRight, leftFace, rightFace) + DrawablePtr pDrawable; + GCPtr pGC; + register int x1, y1, x2, y2; + Bool projectLeft, projectRight; + register LineFacePtr leftFace, rightFace; + { + double l, L, r; + double xa, ya; + double projectXoff, projectYoff; + double k; + double maxy; + int x, y; + int dx, dy; + int finaly; + PolyEdgePtr left, right; + PolyEdgePtr top, bottom; + int lefty, righty, topy, bottomy; + int signdx; + PolyEdgeRec lefts[2], rights[2]; + LineFacePtr tface; + int lw = pGC->lineWidth; + + /* draw top-to-bottom always */ + if (y2 < y1 || y2 == y1 && x2 < x1) { + x = x1; + x1 = x2; + x2 = x; + + y = y1; + y1 = y2; + y2 = y; + + x = projectLeft; + projectLeft = projectRight; + projectRight = x; + + tface = leftFace; + leftFace = rightFace; + rightFace = tface; + } + + dy = y2 - y1; + signdx = 1; + dx = x2 - x1; + if (dx < 0) + signdx = -1; + + leftFace->x = x1; + leftFace->y = y1; + leftFace->dx = dx; + leftFace->dy = dy; + + rightFace->x = x2; + rightFace->y = y2; + rightFace->dx = -dx; + rightFace->dy = -dy; + + + if (!dy) { + rightFace->xa = 0; + rightFace->ya = (double) lw / 2.0; + rightFace->k = -(double) (lw * dx) / 2.0; + leftFace->xa = 0; + leftFace->ya = -rightFace->ya; + leftFace->k = rightFace->k; + x = x1; + if (projectLeft) + x -= (lw >> 1); + y = y1 - (lw >> 1); + dx = x2 - x; + if (projectRight) + dx += (lw + 1 >> 1); + dy = lw; + if(pGC->miTranslate) { + x += pDrawable->x; + y += pDrawable->y; + } + xf86FillRectHelper(x, y, dx, dy); + } else if (!dx) { + leftFace->xa = (double) lw / 2.0; + leftFace->ya = 0; + leftFace->k = (double) (lw * dy) / 2.0; + rightFace->xa = -leftFace->xa; + rightFace->ya = 0; + rightFace->k = leftFace->k; + y = y1; + if (projectLeft) + y -= lw >> 1; + x = x1 - (lw >> 1); + dy = y2 - y; + if (projectRight) + dy += (lw + 1 >> 1); + dx = lw; + if(pGC->miTranslate) { + x += pDrawable->x; + y += pDrawable->y; + } + xf86FillRectHelper(x, y, dx, dy); + } else { + l = ((double) lw) / 2.0; + L = sqrt((double)(dx*dx + dy*dy)); + + if (dx < 0) { + right = &rights[1]; + left = &lefts[0]; + top = &rights[0]; + bottom = &lefts[1]; + } else { + right = &rights[0]; + left = &lefts[1]; + top = &lefts[0]; + bottom = &rights[1]; + } + r = l / L; + + /* coord of upper bound at integral y */ + ya = -r * dx; + xa = r * dy; + + if (projectLeft | projectRight) { + projectXoff = -ya; + projectYoff = xa; + } + + /* xa * dy - ya * dx */ + k = l * L; + + leftFace->xa = xa; + leftFace->ya = ya; + leftFace->k = k; + rightFace->xa = -xa; + rightFace->ya = -ya; + rightFace->k = k; + + if (projectLeft) + righty = miPolyBuildEdge (xa - projectXoff, ya - projectYoff, + k, dx, dy, x1, y1, 0, right); + else + righty = miPolyBuildEdge (xa, ya, + k, dx, dy, x1, y1, 0, right); + + /* coord of lower bound at integral y */ + ya = -ya; + xa = -xa; + + /* xa * dy - ya * dx */ + k = - k; + + if (projectLeft) + lefty = miPolyBuildEdge (xa - projectXoff, ya - projectYoff, + k, dx, dy, x1, y1, 1, left); + else + lefty = miPolyBuildEdge (xa, ya, + k, dx, dy, x1, y1, 1, left); + + /* coord of top face at integral y */ + + if (signdx > 0) { + ya = -ya; + xa = -xa; + } + + if (projectLeft) { + double xap = xa - projectXoff; + double yap = ya - projectYoff; + topy = miPolyBuildEdge (xap, yap, xap * dx + yap * dy, + -dy, dx, x1, y1, dx > 0, top); + } + else + topy = miPolyBuildEdge(xa, ya, 0.0, + -dy, dx, x1, y1, dx > 0, top); + + /* coord of bottom face at integral y */ + + if (projectRight) { + double xap = xa + projectXoff; + double yap = ya + projectYoff; + bottomy = miPolyBuildEdge (xap, yap, xap * dx + yap * dy, + -dy, dx, x2, y2, dx < 0, bottom); + maxy = -ya + projectYoff; + } else { + bottomy = miPolyBuildEdge (xa, ya, 0.0, + -dy, dx, x2, y2, dx < 0, bottom); + maxy = -ya; + } + + finaly = ICEIL (maxy) + y2; + + if (dx < 0) { + left->height = bottomy - lefty; + right->height = finaly - righty; + top->height = righty - topy; + } else { + right->height = bottomy - righty; + left->height = finaly - lefty; + top->height = lefty - topy; + } + bottom->height = finaly - bottomy; + xf86FillPolyHelper (pDrawable, pGC, topy, + bottom->height + bottomy - topy, lefts, rights, 2, 2); + } + } + + + static void + xf86LineArcI (pDraw, pGC, xorg, yorg) + DrawablePtr pDraw; + GCPtr pGC; + int xorg, yorg; + { + register int x, y, e, ex, slw; + + if (pGC->miTranslate) { + xorg += pDraw->x; + yorg += pDraw->y; + } + + slw = pGC->lineWidth; + if (slw == 1) { + xf86PointHelper(xorg, yorg); + return; + } + + y = (slw >> 1) + 1; + if (slw & 1) + e = - ((y << 2) + 3); + else + e = - (y << 3); + ex = -4; + x = 0; + while (y) { + e += (y << 3) - 4; + while (e >= 0) { + x++; + e += (ex = -((x << 3) + 4)); + } + y--; + slw = (x << 1) + 1; + if ((e == ex) && (slw > 1)) + slw--; + + if(Y_IN_BOX(yorg - y)) + xf86SpanHelper(xorg - x, yorg - y, slw); + + if ((y != 0) && ((slw > 1) || (e != ex)) && Y_IN_BOX(yorg + y)) + xf86SpanHelper(xorg - x, yorg + y, slw); + } + } + + + static void + xf86LineArcD (pDraw, pGC, xorg, yorg, + edge1, edgey1, edgeleft1, edge2, edgey2, edgeleft2) + DrawablePtr pDraw; + GCPtr pGC; + double xorg, yorg; + PolyEdgePtr edge1, edge2; + int edgey1, edgey2; + Bool edgeleft1, edgeleft2; + { + double radius, x0, y0, el, er, yk, xlk, xrk, k; + int xbase, ybase, y, boty, xl, xr, xcl, xcr; + int ymin, ymax; + Bool edge1IsMin, edge2IsMin; + int ymin1, ymin2; + + + xbase = floor(xorg); + x0 = xorg - xbase; + ybase = ICEIL (yorg); + y0 = yorg - ybase; + if (pGC->miTranslate) { + xbase += pDraw->x; + ybase += pDraw->y; + edge1->x += pDraw->x; + edge2->x += pDraw->x; + edgey1 += pDraw->y; + edgey2 += pDraw->y; + } + + xlk = x0 + x0 + 1.0; + xrk = x0 + x0 - 1.0; + yk = y0 + y0 - 1.0; + radius = ((double)pGC->lineWidth) / 2.0; + y = floor(radius - y0 + 1.0); + ybase -= y; + ymin = ybase; + ymax = 65536; + edge1IsMin = FALSE; + ymin1 = edgey1; + if (edge1->dy >= 0) { + if (!edge1->dy) { + if (edgeleft1) + edge1IsMin = TRUE; + else + ymax = edgey1; + edgey1 = 65536; + } else if ((edge1->signdx < 0) == edgeleft1) + edge1IsMin = TRUE; + } + edge2IsMin = FALSE; + ymin2 = edgey2; + if (edge2->dy >= 0) { + if (!edge2->dy) { + if (edgeleft2) + edge2IsMin = TRUE; + else + ymax = edgey2; + edgey2 = 65536; + } else if ((edge2->signdx < 0) == edgeleft2) + edge2IsMin = TRUE; + } + if (edge1IsMin) { + ymin = ymin1; + if (edge2IsMin && (ymin1 > ymin2)) + ymin = ymin2; + } else if (edge2IsMin) + ymin = ymin2; + el = radius * radius - ((y + y0) * (y + y0)) - (x0 * x0); + er = el + xrk; + xl = 1; + xr = 0; + if (x0 < 0.5) { + xl = 0; + el -= xlk; + } + boty = (y0 < -0.5) ? 1 : 0; + if (ybase + y - boty > ymax) + boty = ymax - ybase - y; + while (y > boty) { + k = (y << 1) + yk; + er += k; + while (er > 0.0) { + xr++; + er += xrk - (xr << 1); + } + el += k; + while (el >= 0.0) { + xl--; + el += (xl << 1) - xlk; + } + y--; + ybase++; + if (ybase < ymin) + continue; + xcl = xl + xbase; + xcr = xr + xbase; + CLIPSTEPEDGE(edgey1, edge1, edgeleft1); + CLIPSTEPEDGE(edgey2, edge2, edgeleft2); + if((xcr >= xcl) && Y_IN_BOX(ybase)) + xf86SpanHelper(xcl, ybase, xcr - xcl + 1); + } + er = xrk - (xr << 1) - er; + el = (xl << 1) - xlk - el; + boty = floor(-y0 - radius + 1.0); + if (ybase + y - boty > ymax) + boty = ymax - ybase - y; + while (y > boty) { + k = (y << 1) + yk; + er -= k; + while ((er >= 0.0) && (xr >= 0)) { + xr--; + er += xrk - (xr << 1); + } + el -= k; + while ((el > 0.0) && (xl <= 0)) { + xl++; + el += (xl << 1) - xlk; + } + y--; + ybase++; + if (ybase < ymin) + continue; + xcl = xl + xbase; + xcr = xr + xbase; + CLIPSTEPEDGE(edgey1, edge1, edgeleft1); + CLIPSTEPEDGE(edgey2, edge2, edgeleft2); + if((xcr >= xcl) && Y_IN_BOX(ybase)) + xf86SpanHelper(xcl, ybase, xcr - xcl + 1); + } + } + + + static void + xf86LineArc (pDraw, pGC, leftFace, rightFace, xorg, yorg, isInt) + DrawablePtr pDraw; + register GCPtr pGC; + register LineFacePtr leftFace, rightFace; + double xorg, yorg; + Bool isInt; + { + int xorgi, yorgi; + PolyEdgeRec edge1, edge2; + int edgey1, edgey2; + Bool edgeleft1, edgeleft2; + + if (isInt) { + xorgi = leftFace ? leftFace->x : rightFace->x; + yorgi = leftFace ? leftFace->y : rightFace->y; + } + edgey1 = 65536; + edgey2 = 65536; + edge1.x = 0; /* not used, keep memory checkers happy */ + edge1.dy = -1; + edge2.x = 0; /* not used, keep memory checkers happy */ + edge2.dy = -1; + edgeleft1 = FALSE; + edgeleft2 = FALSE; + + if ((pGC->lineWidth > 2) && + (pGC->capStyle == CapRound && pGC->joinStyle != JoinRound || + pGC->joinStyle == JoinRound && pGC->capStyle == CapButt)) { + if (isInt) { + xorg = (double) xorgi; + yorg = (double) yorgi; + } + + if (leftFace && rightFace) { + miRoundJoinClip (leftFace, rightFace, &edge1, &edge2, + &edgey1, &edgey2, &edgeleft1, &edgeleft2); + } else if (leftFace) { + edgey1 = miRoundCapClip (leftFace, isInt, &edge1, &edgeleft1); + } else if (rightFace) { + edgey2 = miRoundCapClip (rightFace, isInt, &edge2, &edgeleft2); + } + + isInt = FALSE; + } + + + if (isInt) + xf86LineArcI(pDraw, pGC, xorgi, yorgi); + else + xf86LineArcD(pDraw, pGC, xorg, yorg, + &edge1, edgey1, edgeleft1, + &edge2, edgey2, edgeleft2); + + } + + + static void + xf86LineJoin (pDrawable, pGC, pLeft, pRight) + DrawablePtr pDrawable; + GCPtr pGC; + register LineFacePtr pLeft, pRight; + { + double mx, my; + double denom; + PolyVertexRec vertices[4]; + PolySlopeRec slopes[4]; + int edgecount; + PolyEdgeRec left[4], right[4]; + int nleft, nright; + int y, height; + int swapslopes; + int joinStyle = pGC->joinStyle; + int lw = pGC->lineWidth; + + if (lw == 1) { + /* Lines going in the same direction have no join */ + if ((pLeft->dx >= 0) == (pRight->dx <= 0)) + return; + if (joinStyle != JoinRound) { + denom = - pLeft->dx * (double)pRight->dy + pRight->dx * + (double)pLeft->dy; + if (denom == 0.0) + return; /* no join to draw */ + } + if (joinStyle != JoinMiter) { + if(pGC->miTranslate) + xf86PointHelper(pLeft->x + pDrawable->x, + pLeft->y + pDrawable->y); + else + xf86PointHelper(pLeft->x, pLeft->y); + return; + } + } else { + if (joinStyle == JoinRound) { + xf86LineArc(pDrawable, pGC, pLeft, pRight, + (double)0.0, (double)0.0, TRUE); + return; + } + denom = - pLeft->dx * (double)pRight->dy + pRight->dx * + (double)pLeft->dy; + if (denom == 0.0) + return; /* no join to draw */ + } + + swapslopes = 0; + if (denom > 0) { + pLeft->xa = -pLeft->xa; + pLeft->ya = -pLeft->ya; + pLeft->dx = -pLeft->dx; + pLeft->dy = -pLeft->dy; + } else { + swapslopes = 1; + pRight->xa = -pRight->xa; + pRight->ya = -pRight->ya; + pRight->dx = -pRight->dx; + pRight->dy = -pRight->dy; + } + + vertices[0].x = pRight->xa; + vertices[0].y = pRight->ya; + slopes[0].dx = -pRight->dy; + slopes[0].dy = pRight->dx; + slopes[0].k = 0; + + vertices[1].x = 0; + vertices[1].y = 0; + slopes[1].dx = pLeft->dy; + slopes[1].dy = -pLeft->dx; + slopes[1].k = 0; + + vertices[2].x = pLeft->xa; + vertices[2].y = pLeft->ya; + + if (joinStyle == JoinMiter) { + my = (pLeft->dy * (pRight->xa * pRight->dy - pRight->ya * pRight->dx) - + pRight->dy * (pLeft->xa * pLeft->dy - pLeft->ya * pLeft->dx ))/ + denom; + if (pLeft->dy != 0) + mx = pLeft->xa + (my - pLeft->ya) * + (double) pLeft->dx / (double) pLeft->dy; + else + mx = pRight->xa + (my - pRight->ya) * + (double) pRight->dx / (double) pRight->dy; + + /* check miter limit */ + if ((mx * mx + my * my) * 4 > SQSECANT * lw * lw) + joinStyle = JoinBevel; + } + + if (joinStyle == JoinMiter) { + slopes[2].dx = pLeft->dx; + slopes[2].dy = pLeft->dy; + slopes[2].k = pLeft->k; + if (swapslopes) { + slopes[2].dx = -slopes[2].dx; + slopes[2].dy = -slopes[2].dy; + slopes[2].k = -slopes[2].k; + } + vertices[3].x = mx; + vertices[3].y = my; + slopes[3].dx = pRight->dx; + slopes[3].dy = pRight->dy; + slopes[3].k = pRight->k; + if (swapslopes) { + slopes[3].dx = -slopes[3].dx; + slopes[3].dy = -slopes[3].dy; + slopes[3].k = -slopes[3].k; + } + edgecount = 4; + } else { + double scale, dx, dy, adx, ady; + + adx = dx = pRight->xa - pLeft->xa; + ady = dy = pRight->ya - pLeft->ya; + if (adx < 0) + adx = -adx; + if (ady < 0) + ady = -ady; + scale = ady; + if (adx > ady) + scale = adx; + slopes[2].dx = (dx * 65536) / scale; + slopes[2].dy = (dy * 65536) / scale; + slopes[2].k = ((pLeft->xa + pRight->xa) * slopes[2].dy - + (pLeft->ya + pRight->ya) * slopes[2].dx) / 2.0; + edgecount = 3; + } + + y = miPolyBuildPoly (vertices, slopes, edgecount, pLeft->x, pLeft->y, + left, right, &nleft, &nright, &height); + xf86FillPolyHelper(pDrawable, pGC, y, height, left, right, nleft, nright); + } + + + void + xf86WideLineSolid1Rect (pDrawable, pGC, mode, npt, pPts) + DrawablePtr pDrawable; + register GCPtr pGC; + int mode; + register int npt; + register DDXPointPtr pPts; + { + int x1, y1, x2, y2; + Bool projectLeft, projectRight; + LineFaceRec leftFace, rightFace, prevRightFace; + LineFaceRec firstFace; + int first = TRUE; + Bool somethingDrawn = FALSE; + Bool selfJoin = FALSE; + cfbPrivGCPtr devPriv = cfbGetGCPrivate(pGC); + + if(REGION_NUM_RECTS(devPriv->pCompositeClip) != 1) { + miWideLine(pDrawable, pGC, mode, npt, pPts); + return; + } + + LeftClip = devPriv->pCompositeClip->extents.x1; + RightClip = devPriv->pCompositeClip->extents.x2 - 1; + TopClip = devPriv->pCompositeClip->extents.y1; + BottomClip = devPriv->pCompositeClip->extents.y2 - 1; + + xf86AccelInfoRec.SetupForFillRectSolid(pGC->fgPixel, pGC->alu, + pGC->planemask); + x2 = pPts->x; + y2 = pPts->y; + if (npt > 1) { + if (mode == CoordModePrevious) { + int nptTmp; + register DDXPointPtr pPtsTmp; + + x1 = x2; + y1 = y2; + nptTmp = npt; + pPtsTmp = pPts + 1; + while (--nptTmp) { + x1 += pPtsTmp->x; + y1 += pPtsTmp->y; + ++pPtsTmp; + } + if ((x2 == x1) && (y2 == y1)) + selfJoin = TRUE; + } else if ((x2 == pPts[npt-1].x) && (y2 == pPts[npt-1].y)) + selfJoin = TRUE; + } + + projectLeft = ((pGC->capStyle == CapProjecting) && !selfJoin); + projectRight = FALSE; + + while (--npt) { + x1 = x2; + y1 = y2; + ++pPts; + x2 = pPts->x; + y2 = pPts->y; + if (mode == CoordModePrevious) { + x2 += x1; + y2 += y1; + } + if ((x1 != x2) || (y1 != y2)) { + somethingDrawn = TRUE; + if ((npt == 1) && (pGC->capStyle == CapProjecting) && !selfJoin) + projectRight = TRUE; + xf86WideSegment(pDrawable, pGC, x1, y1, x2, y2, + projectLeft, projectRight, &leftFace, &rightFace); + if (first) { + if (selfJoin) + firstFace = leftFace; + else if (pGC->capStyle == CapRound) { + if (pGC->lineWidth == 1) { + if(pGC->miTranslate) + xf86PointHelper(x1 + pDrawable->x, + y1 + pDrawable->y); + else + xf86PointHelper(x1, y1); + } else + xf86LineArc(pDrawable, pGC, + &leftFace, (LineFacePtr) NULL, + (double)0.0, (double)0.0, + TRUE); + } + } else + xf86LineJoin (pDrawable, pGC, &leftFace, &prevRightFace); + + prevRightFace = rightFace; + first = FALSE; + projectLeft = FALSE; + } + if (npt == 1 && somethingDrawn) { + if (selfJoin) + xf86LineJoin (pDrawable, pGC, &firstFace, &rightFace); + else if (pGC->capStyle == CapRound) { + if (pGC->lineWidth == 1) { + if(pGC->miTranslate) + xf86PointHelper(x2 + pDrawable->x, + y2 + pDrawable->y); + else + xf86PointHelper(x2, y2); + } else + xf86LineArc (pDrawable, pGC, + (LineFacePtr) NULL, &rightFace, + (double)0.0, (double)0.0, + TRUE); + } + } + } + /* handle crock where all points are coincedent */ + if (!somethingDrawn) { + projectLeft = (pGC->capStyle == CapProjecting); + xf86WideSegment (pDrawable, pGC, + x2, y2, x2, y2, projectLeft, projectLeft, + &leftFace, &rightFace); + if (pGC->capStyle == CapRound) { + xf86LineArc (pDrawable, pGC, + &leftFace, (LineFacePtr) NULL, + (double)0.0, (double)0.0, + TRUE); + rightFace.dx = -1; /* sleezy hack to make it work */ + xf86LineArc (pDrawable, pGC, + (LineFacePtr) NULL, &rightFace, + (double)0.0, (double)0.0, + TRUE); + } + } + if (xf86AccelInfoRec.Flags & BACKGROUND_OPERATIONS) + xf86AccelInfoRec.Sync(); + } *** ./xfree86/xaa/xf86xaa.h@@/PUBLIC-LATEST Sat Jul 19 11:01:57 1997 --- xc/programs/Xserver/hw/xfree86/xaa/xf86xaa.h Fri Mar 6 16:57:06 1998 *************** *** 1,8 **** ! /* $TOG: xf86xaa.h /main/1 1997/07/19 11:01:59 kaleb $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/xaa/xf86xaa.h,v 3.7.2.1 1997/05/18 12:00:22 dawes Exp $ */ /* AccelInfoRec flags */ --- 1,8 ---- ! /* $TOG: xf86xaa.h /main/2 1998/03/06 16:58:43 kaleb $ */ ! /* $XFree86: xc/programs/Xserver/hw/xfree86/xaa/xf86xaa.h,v 3.7.2.2 1998/02/01 16:05:25 robin Exp $ */ /* AccelInfoRec flags */ *************** *** 29,34 **** --- 29,39 ---- #define HARDWARE_PATTERN_MONO_TRANSPARENCY 0x80000 #define NO_TEXT_COLOR_EXPANSION 0x100000 #define HARDWARE_PATTERN_NOT_LINEAR 0x200000 + #define LINE_PATTERN_POWER_OF_2_ONLY 0x400000 + #define LINE_PATTERN_MSBFIRST_MSBJUSTIFIED 0x800000 + #define LINE_PATTERN_MSBFIRST_LSBJUSTIFIED 0x1000000 + #define LINE_PATTERN_ONLY_TRANSPARENCY 0x2000000 + #define DO_NOT_BLIT_STIPPLES 0x4000000 /* Graphics operation flags */ *************** *** 253,258 **** --- 258,283 ---- #endif ); int CopyAreaFlags; + void (*PolyLineDashedZeroWidth)( + #if NeedNestedPrototypes + DrawablePtr pDrawable, + GCPtr pGC, + int mode, + int npt, + DDXPointPtr pptInit + #endif + ); + int PolyLineDashedZeroWidthFlags; + void (*PolySegmentDashedZeroWidth)( + #if NeedNestedPrototypes + DrawablePtr pDrawable, + GCPtr pGC, + int nseg, + xSegment *pSeg + #endif + ); + int PolySegmentDashedZeroWidthFlags; + /* * These fall-back functions are set during screen initialization. *************** *** 524,529 **** --- 549,568 ---- int height #endif ); + void (*SubsequentFillTrapezoidSolid)( + #if NeedNestedPrototypes + int ytop, + int height, + int left, + int dxL, + int dyL, + int eL, + int right, + int dxR, + int dyR, + int eR + #endif + ); void (*SetupForScreenToScreenCopy)( #if NeedNestedPrototypes int xdir, *************** *** 738,743 **** --- 777,814 ---- unsigned long **addrl #endif ); + void (*SetupForDashedLine)( + #if NeedNestedPrototypes + int fg, + int bg, + int rop, + unsigned planemask, + int size + #endif + ); + void (*SubsequentDashedBresenhamLine)( + #if NeedNestedPrototypes + int x2, + int y1, + int octant, + int err, + int e1, + int e2, + int length, + int offset + #endif + ); + void (*SubsequentDashedTwoPointLine)( + #if NeedNestedPrototypes + int x1, + int y1, + int x2, + int y2, + int bias, + int offset + #endif + ); + void (*Sync)(); int Flags; int ColorExpandFlags; *************** *** 757,762 **** --- 828,835 ---- ScrnInfoPtr ServerInfoRec; int PixmapCacheMemoryStart; int PixmapCacheMemoryEnd; + int LinePatternMaxLength; + void *LinePatternBuffer; } xf86AccelInfoRecType; extern xf86AccelInfoRecType xf86AccelInfoRec; *** /dev/null Tue Jun 30 15:23:34 1998 --- xc/programs/Xserver/hw/xfree98/vga256/Imakefile.vga Fri Mar 6 14:12:59 1998 *************** *** 0 **** --- 1,225 ---- + XCOMM $TOG: Imakefile.vga /main/1 1998/03/06 14:14:37 kaleb $ + + + + + XCOMM $XFree86: xc/programs/Xserver/hw/xfree98/vga256/Imakefile.vga,v 1.3.2.1 1998/02/01 16:42:17 robin Exp $ + XCOMM + XCOMM + XCOMM This is the Imakefile for the server-specific subdirectories + XCOMM (egc, ganbwap, mga, nkvnec, pegc, trident, wabep, wabs, wsna). It is + XCOMM included from the Imakefiles in these directories. VGADEFINES + XCOMM should be correctly defined for a specific server. + + #include <Server.tmpl> + + #ifdef i386Architecture + FSRCS = fBitBlt.s fFillCopy.s fFillOr.s fFillAnd.s \ + fFillXor.s fFillSet.s vgabres.s vgalineH.s vgalineV.s + BSRCS = BitBlt.s BitBlt2.s Box.s Line.s VHLine.s vgaBank.s + + FOBJS = fBitBlt.o fFillCopy.o fFillOr.o fFillAnd.o \ + fFillXor.o fFillSet.o vgabres.o vgalineH.o vgalineV.o + BOBJS = BitBlt.o BitBlt2.o Box.o Line.o VHLine.o vgaBank.o + #else + FSRCS = vgaBltFillc.c vgaLinec.c + BSRCS = vgaBankc.c + + FOBJS = vgaBltFillc.o vgaLinec.o + BOBJS = vgaBankc.o + #endif + + SRCS = vgagc.c vgawindow.c vgascrinit.c \ + vgapntwin.c vgapwinS.c vgabitblt.c \ + vgafillsp.c vgasetsp.c vgaimage.c \ + vgagetsp.c vgafillrct.c vgaBitBlt1.c \ + vgasolidC.c vgasolidCS.c vgasolidX.c \ + vgasolidO.c vgasolidA.c vgasolidG.c \ + vgatile32C.c vgatile32G.c \ + vgatileoddC.c vgatileoddG.c \ + vgazerarcC.c vgazerarcX.c vgazerarcG.c \ + vgafillarcC.c vgafillarcG.c \ + vgategblt.c vgabstore.c vga8cppl.c \ + vgabltC.c vgabltCS.c vgabltX.c vgabltO.c vgabltG.c \ + vgateblt8.c vgateblt8S.c vgaglblt8.c vgaglrop8.c \ + vgapush8.c vgarctstp8.c vgarctstp8S.c vgapolypnt.c \ + vgaline.c vgalineS.c vgabresd.c \ + vgalined.c vgasegd.c vgaseg.c vgasegS.c \ + vgaply1rctC.c vgaply1rctG.c vgafuncs.c \ + SpeedUpBlt.c $(BSRCS) \ + vgaBanks.c $(FSRCS) vgaHW.c vga.c vgaCmap.c \ + vgaPCI.c vgatables.c + + FOBJS = fBitBlt.o fFillCopy.o fFillXor.o fFillOr.o fFillAnd.o \ + fFillSet.o vgabres.o vgalineH.o vgalineV.o + + OBJS = vgagc.o vgawindow.o vgascrinit.o \ + vgagetsp.o vgafillrct.o vgaimage.o \ + vgasolidC.o vgasolidCS.o vgasolidX.o \ + vgasolidO.o vgasolidA.o vgasolidG.o \ + vgatile32C.o vgatile32G.o \ + vgatileoddC.o vgatileoddG.o \ + vgafillsp.o vgasetsp.o \ + vgapntwin.o vgapwinS.o vgaBitBlt1.o \ + vgazerarcC.o vgazerarcX.o vgazerarcG.o \ + vgafillarcC.o vgafillarcG.o \ + vgategblt.o vgabstore.o vga8cppl.o \ + vgateblt8.o vgateblt8S.o vgaglblt8.o vgaglrop8.o \ + vgarctstp8.o vgarctstp8S.o vgapolypnt.o \ + vgaline.o vgalineS.o vgabresd.o \ + vgalined.o vgasegd.o vgaseg.o vgasegS.o \ + vgabitblt.o vgabltC.o vgabltCS.o vgabltX.o \ + vgabltO.o vgabltG.o \ + vgapush8.o vgaply1rctC.o vgaply1rctG.o $(STIPPLEOBJ) vgafuncs.o \ + SpeedUpBlt.o $(BOBJS) \ + vgaBanks.o $(FOBJS) vgaHW.o vga.o vgaCmap.o \ + vgaPCI.o vgatables.o + + INCLUDES = -I. -I$(XF98COMSRC) -I$(XF86OSSRC) -I$(XF86HWSRC) \ + -I$(SERVERSRC)/cfb -I$(SERVERSRC)/mfb -I$(SERVERSRC)/mi \ + -I$(SERVERSRC)/include -I$(XINCLUDESRC) -I$(FONTINCSRC) \ + -I$(XF86SRC)/xaa + LINTLIBS = ../../../dix/llib-ldix.ln ../../../os/llib-los.ln \ + ../../mfb/llib-lmfb.ln ../../mi/llib-lmi.ln + + #ifdef DirtyStartup + STARTUPDEFINES = -DDIRTY_STARTUP + #endif + + DEFINES = $(SPEEDUPDEFINES) $(STARTUPDEFINES) -DPSZ=8 -DPC98 VGADEFINES + + #ifdef i386Architecture + SUDEFINE = -DSPEEDUP + #endif + + SubdirLibraryRule($(OBJS)) + NormalLibraryObjectRule() + NormalAsmObjectRule() + + NormalLintTarget($(SRCS)) + + LinkSourceFile(Design,$(XF86SRC)/vga256/vga) + LinkSourceFile(vga.c,$(XF86SRC)/vga256/vga) + LinkSourceFile(vga.h,$(XF86SRC)/vga256/vga) + LinkSourceFile(vga256.h,$(XF86SRC)/vga256/vga) + LinkSourceFile(vga8cppl.c,$(XF86SRC)/vga256/vga) + LinkSourceFile(vgaAsm.h,$(XF86SRC)/vga256/vga) + LinkSourceFile(vgaBank.h,$(XF86SRC)/vga256/vga) + LinkSourceFile(vgaBank.s,$(XF86SRC)/vga256/vga) + LinkSourceFile(vgaCmap.c,$(XF86SRC)/vga256/vga) + LinkSourceFile(vgaHW.c,$(XF86SRC)/vga256/vga) + LinkSourceFile(vgaPCI.c,$(XF86SRC)/vga256/vga) + LinkSourceFile(vgaPCI.h,$(XF86SRC)/vga256/vga) + LinkSourceFile(vgabitblt.c,$(XF86SRC)/vga256/vga) + LinkSourceFile(vgablt.c,$(XF86SRC)/vga256/vga) + LinkSourceFile(vgabltC.c,$(XF86SRC)/vga256/vga) + LinkSourceFile(vgabresd.c,$(XF86SRC)/vga256/vga) + LinkSourceFile(vgabstore.c,$(XF86SRC)/vga256/vga) + LinkSourceFile(vgafillarc.c,$(XF86SRC)/vga256/vga) + LinkSourceFile(vgafillrct.c,$(XF86SRC)/vga256/vga) + LinkSourceFile(vgafillsp.c,$(XF86SRC)/vga256/vga) + LinkSourceFile(vgafuncs.c,$(XF86SRC)/vga256/vga) + LinkSourceFile(vgagc.c,$(XF86SRC)/vga256/vga) + LinkSourceFile(vgagetsp.c,$(XF86SRC)/vga256/vga) + LinkSourceFile(vgaglblt8.c,$(XF86SRC)/vga256/vga) + LinkSourceFile(vgaimage.c,$(XF86SRC)/vga256/vga) + LinkSourceFile(vgaline.c,$(XF86SRC)/vga256/vga) + LinkSourceFile(vgalined.c,$(XF86SRC)/vga256/vga) + LinkSourceFile(vgaply1rct.c,$(XF86SRC)/vga256/vga) + LinkSourceFile(vgapntwin.c,$(XF86SRC)/vga256/vga) + LinkSourceFile(vgapolypnt.c,$(XF86SRC)/vga256/vga) + LinkSourceFile(vgapush8.c,$(XF86SRC)/vga256/vga) + LinkSourceFile(vgapwinS.c,$(XF86SRC)/vga256/vga) + LinkSourceFile(vgarctstp8.c,$(XF86SRC)/vga256/vga) + LinkSourceFile(vgascrinit.c,$(XF86SRC)/vga256/vga) + LinkSourceFile(vgasetsp.c,$(XF86SRC)/vga256/vga) + LinkSourceFile(vgasolid.c,$(XF86SRC)/vga256/vga) + LinkSourceFile(vgatables.c,$(XF86SRC)/vga256/vga) + LinkSourceFile(vgateblt8.c,$(XF86SRC)/vga256/vga) + LinkSourceFile(vgategblt.c,$(XF86SRC)/vga256/vga) + LinkSourceFile(vgatile32.c,$(XF86SRC)/vga256/vga) + LinkSourceFile(vgatileodd.c,$(XF86SRC)/vga256/vga) + LinkSourceFile(vgawindow.c,$(XF86SRC)/vga256/vga) + LinkSourceFile(vgazerarc.c,$(XF86SRC)/vga256/vga) + + #define EnhancedDir $(XF86SRC)/vga256/enhanced + + ObjectFromSpecialSource(vgaBanks,EnhancedDir/gBanks,NullParameter) + #ifdef i386Architecture + ObjectFromSpecialAsmSource(BitBlt,EnhancedDir/suBitBlt,NullParameter) + ObjectFromSpecialAsmSource(BitBlt2,EnhancedDir/suBBlt2,NullParameter) + ObjectFromSpecialAsmSource(Box,EnhancedDir/suBox,NullParameter) + ObjectFromSpecialAsmSource(Line,EnhancedDir/suLine,NullParameter) + ObjectFromSpecialAsmSource(VHLine,EnhancedDir/suVHLine,NullParameter) + ObjectFromSpecialAsmSource(vgabres,EnhancedDir/fLineBres,NullParameter) + ObjectFromSpecialAsmSource(vgalineH,EnhancedDir/fLineH,NullParameter) + ObjectFromSpecialAsmSource(vgalineV,EnhancedDir/fLineV,NullParameter) + LinkSourceFile(fBitBlt.s,EnhancedDir) + LinkSourceFile(fFill.s,EnhancedDir) + LinkSourceFile(fFillSet.s,EnhancedDir) + #else + LinkSourceFile(vgaBltFillc.c,EnhancedDir) + LinkSourceFile(vgaLinec.c,EnhancedDir) + #endif + LinkFile(vgaBitBlt1.c,EnhancedDir/vgaBitBlt.c) + LinkSourceFile(SpeedUpBlt.c,EnhancedDir) + LinkSourceFile(vgaFasm.h,EnhancedDir) + + ObjectFromSpecialSource(vgaseg,vgaline,-DPOLYSEGMENT) + ObjectFromSpecialSource(vgasegd,vgalined,-DPOLYSEGMENT) + ObjectFromSpecialSource(vgaglrop8,vgaglblt8,-DGLYPHROP) + SpecialObjectRule(vgaglblt8.o,vgaglblt8.c,$(STIPPLEDEF)) + + ObjectFromSpecialSource(vgalineS,vgaline,$(SUDEFINE)) + ObjectFromSpecialSource(vgasegS,vgaline,$(SUDEFINE) -DPOLYSEGMENT) + ObjectFromSpecialSource(vgateblt8S,vgateblt8,$(SUDEFINE)) + ObjectFromSpecialSource(vgarctstp8S,vgarctstp8,$(SUDEFINE)) + + ObjectFromSpecialSource(vgafillarcC,vgafillarc,-DRROP=GXcopy) + ObjectFromSpecialSource(vgafillarcG,vgafillarc,-DRROP=GXset) + + ObjectFromSpecialSource(vgazerarcC,vgazerarc,-DRROP=GXcopy) + ObjectFromSpecialSource(vgazerarcX,vgazerarc,-DRROP=GXxor) + ObjectFromSpecialSource(vgazerarcG,vgazerarc,-DRROP=GXset) + + ObjectFromSpecialSource(vgabltCS,vgablt,-DMROP=Mcopy $(SUDEFINE)) + ObjectFromSpecialSource(vgabltX,vgablt,-DMROP=Mxor) + ObjectFromSpecialSource(vgabltO,vgablt,-DMROP=Mor) + ObjectFromSpecialSource(vgabltG,vgablt,-DMROP=0) + + ObjectFromSpecialSource(vgasolidC,vgasolid,-DRROP=GXcopy) + ObjectFromSpecialSource(vgasolidCS,vgasolid,-DRROP=GXcopy $(SUDEFINE)) + ObjectFromSpecialSource(vgasolidX,vgasolid,-DRROP=GXxor) + ObjectFromSpecialSource(vgasolidO,vgasolid,-DRROP=GXor) + ObjectFromSpecialSource(vgasolidA,vgasolid,-DRROP=GXand) + ObjectFromSpecialSource(vgasolidG,vgasolid,-DRROP=GXset) + + ObjectFromSpecialSource(vgatile32C,vgatile32,-DMROP=Mcopy) + ObjectFromSpecialSource(vgatile32G,vgatile32,-DMROP=0) + + ObjectFromSpecialSource(vgatileoddC,vgatileodd,-DMROP=Mcopy) + ObjectFromSpecialSource(vgatileoddG,vgatileodd,-DMROP=0) + + ObjectFromSpecialSource(vgaply1rctC,vgaply1rct,-DRROP=GXcopy) + ObjectFromSpecialSource(vgaply1rctG,vgaply1rct,-DRROP=GXset) + + #ifdef i386Architecture + ObjectFromSpecialAsmSource(fFillAnd,fFill,-DRROP=GXAnd) + ObjectFromSpecialAsmSource(fFillCopy,fFill,-DRROP=GXCopy) + ObjectFromSpecialAsmSource(fFillOr,fFill,-DRROP=GXOr) + ObjectFromSpecialAsmSource(fFillXor,fFill,-DRROP=GXXor) + #endif + + InstallLinkKitNonExecFile(vga.h,$(XF98LINKKITDIR)/drivers98) + InstallLinkKitNonExecFile(vgaBank.h,$(XF98LINKKITDIR)/drivers98) + #ifndef DontInstallPC98Version + InstallLinkKitNonExecFile(vga.h,$(XF98LINKKITDIR)/include) + InstallLinkKitNonExecFile(vga256.h,$(XF98LINKKITDIR)/include) + InstallLinkKitNonExecFile(vgaFasm.h,$(XF98LINKKITDIR)/include) + InstallLinkKitNonExecFile(vgaHW.c,$(XF98LINKKITDIR)/VGADriverDoc) + InstallLinkKitNonExecFile(vgaPCI.h,$(XF98LINKKITDIR)/include) + #endif + + #ifndef OS2Architecture + DependTarget() + #endif *** ./xfree98/xaa/Imakefile@@/PUBLIC-LATEST Sun Jul 20 13:54:51 1997 --- xc/programs/Xserver/hw/xfree98/xaa/Imakefile Fri Mar 6 14:14:44 1998 *************** *** 1,24 **** ! XCOMM $TOG: Imakefile /main/1 1997/07/20 13:54:53 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree98/xaa/Imakefile,v 3.6 1997/01/14 22:22:34 dawes Exp $ #include <Server.tmpl> #define IHaveSubdirs ! BPPSRCS = xaavga256/?*.c xaa8/?*.c xaa16/?*.c xaa32/?*.c ! GENSRCS = xf86initac.c \ xf86cparea.c xf86frect.c xf86spans.c xf86text.c xf86window.c \ xf86defs.c xf86pcache.c xf86farc.c xf86fpoly.c \ xf86expblt.c xf86expblM.c xf86bitmap.c xf86plane.c \ xf86orect.c xf86line.c xf86seg.c \ xf86bench.c xf86line2.c xf86seg2.c \ ! xf86expblF.c xf86expbFM.c xf86tables.c xf86stip.c ! BPPOBJS = xaavga256/xaavga256.o xaa8/xaa8.o xaa16/xaa16.o xaa32/xaa32.o GENOBJS = xf86initac.o \ xf86cparea.o xf86frect.o xf86spans.o xf86text.o xf86window.o \ --- 1,26 ---- ! XCOMM $TOG: Imakefile /main/2 1998/03/06 14:16:22 kaleb $ ! XCOMM $XFree86: xc/programs/Xserver/hw/xfree98/xaa/Imakefile,v 3.6.2.2 1998/02/15 16:09:48 hohndel Exp $ #include <Server.tmpl> #define IHaveSubdirs ! BPPSRCS = xaavga256/?*.c xaa8/?*.c xaa16/?*.c xaa24/?*.c xaa32/?*.c ! GENSRCS = xf86initac.c \ xf86cparea.c xf86frect.c xf86spans.c xf86text.c xf86window.c \ xf86defs.c xf86pcache.c xf86farc.c xf86fpoly.c \ xf86expblt.c xf86expblM.c xf86bitmap.c xf86plane.c \ xf86orect.c xf86line.c xf86seg.c \ xf86bench.c xf86line2.c xf86seg2.c \ ! xf86expblF.c xf86expbFM.c xf86tables.c xf86stip.c xf86dseg.c \ ! xf86dline.c xf86wline.c xf86cursor.c ! BPPOBJS = xaavga256/xaavga256.o xaa8/xaa8.o xaa16/xaa16.o xaa24/xaa24.o \ ! xaa32/xaa32.o GENOBJS = xf86initac.o \ xf86cparea.o xf86frect.o xf86spans.o xf86text.o xf86window.o \ *************** *** 26,35 **** xf86expblt.o xf86expblM.o xf86bitmap.o xf86plane.o \ xf86orect.o xf86line.o xf86seg.o \ xf86bench.o xf86line2.o xf86seg2.o \ ! xf86expblF.o xf86expbFM.o xf86tables.o xf86stip.o #ifdef i386Architecture ! SRCS = $(GENSRCS) xf86txtblt.s xf86txtblM.s OBJS = $(GENOBJS) xf86txtblt.o xf86txtblM.o #else SRCS = $(GENSRCS) --- 28,38 ---- xf86expblt.o xf86expblM.o xf86bitmap.o xf86plane.o \ xf86orect.o xf86line.o xf86seg.o \ xf86bench.o xf86line2.o xf86seg2.o \ ! xf86expblF.o xf86expbFM.o xf86tables.o xf86stip.o xf86dseg.o \ ! xf86dline.o xf86wline.o xf86cursor.o #ifdef i386Architecture ! SRCS = $(GENSRCS) xf86txtblt.s xf86txtblM.s OBJS = $(GENOBJS) xf86txtblt.o xf86txtblM.o #else SRCS = $(GENSRCS) *************** *** 36,44 **** OBJS = $(GENOBJS) #endif ! SUBDIRS = xaavga256 xaa8 xaa16 xaa32 ! DONES = xaavga256/DONE xaa8/DONE xaa16/DONE xaa32/DONE INCLUDES = -I$(XF86COMSRC) -I$(XF86OSSRC) -I$(XF86HWSRC) \ -I$(XF86SRC)/vga256/vga \ --- 39,47 ---- OBJS = $(GENOBJS) #endif ! SUBDIRS = xaavga256 xaa8 xaa16 xaa24 xaa32 ! DONES = xaavga256/DONE xaa8/DONE xaa16/DONE xaa24/DONE xaa32/DONE INCLUDES = -I$(XF86COMSRC) -I$(XF86OSSRC) -I$(XF86HWSRC) \ -I$(XF86SRC)/vga256/vga \ *************** *** 46,51 **** --- 49,58 ---- -I$(SERVERSRC)/include -I$(XINCLUDESRC) -I$(FONTINCSRC) + #if HasGnuMake + $(DONES): $(SUBDIRS) + #endif + NormalDepLibraryTarget(xaa,$(OBJS) $(SUBDIRS) $(DONES),$(OBJS)) NormalLibraryObjectRule() NormalAsmObjectRule() *************** *** 57,63 **** --- 64,74 ---- LinkSourceFile(xf86bench.c,$(XF86SRC)/xaa) LinkSourceFile(xf86bitmap.c,$(XF86SRC)/xaa) LinkSourceFile(xf86cparea.c,$(XF86SRC)/xaa) + LinkSourceFile(xf86cursor.c,$(XF86SRC)/xaa) + LinkSourceFile(xf86cursor.h,$(XF86SRC)/xaa) LinkSourceFile(xf86defs.c,$(XF86SRC)/xaa) + LinkSourceFile(xf86dline.c,$(XF86SRC)/xaa) + LinkSourceFile(xf86dseg.c,$(XF86SRC)/xaa) LinkSourceFile(xf86expblt.c,$(XF86SRC)/xaa) LinkSourceFile(xf86expblt.h,$(XF86SRC)/xaa) LinkSourceFile(xf86farc.c,$(XF86SRC)/xaa) *************** *** 84,89 **** --- 95,101 ---- LinkSourceFile(xf86text.c,$(XF86SRC)/xaa) LinkSourceFile(xf86txtblt.s,$(XF86SRC)/xaa) LinkSourceFile(xf86window.c,$(XF86SRC)/xaa) + LinkSourceFile(xf86wline.c,$(XF86SRC)/xaa) LinkSourceFile(xf86xaa.h,$(XF86SRC)/xaa) ObjectFromSpecialSource(xf86expblM, xf86expblt, -DMSBFIRST) *************** *** 102,107 **** --- 114,122 ---- #ifndef DontInstallPC98Version InstallLinkKitLibrary(xaa,$(LINKKITDIR)/lib) + InstallLinkKitNonExecFile(xf86cursor.h,$(LINKKITDIR)/include) + InstallLinkKitNonExecFile(xf86expblt.h,$(LINKKITDIR)/include) + InstallLinkKitNonExecFile(xf86local.h,$(LINKKITDIR)/include) InstallLinkKitNonExecFile(xf86scrin.h,$(LINKKITDIR)/include) InstallLinkKitNonExecFile(xf86xaa.h,$(LINKKITDIR)/include) #endif *** /dev/null Tue Jun 30 15:46:29 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/s3bank.s Fri Mar 6 16:53:37 1998 *************** *** 0 **** --- 1,90 ---- + /* $TOG: s3bank.s /main/1 1998/03/06 16:55:15 kaleb $ */ + + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/s3bank.s,v 1.1.2.1 1998/02/07 10:05:40 hohndel Exp $ */ + /* + * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany. + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Thomas Roell not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Thomas Roell makes no representations + * about the suitability of this software for any purpose. It is provided + * "as is" without express or implied warranty. + * + * THOMAS ROELL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THOMAS ROELL BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + * + * Author: Thomas Roell, roell@informatik.tu-muenchen.de + * + */ + + /* + * These are here the very lowlevel VGA bankswitching routines. + * The segment to switch to is passed via %eax. Only %eax and %edx my be used + * without saving the original contents. + * + * WHY ASSEMBLY LANGUAGE ??? + * + * These routines must be callable by other assembly routines. But I don't + * want to have the overhead of pushing and poping the normal stack-frame. + */ + + /* + * first we have here a mirror for the segment register. That's because a + * I/O read costs so much more time, that is better to keep the value of it + * in memory. + */ + + #include "assyntax.h" + + FILE("s3bank.s") + + AS_BEGIN + + SEG_DATA + Segment: + D_BYTE 0 + + + SEG_TEXT + + ALIGNTEXT4 + GLOBL GLNAME(S3SetRead) + GLNAME(S3SetRead): + MOV_B (AL, CONTENT(Segment)) + /* Segment b0..3 -> CRTC[0x35] b0..3 */ + MOV_B (CONST(0x35), AL) + MOV_L (CONST(0x3D4), EDX) + OUT_B + MOV_L (CONST(0x3D5), EDX) + IN_B + AND_B (CONST(0xF0), AL) + MOV_B (CONTENT(Segment), AH) + AND_B (CONST(0x0F), AH) + OR_B (AH, AL) + OUT_B + /* Segment b4.5 -> CRTC[0x51] b2.3 */ + MOV_B (CONST(0x51), AL) + MOV_L (CONST(0x3D4), EDX) + OUT_B + MOV_L (CONST(0x3D5), EDX) + IN_B + AND_B (CONST(0xF3), AL) + MOV_B (CONTENT(Segment), AH) + AND_B (CONST(0x30), AH) + ROR_B (CONST(2), AH) + OR_B (AH, AL) + OUT_B + + RET *** /dev/null Tue Jun 30 15:46:32 1998 --- xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/s3driver.c Fri Mar 6 16:53:45 1998 *************** *** 0 **** --- 1,377 ---- + /* $TOG: s3driver.c /main/1 1998/03/06 16:55:23 kaleb $ */ + + + + + /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/s3driver.c,v 1.1.2.2 1998/02/15 16:09:37 hohndel Exp $ */ + /* + * + * Copyright 1995-1997 The XFree86 Project, Inc. + * + */ + /* + + Written mostly by Mark Vojkovich (mvojkovi@ucsd.edu) + With pieces stolen from XF86_S3 + + */ + + + #include "X.h" + #include "input.h" + #include "screenint.h" + + #include "compiler.h" + #include "xf86.h" + #include "xf86Priv.h" + #include "xf86_OSlib.h" + #include "xf86_HWlib.h" + #include "xf86_PCI.h" + #include "vga.h" + #include "vgaPCI.h" + + #ifdef XFreeXDGA + #include "X.h" + #include "Xproto.h" + #include "scrnintstr.h" + #include "servermd.h" + #define _XF86DGA_SERVER_ + #include "extensions/xf86dgastr.h" + #endif + + #define XCONFIG_FLAGS_ONLY + #include "xf86_Config.h" + + #include "s3reg.h" + #include "s3.h" + #include "mipointer.h" + #include "xf86cursor.h" + + /* Not all of these used, I'll weed out the unecessary ones later (MArk) */ + + int s3maxRawClock = 0; + int s3BppDisplayWidth; + int s3CursorBytes; + int s3maxDisplayWidth; + int s3maxDisplayHeight; + int s3numClocks; + int s3ScissB; + int s3ScissR; + int s3HDisplay; + int s3DisplayWidth = 0; + unsigned short s3ChipRev; + unsigned short s3ChipId; + short s3BiosVendor = UNKNOWN_BIOS; + short s3RamdacType = UNKNOWN_DAC; + short s3Bpp = 1; + char s3Mbanks; + char *s3ClockChipProbed = XCONFIG_GIVEN; + Bool s3PCIRetry = FALSE; + Bool s3Localbus = FALSE; + Bool s3VLB = FALSE; + Bool s3DAC8Bit = FALSE; + Bool s3DACSyncOnGreen = FALSE; + Bool s3PixelMultiplexing = FALSE; + Bool s3Bt485PixMux = FALSE; + Bool s3ATT498PixMux = FALSE; + Bool s3PowerSaver = FALSE; + Bool s3Initialized = FALSE; + Bool s3clockDoublingPossible = FALSE; + Bool s3newmmio = FALSE; + unsigned char s3Port31; + unsigned char s3Port51; + unsigned char s3Port59 = 0x00; + unsigned char s3Port5A = 0x00; + unsigned char s3LinApOpt; /* bottom of CR58 */ + unsigned char s3SAM256; /* top of CR58 */ + unsigned char s3SwapBits[256]; + unsigned char s3DACBoarder = 0xff; + ScreenPtr s3savepScreen; + DisplayModePtr s3CurrentMode = NULL; + + static LUTENTRY s3SavedPalette[256]; + + pointer s3MmioMem = NULL; + + Bool (*s3ClockSelectFunc) (); + + int vgaCRIndex; + int vgaCRReg; + + vgaVideoChipRec s3InfoRec = { + S3Probe, /* Bool (* ChipProbe)() */ + S3Ident, /* char * (* ChipIdent)() */ + S3EnterLeave, /* void (* ChipEnterLeave)() */ + S3Init, /* Bool (* ChipInit)() */ + S3ValidMode, /* int (* ChipValidMode)() */ + S3Save, /* void * (* ChipSave)() */ + S3Restore, /* void (* ChipRestore)() */ + S3Adjust, /* void (* ChipAdjust)() */ + vgaHWSaveScreen, /* void (* ChipSaveScreen)() */ + (void(*)())NoopDDA, /* void (* ChipGetMode)() */ + S3FbInit, /* void (* ChipFbInit)() */ + S3SetRead, /* void (* ChipSetRead)() */ + S3SetRead, /* void (* ChipSetWrite)() */ + S3SetRead, /* void (* ChipSetReadWrite)() */ + 0x10000, /* int ChipMapSize */ + 0x10000, /* int ChipSegmentSize */ + 16, /* int ChipSegmentShift */ + 0xFFFF, /* int ChipSegmentMask */ + 0x00000, 0x10000, /* int ChipReadBottom, int ChipReadTop */ + 0x00000, 0x10000, /* int ChipWriteBottom, int ChipWriteTop */ + FALSE, /* Bool ChipUse2Banks */ + VGA_DIVIDE_VERT, /* int ChipInterlaceType */ + {0,}, /* OFlagSet ChipOptionFlags */ + 8, /* int ChipRounding */ + FALSE, /* Bool ChipUseLinearAddressing */ + 0, /* int ChipLinearBase */ + 0, /* int ChipLinearSize */ + /* + * This is TRUE if the driver has support for the given depth for + * the detected configuration. It must be set in the Probe function. + * It most cases it should be FALSE. + */ + TRUE, /* 16bpp */ + TRUE, /* 24bpp */ + TRUE, /* 32bpp */ + NULL, /* DisplayModePtr ChipBuiltinModes */ + 1, /* int ChipClockMulFactor */ + 1 /* int ChipClockDivFactor */ + }; + + short s3alu[16] = + { + MIX_0, + MIX_AND, + MIX_SRC_AND_NOT_DST, + MIX_SRC, + MIX_NOT_SRC_AND_DST, + MIX_DST, + MIX_XOR, + MIX_OR, + MIX_NOR, + MIX_XNOR, + MIX_NOT_DST, + MIX_SRC_OR_NOT_DST, + MIX_NOT_SRC, + MIX_NOT_SRC_OR_DST, + MIX_NAND, + MIX_1 + }; + + /* + * s3Probe -- + * + */ + + /* moved to s3probe.c */ + + /* + * s3Ident -- + * + */ + + char * S3Ident(int n) + { + static char *chipsets[] = {"s3_svga" }; + + if (n + 1 > sizeof(chipsets) / sizeof(char *)) + return(NULL); + else + return(chipsets[n]); + } + + void S3EnterLeave(Bool enter) + { + unsigned char tmp; + static Bool s3VTSwitchBack = FALSE; + + #ifdef S3_DEBUG + ErrorF("In S3EnterLeave(%s)\n", enter ? "ENTER" : "LEAVE"); + #endif + + #ifdef XFreeXDGA + if ((vga256InfoRec.directMode & XF86DGADirectGraphics) && !enter) { + S3SavePalette(s3SavedPalette); + s3VTSwitchBack = TRUE; + if(XAACursorInfoRec.Flags & USE_HARDWARE_CURSOR) + XAACursorInfoRec.HideCursor(); + return; + } + #endif + + if (enter) { + xf86EnableIOPorts(vga256InfoRec.scrnIndex); + + vgaIOBase = (inb(0x3CC) & 0x01) ? 0x3D0 : 0x3B0; + vgaCRIndex = vgaIOBase + 4; + vgaCRReg = vgaIOBase + 5; + + S3Unlock(); + + /* Unprotect CRTC[0-7] */ + outb(vgaCRIndex, 0x11); + tmp = inb(vgaCRReg) & 0x7F; + outb(vgaCRReg, tmp); + + /* needed for virtual console switchback since SVGA server + doesn't reinit but restores */ + if(s3VTSwitchBack) { + if(s3CurrentMode) { + s3Initialized = FALSE; + if(!S3Init(s3CurrentMode)) { + /* what *should* we do here? MArk */ + FatalError("Whoops! Oversight in EnterLeave(ENTER)\n"); + } + } + + S3RestorePalette(s3SavedPalette); + s3VTSwitchBack = FALSE; + } + + } else { + + if(s3Initialized) { + S3SavePalette(s3SavedPalette); + s3VTSwitchBack = TRUE; + S3CleanUp(); + s3Initialized = FALSE; + } + + + /* Protect CRTC[0-7] */ + outb(vgaIOBase + 4, 0x11); + tmp = (inb(vgaIOBase + 5) & 0x7F) | 0x80; + outb(vgaIOBase + 5, tmp); + + /* I suppose I should probably lock the S3 here (MArk) */ + + xf86DisableIOPorts(vga256InfoRec.scrnIndex); + } + + } + + + /* + * S3Init -- + * + */ + + /* moved to s3init.c */ + + /* + * S3ValidMode -- + * + */ + + /* moved to s3probe.c */ + + + /* + * S3Save -- + * + * S3Restore -- + * + */ + + /* moved to s3save.c */ + + + + void S3Adjust(int x, int y) + { + int Base, origBase; + unsigned char tmp; + + if (OFLG_ISSET(OPTION_SHOWCACHE, &vga256InfoRec.options)) { + if(y) y += 128; + } + + if (x > s3DisplayWidth - s3HDisplay) + x = s3DisplayWidth - s3HDisplay; + + /* so may S3 cards have problems with some odd base addresses, + * to catch them all only even base values will be used. + */ + + origBase = (y * s3DisplayWidth + x) * s3Bpp; + Base = (origBase >> 2) & ~1; + + if (S3_964_SERIES(s3ChipId)) { + switch(s3RamdacType) { + case BT485_DAC: + case ATT20C505_DAC: + if ((Base & 0x3f) >= 0x3c) + Base = (Base & ~0x3f) | 0x3b; + else if (s3Bpp>1 && (Base & 0x3f) == 0x3a) + Base = (Base & ~0x3f) | 0x39; + else if (s3Bpp>2 && (Base & 0x1f) == 0x1a) + Base = (Base & ~0x1f) | 0x19; + break; + case TI3025_DAC: + case TI3026_DAC: + case TI3030_DAC: + case IBMRGB524_DAC: + case IBMRGB525_DAC: + case IBMRGB528_DAC: + { + int px, py, a; + miPointerPosition(&px, &py); + if (s3Bpp == 3) { + if (DAC_IS_TI3030 || DAC_IS_IBMRGB528) + a = 12; + else + a = 6; + if (px-x > s3HDisplay/2) + Base = ((origBase + (a-1)*4) >> 2) & ~1; + Base -= Base % a; + } else { + if (s3Bpp==1 && !DAC_IS_TI3030 && !DAC_IS_IBMRGB528) + a = 4-1; + else + a = 8-1; + if (px-x > s3HDisplay/2) + Base = ((origBase + a*4) >> 2) & ~1; + Base &= ~a; + } + } + default: + break; + } + } + outb(vgaCRIndex, 0x31); + outb(vgaCRReg, ((Base & 0x030000) >> 12) | s3Port31); + s3Port51 &= ~0x03; + s3Port51 |= ((Base & 0x0c0000) >> 18); + outb(vgaCRIndex, 0x51); + /* Don't override current bank selection */ + tmp = (inb(vgaCRReg) & ~0x03) | (s3Port51 & 0x03); + outb(vgaCRReg, tmp); + + outw(vgaCRIndex, (Base & 0x00FF00) | 0x0C); + outw(vgaCRIndex, ((Base & 0x00FF) << 8) | 0x0D); + + #ifdef XFreeXDGA + if (vga256InfoRec.directMode & XF86DGADirectGraphics) { + /* Wait until vertical retrace is in progress. */ + S3RetraceWait(); + } + #endif + + } + + /* + * S3FbInit -- + * + */ + + /* moved to s3fbinit.c */ + + /* + * S3SetRead -- + * + */ + + /* moved to s3bank.s */ + +