<def f='src/src/sys/external/bsd/drm2/dist/drm/radeon/atombios.h' l='5214' ll='5276'/>
<size>512</size>
<doc f='src/src/sys/external/bsd/drm2/dist/drm/radeon/atombios.h' l='5077'>/**********************************************************************************************************************
  ATOM_INTEGRATED_SYSTEM_INFO_V1_7 Description
ulBootUpEngineClock:              VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock
ulDentistVCOFreq:                 Dentist VCO clock in 10kHz unit. 
ulBootUpUMAClock:                 System memory boot up clock frequency in 10Khz unit. 
sDISPCLK_Voltage:                 Report Display clock voltage requirement.
 
ulBootUpReqDisplayVector:         VBIOS boot up display IDs, following are supported devices in Trinity projects:
                                  ATOM_DEVICE_CRT1_SUPPORT                  0x0001
                                  ATOM_DEVICE_DFP1_SUPPORT                  0x0008 
                                  ATOM_DEVICE_DFP6_SUPPORT                  0x0040 
                                  ATOM_DEVICE_DFP2_SUPPORT                  0x0080       
                                  ATOM_DEVICE_DFP3_SUPPORT                  0x0200       
                                  ATOM_DEVICE_DFP4_SUPPORT                  0x0400        
                                  ATOM_DEVICE_DFP5_SUPPORT                  0x0800
                                  ATOM_DEVICE_LCD1_SUPPORT                  0x0002
ulOtherDisplayMisc:      	        bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS. 
                                        =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS. 
                                  bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS
                                        =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS
                                  bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS
                                        =1: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is supported by SBIOS
                                  bit[3]=0: VBIOS fast boot is disable
                                        =1: VBIOS fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD panel is connect and LID is open)
ulGPUCapInfo:                     bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode.
                                        =1: TMDS/HDMI Coherent Mode use signel PLL mode.
                                  bit[1]=0: DP mode use cascade PLL mode ( New for Trinity )
                                        =1: DP mode use single PLL mode
                                  bit[3]=0: Enable AUX HW mode detection logic
                                        =1: Disable AUX HW mode detection logic
                                      
ulSB_MMIO_Base_Addr:              Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage.

usRequestedPWMFreqInHz:           When it&apos;s set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). 
                                  Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0;
                                  
                                  When it&apos;s set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below:
                                  1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use;
                                  VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result,
                                  Changing BL using VBIOS function is functional in both driver and non-driver present environment; 
                                  and enabling VariBri under the driver environment from PP table is optional.

                                  2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating
                                  that BL control from GPU is expected.
                                  VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1
                                  Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but
                                  it&apos;s per platform 
                                  and enabling VariBri under the driver environment from PP table is optional.

ucHtcTmpLmt:                      Refer to D18F3x64 bit[22:16], HtcTmpLmt. 
                                  Threshold on value to enter HTC_active state.
ucHtcHystLmt:                     Refer to D18F3x64 bit[27:24], HtcHystLmt. 
                                  To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt.
ulMinEngineClock:                 Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings.
ulSystemConfig:                   Bit[0]=0: PCIE Power Gating Disabled 
                                        =1: PCIE Power Gating Enabled
                                  Bit[1]=0: DDR-DLL shut-down feature disabled.
                                         1: DDR-DLL shut-down feature enabled.
                                  Bit[2]=0: DDR-PLL Power down feature disabled.
                                         1: DDR-PLL Power down feature enabled.                                 
ulCPUCapInfo:                     TBD
usNBP0Voltage:                    VID for voltage on NB P0 State
usNBP1Voltage:                    VID for voltage on NB P1 State  
usNBP2Voltage:                    VID for voltage on NB P2 State
usNBP3Voltage:                    VID for voltage on NB P3 State  
usBootUpNBVoltage:                Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement.
usExtDispConnInfoOffset:          Offset to sExtDispConnInfo inside the structure
usPanelRefreshRateRange:          Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set
                                  to indicate a range.
                                  SUPPORTED_LCD_REFRESHRATE_30Hz          0x0004
                                  SUPPORTED_LCD_REFRESHRATE_40Hz          0x0008
                                  SUPPORTED_LCD_REFRESHRATE_50Hz          0x0010
                                  SUPPORTED_LCD_REFRESHRATE_60Hz          0x0020
ucMemoryType:                     [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved.
ucUMAChannelNumber:      	        System memory channel numbers. 
ulCSR_M3_ARB_CNTL_DEFAULT[10]:    Arrays with values for CSR M3 arbiter for default
ulCSR_M3_ARB_CNTL_UVD[10]:        Arrays with values for CSR M3 arbiter for UVD playback.
ulCSR_M3_ARB_CNTL_FS3D[10]:       Arrays with values for CSR M3 arbiter for Full Screen 3D applications.
sAvail_SCLK[5]:                   Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high  
ulGMCRestoreResetTime:            GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. 
ulMinimumNClk:                    Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz. 
ulIdleNClk:                       NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
ulDDR_DLL_PowerUpTime:            DDR PHY DLL power up time. Unit in ns.
ulDDR_PLL_PowerUpTime:            DDR PHY PLL power up time. Unit in ns.
usPCIEClkSSPercentage:            PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%.
usPCIEClkSSType:                  PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread.
usLvdsSSPercentage:               LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. 
usLvdsSSpreadRateIn10Hz:          LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 
usHDMISSPercentage:               HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%,  =0, use VBIOS default setting. 
usHDMISSpreadRateIn10Hz:          HDMI Spread Spectrum frequency in unit of 10Hz,  =0, use VBIOS default setting. 
usDVISSPercentage:                DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%,  =0, use VBIOS default setting. 
usDVISSpreadRateIn10Hz:           DVI Spread Spectrum frequency in unit of 10Hz,  =0, use VBIOS default setting. 
usMaxLVDSPclkFreqInSingleLink:    Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz
ucLVDSMisc:                       [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode
                                  [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped
                                  [bit2] LVDS 888bit per color mode  =0: 666 bit per color =1:888 bit per color
                                  [bit3] LVDS parameter override enable  =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used
                                  [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low )
                                  [bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to overwrite Traivs register LVDS_CTRL_4
ucTravisLVDSVolAdjust             When ucLVDSMisc[5]=1,it means platform SBIOS want to overwrite TravisLVDSVoltage. Then VBIOS will use ucTravisLVDSVolAdjust 
                                  value to program Travis register LVDS_CTRL_4
ucLVDSPwrOnSeqDIGONtoDE_in4Ms:    LVDS power up sequence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE ).
                                  =0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON-&gt;DE-&gt;VARY_BL-&gt;BLON. 
                                  This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
ucLVDSPwrOnDEtoVARY_BL_in4Ms:     LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable signal active( VARY_BL ).  
                                  =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON-&gt;DE-&gt;VARY_BL-&gt;BLON. 
                                  This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.

ucLVDSPwrOffVARY_BLtoDE_in4Ms:    LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCDVCC (DIGON) off. 
                                  =0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON-&gt;VARY_BL-&gt;DE-&gt;DIGON
                                  This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.

ucLVDSPwrOffDEtoDIGON_in4Ms:      LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable ( DE ) signal off. 
                                  =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON-&gt;VARY_BL-&gt;DE-&gt;DIGON
                                  This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.

ucLVDSOffToOnDelay_in4Ms:         LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal active. 
                                  =0 means to use VBIOS default delay which is 125 ( 500ms ).
                                  This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.

ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms:
                                  LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active. 
                                  =0 means to use VBIOS default delay which is 0 ( 0ms ).
                                  This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.

ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms:  
                                  LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off. 
                                  =0 means to use VBIOS default delay which is 0 ( 0ms ).
                                  This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.

ucMinAllowedBL_Level:             Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0. 

ulNbpStateMemclkFreq[4]:          system memory clock frequncey in unit of 10Khz in different NB pstate. 

**********************************************************************************************************************/

// this IntegrateSystemInfoTable is used for Kaveri &amp; Kabini APU</doc>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::sHeader' o='0' t='ATOM_COMMON_TABLE_HEADER'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::ulBootUpEngineClock' o='32' t='ULONG'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::ulDentistVCOFreq' o='64' t='ULONG'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::ulBootUpUMAClock' o='96' t='ULONG'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::sDISPCLK_Voltage' o='128' t='ATOM_CLK_VOLT_CAPABILITY [4]'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::ulBootUpReqDisplayVector' o='384' t='ULONG'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::ulVBIOSMisc' o='416' t='ULONG'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::ulGPUCapInfo' o='448' t='ULONG'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::ulDISP_CLK2Freq' o='480' t='ULONG'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::usRequestedPWMFreqInHz' o='512' t='USHORT'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::ucHtcTmpLmt' o='528' t='UCHAR'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::ucHtcHystLmt' o='536' t='UCHAR'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::ulReserved2' o='544' t='ULONG'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::ulSystemConfig' o='576' t='ULONG'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::ulCPUCapInfo' o='608' t='ULONG'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::ulReserved3' o='640' t='ULONG'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::usGPUReservedSysMemSize' o='672' t='USHORT'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::usExtDispConnInfoOffset' o='688' t='USHORT'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::usPanelRefreshRateRange' o='704' t='USHORT'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::ucMemoryType' o='720' t='UCHAR'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::ucUMAChannelNumber' o='728' t='UCHAR'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::strVBIOSMsg' o='736' t='UCHAR [40]'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::asTdpConfig' o='1056' t='ATOM_TDP_CONFIG'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::ulReserved' o='1088' t='ULONG [19]'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::sAvail_SCLK' o='1696' t='ATOM_AVAILABLE_SCLK_LIST [5]'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::ulGMCRestoreResetTime' o='2016' t='ULONG'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::ulReserved4' o='2048' t='ULONG'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::ulIdleNClk' o='2080' t='ULONG'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::ulDDR_DLL_PowerUpTime' o='2112' t='ULONG'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::ulDDR_PLL_PowerUpTime' o='2144' t='ULONG'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::usPCIEClkSSPercentage' o='2176' t='USHORT'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::usPCIEClkSSType' o='2192' t='USHORT'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::usLvdsSSPercentage' o='2208' t='USHORT'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::usLvdsSSpreadRateIn10Hz' o='2224' t='USHORT'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::usHDMISSPercentage' o='2240' t='USHORT'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::usHDMISSpreadRateIn10Hz' o='2256' t='USHORT'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::usDVISSPercentage' o='2272' t='USHORT'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::usDVISSpreadRateIn10Hz' o='2288' t='USHORT'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::ulGPUReservedSysMemBaseAddrLo' o='2304' t='ULONG'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::ulGPUReservedSysMemBaseAddrHi' o='2336' t='ULONG'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::ulReserved5' o='2368' t='ULONG [3]'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::usMaxLVDSPclkFreqInSingleLink' o='2464' t='USHORT'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::ucLvdsMisc' o='2480' t='UCHAR'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::ucTravisLVDSVolAdjust' o='2488' t='UCHAR'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::ucLVDSPwrOnSeqDIGONtoDE_in4Ms' o='2496' t='UCHAR'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms' o='2504' t='UCHAR'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms' o='2512' t='UCHAR'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::ucLVDSPwrOffSeqDEtoDIGON_in4Ms' o='2520' t='UCHAR'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::ucLVDSOffToOnDelay_in4Ms' o='2528' t='UCHAR'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms' o='2536' t='UCHAR'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms' o='2544' t='UCHAR'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::ucMinAllowedBL_Level' o='2552' t='UCHAR'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::ulLCDBitDepthControlVal' o='2560' t='ULONG'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::ulNbpStateMemclkFreq' o='2592' t='ULONG [4]'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::ulReserved6' o='2720' t='ULONG'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::ulNbpStateNClkFreq' o='2752' t='ULONG [4]'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::usNBPStateVoltage' o='2880' t='USHORT [4]'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::usBootUpNBVoltage' o='2944' t='USHORT'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::usReserved2' o='2960' t='USHORT'/>
<mbr r='_ATOM_INTEGRATED_SYSTEM_INFO_V1_8::sExtDispConnInfo' o='2976' t='ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO'/>
