<def f='src/src/sys/dev/ic/anreg.h' l='508' ll='607'/>
<size>426</size>
<doc f='src/src/sys/dev/ic/anreg.h' l='503'>/*
 * Grrr. The manual says the statistics record is 384 bytes in length,
 * but the card says the record is 404 bytes. There&apos;s some padding left
 * at the end of this structure to account for any discrepancies.
 */</doc>
<mbr r='an_rid_stats::an_spacer' o='0' t='u_int16_t'/>
<mbr r='an_rid_stats::an_rx_overruns' o='16' t='u_int32_t'/>
<mbr r='an_rid_stats::an_rx_plcp_csum_errs' o='48' t='u_int32_t'/>
<mbr r='an_rid_stats::an_rx_plcp_format_errs' o='80' t='u_int32_t'/>
<mbr r='an_rid_stats::an_rx_plcp_len_errs' o='112' t='u_int32_t'/>
<mbr r='an_rid_stats::an_rx_mac_crc_errs' o='144' t='u_int32_t'/>
<mbr r='an_rid_stats::an_rx_mac_crc_ok' o='176' t='u_int32_t'/>
<mbr r='an_rid_stats::an_rx_wep_errs' o='208' t='u_int32_t'/>
<mbr r='an_rid_stats::an_rx_wep_ok' o='240' t='u_int32_t'/>
<mbr r='an_rid_stats::an_retry_long' o='272' t='u_int32_t'/>
<mbr r='an_rid_stats::an_retry_short' o='304' t='u_int32_t'/>
<mbr r='an_rid_stats::an_retry_max' o='336' t='u_int32_t'/>
<mbr r='an_rid_stats::an_no_ack' o='368' t='u_int32_t'/>
<mbr r='an_rid_stats::an_no_cts' o='400' t='u_int32_t'/>
<mbr r='an_rid_stats::an_rx_ack_ok' o='432' t='u_int32_t'/>
<mbr r='an_rid_stats::an_rx_cts_ok' o='464' t='u_int32_t'/>
<mbr r='an_rid_stats::an_tx_ack_ok' o='496' t='u_int32_t'/>
<mbr r='an_rid_stats::an_tx_rts_ok' o='528' t='u_int32_t'/>
<mbr r='an_rid_stats::an_tx_cts_ok' o='560' t='u_int32_t'/>
<mbr r='an_rid_stats::an_tx_lmac_mcasts' o='592' t='u_int32_t'/>
<mbr r='an_rid_stats::an_tx_lmac_bcasts' o='624' t='u_int32_t'/>
<mbr r='an_rid_stats::an_tx_lmac_ucast_frags' o='656' t='u_int32_t'/>
<mbr r='an_rid_stats::an_tx_lmac_ucasts' o='688' t='u_int32_t'/>
<mbr r='an_rid_stats::an_tx_beacons' o='720' t='u_int32_t'/>
<mbr r='an_rid_stats::an_rx_beacons' o='752' t='u_int32_t'/>
<mbr r='an_rid_stats::an_tx_single_cols' o='784' t='u_int32_t'/>
<mbr r='an_rid_stats::an_tx_multi_cols' o='816' t='u_int32_t'/>
<mbr r='an_rid_stats::an_tx_defers_no' o='848' t='u_int32_t'/>
<mbr r='an_rid_stats::an_tx_defers_prot' o='880' t='u_int32_t'/>
<mbr r='an_rid_stats::an_tx_defers_energy' o='912' t='u_int32_t'/>
<mbr r='an_rid_stats::an_rx_dups' o='944' t='u_int32_t'/>
<mbr r='an_rid_stats::an_rx_partial' o='976' t='u_int32_t'/>
<mbr r='an_rid_stats::an_tx_too_old' o='1008' t='u_int32_t'/>
<mbr r='an_rid_stats::an_rx_too_old' o='1040' t='u_int32_t'/>
<mbr r='an_rid_stats::an_lostsync_max_retries' o='1072' t='u_int32_t'/>
<mbr r='an_rid_stats::an_lostsync_missed_beacons' o='1104' t='u_int32_t'/>
<mbr r='an_rid_stats::an_lostsync_arl_exceeded' o='1136' t='u_int32_t'/>
<mbr r='an_rid_stats::an_lostsync_deauthed' o='1168' t='u_int32_t'/>
<mbr r='an_rid_stats::an_lostsync_disassociated' o='1200' t='u_int32_t'/>
<mbr r='an_rid_stats::an_lostsync_tsf_timing' o='1232' t='u_int32_t'/>
<mbr r='an_rid_stats::an_tx_host_mcasts' o='1264' t='u_int32_t'/>
<mbr r='an_rid_stats::an_tx_host_bcasts' o='1296' t='u_int32_t'/>
<mbr r='an_rid_stats::an_tx_host_ucasts' o='1328' t='u_int32_t'/>
<mbr r='an_rid_stats::an_tx_host_failed' o='1360' t='u_int32_t'/>
<mbr r='an_rid_stats::an_rx_host_mcasts' o='1392' t='u_int32_t'/>
<mbr r='an_rid_stats::an_rx_host_bcasts' o='1424' t='u_int32_t'/>
<mbr r='an_rid_stats::an_rx_host_ucasts' o='1456' t='u_int32_t'/>
<mbr r='an_rid_stats::an_rx_host_discarded' o='1488' t='u_int32_t'/>
<mbr r='an_rid_stats::an_tx_hmac_mcasts' o='1520' t='u_int32_t'/>
<mbr r='an_rid_stats::an_tx_hmac_bcasts' o='1552' t='u_int32_t'/>
<mbr r='an_rid_stats::an_tx_hmac_ucasts' o='1584' t='u_int32_t'/>
<mbr r='an_rid_stats::an_tx_hmac_failed' o='1616' t='u_int32_t'/>
<mbr r='an_rid_stats::an_rx_hmac_mcasts' o='1648' t='u_int32_t'/>
<mbr r='an_rid_stats::an_rx_hmac_bcasts' o='1680' t='u_int32_t'/>
<mbr r='an_rid_stats::an_rx_hmac_ucasts' o='1712' t='u_int32_t'/>
<mbr r='an_rid_stats::an_rx_hmac_discarded' o='1744' t='u_int32_t'/>
<mbr r='an_rid_stats::an_tx_hmac_accepted' o='1776' t='u_int32_t'/>
<mbr r='an_rid_stats::an_ssid_mismatches' o='1808' t='u_int32_t'/>
<mbr r='an_rid_stats::an_ap_mismatches' o='1840' t='u_int32_t'/>
<mbr r='an_rid_stats::an_rates_mismatches' o='1872' t='u_int32_t'/>
<mbr r='an_rid_stats::an_auth_rejects' o='1904' t='u_int32_t'/>
<mbr r='an_rid_stats::an_auth_timeouts' o='1936' t='u_int32_t'/>
<mbr r='an_rid_stats::an_assoc_rejects' o='1968' t='u_int32_t'/>
<mbr r='an_rid_stats::an_assoc_timeouts' o='2000' t='u_int32_t'/>
<mbr r='an_rid_stats::an_reason_outside_table' o='2032' t='u_int32_t'/>
<mbr r='an_rid_stats::an_reason1' o='2064' t='u_int32_t'/>
<mbr r='an_rid_stats::an_reason2' o='2096' t='u_int32_t'/>
<mbr r='an_rid_stats::an_reason3' o='2128' t='u_int32_t'/>
<mbr r='an_rid_stats::an_reason4' o='2160' t='u_int32_t'/>
<mbr r='an_rid_stats::an_reason5' o='2192' t='u_int32_t'/>
<mbr r='an_rid_stats::an_reason6' o='2224' t='u_int32_t'/>
<mbr r='an_rid_stats::an_reason7' o='2256' t='u_int32_t'/>
<mbr r='an_rid_stats::an_reason8' o='2288' t='u_int32_t'/>
<mbr r='an_rid_stats::an_reason9' o='2320' t='u_int32_t'/>
<mbr r='an_rid_stats::an_reason10' o='2352' t='u_int32_t'/>
<mbr r='an_rid_stats::an_reason11' o='2384' t='u_int32_t'/>
<mbr r='an_rid_stats::an_reason12' o='2416' t='u_int32_t'/>
<mbr r='an_rid_stats::an_reason13' o='2448' t='u_int32_t'/>
<mbr r='an_rid_stats::an_reason14' o='2480' t='u_int32_t'/>
<mbr r='an_rid_stats::an_reason15' o='2512' t='u_int32_t'/>
<mbr r='an_rid_stats::an_reason16' o='2544' t='u_int32_t'/>
<mbr r='an_rid_stats::an_reason17' o='2576' t='u_int32_t'/>
<mbr r='an_rid_stats::an_reason18' o='2608' t='u_int32_t'/>
<mbr r='an_rid_stats::an_reason19' o='2640' t='u_int32_t'/>
<mbr r='an_rid_stats::an_rx_mgmt_pkts' o='2672' t='u_int32_t'/>
<mbr r='an_rid_stats::an_tx_mgmt_pkts' o='2704' t='u_int32_t'/>
<mbr r='an_rid_stats::an_rx_refresh_pkts' o='2736' t='u_int32_t'/>
<mbr r='an_rid_stats::an_tx_refresh_pkts' o='2768' t='u_int32_t'/>
<mbr r='an_rid_stats::an_rx_poll_pkts' o='2800' t='u_int32_t'/>
<mbr r='an_rid_stats::an_tx_poll_pkts' o='2832' t='u_int32_t'/>
<mbr r='an_rid_stats::an_host_retries' o='2864' t='u_int32_t'/>
<mbr r='an_rid_stats::an_lostsync_hostreq' o='2896' t='u_int32_t'/>
<mbr r='an_rid_stats::an_host_tx_bytes' o='2928' t='u_int32_t'/>
<mbr r='an_rid_stats::an_host_rx_bytes' o='2960' t='u_int32_t'/>
<mbr r='an_rid_stats::an_uptime_usecs' o='2992' t='u_int32_t'/>
<mbr r='an_rid_stats::an_uptime_secs' o='3024' t='u_int32_t'/>
<mbr r='an_rid_stats::an_lostsync_better_ap' o='3056' t='u_int32_t'/>
<mbr r='an_rid_stats::an_rsvd' o='3088' t='u_int32_t [10]'/>
