<def f='src/src/sys/external/bsd/drm2/dist/drm/i915/i915_drv.h' l='710' ll='748'/>
<size>392</size>
<doc f='src/src/sys/external/bsd/drm2/dist/drm/i915/i915_drv.h' l='703'>/* The Graphics Translation Table is the way in which GEN hardware translates a
 * Graphics Virtual Address into a Physical Address. In addition to the normal
 * collateral associated with any va-&gt;pa translations GEN hardware also has a
 * portion of the GTT which can be mapped by the CPU and remain both coherent
 * and correct (in cases like swizzling). That region is referred to as GMADR in
 * the spec.
 */</doc>
<mbr r='i915_gtt::base' o='0' t='struct i915_address_space'/>
<mbr r='i915_gtt::stolen_size' o='2432' t='size_t'/>
<mbr r='i915_gtt::mappable_end' o='2496' t='unsigned long'/>
<mbr r='i915_gtt::mappable' o='2560' t='struct io_mapping *'/>
<mbr r='i915_gtt::mappable_base' o='2624' t='phys_addr_t'/>
<mbr r='i915_gtt::bst' o='2688' t='bus_space_tag_t'/>
<mbr r='i915_gtt::bsh' o='2752' t='bus_space_handle_t'/>
<mbr r='i915_gtt::size' o='2816' t='bus_size_t'/>
<mbr r='i915_gtt::max_paddr' o='2880' t='__uint64_t'/>
<mbr r='i915_gtt::pgfl' o='2944' t='int'/>
<mbr r='i915_gtt::do_idle_maps' o='2976' t='_Bool'/>
<mbr r='i915_gtt::mtrr' o='3008' t='int'/>
<mbr r='i915_gtt::gtt_probe' o='3072' t='int (*)(struct drm_device *, size_t *, size_t *, phys_addr_t *, unsigned long *)'/>
