<dec f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_drv.h' l='405' type='unsigned long'/>
<offset>13440</offset>
<doc f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_drv.h' l='402'>/* Display surface base address adjustement for pageflips. Note that on
	 * gen4+ this only adjusts up to a tile, offsets within a tile are
	 * handled in the hw itself (with the TILEOFF register). */</doc>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c' l='2241' u='w' c='i9xx_update_primary_plane'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c' l='2245' u='r' c='i9xx_update_primary_plane'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c' l='2247' u='w' c='i9xx_update_primary_plane'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c' l='2256' u='r' c='i9xx_update_primary_plane'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c' l='2337' u='w' c='ironlake_update_primary_plane'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c' l='2341' u='r' c='ironlake_update_primary_plane'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c' l='2348' u='r' c='ironlake_update_primary_plane'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c' l='8705' u='r' c='intel_gen2_queue_flip'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c' l='8747' u='r' c='intel_gen3_queue_flip'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c' l='8788' u='r' c='intel_gen4_queue_flip'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c' l='8832' u='r' c='intel_gen6_queue_flip'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c' l='8935' u='r' c='intel_gen7_queue_flip'/>
