<def f='src/src/sys/dev/isa/isadmavar.h' l='48' ll='64'/>
<size>264</size>
<doc f='src/src/sys/dev/isa/isadmavar.h' l='43'>/*
 * ISA DMA state.  This structure is provided by the ISA chipset
 * DMA entry points to the generic back-end functions that actually
 * frob the controller.
 */</doc>
<mbr r='isa_dma_state::ids_dev' o='0' t='device_t'/>
<mbr r='isa_dma_state::ids_bst' o='64' t='bus_space_tag_t'/>
<mbr r='isa_dma_state::ids_dma1h' o='128' t='bus_space_handle_t'/>
<mbr r='isa_dma_state::ids_dma2h' o='192' t='bus_space_handle_t'/>
<mbr r='isa_dma_state::ids_dmapgh' o='256' t='bus_space_handle_t'/>
<mbr r='isa_dma_state::ids_dmat' o='320' t='bus_dma_tag_t'/>
<mbr r='isa_dma_state::ids_dmamaps' o='384' t='bus_dmamap_t [8]'/>
<mbr r='isa_dma_state::ids_dmalength' o='896' t='bus_size_t [8]'/>
<mbr r='isa_dma_state::ids_maxsize' o='1408' t='bus_size_t [8]'/>
<mbr r='isa_dma_state::ids_drqmap' o='1920' t='int'/>
<mbr r='isa_dma_state::ids_dmareads' o='1952' t='int'/>
<mbr r='isa_dma_state::ids_dmafinished' o='1984' t='int'/>
<mbr r='isa_dma_state::ids_masked' o='2016' t='int'/>
<mbr r='isa_dma_state::ids_frozen' o='2048' t='int'/>
<mbr r='isa_dma_state::ids_initialized' o='2080' t='int'/>
