<def f='src/src/sys/dev/ic/mlxreg.h' l='489' ll='510'/>
<size>88</size>
<doc f='src/src/sys/dev/ic/mlxreg.h' l='481'>/*
 * Bitfields:
 *
 * 0-3	dcdb_target	SCSI target
 * 4-7	dcdb_target	SCSI channel
 * 0-3	dcdb_length	CDB length
 * 4-7	dcdb_length	high 4 bits of `datasize&apos;
 */</doc>
<mbr r='mlx_dcdb::dcdb_target' o='0' t='u_int8_t'/>
<mbr r='mlx_dcdb::dcdb_flags' o='8' t='u_int8_t'/>
<mbr r='mlx_dcdb::dcdb_datasize' o='16' t='u_int16_t'/>
<mbr r='mlx_dcdb::dcdb_physaddr' o='32' t='u_int32_t'/>
<mbr r='mlx_dcdb::dcdb_length' o='64' t='u_int8_t'/>
<mbr r='mlx_dcdb::dcdb_sense_length' o='72' t='u_int8_t'/>
<mbr r='mlx_dcdb::dcdb_cdb' o='80' t='u_int8_t [12]'/>
<mbr r='mlx_dcdb::dcdb_sense' o='176' t='u_int8_t [64]'/>
<mbr r='mlx_dcdb::dcdb_status' o='688' t='u_int8_t'/>
<mbr r='mlx_dcdb::res1' o='696' t='u_int8_t'/>
