<def f='src/src/sys/dev/pci/mlyreg.h' l='977' ll='984'/>
<size>8</size>
<doc f='src/src/sys/dev/pci/mlyreg.h' l='972'>/*
 * 23.6.2 MDACIOCTL_XLATEPHYSDEVTORAIDDEV
 *
 * XXX documentation suggests this format will change
 */</doc>
<mbr r='mly_ioctl_param_xlatephysdevtoraiddev::raid_device' o='0' t='u_int16_t'/>
<mbr r='mly_ioctl_param_xlatephysdevtoraiddev::res1' o='16' t='u_int8_t [2]'/>
<mbr r='mly_ioctl_param_xlatephysdevtoraiddev::controller' o='32' t='u_int8_t'/>
<mbr r='mly_ioctl_param_xlatephysdevtoraiddev::channel' o='40' t='u_int8_t'/>
<mbr r='mly_ioctl_param_xlatephysdevtoraiddev::target' o='48' t='u_int8_t'/>
<mbr r='mly_ioctl_param_xlatephysdevtoraiddev::lun' o='56' t='u_int8_t'/>
