<def f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/dispnv04/disp.h' l='18' ll='65'/>
<size>1344</size>
<mbr r='nv04_crtc_reg::MiscOutReg' o='0' t='unsigned char'/>
<mbr r='nv04_crtc_reg::CRTC' o='8' t='__uint8_t [160]'/>
<mbr r='nv04_crtc_reg::CR58' o='1288' t='__uint8_t [16]'/>
<mbr r='nv04_crtc_reg::Sequencer' o='1416' t='__uint8_t [5]'/>
<mbr r='nv04_crtc_reg::Graphics' o='1456' t='__uint8_t [9]'/>
<mbr r='nv04_crtc_reg::Attribute' o='1528' t='__uint8_t [21]'/>
<mbr r='nv04_crtc_reg::DAC' o='1696' t='unsigned char [768]'/>
<mbr r='nv04_crtc_reg::fb_start' o='7840' t='__uint32_t'/>
<mbr r='nv04_crtc_reg::crtc_cfg' o='7872' t='__uint32_t'/>
<mbr r='nv04_crtc_reg::cursor_cfg' o='7904' t='__uint32_t'/>
<mbr r='nv04_crtc_reg::gpio_ext' o='7936' t='__uint32_t'/>
<mbr r='nv04_crtc_reg::crtc_830' o='7968' t='__uint32_t'/>
<mbr r='nv04_crtc_reg::crtc_834' o='8000' t='__uint32_t'/>
<mbr r='nv04_crtc_reg::crtc_850' o='8032' t='__uint32_t'/>
<mbr r='nv04_crtc_reg::crtc_eng_ctrl' o='8064' t='__uint32_t'/>
<mbr r='nv04_crtc_reg::nv10_cursync' o='8096' t='__uint32_t'/>
<mbr r='nv04_crtc_reg::pllvals' o='8128' t='struct nouveau_pll_vals'/>
<mbr r='nv04_crtc_reg::ramdac_gen_ctrl' o='8224' t='__uint32_t'/>
<mbr r='nv04_crtc_reg::ramdac_630' o='8256' t='__uint32_t'/>
<mbr r='nv04_crtc_reg::ramdac_634' o='8288' t='__uint32_t'/>
<mbr r='nv04_crtc_reg::tv_setup' o='8320' t='__uint32_t'/>
<mbr r='nv04_crtc_reg::tv_vtotal' o='8352' t='__uint32_t'/>
<mbr r='nv04_crtc_reg::tv_vskew' o='8384' t='__uint32_t'/>
<mbr r='nv04_crtc_reg::tv_vsync_delay' o='8416' t='__uint32_t'/>
<mbr r='nv04_crtc_reg::tv_htotal' o='8448' t='__uint32_t'/>
<mbr r='nv04_crtc_reg::tv_hskew' o='8480' t='__uint32_t'/>
<mbr r='nv04_crtc_reg::tv_hsync_delay' o='8512' t='__uint32_t'/>
<mbr r='nv04_crtc_reg::tv_hsync_delay2' o='8544' t='__uint32_t'/>
<mbr r='nv04_crtc_reg::fp_horiz_regs' o='8576' t='__uint32_t [7]'/>
<mbr r='nv04_crtc_reg::fp_vert_regs' o='8800' t='__uint32_t [7]'/>
<mbr r='nv04_crtc_reg::dither' o='9024' t='__uint32_t'/>
<mbr r='nv04_crtc_reg::fp_control' o='9056' t='__uint32_t'/>
<mbr r='nv04_crtc_reg::dither_regs' o='9088' t='__uint32_t [6]'/>
<mbr r='nv04_crtc_reg::fp_debug_0' o='9280' t='__uint32_t'/>
<mbr r='nv04_crtc_reg::fp_debug_1' o='9312' t='__uint32_t'/>
<mbr r='nv04_crtc_reg::fp_debug_2' o='9344' t='__uint32_t'/>
<mbr r='nv04_crtc_reg::fp_margin_color' o='9376' t='__uint32_t'/>
<mbr r='nv04_crtc_reg::ramdac_8c0' o='9408' t='__uint32_t'/>
<mbr r='nv04_crtc_reg::ramdac_a20' o='9440' t='__uint32_t'/>
<mbr r='nv04_crtc_reg::ramdac_a24' o='9472' t='__uint32_t'/>
<mbr r='nv04_crtc_reg::ramdac_a34' o='9504' t='__uint32_t'/>
<mbr r='nv04_crtc_reg::ctv_regs' o='9536' t='__uint32_t [38]'/>
